1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK10 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK12 26 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 37 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK18 39 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 40 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK20 42 43 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 46 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 49 50 // Test target codegen - host bc file has to be created first. 51 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK25 53 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK26 55 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK27 57 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK28 59 60 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 62 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 64 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 66 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 68 69 // expected-no-diagnostics 70 #ifndef HEADER 71 #define HEADER 72 73 74 75 76 // We have 8 target regions, but only 6 that actually will generate offloading 77 // code and have mapped arguments, and only 4 have all-constant map sizes. 78 79 80 81 // Check target registration is registered as a Ctor. 82 83 84 template<typename tx, typename ty> 85 struct TT{ 86 tx X; 87 ty Y; 88 }; 89 90 int global; 91 92 int foo(int n) { 93 int a = 0; 94 short aa = 0; 95 float b[10]; 96 float bn[n]; 97 double c[5][10]; 98 double cn[5][n]; 99 TT<long long, char> d; 100 101 #pragma omp target teams num_teams(a) thread_limit(a) firstprivate(aa) nowait 102 { 103 } 104 105 #pragma omp target teams if(target: 0) 106 { 107 a += 1; 108 } 109 110 111 #pragma omp target teams if(target: 1) 112 { 113 aa += 1; 114 } 115 116 117 118 #pragma omp target teams if(target: n>10) 119 { 120 a += 1; 121 aa += 1; 122 } 123 124 // We capture 3 VLA sizes in this target region 125 126 127 128 129 130 // The names below are not necessarily consistent with the names used for the 131 // addresses above as some are repeated. 132 133 134 135 136 137 138 139 140 141 142 #pragma omp target teams if(target: n>20) 143 { 144 a += 1; 145 b[2] += 1.0; 146 bn[3] += 1.0; 147 c[1][2] += 1.0; 148 cn[1][3] += 1.0; 149 d.X += 1; 150 d.Y += 1; 151 } 152 153 const int nn = 0; 154 #pragma omp target teams shared(nn) 155 #pragma omp parallel firstprivate(nn) 156 (void)nn; 157 #pragma omp target teams firstprivate(nn) 158 #pragma omp parallel shared(nn) 159 (void)nn; 160 return a; 161 } 162 163 // Check that the offloading functions are emitted and that the arguments are 164 // correct and loaded correctly for the target regions in foo(). 165 166 167 168 // Create stack storage and store argument in there. 169 170 // Create stack storage and store argument in there. 171 172 // Create stack storage and store argument in there. 173 174 // Create local storage for each capture. 175 176 177 178 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 179 180 181 void bazzzz(int n, int f[n]) { 182 #pragma omp target teams private(f) 183 ; 184 } 185 186 template<typename tx> 187 tx ftemplate(int n) { 188 tx a = 0; 189 short aa = 0; 190 tx b[10]; 191 192 #pragma omp target teams if(target: n>40) 193 { 194 a += 1; 195 aa += 1; 196 b[2] += 1; 197 } 198 199 return a; 200 } 201 202 static 203 int fstatic(int n) { 204 int a = 0; 205 short aa = 0; 206 char aaa = 0; 207 int b[10]; 208 209 #pragma omp target teams if(target: n>50) 210 { 211 a += 1; 212 aa += 1; 213 aaa += 1; 214 b[2] += 1; 215 } 216 217 return a; 218 } 219 220 struct S1 { 221 double a; 222 223 int r1(int n){ 224 int b = n+1; 225 short int c[2][n]; 226 227 #pragma omp target teams if(target: n>60) 228 { 229 this->a = (double)b + 1.5; 230 c[1][1] = ++a; 231 } 232 233 return c[1][1] + (int)b; 234 } 235 }; 236 237 int bar(int n){ 238 int a = 0; 239 240 a += foo(n); 241 242 S1 S; 243 a += S.r1(n); 244 245 a += fstatic(n); 246 247 a += ftemplate<int>(n); 248 249 return a; 250 } 251 252 253 254 // We capture 2 VLA sizes in this target region 255 256 257 // The names below are not necessarily consistent with the names used for the 258 // addresses above as some are repeated. 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 // Check that the offloading functions are emitted and that the arguments are 280 // correct and loaded correctly for the target regions of the callees of bar(). 281 282 // Create local storage for each capture. 283 // Store captures in the context. 284 285 286 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 287 288 289 // Create local storage for each capture. 290 // Store captures in the context. 291 292 293 294 295 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 296 297 // Create local storage for each capture. 298 // Store captures in the context. 299 300 301 302 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 303 304 #endif 305 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 306 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 307 // CHECK1-NEXT: entry: 308 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 309 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 310 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 311 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 312 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 313 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 315 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 316 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 317 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 325 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 326 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 329 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 330 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 331 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 336 // CHECK1-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 337 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 338 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 339 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 340 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 341 // CHECK1-NEXT: [[NN:%.*]] = alloca i32, align 4 342 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 343 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 344 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 345 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 346 // CHECK1-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 347 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 348 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 349 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 350 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 351 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 352 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 353 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 354 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 355 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 356 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 357 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 358 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 359 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 360 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 361 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 362 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 363 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 364 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 365 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 366 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 367 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 368 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 369 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 370 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 371 // CHECK1-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 372 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 373 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 374 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 375 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 376 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 377 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 378 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 379 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 380 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 381 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 382 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 383 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 384 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 385 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 386 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 387 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 388 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 389 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 390 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 391 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 392 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 393 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 394 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 395 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 396 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 397 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 398 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 399 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 400 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 401 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 402 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 403 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 404 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8 405 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 406 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 407 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 408 // CHECK1-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 409 // CHECK1-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 410 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 411 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 412 // CHECK1-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 413 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 414 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 415 // CHECK1-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 416 // CHECK1-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 417 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 418 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 419 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 420 // CHECK1-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 421 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 422 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 423 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 424 // CHECK1-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 425 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 426 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 427 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 428 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 429 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 430 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 431 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 432 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 433 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 434 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 435 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 436 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 437 // CHECK1-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 438 // CHECK1-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 439 // CHECK1-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 440 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 441 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 442 // CHECK1-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 443 // CHECK1-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 444 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 445 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 446 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 447 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 448 // CHECK1-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 449 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 450 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 451 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 452 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 453 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 454 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 455 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 456 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8 457 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 458 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 459 // CHECK1-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 460 // CHECK1-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 461 // CHECK1-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 462 // CHECK1: omp_offload.failed: 463 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 464 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 465 // CHECK1: omp_offload.cont: 466 // CHECK1-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 467 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 468 // CHECK1-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 469 // CHECK1-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 470 // CHECK1-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 471 // CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 472 // CHECK1-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 473 // CHECK1-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 474 // CHECK1-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 475 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 476 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 477 // CHECK1: omp_if.then: 478 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 479 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 480 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 481 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 482 // CHECK1-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 483 // CHECK1-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 484 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 485 // CHECK1-NEXT: store i8* null, i8** [[TMP79]], align 8 486 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 487 // CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 488 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 489 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 490 // CHECK1-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 491 // CHECK1-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 492 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 493 // CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8 494 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 495 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 496 // CHECK1-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 497 // CHECK1-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 498 // CHECK1-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 499 // CHECK1: omp_offload.failed19: 500 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 501 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT20]] 502 // CHECK1: omp_offload.cont20: 503 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 504 // CHECK1: omp_if.else: 505 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 506 // CHECK1-NEXT: br label [[OMP_IF_END]] 507 // CHECK1: omp_if.end: 508 // CHECK1-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 509 // CHECK1-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* 510 // CHECK1-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 511 // CHECK1-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 512 // CHECK1-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 513 // CHECK1-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 514 // CHECK1-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] 515 // CHECK1: omp_if.then24: 516 // CHECK1-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 517 // CHECK1-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 518 // CHECK1-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 519 // CHECK1-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 520 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) 521 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 522 // CHECK1-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* 523 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP97]], align 8 524 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 525 // CHECK1-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* 526 // CHECK1-NEXT: store i64 [[TMP90]], i64* [[TMP99]], align 8 527 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 528 // CHECK1-NEXT: store i8* null, i8** [[TMP100]], align 8 529 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 530 // CHECK1-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 531 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 532 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 533 // CHECK1-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 534 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 535 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 536 // CHECK1-NEXT: store i8* null, i8** [[TMP105]], align 8 537 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 538 // CHECK1-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* 539 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP107]], align 8 540 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 541 // CHECK1-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64* 542 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP109]], align 8 543 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 544 // CHECK1-NEXT: store i8* null, i8** [[TMP110]], align 8 545 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 546 // CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 547 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP112]], align 8 548 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 549 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 550 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 551 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 552 // CHECK1-NEXT: store i64 [[TMP92]], i64* [[TMP115]], align 8 553 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 554 // CHECK1-NEXT: store i8* null, i8** [[TMP116]], align 8 555 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 556 // CHECK1-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 557 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8 558 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 559 // CHECK1-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 560 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 561 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 562 // CHECK1-NEXT: store i8* null, i8** [[TMP121]], align 8 563 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 564 // CHECK1-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64* 565 // CHECK1-NEXT: store i64 5, i64* [[TMP123]], align 8 566 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 567 // CHECK1-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* 568 // CHECK1-NEXT: store i64 5, i64* [[TMP125]], align 8 569 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 570 // CHECK1-NEXT: store i8* null, i8** [[TMP126]], align 8 571 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 572 // CHECK1-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 573 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 574 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 575 // CHECK1-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64* 576 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP130]], align 8 577 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 578 // CHECK1-NEXT: store i8* null, i8** [[TMP131]], align 8 579 // CHECK1-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 580 // CHECK1-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 581 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP133]], align 8 582 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 583 // CHECK1-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 584 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP135]], align 8 585 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 586 // CHECK1-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 8 587 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 588 // CHECK1-NEXT: store i8* null, i8** [[TMP137]], align 8 589 // CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 590 // CHECK1-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 591 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8 592 // CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 593 // CHECK1-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 594 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8 595 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 596 // CHECK1-NEXT: store i8* null, i8** [[TMP142]], align 8 597 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 598 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 599 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 600 // CHECK1-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 601 // CHECK1-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 602 // CHECK1-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] 603 // CHECK1: omp_offload.failed28: 604 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 605 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT29]] 606 // CHECK1: omp_offload.cont29: 607 // CHECK1-NEXT: br label [[OMP_IF_END31:%.*]] 608 // CHECK1: omp_if.else30: 609 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 610 // CHECK1-NEXT: br label [[OMP_IF_END31]] 611 // CHECK1: omp_if.end31: 612 // CHECK1-NEXT: store i32 0, i32* [[NN]], align 4 613 // CHECK1-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 614 // CHECK1-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 615 // CHECK1-NEXT: store i32 [[TMP148]], i32* [[CONV32]], align 4 616 // CHECK1-NEXT: [[TMP149:%.*]] = load i64, i64* [[NN_CASTED]], align 8 617 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 618 // CHECK1-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* 619 // CHECK1-NEXT: store i64 [[TMP149]], i64* [[TMP151]], align 8 620 // CHECK1-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 621 // CHECK1-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* 622 // CHECK1-NEXT: store i64 [[TMP149]], i64* [[TMP153]], align 8 623 // CHECK1-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 624 // CHECK1-NEXT: store i8* null, i8** [[TMP154]], align 8 625 // CHECK1-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 626 // CHECK1-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 627 // CHECK1-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 628 // CHECK1-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 629 // CHECK1-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 630 // CHECK1: omp_offload.failed36: 631 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP149]]) #[[ATTR3]] 632 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT37]] 633 // CHECK1: omp_offload.cont37: 634 // CHECK1-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 635 // CHECK1-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* 636 // CHECK1-NEXT: store i32 [[TMP159]], i32* [[CONV39]], align 4 637 // CHECK1-NEXT: [[TMP160:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 638 // CHECK1-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 639 // CHECK1-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i64* 640 // CHECK1-NEXT: store i64 [[TMP160]], i64* [[TMP162]], align 8 641 // CHECK1-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 642 // CHECK1-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i64* 643 // CHECK1-NEXT: store i64 [[TMP160]], i64* [[TMP164]], align 8 644 // CHECK1-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 645 // CHECK1-NEXT: store i8* null, i8** [[TMP165]], align 8 646 // CHECK1-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 647 // CHECK1-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 648 // CHECK1-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 649 // CHECK1-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 650 // CHECK1-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] 651 // CHECK1: omp_offload.failed43: 652 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP160]]) #[[ATTR3]] 653 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT44]] 654 // CHECK1: omp_offload.cont44: 655 // CHECK1-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 656 // CHECK1-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 657 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 658 // CHECK1-NEXT: ret i32 [[TMP170]] 659 // 660 // 661 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 662 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 663 // CHECK1-NEXT: entry: 664 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 665 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 666 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 667 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 668 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 669 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 670 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 671 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 672 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 673 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 674 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 675 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 676 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 677 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 678 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 679 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 680 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 681 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 682 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 683 // CHECK1-NEXT: ret void 684 // 685 // 686 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 687 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 688 // CHECK1-NEXT: entry: 689 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 690 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 691 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 692 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 693 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 694 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 695 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 696 // CHECK1-NEXT: ret void 697 // 698 // 699 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 700 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 701 // CHECK1-NEXT: entry: 702 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 703 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 704 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 705 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 706 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 707 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 708 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 709 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 710 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 711 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 712 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 713 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 714 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 715 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 716 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 717 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 718 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 719 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 720 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 721 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 722 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 723 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 724 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 725 // CHECK1-NEXT: ret void 726 // 727 // 728 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 729 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 730 // CHECK1-NEXT: entry: 731 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 732 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 733 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 734 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 735 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 736 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 737 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 738 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 739 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 740 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 741 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 742 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 743 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 744 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 745 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 746 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 747 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 748 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 749 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 750 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 751 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 752 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 753 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 754 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 755 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 756 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 757 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 758 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 759 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 760 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 761 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 762 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 763 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 764 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 765 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 766 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 767 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 768 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 769 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 770 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 771 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 772 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 773 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 774 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 775 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 776 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 777 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 778 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 779 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 780 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 781 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 782 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 783 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 784 // CHECK1-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 785 // CHECK1-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 786 // CHECK1-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 787 // CHECK1: omp_offload.failed.i: 788 // CHECK1-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 789 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 790 // CHECK1-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 791 // CHECK1-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 792 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 793 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 794 // CHECK1-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24 795 // CHECK1-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24 796 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 797 // CHECK1-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 798 // CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24 799 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24 800 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 801 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 802 // CHECK1: .omp_outlined..1.exit: 803 // CHECK1-NEXT: ret i32 0 804 // 805 // 806 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 807 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { 808 // CHECK1-NEXT: entry: 809 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 810 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 811 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 812 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 813 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 814 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 815 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 816 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 817 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 818 // CHECK1-NEXT: ret void 819 // 820 // 821 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 822 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 823 // CHECK1-NEXT: entry: 824 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 825 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 826 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 827 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 828 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 829 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 830 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 831 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 832 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 833 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 834 // CHECK1-NEXT: ret void 835 // 836 // 837 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 838 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 839 // CHECK1-NEXT: entry: 840 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 841 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 842 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 843 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 844 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 845 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 846 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 847 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 848 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 849 // CHECK1-NEXT: ret void 850 // 851 // 852 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 853 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 854 // CHECK1-NEXT: entry: 855 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 856 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 857 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 858 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 859 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 860 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 861 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 862 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 863 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 864 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 865 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 866 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 867 // CHECK1-NEXT: ret void 868 // 869 // 870 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 871 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 872 // CHECK1-NEXT: entry: 873 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 874 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 875 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 876 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 877 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 878 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 879 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 880 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 881 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 882 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 883 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 884 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 885 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 886 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 887 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 888 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 889 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 890 // CHECK1-NEXT: ret void 891 // 892 // 893 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 894 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 895 // CHECK1-NEXT: entry: 896 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 897 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 898 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 899 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 900 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 901 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 902 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 903 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 904 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 905 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 906 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 907 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 908 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 909 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 910 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 911 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 912 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 913 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 914 // CHECK1-NEXT: ret void 915 // 916 // 917 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 918 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 919 // CHECK1-NEXT: entry: 920 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 921 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 922 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 923 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 924 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 925 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 926 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 927 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 928 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 929 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 930 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 931 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 932 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 933 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 934 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 935 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 936 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 937 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 938 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 939 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 940 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 941 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 942 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 943 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 944 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 945 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 946 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 947 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 948 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 949 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 950 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 951 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 952 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 953 // CHECK1-NEXT: ret void 954 // 955 // 956 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 957 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 958 // CHECK1-NEXT: entry: 959 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 960 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 961 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 962 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 963 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 964 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 965 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 966 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 967 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 968 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 969 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 970 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 971 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 972 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 973 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 974 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 975 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 976 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 977 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 978 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 979 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 980 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 981 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 982 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 983 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 984 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 985 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 986 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 987 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 988 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 989 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 990 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 991 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 992 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 993 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 994 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 995 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 996 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 997 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 998 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 999 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1000 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1001 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 1002 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1003 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1004 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 1005 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1006 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 1007 // CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 1008 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 1009 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 1010 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 1011 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 1012 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 1013 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 1014 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 1015 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 1016 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1017 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 1018 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 1019 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 1020 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1021 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 1022 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 1023 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 1024 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 1025 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 1026 // CHECK1-NEXT: ret void 1027 // 1028 // 1029 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 1030 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1031 // CHECK1-NEXT: entry: 1032 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1033 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1034 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1035 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1036 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1037 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1038 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1039 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1040 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1041 // CHECK1-NEXT: ret void 1042 // 1043 // 1044 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 1045 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1046 // CHECK1-NEXT: entry: 1047 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1048 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1049 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1050 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1051 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1052 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1053 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1054 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1055 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1056 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1057 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1058 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1059 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1060 // CHECK1-NEXT: ret void 1061 // 1062 // 1063 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1064 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1065 // CHECK1-NEXT: entry: 1066 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1067 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1068 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1069 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1070 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1071 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1072 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1073 // CHECK1-NEXT: ret void 1074 // 1075 // 1076 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 1077 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1078 // CHECK1-NEXT: entry: 1079 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1080 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1081 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1082 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1083 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1084 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1085 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1086 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1087 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1088 // CHECK1-NEXT: ret void 1089 // 1090 // 1091 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1092 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1093 // CHECK1-NEXT: entry: 1094 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1095 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1096 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1097 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1098 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1099 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1100 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1101 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[CONV]]) 1102 // CHECK1-NEXT: ret void 1103 // 1104 // 1105 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..17 1106 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 1107 // CHECK1-NEXT: entry: 1108 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1109 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1110 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 1111 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1112 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1113 // CHECK1-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 1114 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 1115 // CHECK1-NEXT: ret void 1116 // 1117 // 1118 // CHECK1-LABEL: define {{[^@]+}}@_Z6bazzzziPi 1119 // CHECK1-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 1120 // CHECK1-NEXT: entry: 1121 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1122 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 1123 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1124 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1125 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1126 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1127 // CHECK1-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 1128 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1129 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1130 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1131 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 1132 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 1133 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1134 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 1135 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 1136 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1137 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 1138 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1139 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1140 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1141 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 1142 // CHECK1-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1143 // CHECK1: omp_offload.failed: 1144 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 1145 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1146 // CHECK1: omp_offload.cont: 1147 // CHECK1-NEXT: ret void 1148 // 1149 // 1150 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 1151 // CHECK1-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 1152 // CHECK1-NEXT: entry: 1153 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1154 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1155 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1156 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 1157 // CHECK1-NEXT: ret void 1158 // 1159 // 1160 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..20 1161 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 1162 // CHECK1-NEXT: entry: 1163 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1164 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1165 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1166 // CHECK1-NEXT: [[F:%.*]] = alloca i32*, align 8 1167 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1168 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1169 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1170 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1171 // CHECK1-NEXT: ret void 1172 // 1173 // 1174 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1175 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1176 // CHECK1-NEXT: entry: 1177 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1178 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1179 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1180 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1181 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1182 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1183 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1184 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1185 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1186 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1187 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1188 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1189 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1190 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1191 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1192 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1193 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1194 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1195 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1196 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1197 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1198 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1199 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1200 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1201 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1202 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1203 // CHECK1-NEXT: ret i32 [[TMP8]] 1204 // 1205 // 1206 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1207 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1208 // CHECK1-NEXT: entry: 1209 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1210 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1211 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1212 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1213 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1214 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1215 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1216 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1217 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1218 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1219 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1220 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1221 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1222 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1223 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1224 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1225 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1226 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1227 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1228 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1229 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1230 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1231 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1232 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1233 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1234 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1235 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1236 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1237 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1238 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1239 // CHECK1: omp_if.then: 1240 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1241 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1242 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1243 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1244 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i64 40, i1 false) 1245 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1246 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1247 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1248 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1249 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1250 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 1251 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1252 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1253 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1254 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1255 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1256 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1257 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1258 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1259 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1260 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 1261 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1262 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1263 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 1264 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1265 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1266 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 1267 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1268 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 1269 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1270 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1271 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1272 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1273 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1274 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1275 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1276 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 1277 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1278 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1279 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1280 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1281 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1282 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1283 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1284 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1285 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1286 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 1287 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1288 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1289 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1290 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1291 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1292 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1293 // CHECK1: omp_offload.failed: 1294 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1295 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1296 // CHECK1: omp_offload.cont: 1297 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1298 // CHECK1: omp_if.else: 1299 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1300 // CHECK1-NEXT: br label [[OMP_IF_END]] 1301 // CHECK1: omp_if.end: 1302 // CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 1303 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 1304 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1305 // CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1306 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 1307 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 1308 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 1309 // CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1310 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 1311 // CHECK1-NEXT: ret i32 [[ADD4]] 1312 // 1313 // 1314 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1315 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1316 // CHECK1-NEXT: entry: 1317 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1318 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1319 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1320 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1321 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1322 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1323 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1324 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1325 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1326 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1327 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1328 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1329 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1330 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1331 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1332 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1333 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1334 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1335 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1336 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1337 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1338 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1339 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1340 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1341 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1342 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1343 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1344 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1345 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1346 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1347 // CHECK1: omp_if.then: 1348 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1349 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1350 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1351 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1352 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1353 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1354 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1355 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1356 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1357 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1358 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1359 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1360 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1361 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1362 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1363 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1364 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1365 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1366 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1367 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1368 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1369 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1370 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1371 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1372 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1373 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1374 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1375 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1376 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1377 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1378 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1379 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1380 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1381 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1382 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1383 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1384 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1385 // CHECK1: omp_offload.failed: 1386 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 1387 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1388 // CHECK1: omp_offload.cont: 1389 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1390 // CHECK1: omp_if.else: 1391 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 1392 // CHECK1-NEXT: br label [[OMP_IF_END]] 1393 // CHECK1: omp_if.end: 1394 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1395 // CHECK1-NEXT: ret i32 [[TMP31]] 1396 // 1397 // 1398 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1399 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1400 // CHECK1-NEXT: entry: 1401 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1402 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1403 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1404 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1405 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1406 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1407 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1408 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1409 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1410 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1411 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1412 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1413 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1414 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1415 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1416 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1417 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1418 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1419 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1420 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1421 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1422 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1423 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1424 // CHECK1: omp_if.then: 1425 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1426 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1427 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1428 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1429 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1430 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1431 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1432 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1433 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1434 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1435 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1436 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1437 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1438 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1439 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1440 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1441 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1442 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1443 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1444 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1445 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1446 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1447 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1448 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1449 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1450 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1451 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1452 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1453 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1454 // CHECK1: omp_offload.failed: 1455 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1456 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1457 // CHECK1: omp_offload.cont: 1458 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1459 // CHECK1: omp_if.else: 1460 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1461 // CHECK1-NEXT: br label [[OMP_IF_END]] 1462 // CHECK1: omp_if.end: 1463 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1464 // CHECK1-NEXT: ret i32 [[TMP24]] 1465 // 1466 // 1467 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 1468 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1469 // CHECK1-NEXT: entry: 1470 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1471 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1472 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1473 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1474 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1475 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1476 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1477 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1478 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1479 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1480 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1481 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1482 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1483 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1484 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1485 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1486 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1487 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1488 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1489 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1490 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1491 // CHECK1-NEXT: ret void 1492 // 1493 // 1494 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..23 1495 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1496 // CHECK1-NEXT: entry: 1497 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1498 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1499 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1500 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1501 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1502 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1503 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1504 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1505 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1506 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1507 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1508 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1509 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1510 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1511 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1512 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1513 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1514 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1515 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1516 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1517 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 1518 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 1519 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1520 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1521 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1522 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 1523 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 1524 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 1525 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1526 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 1527 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 1528 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1529 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 1530 // CHECK1-NEXT: ret void 1531 // 1532 // 1533 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 1534 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1535 // CHECK1-NEXT: entry: 1536 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1537 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1538 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1539 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1540 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1541 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1542 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1543 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1544 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1545 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1546 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1547 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1548 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1549 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1550 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1551 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1552 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1553 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1554 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1555 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1556 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1557 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1558 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1559 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1560 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1561 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1562 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1563 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1564 // CHECK1-NEXT: ret void 1565 // 1566 // 1567 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..26 1568 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1569 // CHECK1-NEXT: entry: 1570 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1571 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1572 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1573 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1574 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1575 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1576 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1577 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1578 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1579 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1580 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1581 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1582 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1583 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1584 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1585 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1586 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1587 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1588 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1589 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1590 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 1591 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1592 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1593 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 1594 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 1595 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 1596 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 1597 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 1598 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 1599 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1600 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1601 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 1602 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 1603 // CHECK1-NEXT: ret void 1604 // 1605 // 1606 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 1607 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1608 // CHECK1-NEXT: entry: 1609 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1610 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1611 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1612 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1613 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1614 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1615 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1616 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1617 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1618 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1619 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1620 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1621 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1622 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1623 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1624 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1625 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1626 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1627 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1628 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1629 // CHECK1-NEXT: ret void 1630 // 1631 // 1632 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..29 1633 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1634 // CHECK1-NEXT: entry: 1635 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1636 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1637 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1638 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1639 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1640 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1641 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1642 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1643 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1644 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1645 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1646 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1647 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1648 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1649 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1650 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1651 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1652 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1653 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1654 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1655 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1656 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1657 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1658 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 1659 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 1660 // CHECK1-NEXT: ret void 1661 // 1662 // 1663 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1664 // CHECK1-SAME: () #[[ATTR4]] { 1665 // CHECK1-NEXT: entry: 1666 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1667 // CHECK1-NEXT: ret void 1668 // 1669 // 1670 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi 1671 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1672 // CHECK2-NEXT: entry: 1673 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1674 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 1675 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 1676 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1677 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1678 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1679 // CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1680 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1681 // CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 1682 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1683 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1684 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1685 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1686 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 1687 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1688 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1689 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1690 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 1691 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1692 // CHECK2-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 1693 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 1694 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 1695 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 1696 // CHECK2-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 1697 // CHECK2-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 1698 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 1699 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 1700 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 1701 // CHECK2-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 1702 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 1703 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 1704 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 1705 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 1706 // CHECK2-NEXT: [[NN:%.*]] = alloca i32, align 4 1707 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1708 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 1709 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 1710 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 1711 // CHECK2-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 1712 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 1713 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 1714 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 1715 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1716 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1717 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1718 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 1719 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1720 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1721 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1722 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1723 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 1724 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1725 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1726 // CHECK2-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 1727 // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 1728 // CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 1729 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 1730 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1731 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 1732 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1733 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1734 // CHECK2-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 1735 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1736 // CHECK2-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 1737 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1738 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1739 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 1740 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 1741 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1742 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1743 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 1744 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 1745 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 1746 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1747 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 1748 // CHECK2-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 1749 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1750 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1751 // CHECK2-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 1752 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1753 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 1754 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1755 // CHECK2-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 1756 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 1757 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1758 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 1759 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 1760 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1761 // CHECK2-NEXT: store i8* null, i8** [[TMP24]], align 8 1762 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1763 // CHECK2-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 1764 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 1765 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1766 // CHECK2-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 1767 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 1768 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1769 // CHECK2-NEXT: store i8* null, i8** [[TMP29]], align 8 1770 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1771 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1772 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 1773 // CHECK2-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 1774 // CHECK2-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 1775 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 1776 // CHECK2-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1777 // CHECK2-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 1778 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 1779 // CHECK2-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1780 // CHECK2-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 1781 // CHECK2-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 1782 // CHECK2-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 1783 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 1784 // CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 1785 // CHECK2-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 1786 // CHECK2-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 1787 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 1788 // CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 1789 // CHECK2-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 1790 // CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 1791 // CHECK2-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 1792 // CHECK2-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 1793 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 1794 // CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 1795 // CHECK2-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 1796 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 1797 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 1798 // CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 1799 // CHECK2-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 1800 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 1801 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 1802 // CHECK2-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 1803 // CHECK2-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 1804 // CHECK2-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 1805 // CHECK2-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 1806 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1807 // CHECK2-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 1808 // CHECK2-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 1809 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 1810 // CHECK2-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 1811 // CHECK2-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 1812 // CHECK2-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 1813 // CHECK2-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 1814 // CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 1815 // CHECK2-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 1816 // CHECK2-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 1817 // CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 1818 // CHECK2-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 1819 // CHECK2-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 1820 // CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 1821 // CHECK2-NEXT: store i8* null, i8** [[TMP65]], align 8 1822 // CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 1823 // CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 1824 // CHECK2-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1825 // CHECK2-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 1826 // CHECK2-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1827 // CHECK2: omp_offload.failed: 1828 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 1829 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1830 // CHECK2: omp_offload.cont: 1831 // CHECK2-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 1832 // CHECK2-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 1833 // CHECK2-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 1834 // CHECK2-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 1835 // CHECK2-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 1836 // CHECK2-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 1837 // CHECK2-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 1838 // CHECK2-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 1839 // CHECK2-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 1840 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 1841 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1842 // CHECK2: omp_if.then: 1843 // CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 1844 // CHECK2-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 1845 // CHECK2-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 1846 // CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 1847 // CHECK2-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 1848 // CHECK2-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 1849 // CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 1850 // CHECK2-NEXT: store i8* null, i8** [[TMP79]], align 8 1851 // CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 1852 // CHECK2-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 1853 // CHECK2-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 1854 // CHECK2-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 1855 // CHECK2-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 1856 // CHECK2-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 1857 // CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 1858 // CHECK2-NEXT: store i8* null, i8** [[TMP84]], align 8 1859 // CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 1860 // CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 1861 // CHECK2-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1862 // CHECK2-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 1863 // CHECK2-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 1864 // CHECK2: omp_offload.failed19: 1865 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 1866 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT20]] 1867 // CHECK2: omp_offload.cont20: 1868 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 1869 // CHECK2: omp_if.else: 1870 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 1871 // CHECK2-NEXT: br label [[OMP_IF_END]] 1872 // CHECK2: omp_if.end: 1873 // CHECK2-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 1874 // CHECK2-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* 1875 // CHECK2-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 1876 // CHECK2-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 1877 // CHECK2-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 1878 // CHECK2-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 1879 // CHECK2-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] 1880 // CHECK2: omp_if.then24: 1881 // CHECK2-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 1882 // CHECK2-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 1883 // CHECK2-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 1884 // CHECK2-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1885 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) 1886 // CHECK2-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 1887 // CHECK2-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* 1888 // CHECK2-NEXT: store i64 [[TMP90]], i64* [[TMP97]], align 8 1889 // CHECK2-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 1890 // CHECK2-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* 1891 // CHECK2-NEXT: store i64 [[TMP90]], i64* [[TMP99]], align 8 1892 // CHECK2-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 1893 // CHECK2-NEXT: store i8* null, i8** [[TMP100]], align 8 1894 // CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 1895 // CHECK2-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 1896 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 1897 // CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 1898 // CHECK2-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 1899 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 1900 // CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 1901 // CHECK2-NEXT: store i8* null, i8** [[TMP105]], align 8 1902 // CHECK2-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 1903 // CHECK2-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* 1904 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP107]], align 8 1905 // CHECK2-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 1906 // CHECK2-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64* 1907 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP109]], align 8 1908 // CHECK2-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 1909 // CHECK2-NEXT: store i8* null, i8** [[TMP110]], align 8 1910 // CHECK2-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 1911 // CHECK2-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 1912 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP112]], align 8 1913 // CHECK2-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 1914 // CHECK2-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 1915 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 1916 // CHECK2-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1917 // CHECK2-NEXT: store i64 [[TMP92]], i64* [[TMP115]], align 8 1918 // CHECK2-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 1919 // CHECK2-NEXT: store i8* null, i8** [[TMP116]], align 8 1920 // CHECK2-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 1921 // CHECK2-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 1922 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8 1923 // CHECK2-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 1924 // CHECK2-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 1925 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 1926 // CHECK2-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 1927 // CHECK2-NEXT: store i8* null, i8** [[TMP121]], align 8 1928 // CHECK2-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 1929 // CHECK2-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64* 1930 // CHECK2-NEXT: store i64 5, i64* [[TMP123]], align 8 1931 // CHECK2-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 1932 // CHECK2-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* 1933 // CHECK2-NEXT: store i64 5, i64* [[TMP125]], align 8 1934 // CHECK2-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 1935 // CHECK2-NEXT: store i8* null, i8** [[TMP126]], align 8 1936 // CHECK2-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 1937 // CHECK2-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 1938 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 1939 // CHECK2-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 1940 // CHECK2-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64* 1941 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP130]], align 8 1942 // CHECK2-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 1943 // CHECK2-NEXT: store i8* null, i8** [[TMP131]], align 8 1944 // CHECK2-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 1945 // CHECK2-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 1946 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP133]], align 8 1947 // CHECK2-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 1948 // CHECK2-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 1949 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP135]], align 8 1950 // CHECK2-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 1951 // CHECK2-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 8 1952 // CHECK2-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 1953 // CHECK2-NEXT: store i8* null, i8** [[TMP137]], align 8 1954 // CHECK2-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 1955 // CHECK2-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 1956 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8 1957 // CHECK2-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 1958 // CHECK2-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 1959 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8 1960 // CHECK2-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 1961 // CHECK2-NEXT: store i8* null, i8** [[TMP142]], align 8 1962 // CHECK2-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 1963 // CHECK2-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 1964 // CHECK2-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1965 // CHECK2-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1966 // CHECK2-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 1967 // CHECK2-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] 1968 // CHECK2: omp_offload.failed28: 1969 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 1970 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT29]] 1971 // CHECK2: omp_offload.cont29: 1972 // CHECK2-NEXT: br label [[OMP_IF_END31:%.*]] 1973 // CHECK2: omp_if.else30: 1974 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 1975 // CHECK2-NEXT: br label [[OMP_IF_END31]] 1976 // CHECK2: omp_if.end31: 1977 // CHECK2-NEXT: store i32 0, i32* [[NN]], align 4 1978 // CHECK2-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 1979 // CHECK2-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1980 // CHECK2-NEXT: store i32 [[TMP148]], i32* [[CONV32]], align 4 1981 // CHECK2-NEXT: [[TMP149:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1982 // CHECK2-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 1983 // CHECK2-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* 1984 // CHECK2-NEXT: store i64 [[TMP149]], i64* [[TMP151]], align 8 1985 // CHECK2-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 1986 // CHECK2-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* 1987 // CHECK2-NEXT: store i64 [[TMP149]], i64* [[TMP153]], align 8 1988 // CHECK2-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 1989 // CHECK2-NEXT: store i8* null, i8** [[TMP154]], align 8 1990 // CHECK2-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 1991 // CHECK2-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 1992 // CHECK2-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 1993 // CHECK2-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 1994 // CHECK2-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 1995 // CHECK2: omp_offload.failed36: 1996 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP149]]) #[[ATTR3]] 1997 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT37]] 1998 // CHECK2: omp_offload.cont37: 1999 // CHECK2-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 2000 // CHECK2-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* 2001 // CHECK2-NEXT: store i32 [[TMP159]], i32* [[CONV39]], align 4 2002 // CHECK2-NEXT: [[TMP160:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 2003 // CHECK2-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 2004 // CHECK2-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i64* 2005 // CHECK2-NEXT: store i64 [[TMP160]], i64* [[TMP162]], align 8 2006 // CHECK2-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 2007 // CHECK2-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i64* 2008 // CHECK2-NEXT: store i64 [[TMP160]], i64* [[TMP164]], align 8 2009 // CHECK2-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 2010 // CHECK2-NEXT: store i8* null, i8** [[TMP165]], align 8 2011 // CHECK2-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 2012 // CHECK2-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 2013 // CHECK2-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2014 // CHECK2-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 2015 // CHECK2-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] 2016 // CHECK2: omp_offload.failed43: 2017 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP160]]) #[[ATTR3]] 2018 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT44]] 2019 // CHECK2: omp_offload.cont44: 2020 // CHECK2-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 2021 // CHECK2-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2022 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 2023 // CHECK2-NEXT: ret i32 [[TMP170]] 2024 // 2025 // 2026 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2027 // CHECK2-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 2028 // CHECK2-NEXT: entry: 2029 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2030 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2031 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 2032 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2033 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2034 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2035 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2036 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 2037 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2038 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2039 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 2040 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 2041 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 2042 // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 2043 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2044 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2045 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 2046 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2047 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 2048 // CHECK2-NEXT: ret void 2049 // 2050 // 2051 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 2052 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 2053 // CHECK2-NEXT: entry: 2054 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2055 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2056 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2057 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2058 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2059 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2060 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2061 // CHECK2-NEXT: ret void 2062 // 2063 // 2064 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2065 // CHECK2-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 2066 // CHECK2-NEXT: entry: 2067 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 2068 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 2069 // CHECK2-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 2070 // CHECK2-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 2071 // CHECK2-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 2072 // CHECK2-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 2073 // CHECK2-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 2074 // CHECK2-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 2075 // CHECK2-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 2076 // CHECK2-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 2077 // CHECK2-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 2078 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 2079 // CHECK2-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 2080 // CHECK2-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 2081 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 2082 // CHECK2-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 2083 // CHECK2-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 2084 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 2085 // CHECK2-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 2086 // CHECK2-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 2087 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 2088 // CHECK2-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 2089 // CHECK2-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 2090 // CHECK2-NEXT: ret void 2091 // 2092 // 2093 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. 2094 // CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2095 // CHECK2-NEXT: entry: 2096 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2097 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 2098 // CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 2099 // CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 2100 // CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 2101 // CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 2102 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 2103 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 2104 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 2105 // CHECK2-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 2106 // CHECK2-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 2107 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 2108 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 2109 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2110 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 2111 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2112 // CHECK2-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 2113 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2114 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 2115 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2116 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2117 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2118 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 2119 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2120 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 2121 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 2122 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2123 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 2124 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 2125 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2126 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 2127 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 2128 // CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 2129 // CHECK2-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 2130 // CHECK2-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 2131 // CHECK2-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 2132 // CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 2133 // CHECK2-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 2134 // CHECK2-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 2135 // CHECK2-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 2136 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 2137 // CHECK2-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 2138 // CHECK2-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 2139 // CHECK2-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 2140 // CHECK2-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 2141 // CHECK2-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 2142 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 2143 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 2144 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 2145 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 2146 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 2147 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 2148 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 2149 // CHECK2-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 2150 // CHECK2-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 2151 // CHECK2-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2152 // CHECK2: omp_offload.failed.i: 2153 // CHECK2-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 2154 // CHECK2-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 2155 // CHECK2-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 2156 // CHECK2-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 2157 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 2158 // CHECK2-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 2159 // CHECK2-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24 2160 // CHECK2-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24 2161 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 2162 // CHECK2-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 2163 // CHECK2-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24 2164 // CHECK2-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24 2165 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 2166 // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2167 // CHECK2: .omp_outlined..1.exit: 2168 // CHECK2-NEXT: ret i32 0 2169 // 2170 // 2171 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 2172 // CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { 2173 // CHECK2-NEXT: entry: 2174 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2175 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2176 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2177 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2178 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2179 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2180 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2181 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2182 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2183 // CHECK2-NEXT: ret void 2184 // 2185 // 2186 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 2187 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 2188 // CHECK2-NEXT: entry: 2189 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2190 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2191 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2192 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2193 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2194 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2195 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2196 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2197 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2198 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2199 // CHECK2-NEXT: ret void 2200 // 2201 // 2202 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 2203 // CHECK2-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 2204 // CHECK2-NEXT: entry: 2205 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2206 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2207 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2208 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2209 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2210 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2211 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2212 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2213 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2214 // CHECK2-NEXT: ret void 2215 // 2216 // 2217 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 2218 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 2219 // CHECK2-NEXT: entry: 2220 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2221 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2222 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2223 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2224 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2225 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2226 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2227 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2228 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2229 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 2230 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2231 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 2232 // CHECK2-NEXT: ret void 2233 // 2234 // 2235 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 2236 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 2237 // CHECK2-NEXT: entry: 2238 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2239 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2240 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2241 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2242 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2243 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2244 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2245 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2246 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2247 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2248 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 2249 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2250 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2251 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2252 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 2253 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2254 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 2255 // CHECK2-NEXT: ret void 2256 // 2257 // 2258 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 2259 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 2260 // CHECK2-NEXT: entry: 2261 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2262 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2263 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2264 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2265 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2266 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2267 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2268 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2269 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2270 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2271 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2272 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2273 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2274 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 2275 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 2276 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2277 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2278 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 2279 // CHECK2-NEXT: ret void 2280 // 2281 // 2282 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 2283 // CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 2284 // CHECK2-NEXT: entry: 2285 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2286 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2287 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2288 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2289 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2290 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2291 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2292 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2293 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2294 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2295 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2296 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2297 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2298 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2299 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2300 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2301 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2302 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2303 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2304 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2305 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2306 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2307 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2308 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2309 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2310 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2311 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2312 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2313 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2314 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2315 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 2316 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 2317 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2318 // CHECK2-NEXT: ret void 2319 // 2320 // 2321 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 2322 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 2323 // CHECK2-NEXT: entry: 2324 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2325 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2326 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2327 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2328 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2329 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2330 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2331 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2332 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2333 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2334 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2335 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2336 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2337 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2338 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2339 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2340 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2341 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2342 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2343 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2344 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2345 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2346 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2347 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2348 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2349 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2350 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2351 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2352 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2353 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2354 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2355 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2356 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 2357 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2358 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 2359 // CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2360 // CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 2361 // CHECK2-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 2362 // CHECK2-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 2363 // CHECK2-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 2364 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 2365 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 2366 // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 2367 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 2368 // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 2369 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 2370 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 2371 // CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 2372 // CHECK2-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 2373 // CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 2374 // CHECK2-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 2375 // CHECK2-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 2376 // CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 2377 // CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 2378 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 2379 // CHECK2-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 2380 // CHECK2-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 2381 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2382 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 2383 // CHECK2-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 2384 // CHECK2-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 2385 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2386 // CHECK2-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 2387 // CHECK2-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 2388 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 2389 // CHECK2-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 2390 // CHECK2-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 2391 // CHECK2-NEXT: ret void 2392 // 2393 // 2394 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 2395 // CHECK2-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 2396 // CHECK2-NEXT: entry: 2397 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2398 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 2399 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2400 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2401 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2402 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 2403 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2404 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 2405 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2406 // CHECK2-NEXT: ret void 2407 // 2408 // 2409 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..12 2410 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 2411 // CHECK2-NEXT: entry: 2412 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2413 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2414 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2415 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 2416 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2417 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2418 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2419 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2420 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2421 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 2422 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2423 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 2424 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2425 // CHECK2-NEXT: ret void 2426 // 2427 // 2428 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 2429 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 2430 // CHECK2-NEXT: entry: 2431 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2432 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2433 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2434 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2435 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2436 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2437 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2438 // CHECK2-NEXT: ret void 2439 // 2440 // 2441 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 2442 // CHECK2-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 2443 // CHECK2-NEXT: entry: 2444 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2445 // CHECK2-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 2446 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2447 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2448 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2449 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 2450 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 2451 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 2452 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2453 // CHECK2-NEXT: ret void 2454 // 2455 // 2456 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 2457 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 2458 // CHECK2-NEXT: entry: 2459 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2460 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2461 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 2462 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2463 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2464 // CHECK2-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 2465 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 2466 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[CONV]]) 2467 // CHECK2-NEXT: ret void 2468 // 2469 // 2470 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..17 2471 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 2472 // CHECK2-NEXT: entry: 2473 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2474 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2475 // CHECK2-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 2476 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2477 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2478 // CHECK2-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 2479 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 2480 // CHECK2-NEXT: ret void 2481 // 2482 // 2483 // CHECK2-LABEL: define {{[^@]+}}@_Z6bazzzziPi 2484 // CHECK2-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 2485 // CHECK2-NEXT: entry: 2486 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2487 // CHECK2-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 2488 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 2489 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 2490 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 2491 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2492 // CHECK2-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 2493 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2494 // CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2495 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2496 // CHECK2-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 2497 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 2498 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2499 // CHECK2-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 2500 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 2501 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2502 // CHECK2-NEXT: store i8* null, i8** [[TMP6]], align 8 2503 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2504 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2505 // CHECK2-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2506 // CHECK2-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2507 // CHECK2-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2508 // CHECK2: omp_offload.failed: 2509 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 2510 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2511 // CHECK2: omp_offload.cont: 2512 // CHECK2-NEXT: ret void 2513 // 2514 // 2515 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 2516 // CHECK2-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 2517 // CHECK2-NEXT: entry: 2518 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2519 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2520 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2521 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 2522 // CHECK2-NEXT: ret void 2523 // 2524 // 2525 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..20 2526 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 2527 // CHECK2-NEXT: entry: 2528 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2529 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2530 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2531 // CHECK2-NEXT: [[F:%.*]] = alloca i32*, align 8 2532 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2533 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2534 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2535 // CHECK2-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2536 // CHECK2-NEXT: ret void 2537 // 2538 // 2539 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari 2540 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 2541 // CHECK2-NEXT: entry: 2542 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2543 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2544 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 2545 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2546 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2547 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2548 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 2549 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2550 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2551 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2552 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2553 // CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 2554 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2555 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2556 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2557 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2558 // CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 2559 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2560 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2561 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2562 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2563 // CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 2564 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2565 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2566 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2567 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2568 // CHECK2-NEXT: ret i32 [[TMP8]] 2569 // 2570 // 2571 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2572 // CHECK2-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2573 // CHECK2-NEXT: entry: 2574 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2575 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2576 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 2577 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2578 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2579 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2580 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 2581 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 2582 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 2583 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 2584 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2585 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2586 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2587 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2588 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2589 // CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4 2590 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2591 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 2592 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 2593 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 2594 // CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 2595 // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 2596 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 2597 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 2598 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2599 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 2600 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 2601 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 2602 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 2603 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2604 // CHECK2: omp_if.then: 2605 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2606 // CHECK2-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 2607 // CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 2608 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2609 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i64 40, i1 false) 2610 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2611 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 2612 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 2613 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2614 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 2615 // CHECK2-NEXT: store double* [[A]], double** [[TMP14]], align 8 2616 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2617 // CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8 2618 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2619 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 2620 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 2621 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2622 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 2623 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 2624 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2625 // CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8 2626 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2627 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 2628 // CHECK2-NEXT: store i64 2, i64* [[TMP22]], align 8 2629 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2630 // CHECK2-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 2631 // CHECK2-NEXT: store i64 2, i64* [[TMP24]], align 8 2632 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2633 // CHECK2-NEXT: store i8* null, i8** [[TMP25]], align 8 2634 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2635 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 2636 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 2637 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2638 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 2639 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 2640 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2641 // CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8 2642 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2643 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 2644 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 2645 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2646 // CHECK2-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 2647 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 2648 // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2649 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 2650 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 2651 // CHECK2-NEXT: store i8* null, i8** [[TMP36]], align 8 2652 // CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2653 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2654 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2655 // CHECK2-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2656 // CHECK2-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 2657 // CHECK2-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2658 // CHECK2: omp_offload.failed: 2659 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 2660 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2661 // CHECK2: omp_offload.cont: 2662 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2663 // CHECK2: omp_if.else: 2664 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 2665 // CHECK2-NEXT: br label [[OMP_IF_END]] 2666 // CHECK2: omp_if.end: 2667 // CHECK2-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 2668 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 2669 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 2670 // CHECK2-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 2671 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 2672 // CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 2673 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 2674 // CHECK2-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2675 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 2676 // CHECK2-NEXT: ret i32 [[ADD4]] 2677 // 2678 // 2679 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici 2680 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 2681 // CHECK2-NEXT: entry: 2682 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2683 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2684 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 2685 // CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1 2686 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2687 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2688 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2689 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2690 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 2691 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 2692 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 2693 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2694 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2695 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 2696 // CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1 2697 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2698 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2699 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 2700 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2701 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2702 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2703 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2704 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2705 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 2706 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 2707 // CHECK2-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 2708 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 2709 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2710 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 2711 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2712 // CHECK2: omp_if.then: 2713 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2714 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 2715 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 2716 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2717 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 2718 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 2719 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2720 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8 2721 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2722 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2723 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 2724 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2725 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 2726 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 2727 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2728 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8 2729 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2730 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 2731 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 2732 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2733 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 2734 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 2735 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2736 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 2737 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2738 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 2739 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 2740 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2741 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 2742 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 2743 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2744 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8 2745 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2746 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2747 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2748 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2749 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2750 // CHECK2: omp_offload.failed: 2751 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 2752 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2753 // CHECK2: omp_offload.cont: 2754 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2755 // CHECK2: omp_if.else: 2756 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 2757 // CHECK2-NEXT: br label [[OMP_IF_END]] 2758 // CHECK2: omp_if.end: 2759 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 2760 // CHECK2-NEXT: ret i32 [[TMP31]] 2761 // 2762 // 2763 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2764 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 2765 // CHECK2-NEXT: entry: 2766 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2767 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2768 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 2769 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2770 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2771 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2772 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 2773 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 2774 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 2775 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2776 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2777 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 2778 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2779 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2780 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 2781 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2782 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2783 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2784 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2785 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2786 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2787 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 2788 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2789 // CHECK2: omp_if.then: 2790 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2791 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 2792 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 2793 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2794 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 2795 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 2796 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2797 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8 2798 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2799 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 2800 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 2801 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2802 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2803 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 2804 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2805 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8 2806 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2807 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 2808 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 2809 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2810 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 2811 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 2812 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2813 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 2814 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2815 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2816 // CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 2817 // CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2818 // CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2819 // CHECK2: omp_offload.failed: 2820 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 2821 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2822 // CHECK2: omp_offload.cont: 2823 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2824 // CHECK2: omp_if.else: 2825 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 2826 // CHECK2-NEXT: br label [[OMP_IF_END]] 2827 // CHECK2: omp_if.end: 2828 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 2829 // CHECK2-NEXT: ret i32 [[TMP24]] 2830 // 2831 // 2832 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 2833 // CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2834 // CHECK2-NEXT: entry: 2835 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2836 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2837 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2838 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2839 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2840 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2841 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2842 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2843 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2844 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2845 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2846 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2847 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2848 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2849 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2850 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2851 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2852 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2853 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 2854 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 2855 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 2856 // CHECK2-NEXT: ret void 2857 // 2858 // 2859 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..23 2860 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2861 // CHECK2-NEXT: entry: 2862 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2863 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2864 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2865 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2866 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2867 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2868 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2869 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2870 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2871 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2872 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2873 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2874 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2875 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2876 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2877 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2878 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2879 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2880 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2881 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2882 // CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 2883 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 2884 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2885 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 2886 // CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2887 // CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 2888 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 2889 // CHECK2-NEXT: store double [[INC]], double* [[A4]], align 8 2890 // CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 2891 // CHECK2-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 2892 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 2893 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 2894 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 2895 // CHECK2-NEXT: ret void 2896 // 2897 // 2898 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 2899 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2900 // CHECK2-NEXT: entry: 2901 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2902 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2903 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2904 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2905 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2906 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2907 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2908 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2909 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2910 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2911 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2912 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2913 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2914 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2915 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2916 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2917 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2918 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 2919 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2920 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2921 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2922 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 2923 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2924 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 2925 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 2926 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 2927 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 2928 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 2929 // CHECK2-NEXT: ret void 2930 // 2931 // 2932 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..26 2933 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2934 // CHECK2-NEXT: entry: 2935 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2936 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2937 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2938 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2939 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2940 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2941 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2942 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2943 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2944 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2945 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2946 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2947 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2948 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2949 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2950 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2951 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2952 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2953 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2954 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2955 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 2956 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2957 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2958 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 2959 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 2960 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 2961 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 2962 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 2963 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 2964 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 2965 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2966 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 2967 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 2968 // CHECK2-NEXT: ret void 2969 // 2970 // 2971 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 2972 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2973 // CHECK2-NEXT: entry: 2974 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2975 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2976 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2977 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2978 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2979 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2980 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2981 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2982 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2983 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2984 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2985 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2986 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2987 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 2988 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2989 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2990 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2991 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 2992 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2993 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 2994 // CHECK2-NEXT: ret void 2995 // 2996 // 2997 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..29 2998 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2999 // CHECK2-NEXT: entry: 3000 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3001 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3002 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3003 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3004 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3005 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3006 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3007 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3008 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3009 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3010 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3011 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3012 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3013 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3014 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3015 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3016 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 3017 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 3018 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3019 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3020 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 3021 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 3022 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3023 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 3024 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 3025 // CHECK2-NEXT: ret void 3026 // 3027 // 3028 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3029 // CHECK2-SAME: () #[[ATTR4]] { 3030 // CHECK2-NEXT: entry: 3031 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 3032 // CHECK2-NEXT: ret void 3033 // 3034 // 3035 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 3036 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3037 // CHECK3-NEXT: entry: 3038 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3039 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3040 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3041 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3042 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3043 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3044 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3045 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3046 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 3047 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3048 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 3049 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3050 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 3051 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 3052 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3053 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3054 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3055 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 3056 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3057 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 3058 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 3059 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 3060 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 3061 // CHECK3-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 3062 // CHECK3-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 3063 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 3064 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 3065 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 3066 // CHECK3-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 3067 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 3068 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 3069 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 3070 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 3071 // CHECK3-NEXT: [[NN:%.*]] = alloca i32, align 4 3072 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3073 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 3074 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 3075 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 3076 // CHECK3-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 3077 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 3078 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 3079 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 3080 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 3081 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3082 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3083 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3084 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3085 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3086 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3087 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 3088 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3089 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 3090 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 3091 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 3092 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 3093 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3094 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 3095 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3096 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 3097 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 3098 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3099 // CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 3100 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3101 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3102 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 3103 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 3104 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3105 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 3106 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 3107 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3108 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 3109 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 3110 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3111 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 3112 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 3113 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3114 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 3115 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3116 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 3117 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 3118 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3119 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 3120 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 3121 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3122 // CHECK3-NEXT: store i8* null, i8** [[TMP22]], align 4 3123 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3124 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 3125 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 3126 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3127 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 3128 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 3129 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3130 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4 3131 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3132 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3133 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 3134 // CHECK3-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 3135 // CHECK3-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 3136 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 3137 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3138 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 3139 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 3140 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 3141 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 3142 // CHECK3-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 3143 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 3144 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 3145 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 3146 // CHECK3-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 3147 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 3148 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 3149 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 3150 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 3151 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 3152 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 3153 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 3154 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 3155 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 3156 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 3157 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 3158 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 3159 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 3160 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 3161 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 3162 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 3163 // CHECK3-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 3164 // CHECK3-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 3165 // CHECK3-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 3166 // CHECK3-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 3167 // CHECK3-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 3168 // CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 3169 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 3170 // CHECK3-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 3171 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 3172 // CHECK3-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 3173 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 3174 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 3175 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 3176 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 3177 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 3178 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 3179 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 3180 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 3181 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4 3182 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 3183 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 3184 // CHECK3-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3185 // CHECK3-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 3186 // CHECK3-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3187 // CHECK3: omp_offload.failed: 3188 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 3189 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3190 // CHECK3: omp_offload.cont: 3191 // CHECK3-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 3192 // CHECK3-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 3193 // CHECK3-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 3194 // CHECK3-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 3195 // CHECK3-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 3196 // CHECK3-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 3197 // CHECK3-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 3198 // CHECK3-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 3199 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 3200 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3201 // CHECK3: omp_if.then: 3202 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 3203 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 3204 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 3205 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 3206 // CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 3207 // CHECK3-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 3208 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 3209 // CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4 3210 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 3211 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 3212 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 3213 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 3214 // CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 3215 // CHECK3-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 3216 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 3217 // CHECK3-NEXT: store i8* null, i8** [[TMP82]], align 4 3218 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 3219 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 3220 // CHECK3-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3221 // CHECK3-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 3222 // CHECK3-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 3223 // CHECK3: omp_offload.failed15: 3224 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 3225 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT16]] 3226 // CHECK3: omp_offload.cont16: 3227 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3228 // CHECK3: omp_if.else: 3229 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 3230 // CHECK3-NEXT: br label [[OMP_IF_END]] 3231 // CHECK3: omp_if.end: 3232 // CHECK3-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 3233 // CHECK3-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 3234 // CHECK3-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 3235 // CHECK3-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 3236 // CHECK3-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 3237 // CHECK3-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 3238 // CHECK3: omp_if.then19: 3239 // CHECK3-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 3240 // CHECK3-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 3241 // CHECK3-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 3242 // CHECK3-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 3243 // CHECK3-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 3244 // CHECK3-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3245 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) 3246 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 3247 // CHECK3-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* 3248 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP97]], align 4 3249 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 3250 // CHECK3-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 3251 // CHECK3-NEXT: store i32 [[TMP88]], i32* [[TMP99]], align 4 3252 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 3253 // CHECK3-NEXT: store i8* null, i8** [[TMP100]], align 4 3254 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 3255 // CHECK3-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 3256 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 3257 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 3258 // CHECK3-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 3259 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 3260 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 3261 // CHECK3-NEXT: store i8* null, i8** [[TMP105]], align 4 3262 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 3263 // CHECK3-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32* 3264 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP107]], align 4 3265 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 3266 // CHECK3-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* 3267 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP109]], align 4 3268 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 3269 // CHECK3-NEXT: store i8* null, i8** [[TMP110]], align 4 3270 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 3271 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 3272 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP112]], align 4 3273 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 3274 // CHECK3-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 3275 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 3276 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3277 // CHECK3-NEXT: store i64 [[TMP91]], i64* [[TMP115]], align 4 3278 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 3279 // CHECK3-NEXT: store i8* null, i8** [[TMP116]], align 4 3280 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 3281 // CHECK3-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 3282 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4 3283 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 3284 // CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 3285 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 3286 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 3287 // CHECK3-NEXT: store i8* null, i8** [[TMP121]], align 4 3288 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 3289 // CHECK3-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32* 3290 // CHECK3-NEXT: store i32 5, i32* [[TMP123]], align 4 3291 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 3292 // CHECK3-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* 3293 // CHECK3-NEXT: store i32 5, i32* [[TMP125]], align 4 3294 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 3295 // CHECK3-NEXT: store i8* null, i8** [[TMP126]], align 4 3296 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 3297 // CHECK3-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 3298 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP128]], align 4 3299 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 3300 // CHECK3-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32* 3301 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP130]], align 4 3302 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 3303 // CHECK3-NEXT: store i8* null, i8** [[TMP131]], align 4 3304 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 3305 // CHECK3-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 3306 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP133]], align 4 3307 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 3308 // CHECK3-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 3309 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP135]], align 4 3310 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3311 // CHECK3-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 4 3312 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 3313 // CHECK3-NEXT: store i8* null, i8** [[TMP137]], align 4 3314 // CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 3315 // CHECK3-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 3316 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4 3317 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 3318 // CHECK3-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 3319 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4 3320 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 3321 // CHECK3-NEXT: store i8* null, i8** [[TMP142]], align 4 3322 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 3323 // CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 3324 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3325 // CHECK3-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3326 // CHECK3-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 3327 // CHECK3-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 3328 // CHECK3: omp_offload.failed23: 3329 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 3330 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT24]] 3331 // CHECK3: omp_offload.cont24: 3332 // CHECK3-NEXT: br label [[OMP_IF_END26:%.*]] 3333 // CHECK3: omp_if.else25: 3334 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 3335 // CHECK3-NEXT: br label [[OMP_IF_END26]] 3336 // CHECK3: omp_if.end26: 3337 // CHECK3-NEXT: store i32 0, i32* [[NN]], align 4 3338 // CHECK3-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 3339 // CHECK3-NEXT: store i32 [[TMP148]], i32* [[NN_CASTED]], align 4 3340 // CHECK3-NEXT: [[TMP149:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3341 // CHECK3-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 3342 // CHECK3-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* 3343 // CHECK3-NEXT: store i32 [[TMP149]], i32* [[TMP151]], align 4 3344 // CHECK3-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 3345 // CHECK3-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* 3346 // CHECK3-NEXT: store i32 [[TMP149]], i32* [[TMP153]], align 4 3347 // CHECK3-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 3348 // CHECK3-NEXT: store i8* null, i8** [[TMP154]], align 4 3349 // CHECK3-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 3350 // CHECK3-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 3351 // CHECK3-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3352 // CHECK3-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 3353 // CHECK3-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 3354 // CHECK3: omp_offload.failed30: 3355 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP149]]) #[[ATTR3]] 3356 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT31]] 3357 // CHECK3: omp_offload.cont31: 3358 // CHECK3-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 3359 // CHECK3-NEXT: store i32 [[TMP159]], i32* [[NN_CASTED32]], align 4 3360 // CHECK3-NEXT: [[TMP160:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 3361 // CHECK3-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 3362 // CHECK3-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32* 3363 // CHECK3-NEXT: store i32 [[TMP160]], i32* [[TMP162]], align 4 3364 // CHECK3-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 3365 // CHECK3-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32* 3366 // CHECK3-NEXT: store i32 [[TMP160]], i32* [[TMP164]], align 4 3367 // CHECK3-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 3368 // CHECK3-NEXT: store i8* null, i8** [[TMP165]], align 4 3369 // CHECK3-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 3370 // CHECK3-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 3371 // CHECK3-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3372 // CHECK3-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 3373 // CHECK3-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 3374 // CHECK3: omp_offload.failed36: 3375 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP160]]) #[[ATTR3]] 3376 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT37]] 3377 // CHECK3: omp_offload.cont37: 3378 // CHECK3-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 3379 // CHECK3-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3380 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 3381 // CHECK3-NEXT: ret i32 [[TMP170]] 3382 // 3383 // 3384 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 3385 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 3386 // CHECK3-NEXT: entry: 3387 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3388 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 3389 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 3390 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3391 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3392 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3393 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3394 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 3395 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3396 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3397 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 3398 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 3399 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3400 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3401 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 3402 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3403 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 3404 // CHECK3-NEXT: ret void 3405 // 3406 // 3407 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 3408 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3409 // CHECK3-NEXT: entry: 3410 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3411 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3412 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3413 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3414 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3415 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3416 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3417 // CHECK3-NEXT: ret void 3418 // 3419 // 3420 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 3421 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 3422 // CHECK3-NEXT: entry: 3423 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 3424 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 3425 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 3426 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 3427 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 3428 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 3429 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 3430 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 3431 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 3432 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 3433 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 3434 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 3435 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 3436 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 3437 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 3438 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 3439 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 3440 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 3441 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 3442 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 3443 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 3444 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 3445 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 3446 // CHECK3-NEXT: ret void 3447 // 3448 // 3449 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 3450 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 3451 // CHECK3-NEXT: entry: 3452 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 3453 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 3454 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 3455 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 3456 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 3457 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 3458 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 3459 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 3460 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 3461 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 3462 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 3463 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 3464 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 3465 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 3466 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 3467 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 3468 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 3469 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 3470 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 3471 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 3472 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 3473 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 3474 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 3475 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 3476 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 3477 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 3478 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 3479 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 3480 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 3481 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 3482 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 3483 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 3484 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 3485 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 3486 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 3487 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 3488 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 3489 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 3490 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 3491 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 3492 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 3493 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 3494 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 3495 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 3496 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 3497 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 3498 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 3499 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 3500 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 3501 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 3502 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 3503 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 3504 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 3505 // CHECK3-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 3506 // CHECK3-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 3507 // CHECK3-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 3508 // CHECK3: omp_offload.failed.i: 3509 // CHECK3-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 3510 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 3511 // CHECK3-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25 3512 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 3513 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 3514 // CHECK3-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 3515 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 3516 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 3517 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 3518 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 3519 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 3520 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 3521 // CHECK3: .omp_outlined..1.exit: 3522 // CHECK3-NEXT: ret i32 0 3523 // 3524 // 3525 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 3526 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { 3527 // CHECK3-NEXT: entry: 3528 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3529 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3530 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3531 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3532 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3533 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3534 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3535 // CHECK3-NEXT: ret void 3536 // 3537 // 3538 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 3539 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 3540 // CHECK3-NEXT: entry: 3541 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3542 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3543 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3544 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3545 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3546 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3547 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3548 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3549 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3550 // CHECK3-NEXT: ret void 3551 // 3552 // 3553 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 3554 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3555 // CHECK3-NEXT: entry: 3556 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3557 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3558 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3559 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3560 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3561 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3562 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3563 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3564 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3565 // CHECK3-NEXT: ret void 3566 // 3567 // 3568 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 3569 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3570 // CHECK3-NEXT: entry: 3571 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3572 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3573 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3574 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3575 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3576 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3577 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3578 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3579 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3580 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 3581 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 3582 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 3583 // CHECK3-NEXT: ret void 3584 // 3585 // 3586 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 3587 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3588 // CHECK3-NEXT: entry: 3589 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3590 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3591 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3592 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3593 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3594 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3595 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3596 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3597 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3598 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3599 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3600 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3601 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3602 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3603 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 3604 // CHECK3-NEXT: ret void 3605 // 3606 // 3607 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 3608 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3609 // CHECK3-NEXT: entry: 3610 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3611 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3612 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3613 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3614 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3615 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3616 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3617 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3618 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3619 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3620 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3621 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3622 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 3623 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 3624 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3625 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3626 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3627 // CHECK3-NEXT: ret void 3628 // 3629 // 3630 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 3631 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 3632 // CHECK3-NEXT: entry: 3633 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3634 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3635 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3636 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3637 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3638 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3639 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3640 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3641 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3642 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3643 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3644 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3645 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3646 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3647 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3648 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3649 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3650 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3651 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3652 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3653 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3654 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3655 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3656 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3657 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3658 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3659 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3660 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3661 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 3662 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 3663 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 3664 // CHECK3-NEXT: ret void 3665 // 3666 // 3667 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 3668 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 3669 // CHECK3-NEXT: entry: 3670 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3671 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3672 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3673 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3674 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3675 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3676 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3677 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3678 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3679 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3680 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3681 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3682 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3683 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3684 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3685 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3686 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3687 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3688 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3689 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3690 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3691 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3692 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3693 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3694 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3695 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3696 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3697 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3698 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3699 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3700 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3701 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 3702 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3703 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 3704 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 3705 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 3706 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 3707 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 3708 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 3709 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 3710 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3711 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 3712 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 3713 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 3714 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 3715 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 3716 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 3717 // CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 3718 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 3719 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 3720 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 3721 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 3722 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 3723 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 3724 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 3725 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 3726 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 3727 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 3728 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 3729 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 3730 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 3731 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 3732 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 3733 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 3734 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 3735 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 3736 // CHECK3-NEXT: ret void 3737 // 3738 // 3739 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 3740 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3741 // CHECK3-NEXT: entry: 3742 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3743 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3744 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3745 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 3746 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 3747 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3748 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3749 // CHECK3-NEXT: ret void 3750 // 3751 // 3752 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 3753 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3754 // CHECK3-NEXT: entry: 3755 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3756 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3757 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3758 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3759 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3760 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3761 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3762 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 3763 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 3764 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3765 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3766 // CHECK3-NEXT: ret void 3767 // 3768 // 3769 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 3770 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3771 // CHECK3-NEXT: entry: 3772 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3773 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3774 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3775 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3776 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3777 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3778 // CHECK3-NEXT: ret void 3779 // 3780 // 3781 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 3782 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3783 // CHECK3-NEXT: entry: 3784 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3785 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 3786 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3787 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 3788 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 3789 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 3790 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3791 // CHECK3-NEXT: ret void 3792 // 3793 // 3794 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 3795 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 3796 // CHECK3-NEXT: entry: 3797 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3798 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3799 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 3800 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3801 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3802 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 3803 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 3804 // CHECK3-NEXT: ret void 3805 // 3806 // 3807 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..17 3808 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 3809 // CHECK3-NEXT: entry: 3810 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3811 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3812 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 3813 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3814 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3815 // CHECK3-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 3816 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 3817 // CHECK3-NEXT: ret void 3818 // 3819 // 3820 // CHECK3-LABEL: define {{[^@]+}}@_Z6bazzzziPi 3821 // CHECK3-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 3822 // CHECK3-NEXT: entry: 3823 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3824 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 3825 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 3826 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 3827 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 3828 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3829 // CHECK3-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 3830 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3831 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3832 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 3833 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 3834 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3835 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 3836 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 3837 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3838 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4 3839 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3840 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3841 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3842 // CHECK3-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 3843 // CHECK3-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3844 // CHECK3: omp_offload.failed: 3845 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 3846 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3847 // CHECK3: omp_offload.cont: 3848 // CHECK3-NEXT: ret void 3849 // 3850 // 3851 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 3852 // CHECK3-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 3853 // CHECK3-NEXT: entry: 3854 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3855 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3856 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3857 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 3858 // CHECK3-NEXT: ret void 3859 // 3860 // 3861 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..20 3862 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 3863 // CHECK3-NEXT: entry: 3864 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3865 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3866 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3867 // CHECK3-NEXT: [[F:%.*]] = alloca i32*, align 4 3868 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3869 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3870 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3871 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3872 // CHECK3-NEXT: ret void 3873 // 3874 // 3875 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 3876 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3877 // CHECK3-NEXT: entry: 3878 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3879 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3880 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3881 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3882 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3883 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3884 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 3885 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3886 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3887 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3888 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3889 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 3890 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3891 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3892 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3893 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3894 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 3895 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3896 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3897 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3898 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3899 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 3900 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3901 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 3902 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 3903 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 3904 // CHECK3-NEXT: ret i32 [[TMP8]] 3905 // 3906 // 3907 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3908 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3909 // CHECK3-NEXT: entry: 3910 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3911 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3912 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 3913 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3914 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3915 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3916 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 3917 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 3918 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 3919 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 3920 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3921 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3922 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3923 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3924 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3925 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 3926 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3927 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3928 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3929 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 3930 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 3931 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3932 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 3933 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3934 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3935 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3936 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3937 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3938 // CHECK3: omp_if.then: 3939 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3940 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3941 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3942 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3943 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3944 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i32 40, i1 false) 3945 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3946 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 3947 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 3948 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3949 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 3950 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 3951 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3952 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 3953 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3954 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 3955 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 3956 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3957 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 3958 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 3959 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3960 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 3961 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3962 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 3963 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 3964 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3965 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 3966 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 3967 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3968 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 3969 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3970 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3971 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 3972 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3973 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 3974 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 3975 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3976 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 3977 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3978 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 3979 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 3980 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3981 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 3982 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 3983 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3984 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 3985 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3986 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 3987 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3988 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3989 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3990 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 3991 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 3992 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3993 // CHECK3: omp_offload.failed: 3994 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 3995 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3996 // CHECK3: omp_offload.cont: 3997 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3998 // CHECK3: omp_if.else: 3999 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 4000 // CHECK3-NEXT: br label [[OMP_IF_END]] 4001 // CHECK3: omp_if.end: 4002 // CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 4003 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 4004 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4005 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 4006 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 4007 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 4008 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 4009 // CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4010 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 4011 // CHECK3-NEXT: ret i32 [[ADD3]] 4012 // 4013 // 4014 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 4015 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 4016 // CHECK3-NEXT: entry: 4017 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4018 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4019 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 4020 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 4021 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4022 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4023 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4024 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4025 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 4026 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 4027 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 4028 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4029 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4030 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 4031 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 4032 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4033 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4034 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4035 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4036 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4037 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4038 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4039 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 4040 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4041 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 4042 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4043 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4044 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4045 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4046 // CHECK3: omp_if.then: 4047 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4048 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4049 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4050 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4051 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 4052 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 4053 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4054 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 4055 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4056 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4057 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4058 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4059 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 4060 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 4061 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4062 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 4063 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4064 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 4065 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 4066 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4067 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 4068 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 4069 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4070 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 4071 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4072 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 4073 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 4074 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4075 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 4076 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 4077 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4078 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 4079 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4080 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4081 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4082 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 4083 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4084 // CHECK3: omp_offload.failed: 4085 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 4086 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4087 // CHECK3: omp_offload.cont: 4088 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4089 // CHECK3: omp_if.else: 4090 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 4091 // CHECK3-NEXT: br label [[OMP_IF_END]] 4092 // CHECK3: omp_if.end: 4093 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 4094 // CHECK3-NEXT: ret i32 [[TMP31]] 4095 // 4096 // 4097 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4098 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 4099 // CHECK3-NEXT: entry: 4100 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4101 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 4102 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 4103 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4104 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4105 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4106 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4107 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4108 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4109 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4110 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 4111 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 4112 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4113 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4114 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4115 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4116 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4117 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4118 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4119 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4120 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4121 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4122 // CHECK3: omp_if.then: 4123 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4124 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4125 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 4126 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4127 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4128 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4129 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4130 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 4131 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4132 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 4133 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 4134 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4135 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4136 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4137 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4138 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 4139 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4140 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 4141 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 4142 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4143 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 4144 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 4145 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4146 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 4147 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4148 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4149 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4150 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4151 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4152 // CHECK3: omp_offload.failed: 4153 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 4154 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 4155 // CHECK3: omp_offload.cont: 4156 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 4157 // CHECK3: omp_if.else: 4158 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 4159 // CHECK3-NEXT: br label [[OMP_IF_END]] 4160 // CHECK3: omp_if.end: 4161 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 4162 // CHECK3-NEXT: ret i32 [[TMP24]] 4163 // 4164 // 4165 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 4166 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 4167 // CHECK3-NEXT: entry: 4168 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4169 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4170 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4171 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4172 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4173 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4174 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4175 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4176 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4177 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4178 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4179 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4180 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4181 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4182 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4183 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4184 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4185 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4186 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 4187 // CHECK3-NEXT: ret void 4188 // 4189 // 4190 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..23 4191 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 4192 // CHECK3-NEXT: entry: 4193 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4194 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4195 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4196 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4197 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4198 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4199 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4200 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4201 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4202 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4203 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4204 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4205 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4206 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4207 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4208 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4209 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4210 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4211 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4212 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 4213 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4214 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4215 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 4216 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4217 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 4218 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 4219 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 4 4220 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 4221 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 4222 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 4223 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4224 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 4225 // CHECK3-NEXT: ret void 4226 // 4227 // 4228 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 4229 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4230 // CHECK3-NEXT: entry: 4231 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4232 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4233 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4234 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4235 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4236 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4237 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4238 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4239 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4240 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4241 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4242 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4243 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4244 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4245 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4246 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4247 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4248 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4249 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4250 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 4251 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4252 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 4253 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4254 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 4255 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4256 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 4257 // CHECK3-NEXT: ret void 4258 // 4259 // 4260 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..26 4261 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4262 // CHECK3-NEXT: entry: 4263 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4264 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4265 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4266 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4267 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4268 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4269 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4270 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4271 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4272 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4273 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4274 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4275 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4276 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4277 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4278 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4279 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4280 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4281 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4282 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 4283 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4284 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4285 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 4286 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 4287 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 4288 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 4289 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 4290 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 4291 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4292 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4293 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 4294 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 4295 // CHECK3-NEXT: ret void 4296 // 4297 // 4298 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 4299 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4300 // CHECK3-NEXT: entry: 4301 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4302 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4303 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4304 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4305 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4306 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4307 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4308 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4309 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4310 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4311 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4312 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4313 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4314 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4315 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4316 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 4317 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4318 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 4319 // CHECK3-NEXT: ret void 4320 // 4321 // 4322 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..29 4323 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4324 // CHECK3-NEXT: entry: 4325 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4326 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4327 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4328 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4329 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4330 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4331 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4332 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4333 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4334 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4335 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4336 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4337 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4338 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4339 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4340 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4341 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 4342 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 4343 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 4344 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 4345 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4346 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4347 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 4348 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 4349 // CHECK3-NEXT: ret void 4350 // 4351 // 4352 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4353 // CHECK3-SAME: () #[[ATTR4]] { 4354 // CHECK3-NEXT: entry: 4355 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 4356 // CHECK3-NEXT: ret void 4357 // 4358 // 4359 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi 4360 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 4361 // CHECK4-NEXT: entry: 4362 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4363 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 4364 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 4365 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x float], align 4 4366 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 4367 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 4368 // CHECK4-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 4369 // CHECK4-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 4370 // CHECK4-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 4371 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4372 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 4373 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4374 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4375 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 4376 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4377 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4378 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4379 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 4380 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4381 // CHECK4-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 4382 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 4383 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 4384 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 4385 // CHECK4-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 4386 // CHECK4-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 4387 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 4388 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 4389 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 4390 // CHECK4-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 4391 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 4392 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 4393 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 4394 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 4395 // CHECK4-NEXT: [[NN:%.*]] = alloca i32, align 4 4396 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 4397 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 4398 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 4399 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 4400 // CHECK4-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 4401 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 4402 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 4403 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 4404 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 4405 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4406 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 4407 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 4408 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4409 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 4410 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 4411 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 4412 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 4413 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 4414 // CHECK4-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 4415 // CHECK4-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 4416 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 4417 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4418 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 4419 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 4420 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 4421 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 4422 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4423 // CHECK4-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 4424 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4425 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4426 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4427 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4428 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 4429 // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 4430 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 4431 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4432 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 4433 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 4434 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4435 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 4436 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 4437 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4438 // CHECK4-NEXT: store i8* null, i8** [[TMP17]], align 4 4439 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4440 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4441 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 4442 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4443 // CHECK4-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 4444 // CHECK4-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 4445 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4446 // CHECK4-NEXT: store i8* null, i8** [[TMP22]], align 4 4447 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4448 // CHECK4-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 4449 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 4450 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4451 // CHECK4-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 4452 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 4453 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4454 // CHECK4-NEXT: store i8* null, i8** [[TMP27]], align 4 4455 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4456 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4457 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 4458 // CHECK4-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 4459 // CHECK4-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 4460 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 4461 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4462 // CHECK4-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 4463 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 4464 // CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 4465 // CHECK4-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 4466 // CHECK4-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 4467 // CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 4468 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 4469 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 4470 // CHECK4-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 4471 // CHECK4-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 4472 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 4473 // CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 4474 // CHECK4-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 4475 // CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 4476 // CHECK4-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 4477 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 4478 // CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 4479 // CHECK4-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 4480 // CHECK4-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 4481 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 4482 // CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 4483 // CHECK4-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 4484 // CHECK4-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 4485 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 4486 // CHECK4-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 4487 // CHECK4-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 4488 // CHECK4-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 4489 // CHECK4-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 4490 // CHECK4-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 4491 // CHECK4-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 4492 // CHECK4-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 4493 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 4494 // CHECK4-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 4495 // CHECK4-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 4496 // CHECK4-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 4497 // CHECK4-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 4498 // CHECK4-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 4499 // CHECK4-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 4500 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 4501 // CHECK4-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 4502 // CHECK4-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 4503 // CHECK4-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 4504 // CHECK4-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 4505 // CHECK4-NEXT: store i8* null, i8** [[TMP63]], align 4 4506 // CHECK4-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 4507 // CHECK4-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 4508 // CHECK4-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4509 // CHECK4-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 4510 // CHECK4-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4511 // CHECK4: omp_offload.failed: 4512 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 4513 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 4514 // CHECK4: omp_offload.cont: 4515 // CHECK4-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 4516 // CHECK4-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 4517 // CHECK4-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 4518 // CHECK4-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 4519 // CHECK4-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 4520 // CHECK4-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 4521 // CHECK4-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 4522 // CHECK4-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 4523 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 4524 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4525 // CHECK4: omp_if.then: 4526 // CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 4527 // CHECK4-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 4528 // CHECK4-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 4529 // CHECK4-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 4530 // CHECK4-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 4531 // CHECK4-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 4532 // CHECK4-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 4533 // CHECK4-NEXT: store i8* null, i8** [[TMP77]], align 4 4534 // CHECK4-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 4535 // CHECK4-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 4536 // CHECK4-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 4537 // CHECK4-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 4538 // CHECK4-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 4539 // CHECK4-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 4540 // CHECK4-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 4541 // CHECK4-NEXT: store i8* null, i8** [[TMP82]], align 4 4542 // CHECK4-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 4543 // CHECK4-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 4544 // CHECK4-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4545 // CHECK4-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 4546 // CHECK4-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 4547 // CHECK4: omp_offload.failed15: 4548 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 4549 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT16]] 4550 // CHECK4: omp_offload.cont16: 4551 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 4552 // CHECK4: omp_if.else: 4553 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 4554 // CHECK4-NEXT: br label [[OMP_IF_END]] 4555 // CHECK4: omp_if.end: 4556 // CHECK4-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 4557 // CHECK4-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 4558 // CHECK4-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 4559 // CHECK4-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 4560 // CHECK4-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 4561 // CHECK4-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 4562 // CHECK4: omp_if.then19: 4563 // CHECK4-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 4564 // CHECK4-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 4565 // CHECK4-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 4566 // CHECK4-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 4567 // CHECK4-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 4568 // CHECK4-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 4569 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) 4570 // CHECK4-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 4571 // CHECK4-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* 4572 // CHECK4-NEXT: store i32 [[TMP88]], i32* [[TMP97]], align 4 4573 // CHECK4-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 4574 // CHECK4-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 4575 // CHECK4-NEXT: store i32 [[TMP88]], i32* [[TMP99]], align 4 4576 // CHECK4-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 4577 // CHECK4-NEXT: store i8* null, i8** [[TMP100]], align 4 4578 // CHECK4-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 4579 // CHECK4-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 4580 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 4581 // CHECK4-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 4582 // CHECK4-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 4583 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 4584 // CHECK4-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 4585 // CHECK4-NEXT: store i8* null, i8** [[TMP105]], align 4 4586 // CHECK4-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 4587 // CHECK4-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32* 4588 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP107]], align 4 4589 // CHECK4-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 4590 // CHECK4-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* 4591 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP109]], align 4 4592 // CHECK4-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 4593 // CHECK4-NEXT: store i8* null, i8** [[TMP110]], align 4 4594 // CHECK4-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 4595 // CHECK4-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 4596 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP112]], align 4 4597 // CHECK4-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 4598 // CHECK4-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 4599 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 4600 // CHECK4-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 4601 // CHECK4-NEXT: store i64 [[TMP91]], i64* [[TMP115]], align 4 4602 // CHECK4-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 4603 // CHECK4-NEXT: store i8* null, i8** [[TMP116]], align 4 4604 // CHECK4-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 4605 // CHECK4-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 4606 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4 4607 // CHECK4-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 4608 // CHECK4-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 4609 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 4610 // CHECK4-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 4611 // CHECK4-NEXT: store i8* null, i8** [[TMP121]], align 4 4612 // CHECK4-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 4613 // CHECK4-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32* 4614 // CHECK4-NEXT: store i32 5, i32* [[TMP123]], align 4 4615 // CHECK4-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 4616 // CHECK4-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* 4617 // CHECK4-NEXT: store i32 5, i32* [[TMP125]], align 4 4618 // CHECK4-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 4619 // CHECK4-NEXT: store i8* null, i8** [[TMP126]], align 4 4620 // CHECK4-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 4621 // CHECK4-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 4622 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP128]], align 4 4623 // CHECK4-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 4624 // CHECK4-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32* 4625 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP130]], align 4 4626 // CHECK4-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 4627 // CHECK4-NEXT: store i8* null, i8** [[TMP131]], align 4 4628 // CHECK4-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 4629 // CHECK4-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 4630 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP133]], align 4 4631 // CHECK4-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 4632 // CHECK4-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 4633 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP135]], align 4 4634 // CHECK4-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 4635 // CHECK4-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 4 4636 // CHECK4-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 4637 // CHECK4-NEXT: store i8* null, i8** [[TMP137]], align 4 4638 // CHECK4-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 4639 // CHECK4-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 4640 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4 4641 // CHECK4-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 4642 // CHECK4-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 4643 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4 4644 // CHECK4-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 4645 // CHECK4-NEXT: store i8* null, i8** [[TMP142]], align 4 4646 // CHECK4-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 4647 // CHECK4-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 4648 // CHECK4-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4649 // CHECK4-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4650 // CHECK4-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 4651 // CHECK4-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 4652 // CHECK4: omp_offload.failed23: 4653 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 4654 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT24]] 4655 // CHECK4: omp_offload.cont24: 4656 // CHECK4-NEXT: br label [[OMP_IF_END26:%.*]] 4657 // CHECK4: omp_if.else25: 4658 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 4659 // CHECK4-NEXT: br label [[OMP_IF_END26]] 4660 // CHECK4: omp_if.end26: 4661 // CHECK4-NEXT: store i32 0, i32* [[NN]], align 4 4662 // CHECK4-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 4663 // CHECK4-NEXT: store i32 [[TMP148]], i32* [[NN_CASTED]], align 4 4664 // CHECK4-NEXT: [[TMP149:%.*]] = load i32, i32* [[NN_CASTED]], align 4 4665 // CHECK4-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 4666 // CHECK4-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* 4667 // CHECK4-NEXT: store i32 [[TMP149]], i32* [[TMP151]], align 4 4668 // CHECK4-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 4669 // CHECK4-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* 4670 // CHECK4-NEXT: store i32 [[TMP149]], i32* [[TMP153]], align 4 4671 // CHECK4-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 4672 // CHECK4-NEXT: store i8* null, i8** [[TMP154]], align 4 4673 // CHECK4-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 4674 // CHECK4-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 4675 // CHECK4-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4676 // CHECK4-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 4677 // CHECK4-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 4678 // CHECK4: omp_offload.failed30: 4679 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP149]]) #[[ATTR3]] 4680 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT31]] 4681 // CHECK4: omp_offload.cont31: 4682 // CHECK4-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 4683 // CHECK4-NEXT: store i32 [[TMP159]], i32* [[NN_CASTED32]], align 4 4684 // CHECK4-NEXT: [[TMP160:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 4685 // CHECK4-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 4686 // CHECK4-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32* 4687 // CHECK4-NEXT: store i32 [[TMP160]], i32* [[TMP162]], align 4 4688 // CHECK4-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 4689 // CHECK4-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32* 4690 // CHECK4-NEXT: store i32 [[TMP160]], i32* [[TMP164]], align 4 4691 // CHECK4-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 4692 // CHECK4-NEXT: store i8* null, i8** [[TMP165]], align 4 4693 // CHECK4-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 4694 // CHECK4-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 4695 // CHECK4-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 4696 // CHECK4-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 4697 // CHECK4-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 4698 // CHECK4: omp_offload.failed36: 4699 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP160]]) #[[ATTR3]] 4700 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT37]] 4701 // CHECK4: omp_offload.cont37: 4702 // CHECK4-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 4703 // CHECK4-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4704 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 4705 // CHECK4-NEXT: ret i32 [[TMP170]] 4706 // 4707 // 4708 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 4709 // CHECK4-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 4710 // CHECK4-NEXT: entry: 4711 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4712 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4713 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 4714 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4715 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4716 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4717 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4718 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 4719 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4720 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4721 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 4722 // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 4723 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4724 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4725 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 4726 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4727 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 4728 // CHECK4-NEXT: ret void 4729 // 4730 // 4731 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 4732 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 4733 // CHECK4-NEXT: entry: 4734 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4735 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4736 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4737 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4738 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4739 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4740 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4741 // CHECK4-NEXT: ret void 4742 // 4743 // 4744 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_privates_map. 4745 // CHECK4-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 4746 // CHECK4-NEXT: entry: 4747 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 4748 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 4749 // CHECK4-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 4750 // CHECK4-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 4751 // CHECK4-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 4752 // CHECK4-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 4753 // CHECK4-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 4754 // CHECK4-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 4755 // CHECK4-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 4756 // CHECK4-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 4757 // CHECK4-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 4758 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 4759 // CHECK4-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 4760 // CHECK4-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 4761 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 4762 // CHECK4-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 4763 // CHECK4-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 4764 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 4765 // CHECK4-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 4766 // CHECK4-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 4767 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 4768 // CHECK4-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 4769 // CHECK4-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 4770 // CHECK4-NEXT: ret void 4771 // 4772 // 4773 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. 4774 // CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 4775 // CHECK4-NEXT: entry: 4776 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 4777 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 4778 // CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 4779 // CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 4780 // CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 4781 // CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 4782 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 4783 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 4784 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 4785 // CHECK4-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 4786 // CHECK4-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 4787 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 4788 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 4789 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 4790 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 4791 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 4792 // CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 4793 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 4794 // CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 4795 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 4796 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 4797 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 4798 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 4799 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 4800 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 4801 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 4802 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 4803 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 4804 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 4805 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 4806 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 4807 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 4808 // CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 4809 // CHECK4-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 4810 // CHECK4-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 4811 // CHECK4-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 4812 // CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 4813 // CHECK4-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 4814 // CHECK4-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 4815 // CHECK4-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 4816 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 4817 // CHECK4-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 4818 // CHECK4-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 4819 // CHECK4-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 4820 // CHECK4-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 4821 // CHECK4-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 4822 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 4823 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 4824 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 4825 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 4826 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 4827 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 4828 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 4829 // CHECK4-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 4830 // CHECK4-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 4831 // CHECK4-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 4832 // CHECK4: omp_offload.failed.i: 4833 // CHECK4-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 4834 // CHECK4-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 4835 // CHECK4-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25 4836 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 4837 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 4838 // CHECK4-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 4839 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 4840 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 4841 // CHECK4-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 4842 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 4843 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 4844 // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 4845 // CHECK4: .omp_outlined..1.exit: 4846 // CHECK4-NEXT: ret i32 0 4847 // 4848 // 4849 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 4850 // CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { 4851 // CHECK4-NEXT: entry: 4852 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4853 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4854 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4855 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4856 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4857 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4858 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 4859 // CHECK4-NEXT: ret void 4860 // 4861 // 4862 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 4863 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 4864 // CHECK4-NEXT: entry: 4865 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4866 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4867 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4868 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4869 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4870 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4871 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4872 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4873 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4874 // CHECK4-NEXT: ret void 4875 // 4876 // 4877 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 4878 // CHECK4-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 4879 // CHECK4-NEXT: entry: 4880 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4881 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4882 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4883 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4884 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4885 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4886 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4887 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4888 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 4889 // CHECK4-NEXT: ret void 4890 // 4891 // 4892 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 4893 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 4894 // CHECK4-NEXT: entry: 4895 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4896 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4897 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4898 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4899 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4900 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4901 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4902 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4903 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 4904 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 4905 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 4906 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 4907 // CHECK4-NEXT: ret void 4908 // 4909 // 4910 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 4911 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 4912 // CHECK4-NEXT: entry: 4913 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4914 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4915 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4916 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4917 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4918 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4919 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4920 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4921 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4922 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4923 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4924 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4925 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4926 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4927 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 4928 // CHECK4-NEXT: ret void 4929 // 4930 // 4931 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 4932 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 4933 // CHECK4-NEXT: entry: 4934 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4935 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4936 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4937 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4938 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4939 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4940 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4941 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4942 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4943 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4944 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4945 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4946 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 4947 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 4948 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 4949 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 4950 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 4951 // CHECK4-NEXT: ret void 4952 // 4953 // 4954 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 4955 // CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 4956 // CHECK4-NEXT: entry: 4957 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4958 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4959 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4960 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4961 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4962 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4963 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4964 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4965 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4966 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4967 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4968 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4969 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4970 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4971 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4972 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4973 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4974 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4975 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4976 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4977 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4978 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4979 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4980 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4981 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4982 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4983 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4984 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4985 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 4986 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 4987 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 4988 // CHECK4-NEXT: ret void 4989 // 4990 // 4991 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 4992 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 4993 // CHECK4-NEXT: entry: 4994 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4995 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4996 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4997 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4998 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4999 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5000 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5001 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5002 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5003 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5004 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5005 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5006 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5007 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5008 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5009 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5010 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5011 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5012 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5013 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5014 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5015 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5016 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5017 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5018 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5019 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5020 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5021 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5022 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5023 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5024 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5025 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 5026 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5027 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 5028 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 5029 // CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 5030 // CHECK4-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 5031 // CHECK4-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 5032 // CHECK4-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 5033 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 5034 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 5035 // CHECK4-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 5036 // CHECK4-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 5037 // CHECK4-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 5038 // CHECK4-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 5039 // CHECK4-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 5040 // CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 5041 // CHECK4-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 5042 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 5043 // CHECK4-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 5044 // CHECK4-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 5045 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 5046 // CHECK4-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 5047 // CHECK4-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 5048 // CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 5049 // CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 5050 // CHECK4-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 5051 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 5052 // CHECK4-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 5053 // CHECK4-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 5054 // CHECK4-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 5055 // CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 5056 // CHECK4-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 5057 // CHECK4-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 5058 // CHECK4-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 5059 // CHECK4-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 5060 // CHECK4-NEXT: ret void 5061 // 5062 // 5063 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 5064 // CHECK4-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 5065 // CHECK4-NEXT: entry: 5066 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5067 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 5068 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5069 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 5070 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 5071 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 5072 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5073 // CHECK4-NEXT: ret void 5074 // 5075 // 5076 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..12 5077 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 5078 // CHECK4-NEXT: entry: 5079 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5080 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5081 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5082 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 5083 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5084 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5085 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5086 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 5087 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 5088 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 5089 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5090 // CHECK4-NEXT: ret void 5091 // 5092 // 5093 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 5094 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 5095 // CHECK4-NEXT: entry: 5096 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5097 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5098 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5099 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5100 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5101 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5102 // CHECK4-NEXT: ret void 5103 // 5104 // 5105 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 5106 // CHECK4-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 5107 // CHECK4-NEXT: entry: 5108 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5109 // CHECK4-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 5110 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5111 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 5112 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 5113 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 5114 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5115 // CHECK4-NEXT: ret void 5116 // 5117 // 5118 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 5119 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 5120 // CHECK4-NEXT: entry: 5121 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5122 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5123 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 5124 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5125 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5126 // CHECK4-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 5127 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 5128 // CHECK4-NEXT: ret void 5129 // 5130 // 5131 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..17 5132 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 5133 // CHECK4-NEXT: entry: 5134 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5135 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5136 // CHECK4-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 5137 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5138 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5139 // CHECK4-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 5140 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 5141 // CHECK4-NEXT: ret void 5142 // 5143 // 5144 // CHECK4-LABEL: define {{[^@]+}}@_Z6bazzzziPi 5145 // CHECK4-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 5146 // CHECK4-NEXT: entry: 5147 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5148 // CHECK4-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 5149 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 5150 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 5151 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 5152 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5153 // CHECK4-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 5154 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5155 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5156 // CHECK4-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 5157 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 5158 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5159 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 5160 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 5161 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5162 // CHECK4-NEXT: store i8* null, i8** [[TMP5]], align 4 5163 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5164 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5165 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5166 // CHECK4-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 5167 // CHECK4-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5168 // CHECK4: omp_offload.failed: 5169 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 5170 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5171 // CHECK4: omp_offload.cont: 5172 // CHECK4-NEXT: ret void 5173 // 5174 // 5175 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 5176 // CHECK4-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 5177 // CHECK4-NEXT: entry: 5178 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5179 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5180 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5181 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 5182 // CHECK4-NEXT: ret void 5183 // 5184 // 5185 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..20 5186 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 5187 // CHECK4-NEXT: entry: 5188 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5189 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5190 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5191 // CHECK4-NEXT: [[F:%.*]] = alloca i32*, align 4 5192 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5193 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5194 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5195 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5196 // CHECK4-NEXT: ret void 5197 // 5198 // 5199 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari 5200 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5201 // CHECK4-NEXT: entry: 5202 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5203 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 5204 // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 5205 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5206 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 5207 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5208 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 5209 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5210 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5211 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5212 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5213 // CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 5214 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5215 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5216 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5217 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5218 // CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 5219 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5220 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5221 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5222 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 5223 // CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 5224 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 5225 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 5226 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 5227 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 5228 // CHECK4-NEXT: ret i32 [[TMP8]] 5229 // 5230 // 5231 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5232 // CHECK4-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5233 // CHECK4-NEXT: entry: 5234 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5235 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5236 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 5237 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5238 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5239 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5240 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 5241 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 5242 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 5243 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 5244 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5245 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5246 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5247 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5248 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5249 // CHECK4-NEXT: store i32 [[ADD]], i32* [[B]], align 4 5250 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5251 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 5252 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 5253 // CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 5254 // CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 5255 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5256 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 5257 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 5258 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 5259 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 5260 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 5261 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5262 // CHECK4: omp_if.then: 5263 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5264 // CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 5265 // CHECK4-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 5266 // CHECK4-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 5267 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 5268 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i32 40, i1 false) 5269 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5270 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 5271 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 5272 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5273 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 5274 // CHECK4-NEXT: store double* [[A]], double** [[TMP14]], align 4 5275 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5276 // CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4 5277 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5278 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 5279 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 5280 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5281 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 5282 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 5283 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5284 // CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4 5285 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5286 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 5287 // CHECK4-NEXT: store i32 2, i32* [[TMP22]], align 4 5288 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5289 // CHECK4-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 5290 // CHECK4-NEXT: store i32 2, i32* [[TMP24]], align 4 5291 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5292 // CHECK4-NEXT: store i8* null, i8** [[TMP25]], align 4 5293 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5294 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 5295 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 5296 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5297 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 5298 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 5299 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5300 // CHECK4-NEXT: store i8* null, i8** [[TMP30]], align 4 5301 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 5302 // CHECK4-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 5303 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 5304 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 5305 // CHECK4-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 5306 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 5307 // CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 5308 // CHECK4-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 5309 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 5310 // CHECK4-NEXT: store i8* null, i8** [[TMP36]], align 4 5311 // CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5312 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5313 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5314 // CHECK4-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5315 // CHECK4-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 5316 // CHECK4-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5317 // CHECK4: omp_offload.failed: 5318 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 5319 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5320 // CHECK4: omp_offload.cont: 5321 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 5322 // CHECK4: omp_if.else: 5323 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 5324 // CHECK4-NEXT: br label [[OMP_IF_END]] 5325 // CHECK4: omp_if.end: 5326 // CHECK4-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 5327 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 5328 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5329 // CHECK4-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 5330 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 5331 // CHECK4-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 5332 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 5333 // CHECK4-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5334 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 5335 // CHECK4-NEXT: ret i32 [[ADD3]] 5336 // 5337 // 5338 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici 5339 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5340 // CHECK4-NEXT: entry: 5341 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5342 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 5343 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 5344 // CHECK4-NEXT: [[AAA:%.*]] = alloca i8, align 1 5345 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 5346 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5347 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5348 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5349 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 5350 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 5351 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 5352 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5353 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 5354 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 5355 // CHECK4-NEXT: store i8 0, i8* [[AAA]], align 1 5356 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 5357 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5358 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5359 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 5360 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5361 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 5362 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5363 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 5364 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 5365 // CHECK4-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 5366 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 5367 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 5368 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 5369 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5370 // CHECK4: omp_if.then: 5371 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5372 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 5373 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 5374 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5375 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 5376 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 5377 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5378 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4 5379 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5380 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 5381 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 5382 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5383 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 5384 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 5385 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5386 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4 5387 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5388 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 5389 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 5390 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5391 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 5392 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 5393 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5394 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 5395 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 5396 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 5397 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 5398 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 5399 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 5400 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 5401 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 5402 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4 5403 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5404 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5405 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5406 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 5407 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5408 // CHECK4: omp_offload.failed: 5409 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 5410 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5411 // CHECK4: omp_offload.cont: 5412 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 5413 // CHECK4: omp_if.else: 5414 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 5415 // CHECK4-NEXT: br label [[OMP_IF_END]] 5416 // CHECK4: omp_if.end: 5417 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 5418 // CHECK4-NEXT: ret i32 [[TMP31]] 5419 // 5420 // 5421 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5422 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 5423 // CHECK4-NEXT: entry: 5424 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5425 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 5426 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 5427 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 5428 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5429 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5430 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 5431 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 5432 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 5433 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5434 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 5435 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 5436 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 5437 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5438 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5439 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 5440 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5441 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 5442 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5443 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5444 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 5445 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5446 // CHECK4: omp_if.then: 5447 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5448 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 5449 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 5450 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5451 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 5452 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 5453 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5454 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4 5455 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5456 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 5457 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 5458 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5459 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 5460 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 5461 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5462 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4 5463 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5464 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 5465 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 5466 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5467 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 5468 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 5469 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5470 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 5471 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5472 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5473 // CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 5474 // CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 5475 // CHECK4-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5476 // CHECK4: omp_offload.failed: 5477 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 5478 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 5479 // CHECK4: omp_offload.cont: 5480 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 5481 // CHECK4: omp_if.else: 5482 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 5483 // CHECK4-NEXT: br label [[OMP_IF_END]] 5484 // CHECK4: omp_if.end: 5485 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 5486 // CHECK4-NEXT: ret i32 [[TMP24]] 5487 // 5488 // 5489 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 5490 // CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 5491 // CHECK4-NEXT: entry: 5492 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5493 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5494 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5495 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5496 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5497 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5498 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5499 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5500 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5501 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5502 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5503 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5504 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5505 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5506 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5507 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5508 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 5509 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 5510 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 5511 // CHECK4-NEXT: ret void 5512 // 5513 // 5514 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..23 5515 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 5516 // CHECK4-NEXT: entry: 5517 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5518 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5519 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5520 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5521 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5522 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5523 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5524 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5525 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5526 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5527 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5528 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5529 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5530 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5531 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5532 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5533 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5534 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5535 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5536 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 5537 // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5538 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5539 // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4 5540 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5541 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 5542 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 5543 // CHECK4-NEXT: store double [[INC]], double* [[A3]], align 4 5544 // CHECK4-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 5545 // CHECK4-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 5546 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 5547 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5548 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 5549 // CHECK4-NEXT: ret void 5550 // 5551 // 5552 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 5553 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5554 // CHECK4-NEXT: entry: 5555 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5556 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5557 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5558 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5559 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5560 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5561 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5562 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5563 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5564 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5565 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5566 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5567 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5568 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5569 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5570 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5571 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5572 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5573 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5574 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 5575 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5576 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 5577 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 5578 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 5579 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 5580 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 5581 // CHECK4-NEXT: ret void 5582 // 5583 // 5584 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..26 5585 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5586 // CHECK4-NEXT: entry: 5587 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5588 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5589 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5590 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5591 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5592 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5593 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5594 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5595 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5596 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5597 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5598 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5599 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5600 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5601 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5602 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5603 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5604 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5605 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5606 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 5607 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 5608 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5609 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 5610 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 5611 // CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 5612 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 5613 // CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 5614 // CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 5615 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5616 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5617 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 5618 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 5619 // CHECK4-NEXT: ret void 5620 // 5621 // 5622 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 5623 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5624 // CHECK4-NEXT: entry: 5625 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5626 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5627 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5628 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5629 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5630 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5631 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5632 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5633 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5634 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5635 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5636 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5637 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5638 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5639 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5640 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5641 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5642 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5643 // CHECK4-NEXT: ret void 5644 // 5645 // 5646 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..29 5647 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5648 // CHECK4-NEXT: entry: 5649 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5650 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5651 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5652 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5653 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5654 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5655 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5656 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5657 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5658 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5659 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5660 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5661 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5662 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5663 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5664 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5665 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 5666 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5667 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5668 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 5669 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5670 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5671 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 5672 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 5673 // CHECK4-NEXT: ret void 5674 // 5675 // 5676 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5677 // CHECK4-SAME: () #[[ATTR4]] { 5678 // CHECK4-NEXT: entry: 5679 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 5680 // CHECK4-NEXT: ret void 5681 // 5682 // 5683 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 5684 // CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 5685 // CHECK9-NEXT: entry: 5686 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5687 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5688 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 5689 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5690 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 5691 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5692 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5693 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 5694 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5695 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5696 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 5697 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 5698 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 5699 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 5700 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5701 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5702 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 5703 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5704 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 5705 // CHECK9-NEXT: ret void 5706 // 5707 // 5708 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 5709 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 5710 // CHECK9-NEXT: entry: 5711 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5712 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5713 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5714 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5715 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5716 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5717 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5718 // CHECK9-NEXT: ret void 5719 // 5720 // 5721 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 5722 // CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 5723 // CHECK9-NEXT: entry: 5724 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5725 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5726 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5727 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5728 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5729 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5730 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 5731 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5732 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 5733 // CHECK9-NEXT: ret void 5734 // 5735 // 5736 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 5737 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 5738 // CHECK9-NEXT: entry: 5739 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5740 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5741 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5742 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5743 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5744 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5745 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5746 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5747 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 5748 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 5749 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 5750 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 5751 // CHECK9-NEXT: ret void 5752 // 5753 // 5754 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 5755 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 5756 // CHECK9-NEXT: entry: 5757 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5758 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5759 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5760 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5761 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5762 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5763 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5764 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5765 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 5766 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5767 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 5768 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 5769 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 5770 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5771 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 5772 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5773 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 5774 // CHECK9-NEXT: ret void 5775 // 5776 // 5777 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 5778 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 5779 // CHECK9-NEXT: entry: 5780 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5781 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5782 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5783 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5784 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5785 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5786 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5787 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5788 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5789 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5790 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 5791 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5792 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 5793 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 5794 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 5795 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 5796 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5797 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 5798 // CHECK9-NEXT: ret void 5799 // 5800 // 5801 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 5802 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 5803 // CHECK9-NEXT: entry: 5804 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5805 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 5806 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5807 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 5808 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 5809 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5810 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 5811 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 5812 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 5813 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5814 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5815 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 5816 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5817 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 5818 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 5819 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5820 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 5821 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 5822 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 5823 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5824 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 5825 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5826 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 5827 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 5828 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5829 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 5830 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 5831 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 5832 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 5833 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5834 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 5835 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 5836 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 5837 // CHECK9-NEXT: ret void 5838 // 5839 // 5840 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 5841 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 5842 // CHECK9-NEXT: entry: 5843 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5844 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5845 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5846 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 5847 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5848 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 5849 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 5850 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5851 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 5852 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 5853 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 5854 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5855 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5856 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5857 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 5858 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5859 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 5860 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 5861 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5862 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 5863 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 5864 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 5865 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5866 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 5867 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5868 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 5869 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 5870 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5871 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 5872 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 5873 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 5874 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 5875 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 5876 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 5877 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 5878 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 5879 // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 5880 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 5881 // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 5882 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 5883 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 5884 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 5885 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 5886 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 5887 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 5888 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 5889 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 5890 // CHECK9-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 5891 // CHECK9-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 5892 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 5893 // CHECK9-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 5894 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 5895 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 5896 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 5897 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 5898 // CHECK9-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 5899 // CHECK9-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 5900 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 5901 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 5902 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 5903 // CHECK9-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 5904 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 5905 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 5906 // CHECK9-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 5907 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 5908 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 5909 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 5910 // CHECK9-NEXT: ret void 5911 // 5912 // 5913 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 5914 // CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 5915 // CHECK9-NEXT: entry: 5916 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 5917 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 5918 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 5919 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 5920 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 5921 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 5922 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 5923 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 5924 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 5925 // CHECK9-NEXT: ret void 5926 // 5927 // 5928 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 5929 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 5930 // CHECK9-NEXT: entry: 5931 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5932 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5933 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 5934 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 5935 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5936 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5937 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 5938 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 5939 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 5940 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 5941 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 5942 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 5943 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 5944 // CHECK9-NEXT: ret void 5945 // 5946 // 5947 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 5948 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 5949 // CHECK9-NEXT: entry: 5950 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5951 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5952 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 5953 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5954 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5955 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 5956 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 5957 // CHECK9-NEXT: ret void 5958 // 5959 // 5960 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 5961 // CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 5962 // CHECK9-NEXT: entry: 5963 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 5964 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 5965 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 5966 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 5967 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 5968 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 5969 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 5970 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 5971 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 5972 // CHECK9-NEXT: ret void 5973 // 5974 // 5975 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 5976 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 5977 // CHECK9-NEXT: entry: 5978 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5979 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5980 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 5981 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5982 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5983 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 5984 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 5985 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 5986 // CHECK9-NEXT: ret void 5987 // 5988 // 5989 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 5990 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 5991 // CHECK9-NEXT: entry: 5992 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5993 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5994 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 5995 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5996 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5997 // CHECK9-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 5998 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 5999 // CHECK9-NEXT: ret void 6000 // 6001 // 6002 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 6003 // CHECK9-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 6004 // CHECK9-NEXT: entry: 6005 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6006 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6007 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6008 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 6009 // CHECK9-NEXT: ret void 6010 // 6011 // 6012 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 6013 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 6014 // CHECK9-NEXT: entry: 6015 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6016 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6017 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6018 // CHECK9-NEXT: [[F:%.*]] = alloca i32*, align 8 6019 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6020 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6021 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6022 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6023 // CHECK9-NEXT: ret void 6024 // 6025 // 6026 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 6027 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 6028 // CHECK9-NEXT: entry: 6029 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6030 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6031 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6032 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6033 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6034 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6035 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 6036 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6037 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6038 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6039 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6040 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6041 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6042 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6043 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6044 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6045 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6046 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 6047 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6048 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6049 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6050 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 6051 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6052 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 6053 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 6054 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 6055 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 6056 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 6057 // CHECK9-NEXT: ret void 6058 // 6059 // 6060 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 6061 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 6062 // CHECK9-NEXT: entry: 6063 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6064 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6065 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6066 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6067 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6068 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6069 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6070 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6071 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6072 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6073 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6074 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6075 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6076 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6077 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6078 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6079 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6080 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 6081 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6082 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6083 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 6084 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6085 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6086 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 6087 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 6088 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 6089 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 6090 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 6091 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 6092 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 6093 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6094 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 6095 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 6096 // CHECK9-NEXT: ret void 6097 // 6098 // 6099 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 6100 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 6101 // CHECK9-NEXT: entry: 6102 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6103 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6104 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6105 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6106 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6107 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 6108 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6109 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6110 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6111 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6112 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6113 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6114 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6115 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6116 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6117 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6118 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 6119 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 6120 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 6121 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 6122 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 6123 // CHECK9-NEXT: ret void 6124 // 6125 // 6126 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 6127 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 6128 // CHECK9-NEXT: entry: 6129 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6130 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6131 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6132 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6133 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6134 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6135 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6136 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6137 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6138 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6139 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6140 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6141 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6142 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6143 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6144 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6145 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6146 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6147 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6148 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 6149 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 6150 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 6151 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6152 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 6153 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6154 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 6155 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 6156 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 6157 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 6158 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 6159 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 6160 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 6161 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 6162 // CHECK9-NEXT: ret void 6163 // 6164 // 6165 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 6166 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 6167 // CHECK9-NEXT: entry: 6168 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6169 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6170 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6171 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6172 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6173 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6174 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6175 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6176 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6177 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6178 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6179 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6180 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6181 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 6182 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6183 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6184 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6185 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 6186 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6187 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 6188 // CHECK9-NEXT: ret void 6189 // 6190 // 6191 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 6192 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 6193 // CHECK9-NEXT: entry: 6194 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6195 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6196 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6197 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6198 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6199 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6200 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6201 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6202 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6203 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6204 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6205 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6206 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6207 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6208 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 6209 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6210 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6211 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 6212 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 6213 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6214 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 6215 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 6216 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6217 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 6218 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 6219 // CHECK9-NEXT: ret void 6220 // 6221 // 6222 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 6223 // CHECK10-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 6224 // CHECK10-NEXT: entry: 6225 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6226 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 6227 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 6228 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6229 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 6230 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6231 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 6232 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 6233 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6234 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 6235 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 6236 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 6237 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 6238 // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 6239 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 6240 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6241 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 6242 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6243 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 6244 // CHECK10-NEXT: ret void 6245 // 6246 // 6247 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 6248 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 6249 // CHECK10-NEXT: entry: 6250 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6251 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6252 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6253 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6254 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6255 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6256 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6257 // CHECK10-NEXT: ret void 6258 // 6259 // 6260 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 6261 // CHECK10-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 6262 // CHECK10-NEXT: entry: 6263 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6264 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6265 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6266 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6267 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6268 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6269 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 6270 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6271 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6272 // CHECK10-NEXT: ret void 6273 // 6274 // 6275 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 6276 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 6277 // CHECK10-NEXT: entry: 6278 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6279 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6280 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6281 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6282 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6283 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6284 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6285 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6286 // CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 6287 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 6288 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 6289 // CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 6290 // CHECK10-NEXT: ret void 6291 // 6292 // 6293 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 6294 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 6295 // CHECK10-NEXT: entry: 6296 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6297 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6298 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6299 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6300 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6301 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6302 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6303 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6304 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6305 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6306 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 6307 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6308 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6309 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6310 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 6311 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6312 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 6313 // CHECK10-NEXT: ret void 6314 // 6315 // 6316 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 6317 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 6318 // CHECK10-NEXT: entry: 6319 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6320 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6321 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6322 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6323 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6324 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6325 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6326 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6327 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6328 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6329 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6330 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6331 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6332 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 6333 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 6334 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 6335 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6336 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 6337 // CHECK10-NEXT: ret void 6338 // 6339 // 6340 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 6341 // CHECK10-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 6342 // CHECK10-NEXT: entry: 6343 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6344 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 6345 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6346 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 6347 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 6348 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6349 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 6350 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 6351 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 6352 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6353 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6354 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 6355 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6356 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 6357 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 6358 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6359 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 6360 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 6361 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 6362 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6363 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 6364 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6365 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 6366 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 6367 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6368 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 6369 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 6370 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 6371 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 6372 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6373 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 6374 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 6375 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 6376 // CHECK10-NEXT: ret void 6377 // 6378 // 6379 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 6380 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 6381 // CHECK10-NEXT: entry: 6382 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6383 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6384 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6385 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 6386 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6387 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 6388 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 6389 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6390 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 6391 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 6392 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 6393 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6394 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6395 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6396 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 6397 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6398 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 6399 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 6400 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6401 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 6402 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 6403 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 6404 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6405 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 6406 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6407 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 6408 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 6409 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6410 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 6411 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 6412 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 6413 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 6414 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 6415 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6416 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 6417 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 6418 // CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 6419 // CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 6420 // CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 6421 // CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 6422 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 6423 // CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 6424 // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 6425 // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 6426 // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 6427 // CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 6428 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 6429 // CHECK10-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 6430 // CHECK10-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 6431 // CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 6432 // CHECK10-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 6433 // CHECK10-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 6434 // CHECK10-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 6435 // CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 6436 // CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 6437 // CHECK10-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 6438 // CHECK10-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 6439 // CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6440 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 6441 // CHECK10-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 6442 // CHECK10-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 6443 // CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6444 // CHECK10-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 6445 // CHECK10-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 6446 // CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 6447 // CHECK10-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 6448 // CHECK10-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 6449 // CHECK10-NEXT: ret void 6450 // 6451 // 6452 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 6453 // CHECK10-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 6454 // CHECK10-NEXT: entry: 6455 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 6456 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 6457 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 6458 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 6459 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6460 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 6461 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 6462 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 6463 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6464 // CHECK10-NEXT: ret void 6465 // 6466 // 6467 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 6468 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 6469 // CHECK10-NEXT: entry: 6470 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6471 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6472 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 6473 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 6474 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6475 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6476 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 6477 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 6478 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6479 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 6480 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 6481 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 6482 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6483 // CHECK10-NEXT: ret void 6484 // 6485 // 6486 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 6487 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 6488 // CHECK10-NEXT: entry: 6489 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6490 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6491 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 6492 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6493 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6494 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 6495 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 6496 // CHECK10-NEXT: ret void 6497 // 6498 // 6499 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 6500 // CHECK10-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 6501 // CHECK10-NEXT: entry: 6502 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 6503 // CHECK10-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 6504 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 6505 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 6506 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6507 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 6508 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 6509 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 6510 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6511 // CHECK10-NEXT: ret void 6512 // 6513 // 6514 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 6515 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 6516 // CHECK10-NEXT: entry: 6517 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6518 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6519 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 6520 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6521 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6522 // CHECK10-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 6523 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 6524 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 6525 // CHECK10-NEXT: ret void 6526 // 6527 // 6528 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..7 6529 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 6530 // CHECK10-NEXT: entry: 6531 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6532 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6533 // CHECK10-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 6534 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6535 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6536 // CHECK10-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 6537 // CHECK10-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 6538 // CHECK10-NEXT: ret void 6539 // 6540 // 6541 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 6542 // CHECK10-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 6543 // CHECK10-NEXT: entry: 6544 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6545 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6546 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6547 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 6548 // CHECK10-NEXT: ret void 6549 // 6550 // 6551 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..8 6552 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 6553 // CHECK10-NEXT: entry: 6554 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6555 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6556 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6557 // CHECK10-NEXT: [[F:%.*]] = alloca i32*, align 8 6558 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6559 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6560 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6561 // CHECK10-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6562 // CHECK10-NEXT: ret void 6563 // 6564 // 6565 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 6566 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 6567 // CHECK10-NEXT: entry: 6568 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6569 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6570 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6571 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6572 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6573 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6574 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 6575 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6576 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6577 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6578 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6579 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6580 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6581 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6582 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6583 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6584 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6585 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 6586 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6587 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6588 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6589 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 6590 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6591 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 6592 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 6593 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 6594 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 6595 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 6596 // CHECK10-NEXT: ret void 6597 // 6598 // 6599 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..9 6600 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 6601 // CHECK10-NEXT: entry: 6602 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6603 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6604 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6605 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6606 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6607 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6608 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6609 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6610 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6611 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6612 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6613 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6614 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6615 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6616 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6617 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6618 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6619 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 6620 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6621 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6622 // CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 6623 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6624 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6625 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 6626 // CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 6627 // CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 6628 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 6629 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 6630 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 6631 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 6632 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6633 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 6634 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 6635 // CHECK10-NEXT: ret void 6636 // 6637 // 6638 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 6639 // CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 6640 // CHECK10-NEXT: entry: 6641 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6642 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6643 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6644 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6645 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6646 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 6647 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6648 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6649 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6650 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6651 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6652 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6653 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6654 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6655 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6656 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6657 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 6658 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 6659 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 6660 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 6661 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 6662 // CHECK10-NEXT: ret void 6663 // 6664 // 6665 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..10 6666 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 6667 // CHECK10-NEXT: entry: 6668 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6669 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6670 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6671 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6672 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6673 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6674 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6675 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6676 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6677 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6678 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6679 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6680 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6681 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6682 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6683 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6684 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6685 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6686 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6687 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 6688 // CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 6689 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 6690 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6691 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 6692 // CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6693 // CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 6694 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 6695 // CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8 6696 // CHECK10-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 6697 // CHECK10-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 6698 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 6699 // CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 6700 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 6701 // CHECK10-NEXT: ret void 6702 // 6703 // 6704 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 6705 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 6706 // CHECK10-NEXT: entry: 6707 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6708 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6709 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6710 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6711 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6712 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6713 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6714 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6715 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6716 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6717 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6718 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6719 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6720 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 6721 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6722 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6723 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6724 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 6725 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6726 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 6727 // CHECK10-NEXT: ret void 6728 // 6729 // 6730 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..11 6731 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 6732 // CHECK10-NEXT: entry: 6733 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6734 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6735 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6736 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6737 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6738 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6739 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6740 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6741 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6742 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6743 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6744 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6745 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6746 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6747 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 6748 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6749 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6750 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 6751 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 6752 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6753 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 6754 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 6755 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6756 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 6757 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 6758 // CHECK10-NEXT: ret void 6759 // 6760 // 6761 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 6762 // CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 6763 // CHECK11-NEXT: entry: 6764 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6765 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6766 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 6767 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6768 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 6769 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6770 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6771 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 6772 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6773 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6774 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 6775 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 6776 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 6777 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6778 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 6779 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6780 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 6781 // CHECK11-NEXT: ret void 6782 // 6783 // 6784 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 6785 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 6786 // CHECK11-NEXT: entry: 6787 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6788 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6789 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6790 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6791 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6792 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6793 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6794 // CHECK11-NEXT: ret void 6795 // 6796 // 6797 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 6798 // CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 6799 // CHECK11-NEXT: entry: 6800 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6801 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6802 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6803 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6804 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6805 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6806 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 6807 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6808 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 6809 // CHECK11-NEXT: ret void 6810 // 6811 // 6812 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 6813 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 6814 // CHECK11-NEXT: entry: 6815 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6816 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6817 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6818 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6819 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6820 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6821 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6822 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6823 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 6824 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 6825 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 6826 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 6827 // CHECK11-NEXT: ret void 6828 // 6829 // 6830 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 6831 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 6832 // CHECK11-NEXT: entry: 6833 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6834 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6835 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6836 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6837 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6838 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6839 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6840 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 6841 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6842 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6843 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 6844 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6845 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 6846 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6847 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 6848 // CHECK11-NEXT: ret void 6849 // 6850 // 6851 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 6852 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 6853 // CHECK11-NEXT: entry: 6854 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6855 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6856 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6857 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6858 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6859 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6860 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6861 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6862 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6863 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 6864 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6865 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 6866 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 6867 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 6868 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 6869 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 6870 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 6871 // CHECK11-NEXT: ret void 6872 // 6873 // 6874 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 6875 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 6876 // CHECK11-NEXT: entry: 6877 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6878 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 6879 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6880 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 6881 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 6882 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6883 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6884 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 6885 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 6886 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6887 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6888 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 6889 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6890 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 6891 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 6892 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6893 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 6894 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 6895 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 6896 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 6897 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6898 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 6899 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 6900 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6901 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 6902 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 6903 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 6904 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 6905 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 6906 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 6907 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 6908 // CHECK11-NEXT: ret void 6909 // 6910 // 6911 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 6912 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 6913 // CHECK11-NEXT: entry: 6914 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6915 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6916 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6917 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 6918 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6919 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 6920 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 6921 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6922 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6923 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 6924 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 6925 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6926 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6927 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6928 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 6929 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6930 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 6931 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 6932 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6933 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 6934 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 6935 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 6936 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 6937 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6938 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 6939 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 6940 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6941 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 6942 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 6943 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 6944 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 6945 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 6946 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 6947 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 6948 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 6949 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 6950 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 6951 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 6952 // CHECK11-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 6953 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 6954 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 6955 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 6956 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 6957 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 6958 // CHECK11-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 6959 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 6960 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 6961 // CHECK11-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 6962 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 6963 // CHECK11-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 6964 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 6965 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 6966 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 6967 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 6968 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 6969 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 6970 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6971 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 6972 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 6973 // CHECK11-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 6974 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6975 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 6976 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 6977 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 6978 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 6979 // CHECK11-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 6980 // CHECK11-NEXT: ret void 6981 // 6982 // 6983 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 6984 // CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 6985 // CHECK11-NEXT: entry: 6986 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 6987 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 6988 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 6989 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 6990 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 6991 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 6992 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 6993 // CHECK11-NEXT: ret void 6994 // 6995 // 6996 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 6997 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 6998 // CHECK11-NEXT: entry: 6999 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7000 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7001 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 7002 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 7003 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7004 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7005 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 7006 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 7007 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 7008 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 7009 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 7010 // CHECK11-NEXT: ret void 7011 // 7012 // 7013 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 7014 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 7015 // CHECK11-NEXT: entry: 7016 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7017 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7018 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 7019 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7020 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7021 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 7022 // CHECK11-NEXT: ret void 7023 // 7024 // 7025 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 7026 // CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 7027 // CHECK11-NEXT: entry: 7028 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 7029 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 7030 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 7031 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 7032 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 7033 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 7034 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 7035 // CHECK11-NEXT: ret void 7036 // 7037 // 7038 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 7039 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 7040 // CHECK11-NEXT: entry: 7041 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7042 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7043 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 7044 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7045 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7046 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 7047 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 7048 // CHECK11-NEXT: ret void 7049 // 7050 // 7051 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 7052 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 7053 // CHECK11-NEXT: entry: 7054 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7055 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7056 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 7057 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7058 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7059 // CHECK11-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 7060 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 7061 // CHECK11-NEXT: ret void 7062 // 7063 // 7064 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 7065 // CHECK11-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 7066 // CHECK11-NEXT: entry: 7067 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7068 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7069 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7070 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 7071 // CHECK11-NEXT: ret void 7072 // 7073 // 7074 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 7075 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 7076 // CHECK11-NEXT: entry: 7077 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7078 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7079 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7080 // CHECK11-NEXT: [[F:%.*]] = alloca i32*, align 4 7081 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7082 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7083 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7084 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7085 // CHECK11-NEXT: ret void 7086 // 7087 // 7088 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 7089 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7090 // CHECK11-NEXT: entry: 7091 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7092 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7093 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 7094 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7095 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7096 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7097 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 7098 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7099 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7100 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 7101 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7102 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7103 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 7104 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7105 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7106 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 7107 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 7108 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 7109 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7110 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 7111 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7112 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 7113 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 7114 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 7115 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 7116 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 7117 // CHECK11-NEXT: ret void 7118 // 7119 // 7120 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 7121 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7122 // CHECK11-NEXT: entry: 7123 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7124 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7125 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7126 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7127 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 7128 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7129 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7130 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7131 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7132 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7133 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 7134 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7135 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7136 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 7137 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7138 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7139 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7140 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 7141 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 7142 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 7143 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 7144 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 7145 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 7146 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 7147 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 7148 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 7149 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 7150 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 7151 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 7152 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7153 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 7154 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 7155 // CHECK11-NEXT: ret void 7156 // 7157 // 7158 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 7159 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7160 // CHECK11-NEXT: entry: 7161 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 7162 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 7163 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7164 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7165 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 7166 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 7167 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 7168 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 7169 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7170 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7171 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 7172 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 7173 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7174 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7175 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 7176 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 7177 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 7178 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 7179 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 7180 // CHECK11-NEXT: ret void 7181 // 7182 // 7183 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 7184 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7185 // CHECK11-NEXT: entry: 7186 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7187 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7188 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 7189 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 7190 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7191 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7192 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 7193 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7194 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7195 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 7196 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 7197 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7198 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7199 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 7200 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 7201 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7202 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7203 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 7204 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 7205 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 7206 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 7207 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 7208 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 7209 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 7210 // CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 7211 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 7212 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 7213 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7214 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 7215 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 7216 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 7217 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 7218 // CHECK11-NEXT: ret void 7219 // 7220 // 7221 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 7222 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7223 // CHECK11-NEXT: entry: 7224 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7225 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7226 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7227 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7228 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7229 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7230 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7231 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7232 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7233 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7234 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7235 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 7236 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 7237 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 7238 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7239 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 7240 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7241 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 7242 // CHECK11-NEXT: ret void 7243 // 7244 // 7245 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 7246 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7247 // CHECK11-NEXT: entry: 7248 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7249 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7250 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7251 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7252 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7253 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7254 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7255 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7256 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7257 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7258 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7259 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7260 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7261 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7262 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 7263 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 7264 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 7265 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 7266 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7267 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 7268 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 7269 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7270 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 7271 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 7272 // CHECK11-NEXT: ret void 7273 // 7274 // 7275 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 7276 // CHECK12-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 7277 // CHECK12-NEXT: entry: 7278 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7279 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 7280 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 7281 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7282 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 7283 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7284 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 7285 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 7286 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7287 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 7288 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 7289 // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 7290 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 7291 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7292 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 7293 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7294 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 7295 // CHECK12-NEXT: ret void 7296 // 7297 // 7298 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 7299 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 7300 // CHECK12-NEXT: entry: 7301 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7302 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7303 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7304 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7305 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7306 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7307 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7308 // CHECK12-NEXT: ret void 7309 // 7310 // 7311 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 7312 // CHECK12-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 7313 // CHECK12-NEXT: entry: 7314 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7315 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7316 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7317 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7318 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 7319 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7320 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 7321 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7322 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 7323 // CHECK12-NEXT: ret void 7324 // 7325 // 7326 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 7327 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 7328 // CHECK12-NEXT: entry: 7329 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7330 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7331 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7332 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7333 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7334 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7335 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7336 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 7337 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 7338 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 7339 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 7340 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 7341 // CHECK12-NEXT: ret void 7342 // 7343 // 7344 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 7345 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 7346 // CHECK12-NEXT: entry: 7347 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7348 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7349 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7350 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7351 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7352 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7353 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7354 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 7355 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 7356 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 7357 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 7358 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7359 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 7360 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7361 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 7362 // CHECK12-NEXT: ret void 7363 // 7364 // 7365 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 7366 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 7367 // CHECK12-NEXT: entry: 7368 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7369 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7370 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7371 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7372 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7373 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7374 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7375 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7376 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7377 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 7378 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7379 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 7380 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 7381 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 7382 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 7383 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7384 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 7385 // CHECK12-NEXT: ret void 7386 // 7387 // 7388 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 7389 // CHECK12-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 7390 // CHECK12-NEXT: entry: 7391 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7392 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 7393 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7394 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 7395 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 7396 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7397 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 7398 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 7399 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 7400 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7401 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7402 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 7403 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7404 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 7405 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 7406 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7407 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 7408 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 7409 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 7410 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 7411 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7412 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 7413 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 7414 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7415 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 7416 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 7417 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 7418 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 7419 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 7420 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 7421 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 7422 // CHECK12-NEXT: ret void 7423 // 7424 // 7425 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 7426 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 7427 // CHECK12-NEXT: entry: 7428 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7429 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7430 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7431 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 7432 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7433 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 7434 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 7435 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7436 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 7437 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 7438 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 7439 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7440 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7441 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7442 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 7443 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7444 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 7445 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 7446 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7447 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 7448 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 7449 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 7450 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 7451 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7452 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 7453 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 7454 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7455 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 7456 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 7457 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 7458 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 7459 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 7460 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 7461 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 7462 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 7463 // CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 7464 // CHECK12-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 7465 // CHECK12-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 7466 // CHECK12-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 7467 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 7468 // CHECK12-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 7469 // CHECK12-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 7470 // CHECK12-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 7471 // CHECK12-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 7472 // CHECK12-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 7473 // CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 7474 // CHECK12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 7475 // CHECK12-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 7476 // CHECK12-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 7477 // CHECK12-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 7478 // CHECK12-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 7479 // CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 7480 // CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 7481 // CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 7482 // CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 7483 // CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 7484 // CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 7485 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 7486 // CHECK12-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 7487 // CHECK12-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 7488 // CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 7489 // CHECK12-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 7490 // CHECK12-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 7491 // CHECK12-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 7492 // CHECK12-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 7493 // CHECK12-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 7494 // CHECK12-NEXT: ret void 7495 // 7496 // 7497 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 7498 // CHECK12-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 7499 // CHECK12-NEXT: entry: 7500 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 7501 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 7502 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 7503 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 7504 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 7505 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 7506 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 7507 // CHECK12-NEXT: ret void 7508 // 7509 // 7510 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 7511 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 7512 // CHECK12-NEXT: entry: 7513 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7514 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7515 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 7516 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 7517 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7518 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7519 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 7520 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 7521 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 7522 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 7523 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 7524 // CHECK12-NEXT: ret void 7525 // 7526 // 7527 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 7528 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 7529 // CHECK12-NEXT: entry: 7530 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7531 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7532 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 7533 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7534 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7535 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 7536 // CHECK12-NEXT: ret void 7537 // 7538 // 7539 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 7540 // CHECK12-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 7541 // CHECK12-NEXT: entry: 7542 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 7543 // CHECK12-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 7544 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 7545 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 7546 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 7547 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 7548 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 7549 // CHECK12-NEXT: ret void 7550 // 7551 // 7552 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 7553 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 7554 // CHECK12-NEXT: entry: 7555 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7556 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7557 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 7558 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7559 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7560 // CHECK12-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 7561 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 7562 // CHECK12-NEXT: ret void 7563 // 7564 // 7565 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..7 7566 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 7567 // CHECK12-NEXT: entry: 7568 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7569 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7570 // CHECK12-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 7571 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7572 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7573 // CHECK12-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 7574 // CHECK12-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 7575 // CHECK12-NEXT: ret void 7576 // 7577 // 7578 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 7579 // CHECK12-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 7580 // CHECK12-NEXT: entry: 7581 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7582 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7583 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7584 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 7585 // CHECK12-NEXT: ret void 7586 // 7587 // 7588 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..8 7589 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 7590 // CHECK12-NEXT: entry: 7591 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7592 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7593 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7594 // CHECK12-NEXT: [[F:%.*]] = alloca i32*, align 4 7595 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7596 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7597 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7598 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7599 // CHECK12-NEXT: ret void 7600 // 7601 // 7602 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 7603 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7604 // CHECK12-NEXT: entry: 7605 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7606 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7607 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 7608 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7609 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7610 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7611 // CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 7612 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7613 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7614 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 7615 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7616 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7617 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 7618 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7619 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7620 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 7621 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 7622 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 7623 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7624 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 7625 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7626 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 7627 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 7628 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 7629 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 7630 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 7631 // CHECK12-NEXT: ret void 7632 // 7633 // 7634 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..9 7635 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7636 // CHECK12-NEXT: entry: 7637 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7638 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7639 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7640 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7641 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 7642 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7643 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7644 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7645 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7646 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7647 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 7648 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7649 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7650 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 7651 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7652 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7653 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7654 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 7655 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 7656 // CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 7657 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 7658 // CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 7659 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 7660 // CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 7661 // CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 7662 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 7663 // CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 7664 // CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 7665 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 7666 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7667 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 7668 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 7669 // CHECK12-NEXT: ret void 7670 // 7671 // 7672 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 7673 // CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7674 // CHECK12-NEXT: entry: 7675 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 7676 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 7677 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7678 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7679 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 7680 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 7681 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 7682 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 7683 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7684 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7685 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 7686 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 7687 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7688 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7689 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 7690 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 7691 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 7692 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 7693 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 7694 // CHECK12-NEXT: ret void 7695 // 7696 // 7697 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..10 7698 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 7699 // CHECK12-NEXT: entry: 7700 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7701 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7702 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 7703 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 7704 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 7705 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 7706 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 7707 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7708 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7709 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 7710 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 7711 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 7712 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 7713 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 7714 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 7715 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 7716 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 7717 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 7718 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 7719 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 7720 // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 7721 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 7722 // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 7723 // CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 7724 // CHECK12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 7725 // CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 7726 // CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4 7727 // CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7728 // CHECK12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 7729 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 7730 // CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 7731 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 7732 // CHECK12-NEXT: ret void 7733 // 7734 // 7735 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 7736 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7737 // CHECK12-NEXT: entry: 7738 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7739 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7740 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7741 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7742 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7743 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7744 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7745 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7746 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7747 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7748 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7749 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 7750 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 7751 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 7752 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7753 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 7754 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7755 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 7756 // CHECK12-NEXT: ret void 7757 // 7758 // 7759 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..11 7760 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 7761 // CHECK12-NEXT: entry: 7762 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7763 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7764 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7765 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7766 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7767 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7768 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7769 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7770 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7771 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7772 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7773 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7774 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7775 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7776 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 7777 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 7778 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 7779 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 7780 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7781 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 7782 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 7783 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7784 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 7785 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 7786 // CHECK12-NEXT: ret void 7787 // 7788 // 7789 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi 7790 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 7791 // CHECK17-NEXT: entry: 7792 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7793 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 7794 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 7795 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7796 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7797 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7798 // CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7799 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7800 // CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7801 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7802 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 7803 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7804 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 7805 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 7806 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 7807 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 7808 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 7809 // CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 7810 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7811 // CHECK17-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 7812 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 7813 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 7814 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 7815 // CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 7816 // CHECK17-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 7817 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 7818 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 7819 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 7820 // CHECK17-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 7821 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 7822 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 7823 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 7824 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 7825 // CHECK17-NEXT: [[NN:%.*]] = alloca i32, align 4 7826 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 7827 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 7828 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 7829 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 7830 // CHECK17-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 7831 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 7832 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 7833 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 7834 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 7835 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7836 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 7837 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 7838 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7839 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7840 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 7841 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 7842 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 7843 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 7844 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7845 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 7846 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 7847 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 7848 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 7849 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7850 // CHECK17-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 7851 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7852 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 7853 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 7854 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7855 // CHECK17-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 7856 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7857 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7858 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 7859 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 7860 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 7861 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 7862 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 7863 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 7864 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 7865 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7866 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 7867 // CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 7868 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7869 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 7870 // CHECK17-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 7871 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 7872 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 7873 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7874 // CHECK17-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 7875 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 7876 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7877 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 7878 // CHECK17-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 7879 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 7880 // CHECK17-NEXT: store i8* null, i8** [[TMP24]], align 8 7881 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7882 // CHECK17-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 7883 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 7884 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7885 // CHECK17-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 7886 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 7887 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 7888 // CHECK17-NEXT: store i8* null, i8** [[TMP29]], align 8 7889 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7890 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7891 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 7892 // CHECK17-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 7893 // CHECK17-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 7894 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 7895 // CHECK17-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 7896 // CHECK17-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 7897 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 7898 // CHECK17-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 7899 // CHECK17-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 7900 // CHECK17-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 7901 // CHECK17-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 7902 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 7903 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 7904 // CHECK17-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 7905 // CHECK17-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 7906 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 7907 // CHECK17-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 7908 // CHECK17-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 7909 // CHECK17-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 7910 // CHECK17-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 7911 // CHECK17-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 7912 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 7913 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 7914 // CHECK17-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 7915 // CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 7916 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 7917 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 7918 // CHECK17-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 7919 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 7920 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 7921 // CHECK17-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 7922 // CHECK17-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 7923 // CHECK17-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 7924 // CHECK17-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 7925 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7926 // CHECK17-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 7927 // CHECK17-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 7928 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 7929 // CHECK17-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 7930 // CHECK17-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 7931 // CHECK17-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 7932 // CHECK17-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 7933 // CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 7934 // CHECK17-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 7935 // CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 7936 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 7937 // CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 7938 // CHECK17-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 7939 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 7940 // CHECK17-NEXT: store i8* null, i8** [[TMP65]], align 8 7941 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 7942 // CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 7943 // CHECK17-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 7944 // CHECK17-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 7945 // CHECK17-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7946 // CHECK17: omp_offload.failed: 7947 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 7948 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 7949 // CHECK17: omp_offload.cont: 7950 // CHECK17-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 7951 // CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 7952 // CHECK17-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 7953 // CHECK17-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 7954 // CHECK17-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 7955 // CHECK17-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 7956 // CHECK17-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 7957 // CHECK17-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 7958 // CHECK17-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 7959 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 7960 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7961 // CHECK17: omp_if.then: 7962 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 7963 // CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 7964 // CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 7965 // CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 7966 // CHECK17-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 7967 // CHECK17-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 7968 // CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 7969 // CHECK17-NEXT: store i8* null, i8** [[TMP79]], align 8 7970 // CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 7971 // CHECK17-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 7972 // CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 7973 // CHECK17-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 7974 // CHECK17-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 7975 // CHECK17-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 7976 // CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 7977 // CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8 7978 // CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 7979 // CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 7980 // CHECK17-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 7981 // CHECK17-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 7982 // CHECK17-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 7983 // CHECK17: omp_offload.failed19: 7984 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 7985 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT20]] 7986 // CHECK17: omp_offload.cont20: 7987 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 7988 // CHECK17: omp_if.else: 7989 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 7990 // CHECK17-NEXT: br label [[OMP_IF_END]] 7991 // CHECK17: omp_if.end: 7992 // CHECK17-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 7993 // CHECK17-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* 7994 // CHECK17-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 7995 // CHECK17-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 7996 // CHECK17-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 7997 // CHECK17-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 7998 // CHECK17-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] 7999 // CHECK17: omp_if.then24: 8000 // CHECK17-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 8001 // CHECK17-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 8002 // CHECK17-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 8003 // CHECK17-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 8004 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) 8005 // CHECK17-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 8006 // CHECK17-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* 8007 // CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP97]], align 8 8008 // CHECK17-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 8009 // CHECK17-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* 8010 // CHECK17-NEXT: store i64 [[TMP90]], i64* [[TMP99]], align 8 8011 // CHECK17-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 8012 // CHECK17-NEXT: store i8* null, i8** [[TMP100]], align 8 8013 // CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 8014 // CHECK17-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 8015 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 8016 // CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 8017 // CHECK17-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 8018 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 8019 // CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 8020 // CHECK17-NEXT: store i8* null, i8** [[TMP105]], align 8 8021 // CHECK17-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 8022 // CHECK17-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* 8023 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP107]], align 8 8024 // CHECK17-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 8025 // CHECK17-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64* 8026 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP109]], align 8 8027 // CHECK17-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 8028 // CHECK17-NEXT: store i8* null, i8** [[TMP110]], align 8 8029 // CHECK17-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 8030 // CHECK17-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 8031 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP112]], align 8 8032 // CHECK17-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 8033 // CHECK17-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 8034 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 8035 // CHECK17-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 8036 // CHECK17-NEXT: store i64 [[TMP92]], i64* [[TMP115]], align 8 8037 // CHECK17-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 8038 // CHECK17-NEXT: store i8* null, i8** [[TMP116]], align 8 8039 // CHECK17-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 8040 // CHECK17-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 8041 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8 8042 // CHECK17-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 8043 // CHECK17-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 8044 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 8045 // CHECK17-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 8046 // CHECK17-NEXT: store i8* null, i8** [[TMP121]], align 8 8047 // CHECK17-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 8048 // CHECK17-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64* 8049 // CHECK17-NEXT: store i64 5, i64* [[TMP123]], align 8 8050 // CHECK17-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 8051 // CHECK17-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* 8052 // CHECK17-NEXT: store i64 5, i64* [[TMP125]], align 8 8053 // CHECK17-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 8054 // CHECK17-NEXT: store i8* null, i8** [[TMP126]], align 8 8055 // CHECK17-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 8056 // CHECK17-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 8057 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 8058 // CHECK17-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 8059 // CHECK17-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64* 8060 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP130]], align 8 8061 // CHECK17-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 8062 // CHECK17-NEXT: store i8* null, i8** [[TMP131]], align 8 8063 // CHECK17-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 8064 // CHECK17-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 8065 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP133]], align 8 8066 // CHECK17-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 8067 // CHECK17-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 8068 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP135]], align 8 8069 // CHECK17-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 8070 // CHECK17-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 8 8071 // CHECK17-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 8072 // CHECK17-NEXT: store i8* null, i8** [[TMP137]], align 8 8073 // CHECK17-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 8074 // CHECK17-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 8075 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8 8076 // CHECK17-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 8077 // CHECK17-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 8078 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8 8079 // CHECK17-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 8080 // CHECK17-NEXT: store i8* null, i8** [[TMP142]], align 8 8081 // CHECK17-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 8082 // CHECK17-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 8083 // CHECK17-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 8084 // CHECK17-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 8085 // CHECK17-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 8086 // CHECK17-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] 8087 // CHECK17: omp_offload.failed28: 8088 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 8089 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT29]] 8090 // CHECK17: omp_offload.cont29: 8091 // CHECK17-NEXT: br label [[OMP_IF_END31:%.*]] 8092 // CHECK17: omp_if.else30: 8093 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 8094 // CHECK17-NEXT: br label [[OMP_IF_END31]] 8095 // CHECK17: omp_if.end31: 8096 // CHECK17-NEXT: store i32 0, i32* [[NN]], align 4 8097 // CHECK17-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 8098 // CHECK17-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 8099 // CHECK17-NEXT: store i32 [[TMP148]], i32* [[CONV32]], align 4 8100 // CHECK17-NEXT: [[TMP149:%.*]] = load i64, i64* [[NN_CASTED]], align 8 8101 // CHECK17-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 8102 // CHECK17-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* 8103 // CHECK17-NEXT: store i64 [[TMP149]], i64* [[TMP151]], align 8 8104 // CHECK17-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 8105 // CHECK17-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* 8106 // CHECK17-NEXT: store i64 [[TMP149]], i64* [[TMP153]], align 8 8107 // CHECK17-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 8108 // CHECK17-NEXT: store i8* null, i8** [[TMP154]], align 8 8109 // CHECK17-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 8110 // CHECK17-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 8111 // CHECK17-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 8112 // CHECK17-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 8113 // CHECK17-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 8114 // CHECK17: omp_offload.failed36: 8115 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP149]]) #[[ATTR3]] 8116 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT37]] 8117 // CHECK17: omp_offload.cont37: 8118 // CHECK17-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 8119 // CHECK17-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* 8120 // CHECK17-NEXT: store i32 [[TMP159]], i32* [[CONV39]], align 4 8121 // CHECK17-NEXT: [[TMP160:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 8122 // CHECK17-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 8123 // CHECK17-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i64* 8124 // CHECK17-NEXT: store i64 [[TMP160]], i64* [[TMP162]], align 8 8125 // CHECK17-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 8126 // CHECK17-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i64* 8127 // CHECK17-NEXT: store i64 [[TMP160]], i64* [[TMP164]], align 8 8128 // CHECK17-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 8129 // CHECK17-NEXT: store i8* null, i8** [[TMP165]], align 8 8130 // CHECK17-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 8131 // CHECK17-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 8132 // CHECK17-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 8133 // CHECK17-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 8134 // CHECK17-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] 8135 // CHECK17: omp_offload.failed43: 8136 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP160]]) #[[ATTR3]] 8137 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT44]] 8138 // CHECK17: omp_offload.cont44: 8139 // CHECK17-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 8140 // CHECK17-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 8141 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 8142 // CHECK17-NEXT: ret i32 [[TMP170]] 8143 // 8144 // 8145 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 8146 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 8147 // CHECK17-NEXT: entry: 8148 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8149 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 8150 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 8151 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8152 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 8153 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8154 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 8155 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 8156 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8157 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 8158 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 8159 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 8160 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 8161 // CHECK17-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 8162 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 8163 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8164 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 8165 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8166 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 8167 // CHECK17-NEXT: ret void 8168 // 8169 // 8170 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 8171 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 8172 // CHECK17-NEXT: entry: 8173 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8174 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8175 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8176 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8177 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8178 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8179 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8180 // CHECK17-NEXT: ret void 8181 // 8182 // 8183 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_privates_map. 8184 // CHECK17-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 8185 // CHECK17-NEXT: entry: 8186 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 8187 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 8188 // CHECK17-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 8189 // CHECK17-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 8190 // CHECK17-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 8191 // CHECK17-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 8192 // CHECK17-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 8193 // CHECK17-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 8194 // CHECK17-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 8195 // CHECK17-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 8196 // CHECK17-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 8197 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 8198 // CHECK17-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 8199 // CHECK17-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 8200 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 8201 // CHECK17-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 8202 // CHECK17-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 8203 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 8204 // CHECK17-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 8205 // CHECK17-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 8206 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 8207 // CHECK17-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 8208 // CHECK17-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 8209 // CHECK17-NEXT: ret void 8210 // 8211 // 8212 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. 8213 // CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 8214 // CHECK17-NEXT: entry: 8215 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 8216 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 8217 // CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 8218 // CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 8219 // CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 8220 // CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 8221 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 8222 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 8223 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 8224 // CHECK17-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 8225 // CHECK17-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 8226 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 8227 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 8228 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 8229 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 8230 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 8231 // CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 8232 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 8233 // CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 8234 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 8235 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 8236 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 8237 // CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 8238 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 8239 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 8240 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 8241 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 8242 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 8243 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 8244 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 8245 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 8246 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 8247 // CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 8248 // CHECK17-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 8249 // CHECK17-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 8250 // CHECK17-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 8251 // CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 8252 // CHECK17-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 8253 // CHECK17-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 8254 // CHECK17-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 8255 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 8256 // CHECK17-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 8257 // CHECK17-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 8258 // CHECK17-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 8259 // CHECK17-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 8260 // CHECK17-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 8261 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 8262 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 8263 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 8264 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 8265 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 8266 // CHECK17-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 8267 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 8268 // CHECK17-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 8269 // CHECK17-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 8270 // CHECK17-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 8271 // CHECK17: omp_offload.failed.i: 8272 // CHECK17-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 8273 // CHECK17-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 8274 // CHECK17-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 8275 // CHECK17-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 8276 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 8277 // CHECK17-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 8278 // CHECK17-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24 8279 // CHECK17-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24 8280 // CHECK17-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 8281 // CHECK17-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 8282 // CHECK17-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24 8283 // CHECK17-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24 8284 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 8285 // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 8286 // CHECK17: .omp_outlined..1.exit: 8287 // CHECK17-NEXT: ret i32 0 8288 // 8289 // 8290 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 8291 // CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { 8292 // CHECK17-NEXT: entry: 8293 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8294 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8295 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8296 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8297 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 8298 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8299 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 8300 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 8301 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 8302 // CHECK17-NEXT: ret void 8303 // 8304 // 8305 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 8306 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 8307 // CHECK17-NEXT: entry: 8308 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8309 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8310 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8311 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8312 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8313 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8314 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8315 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 8316 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8317 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 8318 // CHECK17-NEXT: ret void 8319 // 8320 // 8321 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 8322 // CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 8323 // CHECK17-NEXT: entry: 8324 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8325 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8326 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8327 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8328 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 8329 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8330 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 8331 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8332 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 8333 // CHECK17-NEXT: ret void 8334 // 8335 // 8336 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 8337 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 8338 // CHECK17-NEXT: entry: 8339 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8340 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8341 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8342 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8343 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8344 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8345 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8346 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 8347 // CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 8348 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 8349 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 8350 // CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 8351 // CHECK17-NEXT: ret void 8352 // 8353 // 8354 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 8355 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 8356 // CHECK17-NEXT: entry: 8357 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8358 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8359 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8360 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8361 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8362 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8363 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8364 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8365 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 8366 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8367 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 8368 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 8369 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 8370 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8371 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 8372 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8373 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 8374 // CHECK17-NEXT: ret void 8375 // 8376 // 8377 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 8378 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 8379 // CHECK17-NEXT: entry: 8380 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8381 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8382 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8383 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8384 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8385 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8386 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8387 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8388 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8389 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8390 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 8391 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8392 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 8393 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 8394 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 8395 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 8396 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 8397 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 8398 // CHECK17-NEXT: ret void 8399 // 8400 // 8401 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 8402 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 8403 // CHECK17-NEXT: entry: 8404 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8405 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 8406 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8407 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 8408 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 8409 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 8410 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 8411 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 8412 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 8413 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8414 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8415 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 8416 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8417 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 8418 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 8419 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 8420 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 8421 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 8422 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 8423 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8424 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 8425 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8426 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 8427 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 8428 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 8429 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 8430 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 8431 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 8432 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 8433 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8434 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 8435 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 8436 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 8437 // CHECK17-NEXT: ret void 8438 // 8439 // 8440 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 8441 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 8442 // CHECK17-NEXT: entry: 8443 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8444 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8445 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8446 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 8447 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8448 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 8449 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 8450 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 8451 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 8452 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 8453 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 8454 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8455 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8456 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8457 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 8458 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8459 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 8460 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 8461 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 8462 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 8463 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 8464 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 8465 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8466 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 8467 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8468 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 8469 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 8470 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 8471 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 8472 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 8473 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 8474 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 8475 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 8476 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 8477 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 8478 // CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 8479 // CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 8480 // CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 8481 // CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 8482 // CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 8483 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 8484 // CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 8485 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 8486 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 8487 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 8488 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 8489 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 8490 // CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 8491 // CHECK17-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 8492 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 8493 // CHECK17-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 8494 // CHECK17-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 8495 // CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 8496 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 8497 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 8498 // CHECK17-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 8499 // CHECK17-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 8500 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 8501 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 8502 // CHECK17-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 8503 // CHECK17-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 8504 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 8505 // CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 8506 // CHECK17-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 8507 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 8508 // CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 8509 // CHECK17-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 8510 // CHECK17-NEXT: ret void 8511 // 8512 // 8513 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 8514 // CHECK17-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 8515 // CHECK17-NEXT: entry: 8516 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 8517 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 8518 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 8519 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 8520 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 8521 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 8522 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 8523 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 8524 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 8525 // CHECK17-NEXT: ret void 8526 // 8527 // 8528 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..12 8529 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 8530 // CHECK17-NEXT: entry: 8531 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8532 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8533 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 8534 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 8535 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8536 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8537 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 8538 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 8539 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 8540 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 8541 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 8542 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 8543 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 8544 // CHECK17-NEXT: ret void 8545 // 8546 // 8547 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13 8548 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 8549 // CHECK17-NEXT: entry: 8550 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8551 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8552 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 8553 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8554 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8555 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 8556 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 8557 // CHECK17-NEXT: ret void 8558 // 8559 // 8560 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 8561 // CHECK17-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 8562 // CHECK17-NEXT: entry: 8563 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 8564 // CHECK17-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 8565 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 8566 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 8567 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 8568 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 8569 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 8570 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 8571 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 8572 // CHECK17-NEXT: ret void 8573 // 8574 // 8575 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 8576 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 8577 // CHECK17-NEXT: entry: 8578 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8579 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8580 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 8581 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8582 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8583 // CHECK17-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 8584 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 8585 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[CONV]]) 8586 // CHECK17-NEXT: ret void 8587 // 8588 // 8589 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..17 8590 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 8591 // CHECK17-NEXT: entry: 8592 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8593 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8594 // CHECK17-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 8595 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8596 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8597 // CHECK17-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 8598 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 8599 // CHECK17-NEXT: ret void 8600 // 8601 // 8602 // CHECK17-LABEL: define {{[^@]+}}@_Z6bazzzziPi 8603 // CHECK17-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 8604 // CHECK17-NEXT: entry: 8605 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8606 // CHECK17-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 8607 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 8608 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 8609 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 8610 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8611 // CHECK17-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 8612 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8613 // CHECK17-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 8614 // CHECK17-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8615 // CHECK17-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 8616 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 8617 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8618 // CHECK17-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 8619 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 8620 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 8621 // CHECK17-NEXT: store i8* null, i8** [[TMP6]], align 8 8622 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8623 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8624 // CHECK17-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 8625 // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 8626 // CHECK17-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8627 // CHECK17: omp_offload.failed: 8628 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 8629 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 8630 // CHECK17: omp_offload.cont: 8631 // CHECK17-NEXT: ret void 8632 // 8633 // 8634 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 8635 // CHECK17-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 8636 // CHECK17-NEXT: entry: 8637 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8638 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8639 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8640 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 8641 // CHECK17-NEXT: ret void 8642 // 8643 // 8644 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..20 8645 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 8646 // CHECK17-NEXT: entry: 8647 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8648 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8649 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8650 // CHECK17-NEXT: [[F:%.*]] = alloca i32*, align 8 8651 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8652 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8653 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8654 // CHECK17-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8655 // CHECK17-NEXT: ret void 8656 // 8657 // 8658 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari 8659 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8660 // CHECK17-NEXT: entry: 8661 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8662 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 8663 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 8664 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8665 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 8666 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8667 // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 8668 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 8669 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8670 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8671 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8672 // CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 8673 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 8674 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8675 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 8676 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8677 // CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 8678 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8679 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8680 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 8681 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8682 // CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 8683 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8684 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8685 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 8686 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8687 // CHECK17-NEXT: ret i32 [[TMP8]] 8688 // 8689 // 8690 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8691 // CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8692 // CHECK17-NEXT: entry: 8693 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8694 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8695 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 8696 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 8697 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8698 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 8699 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 8700 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 8701 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 8702 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 8703 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8704 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8705 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8706 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8707 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8708 // CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 8709 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8710 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 8711 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 8712 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 8713 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 8714 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 8715 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 8716 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 8717 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 8718 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 8719 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 8720 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 8721 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 8722 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8723 // CHECK17: omp_if.then: 8724 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8725 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 8726 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 8727 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 8728 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i64 40, i1 false) 8729 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8730 // CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 8731 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 8732 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8733 // CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 8734 // CHECK17-NEXT: store double* [[A]], double** [[TMP14]], align 8 8735 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 8736 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 8737 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 8738 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 8739 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 8740 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 8741 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 8742 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 8743 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 8744 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 8745 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 8746 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 8747 // CHECK17-NEXT: store i64 2, i64* [[TMP22]], align 8 8748 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 8749 // CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 8750 // CHECK17-NEXT: store i64 2, i64* [[TMP24]], align 8 8751 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 8752 // CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8 8753 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 8754 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 8755 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 8756 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 8757 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 8758 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 8759 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 8760 // CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 8761 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 8762 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 8763 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 8764 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 8765 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 8766 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 8767 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 8768 // CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 8769 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 8770 // CHECK17-NEXT: store i8* null, i8** [[TMP36]], align 8 8771 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8772 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8773 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 8774 // CHECK17-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 8775 // CHECK17-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 8776 // CHECK17-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8777 // CHECK17: omp_offload.failed: 8778 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 8779 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 8780 // CHECK17: omp_offload.cont: 8781 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 8782 // CHECK17: omp_if.else: 8783 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 8784 // CHECK17-NEXT: br label [[OMP_IF_END]] 8785 // CHECK17: omp_if.end: 8786 // CHECK17-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 8787 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 8788 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 8789 // CHECK17-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 8790 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 8791 // CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 8792 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 8793 // CHECK17-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 8794 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 8795 // CHECK17-NEXT: ret i32 [[ADD4]] 8796 // 8797 // 8798 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici 8799 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8800 // CHECK17-NEXT: entry: 8801 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8802 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 8803 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 8804 // CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 8805 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8806 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8807 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8808 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 8809 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 8810 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 8811 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 8812 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8813 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 8814 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 8815 // CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 8816 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8817 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8818 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 8819 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 8820 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 8821 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8822 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 8823 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8824 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 8825 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 8826 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 8827 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 8828 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8829 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 8830 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8831 // CHECK17: omp_if.then: 8832 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8833 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 8834 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 8835 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8836 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 8837 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 8838 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 8839 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 8840 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 8841 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 8842 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 8843 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 8844 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 8845 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 8846 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 8847 // CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 8848 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 8849 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 8850 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 8851 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 8852 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 8853 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 8854 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 8855 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 8856 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 8857 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 8858 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 8859 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 8860 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 8861 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 8862 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 8863 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 8864 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8865 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8866 // CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 8867 // CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 8868 // CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8869 // CHECK17: omp_offload.failed: 8870 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 8871 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 8872 // CHECK17: omp_offload.cont: 8873 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 8874 // CHECK17: omp_if.else: 8875 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 8876 // CHECK17-NEXT: br label [[OMP_IF_END]] 8877 // CHECK17: omp_if.end: 8878 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 8879 // CHECK17-NEXT: ret i32 [[TMP31]] 8880 // 8881 // 8882 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8883 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 8884 // CHECK17-NEXT: entry: 8885 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8886 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 8887 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 8888 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8889 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8890 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8891 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 8892 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 8893 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 8894 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8895 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 8896 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 8897 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8898 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8899 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 8900 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 8901 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 8902 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8903 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 8904 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8905 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8906 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 8907 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8908 // CHECK17: omp_if.then: 8909 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8910 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 8911 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 8912 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8913 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 8914 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 8915 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 8916 // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 8917 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 8918 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 8919 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 8920 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 8921 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 8922 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 8923 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 8924 // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 8925 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 8926 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 8927 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 8928 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 8929 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 8930 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 8931 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 8932 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 8933 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8934 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8935 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 8936 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 8937 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8938 // CHECK17: omp_offload.failed: 8939 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 8940 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 8941 // CHECK17: omp_offload.cont: 8942 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 8943 // CHECK17: omp_if.else: 8944 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 8945 // CHECK17-NEXT: br label [[OMP_IF_END]] 8946 // CHECK17: omp_if.end: 8947 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 8948 // CHECK17-NEXT: ret i32 [[TMP24]] 8949 // 8950 // 8951 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 8952 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 8953 // CHECK17-NEXT: entry: 8954 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8955 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 8956 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8957 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 8958 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 8959 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 8960 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8961 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 8962 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8963 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 8964 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 8965 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8966 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 8967 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8968 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 8969 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 8970 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 8971 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 8972 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 8973 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 8974 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 8975 // CHECK17-NEXT: ret void 8976 // 8977 // 8978 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..23 8979 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 8980 // CHECK17-NEXT: entry: 8981 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8982 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8983 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8984 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 8985 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 8986 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 8987 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 8988 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8989 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8990 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8991 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 8992 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 8993 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 8994 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 8995 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8996 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 8997 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 8998 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 8999 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 9000 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 9001 // CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 9002 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 9003 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 9004 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 9005 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 9006 // CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 9007 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 9008 // CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 9009 // CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 9010 // CHECK17-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 9011 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 9012 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 9013 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 9014 // CHECK17-NEXT: ret void 9015 // 9016 // 9017 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 9018 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 9019 // CHECK17-NEXT: entry: 9020 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9021 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9022 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9023 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9024 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9025 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9026 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 9027 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9028 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9029 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 9030 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9031 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9032 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9033 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 9034 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9035 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9036 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9037 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 9038 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 9039 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 9040 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9041 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 9042 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9043 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 9044 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 9045 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 9046 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 9047 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 9048 // CHECK17-NEXT: ret void 9049 // 9050 // 9051 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..26 9052 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 9053 // CHECK17-NEXT: entry: 9054 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9055 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9056 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9057 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9058 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9059 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9060 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9061 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9062 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9063 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9064 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 9065 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9066 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9067 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9068 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 9069 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9070 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9071 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 9072 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 9073 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 9074 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 9075 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 9076 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 9077 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 9078 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 9079 // CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 9080 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 9081 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 9082 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 9083 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 9084 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9085 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 9086 // CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 9087 // CHECK17-NEXT: ret void 9088 // 9089 // 9090 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 9091 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 9092 // CHECK17-NEXT: entry: 9093 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9094 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9095 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9096 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9097 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9098 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9099 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9100 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9101 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9102 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9103 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9104 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9105 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9106 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 9107 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 9108 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 9109 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9110 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 9111 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9112 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 9113 // CHECK17-NEXT: ret void 9114 // 9115 // 9116 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..29 9117 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 9118 // CHECK17-NEXT: entry: 9119 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9120 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9121 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9122 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9123 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9124 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9125 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9126 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9127 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9128 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9129 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9130 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9131 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9132 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9133 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 9134 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 9135 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 9136 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 9137 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 9138 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9139 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 9140 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 9141 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9142 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 9143 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 9144 // CHECK17-NEXT: ret void 9145 // 9146 // 9147 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 9148 // CHECK17-SAME: () #[[ATTR4]] { 9149 // CHECK17-NEXT: entry: 9150 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 9151 // CHECK17-NEXT: ret void 9152 // 9153 // 9154 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi 9155 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 9156 // CHECK18-NEXT: entry: 9157 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9158 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 9159 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 9160 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 9161 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 9162 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 9163 // CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 9164 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 9165 // CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 9166 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 9167 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 9168 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9169 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 9170 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 9171 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 9172 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 9173 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 9174 // CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 9175 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9176 // CHECK18-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 9177 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 9178 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 9179 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 9180 // CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 9181 // CHECK18-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 9182 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 9183 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 9184 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 9185 // CHECK18-NEXT: [[A_CASTED21:%.*]] = alloca i64, align 8 9186 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS25:%.*]] = alloca [9 x i8*], align 8 9187 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS26:%.*]] = alloca [9 x i8*], align 8 9188 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS27:%.*]] = alloca [9 x i8*], align 8 9189 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 9190 // CHECK18-NEXT: [[NN:%.*]] = alloca i32, align 4 9191 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 9192 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 8 9193 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 8 9194 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 8 9195 // CHECK18-NEXT: [[NN_CASTED38:%.*]] = alloca i64, align 8 9196 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS40:%.*]] = alloca [1 x i8*], align 8 9197 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS41:%.*]] = alloca [1 x i8*], align 8 9198 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS42:%.*]] = alloca [1 x i8*], align 8 9199 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 9200 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9201 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 9202 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 9203 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9204 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 9205 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 9206 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 9207 // CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 9208 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 9209 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9210 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 9211 // CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 9212 // CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 9213 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 9214 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 9215 // CHECK18-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 9216 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9217 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 9218 // CHECK18-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 9219 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9220 // CHECK18-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 9221 // CHECK18-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9222 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9223 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 9224 // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 9225 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 9226 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 9227 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 9228 // CHECK18-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 9229 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 9230 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9231 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 9232 // CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 9233 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9234 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 9235 // CHECK18-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 9236 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 9237 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 9238 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 9239 // CHECK18-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 9240 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 9241 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 9242 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 9243 // CHECK18-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 9244 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 9245 // CHECK18-NEXT: store i8* null, i8** [[TMP24]], align 8 9246 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 9247 // CHECK18-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 9248 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 9249 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 9250 // CHECK18-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 9251 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 9252 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 9253 // CHECK18-NEXT: store i8* null, i8** [[TMP29]], align 8 9254 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9255 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9256 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 9257 // CHECK18-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 9258 // CHECK18-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 9259 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 9260 // CHECK18-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 9261 // CHECK18-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 9262 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 9263 // CHECK18-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 9264 // CHECK18-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 9265 // CHECK18-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 9266 // CHECK18-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 9267 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 9268 // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 9269 // CHECK18-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 9270 // CHECK18-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 9271 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 9272 // CHECK18-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 9273 // CHECK18-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 9274 // CHECK18-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 9275 // CHECK18-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 9276 // CHECK18-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 9277 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 9278 // CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 9279 // CHECK18-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 9280 // CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 9281 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 9282 // CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 9283 // CHECK18-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 9284 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 9285 // CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 9286 // CHECK18-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 9287 // CHECK18-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 9288 // CHECK18-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 9289 // CHECK18-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 9290 // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9291 // CHECK18-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 9292 // CHECK18-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 9293 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 9294 // CHECK18-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 9295 // CHECK18-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 9296 // CHECK18-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 9297 // CHECK18-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 9298 // CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 9299 // CHECK18-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 9300 // CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 9301 // CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 9302 // CHECK18-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 9303 // CHECK18-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 9304 // CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 9305 // CHECK18-NEXT: store i8* null, i8** [[TMP65]], align 8 9306 // CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 9307 // CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 9308 // CHECK18-NEXT: [[TMP68:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP66]], i8** [[TMP67]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 9309 // CHECK18-NEXT: [[TMP69:%.*]] = icmp ne i32 [[TMP68]], 0 9310 // CHECK18-NEXT: br i1 [[TMP69]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9311 // CHECK18: omp_offload.failed: 9312 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 9313 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 9314 // CHECK18: omp_offload.cont: 9315 // CHECK18-NEXT: [[TMP70:%.*]] = load i32, i32* [[A]], align 4 9316 // CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 9317 // CHECK18-NEXT: store i32 [[TMP70]], i32* [[CONV13]], align 4 9318 // CHECK18-NEXT: [[TMP71:%.*]] = load i64, i64* [[A_CASTED12]], align 8 9319 // CHECK18-NEXT: [[TMP72:%.*]] = load i16, i16* [[AA]], align 2 9320 // CHECK18-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 9321 // CHECK18-NEXT: store i16 [[TMP72]], i16* [[CONV15]], align 2 9322 // CHECK18-NEXT: [[TMP73:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 9323 // CHECK18-NEXT: [[TMP74:%.*]] = load i32, i32* [[N_ADDR]], align 4 9324 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP74]], 10 9325 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9326 // CHECK18: omp_if.then: 9327 // CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 9328 // CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i64* 9329 // CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP76]], align 8 9330 // CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 9331 // CHECK18-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i64* 9332 // CHECK18-NEXT: store i64 [[TMP71]], i64* [[TMP78]], align 8 9333 // CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 9334 // CHECK18-NEXT: store i8* null, i8** [[TMP79]], align 8 9335 // CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 9336 // CHECK18-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 9337 // CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP81]], align 8 9338 // CHECK18-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 9339 // CHECK18-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i64* 9340 // CHECK18-NEXT: store i64 [[TMP73]], i64* [[TMP83]], align 8 9341 // CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 9342 // CHECK18-NEXT: store i8* null, i8** [[TMP84]], align 8 9343 // CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 9344 // CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 9345 // CHECK18-NEXT: [[TMP87:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP85]], i8** [[TMP86]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 9346 // CHECK18-NEXT: [[TMP88:%.*]] = icmp ne i32 [[TMP87]], 0 9347 // CHECK18-NEXT: br i1 [[TMP88]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 9348 // CHECK18: omp_offload.failed19: 9349 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 9350 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT20]] 9351 // CHECK18: omp_offload.cont20: 9352 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 9353 // CHECK18: omp_if.else: 9354 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP71]], i64 [[TMP73]]) #[[ATTR3]] 9355 // CHECK18-NEXT: br label [[OMP_IF_END]] 9356 // CHECK18: omp_if.end: 9357 // CHECK18-NEXT: [[TMP89:%.*]] = load i32, i32* [[A]], align 4 9358 // CHECK18-NEXT: [[CONV22:%.*]] = bitcast i64* [[A_CASTED21]] to i32* 9359 // CHECK18-NEXT: store i32 [[TMP89]], i32* [[CONV22]], align 4 9360 // CHECK18-NEXT: [[TMP90:%.*]] = load i64, i64* [[A_CASTED21]], align 8 9361 // CHECK18-NEXT: [[TMP91:%.*]] = load i32, i32* [[N_ADDR]], align 4 9362 // CHECK18-NEXT: [[CMP23:%.*]] = icmp sgt i32 [[TMP91]], 20 9363 // CHECK18-NEXT: br i1 [[CMP23]], label [[OMP_IF_THEN24:%.*]], label [[OMP_IF_ELSE30:%.*]] 9364 // CHECK18: omp_if.then24: 9365 // CHECK18-NEXT: [[TMP92:%.*]] = mul nuw i64 [[TMP2]], 4 9366 // CHECK18-NEXT: [[TMP93:%.*]] = mul nuw i64 5, [[TMP5]] 9367 // CHECK18-NEXT: [[TMP94:%.*]] = mul nuw i64 [[TMP93]], 8 9368 // CHECK18-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 9369 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP95]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) 9370 // CHECK18-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 9371 // CHECK18-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* 9372 // CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP97]], align 8 9373 // CHECK18-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 9374 // CHECK18-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i64* 9375 // CHECK18-NEXT: store i64 [[TMP90]], i64* [[TMP99]], align 8 9376 // CHECK18-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 0 9377 // CHECK18-NEXT: store i8* null, i8** [[TMP100]], align 8 9378 // CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 1 9379 // CHECK18-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 9380 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 8 9381 // CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 1 9382 // CHECK18-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 9383 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 8 9384 // CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 1 9385 // CHECK18-NEXT: store i8* null, i8** [[TMP105]], align 8 9386 // CHECK18-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 2 9387 // CHECK18-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i64* 9388 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP107]], align 8 9389 // CHECK18-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 2 9390 // CHECK18-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i64* 9391 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP109]], align 8 9392 // CHECK18-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 2 9393 // CHECK18-NEXT: store i8* null, i8** [[TMP110]], align 8 9394 // CHECK18-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 3 9395 // CHECK18-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 9396 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP112]], align 8 9397 // CHECK18-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 3 9398 // CHECK18-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 9399 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP114]], align 8 9400 // CHECK18-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 9401 // CHECK18-NEXT: store i64 [[TMP92]], i64* [[TMP115]], align 8 9402 // CHECK18-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 3 9403 // CHECK18-NEXT: store i8* null, i8** [[TMP116]], align 8 9404 // CHECK18-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 4 9405 // CHECK18-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 9406 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 8 9407 // CHECK18-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 4 9408 // CHECK18-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 9409 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 8 9410 // CHECK18-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 4 9411 // CHECK18-NEXT: store i8* null, i8** [[TMP121]], align 8 9412 // CHECK18-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 5 9413 // CHECK18-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i64* 9414 // CHECK18-NEXT: store i64 5, i64* [[TMP123]], align 8 9415 // CHECK18-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 5 9416 // CHECK18-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* 9417 // CHECK18-NEXT: store i64 5, i64* [[TMP125]], align 8 9418 // CHECK18-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 5 9419 // CHECK18-NEXT: store i8* null, i8** [[TMP126]], align 8 9420 // CHECK18-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 6 9421 // CHECK18-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i64* 9422 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP128]], align 8 9423 // CHECK18-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 6 9424 // CHECK18-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i64* 9425 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP130]], align 8 9426 // CHECK18-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 6 9427 // CHECK18-NEXT: store i8* null, i8** [[TMP131]], align 8 9428 // CHECK18-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 7 9429 // CHECK18-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 9430 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP133]], align 8 9431 // CHECK18-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 7 9432 // CHECK18-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 9433 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP135]], align 8 9434 // CHECK18-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 9435 // CHECK18-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 8 9436 // CHECK18-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 7 9437 // CHECK18-NEXT: store i8* null, i8** [[TMP137]], align 8 9438 // CHECK18-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 8 9439 // CHECK18-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 9440 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 8 9441 // CHECK18-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 8 9442 // CHECK18-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 9443 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 8 9444 // CHECK18-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS27]], i64 0, i64 8 9445 // CHECK18-NEXT: store i8* null, i8** [[TMP142]], align 8 9446 // CHECK18-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS25]], i32 0, i32 0 9447 // CHECK18-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS26]], i32 0, i32 0 9448 // CHECK18-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 9449 // CHECK18-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 9450 // CHECK18-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 9451 // CHECK18-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED28:%.*]], label [[OMP_OFFLOAD_CONT29:%.*]] 9452 // CHECK18: omp_offload.failed28: 9453 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 9454 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT29]] 9455 // CHECK18: omp_offload.cont29: 9456 // CHECK18-NEXT: br label [[OMP_IF_END31:%.*]] 9457 // CHECK18: omp_if.else30: 9458 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP90]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 9459 // CHECK18-NEXT: br label [[OMP_IF_END31]] 9460 // CHECK18: omp_if.end31: 9461 // CHECK18-NEXT: store i32 0, i32* [[NN]], align 4 9462 // CHECK18-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 9463 // CHECK18-NEXT: [[CONV32:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 9464 // CHECK18-NEXT: store i32 [[TMP148]], i32* [[CONV32]], align 4 9465 // CHECK18-NEXT: [[TMP149:%.*]] = load i64, i64* [[NN_CASTED]], align 8 9466 // CHECK18-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 9467 // CHECK18-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i64* 9468 // CHECK18-NEXT: store i64 [[TMP149]], i64* [[TMP151]], align 8 9469 // CHECK18-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 9470 // CHECK18-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i64* 9471 // CHECK18-NEXT: store i64 [[TMP149]], i64* [[TMP153]], align 8 9472 // CHECK18-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i64 0, i64 0 9473 // CHECK18-NEXT: store i8* null, i8** [[TMP154]], align 8 9474 // CHECK18-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 9475 // CHECK18-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 9476 // CHECK18-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 9477 // CHECK18-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 9478 // CHECK18-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 9479 // CHECK18: omp_offload.failed36: 9480 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP149]]) #[[ATTR3]] 9481 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT37]] 9482 // CHECK18: omp_offload.cont37: 9483 // CHECK18-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 9484 // CHECK18-NEXT: [[CONV39:%.*]] = bitcast i64* [[NN_CASTED38]] to i32* 9485 // CHECK18-NEXT: store i32 [[TMP159]], i32* [[CONV39]], align 4 9486 // CHECK18-NEXT: [[TMP160:%.*]] = load i64, i64* [[NN_CASTED38]], align 8 9487 // CHECK18-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 9488 // CHECK18-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i64* 9489 // CHECK18-NEXT: store i64 [[TMP160]], i64* [[TMP162]], align 8 9490 // CHECK18-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 9491 // CHECK18-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i64* 9492 // CHECK18-NEXT: store i64 [[TMP160]], i64* [[TMP164]], align 8 9493 // CHECK18-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS42]], i64 0, i64 0 9494 // CHECK18-NEXT: store i8* null, i8** [[TMP165]], align 8 9495 // CHECK18-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS40]], i32 0, i32 0 9496 // CHECK18-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS41]], i32 0, i32 0 9497 // CHECK18-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 9498 // CHECK18-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 9499 // CHECK18-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED43:%.*]], label [[OMP_OFFLOAD_CONT44:%.*]] 9500 // CHECK18: omp_offload.failed43: 9501 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP160]]) #[[ATTR3]] 9502 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT44]] 9503 // CHECK18: omp_offload.cont44: 9504 // CHECK18-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 9505 // CHECK18-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 9506 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 9507 // CHECK18-NEXT: ret i32 [[TMP170]] 9508 // 9509 // 9510 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 9511 // CHECK18-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 9512 // CHECK18-NEXT: entry: 9513 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9514 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9515 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 9516 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9517 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 9518 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9519 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 9520 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 9521 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9522 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 9523 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 9524 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 9525 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 9526 // CHECK18-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 9527 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9528 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9529 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 9530 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9531 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 9532 // CHECK18-NEXT: ret void 9533 // 9534 // 9535 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 9536 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 9537 // CHECK18-NEXT: entry: 9538 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9539 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9540 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9541 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9542 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9543 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9544 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9545 // CHECK18-NEXT: ret void 9546 // 9547 // 9548 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_privates_map. 9549 // CHECK18-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 9550 // CHECK18-NEXT: entry: 9551 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 9552 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 9553 // CHECK18-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 9554 // CHECK18-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 9555 // CHECK18-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 9556 // CHECK18-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 9557 // CHECK18-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 9558 // CHECK18-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 9559 // CHECK18-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 9560 // CHECK18-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 9561 // CHECK18-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 9562 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 9563 // CHECK18-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 9564 // CHECK18-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 9565 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 9566 // CHECK18-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 9567 // CHECK18-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 9568 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 9569 // CHECK18-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 9570 // CHECK18-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 9571 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 9572 // CHECK18-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 9573 // CHECK18-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 9574 // CHECK18-NEXT: ret void 9575 // 9576 // 9577 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. 9578 // CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 9579 // CHECK18-NEXT: entry: 9580 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 9581 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 9582 // CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 9583 // CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 9584 // CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 9585 // CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 9586 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 9587 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 9588 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 9589 // CHECK18-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 9590 // CHECK18-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 9591 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 9592 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 9593 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 9594 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 9595 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 9596 // CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 9597 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 9598 // CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 9599 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 9600 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 9601 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 9602 // CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 9603 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 9604 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 9605 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 9606 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 9607 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 9608 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 9609 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 9610 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 9611 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 9612 // CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 9613 // CHECK18-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 9614 // CHECK18-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 9615 // CHECK18-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 9616 // CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 9617 // CHECK18-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 9618 // CHECK18-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 9619 // CHECK18-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 9620 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 9621 // CHECK18-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 9622 // CHECK18-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 9623 // CHECK18-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 9624 // CHECK18-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 9625 // CHECK18-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 9626 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 9627 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 9628 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 9629 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 9630 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 9631 // CHECK18-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 9632 // CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 9633 // CHECK18-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 9634 // CHECK18-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 9635 // CHECK18-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 9636 // CHECK18: omp_offload.failed.i: 9637 // CHECK18-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 9638 // CHECK18-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 9639 // CHECK18-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !24 9640 // CHECK18-NEXT: [[TMP30:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 9641 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 9642 // CHECK18-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 9643 // CHECK18-NEXT: store i32 [[TMP31]], i32* [[CONV4_I]], align 4, !noalias !24 9644 // CHECK18-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24 9645 // CHECK18-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 9646 // CHECK18-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 9647 // CHECK18-NEXT: store i32 [[TMP33]], i32* [[CONV6_I]], align 4, !noalias !24 9648 // CHECK18-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24 9649 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP30]], i64 [[TMP32]], i64 [[TMP34]]) #[[ATTR3]] 9650 // CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 9651 // CHECK18: .omp_outlined..1.exit: 9652 // CHECK18-NEXT: ret i32 0 9653 // 9654 // 9655 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 9656 // CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { 9657 // CHECK18-NEXT: entry: 9658 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9659 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9660 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9661 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9662 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9663 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9664 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 9665 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 9666 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 9667 // CHECK18-NEXT: ret void 9668 // 9669 // 9670 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 9671 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 9672 // CHECK18-NEXT: entry: 9673 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9674 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9675 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9676 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9677 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9678 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9679 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9680 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9681 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9682 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 9683 // CHECK18-NEXT: ret void 9684 // 9685 // 9686 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 9687 // CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 9688 // CHECK18-NEXT: entry: 9689 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9690 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9691 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9692 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9693 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9694 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9695 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 9696 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9697 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 9698 // CHECK18-NEXT: ret void 9699 // 9700 // 9701 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 9702 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 9703 // CHECK18-NEXT: entry: 9704 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9705 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9706 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9707 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9708 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9709 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9710 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9711 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9712 // CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 9713 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 9714 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 9715 // CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 9716 // CHECK18-NEXT: ret void 9717 // 9718 // 9719 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 9720 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 9721 // CHECK18-NEXT: entry: 9722 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9723 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9724 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9725 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9726 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9727 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9728 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9729 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9730 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9731 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9732 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 9733 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 9734 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 9735 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9736 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 9737 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9738 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 9739 // CHECK18-NEXT: ret void 9740 // 9741 // 9742 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..6 9743 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 9744 // CHECK18-NEXT: entry: 9745 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9746 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9747 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9748 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9749 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9750 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9751 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9752 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9753 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9754 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9755 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9756 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9757 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 9758 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 9759 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 9760 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 9761 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9762 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 9763 // CHECK18-NEXT: ret void 9764 // 9765 // 9766 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 9767 // CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 9768 // CHECK18-NEXT: entry: 9769 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9770 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 9771 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9772 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 9773 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 9774 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9775 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9776 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 9777 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 9778 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9779 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9780 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 9781 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9782 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 9783 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 9784 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9785 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 9786 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 9787 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 9788 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9789 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 9790 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9791 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 9792 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 9793 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9794 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 9795 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 9796 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 9797 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 9798 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9799 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 9800 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 9801 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 9802 // CHECK18-NEXT: ret void 9803 // 9804 // 9805 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 9806 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 9807 // CHECK18-NEXT: entry: 9808 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9809 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9810 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9811 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 9812 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9813 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 9814 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 9815 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9816 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9817 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 9818 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 9819 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9820 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9821 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9822 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 9823 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9824 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 9825 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 9826 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9827 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 9828 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 9829 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 9830 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9831 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 9832 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9833 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 9834 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 9835 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9836 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 9837 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 9838 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 9839 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 9840 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 9841 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 9842 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 9843 // CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 9844 // CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 9845 // CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 9846 // CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 9847 // CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 9848 // CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 9849 // CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 9850 // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 9851 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 9852 // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 9853 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 9854 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 9855 // CHECK18-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 9856 // CHECK18-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 9857 // CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 9858 // CHECK18-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 9859 // CHECK18-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 9860 // CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 9861 // CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 9862 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 9863 // CHECK18-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 9864 // CHECK18-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 9865 // CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 9866 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 9867 // CHECK18-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 9868 // CHECK18-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 9869 // CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 9870 // CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 9871 // CHECK18-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 9872 // CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 9873 // CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 9874 // CHECK18-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 9875 // CHECK18-NEXT: ret void 9876 // 9877 // 9878 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 9879 // CHECK18-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 9880 // CHECK18-NEXT: entry: 9881 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 9882 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 9883 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 9884 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 9885 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9886 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 9887 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 9888 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 9889 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 9890 // CHECK18-NEXT: ret void 9891 // 9892 // 9893 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..12 9894 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 9895 // CHECK18-NEXT: entry: 9896 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9897 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9898 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 9899 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 9900 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9901 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9902 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 9903 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 9904 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9905 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 9906 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 9907 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 9908 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 9909 // CHECK18-NEXT: ret void 9910 // 9911 // 9912 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13 9913 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 9914 // CHECK18-NEXT: entry: 9915 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9916 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9917 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 9918 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9919 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9920 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 9921 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 9922 // CHECK18-NEXT: ret void 9923 // 9924 // 9925 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 9926 // CHECK18-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 9927 // CHECK18-NEXT: entry: 9928 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 9929 // CHECK18-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 9930 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 9931 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 9932 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9933 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 9934 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 9935 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 9936 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 9937 // CHECK18-NEXT: ret void 9938 // 9939 // 9940 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 9941 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 9942 // CHECK18-NEXT: entry: 9943 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9944 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9945 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 9946 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9947 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9948 // CHECK18-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 9949 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 9950 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[CONV]]) 9951 // CHECK18-NEXT: ret void 9952 // 9953 // 9954 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..17 9955 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 9956 // CHECK18-NEXT: entry: 9957 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9958 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9959 // CHECK18-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 9960 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9961 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9962 // CHECK18-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 9963 // CHECK18-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 9964 // CHECK18-NEXT: ret void 9965 // 9966 // 9967 // CHECK18-LABEL: define {{[^@]+}}@_Z6bazzzziPi 9968 // CHECK18-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 9969 // CHECK18-NEXT: entry: 9970 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9971 // CHECK18-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 9972 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 9973 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 9974 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 9975 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9976 // CHECK18-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 9977 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9978 // CHECK18-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 9979 // CHECK18-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9980 // CHECK18-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 9981 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 9982 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9983 // CHECK18-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 9984 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 9985 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 9986 // CHECK18-NEXT: store i8* null, i8** [[TMP6]], align 8 9987 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9988 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9989 // CHECK18-NEXT: [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 9990 // CHECK18-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 9991 // CHECK18-NEXT: br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9992 // CHECK18: omp_offload.failed: 9993 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 9994 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 9995 // CHECK18: omp_offload.cont: 9996 // CHECK18-NEXT: ret void 9997 // 9998 // 9999 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 10000 // CHECK18-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 10001 // CHECK18-NEXT: entry: 10002 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10003 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10004 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10005 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 10006 // CHECK18-NEXT: ret void 10007 // 10008 // 10009 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..20 10010 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 10011 // CHECK18-NEXT: entry: 10012 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10013 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10014 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10015 // CHECK18-NEXT: [[F:%.*]] = alloca i32*, align 8 10016 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10017 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10018 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10019 // CHECK18-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10020 // CHECK18-NEXT: ret void 10021 // 10022 // 10023 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari 10024 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 10025 // CHECK18-NEXT: entry: 10026 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10027 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 10028 // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 10029 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10030 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 10031 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 10032 // CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 10033 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 10034 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 10035 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 10036 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 10037 // CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 10038 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 10039 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 10040 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 10041 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 10042 // CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 10043 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 10044 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 10045 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 10046 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 10047 // CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 10048 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 10049 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 10050 // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 10051 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 10052 // CHECK18-NEXT: ret i32 [[TMP8]] 10053 // 10054 // 10055 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 10056 // CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 10057 // CHECK18-NEXT: entry: 10058 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10059 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10060 // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 10061 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 10062 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 10063 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10064 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 10065 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 10066 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 10067 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 10068 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10069 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10070 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10071 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 10072 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10073 // CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 10074 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 10075 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 10076 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 10077 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 10078 // CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 10079 // CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 10080 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 10081 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 10082 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10083 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 10084 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 10085 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 10086 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 10087 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10088 // CHECK18: omp_if.then: 10089 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 10090 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 10091 // CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 10092 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 10093 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i64 40, i1 false) 10094 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10095 // CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 10096 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 10097 // CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10098 // CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 10099 // CHECK18-NEXT: store double* [[A]], double** [[TMP14]], align 8 10100 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 10101 // CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 10102 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 10103 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 10104 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 10105 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 10106 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 10107 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 10108 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 10109 // CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 10110 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 10111 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 10112 // CHECK18-NEXT: store i64 2, i64* [[TMP22]], align 8 10113 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 10114 // CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 10115 // CHECK18-NEXT: store i64 2, i64* [[TMP24]], align 8 10116 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 10117 // CHECK18-NEXT: store i8* null, i8** [[TMP25]], align 8 10118 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 10119 // CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 10120 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 10121 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 10122 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 10123 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 10124 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 10125 // CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 10126 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 10127 // CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 10128 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 10129 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 10130 // CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 10131 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 10132 // CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 10133 // CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 10134 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 10135 // CHECK18-NEXT: store i8* null, i8** [[TMP36]], align 8 10136 // CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10137 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10138 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 10139 // CHECK18-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10140 // CHECK18-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 10141 // CHECK18-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 10142 // CHECK18: omp_offload.failed: 10143 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 10144 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 10145 // CHECK18: omp_offload.cont: 10146 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 10147 // CHECK18: omp_if.else: 10148 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 10149 // CHECK18-NEXT: br label [[OMP_IF_END]] 10150 // CHECK18: omp_if.end: 10151 // CHECK18-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 10152 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 10153 // CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 10154 // CHECK18-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 10155 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 10156 // CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 10157 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 10158 // CHECK18-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 10159 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 10160 // CHECK18-NEXT: ret i32 [[ADD4]] 10161 // 10162 // 10163 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici 10164 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 10165 // CHECK18-NEXT: entry: 10166 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10167 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 10168 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 10169 // CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 10170 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 10171 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10172 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10173 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 10174 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 10175 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 10176 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 10177 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10178 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 10179 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 10180 // CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 10181 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 10182 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10183 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 10184 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10185 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 10186 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10187 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 10188 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10189 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 10190 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 10191 // CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 10192 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 10193 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 10194 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 10195 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10196 // CHECK18: omp_if.then: 10197 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10198 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 10199 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 10200 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10201 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 10202 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 10203 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 10204 // CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 10205 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 10206 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 10207 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 10208 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 10209 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 10210 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 10211 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 10212 // CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 10213 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 10214 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 10215 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 10216 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 10217 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 10218 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 10219 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 10220 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 10221 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 10222 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 10223 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 10224 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 10225 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 10226 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 10227 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 10228 // CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 10229 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10230 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10231 // CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10232 // CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 10233 // CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 10234 // CHECK18: omp_offload.failed: 10235 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 10236 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 10237 // CHECK18: omp_offload.cont: 10238 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 10239 // CHECK18: omp_if.else: 10240 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 10241 // CHECK18-NEXT: br label [[OMP_IF_END]] 10242 // CHECK18: omp_if.end: 10243 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 10244 // CHECK18-NEXT: ret i32 [[TMP31]] 10245 // 10246 // 10247 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 10248 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 10249 // CHECK18-NEXT: entry: 10250 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10251 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 10252 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 10253 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 10254 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10255 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10256 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 10257 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 10258 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 10259 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10260 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 10261 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 10262 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 10263 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10264 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 10265 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10266 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 10267 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10268 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 10269 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10270 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 10271 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 10272 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10273 // CHECK18: omp_if.then: 10274 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10275 // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 10276 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 10277 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10278 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 10279 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 10280 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 10281 // CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 10282 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 10283 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 10284 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 10285 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 10286 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 10287 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 10288 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 10289 // CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 10290 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 10291 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 10292 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 10293 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 10294 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 10295 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 10296 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 10297 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 10298 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10299 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10300 // CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10301 // CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 10302 // CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 10303 // CHECK18: omp_offload.failed: 10304 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 10305 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 10306 // CHECK18: omp_offload.cont: 10307 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 10308 // CHECK18: omp_if.else: 10309 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 10310 // CHECK18-NEXT: br label [[OMP_IF_END]] 10311 // CHECK18: omp_if.end: 10312 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 10313 // CHECK18-NEXT: ret i32 [[TMP24]] 10314 // 10315 // 10316 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 10317 // CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 10318 // CHECK18-NEXT: entry: 10319 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10320 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10321 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10322 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10323 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10324 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10325 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10326 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10327 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10328 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10329 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10330 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10331 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10332 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10333 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10334 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10335 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10336 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10337 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 10338 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 10339 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 10340 // CHECK18-NEXT: ret void 10341 // 10342 // 10343 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..23 10344 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 10345 // CHECK18-NEXT: entry: 10346 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10347 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10348 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10349 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10350 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10351 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10352 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10353 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10354 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10355 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10356 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10357 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10358 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10359 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10360 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10361 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10362 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10363 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10364 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10365 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10366 // CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 10367 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 10368 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 10369 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 10370 // CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 10371 // CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 10372 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 10373 // CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 10374 // CHECK18-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10375 // CHECK18-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 10376 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 10377 // CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 10378 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 10379 // CHECK18-NEXT: ret void 10380 // 10381 // 10382 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 10383 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 10384 // CHECK18-NEXT: entry: 10385 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10386 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10387 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10388 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10389 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10390 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10391 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 10392 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10393 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10394 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10395 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10396 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10397 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10398 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10399 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10400 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10401 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10402 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 10403 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10404 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10405 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10406 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 10407 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10408 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 10409 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 10410 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 10411 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 10412 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 10413 // CHECK18-NEXT: ret void 10414 // 10415 // 10416 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..26 10417 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 10418 // CHECK18-NEXT: entry: 10419 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10420 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10421 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10422 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10423 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10424 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10425 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10426 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10427 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10428 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10429 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10430 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10431 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10432 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10433 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10434 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10435 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10436 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10437 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10438 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10439 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 10440 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10441 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10442 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 10443 // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 10444 // CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 10445 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 10446 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 10447 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 10448 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10449 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10450 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 10451 // CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 10452 // CHECK18-NEXT: ret void 10453 // 10454 // 10455 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 10456 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 10457 // CHECK18-NEXT: entry: 10458 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10459 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10460 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10461 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10462 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10463 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10464 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10465 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10466 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10467 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10468 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10469 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10470 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10471 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 10472 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10473 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10474 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10475 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 10476 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10477 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 10478 // CHECK18-NEXT: ret void 10479 // 10480 // 10481 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..29 10482 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 10483 // CHECK18-NEXT: entry: 10484 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10485 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10486 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10487 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10488 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10489 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10490 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10491 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10492 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10493 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10494 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10495 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10496 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10497 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10498 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10499 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10500 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10501 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 10502 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10503 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10504 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 10505 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10506 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10507 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 10508 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 10509 // CHECK18-NEXT: ret void 10510 // 10511 // 10512 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 10513 // CHECK18-SAME: () #[[ATTR4]] { 10514 // CHECK18-NEXT: entry: 10515 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 10516 // CHECK18-NEXT: ret void 10517 // 10518 // 10519 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi 10520 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 10521 // CHECK19-NEXT: entry: 10522 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 10523 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 10524 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 10525 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 10526 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 10527 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 10528 // CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 10529 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 10530 // CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 10531 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 10532 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 10533 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10534 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 10535 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 10536 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 10537 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 10538 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 10539 // CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 10540 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10541 // CHECK19-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 10542 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 10543 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 10544 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 10545 // CHECK19-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 10546 // CHECK19-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 10547 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 10548 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 10549 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 10550 // CHECK19-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 10551 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 10552 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 10553 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 10554 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 10555 // CHECK19-NEXT: [[NN:%.*]] = alloca i32, align 4 10556 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 10557 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 10558 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 10559 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 10560 // CHECK19-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 10561 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 10562 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 10563 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 10564 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 10565 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 10566 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 10567 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 10568 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 10569 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 10570 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 10571 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 10572 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 10573 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 10574 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 10575 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 10576 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 10577 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 10578 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 10579 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 10580 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 10581 // CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 10582 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10583 // CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 10584 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10585 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10586 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 10587 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 10588 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 10589 // CHECK19-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 10590 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 10591 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10592 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 10593 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 10594 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10595 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 10596 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 10597 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 10598 // CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 10599 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 10600 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 10601 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 10602 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 10603 // CHECK19-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 10604 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 10605 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 10606 // CHECK19-NEXT: store i8* null, i8** [[TMP22]], align 4 10607 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 10608 // CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 10609 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 10610 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 10611 // CHECK19-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 10612 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 10613 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 10614 // CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 10615 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 10616 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 10617 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 10618 // CHECK19-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 10619 // CHECK19-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 10620 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 10621 // CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 10622 // CHECK19-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 10623 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 10624 // CHECK19-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 10625 // CHECK19-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 10626 // CHECK19-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 10627 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 10628 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 10629 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 10630 // CHECK19-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 10631 // CHECK19-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 10632 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 10633 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 10634 // CHECK19-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 10635 // CHECK19-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 10636 // CHECK19-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 10637 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 10638 // CHECK19-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 10639 // CHECK19-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 10640 // CHECK19-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 10641 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 10642 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 10643 // CHECK19-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 10644 // CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 10645 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 10646 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 10647 // CHECK19-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 10648 // CHECK19-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 10649 // CHECK19-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 10650 // CHECK19-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 10651 // CHECK19-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 10652 // CHECK19-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 10653 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 10654 // CHECK19-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 10655 // CHECK19-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 10656 // CHECK19-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 10657 // CHECK19-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 10658 // CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 10659 // CHECK19-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 10660 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 10661 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 10662 // CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 10663 // CHECK19-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 10664 // CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 10665 // CHECK19-NEXT: store i8* null, i8** [[TMP63]], align 4 10666 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 10667 // CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 10668 // CHECK19-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10669 // CHECK19-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 10670 // CHECK19-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 10671 // CHECK19: omp_offload.failed: 10672 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 10673 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 10674 // CHECK19: omp_offload.cont: 10675 // CHECK19-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 10676 // CHECK19-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 10677 // CHECK19-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 10678 // CHECK19-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 10679 // CHECK19-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 10680 // CHECK19-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 10681 // CHECK19-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 10682 // CHECK19-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 10683 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 10684 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10685 // CHECK19: omp_if.then: 10686 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 10687 // CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 10688 // CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 10689 // CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 10690 // CHECK19-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 10691 // CHECK19-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 10692 // CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 10693 // CHECK19-NEXT: store i8* null, i8** [[TMP77]], align 4 10694 // CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 10695 // CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 10696 // CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 10697 // CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 10698 // CHECK19-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 10699 // CHECK19-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 10700 // CHECK19-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 10701 // CHECK19-NEXT: store i8* null, i8** [[TMP82]], align 4 10702 // CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 10703 // CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 10704 // CHECK19-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10705 // CHECK19-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 10706 // CHECK19-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 10707 // CHECK19: omp_offload.failed15: 10708 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 10709 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT16]] 10710 // CHECK19: omp_offload.cont16: 10711 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 10712 // CHECK19: omp_if.else: 10713 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 10714 // CHECK19-NEXT: br label [[OMP_IF_END]] 10715 // CHECK19: omp_if.end: 10716 // CHECK19-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 10717 // CHECK19-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 10718 // CHECK19-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 10719 // CHECK19-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 10720 // CHECK19-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 10721 // CHECK19-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 10722 // CHECK19: omp_if.then19: 10723 // CHECK19-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 10724 // CHECK19-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 10725 // CHECK19-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 10726 // CHECK19-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 10727 // CHECK19-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 10728 // CHECK19-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 10729 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) 10730 // CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 10731 // CHECK19-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* 10732 // CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP97]], align 4 10733 // CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 10734 // CHECK19-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 10735 // CHECK19-NEXT: store i32 [[TMP88]], i32* [[TMP99]], align 4 10736 // CHECK19-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 10737 // CHECK19-NEXT: store i8* null, i8** [[TMP100]], align 4 10738 // CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 10739 // CHECK19-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 10740 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 10741 // CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 10742 // CHECK19-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 10743 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 10744 // CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 10745 // CHECK19-NEXT: store i8* null, i8** [[TMP105]], align 4 10746 // CHECK19-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 10747 // CHECK19-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32* 10748 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP107]], align 4 10749 // CHECK19-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 10750 // CHECK19-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* 10751 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP109]], align 4 10752 // CHECK19-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 10753 // CHECK19-NEXT: store i8* null, i8** [[TMP110]], align 4 10754 // CHECK19-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 10755 // CHECK19-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 10756 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP112]], align 4 10757 // CHECK19-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 10758 // CHECK19-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 10759 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 10760 // CHECK19-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 10761 // CHECK19-NEXT: store i64 [[TMP91]], i64* [[TMP115]], align 4 10762 // CHECK19-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 10763 // CHECK19-NEXT: store i8* null, i8** [[TMP116]], align 4 10764 // CHECK19-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 10765 // CHECK19-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 10766 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4 10767 // CHECK19-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 10768 // CHECK19-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 10769 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 10770 // CHECK19-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 10771 // CHECK19-NEXT: store i8* null, i8** [[TMP121]], align 4 10772 // CHECK19-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 10773 // CHECK19-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32* 10774 // CHECK19-NEXT: store i32 5, i32* [[TMP123]], align 4 10775 // CHECK19-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 10776 // CHECK19-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* 10777 // CHECK19-NEXT: store i32 5, i32* [[TMP125]], align 4 10778 // CHECK19-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 10779 // CHECK19-NEXT: store i8* null, i8** [[TMP126]], align 4 10780 // CHECK19-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 10781 // CHECK19-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 10782 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP128]], align 4 10783 // CHECK19-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 10784 // CHECK19-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32* 10785 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP130]], align 4 10786 // CHECK19-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 10787 // CHECK19-NEXT: store i8* null, i8** [[TMP131]], align 4 10788 // CHECK19-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 10789 // CHECK19-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 10790 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP133]], align 4 10791 // CHECK19-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 10792 // CHECK19-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 10793 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP135]], align 4 10794 // CHECK19-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 10795 // CHECK19-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 4 10796 // CHECK19-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 10797 // CHECK19-NEXT: store i8* null, i8** [[TMP137]], align 4 10798 // CHECK19-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 10799 // CHECK19-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 10800 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4 10801 // CHECK19-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 10802 // CHECK19-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 10803 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4 10804 // CHECK19-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 10805 // CHECK19-NEXT: store i8* null, i8** [[TMP142]], align 4 10806 // CHECK19-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 10807 // CHECK19-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 10808 // CHECK19-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 10809 // CHECK19-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10810 // CHECK19-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 10811 // CHECK19-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 10812 // CHECK19: omp_offload.failed23: 10813 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 10814 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT24]] 10815 // CHECK19: omp_offload.cont24: 10816 // CHECK19-NEXT: br label [[OMP_IF_END26:%.*]] 10817 // CHECK19: omp_if.else25: 10818 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 10819 // CHECK19-NEXT: br label [[OMP_IF_END26]] 10820 // CHECK19: omp_if.end26: 10821 // CHECK19-NEXT: store i32 0, i32* [[NN]], align 4 10822 // CHECK19-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 10823 // CHECK19-NEXT: store i32 [[TMP148]], i32* [[NN_CASTED]], align 4 10824 // CHECK19-NEXT: [[TMP149:%.*]] = load i32, i32* [[NN_CASTED]], align 4 10825 // CHECK19-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 10826 // CHECK19-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* 10827 // CHECK19-NEXT: store i32 [[TMP149]], i32* [[TMP151]], align 4 10828 // CHECK19-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 10829 // CHECK19-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* 10830 // CHECK19-NEXT: store i32 [[TMP149]], i32* [[TMP153]], align 4 10831 // CHECK19-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 10832 // CHECK19-NEXT: store i8* null, i8** [[TMP154]], align 4 10833 // CHECK19-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 10834 // CHECK19-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 10835 // CHECK19-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10836 // CHECK19-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 10837 // CHECK19-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 10838 // CHECK19: omp_offload.failed30: 10839 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP149]]) #[[ATTR3]] 10840 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT31]] 10841 // CHECK19: omp_offload.cont31: 10842 // CHECK19-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 10843 // CHECK19-NEXT: store i32 [[TMP159]], i32* [[NN_CASTED32]], align 4 10844 // CHECK19-NEXT: [[TMP160:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 10845 // CHECK19-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 10846 // CHECK19-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32* 10847 // CHECK19-NEXT: store i32 [[TMP160]], i32* [[TMP162]], align 4 10848 // CHECK19-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 10849 // CHECK19-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32* 10850 // CHECK19-NEXT: store i32 [[TMP160]], i32* [[TMP164]], align 4 10851 // CHECK19-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 10852 // CHECK19-NEXT: store i8* null, i8** [[TMP165]], align 4 10853 // CHECK19-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 10854 // CHECK19-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 10855 // CHECK19-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 10856 // CHECK19-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 10857 // CHECK19-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 10858 // CHECK19: omp_offload.failed36: 10859 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP160]]) #[[ATTR3]] 10860 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT37]] 10861 // CHECK19: omp_offload.cont37: 10862 // CHECK19-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 10863 // CHECK19-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 10864 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 10865 // CHECK19-NEXT: ret i32 [[TMP170]] 10866 // 10867 // 10868 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 10869 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 10870 // CHECK19-NEXT: entry: 10871 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10872 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 10873 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 10874 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10875 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 10876 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10877 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 10878 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 10879 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10880 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 10881 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 10882 // CHECK19-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 10883 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 10884 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10885 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 10886 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10887 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 10888 // CHECK19-NEXT: ret void 10889 // 10890 // 10891 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 10892 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 10893 // CHECK19-NEXT: entry: 10894 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10895 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10896 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10897 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10898 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10899 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10900 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10901 // CHECK19-NEXT: ret void 10902 // 10903 // 10904 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_privates_map. 10905 // CHECK19-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 10906 // CHECK19-NEXT: entry: 10907 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 10908 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 10909 // CHECK19-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 10910 // CHECK19-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 10911 // CHECK19-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 10912 // CHECK19-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 10913 // CHECK19-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 10914 // CHECK19-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 10915 // CHECK19-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 10916 // CHECK19-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 10917 // CHECK19-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 10918 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 10919 // CHECK19-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 10920 // CHECK19-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 10921 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 10922 // CHECK19-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 10923 // CHECK19-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 10924 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 10925 // CHECK19-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 10926 // CHECK19-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 10927 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 10928 // CHECK19-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 10929 // CHECK19-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 10930 // CHECK19-NEXT: ret void 10931 // 10932 // 10933 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. 10934 // CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 10935 // CHECK19-NEXT: entry: 10936 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 10937 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 10938 // CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 10939 // CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 10940 // CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 10941 // CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 10942 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 10943 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 10944 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 10945 // CHECK19-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 10946 // CHECK19-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 10947 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 10948 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 10949 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 10950 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 10951 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 10952 // CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 10953 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 10954 // CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 10955 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 10956 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 10957 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 10958 // CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 10959 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 10960 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 10961 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 10962 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 10963 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 10964 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 10965 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 10966 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 10967 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 10968 // CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 10969 // CHECK19-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 10970 // CHECK19-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 10971 // CHECK19-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 10972 // CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 10973 // CHECK19-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 10974 // CHECK19-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 10975 // CHECK19-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 10976 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 10977 // CHECK19-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 10978 // CHECK19-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 10979 // CHECK19-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 10980 // CHECK19-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 10981 // CHECK19-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 10982 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 10983 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 10984 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 10985 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 10986 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 10987 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 10988 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 10989 // CHECK19-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 10990 // CHECK19-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 10991 // CHECK19-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 10992 // CHECK19: omp_offload.failed.i: 10993 // CHECK19-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 10994 // CHECK19-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 10995 // CHECK19-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25 10996 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 10997 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 10998 // CHECK19-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 10999 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 11000 // CHECK19-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 11001 // CHECK19-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 11002 // CHECK19-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 11003 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 11004 // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 11005 // CHECK19: .omp_outlined..1.exit: 11006 // CHECK19-NEXT: ret i32 0 11007 // 11008 // 11009 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 11010 // CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { 11011 // CHECK19-NEXT: entry: 11012 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11013 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11014 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11015 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11016 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 11017 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 11018 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 11019 // CHECK19-NEXT: ret void 11020 // 11021 // 11022 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 11023 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 11024 // CHECK19-NEXT: entry: 11025 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11026 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11027 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11028 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11029 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11030 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11031 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11032 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 11033 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11034 // CHECK19-NEXT: ret void 11035 // 11036 // 11037 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 11038 // CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 11039 // CHECK19-NEXT: entry: 11040 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11041 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11042 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11043 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11044 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 11045 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11046 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 11047 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11048 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 11049 // CHECK19-NEXT: ret void 11050 // 11051 // 11052 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 11053 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 11054 // CHECK19-NEXT: entry: 11055 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11056 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11057 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11058 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11059 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11060 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11061 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11062 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 11063 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 11064 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 11065 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 11066 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 11067 // CHECK19-NEXT: ret void 11068 // 11069 // 11070 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 11071 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 11072 // CHECK19-NEXT: entry: 11073 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11074 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11075 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11076 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11077 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11078 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11079 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11080 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11081 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 11082 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 11083 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11084 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11085 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 11086 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11087 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 11088 // CHECK19-NEXT: ret void 11089 // 11090 // 11091 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 11092 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 11093 // CHECK19-NEXT: entry: 11094 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11095 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11096 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11097 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11098 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11099 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11100 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11101 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11102 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11103 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11104 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 11105 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11106 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 11107 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 11108 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 11109 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 11110 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 11111 // CHECK19-NEXT: ret void 11112 // 11113 // 11114 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 11115 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 11116 // CHECK19-NEXT: entry: 11117 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11118 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11119 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11120 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11121 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11122 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11123 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11124 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11125 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11126 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11127 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11128 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11129 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11130 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11131 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11132 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11133 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11134 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11135 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11136 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11137 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11138 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11139 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11140 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11141 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11142 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11143 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11144 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 11145 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 11146 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 11147 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 11148 // CHECK19-NEXT: ret void 11149 // 11150 // 11151 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 11152 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 11153 // CHECK19-NEXT: entry: 11154 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11155 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11156 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11157 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11158 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11159 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11160 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11161 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11162 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11163 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11164 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11165 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11166 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11167 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11168 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11169 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11170 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11171 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11172 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11173 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11174 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11175 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11176 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11177 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11178 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11179 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11180 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11181 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11182 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11183 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11184 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 11185 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 11186 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11187 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 11188 // CHECK19-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 11189 // CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 11190 // CHECK19-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 11191 // CHECK19-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 11192 // CHECK19-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 11193 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 11194 // CHECK19-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 11195 // CHECK19-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 11196 // CHECK19-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 11197 // CHECK19-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 11198 // CHECK19-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 11199 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 11200 // CHECK19-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 11201 // CHECK19-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 11202 // CHECK19-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 11203 // CHECK19-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 11204 // CHECK19-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 11205 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 11206 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 11207 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 11208 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 11209 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 11210 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 11211 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 11212 // CHECK19-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 11213 // CHECK19-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 11214 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 11215 // CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 11216 // CHECK19-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 11217 // CHECK19-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 11218 // CHECK19-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 11219 // CHECK19-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 11220 // CHECK19-NEXT: ret void 11221 // 11222 // 11223 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 11224 // CHECK19-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 11225 // CHECK19-NEXT: entry: 11226 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 11227 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 11228 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 11229 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 11230 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 11231 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 11232 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 11233 // CHECK19-NEXT: ret void 11234 // 11235 // 11236 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..12 11237 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 11238 // CHECK19-NEXT: entry: 11239 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11240 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11241 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 11242 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 11243 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11244 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11245 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 11246 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 11247 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 11248 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 11249 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 11250 // CHECK19-NEXT: ret void 11251 // 11252 // 11253 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13 11254 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 11255 // CHECK19-NEXT: entry: 11256 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11257 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11258 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 11259 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11260 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11261 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 11262 // CHECK19-NEXT: ret void 11263 // 11264 // 11265 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 11266 // CHECK19-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 11267 // CHECK19-NEXT: entry: 11268 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 11269 // CHECK19-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 11270 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 11271 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 11272 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 11273 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 11274 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 11275 // CHECK19-NEXT: ret void 11276 // 11277 // 11278 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 11279 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 11280 // CHECK19-NEXT: entry: 11281 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11282 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11283 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 11284 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11285 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11286 // CHECK19-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 11287 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 11288 // CHECK19-NEXT: ret void 11289 // 11290 // 11291 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..17 11292 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 11293 // CHECK19-NEXT: entry: 11294 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11295 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11296 // CHECK19-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 11297 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11298 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11299 // CHECK19-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 11300 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 11301 // CHECK19-NEXT: ret void 11302 // 11303 // 11304 // CHECK19-LABEL: define {{[^@]+}}@_Z6bazzzziPi 11305 // CHECK19-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 11306 // CHECK19-NEXT: entry: 11307 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11308 // CHECK19-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 11309 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 11310 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 11311 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 11312 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11313 // CHECK19-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 11314 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 11315 // CHECK19-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11316 // CHECK19-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 11317 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 11318 // CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11319 // CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 11320 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 11321 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 11322 // CHECK19-NEXT: store i8* null, i8** [[TMP5]], align 4 11323 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11324 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11325 // CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11326 // CHECK19-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 11327 // CHECK19-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11328 // CHECK19: omp_offload.failed: 11329 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 11330 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 11331 // CHECK19: omp_offload.cont: 11332 // CHECK19-NEXT: ret void 11333 // 11334 // 11335 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 11336 // CHECK19-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 11337 // CHECK19-NEXT: entry: 11338 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11339 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11340 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11341 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 11342 // CHECK19-NEXT: ret void 11343 // 11344 // 11345 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..20 11346 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 11347 // CHECK19-NEXT: entry: 11348 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11349 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11350 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11351 // CHECK19-NEXT: [[F:%.*]] = alloca i32*, align 4 11352 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11353 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11354 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11355 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11356 // CHECK19-NEXT: ret void 11357 // 11358 // 11359 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari 11360 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 11361 // CHECK19-NEXT: entry: 11362 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11363 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 11364 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 11365 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11366 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 11367 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 11368 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 11369 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 11370 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 11371 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 11372 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 11373 // CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 11374 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 11375 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 11376 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 11377 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 11378 // CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 11379 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 11380 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 11381 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 11382 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 11383 // CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 11384 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 11385 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 11386 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 11387 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 11388 // CHECK19-NEXT: ret i32 [[TMP8]] 11389 // 11390 // 11391 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 11392 // CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 11393 // CHECK19-NEXT: entry: 11394 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11395 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11396 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 11397 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 11398 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 11399 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 11400 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 11401 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 11402 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 11403 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 11404 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11405 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11406 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11407 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 11408 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 11409 // CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 11410 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 11411 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 11412 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 11413 // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 11414 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 11415 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 11416 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 11417 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 11418 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 11419 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 11420 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 11421 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11422 // CHECK19: omp_if.then: 11423 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 11424 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 11425 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 11426 // CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 11427 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 11428 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i32 40, i1 false) 11429 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11430 // CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 11431 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 11432 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11433 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 11434 // CHECK19-NEXT: store double* [[A]], double** [[TMP14]], align 4 11435 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 11436 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 11437 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11438 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 11439 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 11440 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11441 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 11442 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 11443 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 11444 // CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 11445 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11446 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 11447 // CHECK19-NEXT: store i32 2, i32* [[TMP22]], align 4 11448 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11449 // CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 11450 // CHECK19-NEXT: store i32 2, i32* [[TMP24]], align 4 11451 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 11452 // CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 11453 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 11454 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 11455 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 11456 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 11457 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 11458 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 11459 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 11460 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 11461 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 11462 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 11463 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 11464 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 11465 // CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 11466 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 11467 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 11468 // CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 11469 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 11470 // CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 11471 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11472 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11473 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 11474 // CHECK19-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11475 // CHECK19-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 11476 // CHECK19-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11477 // CHECK19: omp_offload.failed: 11478 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 11479 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 11480 // CHECK19: omp_offload.cont: 11481 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 11482 // CHECK19: omp_if.else: 11483 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 11484 // CHECK19-NEXT: br label [[OMP_IF_END]] 11485 // CHECK19: omp_if.end: 11486 // CHECK19-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 11487 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 11488 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 11489 // CHECK19-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 11490 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 11491 // CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 11492 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 11493 // CHECK19-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 11494 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 11495 // CHECK19-NEXT: ret i32 [[ADD3]] 11496 // 11497 // 11498 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici 11499 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 11500 // CHECK19-NEXT: entry: 11501 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11502 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 11503 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 11504 // CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 11505 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 11506 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11507 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11508 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 11509 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 11510 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 11511 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 11512 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11513 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 11514 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 11515 // CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 11516 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 11517 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 11518 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 11519 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 11520 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11521 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 11522 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11523 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 11524 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 11525 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 11526 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 11527 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 11528 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 11529 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11530 // CHECK19: omp_if.then: 11531 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11532 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 11533 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 11534 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11535 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 11536 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 11537 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 11538 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 11539 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11540 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 11541 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 11542 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11543 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 11544 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 11545 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 11546 // CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 11547 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11548 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 11549 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 11550 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11551 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 11552 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 11553 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 11554 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 11555 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 11556 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 11557 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 11558 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 11559 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 11560 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 11561 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 11562 // CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 11563 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11564 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11565 // CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11566 // CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 11567 // CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11568 // CHECK19: omp_offload.failed: 11569 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 11570 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 11571 // CHECK19: omp_offload.cont: 11572 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 11573 // CHECK19: omp_if.else: 11574 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 11575 // CHECK19-NEXT: br label [[OMP_IF_END]] 11576 // CHECK19: omp_if.end: 11577 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 11578 // CHECK19-NEXT: ret i32 [[TMP31]] 11579 // 11580 // 11581 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 11582 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 11583 // CHECK19-NEXT: entry: 11584 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11585 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 11586 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 11587 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 11588 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11589 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11590 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 11591 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 11592 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 11593 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11594 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 11595 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 11596 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 11597 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 11598 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 11599 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 11600 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11601 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 11602 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11603 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 11604 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 11605 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11606 // CHECK19: omp_if.then: 11607 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11608 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 11609 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 11610 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11611 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 11612 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 11613 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 11614 // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 11615 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11616 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 11617 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 11618 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11619 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 11620 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 11621 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 11622 // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 11623 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11624 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 11625 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 11626 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11627 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 11628 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 11629 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 11630 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 11631 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11632 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11633 // CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11634 // CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 11635 // CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11636 // CHECK19: omp_offload.failed: 11637 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 11638 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 11639 // CHECK19: omp_offload.cont: 11640 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 11641 // CHECK19: omp_if.else: 11642 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 11643 // CHECK19-NEXT: br label [[OMP_IF_END]] 11644 // CHECK19: omp_if.end: 11645 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 11646 // CHECK19-NEXT: ret i32 [[TMP24]] 11647 // 11648 // 11649 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 11650 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 11651 // CHECK19-NEXT: entry: 11652 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11653 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11654 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11655 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11656 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11657 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 11658 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11659 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11660 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11661 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11662 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11663 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11664 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11665 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11666 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11667 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11668 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 11669 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 11670 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 11671 // CHECK19-NEXT: ret void 11672 // 11673 // 11674 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..23 11675 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 11676 // CHECK19-NEXT: entry: 11677 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11678 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11679 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11680 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11681 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11682 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11683 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11684 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11685 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11686 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11687 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11688 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11689 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11690 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11691 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11692 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11693 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11694 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11695 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11696 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 11697 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 11698 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11699 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 11700 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11701 // CHECK19-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 11702 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 11703 // CHECK19-NEXT: store double [[INC]], double* [[A3]], align 4 11704 // CHECK19-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 11705 // CHECK19-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 11706 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 11707 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 11708 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 11709 // CHECK19-NEXT: ret void 11710 // 11711 // 11712 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 11713 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11714 // CHECK19-NEXT: entry: 11715 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11716 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11717 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11718 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11719 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11720 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11721 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 11722 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11723 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11724 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11725 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11726 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11727 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11728 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11729 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11730 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11731 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11732 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11733 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11734 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 11735 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11736 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 11737 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 11738 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 11739 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 11740 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 11741 // CHECK19-NEXT: ret void 11742 // 11743 // 11744 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..26 11745 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11746 // CHECK19-NEXT: entry: 11747 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11748 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11749 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11750 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11751 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11752 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11753 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11754 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11755 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11756 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11757 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11758 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11759 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11760 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11761 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11762 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11763 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11764 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11765 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11766 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 11767 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 11768 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11769 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 11770 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 11771 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 11772 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 11773 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 11774 // CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 11775 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11776 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11777 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 11778 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 11779 // CHECK19-NEXT: ret void 11780 // 11781 // 11782 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 11783 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11784 // CHECK19-NEXT: entry: 11785 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11786 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11787 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11788 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11789 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11790 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11791 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11792 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11793 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11794 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11795 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11796 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11797 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11798 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11799 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11800 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 11801 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11802 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 11803 // CHECK19-NEXT: ret void 11804 // 11805 // 11806 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..29 11807 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 11808 // CHECK19-NEXT: entry: 11809 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11810 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11811 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11812 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11813 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11814 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11815 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11816 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11817 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11818 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11819 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11820 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11821 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11822 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11823 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11824 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11825 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 11826 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 11827 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 11828 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 11829 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11830 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11831 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 11832 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 11833 // CHECK19-NEXT: ret void 11834 // 11835 // 11836 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 11837 // CHECK19-SAME: () #[[ATTR4]] { 11838 // CHECK19-NEXT: entry: 11839 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 11840 // CHECK19-NEXT: ret void 11841 // 11842 // 11843 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi 11844 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 11845 // CHECK20-NEXT: entry: 11846 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 11847 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 11848 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 11849 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 11850 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 11851 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 11852 // CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 11853 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 11854 // CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 11855 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 11856 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 11857 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11858 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 11859 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 11860 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 11861 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 11862 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 11863 // CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 11864 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11865 // CHECK20-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 11866 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 11867 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 11868 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 11869 // CHECK20-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 11870 // CHECK20-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 11871 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 11872 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 11873 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 11874 // CHECK20-NEXT: [[A_CASTED17:%.*]] = alloca i32, align 4 11875 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [9 x i8*], align 4 11876 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [9 x i8*], align 4 11877 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [9 x i8*], align 4 11878 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 11879 // CHECK20-NEXT: [[NN:%.*]] = alloca i32, align 4 11880 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 11881 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS27:%.*]] = alloca [1 x i8*], align 4 11882 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS28:%.*]] = alloca [1 x i8*], align 4 11883 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS29:%.*]] = alloca [1 x i8*], align 4 11884 // CHECK20-NEXT: [[NN_CASTED32:%.*]] = alloca i32, align 4 11885 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS33:%.*]] = alloca [1 x i8*], align 4 11886 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS34:%.*]] = alloca [1 x i8*], align 4 11887 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS35:%.*]] = alloca [1 x i8*], align 4 11888 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 11889 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 11890 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 11891 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 11892 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 11893 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 11894 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 11895 // CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 11896 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 11897 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 11898 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 11899 // CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 11900 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 11901 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 11902 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 11903 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 11904 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 11905 // CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 11906 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11907 // CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 11908 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11909 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11910 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 11911 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 11912 // CHECK20-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 11913 // CHECK20-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 11914 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 11915 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11916 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 11917 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 11918 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11919 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 11920 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 11921 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 11922 // CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 11923 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 11924 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 11925 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 11926 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 11927 // CHECK20-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 11928 // CHECK20-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 11929 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 11930 // CHECK20-NEXT: store i8* null, i8** [[TMP22]], align 4 11931 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 11932 // CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 11933 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 11934 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 11935 // CHECK20-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 11936 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 11937 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 11938 // CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 11939 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 11940 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 11941 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 11942 // CHECK20-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 11943 // CHECK20-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 11944 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 11945 // CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 11946 // CHECK20-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 11947 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 11948 // CHECK20-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 11949 // CHECK20-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 11950 // CHECK20-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 11951 // CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 11952 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 11953 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 11954 // CHECK20-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 11955 // CHECK20-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 11956 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 11957 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 11958 // CHECK20-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 11959 // CHECK20-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 11960 // CHECK20-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 11961 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 11962 // CHECK20-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 11963 // CHECK20-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 11964 // CHECK20-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 11965 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 11966 // CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 11967 // CHECK20-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 11968 // CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 11969 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 11970 // CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 11971 // CHECK20-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 11972 // CHECK20-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 11973 // CHECK20-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 11974 // CHECK20-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 11975 // CHECK20-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 11976 // CHECK20-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 11977 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 11978 // CHECK20-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 11979 // CHECK20-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 11980 // CHECK20-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 11981 // CHECK20-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 11982 // CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 11983 // CHECK20-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 11984 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 11985 // CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 11986 // CHECK20-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 11987 // CHECK20-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 11988 // CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 11989 // CHECK20-NEXT: store i8* null, i8** [[TMP63]], align 4 11990 // CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 11991 // CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 11992 // CHECK20-NEXT: [[TMP66:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, i32 1, i8** [[TMP64]], i8** [[TMP65]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 11993 // CHECK20-NEXT: [[TMP67:%.*]] = icmp ne i32 [[TMP66]], 0 11994 // CHECK20-NEXT: br i1 [[TMP67]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 11995 // CHECK20: omp_offload.failed: 11996 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 11997 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 11998 // CHECK20: omp_offload.cont: 11999 // CHECK20-NEXT: [[TMP68:%.*]] = load i32, i32* [[A]], align 4 12000 // CHECK20-NEXT: store i32 [[TMP68]], i32* [[A_CASTED9]], align 4 12001 // CHECK20-NEXT: [[TMP69:%.*]] = load i32, i32* [[A_CASTED9]], align 4 12002 // CHECK20-NEXT: [[TMP70:%.*]] = load i16, i16* [[AA]], align 2 12003 // CHECK20-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 12004 // CHECK20-NEXT: store i16 [[TMP70]], i16* [[CONV11]], align 2 12005 // CHECK20-NEXT: [[TMP71:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 12006 // CHECK20-NEXT: [[TMP72:%.*]] = load i32, i32* [[N_ADDR]], align 4 12007 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP72]], 10 12008 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12009 // CHECK20: omp_if.then: 12010 // CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 12011 // CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to i32* 12012 // CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP74]], align 4 12013 // CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 12014 // CHECK20-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to i32* 12015 // CHECK20-NEXT: store i32 [[TMP69]], i32* [[TMP76]], align 4 12016 // CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 12017 // CHECK20-NEXT: store i8* null, i8** [[TMP77]], align 4 12018 // CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 12019 // CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 12020 // CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP79]], align 4 12021 // CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 12022 // CHECK20-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 12023 // CHECK20-NEXT: store i32 [[TMP71]], i32* [[TMP81]], align 4 12024 // CHECK20-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 12025 // CHECK20-NEXT: store i8* null, i8** [[TMP82]], align 4 12026 // CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 12027 // CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 12028 // CHECK20-NEXT: [[TMP85:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, i32 2, i8** [[TMP83]], i8** [[TMP84]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12029 // CHECK20-NEXT: [[TMP86:%.*]] = icmp ne i32 [[TMP85]], 0 12030 // CHECK20-NEXT: br i1 [[TMP86]], label [[OMP_OFFLOAD_FAILED15:%.*]], label [[OMP_OFFLOAD_CONT16:%.*]] 12031 // CHECK20: omp_offload.failed15: 12032 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 12033 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT16]] 12034 // CHECK20: omp_offload.cont16: 12035 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 12036 // CHECK20: omp_if.else: 12037 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP69]], i32 [[TMP71]]) #[[ATTR3]] 12038 // CHECK20-NEXT: br label [[OMP_IF_END]] 12039 // CHECK20: omp_if.end: 12040 // CHECK20-NEXT: [[TMP87:%.*]] = load i32, i32* [[A]], align 4 12041 // CHECK20-NEXT: store i32 [[TMP87]], i32* [[A_CASTED17]], align 4 12042 // CHECK20-NEXT: [[TMP88:%.*]] = load i32, i32* [[A_CASTED17]], align 4 12043 // CHECK20-NEXT: [[TMP89:%.*]] = load i32, i32* [[N_ADDR]], align 4 12044 // CHECK20-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP89]], 20 12045 // CHECK20-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 12046 // CHECK20: omp_if.then19: 12047 // CHECK20-NEXT: [[TMP90:%.*]] = mul nuw i32 [[TMP1]], 4 12048 // CHECK20-NEXT: [[TMP91:%.*]] = sext i32 [[TMP90]] to i64 12049 // CHECK20-NEXT: [[TMP92:%.*]] = mul nuw i32 5, [[TMP3]] 12050 // CHECK20-NEXT: [[TMP93:%.*]] = mul nuw i32 [[TMP92]], 8 12051 // CHECK20-NEXT: [[TMP94:%.*]] = sext i32 [[TMP93]] to i64 12052 // CHECK20-NEXT: [[TMP95:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 12053 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP95]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) 12054 // CHECK20-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 12055 // CHECK20-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* 12056 // CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP97]], align 4 12057 // CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 12058 // CHECK20-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 12059 // CHECK20-NEXT: store i32 [[TMP88]], i32* [[TMP99]], align 4 12060 // CHECK20-NEXT: [[TMP100:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 0 12061 // CHECK20-NEXT: store i8* null, i8** [[TMP100]], align 4 12062 // CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 12063 // CHECK20-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to [10 x float]** 12064 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP102]], align 4 12065 // CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 12066 // CHECK20-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to [10 x float]** 12067 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP104]], align 4 12068 // CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 1 12069 // CHECK20-NEXT: store i8* null, i8** [[TMP105]], align 4 12070 // CHECK20-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 12071 // CHECK20-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to i32* 12072 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP107]], align 4 12073 // CHECK20-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 12074 // CHECK20-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to i32* 12075 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP109]], align 4 12076 // CHECK20-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 2 12077 // CHECK20-NEXT: store i8* null, i8** [[TMP110]], align 4 12078 // CHECK20-NEXT: [[TMP111:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 12079 // CHECK20-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to float** 12080 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP112]], align 4 12081 // CHECK20-NEXT: [[TMP113:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 12082 // CHECK20-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to float** 12083 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP114]], align 4 12084 // CHECK20-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 12085 // CHECK20-NEXT: store i64 [[TMP91]], i64* [[TMP115]], align 4 12086 // CHECK20-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 3 12087 // CHECK20-NEXT: store i8* null, i8** [[TMP116]], align 4 12088 // CHECK20-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 12089 // CHECK20-NEXT: [[TMP118:%.*]] = bitcast i8** [[TMP117]] to [5 x [10 x double]]** 12090 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP118]], align 4 12091 // CHECK20-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 12092 // CHECK20-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [5 x [10 x double]]** 12093 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP120]], align 4 12094 // CHECK20-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 4 12095 // CHECK20-NEXT: store i8* null, i8** [[TMP121]], align 4 12096 // CHECK20-NEXT: [[TMP122:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 12097 // CHECK20-NEXT: [[TMP123:%.*]] = bitcast i8** [[TMP122]] to i32* 12098 // CHECK20-NEXT: store i32 5, i32* [[TMP123]], align 4 12099 // CHECK20-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 12100 // CHECK20-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* 12101 // CHECK20-NEXT: store i32 5, i32* [[TMP125]], align 4 12102 // CHECK20-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 5 12103 // CHECK20-NEXT: store i8* null, i8** [[TMP126]], align 4 12104 // CHECK20-NEXT: [[TMP127:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 12105 // CHECK20-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to i32* 12106 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP128]], align 4 12107 // CHECK20-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 12108 // CHECK20-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to i32* 12109 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP130]], align 4 12110 // CHECK20-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 6 12111 // CHECK20-NEXT: store i8* null, i8** [[TMP131]], align 4 12112 // CHECK20-NEXT: [[TMP132:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 12113 // CHECK20-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to double** 12114 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP133]], align 4 12115 // CHECK20-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 12116 // CHECK20-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to double** 12117 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP135]], align 4 12118 // CHECK20-NEXT: [[TMP136:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 12119 // CHECK20-NEXT: store i64 [[TMP94]], i64* [[TMP136]], align 4 12120 // CHECK20-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 7 12121 // CHECK20-NEXT: store i8* null, i8** [[TMP137]], align 4 12122 // CHECK20-NEXT: [[TMP138:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 12123 // CHECK20-NEXT: [[TMP139:%.*]] = bitcast i8** [[TMP138]] to %struct.TT** 12124 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP139]], align 4 12125 // CHECK20-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 12126 // CHECK20-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to %struct.TT** 12127 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP141]], align 4 12128 // CHECK20-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i32 0, i32 8 12129 // CHECK20-NEXT: store i8* null, i8** [[TMP142]], align 4 12130 // CHECK20-NEXT: [[TMP143:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 12131 // CHECK20-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 12132 // CHECK20-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 12133 // CHECK20-NEXT: [[TMP146:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, i32 9, i8** [[TMP143]], i8** [[TMP144]], i64* [[TMP145]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12134 // CHECK20-NEXT: [[TMP147:%.*]] = icmp ne i32 [[TMP146]], 0 12135 // CHECK20-NEXT: br i1 [[TMP147]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 12136 // CHECK20: omp_offload.failed23: 12137 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 12138 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT24]] 12139 // CHECK20: omp_offload.cont24: 12140 // CHECK20-NEXT: br label [[OMP_IF_END26:%.*]] 12141 // CHECK20: omp_if.else25: 12142 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP88]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 12143 // CHECK20-NEXT: br label [[OMP_IF_END26]] 12144 // CHECK20: omp_if.end26: 12145 // CHECK20-NEXT: store i32 0, i32* [[NN]], align 4 12146 // CHECK20-NEXT: [[TMP148:%.*]] = load i32, i32* [[NN]], align 4 12147 // CHECK20-NEXT: store i32 [[TMP148]], i32* [[NN_CASTED]], align 4 12148 // CHECK20-NEXT: [[TMP149:%.*]] = load i32, i32* [[NN_CASTED]], align 4 12149 // CHECK20-NEXT: [[TMP150:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 12150 // CHECK20-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to i32* 12151 // CHECK20-NEXT: store i32 [[TMP149]], i32* [[TMP151]], align 4 12152 // CHECK20-NEXT: [[TMP152:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 12153 // CHECK20-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to i32* 12154 // CHECK20-NEXT: store i32 [[TMP149]], i32* [[TMP153]], align 4 12155 // CHECK20-NEXT: [[TMP154:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS29]], i32 0, i32 0 12156 // CHECK20-NEXT: store i8* null, i8** [[TMP154]], align 4 12157 // CHECK20-NEXT: [[TMP155:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS27]], i32 0, i32 0 12158 // CHECK20-NEXT: [[TMP156:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS28]], i32 0, i32 0 12159 // CHECK20-NEXT: [[TMP157:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, i32 1, i8** [[TMP155]], i8** [[TMP156]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12160 // CHECK20-NEXT: [[TMP158:%.*]] = icmp ne i32 [[TMP157]], 0 12161 // CHECK20-NEXT: br i1 [[TMP158]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 12162 // CHECK20: omp_offload.failed30: 12163 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP149]]) #[[ATTR3]] 12164 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT31]] 12165 // CHECK20: omp_offload.cont31: 12166 // CHECK20-NEXT: [[TMP159:%.*]] = load i32, i32* [[NN]], align 4 12167 // CHECK20-NEXT: store i32 [[TMP159]], i32* [[NN_CASTED32]], align 4 12168 // CHECK20-NEXT: [[TMP160:%.*]] = load i32, i32* [[NN_CASTED32]], align 4 12169 // CHECK20-NEXT: [[TMP161:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 12170 // CHECK20-NEXT: [[TMP162:%.*]] = bitcast i8** [[TMP161]] to i32* 12171 // CHECK20-NEXT: store i32 [[TMP160]], i32* [[TMP162]], align 4 12172 // CHECK20-NEXT: [[TMP163:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 12173 // CHECK20-NEXT: [[TMP164:%.*]] = bitcast i8** [[TMP163]] to i32* 12174 // CHECK20-NEXT: store i32 [[TMP160]], i32* [[TMP164]], align 4 12175 // CHECK20-NEXT: [[TMP165:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS35]], i32 0, i32 0 12176 // CHECK20-NEXT: store i8* null, i8** [[TMP165]], align 4 12177 // CHECK20-NEXT: [[TMP166:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS33]], i32 0, i32 0 12178 // CHECK20-NEXT: [[TMP167:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS34]], i32 0, i32 0 12179 // CHECK20-NEXT: [[TMP168:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, i32 1, i8** [[TMP166]], i8** [[TMP167]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12180 // CHECK20-NEXT: [[TMP169:%.*]] = icmp ne i32 [[TMP168]], 0 12181 // CHECK20-NEXT: br i1 [[TMP169]], label [[OMP_OFFLOAD_FAILED36:%.*]], label [[OMP_OFFLOAD_CONT37:%.*]] 12182 // CHECK20: omp_offload.failed36: 12183 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP160]]) #[[ATTR3]] 12184 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT37]] 12185 // CHECK20: omp_offload.cont37: 12186 // CHECK20-NEXT: [[TMP170:%.*]] = load i32, i32* [[A]], align 4 12187 // CHECK20-NEXT: [[TMP171:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 12188 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP171]]) 12189 // CHECK20-NEXT: ret i32 [[TMP170]] 12190 // 12191 // 12192 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 12193 // CHECK20-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 12194 // CHECK20-NEXT: entry: 12195 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12196 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12197 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 12198 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12199 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 12200 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12201 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12202 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 12203 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12204 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12205 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 12206 // CHECK20-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 12207 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 12208 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12209 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 12210 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12211 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 12212 // CHECK20-NEXT: ret void 12213 // 12214 // 12215 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 12216 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 12217 // CHECK20-NEXT: entry: 12218 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12219 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12220 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12221 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12222 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12223 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12224 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12225 // CHECK20-NEXT: ret void 12226 // 12227 // 12228 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_privates_map. 12229 // CHECK20-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 12230 // CHECK20-NEXT: entry: 12231 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 12232 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 12233 // CHECK20-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 12234 // CHECK20-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 12235 // CHECK20-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 12236 // CHECK20-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 12237 // CHECK20-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 12238 // CHECK20-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 12239 // CHECK20-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 12240 // CHECK20-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 12241 // CHECK20-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 12242 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 12243 // CHECK20-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 12244 // CHECK20-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 12245 // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 12246 // CHECK20-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 12247 // CHECK20-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 12248 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 12249 // CHECK20-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 12250 // CHECK20-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 12251 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 12252 // CHECK20-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 12253 // CHECK20-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 12254 // CHECK20-NEXT: ret void 12255 // 12256 // 12257 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. 12258 // CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 12259 // CHECK20-NEXT: entry: 12260 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 12261 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 12262 // CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 12263 // CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 12264 // CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 12265 // CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 12266 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 12267 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 12268 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 12269 // CHECK20-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 12270 // CHECK20-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 12271 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 12272 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 12273 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 12274 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 12275 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 12276 // CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 12277 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 12278 // CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 12279 // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 12280 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 12281 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 12282 // CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 12283 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 12284 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 12285 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 12286 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 12287 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 12288 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 12289 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 12290 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 12291 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 12292 // CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 12293 // CHECK20-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 12294 // CHECK20-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 12295 // CHECK20-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 12296 // CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 12297 // CHECK20-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 12298 // CHECK20-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 12299 // CHECK20-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 12300 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 12301 // CHECK20-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 12302 // CHECK20-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 12303 // CHECK20-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 12304 // CHECK20-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 12305 // CHECK20-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 12306 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 12307 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 12308 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 12309 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 12310 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 12311 // CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 12312 // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 12313 // CHECK20-NEXT: [[TMP27:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP25]], i32 [[TMP26]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 12314 // CHECK20-NEXT: [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0 12315 // CHECK20-NEXT: br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 12316 // CHECK20: omp_offload.failed.i: 12317 // CHECK20-NEXT: [[TMP29:%.*]] = load i16, i16* [[TMP16]], align 2 12318 // CHECK20-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 12319 // CHECK20-NEXT: store i16 [[TMP29]], i16* [[CONV_I]], align 2, !noalias !25 12320 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 12321 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[TMP23]], align 4 12322 // CHECK20-NEXT: store i32 [[TMP31]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 12323 // CHECK20-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 12324 // CHECK20-NEXT: [[TMP33:%.*]] = load i32, i32* [[TMP24]], align 4 12325 // CHECK20-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 12326 // CHECK20-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 12327 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP30]], i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR3]] 12328 // CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 12329 // CHECK20: .omp_outlined..1.exit: 12330 // CHECK20-NEXT: ret i32 0 12331 // 12332 // 12333 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 12334 // CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { 12335 // CHECK20-NEXT: entry: 12336 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12337 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12338 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12339 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 12340 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 12341 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 12342 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 12343 // CHECK20-NEXT: ret void 12344 // 12345 // 12346 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 12347 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 12348 // CHECK20-NEXT: entry: 12349 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12350 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12351 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12352 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12353 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12354 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12355 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 12356 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 12357 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 12358 // CHECK20-NEXT: ret void 12359 // 12360 // 12361 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 12362 // CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 12363 // CHECK20-NEXT: entry: 12364 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12365 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12366 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12367 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12368 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 12369 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12370 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 12371 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12372 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 12373 // CHECK20-NEXT: ret void 12374 // 12375 // 12376 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 12377 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 12378 // CHECK20-NEXT: entry: 12379 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12380 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12381 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12382 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12383 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12384 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12385 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12386 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 12387 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 12388 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 12389 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 12390 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 12391 // CHECK20-NEXT: ret void 12392 // 12393 // 12394 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 12395 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 12396 // CHECK20-NEXT: entry: 12397 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12398 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12399 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12400 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12401 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12402 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12403 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12404 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 12405 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 12406 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 12407 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 12408 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12409 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 12410 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12411 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 12412 // CHECK20-NEXT: ret void 12413 // 12414 // 12415 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..6 12416 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 12417 // CHECK20-NEXT: entry: 12418 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12419 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12420 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12421 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12422 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12423 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12424 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12425 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12426 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12427 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 12428 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 12429 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 12430 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 12431 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 12432 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 12433 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 12434 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 12435 // CHECK20-NEXT: ret void 12436 // 12437 // 12438 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 12439 // CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 12440 // CHECK20-NEXT: entry: 12441 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12442 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 12443 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12444 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 12445 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 12446 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12447 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 12448 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 12449 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 12450 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12451 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12452 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 12453 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12454 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 12455 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 12456 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12457 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 12458 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 12459 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 12460 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 12461 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12462 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 12463 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 12464 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12465 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 12466 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 12467 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 12468 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 12469 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 12470 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 12471 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 12472 // CHECK20-NEXT: ret void 12473 // 12474 // 12475 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 12476 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 12477 // CHECK20-NEXT: entry: 12478 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12479 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12480 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12481 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 12482 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12483 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 12484 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 12485 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12486 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 12487 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 12488 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 12489 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12490 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12491 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12492 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 12493 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12494 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 12495 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 12496 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12497 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 12498 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 12499 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 12500 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 12501 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12502 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 12503 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 12504 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12505 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 12506 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 12507 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 12508 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 12509 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 12510 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 12511 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 12512 // CHECK20-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 12513 // CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 12514 // CHECK20-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 12515 // CHECK20-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 12516 // CHECK20-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 12517 // CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 12518 // CHECK20-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 12519 // CHECK20-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 12520 // CHECK20-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 12521 // CHECK20-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 12522 // CHECK20-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 12523 // CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 12524 // CHECK20-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 12525 // CHECK20-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 12526 // CHECK20-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 12527 // CHECK20-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 12528 // CHECK20-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 12529 // CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 12530 // CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 12531 // CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 12532 // CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 12533 // CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 12534 // CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 12535 // CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 12536 // CHECK20-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 12537 // CHECK20-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 12538 // CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 12539 // CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 12540 // CHECK20-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 12541 // CHECK20-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 12542 // CHECK20-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 12543 // CHECK20-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 12544 // CHECK20-NEXT: ret void 12545 // 12546 // 12547 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 12548 // CHECK20-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 12549 // CHECK20-NEXT: entry: 12550 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 12551 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 12552 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 12553 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 12554 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 12555 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 12556 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 12557 // CHECK20-NEXT: ret void 12558 // 12559 // 12560 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..12 12561 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 12562 // CHECK20-NEXT: entry: 12563 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12564 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12565 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 12566 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 12567 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12568 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12569 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 12570 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 12571 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 12572 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 12573 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 12574 // CHECK20-NEXT: ret void 12575 // 12576 // 12577 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13 12578 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 12579 // CHECK20-NEXT: entry: 12580 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12581 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12582 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 12583 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12584 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12585 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 12586 // CHECK20-NEXT: ret void 12587 // 12588 // 12589 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 12590 // CHECK20-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 12591 // CHECK20-NEXT: entry: 12592 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 12593 // CHECK20-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 12594 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 12595 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 12596 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 12597 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 12598 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 12599 // CHECK20-NEXT: ret void 12600 // 12601 // 12602 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 12603 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 12604 // CHECK20-NEXT: entry: 12605 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12606 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12607 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 12608 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12609 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12610 // CHECK20-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 12611 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 12612 // CHECK20-NEXT: ret void 12613 // 12614 // 12615 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..17 12616 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 12617 // CHECK20-NEXT: entry: 12618 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12619 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12620 // CHECK20-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 12621 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12622 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12623 // CHECK20-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 12624 // CHECK20-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 12625 // CHECK20-NEXT: ret void 12626 // 12627 // 12628 // CHECK20-LABEL: define {{[^@]+}}@_Z6bazzzziPi 12629 // CHECK20-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 12630 // CHECK20-NEXT: entry: 12631 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12632 // CHECK20-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 12633 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 12634 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 12635 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 12636 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12637 // CHECK20-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 12638 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12639 // CHECK20-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12640 // CHECK20-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 12641 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 12642 // CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12643 // CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 12644 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 12645 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 12646 // CHECK20-NEXT: store i8* null, i8** [[TMP5]], align 4 12647 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12648 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12649 // CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, i32 1, i8** [[TMP6]], i8** [[TMP7]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12650 // CHECK20-NEXT: [[TMP9:%.*]] = icmp ne i32 [[TMP8]], 0 12651 // CHECK20-NEXT: br i1 [[TMP9]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12652 // CHECK20: omp_offload.failed: 12653 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 12654 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 12655 // CHECK20: omp_offload.cont: 12656 // CHECK20-NEXT: ret void 12657 // 12658 // 12659 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 12660 // CHECK20-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 12661 // CHECK20-NEXT: entry: 12662 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12663 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12664 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12665 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 12666 // CHECK20-NEXT: ret void 12667 // 12668 // 12669 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..20 12670 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 12671 // CHECK20-NEXT: entry: 12672 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12673 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12674 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12675 // CHECK20-NEXT: [[F:%.*]] = alloca i32*, align 4 12676 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12677 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12678 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12679 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12680 // CHECK20-NEXT: ret void 12681 // 12682 // 12683 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari 12684 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 12685 // CHECK20-NEXT: entry: 12686 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12687 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 12688 // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 12689 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12690 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 12691 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12692 // CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 12693 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 12694 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 12695 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 12696 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 12697 // CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 12698 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 12699 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 12700 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 12701 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 12702 // CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 12703 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 12704 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 12705 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 12706 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 12707 // CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 12708 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 12709 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 12710 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 12711 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 12712 // CHECK20-NEXT: ret i32 [[TMP8]] 12713 // 12714 // 12715 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 12716 // CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 12717 // CHECK20-NEXT: entry: 12718 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 12719 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12720 // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 12721 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 12722 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 12723 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 12724 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 12725 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 12726 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 12727 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 12728 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 12729 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12730 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 12731 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 12732 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 12733 // CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 12734 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 12735 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 12736 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 12737 // CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 12738 // CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 12739 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 12740 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 12741 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 12742 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 12743 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 12744 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 12745 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12746 // CHECK20: omp_if.then: 12747 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 12748 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 12749 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 12750 // CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 12751 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 12752 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i32 40, i1 false) 12753 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12754 // CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 12755 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 12756 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12757 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 12758 // CHECK20-NEXT: store double* [[A]], double** [[TMP14]], align 4 12759 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 12760 // CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 12761 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12762 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 12763 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 12764 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12765 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 12766 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 12767 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 12768 // CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 12769 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12770 // CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 12771 // CHECK20-NEXT: store i32 2, i32* [[TMP22]], align 4 12772 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12773 // CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 12774 // CHECK20-NEXT: store i32 2, i32* [[TMP24]], align 4 12775 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 12776 // CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 12777 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 12778 // CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 12779 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 12780 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 12781 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 12782 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 12783 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 12784 // CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 12785 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 12786 // CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 12787 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 12788 // CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 12789 // CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 12790 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 12791 // CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 12792 // CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 12793 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 12794 // CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 12795 // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12796 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12797 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 12798 // CHECK20-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12799 // CHECK20-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 12800 // CHECK20-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12801 // CHECK20: omp_offload.failed: 12802 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 12803 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 12804 // CHECK20: omp_offload.cont: 12805 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 12806 // CHECK20: omp_if.else: 12807 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 12808 // CHECK20-NEXT: br label [[OMP_IF_END]] 12809 // CHECK20: omp_if.end: 12810 // CHECK20-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 12811 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 12812 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 12813 // CHECK20-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 12814 // CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 12815 // CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 12816 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 12817 // CHECK20-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 12818 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 12819 // CHECK20-NEXT: ret i32 [[ADD3]] 12820 // 12821 // 12822 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici 12823 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 12824 // CHECK20-NEXT: entry: 12825 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12826 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 12827 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 12828 // CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 12829 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 12830 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12831 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12832 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 12833 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 12834 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 12835 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 12836 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12837 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 12838 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 12839 // CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 12840 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 12841 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 12842 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 12843 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 12844 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12845 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 12846 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12847 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 12848 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 12849 // CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 12850 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 12851 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 12852 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 12853 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12854 // CHECK20: omp_if.then: 12855 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12856 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 12857 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 12858 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12859 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 12860 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 12861 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 12862 // CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 12863 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12864 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 12865 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 12866 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12867 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 12868 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 12869 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 12870 // CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 12871 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12872 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 12873 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 12874 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12875 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 12876 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 12877 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 12878 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 12879 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 12880 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 12881 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 12882 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 12883 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 12884 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 12885 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 12886 // CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 12887 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12888 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12889 // CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12890 // CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 12891 // CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12892 // CHECK20: omp_offload.failed: 12893 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 12894 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 12895 // CHECK20: omp_offload.cont: 12896 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 12897 // CHECK20: omp_if.else: 12898 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 12899 // CHECK20-NEXT: br label [[OMP_IF_END]] 12900 // CHECK20: omp_if.end: 12901 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 12902 // CHECK20-NEXT: ret i32 [[TMP31]] 12903 // 12904 // 12905 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 12906 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 12907 // CHECK20-NEXT: entry: 12908 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 12909 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 12910 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 12911 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 12912 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12913 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12914 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 12915 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 12916 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 12917 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 12918 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 12919 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 12920 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 12921 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 12922 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 12923 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 12924 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12925 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 12926 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12927 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 12928 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 12929 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12930 // CHECK20: omp_if.then: 12931 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12932 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 12933 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 12934 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12935 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 12936 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 12937 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 12938 // CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 12939 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 12940 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 12941 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 12942 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 12943 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 12944 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 12945 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 12946 // CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 12947 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 12948 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 12949 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 12950 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 12951 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 12952 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 12953 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 12954 // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 12955 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 12956 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 12957 // CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) 12958 // CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 12959 // CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 12960 // CHECK20: omp_offload.failed: 12961 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 12962 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 12963 // CHECK20: omp_offload.cont: 12964 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 12965 // CHECK20: omp_if.else: 12966 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 12967 // CHECK20-NEXT: br label [[OMP_IF_END]] 12968 // CHECK20: omp_if.end: 12969 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 12970 // CHECK20-NEXT: ret i32 [[TMP24]] 12971 // 12972 // 12973 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 12974 // CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 12975 // CHECK20-NEXT: entry: 12976 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 12977 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 12978 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12979 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12980 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 12981 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 12982 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 12983 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 12984 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12985 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12986 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 12987 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 12988 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12989 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12990 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 12991 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 12992 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 12993 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 12994 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 12995 // CHECK20-NEXT: ret void 12996 // 12997 // 12998 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..23 12999 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 13000 // CHECK20-NEXT: entry: 13001 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13002 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13003 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 13004 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 13005 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 13006 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 13007 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 13008 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13009 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13010 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 13011 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 13012 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 13013 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 13014 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 13015 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 13016 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 13017 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 13018 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 13019 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 13020 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 13021 // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 13022 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 13023 // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 13024 // CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 13025 // CHECK20-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 13026 // CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 13027 // CHECK20-NEXT: store double [[INC]], double* [[A3]], align 4 13028 // CHECK20-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 13029 // CHECK20-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 13030 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 13031 // CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 13032 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 13033 // CHECK20-NEXT: ret void 13034 // 13035 // 13036 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 13037 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13038 // CHECK20-NEXT: entry: 13039 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13040 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13041 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 13042 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 13043 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13044 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13045 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 13046 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13047 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13048 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 13049 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 13050 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13051 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 13052 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 13053 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13054 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 13055 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 13056 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 13057 // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13058 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 13059 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13060 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 13061 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 13062 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 13063 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 13064 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 13065 // CHECK20-NEXT: ret void 13066 // 13067 // 13068 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..26 13069 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13070 // CHECK20-NEXT: entry: 13071 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13072 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13073 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13074 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13075 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 13076 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 13077 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13078 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13079 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13080 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13081 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 13082 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 13083 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13084 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 13085 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 13086 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13087 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 13088 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 13089 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 13090 // CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 13091 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 13092 // CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 13093 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 13094 // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 13095 // CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 13096 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 13097 // CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 13098 // CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 13099 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 13100 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 13101 // CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 13102 // CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 13103 // CHECK20-NEXT: ret void 13104 // 13105 // 13106 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 13107 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13108 // CHECK20-NEXT: entry: 13109 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13110 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13111 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 13112 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 13113 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 13114 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13115 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13116 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 13117 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13118 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 13119 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13120 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 13121 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 13122 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 13123 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 13124 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 13125 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 13126 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 13127 // CHECK20-NEXT: ret void 13128 // 13129 // 13130 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..29 13131 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 13132 // CHECK20-NEXT: entry: 13133 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 13134 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 13135 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 13136 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 13137 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 13138 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 13139 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 13140 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 13141 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 13142 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 13143 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 13144 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 13145 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 13146 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 13147 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 13148 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 13149 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 13150 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 13151 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 13152 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 13153 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 13154 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 13155 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 13156 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 13157 // CHECK20-NEXT: ret void 13158 // 13159 // 13160 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 13161 // CHECK20-SAME: () #[[ATTR4]] { 13162 // CHECK20-NEXT: entry: 13163 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 13164 // CHECK20-NEXT: ret void 13165 // 13166 // 13167 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 13168 // CHECK25-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 13169 // CHECK25-NEXT: entry: 13170 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13171 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 13172 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 13173 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13174 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 13175 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13176 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 13177 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 13178 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13179 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 13180 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 13181 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 13182 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 13183 // CHECK25-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 13184 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 13185 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13186 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 13187 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13188 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 13189 // CHECK25-NEXT: ret void 13190 // 13191 // 13192 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. 13193 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13194 // CHECK25-NEXT: entry: 13195 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13196 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13197 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13198 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13199 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13200 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13201 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13202 // CHECK25-NEXT: ret void 13203 // 13204 // 13205 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 13206 // CHECK25-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13207 // CHECK25-NEXT: entry: 13208 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13209 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13210 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13211 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13212 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 13213 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13214 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 13215 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13216 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 13217 // CHECK25-NEXT: ret void 13218 // 13219 // 13220 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 13221 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13222 // CHECK25-NEXT: entry: 13223 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13224 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13225 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13226 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13227 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13228 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13229 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13230 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 13231 // CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 13232 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 13233 // CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 13234 // CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 13235 // CHECK25-NEXT: ret void 13236 // 13237 // 13238 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 13239 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13240 // CHECK25-NEXT: entry: 13241 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13242 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13243 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 13244 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13245 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13246 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13247 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13248 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13249 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13250 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 13251 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 13252 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 13253 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 13254 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13255 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 13256 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13257 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 13258 // CHECK25-NEXT: ret void 13259 // 13260 // 13261 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 13262 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13263 // CHECK25-NEXT: entry: 13264 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13265 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13266 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13267 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13268 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13269 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13270 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13271 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13272 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13273 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13274 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13275 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 13276 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 13277 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 13278 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 13279 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 13280 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 13281 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 13282 // CHECK25-NEXT: ret void 13283 // 13284 // 13285 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 13286 // CHECK25-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 13287 // CHECK25-NEXT: entry: 13288 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13289 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 13290 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 13291 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 13292 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 13293 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 13294 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 13295 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 13296 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 13297 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 13298 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13299 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 13300 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 13301 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 13302 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 13303 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 13304 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 13305 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 13306 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 13307 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13308 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 13309 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 13310 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 13311 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 13312 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 13313 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 13314 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 13315 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 13316 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 13317 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 13318 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 13319 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 13320 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 13321 // CHECK25-NEXT: ret void 13322 // 13323 // 13324 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 13325 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 13326 // CHECK25-NEXT: entry: 13327 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13328 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13329 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13330 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 13331 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 13332 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 13333 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 13334 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 13335 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 13336 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 13337 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 13338 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13339 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13340 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13341 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 13342 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 13343 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 13344 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 13345 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 13346 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 13347 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 13348 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 13349 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13350 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 13351 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 13352 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 13353 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 13354 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 13355 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 13356 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 13357 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 13358 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 13359 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 13360 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 13361 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 13362 // CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 13363 // CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 13364 // CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 13365 // CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 13366 // CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 13367 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 13368 // CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 13369 // CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 13370 // CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 13371 // CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 13372 // CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 13373 // CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 13374 // CHECK25-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 13375 // CHECK25-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 13376 // CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 13377 // CHECK25-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 13378 // CHECK25-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 13379 // CHECK25-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 13380 // CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 13381 // CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 13382 // CHECK25-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 13383 // CHECK25-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 13384 // CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 13385 // CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 13386 // CHECK25-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 13387 // CHECK25-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 13388 // CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 13389 // CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 13390 // CHECK25-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 13391 // CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 13392 // CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 13393 // CHECK25-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 13394 // CHECK25-NEXT: ret void 13395 // 13396 // 13397 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 13398 // CHECK25-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 13399 // CHECK25-NEXT: entry: 13400 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 13401 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 13402 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 13403 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 13404 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13405 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 13406 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 13407 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 13408 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 13409 // CHECK25-NEXT: ret void 13410 // 13411 // 13412 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 13413 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 13414 // CHECK25-NEXT: entry: 13415 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13416 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13417 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 13418 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 13419 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13420 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13421 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 13422 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 13423 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13424 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 13425 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 13426 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 13427 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 13428 // CHECK25-NEXT: ret void 13429 // 13430 // 13431 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 13432 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 13433 // CHECK25-NEXT: entry: 13434 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13435 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13436 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 13437 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13438 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13439 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 13440 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 13441 // CHECK25-NEXT: ret void 13442 // 13443 // 13444 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 13445 // CHECK25-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 13446 // CHECK25-NEXT: entry: 13447 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 13448 // CHECK25-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 13449 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 13450 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 13451 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13452 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 13453 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 13454 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 13455 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 13456 // CHECK25-NEXT: ret void 13457 // 13458 // 13459 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 13460 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 13461 // CHECK25-NEXT: entry: 13462 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13463 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13464 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 13465 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13466 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13467 // CHECK25-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 13468 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 13469 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 13470 // CHECK25-NEXT: ret void 13471 // 13472 // 13473 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..7 13474 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 13475 // CHECK25-NEXT: entry: 13476 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13477 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13478 // CHECK25-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 13479 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13480 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13481 // CHECK25-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 13482 // CHECK25-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 13483 // CHECK25-NEXT: ret void 13484 // 13485 // 13486 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 13487 // CHECK25-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 13488 // CHECK25-NEXT: entry: 13489 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 13490 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 13491 // CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 13492 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 13493 // CHECK25-NEXT: ret void 13494 // 13495 // 13496 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..8 13497 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 13498 // CHECK25-NEXT: entry: 13499 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13500 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13501 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 13502 // CHECK25-NEXT: [[F:%.*]] = alloca i32*, align 8 13503 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13504 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13505 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 13506 // CHECK25-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 13507 // CHECK25-NEXT: ret void 13508 // 13509 // 13510 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 13511 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 13512 // CHECK25-NEXT: entry: 13513 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13514 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13515 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 13516 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 13517 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 13518 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13519 // CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 13520 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13521 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13522 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 13523 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13524 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13525 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13526 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 13527 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13528 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 13529 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 13530 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 13531 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 13532 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 13533 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13534 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 13535 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13536 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 13537 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 13538 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 13539 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 13540 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 13541 // CHECK25-NEXT: ret void 13542 // 13543 // 13544 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..9 13545 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 13546 // CHECK25-NEXT: entry: 13547 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13548 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13549 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13550 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13551 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 13552 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 13553 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13554 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13555 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13556 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13557 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 13558 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13559 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13560 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13561 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 13562 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13563 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 13564 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 13565 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 13566 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 13567 // CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 13568 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 13569 // CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 13570 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 13571 // CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 13572 // CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 13573 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 13574 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 13575 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 13576 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 13577 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 13578 // CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 13579 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 13580 // CHECK25-NEXT: ret void 13581 // 13582 // 13583 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 13584 // CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 13585 // CHECK25-NEXT: entry: 13586 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 13587 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 13588 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 13589 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 13590 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 13591 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 13592 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 13593 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 13594 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 13595 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 13596 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 13597 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 13598 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 13599 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 13600 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 13601 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 13602 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 13603 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 13604 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 13605 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 13606 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 13607 // CHECK25-NEXT: ret void 13608 // 13609 // 13610 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..10 13611 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 13612 // CHECK25-NEXT: entry: 13613 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13614 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13615 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 13616 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 13617 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 13618 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 13619 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 13620 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13621 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13622 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 13623 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 13624 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 13625 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 13626 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 13627 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 13628 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 13629 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 13630 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 13631 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 13632 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 13633 // CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 13634 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 13635 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 13636 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 13637 // CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 13638 // CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 13639 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 13640 // CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 13641 // CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 13642 // CHECK25-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 13643 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 13644 // CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 13645 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 13646 // CHECK25-NEXT: ret void 13647 // 13648 // 13649 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 13650 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 13651 // CHECK25-NEXT: entry: 13652 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13653 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13654 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 13655 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 13656 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13657 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13658 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13659 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13660 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13661 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13662 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13663 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 13664 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 13665 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 13666 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 13667 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 13668 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13669 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 13670 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13671 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 13672 // CHECK25-NEXT: ret void 13673 // 13674 // 13675 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..11 13676 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 13677 // CHECK25-NEXT: entry: 13678 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13679 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13680 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13681 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13682 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 13683 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13684 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13685 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13686 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13687 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 13688 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13689 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13690 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 13691 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 13692 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 13693 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 13694 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 13695 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 13696 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 13697 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 13698 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 13699 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 13700 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 13701 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 13702 // CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 13703 // CHECK25-NEXT: ret void 13704 // 13705 // 13706 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 13707 // CHECK26-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 13708 // CHECK26-NEXT: entry: 13709 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13710 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 13711 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 13712 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13713 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 13714 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13715 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 13716 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 13717 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13718 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 13719 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 13720 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 13721 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 13722 // CHECK26-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 13723 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 13724 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13725 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 13726 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13727 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 13728 // CHECK26-NEXT: ret void 13729 // 13730 // 13731 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. 13732 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13733 // CHECK26-NEXT: entry: 13734 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13735 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13736 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13737 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13738 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13739 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13740 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13741 // CHECK26-NEXT: ret void 13742 // 13743 // 13744 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 13745 // CHECK26-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13746 // CHECK26-NEXT: entry: 13747 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13748 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13749 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13750 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13751 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 13752 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13753 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 13754 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13755 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 13756 // CHECK26-NEXT: ret void 13757 // 13758 // 13759 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 13760 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13761 // CHECK26-NEXT: entry: 13762 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13763 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13764 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13765 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13766 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13767 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13768 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13769 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 13770 // CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 13771 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 13772 // CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 13773 // CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 13774 // CHECK26-NEXT: ret void 13775 // 13776 // 13777 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 13778 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13779 // CHECK26-NEXT: entry: 13780 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13781 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13782 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 13783 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 13784 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13785 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13786 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13787 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13788 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13789 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 13790 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 13791 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 13792 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 13793 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 13794 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 13795 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 13796 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 13797 // CHECK26-NEXT: ret void 13798 // 13799 // 13800 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 13801 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 13802 // CHECK26-NEXT: entry: 13803 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13804 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13805 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13806 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 13807 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13808 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13809 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13810 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 13811 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13812 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 13813 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13814 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 13815 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 13816 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 13817 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 13818 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 13819 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 13820 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 13821 // CHECK26-NEXT: ret void 13822 // 13823 // 13824 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 13825 // CHECK26-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 13826 // CHECK26-NEXT: entry: 13827 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13828 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 13829 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 13830 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 13831 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 13832 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 13833 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 13834 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 13835 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 13836 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 13837 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13838 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 13839 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 13840 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 13841 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 13842 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 13843 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 13844 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 13845 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 13846 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13847 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 13848 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 13849 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 13850 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 13851 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 13852 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 13853 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 13854 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 13855 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 13856 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 13857 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 13858 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 13859 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 13860 // CHECK26-NEXT: ret void 13861 // 13862 // 13863 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 13864 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 13865 // CHECK26-NEXT: entry: 13866 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13867 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13868 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 13869 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 13870 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 13871 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 13872 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 13873 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 13874 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 13875 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 13876 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 13877 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13878 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13879 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 13880 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 13881 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 13882 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 13883 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 13884 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 13885 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 13886 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 13887 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 13888 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 13889 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 13890 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 13891 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 13892 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 13893 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 13894 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 13895 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 13896 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 13897 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 13898 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 13899 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 13900 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 13901 // CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 13902 // CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 13903 // CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 13904 // CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 13905 // CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 13906 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 13907 // CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 13908 // CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 13909 // CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 13910 // CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 13911 // CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 13912 // CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 13913 // CHECK26-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 13914 // CHECK26-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 13915 // CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 13916 // CHECK26-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 13917 // CHECK26-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 13918 // CHECK26-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 13919 // CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 13920 // CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 13921 // CHECK26-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 13922 // CHECK26-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 13923 // CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 13924 // CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 13925 // CHECK26-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 13926 // CHECK26-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 13927 // CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 13928 // CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 13929 // CHECK26-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 13930 // CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 13931 // CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 13932 // CHECK26-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 13933 // CHECK26-NEXT: ret void 13934 // 13935 // 13936 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 13937 // CHECK26-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 13938 // CHECK26-NEXT: entry: 13939 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 13940 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 13941 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 13942 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 13943 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13944 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 13945 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 13946 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 13947 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 13948 // CHECK26-NEXT: ret void 13949 // 13950 // 13951 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 13952 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 13953 // CHECK26-NEXT: entry: 13954 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13955 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13956 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 13957 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 13958 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13959 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13960 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 13961 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 13962 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13963 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 13964 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 13965 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 13966 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 13967 // CHECK26-NEXT: ret void 13968 // 13969 // 13970 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 13971 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 13972 // CHECK26-NEXT: entry: 13973 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 13974 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 13975 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 13976 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 13977 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 13978 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 13979 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 13980 // CHECK26-NEXT: ret void 13981 // 13982 // 13983 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 13984 // CHECK26-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 13985 // CHECK26-NEXT: entry: 13986 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 13987 // CHECK26-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 13988 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 13989 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 13990 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 13991 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 13992 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 13993 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 13994 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 13995 // CHECK26-NEXT: ret void 13996 // 13997 // 13998 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 13999 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 14000 // CHECK26-NEXT: entry: 14001 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 14002 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 14003 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 14004 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 14005 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 14006 // CHECK26-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 14007 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 14008 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 14009 // CHECK26-NEXT: ret void 14010 // 14011 // 14012 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..7 14013 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 14014 // CHECK26-NEXT: entry: 14015 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 14016 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 14017 // CHECK26-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 14018 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 14019 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 14020 // CHECK26-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 14021 // CHECK26-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 14022 // CHECK26-NEXT: ret void 14023 // 14024 // 14025 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 14026 // CHECK26-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 14027 // CHECK26-NEXT: entry: 14028 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 14029 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 14030 // CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 14031 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 14032 // CHECK26-NEXT: ret void 14033 // 14034 // 14035 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..8 14036 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 14037 // CHECK26-NEXT: entry: 14038 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 14039 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 14040 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 14041 // CHECK26-NEXT: [[F:%.*]] = alloca i32*, align 8 14042 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 14043 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 14044 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 14045 // CHECK26-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 14046 // CHECK26-NEXT: ret void 14047 // 14048 // 14049 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 14050 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 14051 // CHECK26-NEXT: entry: 14052 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 14053 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 14054 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 14055 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 14056 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 14057 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 14058 // CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 14059 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 14060 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 14061 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 14062 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 14063 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 14064 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 14065 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 14066 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 14067 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 14068 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 14069 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 14070 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 14071 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 14072 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 14073 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 14074 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 14075 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 14076 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 14077 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 14078 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 14079 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 14080 // CHECK26-NEXT: ret void 14081 // 14082 // 14083 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..9 14084 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 14085 // CHECK26-NEXT: entry: 14086 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 14087 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 14088 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 14089 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 14090 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 14091 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 14092 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 14093 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 14094 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 14095 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 14096 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 14097 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 14098 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 14099 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 14100 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 14101 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 14102 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 14103 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 14104 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 14105 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 14106 // CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 14107 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 14108 // CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 14109 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 14110 // CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 14111 // CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 14112 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 14113 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 14114 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 14115 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 14116 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 14117 // CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 14118 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 14119 // CHECK26-NEXT: ret void 14120 // 14121 // 14122 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 14123 // CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 14124 // CHECK26-NEXT: entry: 14125 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 14126 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 14127 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 14128 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 14129 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 14130 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 14131 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 14132 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 14133 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 14134 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 14135 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 14136 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 14137 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 14138 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 14139 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 14140 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 14141 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 14142 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 14143 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 14144 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 14145 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 14146 // CHECK26-NEXT: ret void 14147 // 14148 // 14149 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..10 14150 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 14151 // CHECK26-NEXT: entry: 14152 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 14153 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 14154 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 14155 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 14156 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 14157 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 14158 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 14159 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 14160 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 14161 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 14162 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 14163 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 14164 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 14165 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 14166 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 14167 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 14168 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 14169 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 14170 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 14171 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 14172 // CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 14173 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 14174 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 14175 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 14176 // CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 14177 // CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 14178 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 14179 // CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 14180 // CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 14181 // CHECK26-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 14182 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 14183 // CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 14184 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 14185 // CHECK26-NEXT: ret void 14186 // 14187 // 14188 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 14189 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 14190 // CHECK26-NEXT: entry: 14191 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 14192 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 14193 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 14194 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 14195 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 14196 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 14197 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 14198 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 14199 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 14200 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 14201 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 14202 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 14203 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 14204 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 14205 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 14206 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 14207 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 14208 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 14209 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 14210 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 14211 // CHECK26-NEXT: ret void 14212 // 14213 // 14214 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..11 14215 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 14216 // CHECK26-NEXT: entry: 14217 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 14218 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 14219 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 14220 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 14221 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 14222 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 14223 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 14224 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 14225 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 14226 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 14227 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 14228 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 14229 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 14230 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 14231 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 14232 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 14233 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 14234 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 14235 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 14236 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 14237 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 14238 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 14239 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 14240 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 14241 // CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 14242 // CHECK26-NEXT: ret void 14243 // 14244 // 14245 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 14246 // CHECK27-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 14247 // CHECK27-NEXT: entry: 14248 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14249 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 14250 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 14251 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14252 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 14253 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14254 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14255 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 14256 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14257 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14258 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 14259 // CHECK27-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 14260 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 14261 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14262 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 14263 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14264 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 14265 // CHECK27-NEXT: ret void 14266 // 14267 // 14268 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. 14269 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14270 // CHECK27-NEXT: entry: 14271 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14272 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14273 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14274 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14275 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14276 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14277 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14278 // CHECK27-NEXT: ret void 14279 // 14280 // 14281 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 14282 // CHECK27-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14283 // CHECK27-NEXT: entry: 14284 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14285 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14286 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14287 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14288 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 14289 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14290 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 14291 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14292 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14293 // CHECK27-NEXT: ret void 14294 // 14295 // 14296 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 14297 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14298 // CHECK27-NEXT: entry: 14299 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14300 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14301 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14302 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14303 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14304 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14305 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14306 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 14307 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 14308 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 14309 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 14310 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 14311 // CHECK27-NEXT: ret void 14312 // 14313 // 14314 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 14315 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14316 // CHECK27-NEXT: entry: 14317 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14318 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14319 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14320 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14321 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14322 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14323 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14324 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 14325 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14326 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14327 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 14328 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14329 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 14330 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14331 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 14332 // CHECK27-NEXT: ret void 14333 // 14334 // 14335 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 14336 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14337 // CHECK27-NEXT: entry: 14338 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14339 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14340 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14341 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14342 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14343 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14344 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14345 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14346 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14347 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 14348 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 14349 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14350 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 14351 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 14352 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 14353 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 14354 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 14355 // CHECK27-NEXT: ret void 14356 // 14357 // 14358 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 14359 // CHECK27-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 14360 // CHECK27-NEXT: entry: 14361 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14362 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 14363 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14364 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 14365 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 14366 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14367 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 14368 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 14369 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 14370 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14371 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14372 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 14373 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14374 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 14375 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 14376 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14377 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 14378 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 14379 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 14380 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 14381 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14382 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 14383 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 14384 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14385 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 14386 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 14387 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 14388 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 14389 // CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 14390 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 14391 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 14392 // CHECK27-NEXT: ret void 14393 // 14394 // 14395 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 14396 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 14397 // CHECK27-NEXT: entry: 14398 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14399 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14400 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14401 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 14402 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14403 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 14404 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 14405 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14406 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 14407 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 14408 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 14409 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14410 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14411 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14412 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 14413 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14414 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 14415 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 14416 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14417 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 14418 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 14419 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 14420 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 14421 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14422 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 14423 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 14424 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14425 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 14426 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 14427 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 14428 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 14429 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 14430 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14431 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 14432 // CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 14433 // CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 14434 // CHECK27-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 14435 // CHECK27-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 14436 // CHECK27-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 14437 // CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 14438 // CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 14439 // CHECK27-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 14440 // CHECK27-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 14441 // CHECK27-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 14442 // CHECK27-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 14443 // CHECK27-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 14444 // CHECK27-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 14445 // CHECK27-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 14446 // CHECK27-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 14447 // CHECK27-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 14448 // CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 14449 // CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 14450 // CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 14451 // CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 14452 // CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 14453 // CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 14454 // CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 14455 // CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 14456 // CHECK27-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 14457 // CHECK27-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 14458 // CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 14459 // CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 14460 // CHECK27-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 14461 // CHECK27-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 14462 // CHECK27-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 14463 // CHECK27-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 14464 // CHECK27-NEXT: ret void 14465 // 14466 // 14467 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 14468 // CHECK27-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 14469 // CHECK27-NEXT: entry: 14470 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14471 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 14472 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14473 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 14474 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 14475 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 14476 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14477 // CHECK27-NEXT: ret void 14478 // 14479 // 14480 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 14481 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 14482 // CHECK27-NEXT: entry: 14483 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14484 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14485 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14486 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 14487 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14488 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14489 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14490 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 14491 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 14492 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 14493 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14494 // CHECK27-NEXT: ret void 14495 // 14496 // 14497 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 14498 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 14499 // CHECK27-NEXT: entry: 14500 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14501 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14502 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14503 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14504 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14505 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14506 // CHECK27-NEXT: ret void 14507 // 14508 // 14509 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 14510 // CHECK27-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 14511 // CHECK27-NEXT: entry: 14512 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14513 // CHECK27-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 14514 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14515 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 14516 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 14517 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 14518 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14519 // CHECK27-NEXT: ret void 14520 // 14521 // 14522 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 14523 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 14524 // CHECK27-NEXT: entry: 14525 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14526 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14527 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14528 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14529 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14530 // CHECK27-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14531 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 14532 // CHECK27-NEXT: ret void 14533 // 14534 // 14535 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..7 14536 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 14537 // CHECK27-NEXT: entry: 14538 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14539 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14540 // CHECK27-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 14541 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14542 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14543 // CHECK27-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 14544 // CHECK27-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 14545 // CHECK27-NEXT: ret void 14546 // 14547 // 14548 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 14549 // CHECK27-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 14550 // CHECK27-NEXT: entry: 14551 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14552 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14553 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14554 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 14555 // CHECK27-NEXT: ret void 14556 // 14557 // 14558 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..8 14559 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 14560 // CHECK27-NEXT: entry: 14561 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14562 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14563 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14564 // CHECK27-NEXT: [[F:%.*]] = alloca i32*, align 4 14565 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14566 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14567 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14568 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14569 // CHECK27-NEXT: ret void 14570 // 14571 // 14572 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 14573 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 14574 // CHECK27-NEXT: entry: 14575 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14576 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14577 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 14578 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14579 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14580 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14581 // CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 14582 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14583 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14584 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 14585 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14586 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14587 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 14588 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14589 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 14590 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 14591 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 14592 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 14593 // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14594 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 14595 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14596 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 14597 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 14598 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 14599 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 14600 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 14601 // CHECK27-NEXT: ret void 14602 // 14603 // 14604 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..9 14605 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 14606 // CHECK27-NEXT: entry: 14607 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14608 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14609 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14610 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14611 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 14612 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14613 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14614 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14615 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14616 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14617 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 14618 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14619 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14620 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 14621 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14622 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 14623 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 14624 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14625 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 14626 // CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 14627 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 14628 // CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 14629 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 14630 // CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 14631 // CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 14632 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 14633 // CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 14634 // CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 14635 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 14636 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 14637 // CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 14638 // CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 14639 // CHECK27-NEXT: ret void 14640 // 14641 // 14642 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 14643 // CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 14644 // CHECK27-NEXT: entry: 14645 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 14646 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 14647 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14648 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14649 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 14650 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 14651 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 14652 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 14653 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14654 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14655 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 14656 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 14657 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14658 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14659 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 14660 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 14661 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 14662 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 14663 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 14664 // CHECK27-NEXT: ret void 14665 // 14666 // 14667 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..10 14668 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 14669 // CHECK27-NEXT: entry: 14670 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14671 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14672 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 14673 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 14674 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14675 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14676 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 14677 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14678 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14679 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 14680 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 14681 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14682 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14683 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 14684 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 14685 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14686 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14687 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 14688 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 14689 // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 14690 // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 14691 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 14692 // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 14693 // CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 14694 // CHECK27-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 14695 // CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 14696 // CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4 14697 // CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 14698 // CHECK27-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 14699 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 14700 // CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 14701 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 14702 // CHECK27-NEXT: ret void 14703 // 14704 // 14705 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 14706 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 14707 // CHECK27-NEXT: entry: 14708 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14709 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14710 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14711 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14712 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14713 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14714 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14715 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14716 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14717 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14718 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 14719 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 14720 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 14721 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 14722 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14723 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 14724 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14725 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 14726 // CHECK27-NEXT: ret void 14727 // 14728 // 14729 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..11 14730 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 14731 // CHECK27-NEXT: entry: 14732 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14733 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14734 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14735 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14736 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 14737 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14738 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14739 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14740 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14741 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 14742 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14743 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 14744 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 14745 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 14746 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14747 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 14748 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 14749 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 14750 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 14751 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 14752 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 14753 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 14754 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 14755 // CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 14756 // CHECK27-NEXT: ret void 14757 // 14758 // 14759 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 14760 // CHECK28-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 14761 // CHECK28-NEXT: entry: 14762 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14763 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 14764 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 14765 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14766 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 14767 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14768 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14769 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 14770 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14771 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 14772 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 14773 // CHECK28-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 14774 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 14775 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14776 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 14777 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14778 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 14779 // CHECK28-NEXT: ret void 14780 // 14781 // 14782 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. 14783 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14784 // CHECK28-NEXT: entry: 14785 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14786 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14787 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14788 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14789 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14790 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14791 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14792 // CHECK28-NEXT: ret void 14793 // 14794 // 14795 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 14796 // CHECK28-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14797 // CHECK28-NEXT: entry: 14798 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14799 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14800 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14801 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14802 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 14803 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14804 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 14805 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14806 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14807 // CHECK28-NEXT: ret void 14808 // 14809 // 14810 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 14811 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14812 // CHECK28-NEXT: entry: 14813 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14814 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14815 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14816 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14817 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14818 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14819 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14820 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 14821 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 14822 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 14823 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 14824 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 14825 // CHECK28-NEXT: ret void 14826 // 14827 // 14828 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 14829 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14830 // CHECK28-NEXT: entry: 14831 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14832 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14833 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14834 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 14835 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14836 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14837 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14838 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 14839 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 14840 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 14841 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 14842 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 14843 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 14844 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 14845 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 14846 // CHECK28-NEXT: ret void 14847 // 14848 // 14849 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 14850 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 14851 // CHECK28-NEXT: entry: 14852 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14853 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14854 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14855 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 14856 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14857 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14858 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14859 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 14860 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 14861 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 14862 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 14863 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14864 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 14865 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 14866 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 14867 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 14868 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 14869 // CHECK28-NEXT: ret void 14870 // 14871 // 14872 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 14873 // CHECK28-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 14874 // CHECK28-NEXT: entry: 14875 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14876 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 14877 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14878 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 14879 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 14880 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14881 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 14882 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 14883 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 14884 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 14885 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14886 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 14887 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14888 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 14889 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 14890 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14891 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 14892 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 14893 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 14894 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 14895 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14896 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 14897 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 14898 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14899 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 14900 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 14901 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 14902 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 14903 // CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 14904 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 14905 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 14906 // CHECK28-NEXT: ret void 14907 // 14908 // 14909 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 14910 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 14911 // CHECK28-NEXT: entry: 14912 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14913 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14914 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 14915 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 14916 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 14917 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 14918 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 14919 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 14920 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 14921 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 14922 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 14923 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 14924 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 14925 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 14926 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 14927 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 14928 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 14929 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 14930 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 14931 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 14932 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 14933 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 14934 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 14935 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 14936 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 14937 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 14938 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 14939 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 14940 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 14941 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 14942 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 14943 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 14944 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 14945 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 14946 // CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 14947 // CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 14948 // CHECK28-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 14949 // CHECK28-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 14950 // CHECK28-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 14951 // CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 14952 // CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 14953 // CHECK28-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 14954 // CHECK28-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 14955 // CHECK28-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 14956 // CHECK28-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 14957 // CHECK28-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 14958 // CHECK28-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 14959 // CHECK28-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 14960 // CHECK28-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 14961 // CHECK28-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 14962 // CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 14963 // CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 14964 // CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 14965 // CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 14966 // CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 14967 // CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 14968 // CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 14969 // CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 14970 // CHECK28-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 14971 // CHECK28-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 14972 // CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 14973 // CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 14974 // CHECK28-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 14975 // CHECK28-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 14976 // CHECK28-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 14977 // CHECK28-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 14978 // CHECK28-NEXT: ret void 14979 // 14980 // 14981 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 14982 // CHECK28-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 14983 // CHECK28-NEXT: entry: 14984 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 14985 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 14986 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 14987 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 14988 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 14989 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 14990 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 14991 // CHECK28-NEXT: ret void 14992 // 14993 // 14994 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 14995 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 14996 // CHECK28-NEXT: entry: 14997 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 14998 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 14999 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 15000 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 15001 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15002 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15003 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 15004 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 15005 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 15006 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 15007 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 15008 // CHECK28-NEXT: ret void 15009 // 15010 // 15011 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 15012 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 15013 // CHECK28-NEXT: entry: 15014 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15015 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15016 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 15017 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15018 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15019 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 15020 // CHECK28-NEXT: ret void 15021 // 15022 // 15023 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 15024 // CHECK28-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 15025 // CHECK28-NEXT: entry: 15026 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 15027 // CHECK28-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 15028 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 15029 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 15030 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 15031 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 15032 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 15033 // CHECK28-NEXT: ret void 15034 // 15035 // 15036 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 15037 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 15038 // CHECK28-NEXT: entry: 15039 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15040 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15041 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 15042 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15043 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15044 // CHECK28-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 15045 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 15046 // CHECK28-NEXT: ret void 15047 // 15048 // 15049 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..7 15050 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 15051 // CHECK28-NEXT: entry: 15052 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15053 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15054 // CHECK28-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 15055 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15056 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15057 // CHECK28-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 15058 // CHECK28-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 15059 // CHECK28-NEXT: ret void 15060 // 15061 // 15062 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 15063 // CHECK28-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 15064 // CHECK28-NEXT: entry: 15065 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15066 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15067 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15068 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 15069 // CHECK28-NEXT: ret void 15070 // 15071 // 15072 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..8 15073 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 15074 // CHECK28-NEXT: entry: 15075 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15076 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15077 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15078 // CHECK28-NEXT: [[F:%.*]] = alloca i32*, align 4 15079 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15080 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15081 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15082 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15083 // CHECK28-NEXT: ret void 15084 // 15085 // 15086 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 15087 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 15088 // CHECK28-NEXT: entry: 15089 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15090 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15091 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 15092 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 15093 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15094 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15095 // CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 15096 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15097 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15098 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 15099 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 15100 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15101 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 15102 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 15103 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15104 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 15105 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 15106 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 15107 // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15108 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 15109 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15110 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 15111 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 15112 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 15113 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 15114 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 15115 // CHECK28-NEXT: ret void 15116 // 15117 // 15118 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..9 15119 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 15120 // CHECK28-NEXT: entry: 15121 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15122 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15123 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15124 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15125 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 15126 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 15127 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15128 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15129 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15130 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15131 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 15132 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 15133 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15134 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 15135 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 15136 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15137 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 15138 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 15139 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 15140 // CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 15141 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 15142 // CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 15143 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 15144 // CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 15145 // CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 15146 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 15147 // CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 15148 // CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 15149 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 15150 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15151 // CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 15152 // CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 15153 // CHECK28-NEXT: ret void 15154 // 15155 // 15156 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 15157 // CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 15158 // CHECK28-NEXT: entry: 15159 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 15160 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 15161 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15162 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 15163 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 15164 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 15165 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 15166 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 15167 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15168 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 15169 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 15170 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 15171 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15172 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 15173 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 15174 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 15175 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 15176 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 15177 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 15178 // CHECK28-NEXT: ret void 15179 // 15180 // 15181 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..10 15182 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 15183 // CHECK28-NEXT: entry: 15184 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15185 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15186 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 15187 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 15188 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 15189 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 15190 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 15191 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15192 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15193 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 15194 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 15195 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 15196 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 15197 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 15198 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 15199 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 15200 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 15201 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 15202 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 15203 // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 15204 // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 15205 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 15206 // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 15207 // CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 15208 // CHECK28-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 15209 // CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 15210 // CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4 15211 // CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 15212 // CHECK28-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 15213 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 15214 // CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 15215 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 15216 // CHECK28-NEXT: ret void 15217 // 15218 // 15219 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 15220 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 15221 // CHECK28-NEXT: entry: 15222 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15223 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15224 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 15225 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 15226 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 15227 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15228 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15229 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 15230 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15231 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 15232 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15233 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 15234 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 15235 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 15236 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 15237 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 15238 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 15239 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 15240 // CHECK28-NEXT: ret void 15241 // 15242 // 15243 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..11 15244 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 15245 // CHECK28-NEXT: entry: 15246 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 15247 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 15248 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 15249 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 15250 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 15251 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 15252 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 15253 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 15254 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 15255 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 15256 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 15257 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 15258 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 15259 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 15260 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 15261 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 15262 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 15263 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 15264 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 15265 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 15266 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 15267 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 15268 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 15269 // CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 15270 // CHECK28-NEXT: ret void 15271 // 15272