1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 26 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 37 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 39 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 40 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 42 43 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 46 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 49 50 // Test target codegen - host bc file has to be created first. 51 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 53 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 55 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 57 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 59 60 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 62 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 64 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 66 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 68 69 // expected-no-diagnostics 70 #ifndef HEADER 71 #define HEADER 72 73 74 75 76 // We have 8 target regions, but only 6 that actually will generate offloading 77 // code and have mapped arguments, and only 4 have all-constant map sizes. 78 79 80 81 // Check target registration is registered as a Ctor. 82 83 84 template<typename tx, typename ty> 85 struct TT{ 86 tx X; 87 ty Y; 88 }; 89 90 int global; 91 92 int foo(int n) { 93 int a = 0; 94 short aa = 0; 95 float b[10]; 96 float bn[n]; 97 double c[5][10]; 98 double cn[5][n]; 99 TT<long long, char> d; 100 101 #pragma omp target teams num_teams(a) thread_limit(a) firstprivate(aa) nowait 102 { 103 } 104 105 #pragma omp target teams if(target: 0) 106 { 107 a += 1; 108 } 109 110 111 #pragma omp target teams if(target: 1) 112 { 113 aa += 1; 114 } 115 116 117 118 #pragma omp target teams if(target: n>10) 119 { 120 a += 1; 121 aa += 1; 122 } 123 124 // We capture 3 VLA sizes in this target region 125 126 127 128 129 130 // The names below are not necessarily consistent with the names used for the 131 // addresses above as some are repeated. 132 133 134 135 136 137 138 139 140 141 142 #pragma omp target teams if(target: n>20) 143 { 144 a += 1; 145 b[2] += 1.0; 146 bn[3] += 1.0; 147 c[1][2] += 1.0; 148 cn[1][3] += 1.0; 149 d.X += 1; 150 d.Y += 1; 151 } 152 153 const int nn = 0; 154 #pragma omp target teams shared(nn) 155 #pragma omp parallel firstprivate(nn) 156 (void)nn; 157 #pragma omp target teams firstprivate(nn) 158 #pragma omp parallel shared(nn) 159 (void)nn; 160 return a; 161 } 162 163 // Check that the offloading functions are emitted and that the arguments are 164 // correct and loaded correctly for the target regions in foo(). 165 166 167 168 // Create stack storage and store argument in there. 169 170 // Create stack storage and store argument in there. 171 172 // Create stack storage and store argument in there. 173 174 // Create local storage for each capture. 175 176 177 178 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 179 180 181 void bazzzz(int n, int f[n]) { 182 #pragma omp target teams private(f) 183 ; 184 } 185 186 template<typename tx> 187 tx ftemplate(int n) { 188 tx a = 0; 189 short aa = 0; 190 tx b[10]; 191 192 #pragma omp target teams if(target: n>40) 193 { 194 a += 1; 195 aa += 1; 196 b[2] += 1; 197 } 198 199 return a; 200 } 201 202 static 203 int fstatic(int n) { 204 int a = 0; 205 short aa = 0; 206 char aaa = 0; 207 int b[10]; 208 209 #pragma omp target teams if(target: n>50) 210 { 211 a += 1; 212 aa += 1; 213 aaa += 1; 214 b[2] += 1; 215 } 216 217 return a; 218 } 219 220 struct S1 { 221 double a; 222 223 int r1(int n){ 224 int b = n+1; 225 short int c[2][n]; 226 227 #pragma omp target teams if(target: n>60) 228 { 229 this->a = (double)b + 1.5; 230 c[1][1] = ++a; 231 } 232 233 return c[1][1] + (int)b; 234 } 235 }; 236 237 int bar(int n){ 238 int a = 0; 239 240 a += foo(n); 241 242 S1 S; 243 a += S.r1(n); 244 245 a += fstatic(n); 246 247 a += ftemplate<int>(n); 248 249 return a; 250 } 251 252 253 254 // We capture 2 VLA sizes in this target region 255 256 257 // The names below are not necessarily consistent with the names used for the 258 // addresses above as some are repeated. 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 // Check that the offloading functions are emitted and that the arguments are 280 // correct and loaded correctly for the target regions of the callees of bar(). 281 282 // Create local storage for each capture. 283 // Store captures in the context. 284 285 286 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 287 288 289 // Create local storage for each capture. 290 // Store captures in the context. 291 292 293 294 295 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 296 297 // Create local storage for each capture. 298 // Store captures in the context. 299 300 301 302 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 303 304 #endif 305 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 306 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 307 // CHECK1-NEXT: entry: 308 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 309 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 310 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 311 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 312 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 313 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 315 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 316 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 317 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 318 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED4:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 325 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 326 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[AA_CASTED7:%.*]] = alloca i64, align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS9:%.*]] = alloca [1 x i8*], align 8 329 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS10:%.*]] = alloca [1 x i8*], align 8 330 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS11:%.*]] = alloca [1 x i8*], align 8 331 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[AA_CASTED14:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [2 x i8*], align 8 334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [2 x i8*], align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [2 x i8*], align 8 336 // CHECK1-NEXT: [[A_CASTED22:%.*]] = alloca i64, align 8 337 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS26:%.*]] = alloca [9 x i8*], align 8 338 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS27:%.*]] = alloca [9 x i8*], align 8 339 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS28:%.*]] = alloca [9 x i8*], align 8 340 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 341 // CHECK1-NEXT: [[NN:%.*]] = alloca i32, align 4 342 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 343 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS35:%.*]] = alloca [1 x i8*], align 8 344 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS36:%.*]] = alloca [1 x i8*], align 8 345 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS37:%.*]] = alloca [1 x i8*], align 8 346 // CHECK1-NEXT: [[NN_CASTED41:%.*]] = alloca i64, align 8 347 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS43:%.*]] = alloca [1 x i8*], align 8 348 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS44:%.*]] = alloca [1 x i8*], align 8 349 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS45:%.*]] = alloca [1 x i8*], align 8 350 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 351 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 352 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 353 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 354 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 355 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 356 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 357 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 358 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 359 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 360 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 361 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 362 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 363 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 364 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 365 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 366 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR_]], align 4 367 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 368 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTCAPTURE_EXPR_2]], align 4 369 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[AA]], align 2 370 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 371 // CHECK1-NEXT: store i16 [[TMP9]], i16* [[CONV]], align 2 372 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[AA_CASTED]], align 8 373 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 374 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 375 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV3]], align 4 376 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 377 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 378 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED4]] to i32* 379 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[CONV5]], align 4 380 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED4]], align 8 381 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 382 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 383 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP16]], align 8 384 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 385 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 386 // CHECK1-NEXT: store i64 [[TMP10]], i64* [[TMP18]], align 8 387 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 388 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 389 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 390 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64* 391 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP21]], align 8 392 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 393 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 394 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[TMP23]], align 8 395 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 396 // CHECK1-NEXT: store i8* null, i8** [[TMP24]], align 8 397 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 398 // CHECK1-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i64* 399 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP26]], align 8 400 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 401 // CHECK1-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i64* 402 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP28]], align 8 403 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 404 // CHECK1-NEXT: store i8* null, i8** [[TMP29]], align 8 405 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 406 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 407 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 408 // CHECK1-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 409 // CHECK1-NEXT: store i16 [[TMP33]], i16* [[TMP32]], align 4 410 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 411 // CHECK1-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 412 // CHECK1-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 413 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 414 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 415 // CHECK1-NEXT: store i32 [[TMP37]], i32* [[TMP36]], align 4 416 // CHECK1-NEXT: [[TMP38:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 120, i64 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 417 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8* [[TMP38]] to %struct.kmp_task_t_with_privates* 418 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 0 419 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP40]], i32 0, i32 0 420 // CHECK1-NEXT: [[TMP42:%.*]] = load i8*, i8** [[TMP41]], align 8 421 // CHECK1-NEXT: [[TMP43:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 422 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP42]], i8* align 4 [[TMP43]], i64 12, i1 false) 423 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP39]], i32 0, i32 1 424 // CHECK1-NEXT: [[TMP45:%.*]] = bitcast i8* [[TMP42]] to %struct.anon* 425 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 0 426 // CHECK1-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 427 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP30]] to i8* 428 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP47]], i8* align 8 [[TMP48]], i64 24, i1 false) 429 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 1 430 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 431 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP31]] to i8* 432 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP50]], i8* align 8 [[TMP51]], i64 24, i1 false) 433 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 2 434 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast [3 x i64]* [[TMP52]] to i8* 435 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP53]], i8* align 8 bitcast ([3 x i64]* @.offload_sizes to i8*), i64 24, i1 false) 436 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP44]], i32 0, i32 3 437 // CHECK1-NEXT: [[TMP55:%.*]] = load i16, i16* [[AA]], align 2 438 // CHECK1-NEXT: store i16 [[TMP55]], i16* [[TMP54]], align 8 439 // CHECK1-NEXT: [[TMP56:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP38]]) 440 // CHECK1-NEXT: [[TMP57:%.*]] = load i32, i32* [[A]], align 4 441 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 442 // CHECK1-NEXT: store i32 [[TMP57]], i32* [[CONV6]], align 4 443 // CHECK1-NEXT: [[TMP58:%.*]] = load i64, i64* [[A_CASTED]], align 8 444 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i64 [[TMP58]]) #[[ATTR3:[0-9]+]] 445 // CHECK1-NEXT: [[TMP59:%.*]] = load i16, i16* [[AA]], align 2 446 // CHECK1-NEXT: [[CONV8:%.*]] = bitcast i64* [[AA_CASTED7]] to i16* 447 // CHECK1-NEXT: store i16 [[TMP59]], i16* [[CONV8]], align 2 448 // CHECK1-NEXT: [[TMP60:%.*]] = load i64, i64* [[AA_CASTED7]], align 8 449 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 450 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 451 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP62]], align 8 452 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 453 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 454 // CHECK1-NEXT: store i64 [[TMP60]], i64* [[TMP64]], align 8 455 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS11]], i64 0, i64 0 456 // CHECK1-NEXT: store i8* null, i8** [[TMP65]], align 8 457 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS9]], i32 0, i32 0 458 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS10]], i32 0, i32 0 459 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 460 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 461 // CHECK1-NEXT: store i32 1, i32* [[TMP68]], align 4 462 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 463 // CHECK1-NEXT: store i32 1, i32* [[TMP69]], align 4 464 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 465 // CHECK1-NEXT: store i8** [[TMP66]], i8*** [[TMP70]], align 8 466 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 467 // CHECK1-NEXT: store i8** [[TMP67]], i8*** [[TMP71]], align 8 468 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 469 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP72]], align 8 470 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 471 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP73]], align 8 472 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 473 // CHECK1-NEXT: store i8** null, i8*** [[TMP74]], align 8 474 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 475 // CHECK1-NEXT: store i8** null, i8*** [[TMP75]], align 8 476 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 477 // CHECK1-NEXT: store i64 0, i64* [[TMP76]], align 8 478 // CHECK1-NEXT: [[TMP77:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 479 // CHECK1-NEXT: [[TMP78:%.*]] = icmp ne i32 [[TMP77]], 0 480 // CHECK1-NEXT: br i1 [[TMP78]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 481 // CHECK1: omp_offload.failed: 482 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i64 [[TMP60]]) #[[ATTR3]] 483 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 484 // CHECK1: omp_offload.cont: 485 // CHECK1-NEXT: [[TMP79:%.*]] = load i32, i32* [[A]], align 4 486 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 487 // CHECK1-NEXT: store i32 [[TMP79]], i32* [[CONV13]], align 4 488 // CHECK1-NEXT: [[TMP80:%.*]] = load i64, i64* [[A_CASTED12]], align 8 489 // CHECK1-NEXT: [[TMP81:%.*]] = load i16, i16* [[AA]], align 2 490 // CHECK1-NEXT: [[CONV15:%.*]] = bitcast i64* [[AA_CASTED14]] to i16* 491 // CHECK1-NEXT: store i16 [[TMP81]], i16* [[CONV15]], align 2 492 // CHECK1-NEXT: [[TMP82:%.*]] = load i64, i64* [[AA_CASTED14]], align 8 493 // CHECK1-NEXT: [[TMP83:%.*]] = load i32, i32* [[N_ADDR]], align 4 494 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP83]], 10 495 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 496 // CHECK1: omp_if.then: 497 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 498 // CHECK1-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i64* 499 // CHECK1-NEXT: store i64 [[TMP80]], i64* [[TMP85]], align 8 500 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 501 // CHECK1-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to i64* 502 // CHECK1-NEXT: store i64 [[TMP80]], i64* [[TMP87]], align 8 503 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 504 // CHECK1-NEXT: store i8* null, i8** [[TMP88]], align 8 505 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 506 // CHECK1-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* 507 // CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP90]], align 8 508 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 509 // CHECK1-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to i64* 510 // CHECK1-NEXT: store i64 [[TMP82]], i64* [[TMP92]], align 8 511 // CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 512 // CHECK1-NEXT: store i8* null, i8** [[TMP93]], align 8 513 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 514 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 515 // CHECK1-NEXT: [[KERNEL_ARGS19:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 516 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]], i32 0, i32 0 517 // CHECK1-NEXT: store i32 1, i32* [[TMP96]], align 4 518 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]], i32 0, i32 1 519 // CHECK1-NEXT: store i32 2, i32* [[TMP97]], align 4 520 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]], i32 0, i32 2 521 // CHECK1-NEXT: store i8** [[TMP94]], i8*** [[TMP98]], align 8 522 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]], i32 0, i32 3 523 // CHECK1-NEXT: store i8** [[TMP95]], i8*** [[TMP99]], align 8 524 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]], i32 0, i32 4 525 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP100]], align 8 526 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]], i32 0, i32 5 527 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP101]], align 8 528 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]], i32 0, i32 6 529 // CHECK1-NEXT: store i8** null, i8*** [[TMP102]], align 8 530 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]], i32 0, i32 7 531 // CHECK1-NEXT: store i8** null, i8*** [[TMP103]], align 8 532 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]], i32 0, i32 8 533 // CHECK1-NEXT: store i64 0, i64* [[TMP104]], align 8 534 // CHECK1-NEXT: [[TMP105:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS19]]) 535 // CHECK1-NEXT: [[TMP106:%.*]] = icmp ne i32 [[TMP105]], 0 536 // CHECK1-NEXT: br i1 [[TMP106]], label [[OMP_OFFLOAD_FAILED20:%.*]], label [[OMP_OFFLOAD_CONT21:%.*]] 537 // CHECK1: omp_offload.failed20: 538 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP80]], i64 [[TMP82]]) #[[ATTR3]] 539 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT21]] 540 // CHECK1: omp_offload.cont21: 541 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 542 // CHECK1: omp_if.else: 543 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i64 [[TMP80]], i64 [[TMP82]]) #[[ATTR3]] 544 // CHECK1-NEXT: br label [[OMP_IF_END]] 545 // CHECK1: omp_if.end: 546 // CHECK1-NEXT: [[TMP107:%.*]] = load i32, i32* [[A]], align 4 547 // CHECK1-NEXT: [[CONV23:%.*]] = bitcast i64* [[A_CASTED22]] to i32* 548 // CHECK1-NEXT: store i32 [[TMP107]], i32* [[CONV23]], align 4 549 // CHECK1-NEXT: [[TMP108:%.*]] = load i64, i64* [[A_CASTED22]], align 8 550 // CHECK1-NEXT: [[TMP109:%.*]] = load i32, i32* [[N_ADDR]], align 4 551 // CHECK1-NEXT: [[CMP24:%.*]] = icmp sgt i32 [[TMP109]], 20 552 // CHECK1-NEXT: br i1 [[CMP24]], label [[OMP_IF_THEN25:%.*]], label [[OMP_IF_ELSE32:%.*]] 553 // CHECK1: omp_if.then25: 554 // CHECK1-NEXT: [[TMP110:%.*]] = mul nuw i64 [[TMP2]], 4 555 // CHECK1-NEXT: [[TMP111:%.*]] = mul nuw i64 5, [[TMP5]] 556 // CHECK1-NEXT: [[TMP112:%.*]] = mul nuw i64 [[TMP111]], 8 557 // CHECK1-NEXT: [[TMP113:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 558 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP113]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i64 72, i1 false) 559 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 560 // CHECK1-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i64* 561 // CHECK1-NEXT: store i64 [[TMP108]], i64* [[TMP115]], align 8 562 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 563 // CHECK1-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 564 // CHECK1-NEXT: store i64 [[TMP108]], i64* [[TMP117]], align 8 565 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 0 566 // CHECK1-NEXT: store i8* null, i8** [[TMP118]], align 8 567 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 1 568 // CHECK1-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [10 x float]** 569 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP120]], align 8 570 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 1 571 // CHECK1-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [10 x float]** 572 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP122]], align 8 573 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 1 574 // CHECK1-NEXT: store i8* null, i8** [[TMP123]], align 8 575 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 2 576 // CHECK1-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i64* 577 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP125]], align 8 578 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 2 579 // CHECK1-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i64* 580 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP127]], align 8 581 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 2 582 // CHECK1-NEXT: store i8* null, i8** [[TMP128]], align 8 583 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 3 584 // CHECK1-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to float** 585 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP130]], align 8 586 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 3 587 // CHECK1-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to float** 588 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP132]], align 8 589 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 590 // CHECK1-NEXT: store i64 [[TMP110]], i64* [[TMP133]], align 8 591 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 3 592 // CHECK1-NEXT: store i8* null, i8** [[TMP134]], align 8 593 // CHECK1-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 4 594 // CHECK1-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to [5 x [10 x double]]** 595 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP136]], align 8 596 // CHECK1-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 4 597 // CHECK1-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to [5 x [10 x double]]** 598 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP138]], align 8 599 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 4 600 // CHECK1-NEXT: store i8* null, i8** [[TMP139]], align 8 601 // CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 5 602 // CHECK1-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i64* 603 // CHECK1-NEXT: store i64 5, i64* [[TMP141]], align 8 604 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 5 605 // CHECK1-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i64* 606 // CHECK1-NEXT: store i64 5, i64* [[TMP143]], align 8 607 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 5 608 // CHECK1-NEXT: store i8* null, i8** [[TMP144]], align 8 609 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 6 610 // CHECK1-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i64* 611 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP146]], align 8 612 // CHECK1-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 6 613 // CHECK1-NEXT: [[TMP148:%.*]] = bitcast i8** [[TMP147]] to i64* 614 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP148]], align 8 615 // CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 6 616 // CHECK1-NEXT: store i8* null, i8** [[TMP149]], align 8 617 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 7 618 // CHECK1-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to double** 619 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP151]], align 8 620 // CHECK1-NEXT: [[TMP152:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 7 621 // CHECK1-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to double** 622 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP153]], align 8 623 // CHECK1-NEXT: [[TMP154:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 624 // CHECK1-NEXT: store i64 [[TMP112]], i64* [[TMP154]], align 8 625 // CHECK1-NEXT: [[TMP155:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 7 626 // CHECK1-NEXT: store i8* null, i8** [[TMP155]], align 8 627 // CHECK1-NEXT: [[TMP156:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 8 628 // CHECK1-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to %struct.TT** 629 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP157]], align 8 630 // CHECK1-NEXT: [[TMP158:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 8 631 // CHECK1-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to %struct.TT** 632 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP159]], align 8 633 // CHECK1-NEXT: [[TMP160:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS28]], i64 0, i64 8 634 // CHECK1-NEXT: store i8* null, i8** [[TMP160]], align 8 635 // CHECK1-NEXT: [[TMP161:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS26]], i32 0, i32 0 636 // CHECK1-NEXT: [[TMP162:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS27]], i32 0, i32 0 637 // CHECK1-NEXT: [[TMP163:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 638 // CHECK1-NEXT: [[KERNEL_ARGS29:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 639 // CHECK1-NEXT: [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]], i32 0, i32 0 640 // CHECK1-NEXT: store i32 1, i32* [[TMP164]], align 4 641 // CHECK1-NEXT: [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]], i32 0, i32 1 642 // CHECK1-NEXT: store i32 9, i32* [[TMP165]], align 4 643 // CHECK1-NEXT: [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]], i32 0, i32 2 644 // CHECK1-NEXT: store i8** [[TMP161]], i8*** [[TMP166]], align 8 645 // CHECK1-NEXT: [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]], i32 0, i32 3 646 // CHECK1-NEXT: store i8** [[TMP162]], i8*** [[TMP167]], align 8 647 // CHECK1-NEXT: [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]], i32 0, i32 4 648 // CHECK1-NEXT: store i64* [[TMP163]], i64** [[TMP168]], align 8 649 // CHECK1-NEXT: [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]], i32 0, i32 5 650 // CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i64** [[TMP169]], align 8 651 // CHECK1-NEXT: [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]], i32 0, i32 6 652 // CHECK1-NEXT: store i8** null, i8*** [[TMP170]], align 8 653 // CHECK1-NEXT: [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]], i32 0, i32 7 654 // CHECK1-NEXT: store i8** null, i8*** [[TMP171]], align 8 655 // CHECK1-NEXT: [[TMP172:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]], i32 0, i32 8 656 // CHECK1-NEXT: store i64 0, i64* [[TMP172]], align 8 657 // CHECK1-NEXT: [[TMP173:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS29]]) 658 // CHECK1-NEXT: [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0 659 // CHECK1-NEXT: br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED30:%.*]], label [[OMP_OFFLOAD_CONT31:%.*]] 660 // CHECK1: omp_offload.failed30: 661 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP108]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 662 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT31]] 663 // CHECK1: omp_offload.cont31: 664 // CHECK1-NEXT: br label [[OMP_IF_END33:%.*]] 665 // CHECK1: omp_if.else32: 666 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i64 [[TMP108]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 667 // CHECK1-NEXT: br label [[OMP_IF_END33]] 668 // CHECK1: omp_if.end33: 669 // CHECK1-NEXT: store i32 0, i32* [[NN]], align 4 670 // CHECK1-NEXT: [[TMP175:%.*]] = load i32, i32* [[NN]], align 4 671 // CHECK1-NEXT: [[CONV34:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 672 // CHECK1-NEXT: store i32 [[TMP175]], i32* [[CONV34]], align 4 673 // CHECK1-NEXT: [[TMP176:%.*]] = load i64, i64* [[NN_CASTED]], align 8 674 // CHECK1-NEXT: [[TMP177:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0 675 // CHECK1-NEXT: [[TMP178:%.*]] = bitcast i8** [[TMP177]] to i64* 676 // CHECK1-NEXT: store i64 [[TMP176]], i64* [[TMP178]], align 8 677 // CHECK1-NEXT: [[TMP179:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS36]], i32 0, i32 0 678 // CHECK1-NEXT: [[TMP180:%.*]] = bitcast i8** [[TMP179]] to i64* 679 // CHECK1-NEXT: store i64 [[TMP176]], i64* [[TMP180]], align 8 680 // CHECK1-NEXT: [[TMP181:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS37]], i64 0, i64 0 681 // CHECK1-NEXT: store i8* null, i8** [[TMP181]], align 8 682 // CHECK1-NEXT: [[TMP182:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS35]], i32 0, i32 0 683 // CHECK1-NEXT: [[TMP183:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS36]], i32 0, i32 0 684 // CHECK1-NEXT: [[KERNEL_ARGS38:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 685 // CHECK1-NEXT: [[TMP184:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]], i32 0, i32 0 686 // CHECK1-NEXT: store i32 1, i32* [[TMP184]], align 4 687 // CHECK1-NEXT: [[TMP185:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]], i32 0, i32 1 688 // CHECK1-NEXT: store i32 1, i32* [[TMP185]], align 4 689 // CHECK1-NEXT: [[TMP186:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]], i32 0, i32 2 690 // CHECK1-NEXT: store i8** [[TMP182]], i8*** [[TMP186]], align 8 691 // CHECK1-NEXT: [[TMP187:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]], i32 0, i32 3 692 // CHECK1-NEXT: store i8** [[TMP183]], i8*** [[TMP187]], align 8 693 // CHECK1-NEXT: [[TMP188:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]], i32 0, i32 4 694 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP188]], align 8 695 // CHECK1-NEXT: [[TMP189:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]], i32 0, i32 5 696 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP189]], align 8 697 // CHECK1-NEXT: [[TMP190:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]], i32 0, i32 6 698 // CHECK1-NEXT: store i8** null, i8*** [[TMP190]], align 8 699 // CHECK1-NEXT: [[TMP191:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]], i32 0, i32 7 700 // CHECK1-NEXT: store i8** null, i8*** [[TMP191]], align 8 701 // CHECK1-NEXT: [[TMP192:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]], i32 0, i32 8 702 // CHECK1-NEXT: store i64 0, i64* [[TMP192]], align 8 703 // CHECK1-NEXT: [[TMP193:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS38]]) 704 // CHECK1-NEXT: [[TMP194:%.*]] = icmp ne i32 [[TMP193]], 0 705 // CHECK1-NEXT: br i1 [[TMP194]], label [[OMP_OFFLOAD_FAILED39:%.*]], label [[OMP_OFFLOAD_CONT40:%.*]] 706 // CHECK1: omp_offload.failed39: 707 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i64 [[TMP176]]) #[[ATTR3]] 708 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT40]] 709 // CHECK1: omp_offload.cont40: 710 // CHECK1-NEXT: [[TMP195:%.*]] = load i32, i32* [[NN]], align 4 711 // CHECK1-NEXT: [[CONV42:%.*]] = bitcast i64* [[NN_CASTED41]] to i32* 712 // CHECK1-NEXT: store i32 [[TMP195]], i32* [[CONV42]], align 4 713 // CHECK1-NEXT: [[TMP196:%.*]] = load i64, i64* [[NN_CASTED41]], align 8 714 // CHECK1-NEXT: [[TMP197:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 0 715 // CHECK1-NEXT: [[TMP198:%.*]] = bitcast i8** [[TMP197]] to i64* 716 // CHECK1-NEXT: store i64 [[TMP196]], i64* [[TMP198]], align 8 717 // CHECK1-NEXT: [[TMP199:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS44]], i32 0, i32 0 718 // CHECK1-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i64* 719 // CHECK1-NEXT: store i64 [[TMP196]], i64* [[TMP200]], align 8 720 // CHECK1-NEXT: [[TMP201:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS45]], i64 0, i64 0 721 // CHECK1-NEXT: store i8* null, i8** [[TMP201]], align 8 722 // CHECK1-NEXT: [[TMP202:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS43]], i32 0, i32 0 723 // CHECK1-NEXT: [[TMP203:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS44]], i32 0, i32 0 724 // CHECK1-NEXT: [[KERNEL_ARGS46:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 725 // CHECK1-NEXT: [[TMP204:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]], i32 0, i32 0 726 // CHECK1-NEXT: store i32 1, i32* [[TMP204]], align 4 727 // CHECK1-NEXT: [[TMP205:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]], i32 0, i32 1 728 // CHECK1-NEXT: store i32 1, i32* [[TMP205]], align 4 729 // CHECK1-NEXT: [[TMP206:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]], i32 0, i32 2 730 // CHECK1-NEXT: store i8** [[TMP202]], i8*** [[TMP206]], align 8 731 // CHECK1-NEXT: [[TMP207:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]], i32 0, i32 3 732 // CHECK1-NEXT: store i8** [[TMP203]], i8*** [[TMP207]], align 8 733 // CHECK1-NEXT: [[TMP208:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]], i32 0, i32 4 734 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64** [[TMP208]], align 8 735 // CHECK1-NEXT: [[TMP209:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]], i32 0, i32 5 736 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i64** [[TMP209]], align 8 737 // CHECK1-NEXT: [[TMP210:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]], i32 0, i32 6 738 // CHECK1-NEXT: store i8** null, i8*** [[TMP210]], align 8 739 // CHECK1-NEXT: [[TMP211:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]], i32 0, i32 7 740 // CHECK1-NEXT: store i8** null, i8*** [[TMP211]], align 8 741 // CHECK1-NEXT: [[TMP212:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]], i32 0, i32 8 742 // CHECK1-NEXT: store i64 0, i64* [[TMP212]], align 8 743 // CHECK1-NEXT: [[TMP213:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS46]]) 744 // CHECK1-NEXT: [[TMP214:%.*]] = icmp ne i32 [[TMP213]], 0 745 // CHECK1-NEXT: br i1 [[TMP214]], label [[OMP_OFFLOAD_FAILED47:%.*]], label [[OMP_OFFLOAD_CONT48:%.*]] 746 // CHECK1: omp_offload.failed47: 747 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i64 [[TMP196]]) #[[ATTR3]] 748 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT48]] 749 // CHECK1: omp_offload.cont48: 750 // CHECK1-NEXT: [[TMP215:%.*]] = load i32, i32* [[A]], align 4 751 // CHECK1-NEXT: [[TMP216:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 752 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP216]]) 753 // CHECK1-NEXT: ret i32 [[TMP215]] 754 // 755 // 756 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 757 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 758 // CHECK1-NEXT: entry: 759 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 760 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 761 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 762 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 763 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 764 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 765 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 766 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 767 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 768 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 769 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 770 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 771 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 772 // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 773 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 774 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 775 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 776 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 777 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 778 // CHECK1-NEXT: ret void 779 // 780 // 781 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 782 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 783 // CHECK1-NEXT: entry: 784 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 785 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 786 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 787 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 788 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 789 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 790 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 791 // CHECK1-NEXT: ret void 792 // 793 // 794 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_privates_map. 795 // CHECK1-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 796 // CHECK1-NEXT: entry: 797 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 8 798 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 8 799 // CHECK1-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 8 800 // CHECK1-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 8 801 // CHECK1-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 8 802 // CHECK1-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 8 803 // CHECK1-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 8 804 // CHECK1-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 8 805 // CHECK1-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 8 806 // CHECK1-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 8 807 // CHECK1-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 8 808 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 809 // CHECK1-NEXT: [[TMP7:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 8 810 // CHECK1-NEXT: store [3 x i8*]* [[TMP6]], [3 x i8*]** [[TMP7]], align 8 811 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 812 // CHECK1-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 8 813 // CHECK1-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 8 814 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 815 // CHECK1-NEXT: [[TMP11:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 8 816 // CHECK1-NEXT: store [3 x i64]* [[TMP10]], [3 x i64]** [[TMP11]], align 8 817 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 818 // CHECK1-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 8 819 // CHECK1-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 8 820 // CHECK1-NEXT: ret void 821 // 822 // 823 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 824 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 825 // CHECK1-NEXT: entry: 826 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 827 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 828 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 829 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 830 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 831 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 832 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 8 833 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 8 834 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 8 835 // CHECK1-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 8 836 // CHECK1-NEXT: [[AA_CASTED_I:%.*]] = alloca i64, align 8 837 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i64, align 8 838 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED5_I:%.*]] = alloca i64, align 8 839 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 840 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 841 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 842 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 843 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 844 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 845 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 846 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 847 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 848 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 849 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 850 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 851 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 852 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 853 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 854 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 855 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 856 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 857 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 858 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !24 859 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !24 860 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 861 // CHECK1-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 862 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !24 863 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 864 // CHECK1-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !24 865 // CHECK1-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !24 866 // CHECK1-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !24 867 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 868 // CHECK1-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 869 // CHECK1-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 8, !noalias !24 870 // CHECK1-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 8, !noalias !24 871 // CHECK1-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 8, !noalias !24 872 // CHECK1-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 8, !noalias !24 873 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i64 0, i64 0 874 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i64 0, i64 0 875 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i64 0, i64 0 876 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 877 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 878 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 879 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 880 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0 881 // CHECK1-NEXT: store i32 1, i32* [[TMP27]], align 4, !noalias !24 882 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1 883 // CHECK1-NEXT: store i32 3, i32* [[TMP28]], align 4, !noalias !24 884 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2 885 // CHECK1-NEXT: store i8** [[TMP20]], i8*** [[TMP29]], align 8, !noalias !24 886 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3 887 // CHECK1-NEXT: store i8** [[TMP21]], i8*** [[TMP30]], align 8, !noalias !24 888 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4 889 // CHECK1-NEXT: store i64* [[TMP22]], i64** [[TMP31]], align 8, !noalias !24 890 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5 891 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP32]], align 8, !noalias !24 892 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6 893 // CHECK1-NEXT: store i8** null, i8*** [[TMP33]], align 8, !noalias !24 894 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7 895 // CHECK1-NEXT: store i8** null, i8*** [[TMP34]], align 8, !noalias !24 896 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8 897 // CHECK1-NEXT: store i64 0, i64* [[TMP35]], align 8, !noalias !24 898 // CHECK1-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB1]], i64 -1, i32 [[TMP25]], i32 [[TMP26]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 899 // CHECK1-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 900 // CHECK1-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 901 // CHECK1: omp_offload.failed.i: 902 // CHECK1-NEXT: [[TMP38:%.*]] = load i16, i16* [[TMP16]], align 2 903 // CHECK1-NEXT: [[CONV_I:%.*]] = bitcast i64* [[AA_CASTED_I]] to i16* 904 // CHECK1-NEXT: store i16 [[TMP38]], i16* [[CONV_I]], align 2, !noalias !24 905 // CHECK1-NEXT: [[TMP39:%.*]] = load i64, i64* [[AA_CASTED_I]], align 8, !noalias !24 906 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP23]], align 4 907 // CHECK1-NEXT: [[CONV4_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED_I]] to i32* 908 // CHECK1-NEXT: store i32 [[TMP40]], i32* [[CONV4_I]], align 4, !noalias !24 909 // CHECK1-NEXT: [[TMP41:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED_I]], align 8, !noalias !24 910 // CHECK1-NEXT: [[TMP42:%.*]] = load i32, i32* [[TMP24]], align 4 911 // CHECK1-NEXT: [[CONV6_I:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED5_I]] to i32* 912 // CHECK1-NEXT: store i32 [[TMP42]], i32* [[CONV6_I]], align 4, !noalias !24 913 // CHECK1-NEXT: [[TMP43:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED5_I]], align 8, !noalias !24 914 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP39]], i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR3]] 915 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 916 // CHECK1: .omp_outlined..1.exit: 917 // CHECK1-NEXT: ret i32 0 918 // 919 // 920 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 921 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR2]] { 922 // CHECK1-NEXT: entry: 923 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 924 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 925 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 926 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 927 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 928 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 929 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 930 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 931 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 932 // CHECK1-NEXT: ret void 933 // 934 // 935 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 936 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 937 // CHECK1-NEXT: entry: 938 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 939 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 940 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 941 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 942 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 943 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 944 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 945 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 946 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 947 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 948 // CHECK1-NEXT: ret void 949 // 950 // 951 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 952 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 953 // CHECK1-NEXT: entry: 954 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 955 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 956 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 957 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 958 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 959 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 960 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 961 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 962 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 963 // CHECK1-NEXT: ret void 964 // 965 // 966 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 967 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 968 // CHECK1-NEXT: entry: 969 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 970 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 971 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 972 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 973 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 974 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 975 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 976 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 977 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 978 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 979 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 980 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 981 // CHECK1-NEXT: ret void 982 // 983 // 984 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 985 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 986 // CHECK1-NEXT: entry: 987 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 988 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 989 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 990 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 991 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 992 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 993 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 994 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 995 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 996 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 997 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 998 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 999 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1000 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1001 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 1002 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1003 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 1004 // CHECK1-NEXT: ret void 1005 // 1006 // 1007 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 1008 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1009 // CHECK1-NEXT: entry: 1010 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1011 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1012 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1013 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1014 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1015 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1016 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1017 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1018 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1019 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1020 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1021 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1022 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1023 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 1024 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 1025 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1026 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1027 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1028 // CHECK1-NEXT: ret void 1029 // 1030 // 1031 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 1032 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 1033 // CHECK1-NEXT: entry: 1034 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1035 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1036 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1037 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1038 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1039 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1040 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1041 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1042 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1043 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1044 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1045 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1046 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1047 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1048 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1049 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1050 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1051 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1052 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1053 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1054 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1055 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1056 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1057 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1058 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1059 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1060 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1061 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1062 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1063 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1064 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 1065 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1066 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 1067 // CHECK1-NEXT: ret void 1068 // 1069 // 1070 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 1071 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 1072 // CHECK1-NEXT: entry: 1073 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1074 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1075 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1076 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1077 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1078 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1079 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1080 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1081 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1082 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1083 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1084 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1085 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1086 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1087 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1088 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1089 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1090 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1091 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1092 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1093 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1094 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1095 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1096 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1097 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1098 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1099 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1100 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1101 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1102 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1103 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1104 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1105 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 1106 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1107 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1108 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 1109 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 1110 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 1111 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 1112 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 1113 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1114 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1115 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 1116 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1117 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1118 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 1119 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1120 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 1121 // CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 1122 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 1123 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 1124 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 1125 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 1126 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 1127 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 1128 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 1129 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 1130 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1131 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 1132 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 1133 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 1134 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1135 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 1136 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 1137 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 1138 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 1139 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 1140 // CHECK1-NEXT: ret void 1141 // 1142 // 1143 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 1144 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1145 // CHECK1-NEXT: entry: 1146 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1147 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1148 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1149 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1150 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1151 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1152 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1153 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1154 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1155 // CHECK1-NEXT: ret void 1156 // 1157 // 1158 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..12 1159 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1160 // CHECK1-NEXT: entry: 1161 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1162 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1163 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1164 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1165 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1166 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1167 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1168 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1169 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1170 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1171 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1172 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1173 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1174 // CHECK1-NEXT: ret void 1175 // 1176 // 1177 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1178 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1179 // CHECK1-NEXT: entry: 1180 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1181 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1182 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1183 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1184 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1185 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1186 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1187 // CHECK1-NEXT: ret void 1188 // 1189 // 1190 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 1191 // CHECK1-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1192 // CHECK1-NEXT: entry: 1193 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1194 // CHECK1-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 1195 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1196 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1197 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1198 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 1199 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1200 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 1201 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1202 // CHECK1-NEXT: ret void 1203 // 1204 // 1205 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1206 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR2]] { 1207 // CHECK1-NEXT: entry: 1208 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1209 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1210 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 1211 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1212 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1213 // CHECK1-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 1214 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 1215 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[CONV]]) 1216 // CHECK1-NEXT: ret void 1217 // 1218 // 1219 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..17 1220 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 1221 // CHECK1-NEXT: entry: 1222 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1223 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1224 // CHECK1-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 1225 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1226 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1227 // CHECK1-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 1228 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 1229 // CHECK1-NEXT: ret void 1230 // 1231 // 1232 // CHECK1-LABEL: define {{[^@]+}}@_Z6bazzzziPi 1233 // CHECK1-SAME: (i32 noundef signext [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 1234 // CHECK1-NEXT: entry: 1235 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1236 // CHECK1-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 8 1237 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1238 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1239 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1240 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1241 // CHECK1-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 8 1242 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1243 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1244 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1245 // CHECK1-NEXT: [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64* 1246 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP3]], align 8 1247 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1248 // CHECK1-NEXT: [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64* 1249 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP5]], align 8 1250 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1251 // CHECK1-NEXT: store i8* null, i8** [[TMP6]], align 8 1252 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1253 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1254 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1255 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1256 // CHECK1-NEXT: store i32 1, i32* [[TMP9]], align 4 1257 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1258 // CHECK1-NEXT: store i32 1, i32* [[TMP10]], align 4 1259 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1260 // CHECK1-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 8 1261 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1262 // CHECK1-NEXT: store i8** [[TMP8]], i8*** [[TMP12]], align 8 1263 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1264 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64** [[TMP13]], align 8 1265 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1266 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i64** [[TMP14]], align 8 1267 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1268 // CHECK1-NEXT: store i8** null, i8*** [[TMP15]], align 8 1269 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1270 // CHECK1-NEXT: store i8** null, i8*** [[TMP16]], align 8 1271 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1272 // CHECK1-NEXT: store i64 0, i64* [[TMP17]], align 8 1273 // CHECK1-NEXT: [[TMP18:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1274 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 1275 // CHECK1-NEXT: br i1 [[TMP19]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1276 // CHECK1: omp_offload.failed: 1277 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i64 [[TMP1]]) #[[ATTR3]] 1278 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1279 // CHECK1: omp_offload.cont: 1280 // CHECK1-NEXT: ret void 1281 // 1282 // 1283 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 1284 // CHECK1-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 1285 // CHECK1-NEXT: entry: 1286 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1287 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1288 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1289 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 1290 // CHECK1-NEXT: ret void 1291 // 1292 // 1293 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..20 1294 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR2]] { 1295 // CHECK1-NEXT: entry: 1296 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1297 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1298 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1299 // CHECK1-NEXT: [[F:%.*]] = alloca i32*, align 8 1300 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1301 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1302 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1303 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1304 // CHECK1-NEXT: ret void 1305 // 1306 // 1307 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1308 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1309 // CHECK1-NEXT: entry: 1310 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1311 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1312 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1313 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1314 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1315 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1316 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1317 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1318 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1319 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1320 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1321 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1322 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1323 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1324 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1325 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1326 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1327 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1328 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1329 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1330 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1331 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1332 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1333 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1334 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1335 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1336 // CHECK1-NEXT: ret i32 [[TMP8]] 1337 // 1338 // 1339 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1340 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1341 // CHECK1-NEXT: entry: 1342 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1343 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1344 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1345 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1346 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1347 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1348 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1349 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1350 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1351 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1352 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1353 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1354 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1355 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1356 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1357 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1358 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1359 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1360 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1361 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1362 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1363 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1364 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1365 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1366 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1367 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1368 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1369 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1370 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1371 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1372 // CHECK1: omp_if.then: 1373 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1374 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1375 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1376 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1377 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i64 40, i1 false) 1378 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1379 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1380 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1381 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1382 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1383 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 1384 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1385 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1386 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1387 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1388 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1389 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1390 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1391 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1392 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1393 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 1394 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1395 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1396 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 1397 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1398 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1399 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 1400 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1401 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 1402 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1403 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1404 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1405 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1406 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1407 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1408 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1409 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 1410 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1411 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1412 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1413 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1414 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1415 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1416 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1417 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1418 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1419 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 1420 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1421 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1422 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1423 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1424 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1425 // CHECK1-NEXT: store i32 1, i32* [[TMP40]], align 4 1426 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1427 // CHECK1-NEXT: store i32 5, i32* [[TMP41]], align 4 1428 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1429 // CHECK1-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8 1430 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1431 // CHECK1-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 8 1432 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1433 // CHECK1-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 8 1434 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1435 // CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i64** [[TMP45]], align 8 1436 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1437 // CHECK1-NEXT: store i8** null, i8*** [[TMP46]], align 8 1438 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1439 // CHECK1-NEXT: store i8** null, i8*** [[TMP47]], align 8 1440 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1441 // CHECK1-NEXT: store i64 0, i64* [[TMP48]], align 8 1442 // CHECK1-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1443 // CHECK1-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 1444 // CHECK1-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1445 // CHECK1: omp_offload.failed: 1446 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1447 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1448 // CHECK1: omp_offload.cont: 1449 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1450 // CHECK1: omp_if.else: 1451 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]] 1452 // CHECK1-NEXT: br label [[OMP_IF_END]] 1453 // CHECK1: omp_if.end: 1454 // CHECK1-NEXT: [[TMP51:%.*]] = mul nsw i64 1, [[TMP2]] 1455 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP51]] 1456 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1457 // CHECK1-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1458 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP52]] to i32 1459 // CHECK1-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4 1460 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP53]] 1461 // CHECK1-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1462 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP54]]) 1463 // CHECK1-NEXT: ret i32 [[ADD4]] 1464 // 1465 // 1466 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1467 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1468 // CHECK1-NEXT: entry: 1469 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1470 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1471 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1472 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1473 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1474 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1475 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1476 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1477 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1478 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1479 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1480 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1481 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1482 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1483 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1484 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1485 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1486 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1487 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1488 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1489 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1490 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1491 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1492 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1493 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1494 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1495 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1496 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1497 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1498 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1499 // CHECK1: omp_if.then: 1500 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1501 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1502 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1503 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1504 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1505 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1506 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1507 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1508 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1509 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1510 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1511 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1512 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1513 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1514 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1515 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1516 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1517 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1518 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1519 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1520 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1521 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1522 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1523 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1524 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1525 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1526 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1527 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1528 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1529 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1530 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1531 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1532 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1533 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1534 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1535 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1536 // CHECK1-NEXT: store i32 1, i32* [[TMP29]], align 4 1537 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1538 // CHECK1-NEXT: store i32 4, i32* [[TMP30]], align 4 1539 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1540 // CHECK1-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 8 1541 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1542 // CHECK1-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8 1543 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1544 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64** [[TMP33]], align 8 1545 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1546 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i64** [[TMP34]], align 8 1547 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1548 // CHECK1-NEXT: store i8** null, i8*** [[TMP35]], align 8 1549 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1550 // CHECK1-NEXT: store i8** null, i8*** [[TMP36]], align 8 1551 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1552 // CHECK1-NEXT: store i64 0, i64* [[TMP37]], align 8 1553 // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1554 // CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 1555 // CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1556 // CHECK1: omp_offload.failed: 1557 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 1558 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1559 // CHECK1: omp_offload.cont: 1560 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1561 // CHECK1: omp_if.else: 1562 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 1563 // CHECK1-NEXT: br label [[OMP_IF_END]] 1564 // CHECK1: omp_if.end: 1565 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 1566 // CHECK1-NEXT: ret i32 [[TMP40]] 1567 // 1568 // 1569 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1570 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1571 // CHECK1-NEXT: entry: 1572 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1573 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1574 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1575 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1576 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1577 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1578 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1579 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1580 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1581 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1582 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1583 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1584 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1585 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1586 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1587 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1588 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1589 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1590 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1591 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1592 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1593 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1594 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1595 // CHECK1: omp_if.then: 1596 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1597 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1598 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1599 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1600 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1601 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1602 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1603 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1604 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1605 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1606 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1607 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1608 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1609 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1610 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1611 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1612 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1613 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1614 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1615 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1616 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1617 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1618 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1619 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1620 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1621 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1622 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1623 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1624 // CHECK1-NEXT: store i32 1, i32* [[TMP22]], align 4 1625 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1626 // CHECK1-NEXT: store i32 3, i32* [[TMP23]], align 4 1627 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1628 // CHECK1-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8 1629 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1630 // CHECK1-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 8 1631 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1632 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64** [[TMP26]], align 8 1633 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1634 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i64** [[TMP27]], align 8 1635 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1636 // CHECK1-NEXT: store i8** null, i8*** [[TMP28]], align 8 1637 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1638 // CHECK1-NEXT: store i8** null, i8*** [[TMP29]], align 8 1639 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1640 // CHECK1-NEXT: store i64 0, i64* [[TMP30]], align 8 1641 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1642 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1643 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1644 // CHECK1: omp_offload.failed: 1645 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1646 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1647 // CHECK1: omp_offload.cont: 1648 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1649 // CHECK1: omp_if.else: 1650 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 1651 // CHECK1-NEXT: br label [[OMP_IF_END]] 1652 // CHECK1: omp_if.end: 1653 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4 1654 // CHECK1-NEXT: ret i32 [[TMP33]] 1655 // 1656 // 1657 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 1658 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1659 // CHECK1-NEXT: entry: 1660 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1661 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1662 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1663 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1664 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1665 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1666 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1667 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1668 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1669 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1670 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1671 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1672 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1673 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1674 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1675 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1676 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1677 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1678 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1679 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1680 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1681 // CHECK1-NEXT: ret void 1682 // 1683 // 1684 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..23 1685 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1686 // CHECK1-NEXT: entry: 1687 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1688 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1689 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1690 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1691 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1692 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1693 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1694 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1695 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1696 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1697 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1698 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1699 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1700 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1701 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1702 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1703 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1704 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1705 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1706 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1707 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 1708 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 1709 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1710 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1711 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1712 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 1713 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 1714 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 1715 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1716 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 1717 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 1718 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1719 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 1720 // CHECK1-NEXT: ret void 1721 // 1722 // 1723 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 1724 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1725 // CHECK1-NEXT: entry: 1726 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1727 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1728 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1729 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1730 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1731 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1732 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1733 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1734 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1735 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1736 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1737 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1738 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1739 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1740 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1741 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1742 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1743 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1744 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1745 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1746 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1747 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1748 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1749 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1750 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1751 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1752 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1753 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1754 // CHECK1-NEXT: ret void 1755 // 1756 // 1757 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..26 1758 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1759 // CHECK1-NEXT: entry: 1760 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1761 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1762 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1763 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1764 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1765 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1766 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1767 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1768 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1769 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1770 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1771 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1772 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1773 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1774 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1775 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1776 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1777 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1778 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1779 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1780 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 1781 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1782 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1783 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 1784 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 1785 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 1786 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 1787 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 1788 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 1789 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1790 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1791 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 1792 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 1793 // CHECK1-NEXT: ret void 1794 // 1795 // 1796 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 1797 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1798 // CHECK1-NEXT: entry: 1799 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1800 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1801 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1802 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1803 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1804 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1805 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1806 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1807 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1808 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1809 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1810 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1811 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1812 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1813 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1814 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1815 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1816 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1817 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1818 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1819 // CHECK1-NEXT: ret void 1820 // 1821 // 1822 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..29 1823 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1824 // CHECK1-NEXT: entry: 1825 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1826 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1827 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1828 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1829 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1830 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1831 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1832 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1833 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1834 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1835 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1836 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1837 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1838 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1839 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1840 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1841 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1842 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1843 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1844 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1845 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1846 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1847 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1848 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 1849 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 1850 // CHECK1-NEXT: ret void 1851 // 1852 // 1853 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1854 // CHECK1-SAME: () #[[ATTR4]] { 1855 // CHECK1-NEXT: entry: 1856 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1857 // CHECK1-NEXT: ret void 1858 // 1859 // 1860 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1861 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1862 // CHECK3-NEXT: entry: 1863 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1864 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1865 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1866 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1867 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1868 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1869 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1870 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1871 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1872 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1873 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32, align 4 1874 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1875 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1876 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i32, align 4 1877 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1878 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1879 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1880 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 4 1881 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1882 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 1883 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [1 x i8*], align 4 1884 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [1 x i8*], align 4 1885 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [1 x i8*], align 4 1886 // CHECK3-NEXT: [[A_CASTED9:%.*]] = alloca i32, align 4 1887 // CHECK3-NEXT: [[AA_CASTED10:%.*]] = alloca i32, align 4 1888 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS12:%.*]] = alloca [2 x i8*], align 4 1889 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS13:%.*]] = alloca [2 x i8*], align 4 1890 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS14:%.*]] = alloca [2 x i8*], align 4 1891 // CHECK3-NEXT: [[A_CASTED18:%.*]] = alloca i32, align 4 1892 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [9 x i8*], align 4 1893 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [9 x i8*], align 4 1894 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [9 x i8*], align 4 1895 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 1896 // CHECK3-NEXT: [[NN:%.*]] = alloca i32, align 4 1897 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 1898 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS29:%.*]] = alloca [1 x i8*], align 4 1899 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS30:%.*]] = alloca [1 x i8*], align 4 1900 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS31:%.*]] = alloca [1 x i8*], align 4 1901 // CHECK3-NEXT: [[NN_CASTED35:%.*]] = alloca i32, align 4 1902 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS36:%.*]] = alloca [1 x i8*], align 4 1903 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS37:%.*]] = alloca [1 x i8*], align 4 1904 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS38:%.*]] = alloca [1 x i8*], align 4 1905 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1906 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1907 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1908 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1909 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1910 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1911 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1912 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 1913 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 1914 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1915 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 1916 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 1917 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 1918 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1919 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR_]], align 4 1920 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 1921 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[DOTCAPTURE_EXPR_2]], align 4 1922 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[AA]], align 2 1923 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1924 // CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV]], align 2 1925 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1926 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1927 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1928 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1929 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1930 // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 1931 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED3]], align 4 1932 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1933 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1934 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP14]], align 4 1935 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1936 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 1937 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP16]], align 4 1938 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1939 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 1940 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1941 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1942 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP19]], align 4 1943 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1944 // CHECK3-NEXT: [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32* 1945 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[TMP21]], align 4 1946 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1947 // CHECK3-NEXT: store i8* null, i8** [[TMP22]], align 4 1948 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1949 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 1950 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP24]], align 4 1951 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1952 // CHECK3-NEXT: [[TMP26:%.*]] = bitcast i8** [[TMP25]] to i32* 1953 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP26]], align 4 1954 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1955 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4 1956 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1957 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1958 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 0 1959 // CHECK3-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2 1960 // CHECK3-NEXT: store i16 [[TMP31]], i16* [[TMP30]], align 4 1961 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 1 1962 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1963 // CHECK3-NEXT: store i32 [[TMP33]], i32* [[TMP32]], align 4 1964 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[AGG_CAPTURED]], i32 0, i32 2 1965 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_2]], align 4 1966 // CHECK3-NEXT: store i32 [[TMP35]], i32* [[TMP34]], align 4 1967 // CHECK3-NEXT: [[TMP36:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 72, i32 12, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 1968 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8* [[TMP36]] to %struct.kmp_task_t_with_privates* 1969 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 0 1970 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP38]], i32 0, i32 0 1971 // CHECK3-NEXT: [[TMP40:%.*]] = load i8*, i8** [[TMP39]], align 4 1972 // CHECK3-NEXT: [[TMP41:%.*]] = bitcast %struct.anon* [[AGG_CAPTURED]] to i8* 1973 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP40]], i8* align 4 [[TMP41]], i32 12, i1 false) 1974 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP37]], i32 0, i32 1 1975 // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8* [[TMP40]] to %struct.anon* 1976 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 0 1977 // CHECK3-NEXT: [[TMP45:%.*]] = bitcast [3 x i64]* [[TMP44]] to i8* 1978 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP45]], i8* align 4 bitcast ([3 x i64]* @.offload_sizes to i8*), i32 24, i1 false) 1979 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 1 1980 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast [3 x i8*]* [[TMP46]] to i8* 1981 // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP28]] to i8* 1982 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP47]], i8* align 4 [[TMP48]], i32 12, i1 false) 1983 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 2 1984 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast [3 x i8*]* [[TMP49]] to i8* 1985 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP29]] to i8* 1986 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP50]], i8* align 4 [[TMP51]], i32 12, i1 false) 1987 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP42]], i32 0, i32 3 1988 // CHECK3-NEXT: [[TMP53:%.*]] = load i16, i16* [[AA]], align 2 1989 // CHECK3-NEXT: store i16 [[TMP53]], i16* [[TMP52]], align 4 1990 // CHECK3-NEXT: [[TMP54:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP36]]) 1991 // CHECK3-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 1992 // CHECK3-NEXT: store i32 [[TMP55]], i32* [[A_CASTED]], align 4 1993 // CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[A_CASTED]], align 4 1994 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105(i32 [[TMP56]]) #[[ATTR3:[0-9]+]] 1995 // CHECK3-NEXT: [[TMP57:%.*]] = load i16, i16* [[AA]], align 2 1996 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 1997 // CHECK3-NEXT: store i16 [[TMP57]], i16* [[CONV5]], align 2 1998 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 1999 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2000 // CHECK3-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i32* 2001 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP60]], align 4 2002 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2003 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 2004 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[TMP62]], align 4 2005 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 2006 // CHECK3-NEXT: store i8* null, i8** [[TMP63]], align 4 2007 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2008 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2009 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2010 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 2011 // CHECK3-NEXT: store i32 1, i32* [[TMP66]], align 4 2012 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 2013 // CHECK3-NEXT: store i32 1, i32* [[TMP67]], align 4 2014 // CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 2015 // CHECK3-NEXT: store i8** [[TMP64]], i8*** [[TMP68]], align 4 2016 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 2017 // CHECK3-NEXT: store i8** [[TMP65]], i8*** [[TMP69]], align 4 2018 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 2019 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.4, i32 0, i32 0), i64** [[TMP70]], align 4 2020 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 2021 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.5, i32 0, i32 0), i64** [[TMP71]], align 4 2022 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 2023 // CHECK3-NEXT: store i8** null, i8*** [[TMP72]], align 4 2024 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 2025 // CHECK3-NEXT: store i8** null, i8*** [[TMP73]], align 4 2026 // CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 2027 // CHECK3-NEXT: store i64 0, i64* [[TMP74]], align 8 2028 // CHECK3-NEXT: [[TMP75:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 2029 // CHECK3-NEXT: [[TMP76:%.*]] = icmp ne i32 [[TMP75]], 0 2030 // CHECK3-NEXT: br i1 [[TMP76]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2031 // CHECK3: omp_offload.failed: 2032 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111(i32 [[TMP58]]) #[[ATTR3]] 2033 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2034 // CHECK3: omp_offload.cont: 2035 // CHECK3-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 2036 // CHECK3-NEXT: store i32 [[TMP77]], i32* [[A_CASTED9]], align 4 2037 // CHECK3-NEXT: [[TMP78:%.*]] = load i32, i32* [[A_CASTED9]], align 4 2038 // CHECK3-NEXT: [[TMP79:%.*]] = load i16, i16* [[AA]], align 2 2039 // CHECK3-NEXT: [[CONV11:%.*]] = bitcast i32* [[AA_CASTED10]] to i16* 2040 // CHECK3-NEXT: store i16 [[TMP79]], i16* [[CONV11]], align 2 2041 // CHECK3-NEXT: [[TMP80:%.*]] = load i32, i32* [[AA_CASTED10]], align 4 2042 // CHECK3-NEXT: [[TMP81:%.*]] = load i32, i32* [[N_ADDR]], align 4 2043 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP81]], 10 2044 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2045 // CHECK3: omp_if.then: 2046 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 2047 // CHECK3-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to i32* 2048 // CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP83]], align 4 2049 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 2050 // CHECK3-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to i32* 2051 // CHECK3-NEXT: store i32 [[TMP78]], i32* [[TMP85]], align 4 2052 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 0 2053 // CHECK3-NEXT: store i8* null, i8** [[TMP86]], align 4 2054 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 1 2055 // CHECK3-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 2056 // CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP88]], align 4 2057 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 1 2058 // CHECK3-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i32* 2059 // CHECK3-NEXT: store i32 [[TMP80]], i32* [[TMP90]], align 4 2060 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS14]], i32 0, i32 1 2061 // CHECK3-NEXT: store i8* null, i8** [[TMP91]], align 4 2062 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS12]], i32 0, i32 0 2063 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS13]], i32 0, i32 0 2064 // CHECK3-NEXT: [[KERNEL_ARGS15:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2065 // CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]], i32 0, i32 0 2066 // CHECK3-NEXT: store i32 1, i32* [[TMP94]], align 4 2067 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]], i32 0, i32 1 2068 // CHECK3-NEXT: store i32 2, i32* [[TMP95]], align 4 2069 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]], i32 0, i32 2 2070 // CHECK3-NEXT: store i8** [[TMP92]], i8*** [[TMP96]], align 4 2071 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]], i32 0, i32 3 2072 // CHECK3-NEXT: store i8** [[TMP93]], i8*** [[TMP97]], align 4 2073 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]], i32 0, i32 4 2074 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.7, i32 0, i32 0), i64** [[TMP98]], align 4 2075 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]], i32 0, i32 5 2076 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.8, i32 0, i32 0), i64** [[TMP99]], align 4 2077 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]], i32 0, i32 6 2078 // CHECK3-NEXT: store i8** null, i8*** [[TMP100]], align 4 2079 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]], i32 0, i32 7 2080 // CHECK3-NEXT: store i8** null, i8*** [[TMP101]], align 4 2081 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]], i32 0, i32 8 2082 // CHECK3-NEXT: store i64 0, i64* [[TMP102]], align 8 2083 // CHECK3-NEXT: [[TMP103:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS15]]) 2084 // CHECK3-NEXT: [[TMP104:%.*]] = icmp ne i32 [[TMP103]], 0 2085 // CHECK3-NEXT: br i1 [[TMP104]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 2086 // CHECK3: omp_offload.failed16: 2087 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP78]], i32 [[TMP80]]) #[[ATTR3]] 2088 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] 2089 // CHECK3: omp_offload.cont17: 2090 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2091 // CHECK3: omp_if.else: 2092 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118(i32 [[TMP78]], i32 [[TMP80]]) #[[ATTR3]] 2093 // CHECK3-NEXT: br label [[OMP_IF_END]] 2094 // CHECK3: omp_if.end: 2095 // CHECK3-NEXT: [[TMP105:%.*]] = load i32, i32* [[A]], align 4 2096 // CHECK3-NEXT: store i32 [[TMP105]], i32* [[A_CASTED18]], align 4 2097 // CHECK3-NEXT: [[TMP106:%.*]] = load i32, i32* [[A_CASTED18]], align 4 2098 // CHECK3-NEXT: [[TMP107:%.*]] = load i32, i32* [[N_ADDR]], align 4 2099 // CHECK3-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[TMP107]], 20 2100 // CHECK3-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]] 2101 // CHECK3: omp_if.then20: 2102 // CHECK3-NEXT: [[TMP108:%.*]] = mul nuw i32 [[TMP1]], 4 2103 // CHECK3-NEXT: [[TMP109:%.*]] = sext i32 [[TMP108]] to i64 2104 // CHECK3-NEXT: [[TMP110:%.*]] = mul nuw i32 5, [[TMP3]] 2105 // CHECK3-NEXT: [[TMP111:%.*]] = mul nuw i32 [[TMP110]], 8 2106 // CHECK3-NEXT: [[TMP112:%.*]] = sext i32 [[TMP111]] to i64 2107 // CHECK3-NEXT: [[TMP113:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2108 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP113]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.10 to i8*), i32 72, i1 false) 2109 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 2110 // CHECK3-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 2111 // CHECK3-NEXT: store i32 [[TMP106]], i32* [[TMP115]], align 4 2112 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 2113 // CHECK3-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 2114 // CHECK3-NEXT: store i32 [[TMP106]], i32* [[TMP117]], align 4 2115 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 0 2116 // CHECK3-NEXT: store i8* null, i8** [[TMP118]], align 4 2117 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 2118 // CHECK3-NEXT: [[TMP120:%.*]] = bitcast i8** [[TMP119]] to [10 x float]** 2119 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP120]], align 4 2120 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 2121 // CHECK3-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to [10 x float]** 2122 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP122]], align 4 2123 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 1 2124 // CHECK3-NEXT: store i8* null, i8** [[TMP123]], align 4 2125 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 2126 // CHECK3-NEXT: [[TMP125:%.*]] = bitcast i8** [[TMP124]] to i32* 2127 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP125]], align 4 2128 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 2129 // CHECK3-NEXT: [[TMP127:%.*]] = bitcast i8** [[TMP126]] to i32* 2130 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP127]], align 4 2131 // CHECK3-NEXT: [[TMP128:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 2 2132 // CHECK3-NEXT: store i8* null, i8** [[TMP128]], align 4 2133 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 2134 // CHECK3-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to float** 2135 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP130]], align 4 2136 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 2137 // CHECK3-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to float** 2138 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP132]], align 4 2139 // CHECK3-NEXT: [[TMP133:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2140 // CHECK3-NEXT: store i64 [[TMP109]], i64* [[TMP133]], align 4 2141 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 3 2142 // CHECK3-NEXT: store i8* null, i8** [[TMP134]], align 4 2143 // CHECK3-NEXT: [[TMP135:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4 2144 // CHECK3-NEXT: [[TMP136:%.*]] = bitcast i8** [[TMP135]] to [5 x [10 x double]]** 2145 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP136]], align 4 2146 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4 2147 // CHECK3-NEXT: [[TMP138:%.*]] = bitcast i8** [[TMP137]] to [5 x [10 x double]]** 2148 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP138]], align 4 2149 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 4 2150 // CHECK3-NEXT: store i8* null, i8** [[TMP139]], align 4 2151 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5 2152 // CHECK3-NEXT: [[TMP141:%.*]] = bitcast i8** [[TMP140]] to i32* 2153 // CHECK3-NEXT: store i32 5, i32* [[TMP141]], align 4 2154 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5 2155 // CHECK3-NEXT: [[TMP143:%.*]] = bitcast i8** [[TMP142]] to i32* 2156 // CHECK3-NEXT: store i32 5, i32* [[TMP143]], align 4 2157 // CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 5 2158 // CHECK3-NEXT: store i8* null, i8** [[TMP144]], align 4 2159 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6 2160 // CHECK3-NEXT: [[TMP146:%.*]] = bitcast i8** [[TMP145]] to i32* 2161 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP146]], align 4 2162 // CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6 2163 // CHECK3-NEXT: [[TMP148:%.*]] = bitcast i8** [[TMP147]] to i32* 2164 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP148]], align 4 2165 // CHECK3-NEXT: [[TMP149:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 6 2166 // CHECK3-NEXT: store i8* null, i8** [[TMP149]], align 4 2167 // CHECK3-NEXT: [[TMP150:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7 2168 // CHECK3-NEXT: [[TMP151:%.*]] = bitcast i8** [[TMP150]] to double** 2169 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP151]], align 4 2170 // CHECK3-NEXT: [[TMP152:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7 2171 // CHECK3-NEXT: [[TMP153:%.*]] = bitcast i8** [[TMP152]] to double** 2172 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP153]], align 4 2173 // CHECK3-NEXT: [[TMP154:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2174 // CHECK3-NEXT: store i64 [[TMP112]], i64* [[TMP154]], align 4 2175 // CHECK3-NEXT: [[TMP155:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 7 2176 // CHECK3-NEXT: store i8* null, i8** [[TMP155]], align 4 2177 // CHECK3-NEXT: [[TMP156:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8 2178 // CHECK3-NEXT: [[TMP157:%.*]] = bitcast i8** [[TMP156]] to %struct.TT** 2179 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP157]], align 4 2180 // CHECK3-NEXT: [[TMP158:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8 2181 // CHECK3-NEXT: [[TMP159:%.*]] = bitcast i8** [[TMP158]] to %struct.TT** 2182 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP159]], align 4 2183 // CHECK3-NEXT: [[TMP160:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i32 0, i32 8 2184 // CHECK3-NEXT: store i8* null, i8** [[TMP160]], align 4 2185 // CHECK3-NEXT: [[TMP161:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 2186 // CHECK3-NEXT: [[TMP162:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 2187 // CHECK3-NEXT: [[TMP163:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2188 // CHECK3-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2189 // CHECK3-NEXT: [[TMP164:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 0 2190 // CHECK3-NEXT: store i32 1, i32* [[TMP164]], align 4 2191 // CHECK3-NEXT: [[TMP165:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 1 2192 // CHECK3-NEXT: store i32 9, i32* [[TMP165]], align 4 2193 // CHECK3-NEXT: [[TMP166:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 2 2194 // CHECK3-NEXT: store i8** [[TMP161]], i8*** [[TMP166]], align 4 2195 // CHECK3-NEXT: [[TMP167:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 3 2196 // CHECK3-NEXT: store i8** [[TMP162]], i8*** [[TMP167]], align 4 2197 // CHECK3-NEXT: [[TMP168:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 4 2198 // CHECK3-NEXT: store i64* [[TMP163]], i64** [[TMP168]], align 4 2199 // CHECK3-NEXT: [[TMP169:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 5 2200 // CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.11, i32 0, i32 0), i64** [[TMP169]], align 4 2201 // CHECK3-NEXT: [[TMP170:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 6 2202 // CHECK3-NEXT: store i8** null, i8*** [[TMP170]], align 4 2203 // CHECK3-NEXT: [[TMP171:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 7 2204 // CHECK3-NEXT: store i8** null, i8*** [[TMP171]], align 4 2205 // CHECK3-NEXT: [[TMP172:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 8 2206 // CHECK3-NEXT: store i64 0, i64* [[TMP172]], align 8 2207 // CHECK3-NEXT: [[TMP173:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]]) 2208 // CHECK3-NEXT: [[TMP174:%.*]] = icmp ne i32 [[TMP173]], 0 2209 // CHECK3-NEXT: br i1 [[TMP174]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] 2210 // CHECK3: omp_offload.failed25: 2211 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP106]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 2212 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT26]] 2213 // CHECK3: omp_offload.cont26: 2214 // CHECK3-NEXT: br label [[OMP_IF_END28:%.*]] 2215 // CHECK3: omp_if.else27: 2216 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142(i32 [[TMP106]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]] 2217 // CHECK3-NEXT: br label [[OMP_IF_END28]] 2218 // CHECK3: omp_if.end28: 2219 // CHECK3-NEXT: store i32 0, i32* [[NN]], align 4 2220 // CHECK3-NEXT: [[TMP175:%.*]] = load i32, i32* [[NN]], align 4 2221 // CHECK3-NEXT: store i32 [[TMP175]], i32* [[NN_CASTED]], align 4 2222 // CHECK3-NEXT: [[TMP176:%.*]] = load i32, i32* [[NN_CASTED]], align 4 2223 // CHECK3-NEXT: [[TMP177:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 2224 // CHECK3-NEXT: [[TMP178:%.*]] = bitcast i8** [[TMP177]] to i32* 2225 // CHECK3-NEXT: store i32 [[TMP176]], i32* [[TMP178]], align 4 2226 // CHECK3-NEXT: [[TMP179:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 2227 // CHECK3-NEXT: [[TMP180:%.*]] = bitcast i8** [[TMP179]] to i32* 2228 // CHECK3-NEXT: store i32 [[TMP176]], i32* [[TMP180]], align 4 2229 // CHECK3-NEXT: [[TMP181:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS31]], i32 0, i32 0 2230 // CHECK3-NEXT: store i8* null, i8** [[TMP181]], align 4 2231 // CHECK3-NEXT: [[TMP182:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS29]], i32 0, i32 0 2232 // CHECK3-NEXT: [[TMP183:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS30]], i32 0, i32 0 2233 // CHECK3-NEXT: [[KERNEL_ARGS32:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2234 // CHECK3-NEXT: [[TMP184:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]], i32 0, i32 0 2235 // CHECK3-NEXT: store i32 1, i32* [[TMP184]], align 4 2236 // CHECK3-NEXT: [[TMP185:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]], i32 0, i32 1 2237 // CHECK3-NEXT: store i32 1, i32* [[TMP185]], align 4 2238 // CHECK3-NEXT: [[TMP186:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]], i32 0, i32 2 2239 // CHECK3-NEXT: store i8** [[TMP182]], i8*** [[TMP186]], align 4 2240 // CHECK3-NEXT: [[TMP187:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]], i32 0, i32 3 2241 // CHECK3-NEXT: store i8** [[TMP183]], i8*** [[TMP187]], align 4 2242 // CHECK3-NEXT: [[TMP188:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]], i32 0, i32 4 2243 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP188]], align 4 2244 // CHECK3-NEXT: [[TMP189:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]], i32 0, i32 5 2245 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP189]], align 4 2246 // CHECK3-NEXT: [[TMP190:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]], i32 0, i32 6 2247 // CHECK3-NEXT: store i8** null, i8*** [[TMP190]], align 4 2248 // CHECK3-NEXT: [[TMP191:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]], i32 0, i32 7 2249 // CHECK3-NEXT: store i8** null, i8*** [[TMP191]], align 4 2250 // CHECK3-NEXT: [[TMP192:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]], i32 0, i32 8 2251 // CHECK3-NEXT: store i64 0, i64* [[TMP192]], align 8 2252 // CHECK3-NEXT: [[TMP193:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS32]]) 2253 // CHECK3-NEXT: [[TMP194:%.*]] = icmp ne i32 [[TMP193]], 0 2254 // CHECK3-NEXT: br i1 [[TMP194]], label [[OMP_OFFLOAD_FAILED33:%.*]], label [[OMP_OFFLOAD_CONT34:%.*]] 2255 // CHECK3: omp_offload.failed33: 2256 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154(i32 [[TMP176]]) #[[ATTR3]] 2257 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT34]] 2258 // CHECK3: omp_offload.cont34: 2259 // CHECK3-NEXT: [[TMP195:%.*]] = load i32, i32* [[NN]], align 4 2260 // CHECK3-NEXT: store i32 [[TMP195]], i32* [[NN_CASTED35]], align 4 2261 // CHECK3-NEXT: [[TMP196:%.*]] = load i32, i32* [[NN_CASTED35]], align 4 2262 // CHECK3-NEXT: [[TMP197:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 2263 // CHECK3-NEXT: [[TMP198:%.*]] = bitcast i8** [[TMP197]] to i32* 2264 // CHECK3-NEXT: store i32 [[TMP196]], i32* [[TMP198]], align 4 2265 // CHECK3-NEXT: [[TMP199:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 2266 // CHECK3-NEXT: [[TMP200:%.*]] = bitcast i8** [[TMP199]] to i32* 2267 // CHECK3-NEXT: store i32 [[TMP196]], i32* [[TMP200]], align 4 2268 // CHECK3-NEXT: [[TMP201:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS38]], i32 0, i32 0 2269 // CHECK3-NEXT: store i8* null, i8** [[TMP201]], align 4 2270 // CHECK3-NEXT: [[TMP202:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS36]], i32 0, i32 0 2271 // CHECK3-NEXT: [[TMP203:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS37]], i32 0, i32 0 2272 // CHECK3-NEXT: [[KERNEL_ARGS39:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2273 // CHECK3-NEXT: [[TMP204:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]], i32 0, i32 0 2274 // CHECK3-NEXT: store i32 1, i32* [[TMP204]], align 4 2275 // CHECK3-NEXT: [[TMP205:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]], i32 0, i32 1 2276 // CHECK3-NEXT: store i32 1, i32* [[TMP205]], align 4 2277 // CHECK3-NEXT: [[TMP206:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]], i32 0, i32 2 2278 // CHECK3-NEXT: store i8** [[TMP202]], i8*** [[TMP206]], align 4 2279 // CHECK3-NEXT: [[TMP207:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]], i32 0, i32 3 2280 // CHECK3-NEXT: store i8** [[TMP203]], i8*** [[TMP207]], align 4 2281 // CHECK3-NEXT: [[TMP208:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]], i32 0, i32 4 2282 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.18, i32 0, i32 0), i64** [[TMP208]], align 4 2283 // CHECK3-NEXT: [[TMP209:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]], i32 0, i32 5 2284 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.19, i32 0, i32 0), i64** [[TMP209]], align 4 2285 // CHECK3-NEXT: [[TMP210:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]], i32 0, i32 6 2286 // CHECK3-NEXT: store i8** null, i8*** [[TMP210]], align 4 2287 // CHECK3-NEXT: [[TMP211:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]], i32 0, i32 7 2288 // CHECK3-NEXT: store i8** null, i8*** [[TMP211]], align 4 2289 // CHECK3-NEXT: [[TMP212:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]], i32 0, i32 8 2290 // CHECK3-NEXT: store i64 0, i64* [[TMP212]], align 8 2291 // CHECK3-NEXT: [[TMP213:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS39]]) 2292 // CHECK3-NEXT: [[TMP214:%.*]] = icmp ne i32 [[TMP213]], 0 2293 // CHECK3-NEXT: br i1 [[TMP214]], label [[OMP_OFFLOAD_FAILED40:%.*]], label [[OMP_OFFLOAD_CONT41:%.*]] 2294 // CHECK3: omp_offload.failed40: 2295 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157(i32 [[TMP196]]) #[[ATTR3]] 2296 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT41]] 2297 // CHECK3: omp_offload.cont41: 2298 // CHECK3-NEXT: [[TMP215:%.*]] = load i32, i32* [[A]], align 4 2299 // CHECK3-NEXT: [[TMP216:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2300 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP216]]) 2301 // CHECK3-NEXT: ret i32 [[TMP215]] 2302 // 2303 // 2304 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2305 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR2:[0-9]+]] { 2306 // CHECK3-NEXT: entry: 2307 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2308 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2309 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 2310 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2311 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2312 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2313 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2314 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 2315 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2316 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2317 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 2318 // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 2319 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2320 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2321 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 2322 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2323 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 2324 // CHECK3-NEXT: ret void 2325 // 2326 // 2327 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2328 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2329 // CHECK3-NEXT: entry: 2330 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2331 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2332 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2333 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2334 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2335 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2336 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2337 // CHECK3-NEXT: ret void 2338 // 2339 // 2340 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_privates_map. 2341 // CHECK3-SAME: (%struct..kmp_privates.t* noalias noundef [[TMP0:%.*]], i16** noalias noundef [[TMP1:%.*]], [3 x i8*]** noalias noundef [[TMP2:%.*]], [3 x i8*]** noalias noundef [[TMP3:%.*]], [3 x i64]** noalias noundef [[TMP4:%.*]]) #[[ATTR4:[0-9]+]] { 2342 // CHECK3-NEXT: entry: 2343 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca %struct..kmp_privates.t*, align 4 2344 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca i16**, align 4 2345 // CHECK3-NEXT: [[DOTADDR2:%.*]] = alloca [3 x i8*]**, align 4 2346 // CHECK3-NEXT: [[DOTADDR3:%.*]] = alloca [3 x i8*]**, align 4 2347 // CHECK3-NEXT: [[DOTADDR4:%.*]] = alloca [3 x i64]**, align 4 2348 // CHECK3-NEXT: store %struct..kmp_privates.t* [[TMP0]], %struct..kmp_privates.t** [[DOTADDR]], align 4 2349 // CHECK3-NEXT: store i16** [[TMP1]], i16*** [[DOTADDR1]], align 4 2350 // CHECK3-NEXT: store [3 x i8*]** [[TMP2]], [3 x i8*]*** [[DOTADDR2]], align 4 2351 // CHECK3-NEXT: store [3 x i8*]** [[TMP3]], [3 x i8*]*** [[DOTADDR3]], align 4 2352 // CHECK3-NEXT: store [3 x i64]** [[TMP4]], [3 x i64]*** [[DOTADDR4]], align 4 2353 // CHECK3-NEXT: [[TMP5:%.*]] = load %struct..kmp_privates.t*, %struct..kmp_privates.t** [[DOTADDR]], align 4 2354 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T:%.*]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 0 2355 // CHECK3-NEXT: [[TMP7:%.*]] = load [3 x i64]**, [3 x i64]*** [[DOTADDR4]], align 4 2356 // CHECK3-NEXT: store [3 x i64]* [[TMP6]], [3 x i64]** [[TMP7]], align 4 2357 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 1 2358 // CHECK3-NEXT: [[TMP9:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR2]], align 4 2359 // CHECK3-NEXT: store [3 x i8*]* [[TMP8]], [3 x i8*]** [[TMP9]], align 4 2360 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 2 2361 // CHECK3-NEXT: [[TMP11:%.*]] = load [3 x i8*]**, [3 x i8*]*** [[DOTADDR3]], align 4 2362 // CHECK3-NEXT: store [3 x i8*]* [[TMP10]], [3 x i8*]** [[TMP11]], align 4 2363 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT__KMP_PRIVATES_T]], %struct..kmp_privates.t* [[TMP5]], i32 0, i32 3 2364 // CHECK3-NEXT: [[TMP13:%.*]] = load i16**, i16*** [[DOTADDR1]], align 4 2365 // CHECK3-NEXT: store i16* [[TMP12]], i16** [[TMP13]], align 4 2366 // CHECK3-NEXT: ret void 2367 // 2368 // 2369 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2370 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2371 // CHECK3-NEXT: entry: 2372 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2373 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 2374 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 2375 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 2376 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 2377 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 2378 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR_I:%.*]] = alloca i16*, align 4 2379 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR1_I:%.*]] = alloca [3 x i8*]*, align 4 2380 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR2_I:%.*]] = alloca [3 x i8*]*, align 4 2381 // CHECK3-NEXT: [[DOTFIRSTPRIV_PTR_ADDR3_I:%.*]] = alloca [3 x i64]*, align 4 2382 // CHECK3-NEXT: [[AA_CASTED_I:%.*]] = alloca i32, align 4 2383 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED_I:%.*]] = alloca i32, align 4 2384 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED4_I:%.*]] = alloca i32, align 4 2385 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2386 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2387 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 2388 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2389 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2390 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2391 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2392 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2393 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2394 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2395 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 2396 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2397 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 1 2398 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast %struct..kmp_privates.t* [[TMP9]] to i8* 2399 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2400 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 2401 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 2402 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 2403 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 2404 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 2405 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !25 2406 // CHECK3-NEXT: store i8* [[TMP10]], i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 2407 // CHECK3-NEXT: store void (i8*, ...)* bitcast (void (%struct..kmp_privates.t*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* @.omp_task_privates_map. to void (i8*, ...)*), void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 2408 // CHECK3-NEXT: store i8* [[TMP11]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !25 2409 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 2410 // CHECK3-NEXT: [[TMP12:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !25 2411 // CHECK3-NEXT: [[TMP13:%.*]] = load void (i8*, ...)*, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !25 2412 // CHECK3-NEXT: [[TMP14:%.*]] = load i8*, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !25 2413 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast void (i8*, ...)* [[TMP13]] to void (i8*, i16**, [3 x i8*]**, [3 x i8*]**, [3 x i64]**)* 2414 // CHECK3-NEXT: call void [[TMP15]](i8* [[TMP14]], i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]]) #[[ATTR3]] 2415 // CHECK3-NEXT: [[TMP16:%.*]] = load i16*, i16** [[DOTFIRSTPRIV_PTR_ADDR_I]], align 4, !noalias !25 2416 // CHECK3-NEXT: [[TMP17:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR1_I]], align 4, !noalias !25 2417 // CHECK3-NEXT: [[TMP18:%.*]] = load [3 x i8*]*, [3 x i8*]** [[DOTFIRSTPRIV_PTR_ADDR2_I]], align 4, !noalias !25 2418 // CHECK3-NEXT: [[TMP19:%.*]] = load [3 x i64]*, [3 x i64]** [[DOTFIRSTPRIV_PTR_ADDR3_I]], align 4, !noalias !25 2419 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP17]], i32 0, i32 0 2420 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[TMP18]], i32 0, i32 0 2421 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i64], [3 x i64]* [[TMP19]], i32 0, i32 0 2422 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP12]], i32 0, i32 1 2423 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP12]], i32 0, i32 2 2424 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP23]], align 4 2425 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP24]], align 4 2426 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0 2427 // CHECK3-NEXT: store i32 1, i32* [[TMP27]], align 4, !noalias !25 2428 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1 2429 // CHECK3-NEXT: store i32 3, i32* [[TMP28]], align 4, !noalias !25 2430 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2 2431 // CHECK3-NEXT: store i8** [[TMP20]], i8*** [[TMP29]], align 4, !noalias !25 2432 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3 2433 // CHECK3-NEXT: store i8** [[TMP21]], i8*** [[TMP30]], align 4, !noalias !25 2434 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4 2435 // CHECK3-NEXT: store i64* [[TMP22]], i64** [[TMP31]], align 4, !noalias !25 2436 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5 2437 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP32]], align 4, !noalias !25 2438 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6 2439 // CHECK3-NEXT: store i8** null, i8*** [[TMP33]], align 4, !noalias !25 2440 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7 2441 // CHECK3-NEXT: store i8** null, i8*** [[TMP34]], align 4, !noalias !25 2442 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8 2443 // CHECK3-NEXT: store i64 0, i64* [[TMP35]], align 8, !noalias !25 2444 // CHECK3-NEXT: [[TMP36:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB1]], i64 -1, i32 [[TMP25]], i32 [[TMP26]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) #[[ATTR3]] 2445 // CHECK3-NEXT: [[TMP37:%.*]] = icmp ne i32 [[TMP36]], 0 2446 // CHECK3-NEXT: br i1 [[TMP37]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2447 // CHECK3: omp_offload.failed.i: 2448 // CHECK3-NEXT: [[TMP38:%.*]] = load i16, i16* [[TMP16]], align 2 2449 // CHECK3-NEXT: [[CONV_I:%.*]] = bitcast i32* [[AA_CASTED_I]] to i16* 2450 // CHECK3-NEXT: store i16 [[TMP38]], i16* [[CONV_I]], align 2, !noalias !25 2451 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[AA_CASTED_I]], align 4, !noalias !25 2452 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP23]], align 4 2453 // CHECK3-NEXT: store i32 [[TMP40]], i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 2454 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED_I]], align 4, !noalias !25 2455 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[TMP24]], align 4 2456 // CHECK3-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 2457 // CHECK3-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED4_I]], align 4, !noalias !25 2458 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP39]], i32 [[TMP41]], i32 [[TMP43]]) #[[ATTR3]] 2459 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2460 // CHECK3: .omp_outlined..1.exit: 2461 // CHECK3-NEXT: ret i32 0 2462 // 2463 // 2464 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l105 2465 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR2]] { 2466 // CHECK3-NEXT: entry: 2467 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2468 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2469 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2470 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2471 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2472 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2473 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2474 // CHECK3-NEXT: ret void 2475 // 2476 // 2477 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2478 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2479 // CHECK3-NEXT: entry: 2480 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2481 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2482 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2483 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2484 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2485 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2486 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2487 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2488 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2489 // CHECK3-NEXT: ret void 2490 // 2491 // 2492 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 2493 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2494 // CHECK3-NEXT: entry: 2495 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2496 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2497 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2498 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2499 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2500 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2501 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2502 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2503 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2504 // CHECK3-NEXT: ret void 2505 // 2506 // 2507 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2508 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2509 // CHECK3-NEXT: entry: 2510 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2511 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2512 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2513 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2514 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2515 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2516 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2517 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2518 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2519 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 2520 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2521 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 2522 // CHECK3-NEXT: ret void 2523 // 2524 // 2525 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 2526 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2527 // CHECK3-NEXT: entry: 2528 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2529 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2530 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2531 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2532 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2533 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2534 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2535 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2536 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2537 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2538 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2539 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2540 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2541 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2542 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2543 // CHECK3-NEXT: ret void 2544 // 2545 // 2546 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 2547 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2548 // CHECK3-NEXT: entry: 2549 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2550 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2551 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2552 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2553 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2554 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2555 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2556 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2557 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2558 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2559 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2560 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2561 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 2562 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 2563 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 2564 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 2565 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 2566 // CHECK3-NEXT: ret void 2567 // 2568 // 2569 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 2570 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 2571 // CHECK3-NEXT: entry: 2572 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2573 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2574 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2575 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2576 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2577 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2578 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2579 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2580 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2581 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2582 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2583 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2584 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2585 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2586 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2587 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2588 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2589 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2590 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2591 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2592 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2593 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2594 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2595 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2596 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2597 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2598 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2599 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2600 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2601 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2602 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2603 // CHECK3-NEXT: ret void 2604 // 2605 // 2606 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 2607 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 2608 // CHECK3-NEXT: entry: 2609 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2610 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2611 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2612 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2613 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2614 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2615 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2616 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2617 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2618 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2619 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2620 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2621 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2622 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2623 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2624 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2625 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2626 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2627 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2628 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2629 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2630 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2631 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2632 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2633 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2634 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2635 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2636 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2637 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2638 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2639 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2640 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 2641 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2642 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2643 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2644 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 2645 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 2646 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 2647 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 2648 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2649 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2650 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 2651 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 2652 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 2653 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 2654 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2655 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 2656 // CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 2657 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 2658 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 2659 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 2660 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 2661 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 2662 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 2663 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 2664 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 2665 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2666 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 2667 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 2668 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 2669 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2670 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 2671 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 2672 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 2673 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 2674 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 2675 // CHECK3-NEXT: ret void 2676 // 2677 // 2678 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 2679 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2680 // CHECK3-NEXT: entry: 2681 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2682 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 2683 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2684 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 2685 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 2686 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 2687 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..12 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2688 // CHECK3-NEXT: ret void 2689 // 2690 // 2691 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..12 2692 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2693 // CHECK3-NEXT: entry: 2694 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2695 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2696 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2697 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 2698 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2699 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2700 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2701 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 2702 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 2703 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 2704 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2705 // CHECK3-NEXT: ret void 2706 // 2707 // 2708 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 2709 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2710 // CHECK3-NEXT: entry: 2711 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2712 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2713 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2714 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2715 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2716 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2717 // CHECK3-NEXT: ret void 2718 // 2719 // 2720 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 2721 // CHECK3-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2722 // CHECK3-NEXT: entry: 2723 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2724 // CHECK3-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 2725 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2726 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 2727 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 2728 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 2729 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2730 // CHECK3-NEXT: ret void 2731 // 2732 // 2733 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 2734 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR2]] { 2735 // CHECK3-NEXT: entry: 2736 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2737 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2738 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 2739 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2740 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2741 // CHECK3-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 2742 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..17 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 2743 // CHECK3-NEXT: ret void 2744 // 2745 // 2746 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..17 2747 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR2]] { 2748 // CHECK3-NEXT: entry: 2749 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2750 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2751 // CHECK3-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 2752 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2753 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2754 // CHECK3-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 2755 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 2756 // CHECK3-NEXT: ret void 2757 // 2758 // 2759 // CHECK3-LABEL: define {{[^@]+}}@_Z6bazzzziPi 2760 // CHECK3-SAME: (i32 noundef [[N:%.*]], i32* noundef [[F:%.*]]) #[[ATTR0]] { 2761 // CHECK3-NEXT: entry: 2762 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2763 // CHECK3-NEXT: [[F_ADDR:%.*]] = alloca i32*, align 4 2764 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2765 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2766 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2767 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2768 // CHECK3-NEXT: store i32* [[F]], i32** [[F_ADDR]], align 4 2769 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2770 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2771 // CHECK3-NEXT: [[TMP2:%.*]] = bitcast i8** [[TMP1]] to i32* 2772 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP2]], align 4 2773 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2774 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 2775 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[TMP4]], align 4 2776 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2777 // CHECK3-NEXT: store i8* null, i8** [[TMP5]], align 4 2778 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2779 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2780 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2781 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 2782 // CHECK3-NEXT: store i32 1, i32* [[TMP8]], align 4 2783 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 2784 // CHECK3-NEXT: store i32 1, i32* [[TMP9]], align 4 2785 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 2786 // CHECK3-NEXT: store i8** [[TMP6]], i8*** [[TMP10]], align 4 2787 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 2788 // CHECK3-NEXT: store i8** [[TMP7]], i8*** [[TMP11]], align 4 2789 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 2790 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.21, i32 0, i32 0), i64** [[TMP12]], align 4 2791 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 2792 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.22, i32 0, i32 0), i64** [[TMP13]], align 4 2793 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 2794 // CHECK3-NEXT: store i8** null, i8*** [[TMP14]], align 4 2795 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 2796 // CHECK3-NEXT: store i8** null, i8*** [[TMP15]], align 4 2797 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 2798 // CHECK3-NEXT: store i64 0, i64* [[TMP16]], align 8 2799 // CHECK3-NEXT: [[TMP17:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 2800 // CHECK3-NEXT: [[TMP18:%.*]] = icmp ne i32 [[TMP17]], 0 2801 // CHECK3-NEXT: br i1 [[TMP18]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2802 // CHECK3: omp_offload.failed: 2803 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182(i32 [[TMP0]]) #[[ATTR3]] 2804 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2805 // CHECK3: omp_offload.cont: 2806 // CHECK3-NEXT: ret void 2807 // 2808 // 2809 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 2810 // CHECK3-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 2811 // CHECK3-NEXT: entry: 2812 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2813 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2814 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2815 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..20 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 2816 // CHECK3-NEXT: ret void 2817 // 2818 // 2819 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..20 2820 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR2]] { 2821 // CHECK3-NEXT: entry: 2822 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2823 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2824 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2825 // CHECK3-NEXT: [[F:%.*]] = alloca i32*, align 4 2826 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2827 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2828 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2829 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2830 // CHECK3-NEXT: ret void 2831 // 2832 // 2833 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2834 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2835 // CHECK3-NEXT: entry: 2836 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2837 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2838 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2839 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2840 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2841 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2842 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2843 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2844 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2845 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2846 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2847 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2848 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2849 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2850 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2851 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2852 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2853 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2854 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2855 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2856 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2857 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2858 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2859 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2860 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2861 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2862 // CHECK3-NEXT: ret i32 [[TMP8]] 2863 // 2864 // 2865 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2866 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2867 // CHECK3-NEXT: entry: 2868 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2869 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2870 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2871 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2872 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2873 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2874 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2875 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2876 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2877 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2878 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2879 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2880 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2881 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2882 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2883 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 2884 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2885 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2886 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2887 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2888 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2889 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2890 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 2891 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 2892 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 2893 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2894 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 2895 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2896 // CHECK3: omp_if.then: 2897 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2898 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 2899 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 2900 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 2901 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2902 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.24 to i8*), i32 40, i1 false) 2903 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2904 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 2905 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 2906 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2907 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 2908 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 2909 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2910 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 2911 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2912 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 2913 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 2914 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2915 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 2916 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 2917 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2918 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 2919 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2920 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 2921 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 2922 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2923 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 2924 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 2925 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2926 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 2927 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2928 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2929 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 2930 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2931 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 2932 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 2933 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2934 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 2935 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2936 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 2937 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 2938 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2939 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 2940 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 2941 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2942 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 2943 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2944 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 2945 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2946 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2947 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2948 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2949 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 2950 // CHECK3-NEXT: store i32 1, i32* [[TMP40]], align 4 2951 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 2952 // CHECK3-NEXT: store i32 5, i32* [[TMP41]], align 4 2953 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 2954 // CHECK3-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4 2955 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 2956 // CHECK3-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 4 2957 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 2958 // CHECK3-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 4 2959 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 2960 // CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.25, i32 0, i32 0), i64** [[TMP45]], align 4 2961 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 2962 // CHECK3-NEXT: store i8** null, i8*** [[TMP46]], align 4 2963 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 2964 // CHECK3-NEXT: store i8** null, i8*** [[TMP47]], align 4 2965 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 2966 // CHECK3-NEXT: store i64 0, i64* [[TMP48]], align 8 2967 // CHECK3-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 2968 // CHECK3-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 2969 // CHECK3-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2970 // CHECK3: omp_offload.failed: 2971 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 2972 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2973 // CHECK3: omp_offload.cont: 2974 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2975 // CHECK3: omp_if.else: 2976 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]] 2977 // CHECK3-NEXT: br label [[OMP_IF_END]] 2978 // CHECK3: omp_if.end: 2979 // CHECK3-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP1]] 2980 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP51]] 2981 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 2982 // CHECK3-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 2983 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP52]] to i32 2984 // CHECK3-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4 2985 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP53]] 2986 // CHECK3-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2987 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP54]]) 2988 // CHECK3-NEXT: ret i32 [[ADD3]] 2989 // 2990 // 2991 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 2992 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2993 // CHECK3-NEXT: entry: 2994 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2995 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2996 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2997 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 2998 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2999 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3000 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3001 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3002 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 3003 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 3004 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 3005 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3006 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3007 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3008 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 3009 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3010 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3011 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3012 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3013 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3014 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3015 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3016 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 3017 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3018 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 3019 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3020 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3021 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3022 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3023 // CHECK3: omp_if.then: 3024 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3025 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3026 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3027 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3028 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3029 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3030 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3031 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 3032 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3033 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3034 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3035 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3036 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 3037 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 3038 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3039 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 3040 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3041 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 3042 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 3043 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3044 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 3045 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 3046 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3047 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 3048 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3049 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 3050 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 3051 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3052 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 3053 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 3054 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3055 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 3056 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3057 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3058 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3059 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 3060 // CHECK3-NEXT: store i32 1, i32* [[TMP29]], align 4 3061 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 3062 // CHECK3-NEXT: store i32 4, i32* [[TMP30]], align 4 3063 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 3064 // CHECK3-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4 3065 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 3066 // CHECK3-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 4 3067 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 3068 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.27, i32 0, i32 0), i64** [[TMP33]], align 4 3069 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 3070 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.28, i32 0, i32 0), i64** [[TMP34]], align 4 3071 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 3072 // CHECK3-NEXT: store i8** null, i8*** [[TMP35]], align 4 3073 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 3074 // CHECK3-NEXT: store i8** null, i8*** [[TMP36]], align 4 3075 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 3076 // CHECK3-NEXT: store i64 0, i64* [[TMP37]], align 8 3077 // CHECK3-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 3078 // CHECK3-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 3079 // CHECK3-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3080 // CHECK3: omp_offload.failed: 3081 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 3082 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3083 // CHECK3: omp_offload.cont: 3084 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3085 // CHECK3: omp_if.else: 3086 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]] 3087 // CHECK3-NEXT: br label [[OMP_IF_END]] 3088 // CHECK3: omp_if.end: 3089 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 3090 // CHECK3-NEXT: ret i32 [[TMP40]] 3091 // 3092 // 3093 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3094 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3095 // CHECK3-NEXT: entry: 3096 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3097 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3098 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3099 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3100 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3101 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3102 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3103 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3104 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3105 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3106 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3107 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3108 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3109 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3110 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3111 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3112 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3113 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3114 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3115 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3116 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3117 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3118 // CHECK3: omp_if.then: 3119 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3120 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 3121 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 3122 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3123 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3124 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3125 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3126 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 3127 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3128 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 3129 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 3130 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3131 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3132 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3133 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3134 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 3135 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3136 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3137 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 3138 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3139 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3140 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 3141 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3142 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3143 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3144 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3145 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3146 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 3147 // CHECK3-NEXT: store i32 1, i32* [[TMP22]], align 4 3148 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 3149 // CHECK3-NEXT: store i32 3, i32* [[TMP23]], align 4 3150 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 3151 // CHECK3-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4 3152 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 3153 // CHECK3-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 4 3154 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 3155 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.30, i32 0, i32 0), i64** [[TMP26]], align 4 3156 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 3157 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.31, i32 0, i32 0), i64** [[TMP27]], align 4 3158 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 3159 // CHECK3-NEXT: store i8** null, i8*** [[TMP28]], align 4 3160 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 3161 // CHECK3-NEXT: store i8** null, i8*** [[TMP29]], align 4 3162 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 3163 // CHECK3-NEXT: store i64 0, i64* [[TMP30]], align 8 3164 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 0, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 3165 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 3166 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3167 // CHECK3: omp_offload.failed: 3168 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 3169 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3170 // CHECK3: omp_offload.cont: 3171 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3172 // CHECK3: omp_if.else: 3173 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]] 3174 // CHECK3-NEXT: br label [[OMP_IF_END]] 3175 // CHECK3: omp_if.end: 3176 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4 3177 // CHECK3-NEXT: ret i32 [[TMP33]] 3178 // 3179 // 3180 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 3181 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3182 // CHECK3-NEXT: entry: 3183 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3184 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3185 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3186 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3187 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3188 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3189 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3190 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3191 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3192 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3193 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3194 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3195 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3196 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3197 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3198 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3199 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3200 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3201 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..23 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3202 // CHECK3-NEXT: ret void 3203 // 3204 // 3205 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..23 3206 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3207 // CHECK3-NEXT: entry: 3208 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3209 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3210 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3211 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3212 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3213 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3214 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3215 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3216 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3217 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3218 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3219 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3220 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3221 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3222 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3223 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3224 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3225 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3226 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3227 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 3228 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3229 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3230 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 3231 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3232 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 3233 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 3234 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 4 3235 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 3236 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 3237 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 3238 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3239 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 3240 // CHECK3-NEXT: ret void 3241 // 3242 // 3243 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 3244 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3245 // CHECK3-NEXT: entry: 3246 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3247 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3248 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3249 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3250 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3251 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3252 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3253 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3254 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3255 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3256 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3257 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3258 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3259 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3260 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3261 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3262 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3263 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3264 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3265 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 3266 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3267 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 3268 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3269 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 3270 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3271 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..26 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 3272 // CHECK3-NEXT: ret void 3273 // 3274 // 3275 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..26 3276 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3277 // CHECK3-NEXT: entry: 3278 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3279 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3280 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3281 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3282 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3283 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3284 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3285 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3286 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3287 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3288 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3289 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3290 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3291 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3292 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3293 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3294 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3295 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3296 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3297 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 3298 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3299 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3300 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 3301 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 3302 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 3303 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 3304 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 3305 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 3306 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3307 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3308 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 3309 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 3310 // CHECK3-NEXT: ret void 3311 // 3312 // 3313 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 3314 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3315 // CHECK3-NEXT: entry: 3316 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3317 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3318 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3319 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3320 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3321 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3322 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3323 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3324 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3325 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3326 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3327 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3328 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3329 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3330 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3331 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3332 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3333 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..29 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3334 // CHECK3-NEXT: ret void 3335 // 3336 // 3337 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..29 3338 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3339 // CHECK3-NEXT: entry: 3340 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3341 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3342 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3343 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3344 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3345 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3346 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3347 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3348 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3349 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3350 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3351 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3352 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3353 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3354 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3355 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3356 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 3357 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3358 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3359 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3360 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3361 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3362 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 3363 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 3364 // CHECK3-NEXT: ret void 3365 // 3366 // 3367 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3368 // CHECK3-SAME: () #[[ATTR4]] { 3369 // CHECK3-NEXT: entry: 3370 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3371 // CHECK3-NEXT: ret void 3372 // 3373 // 3374 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 3375 // CHECK9-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]], i64 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 3376 // CHECK9-NEXT: entry: 3377 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3378 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3379 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 3380 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3381 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 3382 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3383 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3384 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 3385 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3386 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3387 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* 3388 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV3]], align 4 3389 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV4]], align 4 3390 // CHECK9-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 3391 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3392 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3393 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV5]], align 2 3394 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3395 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP4]]) 3396 // CHECK9-NEXT: ret void 3397 // 3398 // 3399 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 3400 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3401 // CHECK9-NEXT: entry: 3402 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3403 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3404 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3405 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3406 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3407 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3408 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3409 // CHECK9-NEXT: ret void 3410 // 3411 // 3412 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 3413 // CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3414 // CHECK9-NEXT: entry: 3415 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3416 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3417 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3418 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3419 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3420 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3421 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3422 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3423 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 3424 // CHECK9-NEXT: ret void 3425 // 3426 // 3427 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 3428 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3429 // CHECK9-NEXT: entry: 3430 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3431 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3432 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3433 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3434 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3435 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3436 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3437 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3438 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3439 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 3440 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 3441 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 3442 // CHECK9-NEXT: ret void 3443 // 3444 // 3445 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 3446 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3447 // CHECK9-NEXT: entry: 3448 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3449 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3450 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3451 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3452 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3453 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3454 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3455 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3456 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3457 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3458 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 3459 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3460 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 3461 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3462 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 3463 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3464 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 3465 // CHECK9-NEXT: ret void 3466 // 3467 // 3468 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 3469 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 3470 // CHECK9-NEXT: entry: 3471 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3472 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3473 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3474 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3475 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3476 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3477 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3478 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3479 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3480 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3481 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3482 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3483 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3484 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 3485 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 3486 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3487 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3488 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 3489 // CHECK9-NEXT: ret void 3490 // 3491 // 3492 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 3493 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 3494 // CHECK9-NEXT: entry: 3495 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3496 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 3497 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3498 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 3499 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 3500 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3501 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3502 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 3503 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 3504 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3505 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3506 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 3507 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3508 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 3509 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 3510 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3511 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 3512 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 3513 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 3514 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3515 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 3516 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3517 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 3518 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 3519 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3520 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 3521 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 3522 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 3523 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 3524 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3525 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 3526 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 3527 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 3528 // CHECK9-NEXT: ret void 3529 // 3530 // 3531 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 3532 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 3533 // CHECK9-NEXT: entry: 3534 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3535 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3536 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3537 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 3538 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3539 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 3540 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 3541 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3542 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 3543 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 3544 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 3545 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3546 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3547 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3548 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 3549 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3550 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 3551 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 3552 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3553 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 3554 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 3555 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 3556 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3557 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 3558 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3559 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 3560 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 3561 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3562 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 3563 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 3564 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 3565 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 3566 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 3567 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3568 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 3569 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 3570 // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 3571 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 3572 // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 3573 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 3574 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 3575 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 3576 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 3577 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 3578 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 3579 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 3580 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 3581 // CHECK9-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 3582 // CHECK9-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 3583 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 3584 // CHECK9-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 3585 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 3586 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 3587 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 3588 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 3589 // CHECK9-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 3590 // CHECK9-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 3591 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 3592 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 3593 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 3594 // CHECK9-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 3595 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 3596 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 3597 // CHECK9-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 3598 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 3599 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 3600 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 3601 // CHECK9-NEXT: ret void 3602 // 3603 // 3604 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 3605 // CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3606 // CHECK9-NEXT: entry: 3607 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3608 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 3609 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3610 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3611 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3612 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 3613 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 3614 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 3615 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 3616 // CHECK9-NEXT: ret void 3617 // 3618 // 3619 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 3620 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3621 // CHECK9-NEXT: entry: 3622 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3623 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3624 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3625 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 3626 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3627 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3628 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3629 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3630 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3631 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 3632 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 3633 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 3634 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 3635 // CHECK9-NEXT: ret void 3636 // 3637 // 3638 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 3639 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3640 // CHECK9-NEXT: entry: 3641 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3642 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3643 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3644 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3645 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3646 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3647 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3648 // CHECK9-NEXT: ret void 3649 // 3650 // 3651 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 3652 // CHECK9-SAME: (i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3653 // CHECK9-NEXT: entry: 3654 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3655 // CHECK9-NEXT: [[NN_CASTED:%.*]] = alloca i64, align 8 3656 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3657 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3658 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3659 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[NN_CASTED]] to i32* 3660 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 3661 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[NN_CASTED]], align 8 3662 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 3663 // CHECK9-NEXT: ret void 3664 // 3665 // 3666 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 3667 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[NN:%.*]]) #[[ATTR0]] { 3668 // CHECK9-NEXT: entry: 3669 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3670 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3671 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i64, align 8 3672 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3673 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3674 // CHECK9-NEXT: store i64 [[NN]], i64* [[NN_ADDR]], align 8 3675 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[NN_ADDR]] to i32* 3676 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[CONV]]) 3677 // CHECK9-NEXT: ret void 3678 // 3679 // 3680 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..7 3681 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 3682 // CHECK9-NEXT: entry: 3683 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3684 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3685 // CHECK9-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 8 3686 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3687 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3688 // CHECK9-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 8 3689 // CHECK9-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 8 3690 // CHECK9-NEXT: ret void 3691 // 3692 // 3693 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 3694 // CHECK9-SAME: (i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 3695 // CHECK9-NEXT: entry: 3696 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3697 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3698 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3699 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i64 [[TMP0]]) 3700 // CHECK9-NEXT: ret void 3701 // 3702 // 3703 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..8 3704 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[VLA:%.*]]) #[[ATTR0]] { 3705 // CHECK9-NEXT: entry: 3706 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3707 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3708 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3709 // CHECK9-NEXT: [[F:%.*]] = alloca i32*, align 8 3710 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3711 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3712 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3713 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3714 // CHECK9-NEXT: ret void 3715 // 3716 // 3717 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 3718 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3719 // CHECK9-NEXT: entry: 3720 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3721 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3722 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 3723 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3724 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3725 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3726 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 3727 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3728 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3729 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 3730 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3731 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3732 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3733 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 3734 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3735 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3736 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3737 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 3738 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3739 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 3740 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3741 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 3742 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3743 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 3744 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 3745 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 3746 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 3747 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 3748 // CHECK9-NEXT: ret void 3749 // 3750 // 3751 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..9 3752 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3753 // CHECK9-NEXT: entry: 3754 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3755 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3756 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3757 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3758 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 3759 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3760 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3761 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3762 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3763 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3764 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 3765 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3766 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3767 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3768 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 3769 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3770 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3771 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3772 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3773 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 3774 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 3775 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 3776 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 3777 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 3778 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 3779 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 3780 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 3781 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 3782 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 3783 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 3784 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3785 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 3786 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 3787 // CHECK9-NEXT: ret void 3788 // 3789 // 3790 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 3791 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 3792 // CHECK9-NEXT: entry: 3793 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3794 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3795 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3796 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3797 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 3798 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3799 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3800 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3801 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3802 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3803 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 3804 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3805 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3806 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3807 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3808 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 3809 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 3810 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3811 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 3812 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 3813 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 3814 // CHECK9-NEXT: ret void 3815 // 3816 // 3817 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..10 3818 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 3819 // CHECK9-NEXT: entry: 3820 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3821 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3822 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3823 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3824 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3825 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 3826 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 3827 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3828 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3829 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3830 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3831 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3832 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 3833 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 3834 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3835 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3836 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3837 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 3838 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 3839 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 3840 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 3841 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 3842 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3843 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 3844 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3845 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 3846 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 3847 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 3848 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 3849 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 3850 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 3851 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 3852 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 3853 // CHECK9-NEXT: ret void 3854 // 3855 // 3856 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 3857 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3858 // CHECK9-NEXT: entry: 3859 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3860 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3861 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3862 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3863 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3864 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3865 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3866 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3867 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3868 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3869 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3870 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3871 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3872 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 3873 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 3874 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 3875 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3876 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 3877 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3878 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 3879 // CHECK9-NEXT: ret void 3880 // 3881 // 3882 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..11 3883 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3884 // CHECK9-NEXT: entry: 3885 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3886 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3887 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3888 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3889 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 3890 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3891 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3892 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3893 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3894 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 3895 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3896 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3897 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 3898 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 3899 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3900 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 3901 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 3902 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 3903 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3904 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3905 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 3906 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 3907 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3908 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 3909 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 3910 // CHECK9-NEXT: ret void 3911 // 3912 // 3913 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 3914 // CHECK11-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]], i32 noundef [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { 3915 // CHECK11-NEXT: entry: 3916 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3917 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 3918 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 3919 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3920 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 3921 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3922 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3923 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 3924 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3925 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3926 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 3927 // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]], i32 [[TMP2]]) 3928 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3929 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3930 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 3931 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3932 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP4]]) 3933 // CHECK11-NEXT: ret void 3934 // 3935 // 3936 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 3937 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3938 // CHECK11-NEXT: entry: 3939 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3940 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3941 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3942 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3943 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3944 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3945 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3946 // CHECK11-NEXT: ret void 3947 // 3948 // 3949 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l111 3950 // CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3951 // CHECK11-NEXT: entry: 3952 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3953 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3954 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3955 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3956 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3957 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3958 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3959 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3960 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3961 // CHECK11-NEXT: ret void 3962 // 3963 // 3964 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 3965 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3966 // CHECK11-NEXT: entry: 3967 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3968 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3969 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3970 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3971 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3972 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3973 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3974 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3975 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3976 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 3977 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 3978 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 3979 // CHECK11-NEXT: ret void 3980 // 3981 // 3982 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l118 3983 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3984 // CHECK11-NEXT: entry: 3985 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3986 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3987 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3988 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3989 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3990 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3991 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3992 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3993 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3994 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3995 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3996 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3997 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3998 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3999 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 4000 // CHECK11-NEXT: ret void 4001 // 4002 // 4003 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 4004 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 4005 // CHECK11-NEXT: entry: 4006 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4007 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4008 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4009 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4010 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4011 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4012 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4013 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4014 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4015 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 4016 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4017 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4018 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 4019 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 4020 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 4021 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 4022 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 4023 // CHECK11-NEXT: ret void 4024 // 4025 // 4026 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l142 4027 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 4028 // CHECK11-NEXT: entry: 4029 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4030 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4031 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4032 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4033 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4034 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4035 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4036 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4037 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4038 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4039 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4040 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4041 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4042 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4043 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4044 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4045 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4046 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4047 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4048 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4049 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4050 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4051 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4052 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4053 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4054 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4055 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4056 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4057 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 4058 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 4059 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 4060 // CHECK11-NEXT: ret void 4061 // 4062 // 4063 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 4064 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 4065 // CHECK11-NEXT: entry: 4066 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4067 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4068 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4069 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 4070 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4071 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 4072 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 4073 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4074 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 4075 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 4076 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 4077 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4078 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4079 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4080 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 4081 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4082 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 4083 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 4084 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4085 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 4086 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 4087 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 4088 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 4089 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4090 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 4091 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 4092 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4093 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 4094 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 4095 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 4096 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 4097 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 4098 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4099 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 4100 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 4101 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 4102 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 4103 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 4104 // CHECK11-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 4105 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 4106 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 4107 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 4108 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 4109 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 4110 // CHECK11-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 4111 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 4112 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 4113 // CHECK11-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 4114 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 4115 // CHECK11-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 4116 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 4117 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 4118 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 4119 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 4120 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 4121 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 4122 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4123 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 4124 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 4125 // CHECK11-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 4126 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4127 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 4128 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 4129 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 4130 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 4131 // CHECK11-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 4132 // CHECK11-NEXT: ret void 4133 // 4134 // 4135 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l154 4136 // CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4137 // CHECK11-NEXT: entry: 4138 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4139 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 4140 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 4141 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 4142 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 4143 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 4144 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 4145 // CHECK11-NEXT: ret void 4146 // 4147 // 4148 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 4149 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4150 // CHECK11-NEXT: entry: 4151 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4152 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4153 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4154 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 4155 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4156 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4157 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 4158 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 4159 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 4160 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 4161 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 4162 // CHECK11-NEXT: ret void 4163 // 4164 // 4165 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 4166 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4167 // CHECK11-NEXT: entry: 4168 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4169 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4170 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4171 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4172 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4173 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 4174 // CHECK11-NEXT: ret void 4175 // 4176 // 4177 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l157 4178 // CHECK11-SAME: (i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4179 // CHECK11-NEXT: entry: 4180 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4181 // CHECK11-NEXT: [[NN_CASTED:%.*]] = alloca i32, align 4 4182 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 4183 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[NN_ADDR]], align 4 4184 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[NN_CASTED]], align 4 4185 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[NN_CASTED]], align 4 4186 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 4187 // CHECK11-NEXT: ret void 4188 // 4189 // 4190 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 4191 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[NN:%.*]]) #[[ATTR0]] { 4192 // CHECK11-NEXT: entry: 4193 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4194 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4195 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32, align 4 4196 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4197 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4198 // CHECK11-NEXT: store i32 [[NN]], i32* [[NN_ADDR]], align 4 4199 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32* [[NN_ADDR]]) 4200 // CHECK11-NEXT: ret void 4201 // 4202 // 4203 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..7 4204 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32* noundef nonnull align 4 dereferenceable(4) [[NN:%.*]]) #[[ATTR0]] { 4205 // CHECK11-NEXT: entry: 4206 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4207 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4208 // CHECK11-NEXT: [[NN_ADDR:%.*]] = alloca i32*, align 4 4209 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4210 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4211 // CHECK11-NEXT: store i32* [[NN]], i32** [[NN_ADDR]], align 4 4212 // CHECK11-NEXT: [[TMP0:%.*]] = load i32*, i32** [[NN_ADDR]], align 4 4213 // CHECK11-NEXT: ret void 4214 // 4215 // 4216 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z6bazzzziPi_l182 4217 // CHECK11-SAME: (i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 4218 // CHECK11-NEXT: entry: 4219 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4220 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4221 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4222 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..8 to void (i32*, i32*, ...)*), i32 [[TMP0]]) 4223 // CHECK11-NEXT: ret void 4224 // 4225 // 4226 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..8 4227 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[VLA:%.*]]) #[[ATTR0]] { 4228 // CHECK11-NEXT: entry: 4229 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4230 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4231 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4232 // CHECK11-NEXT: [[F:%.*]] = alloca i32*, align 4 4233 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4234 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4235 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4236 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4237 // CHECK11-NEXT: ret void 4238 // 4239 // 4240 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l209 4241 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4242 // CHECK11-NEXT: entry: 4243 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4244 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4245 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4246 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4247 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4248 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4249 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4250 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4251 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4252 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4253 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4254 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4255 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4256 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4257 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4258 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4259 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4260 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4261 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4262 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 4263 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4264 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 4265 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4266 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 4267 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4268 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 4269 // CHECK11-NEXT: ret void 4270 // 4271 // 4272 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..9 4273 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4274 // CHECK11-NEXT: entry: 4275 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4276 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4277 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4278 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4279 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4280 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4281 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4282 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4283 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4284 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4285 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4286 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4287 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4288 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4289 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4290 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4291 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4292 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4293 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4294 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 4295 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4296 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4297 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 4298 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 4299 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 4300 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 4301 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 4302 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 4303 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4304 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4305 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 4306 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 4307 // CHECK11-NEXT: ret void 4308 // 4309 // 4310 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l227 4311 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4312 // CHECK11-NEXT: entry: 4313 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4314 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4315 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4316 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4317 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4318 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4319 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4320 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4321 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4322 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4323 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4324 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4325 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4326 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4327 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4328 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4329 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4330 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4331 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 4332 // CHECK11-NEXT: ret void 4333 // 4334 // 4335 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..10 4336 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4337 // CHECK11-NEXT: entry: 4338 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4339 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4340 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4341 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4342 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4343 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4344 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4345 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4346 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4347 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4348 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4349 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4350 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4351 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4352 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4353 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4354 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4355 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4356 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4357 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 4358 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4359 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4360 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 4361 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4362 // CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 4363 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 4364 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 4365 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 4366 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 4367 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 4368 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4369 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 4370 // CHECK11-NEXT: ret void 4371 // 4372 // 4373 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l192 4374 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4375 // CHECK11-NEXT: entry: 4376 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4377 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4378 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4379 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4380 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4381 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4382 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4383 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4384 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4385 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4386 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4387 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4388 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4389 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4390 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4391 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 4392 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4393 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 4394 // CHECK11-NEXT: ret void 4395 // 4396 // 4397 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..11 4398 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4399 // CHECK11-NEXT: entry: 4400 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4401 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4402 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4403 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4404 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4405 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4406 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4407 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4408 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4409 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4410 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4411 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4412 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4413 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4414 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4415 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4416 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 4417 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 4418 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 4419 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 4420 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4421 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4422 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 4423 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 4424 // CHECK11-NEXT: ret void 4425 // 4426