1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6 13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7 14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 26 27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13 29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15 33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 40 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 43 44 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21 45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22 47 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23 48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 60 61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29 63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30 65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31 67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 6 target regions 78 79 80 81 // Check target registration is registered as a Ctor. 82 83 84 template<typename tx> 85 tx ftemplate(int n) { 86 tx a = 0; 87 88 #pragma omp target parallel num_threads(tx(20)) 89 { 90 } 91 92 short b = 1; 93 #pragma omp target parallel num_threads(b) 94 { 95 a += b; 96 } 97 98 return a; 99 } 100 101 static 102 int fstatic(int n) { 103 104 #pragma omp target parallel num_threads(n) 105 { 106 } 107 108 #pragma omp target parallel num_threads(32+n) 109 { 110 } 111 112 return n+1; 113 } 114 115 struct S1 { 116 double a; 117 118 int r1(int n){ 119 int b = 1; 120 121 #pragma omp target parallel num_threads(n-b) 122 { 123 this->a = (double)b + 1.5; 124 } 125 126 #pragma omp target parallel num_threads(1024) 127 { 128 this->a = 2.5; 129 } 130 131 return (int)a; 132 } 133 }; 134 135 int bar(int n){ 136 int a = 0; 137 138 S1 S; 139 a += S.r1(n); 140 141 a += fstatic(n); 142 143 a += ftemplate<int>(n); 144 145 return a; 146 } 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 // Check that the offloading functions are emitted and that the parallel function 169 // is appropriately guarded. 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 #endif 192 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 193 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 194 // CHECK1-NEXT: entry: 195 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 196 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 197 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 198 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 199 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 200 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 201 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 202 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 203 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 204 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 205 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 206 // CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 207 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 208 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 209 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 210 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 211 // CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 212 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 213 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 214 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 215 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 216 // CHECK1-NEXT: ret i32 [[TMP6]] 217 // 218 // 219 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 220 // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 221 // CHECK1-NEXT: entry: 222 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 223 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 224 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 225 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 226 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 227 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 228 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 229 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 230 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 231 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 232 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 233 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 234 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 235 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 236 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 237 // CHECK1-NEXT: store i32 1, i32* [[B]], align 4 238 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 239 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 240 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 241 // CHECK1-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 242 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 243 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 244 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 245 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 246 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 247 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 248 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 249 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 250 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 251 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 252 // CHECK1-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 253 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 254 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 255 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 256 // CHECK1-NEXT: store double* [[A]], double** [[TMP9]], align 8 257 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 258 // CHECK1-NEXT: store i8* null, i8** [[TMP10]], align 8 259 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 260 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 261 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 262 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 263 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 264 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 265 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 266 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 267 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 268 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 269 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 270 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 271 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 272 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 273 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 274 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 275 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 276 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 277 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 278 // CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 279 // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 280 // CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 281 // CHECK1: omp_offload.failed: 282 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] 283 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 284 // CHECK1: omp_offload.cont: 285 // CHECK1-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 286 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 287 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 288 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 289 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 290 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 291 // CHECK1-NEXT: store double* [[A3]], double** [[TMP29]], align 8 292 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 293 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 294 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 295 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 296 // CHECK1-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) 297 // CHECK1-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 298 // CHECK1-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 299 // CHECK1: omp_offload.failed7: 300 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 301 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]] 302 // CHECK1: omp_offload.cont8: 303 // CHECK1-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 304 // CHECK1-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 305 // CHECK1-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 306 // CHECK1-NEXT: ret i32 [[CONV10]] 307 // 308 // 309 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 310 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 311 // CHECK1-NEXT: entry: 312 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 313 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 314 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 315 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 316 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 317 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 318 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 321 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 323 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 324 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 325 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 326 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 327 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 328 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 329 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 330 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 331 // CHECK1-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 332 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 333 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 334 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 335 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 336 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 337 // CHECK1-NEXT: store i8* null, i8** [[TMP7]], align 8 338 // CHECK1-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 339 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 340 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 341 // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) 342 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 343 // CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 344 // CHECK1: omp_offload.failed: 345 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] 346 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 347 // CHECK1: omp_offload.cont: 348 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 349 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 350 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 351 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 352 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* 353 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 354 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 355 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 356 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 357 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 358 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 359 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 360 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 361 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 362 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 363 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 364 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 365 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 366 // CHECK1-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 367 // CHECK1-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 368 // CHECK1-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 369 // CHECK1: omp_offload.failed7: 370 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] 371 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT8]] 372 // CHECK1: omp_offload.cont8: 373 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 374 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 375 // CHECK1-NEXT: ret i32 [[ADD9]] 376 // 377 // 378 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 379 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 380 // CHECK1-NEXT: entry: 381 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 382 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 383 // CHECK1-NEXT: [[B:%.*]] = alloca i16, align 2 384 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 385 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 386 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 387 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 388 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 389 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 390 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 391 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 392 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 393 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) 394 // CHECK1-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 395 // CHECK1-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 396 // CHECK1: omp_offload.failed: 397 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 398 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 399 // CHECK1: omp_offload.cont: 400 // CHECK1-NEXT: store i16 1, i16* [[B]], align 2 401 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 402 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 403 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 404 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 405 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 406 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 407 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 408 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* 409 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 410 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 411 // CHECK1-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 412 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* 413 // CHECK1-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 414 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 415 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 416 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 417 // CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 418 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 419 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 420 // CHECK1-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 421 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 422 // CHECK1-NEXT: store i8* null, i8** [[TMP13]], align 8 423 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 424 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 425 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 426 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 427 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 428 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 429 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 430 // CHECK1-NEXT: store i8* null, i8** [[TMP18]], align 8 431 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 432 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 433 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 434 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 435 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 436 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 437 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 438 // CHECK1-NEXT: store i8* null, i8** [[TMP23]], align 8 439 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 440 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 441 // CHECK1-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 442 // CHECK1-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 443 // CHECK1-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) 444 // CHECK1-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 445 // CHECK1-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 446 // CHECK1: omp_offload.failed3: 447 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] 448 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT4]] 449 // CHECK1: omp_offload.cont4: 450 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 451 // CHECK1-NEXT: ret i32 [[TMP30]] 452 // 453 // 454 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 455 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 456 // CHECK1-NEXT: entry: 457 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 458 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 459 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 460 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 461 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 462 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 463 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 464 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 465 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 466 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 467 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 468 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 469 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 470 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 471 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 472 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 473 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 474 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 475 // CHECK1-NEXT: ret void 476 // 477 // 478 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 479 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 480 // CHECK1-NEXT: entry: 481 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 482 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 483 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 484 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 485 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 486 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 487 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 488 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 489 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 490 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 491 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 492 // CHECK1-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 493 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 494 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 495 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 496 // CHECK1-NEXT: ret void 497 // 498 // 499 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 500 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 501 // CHECK1-NEXT: entry: 502 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 503 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 504 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 505 // CHECK1-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 506 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 507 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 508 // CHECK1-NEXT: ret void 509 // 510 // 511 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 512 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 513 // CHECK1-NEXT: entry: 514 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 515 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 516 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 517 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 518 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 519 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 520 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 521 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 522 // CHECK1-NEXT: store double 2.500000e+00, double* [[A]], align 8 523 // CHECK1-NEXT: ret void 524 // 525 // 526 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 527 // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 528 // CHECK1-NEXT: entry: 529 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 530 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 531 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 532 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 533 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 534 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 535 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 536 // CHECK1-NEXT: ret void 537 // 538 // 539 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 540 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 541 // CHECK1-NEXT: entry: 542 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 543 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 544 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 545 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 546 // CHECK1-NEXT: ret void 547 // 548 // 549 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 550 // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 551 // CHECK1-NEXT: entry: 552 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 553 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 554 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 555 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 556 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 557 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 558 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 559 // CHECK1-NEXT: ret void 560 // 561 // 562 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 563 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 564 // CHECK1-NEXT: entry: 565 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 566 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 567 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 568 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 569 // CHECK1-NEXT: ret void 570 // 571 // 572 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 573 // CHECK1-SAME: () #[[ATTR1]] { 574 // CHECK1-NEXT: entry: 575 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 576 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 577 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 578 // CHECK1-NEXT: ret void 579 // 580 // 581 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 582 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 583 // CHECK1-NEXT: entry: 584 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 585 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 586 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 587 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 588 // CHECK1-NEXT: ret void 589 // 590 // 591 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 592 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 593 // CHECK1-NEXT: entry: 594 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 595 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 596 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 597 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 598 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 599 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 600 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 601 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 602 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 603 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 604 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 605 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 606 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 607 // CHECK1-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 608 // CHECK1-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 609 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 610 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 611 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 612 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 613 // CHECK1-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 614 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 615 // CHECK1-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 616 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 617 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 618 // CHECK1-NEXT: ret void 619 // 620 // 621 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 622 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 623 // CHECK1-NEXT: entry: 624 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 625 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 626 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 627 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 628 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 629 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 630 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 631 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 632 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 633 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 634 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 635 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 636 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 637 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 638 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 639 // CHECK1-NEXT: ret void 640 // 641 // 642 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 643 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 644 // CHECK1-NEXT: entry: 645 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 646 // CHECK1-NEXT: ret void 647 // 648 // 649 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari 650 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 651 // CHECK2-NEXT: entry: 652 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 653 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 654 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 655 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 656 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 657 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 658 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 659 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 660 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 661 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 662 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 663 // CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 664 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 665 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 666 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 667 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 668 // CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 669 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 670 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 671 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 672 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 673 // CHECK2-NEXT: ret i32 [[TMP6]] 674 // 675 // 676 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 677 // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 678 // CHECK2-NEXT: entry: 679 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 680 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 681 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 682 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 683 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 684 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 685 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 686 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 687 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 688 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 689 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 690 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 691 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 692 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 693 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 694 // CHECK2-NEXT: store i32 1, i32* [[B]], align 4 695 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 696 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 697 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 698 // CHECK2-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 699 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 700 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 701 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 702 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 703 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 704 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 705 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 706 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 707 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 708 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 709 // CHECK2-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 710 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 711 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 712 // CHECK2-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 713 // CHECK2-NEXT: store double* [[A]], double** [[TMP9]], align 8 714 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 715 // CHECK2-NEXT: store i8* null, i8** [[TMP10]], align 8 716 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 717 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 718 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 719 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 720 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 721 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 722 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 723 // CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8 724 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 725 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 726 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 727 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 728 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 729 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 730 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 731 // CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8 732 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 733 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 734 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 735 // CHECK2-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 736 // CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 737 // CHECK2-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 738 // CHECK2: omp_offload.failed: 739 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] 740 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 741 // CHECK2: omp_offload.cont: 742 // CHECK2-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 743 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 744 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 745 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 746 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 747 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 748 // CHECK2-NEXT: store double* [[A3]], double** [[TMP29]], align 8 749 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 750 // CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8 751 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 752 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 753 // CHECK2-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) 754 // CHECK2-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 755 // CHECK2-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 756 // CHECK2: omp_offload.failed7: 757 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 758 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT8]] 759 // CHECK2: omp_offload.cont8: 760 // CHECK2-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 761 // CHECK2-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 762 // CHECK2-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 763 // CHECK2-NEXT: ret i32 [[CONV10]] 764 // 765 // 766 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici 767 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 768 // CHECK2-NEXT: entry: 769 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 770 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 771 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 772 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 773 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 774 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 775 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 776 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 777 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 778 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 779 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 780 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 781 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 782 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 783 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 784 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 785 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 786 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 787 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 788 // CHECK2-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 789 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 790 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 791 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 792 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 793 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 794 // CHECK2-NEXT: store i8* null, i8** [[TMP7]], align 8 795 // CHECK2-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 796 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 797 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 798 // CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) 799 // CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 800 // CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 801 // CHECK2: omp_offload.failed: 802 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] 803 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 804 // CHECK2: omp_offload.cont: 805 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 806 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 807 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 808 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 809 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* 810 // CHECK2-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 811 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 812 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 813 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 814 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 815 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 816 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 817 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 818 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 819 // CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8 820 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 821 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 822 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 823 // CHECK2-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 824 // CHECK2-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 825 // CHECK2-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 826 // CHECK2: omp_offload.failed7: 827 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] 828 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT8]] 829 // CHECK2: omp_offload.cont8: 830 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 831 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 832 // CHECK2-NEXT: ret i32 [[ADD9]] 833 // 834 // 835 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 836 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 837 // CHECK2-NEXT: entry: 838 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 839 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 840 // CHECK2-NEXT: [[B:%.*]] = alloca i16, align 2 841 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 842 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 843 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 844 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 845 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 846 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 847 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 848 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 849 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 850 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) 851 // CHECK2-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 852 // CHECK2-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 853 // CHECK2: omp_offload.failed: 854 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 855 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 856 // CHECK2: omp_offload.cont: 857 // CHECK2-NEXT: store i16 1, i16* [[B]], align 2 858 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 859 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 860 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 861 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 862 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 863 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 864 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 865 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* 866 // CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 867 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 868 // CHECK2-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 869 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* 870 // CHECK2-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 871 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 872 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 873 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 874 // CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 875 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 876 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 877 // CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 878 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 879 // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 880 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 881 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 882 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 883 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 884 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 885 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 886 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 887 // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 888 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 889 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 890 // CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 891 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 892 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 893 // CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 894 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 895 // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 896 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 897 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 898 // CHECK2-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 899 // CHECK2-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 900 // CHECK2-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) 901 // CHECK2-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 902 // CHECK2-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 903 // CHECK2: omp_offload.failed3: 904 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] 905 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT4]] 906 // CHECK2: omp_offload.cont4: 907 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 908 // CHECK2-NEXT: ret i32 [[TMP30]] 909 // 910 // 911 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 912 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 913 // CHECK2-NEXT: entry: 914 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 915 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 916 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 917 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 918 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 919 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 920 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 921 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 922 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 923 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 924 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 925 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 926 // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 927 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 928 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 929 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 930 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 931 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 932 // CHECK2-NEXT: ret void 933 // 934 // 935 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 936 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 937 // CHECK2-NEXT: entry: 938 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 939 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 940 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 941 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 942 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 943 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 944 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 945 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 946 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 947 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 948 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 949 // CHECK2-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 950 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 951 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 952 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 953 // CHECK2-NEXT: ret void 954 // 955 // 956 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 957 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 958 // CHECK2-NEXT: entry: 959 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 960 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 961 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 962 // CHECK2-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 963 // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 964 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 965 // CHECK2-NEXT: ret void 966 // 967 // 968 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 969 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 970 // CHECK2-NEXT: entry: 971 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 972 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 973 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 974 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 975 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 976 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 977 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 978 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 979 // CHECK2-NEXT: store double 2.500000e+00, double* [[A]], align 8 980 // CHECK2-NEXT: ret void 981 // 982 // 983 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 984 // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 985 // CHECK2-NEXT: entry: 986 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 987 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 988 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 989 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 990 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 991 // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 992 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 993 // CHECK2-NEXT: ret void 994 // 995 // 996 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 997 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 998 // CHECK2-NEXT: entry: 999 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1000 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1001 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1002 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1003 // CHECK2-NEXT: ret void 1004 // 1005 // 1006 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 1007 // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1008 // CHECK2-NEXT: entry: 1009 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1010 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1011 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1012 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1013 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1014 // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 1015 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 1016 // CHECK2-NEXT: ret void 1017 // 1018 // 1019 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 1020 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1021 // CHECK2-NEXT: entry: 1022 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1023 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1024 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1025 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1026 // CHECK2-NEXT: ret void 1027 // 1028 // 1029 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 1030 // CHECK2-SAME: () #[[ATTR1]] { 1031 // CHECK2-NEXT: entry: 1032 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1033 // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 1034 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 1035 // CHECK2-NEXT: ret void 1036 // 1037 // 1038 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 1039 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1040 // CHECK2-NEXT: entry: 1041 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1042 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1043 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1044 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1045 // CHECK2-NEXT: ret void 1046 // 1047 // 1048 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 1049 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1050 // CHECK2-NEXT: entry: 1051 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1052 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1053 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1054 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1055 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1056 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1057 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1058 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1059 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1060 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1061 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 1062 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 1063 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 1064 // CHECK2-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 1065 // CHECK2-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 1066 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 1067 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1068 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 1069 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 1070 // CHECK2-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 1071 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 1072 // CHECK2-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 1073 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1074 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 1075 // CHECK2-NEXT: ret void 1076 // 1077 // 1078 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 1079 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 1080 // CHECK2-NEXT: entry: 1081 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1082 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1083 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1084 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1085 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1086 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1087 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1088 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1089 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1090 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 1091 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 1092 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 1093 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 1094 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 1095 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 1096 // CHECK2-NEXT: ret void 1097 // 1098 // 1099 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1100 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 1101 // CHECK2-NEXT: entry: 1102 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 1103 // CHECK2-NEXT: ret void 1104 // 1105 // 1106 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 1107 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1108 // CHECK3-NEXT: entry: 1109 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1110 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1111 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 1112 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1113 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1114 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1115 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 1116 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1117 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1118 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1119 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1120 // CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 1121 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1122 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1123 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1124 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1125 // CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 1126 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1127 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1128 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1129 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 1130 // CHECK3-NEXT: ret i32 [[TMP6]] 1131 // 1132 // 1133 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1134 // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1135 // CHECK3-NEXT: entry: 1136 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1137 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1138 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 1139 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1140 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1141 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1142 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1143 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1144 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1145 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 1146 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 1147 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 1148 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1149 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1150 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1151 // CHECK3-NEXT: store i32 1, i32* [[B]], align 4 1152 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1153 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 1154 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 1155 // CHECK3-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 1156 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 1157 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 1158 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 1159 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1160 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1161 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1162 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1163 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1164 // CHECK3-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 1165 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 1166 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1167 // CHECK3-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 1168 // CHECK3-NEXT: store double* [[A]], double** [[TMP9]], align 4 1169 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1170 // CHECK3-NEXT: store i8* null, i8** [[TMP10]], align 4 1171 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1172 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1173 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 1174 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1175 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1176 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 1177 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1178 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 1179 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1180 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1181 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 1182 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1183 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1184 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 1185 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1186 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 1187 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1188 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1189 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1190 // CHECK3-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 1191 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1192 // CHECK3-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1193 // CHECK3: omp_offload.failed: 1194 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] 1195 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1196 // CHECK3: omp_offload.cont: 1197 // CHECK3-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 1198 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1199 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 1200 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 1201 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1202 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 1203 // CHECK3-NEXT: store double* [[A2]], double** [[TMP29]], align 4 1204 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 1205 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 1206 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1207 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1208 // CHECK3-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) 1209 // CHECK3-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1210 // CHECK3-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1211 // CHECK3: omp_offload.failed6: 1212 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 1213 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1214 // CHECK3: omp_offload.cont7: 1215 // CHECK3-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 1216 // CHECK3-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 1217 // CHECK3-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 1218 // CHECK3-NEXT: ret i32 [[CONV]] 1219 // 1220 // 1221 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 1222 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 1223 // CHECK3-NEXT: entry: 1224 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1225 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1226 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1227 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1228 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1229 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1230 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1231 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 1232 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 1233 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 1234 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 1235 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1236 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1237 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 1238 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1239 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1240 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1241 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1242 // CHECK3-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 1243 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 1244 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1245 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 1246 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 1247 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1248 // CHECK3-NEXT: store i8* null, i8** [[TMP7]], align 4 1249 // CHECK3-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1250 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1251 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1252 // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) 1253 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1254 // CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1255 // CHECK3: omp_offload.failed: 1256 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] 1257 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1258 // CHECK3: omp_offload.cont: 1259 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 1260 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 1261 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1262 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1263 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 1264 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 1265 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1266 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1267 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 1268 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1269 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1270 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 1271 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 1272 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 1273 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1274 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1275 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1276 // CHECK3-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 1277 // CHECK3-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1278 // CHECK3-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1279 // CHECK3: omp_offload.failed6: 1280 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] 1281 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1282 // CHECK3: omp_offload.cont7: 1283 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 1284 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 1285 // CHECK3-NEXT: ret i32 [[ADD8]] 1286 // 1287 // 1288 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1289 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 1290 // CHECK3-NEXT: entry: 1291 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1292 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1293 // CHECK3-NEXT: [[B:%.*]] = alloca i16, align 2 1294 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 1295 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1296 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1297 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1298 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1299 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1300 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1301 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1302 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1303 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) 1304 // CHECK3-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 1305 // CHECK3-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1306 // CHECK3: omp_offload.failed: 1307 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 1308 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1309 // CHECK3: omp_offload.cont: 1310 // CHECK3-NEXT: store i16 1, i16* [[B]], align 2 1311 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 1312 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 1313 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1314 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1315 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1316 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 1317 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1318 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 1319 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1320 // CHECK3-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 1321 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* 1322 // CHECK3-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 1323 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1324 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1325 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1326 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 1327 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1328 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1329 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 1330 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1331 // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 4 1332 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1333 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1334 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 1335 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1336 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1337 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 1338 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1339 // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 4 1340 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1341 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1342 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 1343 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1344 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 1345 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 1346 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1347 // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 4 1348 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1349 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1350 // CHECK3-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 1351 // CHECK3-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 1352 // CHECK3-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) 1353 // CHECK3-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 1354 // CHECK3-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] 1355 // CHECK3: omp_offload.failed2: 1356 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] 1357 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT3]] 1358 // CHECK3: omp_offload.cont3: 1359 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 1360 // CHECK3-NEXT: ret i32 [[TMP30]] 1361 // 1362 // 1363 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 1364 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 1365 // CHECK3-NEXT: entry: 1366 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1367 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1368 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1369 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1370 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1371 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1372 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1373 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1374 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1375 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1376 // CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 1377 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 1378 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 1379 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 1380 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 1381 // CHECK3-NEXT: ret void 1382 // 1383 // 1384 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1385 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 1386 // CHECK3-NEXT: entry: 1387 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1388 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1389 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1390 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1391 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1392 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1393 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1394 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1395 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1396 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 1397 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 1398 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1399 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1400 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 1401 // CHECK3-NEXT: ret void 1402 // 1403 // 1404 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 1405 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 1406 // CHECK3-NEXT: entry: 1407 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1408 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1409 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1410 // CHECK3-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1411 // CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 1412 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 1413 // CHECK3-NEXT: ret void 1414 // 1415 // 1416 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 1417 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 1418 // CHECK3-NEXT: entry: 1419 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1420 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1421 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1422 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1423 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1424 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1425 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1426 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1427 // CHECK3-NEXT: store double 2.500000e+00, double* [[A]], align 4 1428 // CHECK3-NEXT: ret void 1429 // 1430 // 1431 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 1432 // CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1433 // CHECK3-NEXT: entry: 1434 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1435 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1436 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1437 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1438 // CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 1439 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 1440 // CHECK3-NEXT: ret void 1441 // 1442 // 1443 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1444 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1445 // CHECK3-NEXT: entry: 1446 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1447 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1448 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1449 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1450 // CHECK3-NEXT: ret void 1451 // 1452 // 1453 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 1454 // CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1455 // CHECK3-NEXT: entry: 1456 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1457 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1458 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1459 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1460 // CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 1461 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 1462 // CHECK3-NEXT: ret void 1463 // 1464 // 1465 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 1466 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1467 // CHECK3-NEXT: entry: 1468 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1469 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1470 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1471 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1472 // CHECK3-NEXT: ret void 1473 // 1474 // 1475 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 1476 // CHECK3-SAME: () #[[ATTR1]] { 1477 // CHECK3-NEXT: entry: 1478 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1479 // CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 1480 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 1481 // CHECK3-NEXT: ret void 1482 // 1483 // 1484 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 1485 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1486 // CHECK3-NEXT: entry: 1487 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1488 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1489 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1490 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1491 // CHECK3-NEXT: ret void 1492 // 1493 // 1494 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 1495 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1496 // CHECK3-NEXT: entry: 1497 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1498 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1499 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1500 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1501 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1502 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1503 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1504 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1505 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1506 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1507 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 1508 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 1509 // CHECK3-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 1510 // CHECK3-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 1511 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 1512 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1513 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1514 // CHECK3-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 1515 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1516 // CHECK3-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 1517 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1518 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 1519 // CHECK3-NEXT: ret void 1520 // 1521 // 1522 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 1523 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 1524 // CHECK3-NEXT: entry: 1525 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1526 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1527 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1528 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1529 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1530 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1531 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1532 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1533 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1534 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 1535 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 1536 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 1537 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 1538 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1539 // CHECK3-NEXT: ret void 1540 // 1541 // 1542 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1543 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 1544 // CHECK3-NEXT: entry: 1545 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 1546 // CHECK3-NEXT: ret void 1547 // 1548 // 1549 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari 1550 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1551 // CHECK4-NEXT: entry: 1552 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1553 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 1554 // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 1555 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1556 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 1557 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1558 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 1559 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1560 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1561 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1562 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1563 // CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 1564 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1565 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1566 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1567 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1568 // CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 1569 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1570 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1571 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1572 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 1573 // CHECK4-NEXT: ret i32 [[TMP6]] 1574 // 1575 // 1576 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1577 // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1578 // CHECK4-NEXT: entry: 1579 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1580 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1581 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 1582 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1583 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1584 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1585 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1586 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1587 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1588 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 1589 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 1590 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 1591 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1592 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1593 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1594 // CHECK4-NEXT: store i32 1, i32* [[B]], align 4 1595 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1596 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 1597 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 1598 // CHECK4-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 1599 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 1600 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 1601 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 1602 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1603 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1604 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1605 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1606 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1607 // CHECK4-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 1608 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 1609 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1610 // CHECK4-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 1611 // CHECK4-NEXT: store double* [[A]], double** [[TMP9]], align 4 1612 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1613 // CHECK4-NEXT: store i8* null, i8** [[TMP10]], align 4 1614 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1615 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1616 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 1617 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1618 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1619 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 1620 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1621 // CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4 1622 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1623 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1624 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 1625 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1626 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1627 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 1628 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1629 // CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4 1630 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1631 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1632 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1633 // CHECK4-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 1634 // CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1635 // CHECK4-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1636 // CHECK4: omp_offload.failed: 1637 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] 1638 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1639 // CHECK4: omp_offload.cont: 1640 // CHECK4-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 1641 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1642 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 1643 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 1644 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1645 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 1646 // CHECK4-NEXT: store double* [[A2]], double** [[TMP29]], align 4 1647 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 1648 // CHECK4-NEXT: store i8* null, i8** [[TMP30]], align 4 1649 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1650 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1651 // CHECK4-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) 1652 // CHECK4-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 1653 // CHECK4-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1654 // CHECK4: omp_offload.failed6: 1655 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 1656 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1657 // CHECK4: omp_offload.cont7: 1658 // CHECK4-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 1659 // CHECK4-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 1660 // CHECK4-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 1661 // CHECK4-NEXT: ret i32 [[CONV]] 1662 // 1663 // 1664 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici 1665 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 1666 // CHECK4-NEXT: entry: 1667 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1668 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1669 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1670 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1671 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1672 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1673 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 1674 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 1675 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 1676 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 1677 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 1678 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1679 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1680 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 1681 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1682 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1683 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1684 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1685 // CHECK4-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 1686 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 1687 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1688 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 1689 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 1690 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1691 // CHECK4-NEXT: store i8* null, i8** [[TMP7]], align 4 1692 // CHECK4-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1693 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1694 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 1695 // CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) 1696 // CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1697 // CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1698 // CHECK4: omp_offload.failed: 1699 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] 1700 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1701 // CHECK4: omp_offload.cont: 1702 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 1703 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 1704 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 1705 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1706 // CHECK4-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 1707 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 1708 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1709 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1710 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 1711 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1712 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1713 // CHECK4-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 1714 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 1715 // CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4 1716 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 1717 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 1718 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 1719 // CHECK4-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 1720 // CHECK4-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 1721 // CHECK4-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 1722 // CHECK4: omp_offload.failed6: 1723 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] 1724 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT7]] 1725 // CHECK4: omp_offload.cont7: 1726 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 1727 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 1728 // CHECK4-NEXT: ret i32 [[ADD8]] 1729 // 1730 // 1731 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1732 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 1733 // CHECK4-NEXT: entry: 1734 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1735 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 1736 // CHECK4-NEXT: [[B:%.*]] = alloca i16, align 2 1737 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 1738 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1739 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1740 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1741 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1742 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1743 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1744 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1745 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 1746 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) 1747 // CHECK4-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 1748 // CHECK4-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1749 // CHECK4: omp_offload.failed: 1750 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 1751 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 1752 // CHECK4: omp_offload.cont: 1753 // CHECK4-NEXT: store i16 1, i16* [[B]], align 2 1754 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 1755 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 1756 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1757 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1758 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1759 // CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 1760 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1761 // CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 1762 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1763 // CHECK4-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 1764 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* 1765 // CHECK4-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 1766 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 1767 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1768 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1769 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 1770 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1771 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 1772 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 1773 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1774 // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 1775 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1776 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1777 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 1778 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1779 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1780 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 1781 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1782 // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 1783 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1784 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1785 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 1786 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1787 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 1788 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 1789 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1790 // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 1791 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1792 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1793 // CHECK4-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 1794 // CHECK4-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 1795 // CHECK4-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) 1796 // CHECK4-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 1797 // CHECK4-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] 1798 // CHECK4: omp_offload.failed2: 1799 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] 1800 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT3]] 1801 // CHECK4: omp_offload.cont3: 1802 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 1803 // CHECK4-NEXT: ret i32 [[TMP30]] 1804 // 1805 // 1806 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 1807 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 1808 // CHECK4-NEXT: entry: 1809 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1810 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1811 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1812 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1813 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1814 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1815 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1816 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1817 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1818 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1819 // CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 1820 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 1821 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 1822 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 1823 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 1824 // CHECK4-NEXT: ret void 1825 // 1826 // 1827 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 1828 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 1829 // CHECK4-NEXT: entry: 1830 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1831 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1832 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1833 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1834 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1835 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1836 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1837 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1838 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1839 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 1840 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 1841 // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 1842 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1843 // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4 1844 // CHECK4-NEXT: ret void 1845 // 1846 // 1847 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 1848 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 1849 // CHECK4-NEXT: entry: 1850 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1851 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1852 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1853 // CHECK4-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1854 // CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 1855 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 1856 // CHECK4-NEXT: ret void 1857 // 1858 // 1859 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 1860 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 1861 // CHECK4-NEXT: entry: 1862 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1863 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1864 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1865 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1866 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1867 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1868 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1869 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1870 // CHECK4-NEXT: store double 2.500000e+00, double* [[A]], align 4 1871 // CHECK4-NEXT: ret void 1872 // 1873 // 1874 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 1875 // CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1876 // CHECK4-NEXT: entry: 1877 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1878 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1879 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1880 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1881 // CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 1882 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 1883 // CHECK4-NEXT: ret void 1884 // 1885 // 1886 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 1887 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1888 // CHECK4-NEXT: entry: 1889 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1890 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1891 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1892 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1893 // CHECK4-NEXT: ret void 1894 // 1895 // 1896 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 1897 // CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1898 // CHECK4-NEXT: entry: 1899 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1900 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1901 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1902 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1903 // CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 1904 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 1905 // CHECK4-NEXT: ret void 1906 // 1907 // 1908 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 1909 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1910 // CHECK4-NEXT: entry: 1911 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1912 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1913 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1914 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1915 // CHECK4-NEXT: ret void 1916 // 1917 // 1918 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 1919 // CHECK4-SAME: () #[[ATTR1]] { 1920 // CHECK4-NEXT: entry: 1921 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1922 // CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 1923 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 1924 // CHECK4-NEXT: ret void 1925 // 1926 // 1927 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 1928 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 1929 // CHECK4-NEXT: entry: 1930 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1931 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1932 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1933 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1934 // CHECK4-NEXT: ret void 1935 // 1936 // 1937 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 1938 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 1939 // CHECK4-NEXT: entry: 1940 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1941 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1942 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 1943 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1944 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1945 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 1946 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1947 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1948 // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 1949 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1950 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 1951 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 1952 // CHECK4-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 1953 // CHECK4-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 1954 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 1955 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 1956 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 1957 // CHECK4-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 1958 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 1959 // CHECK4-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 1960 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 1961 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 1962 // CHECK4-NEXT: ret void 1963 // 1964 // 1965 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 1966 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 1967 // CHECK4-NEXT: entry: 1968 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1969 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1970 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1971 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 1972 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1973 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1974 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1975 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 1976 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 1977 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 1978 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 1979 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 1980 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 1981 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1982 // CHECK4-NEXT: ret void 1983 // 1984 // 1985 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1986 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 1987 // CHECK4-NEXT: entry: 1988 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 1989 // CHECK4-NEXT: ret void 1990 // 1991 // 1992 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari 1993 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1994 // CHECK5-NEXT: entry: 1995 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1996 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 1997 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1998 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1999 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 2000 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2001 // CHECK5-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 2002 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2003 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2004 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2005 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2006 // CHECK5-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 2007 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2008 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2009 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2010 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2011 // CHECK5-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 2012 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2013 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2014 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2015 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2016 // CHECK5-NEXT: ret i32 [[TMP6]] 2017 // 2018 // 2019 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2020 // CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2021 // CHECK5-NEXT: entry: 2022 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2023 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2024 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 2025 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2026 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2027 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2028 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2029 // CHECK5-NEXT: store i32 1, i32* [[B]], align 4 2030 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2031 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 2032 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 2033 // CHECK5-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 2034 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 2035 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 2036 // CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2037 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2038 // CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8 2039 // CHECK5-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2040 // CHECK5-NEXT: store double 2.500000e+00, double* [[A2]], align 8 2041 // CHECK5-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2042 // CHECK5-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 2043 // CHECK5-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 2044 // CHECK5-NEXT: ret i32 [[CONV4]] 2045 // 2046 // 2047 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici 2048 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 2049 // CHECK5-NEXT: entry: 2050 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2051 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2052 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2053 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2054 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2055 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2056 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2057 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 2058 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2059 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2060 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 2061 // CHECK5-NEXT: ret i32 [[ADD2]] 2062 // 2063 // 2064 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2065 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 2066 // CHECK5-NEXT: entry: 2067 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2068 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 2069 // CHECK5-NEXT: [[B:%.*]] = alloca i16, align 2 2070 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 2071 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2072 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 2073 // CHECK5-NEXT: store i16 1, i16* [[B]], align 2 2074 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 2075 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 2076 // CHECK5-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 2077 // CHECK5-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2078 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2079 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 2080 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2081 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2082 // CHECK5-NEXT: ret i32 [[TMP3]] 2083 // 2084 // 2085 // CHECK6-LABEL: define {{[^@]+}}@_Z3bari 2086 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2087 // CHECK6-NEXT: entry: 2088 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2089 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 2090 // CHECK6-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 2091 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2092 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 2093 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2094 // CHECK6-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 2095 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2096 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2097 // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2098 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2099 // CHECK6-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 2100 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2101 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2102 // CHECK6-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2103 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2104 // CHECK6-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 2105 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2106 // CHECK6-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2107 // CHECK6-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2108 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2109 // CHECK6-NEXT: ret i32 [[TMP6]] 2110 // 2111 // 2112 // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2113 // CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2114 // CHECK6-NEXT: entry: 2115 // CHECK6-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2116 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2117 // CHECK6-NEXT: [[B:%.*]] = alloca i32, align 4 2118 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2119 // CHECK6-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2120 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2121 // CHECK6-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2122 // CHECK6-NEXT: store i32 1, i32* [[B]], align 4 2123 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2124 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 2125 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 2126 // CHECK6-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 2127 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 2128 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 2129 // CHECK6-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2130 // CHECK6-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2131 // CHECK6-NEXT: store double [[ADD]], double* [[A]], align 8 2132 // CHECK6-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2133 // CHECK6-NEXT: store double 2.500000e+00, double* [[A2]], align 8 2134 // CHECK6-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2135 // CHECK6-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 2136 // CHECK6-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 2137 // CHECK6-NEXT: ret i32 [[CONV4]] 2138 // 2139 // 2140 // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici 2141 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 2142 // CHECK6-NEXT: entry: 2143 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2144 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2145 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2146 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2147 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2148 // CHECK6-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2149 // CHECK6-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2150 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 2151 // CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2152 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2153 // CHECK6-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 2154 // CHECK6-NEXT: ret i32 [[ADD2]] 2155 // 2156 // 2157 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2158 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 2159 // CHECK6-NEXT: entry: 2160 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2161 // CHECK6-NEXT: [[A:%.*]] = alloca i32, align 4 2162 // CHECK6-NEXT: [[B:%.*]] = alloca i16, align 2 2163 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 2164 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2165 // CHECK6-NEXT: store i32 0, i32* [[A]], align 4 2166 // CHECK6-NEXT: store i16 1, i16* [[B]], align 2 2167 // CHECK6-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 2168 // CHECK6-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 2169 // CHECK6-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 2170 // CHECK6-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2171 // CHECK6-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2172 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 2173 // CHECK6-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2174 // CHECK6-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2175 // CHECK6-NEXT: ret i32 [[TMP3]] 2176 // 2177 // 2178 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari 2179 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2180 // CHECK7-NEXT: entry: 2181 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2182 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 2183 // CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2184 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2185 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 2186 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2187 // CHECK7-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 2188 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2189 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2190 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2191 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2192 // CHECK7-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 2193 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2194 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2195 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2196 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2197 // CHECK7-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 2198 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2199 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2200 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2201 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2202 // CHECK7-NEXT: ret i32 [[TMP6]] 2203 // 2204 // 2205 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2206 // CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2207 // CHECK7-NEXT: entry: 2208 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2209 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2210 // CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 2211 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2212 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2213 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2214 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2215 // CHECK7-NEXT: store i32 1, i32* [[B]], align 4 2216 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2217 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 2218 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 2219 // CHECK7-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 2220 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 2221 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 2222 // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2223 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2224 // CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4 2225 // CHECK7-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2226 // CHECK7-NEXT: store double 2.500000e+00, double* [[A2]], align 4 2227 // CHECK7-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2228 // CHECK7-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 2229 // CHECK7-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 2230 // CHECK7-NEXT: ret i32 [[CONV4]] 2231 // 2232 // 2233 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici 2234 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 2235 // CHECK7-NEXT: entry: 2236 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2237 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2238 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2239 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2240 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2241 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2242 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2243 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 2244 // CHECK7-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2245 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2246 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 2247 // CHECK7-NEXT: ret i32 [[ADD2]] 2248 // 2249 // 2250 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2251 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 2252 // CHECK7-NEXT: entry: 2253 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2254 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 2255 // CHECK7-NEXT: [[B:%.*]] = alloca i16, align 2 2256 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 2257 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2258 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 2259 // CHECK7-NEXT: store i16 1, i16* [[B]], align 2 2260 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 2261 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 2262 // CHECK7-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 2263 // CHECK7-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2264 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2265 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 2266 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2267 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2268 // CHECK7-NEXT: ret i32 [[TMP3]] 2269 // 2270 // 2271 // CHECK8-LABEL: define {{[^@]+}}@_Z3bari 2272 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2273 // CHECK8-NEXT: entry: 2274 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2275 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 2276 // CHECK8-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2277 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2278 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 2279 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2280 // CHECK8-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 2281 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2282 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2283 // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2284 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2285 // CHECK8-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 2286 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2287 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2288 // CHECK8-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2289 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2290 // CHECK8-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 2291 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2292 // CHECK8-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2293 // CHECK8-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2294 // CHECK8-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 2295 // CHECK8-NEXT: ret i32 [[TMP6]] 2296 // 2297 // 2298 // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2299 // CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2300 // CHECK8-NEXT: entry: 2301 // CHECK8-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2302 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2303 // CHECK8-NEXT: [[B:%.*]] = alloca i32, align 4 2304 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2305 // CHECK8-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2306 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2307 // CHECK8-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2308 // CHECK8-NEXT: store i32 1, i32* [[B]], align 4 2309 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2310 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 2311 // CHECK8-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 2312 // CHECK8-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 2313 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 2314 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 2315 // CHECK8-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2316 // CHECK8-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2317 // CHECK8-NEXT: store double [[ADD]], double* [[A]], align 4 2318 // CHECK8-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2319 // CHECK8-NEXT: store double 2.500000e+00, double* [[A2]], align 4 2320 // CHECK8-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 2321 // CHECK8-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 2322 // CHECK8-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 2323 // CHECK8-NEXT: ret i32 [[CONV4]] 2324 // 2325 // 2326 // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici 2327 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 2328 // CHECK8-NEXT: entry: 2329 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2330 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2331 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 2332 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2333 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2334 // CHECK8-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 2335 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2336 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 2337 // CHECK8-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 2338 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2339 // CHECK8-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 2340 // CHECK8-NEXT: ret i32 [[ADD2]] 2341 // 2342 // 2343 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2344 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 2345 // CHECK8-NEXT: entry: 2346 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2347 // CHECK8-NEXT: [[A:%.*]] = alloca i32, align 4 2348 // CHECK8-NEXT: [[B:%.*]] = alloca i16, align 2 2349 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 2350 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2351 // CHECK8-NEXT: store i32 0, i32* [[A]], align 4 2352 // CHECK8-NEXT: store i16 1, i16* [[B]], align 2 2353 // CHECK8-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 2354 // CHECK8-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 2355 // CHECK8-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 2356 // CHECK8-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 2357 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 2358 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 2359 // CHECK8-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2360 // CHECK8-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2361 // CHECK8-NEXT: ret i32 [[TMP3]] 2362 // 2363 // 2364 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 2365 // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 2366 // CHECK9-NEXT: entry: 2367 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2368 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2369 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2370 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2371 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2372 // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 2373 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2374 // CHECK9-NEXT: ret void 2375 // 2376 // 2377 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2378 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2379 // CHECK9-NEXT: entry: 2380 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2381 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2382 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2383 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2384 // CHECK9-NEXT: ret void 2385 // 2386 // 2387 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 2388 // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2389 // CHECK9-NEXT: entry: 2390 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2391 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2392 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2393 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2394 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2395 // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 2396 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 2397 // CHECK9-NEXT: ret void 2398 // 2399 // 2400 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 2401 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2402 // CHECK9-NEXT: entry: 2403 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2404 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2405 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2406 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2407 // CHECK9-NEXT: ret void 2408 // 2409 // 2410 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 2411 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2412 // CHECK9-NEXT: entry: 2413 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2414 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2415 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2416 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2417 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2418 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2419 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2420 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2421 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2422 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2423 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2424 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 2425 // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 2426 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 2427 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2428 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 2429 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 2430 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 2431 // CHECK9-NEXT: ret void 2432 // 2433 // 2434 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 2435 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 2436 // CHECK9-NEXT: entry: 2437 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2438 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2439 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2440 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2441 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2442 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2443 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2444 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2445 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2446 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2447 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2448 // CHECK9-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 2449 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 2450 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2451 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 2452 // CHECK9-NEXT: ret void 2453 // 2454 // 2455 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 2456 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2457 // CHECK9-NEXT: entry: 2458 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2459 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2460 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2461 // CHECK9-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2462 // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 2463 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 2464 // CHECK9-NEXT: ret void 2465 // 2466 // 2467 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 2468 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2469 // CHECK9-NEXT: entry: 2470 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2471 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2472 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2473 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2474 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2475 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2476 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2477 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2478 // CHECK9-NEXT: store double 2.500000e+00, double* [[A]], align 8 2479 // CHECK9-NEXT: ret void 2480 // 2481 // 2482 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 2483 // CHECK9-SAME: () #[[ATTR0]] { 2484 // CHECK9-NEXT: entry: 2485 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2486 // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 2487 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 2488 // CHECK9-NEXT: ret void 2489 // 2490 // 2491 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 2492 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2493 // CHECK9-NEXT: entry: 2494 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2495 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2496 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2497 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2498 // CHECK9-NEXT: ret void 2499 // 2500 // 2501 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 2502 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2503 // CHECK9-NEXT: entry: 2504 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2505 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2506 // CHECK9-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2507 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2508 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2509 // CHECK9-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2510 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2511 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2512 // CHECK9-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2513 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2514 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 2515 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 2516 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 2517 // CHECK9-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 2518 // CHECK9-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 2519 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 2520 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2521 // CHECK9-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 2522 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 2523 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 2524 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 2525 // CHECK9-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 2526 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 2527 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 2528 // CHECK9-NEXT: ret void 2529 // 2530 // 2531 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 2532 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 2533 // CHECK9-NEXT: entry: 2534 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2535 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2536 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2537 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2538 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2539 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2540 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2541 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2542 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2543 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 2544 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 2545 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 2546 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2547 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 2548 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 2549 // CHECK9-NEXT: ret void 2550 // 2551 // 2552 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 2553 // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 2554 // CHECK10-NEXT: entry: 2555 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2556 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2557 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2558 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2559 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2560 // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 2561 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2562 // CHECK10-NEXT: ret void 2563 // 2564 // 2565 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 2566 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2567 // CHECK10-NEXT: entry: 2568 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2569 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2570 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2571 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2572 // CHECK10-NEXT: ret void 2573 // 2574 // 2575 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 2576 // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2577 // CHECK10-NEXT: entry: 2578 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2579 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2580 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2581 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2582 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2583 // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 2584 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 2585 // CHECK10-NEXT: ret void 2586 // 2587 // 2588 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 2589 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2590 // CHECK10-NEXT: entry: 2591 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2592 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2593 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2594 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2595 // CHECK10-NEXT: ret void 2596 // 2597 // 2598 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 2599 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2600 // CHECK10-NEXT: entry: 2601 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2602 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2603 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2604 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2605 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2606 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2607 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2608 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2609 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2610 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2611 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 2612 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 2613 // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 2614 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 2615 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2616 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 2617 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 2618 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 2619 // CHECK10-NEXT: ret void 2620 // 2621 // 2622 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 2623 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 2624 // CHECK10-NEXT: entry: 2625 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2626 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2627 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2628 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2629 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2630 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2631 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2632 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2633 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2634 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2635 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2636 // CHECK10-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 2637 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 2638 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2639 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 2640 // CHECK10-NEXT: ret void 2641 // 2642 // 2643 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 2644 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2645 // CHECK10-NEXT: entry: 2646 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2647 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2648 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2649 // CHECK10-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2650 // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 2651 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 2652 // CHECK10-NEXT: ret void 2653 // 2654 // 2655 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 2656 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2657 // CHECK10-NEXT: entry: 2658 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2659 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2660 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2661 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2662 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2663 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2664 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2665 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2666 // CHECK10-NEXT: store double 2.500000e+00, double* [[A]], align 8 2667 // CHECK10-NEXT: ret void 2668 // 2669 // 2670 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 2671 // CHECK10-SAME: () #[[ATTR0]] { 2672 // CHECK10-NEXT: entry: 2673 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2674 // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 2675 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 2676 // CHECK10-NEXT: ret void 2677 // 2678 // 2679 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 2680 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2681 // CHECK10-NEXT: entry: 2682 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2683 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2684 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2685 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2686 // CHECK10-NEXT: ret void 2687 // 2688 // 2689 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 2690 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2691 // CHECK10-NEXT: entry: 2692 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2693 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2694 // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2695 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2696 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2697 // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2698 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2699 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2700 // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2701 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2702 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 2703 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 2704 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 2705 // CHECK10-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 2706 // CHECK10-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 2707 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 2708 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2709 // CHECK10-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 2710 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 2711 // CHECK10-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 2712 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 2713 // CHECK10-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 2714 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 2715 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 2716 // CHECK10-NEXT: ret void 2717 // 2718 // 2719 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 2720 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 2721 // CHECK10-NEXT: entry: 2722 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2723 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2724 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2725 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2726 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2727 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2728 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2729 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2730 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2731 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 2732 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 2733 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 2734 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 2735 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 2736 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 2737 // CHECK10-NEXT: ret void 2738 // 2739 // 2740 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 2741 // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 2742 // CHECK11-NEXT: entry: 2743 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2744 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2745 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2746 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2747 // CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 2748 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2749 // CHECK11-NEXT: ret void 2750 // 2751 // 2752 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 2753 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2754 // CHECK11-NEXT: entry: 2755 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2756 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2757 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2758 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2759 // CHECK11-NEXT: ret void 2760 // 2761 // 2762 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 2763 // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2764 // CHECK11-NEXT: entry: 2765 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2766 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2767 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2768 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2769 // CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 2770 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 2771 // CHECK11-NEXT: ret void 2772 // 2773 // 2774 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2775 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2776 // CHECK11-NEXT: entry: 2777 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2778 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2779 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2780 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2781 // CHECK11-NEXT: ret void 2782 // 2783 // 2784 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 2785 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2786 // CHECK11-NEXT: entry: 2787 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2788 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2789 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2790 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2791 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2792 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2793 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2794 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2795 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2796 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2797 // CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 2798 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 2799 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 2800 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 2801 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 2802 // CHECK11-NEXT: ret void 2803 // 2804 // 2805 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 2806 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 2807 // CHECK11-NEXT: entry: 2808 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2809 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2810 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2811 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2812 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2813 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2814 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2815 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2816 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2817 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 2818 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 2819 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2820 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2821 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 2822 // CHECK11-NEXT: ret void 2823 // 2824 // 2825 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 2826 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2827 // CHECK11-NEXT: entry: 2828 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2829 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2830 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2831 // CHECK11-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2832 // CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 2833 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 2834 // CHECK11-NEXT: ret void 2835 // 2836 // 2837 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 2838 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 2839 // CHECK11-NEXT: entry: 2840 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2841 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2842 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2843 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2844 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2845 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2846 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2847 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2848 // CHECK11-NEXT: store double 2.500000e+00, double* [[A]], align 4 2849 // CHECK11-NEXT: ret void 2850 // 2851 // 2852 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 2853 // CHECK11-SAME: () #[[ATTR0]] { 2854 // CHECK11-NEXT: entry: 2855 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2856 // CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 2857 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 2858 // CHECK11-NEXT: ret void 2859 // 2860 // 2861 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 2862 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2863 // CHECK11-NEXT: entry: 2864 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2865 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2866 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2867 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2868 // CHECK11-NEXT: ret void 2869 // 2870 // 2871 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 2872 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2873 // CHECK11-NEXT: entry: 2874 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2875 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2876 // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2877 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2878 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2879 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2880 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2881 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2882 // CHECK11-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2883 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 2884 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 2885 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 2886 // CHECK11-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 2887 // CHECK11-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 2888 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 2889 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 2890 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 2891 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 2892 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 2893 // CHECK11-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 2894 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 2895 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 2896 // CHECK11-NEXT: ret void 2897 // 2898 // 2899 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 2900 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 2901 // CHECK11-NEXT: entry: 2902 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2903 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2904 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2905 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2906 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2907 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2908 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2909 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2910 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 2911 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 2912 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2913 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2914 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 2915 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2916 // CHECK11-NEXT: ret void 2917 // 2918 // 2919 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 2920 // CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 2921 // CHECK12-NEXT: entry: 2922 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2923 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2924 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2925 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2926 // CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 2927 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2928 // CHECK12-NEXT: ret void 2929 // 2930 // 2931 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 2932 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2933 // CHECK12-NEXT: entry: 2934 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2935 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2936 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2937 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2938 // CHECK12-NEXT: ret void 2939 // 2940 // 2941 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 2942 // CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2943 // CHECK12-NEXT: entry: 2944 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2945 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2946 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2947 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2948 // CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 2949 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 2950 // CHECK12-NEXT: ret void 2951 // 2952 // 2953 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 2954 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 2955 // CHECK12-NEXT: entry: 2956 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2957 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2958 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2959 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2960 // CHECK12-NEXT: ret void 2961 // 2962 // 2963 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 2964 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 2965 // CHECK12-NEXT: entry: 2966 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2967 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2968 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2969 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2970 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 2971 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2972 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2973 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2974 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2975 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2976 // CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 2977 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 2978 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 2979 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 2980 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 2981 // CHECK12-NEXT: ret void 2982 // 2983 // 2984 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 2985 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 2986 // CHECK12-NEXT: entry: 2987 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2988 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2989 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2990 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2991 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2992 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2993 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2994 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2995 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2996 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 2997 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 2998 // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2999 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3000 // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 3001 // CHECK12-NEXT: ret void 3002 // 3003 // 3004 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 3005 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 3006 // CHECK12-NEXT: entry: 3007 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3008 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3009 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3010 // CHECK12-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3011 // CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 3012 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 3013 // CHECK12-NEXT: ret void 3014 // 3015 // 3016 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 3017 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 3018 // CHECK12-NEXT: entry: 3019 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3020 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3021 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3022 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3023 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3024 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3025 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3026 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3027 // CHECK12-NEXT: store double 2.500000e+00, double* [[A]], align 4 3028 // CHECK12-NEXT: ret void 3029 // 3030 // 3031 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 3032 // CHECK12-SAME: () #[[ATTR0]] { 3033 // CHECK12-NEXT: entry: 3034 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3035 // CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 3036 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 3037 // CHECK12-NEXT: ret void 3038 // 3039 // 3040 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 3041 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 3042 // CHECK12-NEXT: entry: 3043 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3044 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3045 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3046 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3047 // CHECK12-NEXT: ret void 3048 // 3049 // 3050 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 3051 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 3052 // CHECK12-NEXT: entry: 3053 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3054 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3055 // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 3056 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3057 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3058 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3059 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3060 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3061 // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 3062 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 3063 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 3064 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 3065 // CHECK12-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 3066 // CHECK12-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 3067 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 3068 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 3069 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 3070 // CHECK12-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 3071 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 3072 // CHECK12-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 3073 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 3074 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 3075 // CHECK12-NEXT: ret void 3076 // 3077 // 3078 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 3079 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 3080 // CHECK12-NEXT: entry: 3081 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3082 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3083 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3084 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3085 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3086 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3087 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3088 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3089 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 3090 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 3091 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3092 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3093 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 3094 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3095 // CHECK12-NEXT: ret void 3096 // 3097 // 3098 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari 3099 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3100 // CHECK13-NEXT: entry: 3101 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3102 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 3103 // CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 3104 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3105 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 3106 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3107 // CHECK13-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 3108 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3109 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3110 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3111 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3112 // CHECK13-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 3113 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3114 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3115 // CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3116 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3117 // CHECK13-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 3118 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3119 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3120 // CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3121 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3122 // CHECK13-NEXT: ret i32 [[TMP6]] 3123 // 3124 // 3125 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3126 // CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3127 // CHECK13-NEXT: entry: 3128 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3129 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3130 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 3131 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3132 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3133 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3134 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3135 // CHECK13-NEXT: store i32 1, i32* [[B]], align 4 3136 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3137 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3138 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3139 // CHECK13-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3140 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3141 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 3142 // CHECK13-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3143 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3144 // CHECK13-NEXT: store double [[ADD]], double* [[A]], align 8 3145 // CHECK13-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3146 // CHECK13-NEXT: store double 2.500000e+00, double* [[A2]], align 8 3147 // CHECK13-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3148 // CHECK13-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 3149 // CHECK13-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 3150 // CHECK13-NEXT: ret i32 [[CONV4]] 3151 // 3152 // 3153 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici 3154 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 3155 // CHECK13-NEXT: entry: 3156 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3157 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3158 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3159 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3160 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3161 // CHECK13-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3162 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3163 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 3164 // CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3165 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3166 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 3167 // CHECK13-NEXT: ret i32 [[ADD2]] 3168 // 3169 // 3170 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3171 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 3172 // CHECK13-NEXT: entry: 3173 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3174 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 3175 // CHECK13-NEXT: [[B:%.*]] = alloca i16, align 2 3176 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3177 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3178 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 3179 // CHECK13-NEXT: store i16 1, i16* [[B]], align 2 3180 // CHECK13-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 3181 // CHECK13-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 3182 // CHECK13-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 3183 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3184 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3185 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 3186 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3187 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3188 // CHECK13-NEXT: ret i32 [[TMP3]] 3189 // 3190 // 3191 // CHECK14-LABEL: define {{[^@]+}}@_Z3bari 3192 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3193 // CHECK14-NEXT: entry: 3194 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3195 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 3196 // CHECK14-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 3197 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3198 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 3199 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3200 // CHECK14-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 3201 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3202 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3203 // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3204 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3205 // CHECK14-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 3206 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3207 // CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3208 // CHECK14-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3209 // CHECK14-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3210 // CHECK14-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 3211 // CHECK14-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3212 // CHECK14-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3213 // CHECK14-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3214 // CHECK14-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3215 // CHECK14-NEXT: ret i32 [[TMP6]] 3216 // 3217 // 3218 // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3219 // CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3220 // CHECK14-NEXT: entry: 3221 // CHECK14-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3222 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3223 // CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 3224 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3225 // CHECK14-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3226 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3227 // CHECK14-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3228 // CHECK14-NEXT: store i32 1, i32* [[B]], align 4 3229 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3230 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3231 // CHECK14-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3232 // CHECK14-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3233 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3234 // CHECK14-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 3235 // CHECK14-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3236 // CHECK14-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3237 // CHECK14-NEXT: store double [[ADD]], double* [[A]], align 8 3238 // CHECK14-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3239 // CHECK14-NEXT: store double 2.500000e+00, double* [[A2]], align 8 3240 // CHECK14-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3241 // CHECK14-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 3242 // CHECK14-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 3243 // CHECK14-NEXT: ret i32 [[CONV4]] 3244 // 3245 // 3246 // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici 3247 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 3248 // CHECK14-NEXT: entry: 3249 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3250 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3251 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3252 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3253 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3254 // CHECK14-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3255 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3256 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 3257 // CHECK14-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3258 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3259 // CHECK14-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 3260 // CHECK14-NEXT: ret i32 [[ADD2]] 3261 // 3262 // 3263 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3264 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 3265 // CHECK14-NEXT: entry: 3266 // CHECK14-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3267 // CHECK14-NEXT: [[A:%.*]] = alloca i32, align 4 3268 // CHECK14-NEXT: [[B:%.*]] = alloca i16, align 2 3269 // CHECK14-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3270 // CHECK14-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3271 // CHECK14-NEXT: store i32 0, i32* [[A]], align 4 3272 // CHECK14-NEXT: store i16 1, i16* [[B]], align 2 3273 // CHECK14-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 3274 // CHECK14-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 3275 // CHECK14-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 3276 // CHECK14-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3277 // CHECK14-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3278 // CHECK14-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 3279 // CHECK14-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3280 // CHECK14-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3281 // CHECK14-NEXT: ret i32 [[TMP3]] 3282 // 3283 // 3284 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari 3285 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3286 // CHECK15-NEXT: entry: 3287 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3288 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 3289 // CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3290 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3291 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 3292 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3293 // CHECK15-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 3294 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3295 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3296 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3297 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3298 // CHECK15-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 3299 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3300 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3301 // CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3302 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3303 // CHECK15-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 3304 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3305 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3306 // CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3307 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3308 // CHECK15-NEXT: ret i32 [[TMP6]] 3309 // 3310 // 3311 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3312 // CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3313 // CHECK15-NEXT: entry: 3314 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3315 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3316 // CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 3317 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3318 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3319 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3320 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3321 // CHECK15-NEXT: store i32 1, i32* [[B]], align 4 3322 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3323 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3324 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3325 // CHECK15-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3326 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3327 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 3328 // CHECK15-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3329 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3330 // CHECK15-NEXT: store double [[ADD]], double* [[A]], align 4 3331 // CHECK15-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3332 // CHECK15-NEXT: store double 2.500000e+00, double* [[A2]], align 4 3333 // CHECK15-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3334 // CHECK15-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 3335 // CHECK15-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 3336 // CHECK15-NEXT: ret i32 [[CONV4]] 3337 // 3338 // 3339 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici 3340 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 3341 // CHECK15-NEXT: entry: 3342 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3343 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3344 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3345 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3346 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3347 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3348 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3349 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 3350 // CHECK15-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3351 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3352 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 3353 // CHECK15-NEXT: ret i32 [[ADD2]] 3354 // 3355 // 3356 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3357 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 3358 // CHECK15-NEXT: entry: 3359 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3360 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 3361 // CHECK15-NEXT: [[B:%.*]] = alloca i16, align 2 3362 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3363 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3364 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 3365 // CHECK15-NEXT: store i16 1, i16* [[B]], align 2 3366 // CHECK15-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 3367 // CHECK15-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 3368 // CHECK15-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 3369 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3370 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3371 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 3372 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3373 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3374 // CHECK15-NEXT: ret i32 [[TMP3]] 3375 // 3376 // 3377 // CHECK16-LABEL: define {{[^@]+}}@_Z3bari 3378 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3379 // CHECK16-NEXT: entry: 3380 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3381 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 3382 // CHECK16-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3383 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3384 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 3385 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3386 // CHECK16-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 3387 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3388 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3389 // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3390 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3391 // CHECK16-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 3392 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3393 // CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3394 // CHECK16-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3395 // CHECK16-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3396 // CHECK16-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 3397 // CHECK16-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3398 // CHECK16-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3399 // CHECK16-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3400 // CHECK16-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3401 // CHECK16-NEXT: ret i32 [[TMP6]] 3402 // 3403 // 3404 // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3405 // CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3406 // CHECK16-NEXT: entry: 3407 // CHECK16-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3408 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3409 // CHECK16-NEXT: [[B:%.*]] = alloca i32, align 4 3410 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3411 // CHECK16-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3412 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3413 // CHECK16-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3414 // CHECK16-NEXT: store i32 1, i32* [[B]], align 4 3415 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3416 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3417 // CHECK16-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3418 // CHECK16-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3419 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3420 // CHECK16-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 3421 // CHECK16-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3422 // CHECK16-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3423 // CHECK16-NEXT: store double [[ADD]], double* [[A]], align 4 3424 // CHECK16-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3425 // CHECK16-NEXT: store double 2.500000e+00, double* [[A2]], align 4 3426 // CHECK16-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3427 // CHECK16-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 3428 // CHECK16-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 3429 // CHECK16-NEXT: ret i32 [[CONV4]] 3430 // 3431 // 3432 // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici 3433 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 3434 // CHECK16-NEXT: entry: 3435 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3436 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3437 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3438 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3439 // CHECK16-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3440 // CHECK16-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3441 // CHECK16-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3442 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 3443 // CHECK16-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3444 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3445 // CHECK16-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 3446 // CHECK16-NEXT: ret i32 [[ADD2]] 3447 // 3448 // 3449 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3450 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 3451 // CHECK16-NEXT: entry: 3452 // CHECK16-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3453 // CHECK16-NEXT: [[A:%.*]] = alloca i32, align 4 3454 // CHECK16-NEXT: [[B:%.*]] = alloca i16, align 2 3455 // CHECK16-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3456 // CHECK16-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3457 // CHECK16-NEXT: store i32 0, i32* [[A]], align 4 3458 // CHECK16-NEXT: store i16 1, i16* [[B]], align 2 3459 // CHECK16-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 3460 // CHECK16-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 3461 // CHECK16-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 3462 // CHECK16-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 3463 // CHECK16-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 3464 // CHECK16-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 3465 // CHECK16-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3466 // CHECK16-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3467 // CHECK16-NEXT: ret i32 [[TMP3]] 3468 // 3469 // 3470 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari 3471 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3472 // CHECK17-NEXT: entry: 3473 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3474 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 3475 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 3476 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3477 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 3478 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3479 // CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 3480 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3481 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3482 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3483 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3484 // CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 3485 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3486 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3487 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3488 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3489 // CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 3490 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3491 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3492 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3493 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3494 // CHECK17-NEXT: ret i32 [[TMP6]] 3495 // 3496 // 3497 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3498 // CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3499 // CHECK17-NEXT: entry: 3500 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3501 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3502 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 3503 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3504 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3505 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3506 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3507 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3508 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3509 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 3510 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 3511 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 3512 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3513 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3514 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3515 // CHECK17-NEXT: store i32 1, i32* [[B]], align 4 3516 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3517 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3518 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3519 // CHECK17-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3520 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3521 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3522 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 3523 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 3524 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3525 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3526 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 3527 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3528 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3529 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3530 // CHECK17-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 3531 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 3532 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3533 // CHECK17-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 3534 // CHECK17-NEXT: store double* [[A]], double** [[TMP9]], align 8 3535 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3536 // CHECK17-NEXT: store i8* null, i8** [[TMP10]], align 8 3537 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3538 // CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 3539 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 3540 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3541 // CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 3542 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 3543 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3544 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 3545 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3546 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 3547 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 3548 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3549 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 3550 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 3551 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3552 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 3553 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3554 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3555 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3556 // CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 3557 // CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 3558 // CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3559 // CHECK17: omp_offload.failed: 3560 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] 3561 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 3562 // CHECK17: omp_offload.cont: 3563 // CHECK17-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3564 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3565 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 3566 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 3567 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3568 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 3569 // CHECK17-NEXT: store double* [[A3]], double** [[TMP29]], align 8 3570 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 3571 // CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 3572 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3573 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3574 // CHECK17-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) 3575 // CHECK17-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 3576 // CHECK17-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 3577 // CHECK17: omp_offload.failed7: 3578 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 3579 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] 3580 // CHECK17: omp_offload.cont8: 3581 // CHECK17-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 3582 // CHECK17-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 3583 // CHECK17-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 3584 // CHECK17-NEXT: ret i32 [[CONV10]] 3585 // 3586 // 3587 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici 3588 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 3589 // CHECK17-NEXT: entry: 3590 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3591 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3592 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3593 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 3594 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 3595 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 3596 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 3597 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 3598 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 3599 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 3600 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 3601 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3602 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3603 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 3604 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3605 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3606 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 3607 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3608 // CHECK17-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3609 // CHECK17-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 3610 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 3611 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3612 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 3613 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 3614 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3615 // CHECK17-NEXT: store i8* null, i8** [[TMP7]], align 8 3616 // CHECK17-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3617 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3618 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3619 // CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) 3620 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 3621 // CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3622 // CHECK17: omp_offload.failed: 3623 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] 3624 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 3625 // CHECK17: omp_offload.cont: 3626 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 3627 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 3628 // CHECK17-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 3629 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3630 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* 3631 // CHECK17-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 3632 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 3633 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3634 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 3635 // CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 3636 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3637 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 3638 // CHECK17-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 3639 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 3640 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 3641 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 3642 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 3643 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 3644 // CHECK17-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 3645 // CHECK17-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 3646 // CHECK17-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 3647 // CHECK17: omp_offload.failed7: 3648 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] 3649 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT8]] 3650 // CHECK17: omp_offload.cont8: 3651 // CHECK17-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 3652 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 3653 // CHECK17-NEXT: ret i32 [[ADD9]] 3654 // 3655 // 3656 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3657 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 3658 // CHECK17-NEXT: entry: 3659 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3660 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 3661 // CHECK17-NEXT: [[B:%.*]] = alloca i16, align 2 3662 // CHECK17-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 3663 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3664 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3665 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3666 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3667 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3668 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3669 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3670 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 3671 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) 3672 // CHECK17-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 3673 // CHECK17-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3674 // CHECK17: omp_offload.failed: 3675 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 3676 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 3677 // CHECK17: omp_offload.cont: 3678 // CHECK17-NEXT: store i16 1, i16* [[B]], align 2 3679 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 3680 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 3681 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3682 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3683 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 3684 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 3685 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 3686 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* 3687 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 3688 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 3689 // CHECK17-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 3690 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* 3691 // CHECK17-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 3692 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3693 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3694 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 3695 // CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 3696 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3697 // CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 3698 // CHECK17-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 3699 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3700 // CHECK17-NEXT: store i8* null, i8** [[TMP13]], align 8 3701 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3702 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 3703 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 3704 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3705 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 3706 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 3707 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3708 // CHECK17-NEXT: store i8* null, i8** [[TMP18]], align 8 3709 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3710 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 3711 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 3712 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3713 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 3714 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 3715 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3716 // CHECK17-NEXT: store i8* null, i8** [[TMP23]], align 8 3717 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3718 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3719 // CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 3720 // CHECK17-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 3721 // CHECK17-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) 3722 // CHECK17-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 3723 // CHECK17-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 3724 // CHECK17: omp_offload.failed3: 3725 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] 3726 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT4]] 3727 // CHECK17: omp_offload.cont4: 3728 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 3729 // CHECK17-NEXT: ret i32 [[TMP30]] 3730 // 3731 // 3732 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 3733 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 3734 // CHECK17-NEXT: entry: 3735 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3736 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3737 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3738 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3739 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3740 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3741 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3742 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3743 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3744 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3745 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3746 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 3747 // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 3748 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 3749 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3750 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 3751 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 3752 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 3753 // CHECK17-NEXT: ret void 3754 // 3755 // 3756 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 3757 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 3758 // CHECK17-NEXT: entry: 3759 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3760 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3761 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3762 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3763 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3764 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3765 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3766 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3767 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3768 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 3769 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3770 // CHECK17-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 3771 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 3772 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3773 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 3774 // CHECK17-NEXT: ret void 3775 // 3776 // 3777 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 3778 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 3779 // CHECK17-NEXT: entry: 3780 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3781 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3782 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3783 // CHECK17-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3784 // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 3785 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 3786 // CHECK17-NEXT: ret void 3787 // 3788 // 3789 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 3790 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 3791 // CHECK17-NEXT: entry: 3792 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3793 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3794 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3795 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3796 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3797 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3798 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3799 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3800 // CHECK17-NEXT: store double 2.500000e+00, double* [[A]], align 8 3801 // CHECK17-NEXT: ret void 3802 // 3803 // 3804 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 3805 // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 3806 // CHECK17-NEXT: entry: 3807 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3808 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3809 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3810 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3811 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3812 // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 3813 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 3814 // CHECK17-NEXT: ret void 3815 // 3816 // 3817 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 3818 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 3819 // CHECK17-NEXT: entry: 3820 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3821 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3822 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3823 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3824 // CHECK17-NEXT: ret void 3825 // 3826 // 3827 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 3828 // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 3829 // CHECK17-NEXT: entry: 3830 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3831 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3832 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3833 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 3834 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3835 // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 3836 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 3837 // CHECK17-NEXT: ret void 3838 // 3839 // 3840 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 3841 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 3842 // CHECK17-NEXT: entry: 3843 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3844 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3845 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3846 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3847 // CHECK17-NEXT: ret void 3848 // 3849 // 3850 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 3851 // CHECK17-SAME: () #[[ATTR1]] { 3852 // CHECK17-NEXT: entry: 3853 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3854 // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 3855 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 3856 // CHECK17-NEXT: ret void 3857 // 3858 // 3859 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 3860 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 3861 // CHECK17-NEXT: entry: 3862 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3863 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3864 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3865 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3866 // CHECK17-NEXT: ret void 3867 // 3868 // 3869 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 3870 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 3871 // CHECK17-NEXT: entry: 3872 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3873 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3874 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3875 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3876 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3877 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 3878 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3879 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3880 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3881 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3882 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 3883 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 3884 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 3885 // CHECK17-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 3886 // CHECK17-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 3887 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 3888 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3889 // CHECK17-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 3890 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 3891 // CHECK17-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 3892 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 3893 // CHECK17-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 3894 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 3895 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 3896 // CHECK17-NEXT: ret void 3897 // 3898 // 3899 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 3900 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 3901 // CHECK17-NEXT: entry: 3902 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3903 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3904 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3905 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 3906 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3907 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3908 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3909 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 3910 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3911 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 3912 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 3913 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 3914 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 3915 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 3916 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 3917 // CHECK17-NEXT: ret void 3918 // 3919 // 3920 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3921 // CHECK17-SAME: () #[[ATTR3:[0-9]+]] { 3922 // CHECK17-NEXT: entry: 3923 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 3924 // CHECK17-NEXT: ret void 3925 // 3926 // 3927 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari 3928 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3929 // CHECK18-NEXT: entry: 3930 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3931 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 3932 // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 3933 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3934 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 3935 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3936 // CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 3937 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3938 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3939 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3940 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3941 // CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 3942 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3943 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3944 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3945 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3946 // CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 3947 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3948 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3949 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3950 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 3951 // CHECK18-NEXT: ret i32 [[TMP6]] 3952 // 3953 // 3954 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3955 // CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3956 // CHECK18-NEXT: entry: 3957 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 3958 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3959 // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 3960 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3961 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 3962 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3963 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3964 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3965 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3966 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 3967 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 3968 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 3969 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 3970 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3971 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 3972 // CHECK18-NEXT: store i32 1, i32* [[B]], align 4 3973 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3974 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 3975 // CHECK18-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 3976 // CHECK18-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 3977 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 3978 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 3979 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[CONV]], align 4 3980 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8 3981 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3982 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3983 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV2]], align 4 3984 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3985 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3986 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3987 // CHECK18-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 3988 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 8 3989 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3990 // CHECK18-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 3991 // CHECK18-NEXT: store double* [[A]], double** [[TMP9]], align 8 3992 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3993 // CHECK18-NEXT: store i8* null, i8** [[TMP10]], align 8 3994 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3995 // CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 3996 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP12]], align 8 3997 // CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3998 // CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i64* 3999 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP14]], align 8 4000 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4001 // CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 4002 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4003 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 4004 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP17]], align 8 4005 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4006 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 4007 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP19]], align 8 4008 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4009 // CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 4010 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4011 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4012 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4013 // CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 4014 // CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4015 // CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4016 // CHECK18: omp_offload.failed: 4017 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP3]], i64 [[TMP5]]) #[[ATTR2:[0-9]+]] 4018 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 4019 // CHECK18: omp_offload.cont: 4020 // CHECK18-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4021 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 4022 // CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 4023 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 8 4024 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 4025 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 4026 // CHECK18-NEXT: store double* [[A3]], double** [[TMP29]], align 8 4027 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 4028 // CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 4029 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 4030 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 4031 // CHECK18-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) 4032 // CHECK18-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 4033 // CHECK18-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 4034 // CHECK18: omp_offload.failed7: 4035 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 4036 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] 4037 // CHECK18: omp_offload.cont8: 4038 // CHECK18-NEXT: [[A9:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4039 // CHECK18-NEXT: [[TMP35:%.*]] = load double, double* [[A9]], align 8 4040 // CHECK18-NEXT: [[CONV10:%.*]] = fptosi double [[TMP35]] to i32 4041 // CHECK18-NEXT: ret i32 [[CONV10]] 4042 // 4043 // 4044 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici 4045 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 4046 // CHECK18-NEXT: entry: 4047 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4048 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4049 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4050 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 4051 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 4052 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 4053 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4054 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i64, align 8 4055 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [1 x i8*], align 8 4056 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS5:%.*]] = alloca [1 x i8*], align 8 4057 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [1 x i8*], align 8 4058 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4059 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4060 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 4061 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4062 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 4063 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV]], align 4 4064 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4065 // CHECK18-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4066 // CHECK18-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i64* 4067 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP4]], align 8 4068 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4069 // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 4070 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP6]], align 8 4071 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4072 // CHECK18-NEXT: store i8* null, i8** [[TMP7]], align 8 4073 // CHECK18-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4074 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4075 // CHECK18-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4076 // CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) 4077 // CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4078 // CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4079 // CHECK18: omp_offload.failed: 4080 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]] 4081 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 4082 // CHECK18: omp_offload.cont: 4083 // CHECK18-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 4084 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 4085 // CHECK18-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4086 // CHECK18-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4087 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED2]] to i32* 4088 // CHECK18-NEXT: store i32 [[TMP14]], i32* [[CONV3]], align 4 4089 // CHECK18-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED2]], align 8 4090 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 4091 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 4092 // CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP17]], align 8 4093 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 4094 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 4095 // CHECK18-NEXT: store i64 [[TMP15]], i64* [[TMP19]], align 8 4096 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0 4097 // CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 4098 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0 4099 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0 4100 // CHECK18-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4101 // CHECK18-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 4102 // CHECK18-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4103 // CHECK18-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]] 4104 // CHECK18: omp_offload.failed7: 4105 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i64 [[TMP15]]) #[[ATTR2]] 4106 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT8]] 4107 // CHECK18: omp_offload.cont8: 4108 // CHECK18-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 4109 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP26]], 1 4110 // CHECK18-NEXT: ret i32 [[ADD9]] 4111 // 4112 // 4113 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4114 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 4115 // CHECK18-NEXT: entry: 4116 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4117 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 4118 // CHECK18-NEXT: [[B:%.*]] = alloca i16, align 2 4119 // CHECK18-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 4120 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4121 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4122 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4123 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 4124 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 4125 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 4126 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4127 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 4128 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) 4129 // CHECK18-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 4130 // CHECK18-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4131 // CHECK18: omp_offload.failed: 4132 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 4133 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 4134 // CHECK18: omp_offload.cont: 4135 // CHECK18-NEXT: store i16 1, i16* [[B]], align 2 4136 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 4137 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 4138 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4139 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4140 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 4141 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 4142 // CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 4143 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_CASTED]] to i16* 4144 // CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV1]], align 2 4145 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 4146 // CHECK18-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 4147 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i16* 4148 // CHECK18-NEXT: store i16 [[TMP7]], i16* [[CONV2]], align 2 4149 // CHECK18-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4150 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4151 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 4152 // CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 4153 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4154 // CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* 4155 // CHECK18-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 4156 // CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4157 // CHECK18-NEXT: store i8* null, i8** [[TMP13]], align 8 4158 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4159 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 4160 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP15]], align 8 4161 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4162 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 4163 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 4164 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4165 // CHECK18-NEXT: store i8* null, i8** [[TMP18]], align 8 4166 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4167 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 4168 // CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP20]], align 8 4169 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4170 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 4171 // CHECK18-NEXT: store i64 [[TMP8]], i64* [[TMP22]], align 8 4172 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4173 // CHECK18-NEXT: store i8* null, i8** [[TMP23]], align 8 4174 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4175 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4176 // CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 4177 // CHECK18-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 4178 // CHECK18-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) 4179 // CHECK18-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 4180 // CHECK18-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED3:%.*]], label [[OMP_OFFLOAD_CONT4:%.*]] 4181 // CHECK18: omp_offload.failed3: 4182 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP4]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2]] 4183 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT4]] 4184 // CHECK18: omp_offload.cont4: 4185 // CHECK18-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 4186 // CHECK18-NEXT: ret i32 [[TMP30]] 4187 // 4188 // 4189 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 4190 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 4191 // CHECK18-NEXT: entry: 4192 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4193 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4194 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4195 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4196 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4197 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4198 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4199 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4200 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4201 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4202 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4203 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 4204 // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 4205 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 4206 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4207 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 4208 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 4209 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 4210 // CHECK18-NEXT: ret void 4211 // 4212 // 4213 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 4214 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 4215 // CHECK18-NEXT: entry: 4216 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4217 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4218 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4219 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4220 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4221 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4222 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4223 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4224 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4225 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4226 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4227 // CHECK18-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 4228 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 4229 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4230 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 4231 // CHECK18-NEXT: ret void 4232 // 4233 // 4234 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 4235 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 4236 // CHECK18-NEXT: entry: 4237 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4238 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4239 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4240 // CHECK18-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4241 // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 4242 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 4243 // CHECK18-NEXT: ret void 4244 // 4245 // 4246 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1 4247 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 4248 // CHECK18-NEXT: entry: 4249 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4250 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4251 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4252 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4253 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4254 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4255 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4256 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4257 // CHECK18-NEXT: store double 2.500000e+00, double* [[A]], align 8 4258 // CHECK18-NEXT: ret void 4259 // 4260 // 4261 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 4262 // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4263 // CHECK18-NEXT: entry: 4264 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4265 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4266 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4267 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4268 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4269 // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 4270 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 4271 // CHECK18-NEXT: ret void 4272 // 4273 // 4274 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 4275 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4276 // CHECK18-NEXT: entry: 4277 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4278 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4279 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4280 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4281 // CHECK18-NEXT: ret void 4282 // 4283 // 4284 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 4285 // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4286 // CHECK18-NEXT: entry: 4287 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4288 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4289 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4290 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4291 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4292 // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 4293 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 4294 // CHECK18-NEXT: ret void 4295 // 4296 // 4297 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 4298 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4299 // CHECK18-NEXT: entry: 4300 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4301 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4302 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4303 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4304 // CHECK18-NEXT: ret void 4305 // 4306 // 4307 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 4308 // CHECK18-SAME: () #[[ATTR1]] { 4309 // CHECK18-NEXT: entry: 4310 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4311 // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 4312 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 4313 // CHECK18-NEXT: ret void 4314 // 4315 // 4316 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 4317 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4318 // CHECK18-NEXT: entry: 4319 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4320 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4321 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4322 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4323 // CHECK18-NEXT: ret void 4324 // 4325 // 4326 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 4327 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4328 // CHECK18-NEXT: entry: 4329 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4330 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4331 // CHECK18-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4332 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4333 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4334 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4335 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4336 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4337 // CHECK18-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4338 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4339 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 4340 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 4341 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 4342 // CHECK18-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 4343 // CHECK18-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 4344 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 4345 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4346 // CHECK18-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 4347 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 4348 // CHECK18-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 4349 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 4350 // CHECK18-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 4351 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 4352 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 4353 // CHECK18-NEXT: ret void 4354 // 4355 // 4356 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 4357 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] { 4358 // CHECK18-NEXT: entry: 4359 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4360 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4361 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4362 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4363 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4364 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4365 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4366 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4367 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4368 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 4369 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 4370 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 4371 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 4372 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 4373 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 4374 // CHECK18-NEXT: ret void 4375 // 4376 // 4377 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4378 // CHECK18-SAME: () #[[ATTR3:[0-9]+]] { 4379 // CHECK18-NEXT: entry: 4380 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 4381 // CHECK18-NEXT: ret void 4382 // 4383 // 4384 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari 4385 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 4386 // CHECK19-NEXT: entry: 4387 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4388 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 4389 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 4390 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4391 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 4392 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4393 // CHECK19-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 4394 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 4395 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4396 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 4397 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4398 // CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 4399 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4400 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4401 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 4402 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4403 // CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 4404 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4405 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4406 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 4407 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 4408 // CHECK19-NEXT: ret i32 [[TMP6]] 4409 // 4410 // 4411 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4412 // CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4413 // CHECK19-NEXT: entry: 4414 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4415 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4416 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 4417 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4418 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4419 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4420 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4421 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4422 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4423 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 4424 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 4425 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 4426 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4427 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4428 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4429 // CHECK19-NEXT: store i32 1, i32* [[B]], align 4 4430 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4431 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 4432 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 4433 // CHECK19-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 4434 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 4435 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 4436 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 4437 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4438 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4439 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4440 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 4441 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4442 // CHECK19-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 4443 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 4444 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4445 // CHECK19-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 4446 // CHECK19-NEXT: store double* [[A]], double** [[TMP9]], align 4 4447 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4448 // CHECK19-NEXT: store i8* null, i8** [[TMP10]], align 4 4449 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4450 // CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 4451 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 4452 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4453 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 4454 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 4455 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4456 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 4457 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4458 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4459 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 4460 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4461 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4462 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 4463 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4464 // CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 4465 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4466 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4467 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4468 // CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 4469 // CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4470 // CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4471 // CHECK19: omp_offload.failed: 4472 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] 4473 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 4474 // CHECK19: omp_offload.cont: 4475 // CHECK19-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4476 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4477 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 4478 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 4479 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4480 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 4481 // CHECK19-NEXT: store double* [[A2]], double** [[TMP29]], align 4 4482 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 4483 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 4484 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4485 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4486 // CHECK19-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) 4487 // CHECK19-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 4488 // CHECK19-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 4489 // CHECK19: omp_offload.failed6: 4490 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 4491 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] 4492 // CHECK19: omp_offload.cont7: 4493 // CHECK19-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4494 // CHECK19-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 4495 // CHECK19-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 4496 // CHECK19-NEXT: ret i32 [[CONV]] 4497 // 4498 // 4499 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici 4500 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 4501 // CHECK19-NEXT: entry: 4502 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4503 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4504 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4505 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 4506 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 4507 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 4508 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4509 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 4510 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 4511 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 4512 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 4513 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4514 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4515 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 4516 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4517 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4518 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4519 // CHECK19-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4520 // CHECK19-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 4521 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 4522 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4523 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4524 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 4525 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4526 // CHECK19-NEXT: store i8* null, i8** [[TMP7]], align 4 4527 // CHECK19-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4528 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4529 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4530 // CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) 4531 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4532 // CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4533 // CHECK19: omp_offload.failed: 4534 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] 4535 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 4536 // CHECK19: omp_offload.cont: 4537 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 4538 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 4539 // CHECK19-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4540 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4541 // CHECK19-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 4542 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 4543 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4544 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4545 // CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 4546 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4547 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4548 // CHECK19-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 4549 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 4550 // CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 4551 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4552 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4553 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4554 // CHECK19-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 4555 // CHECK19-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4556 // CHECK19-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 4557 // CHECK19: omp_offload.failed6: 4558 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] 4559 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT7]] 4560 // CHECK19: omp_offload.cont7: 4561 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 4562 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 4563 // CHECK19-NEXT: ret i32 [[ADD8]] 4564 // 4565 // 4566 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4567 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 4568 // CHECK19-NEXT: entry: 4569 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4570 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 4571 // CHECK19-NEXT: [[B:%.*]] = alloca i16, align 2 4572 // CHECK19-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 4573 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4574 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4575 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4576 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4577 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4578 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4579 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4580 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 4581 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) 4582 // CHECK19-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 4583 // CHECK19-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4584 // CHECK19: omp_offload.failed: 4585 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 4586 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 4587 // CHECK19: omp_offload.cont: 4588 // CHECK19-NEXT: store i16 1, i16* [[B]], align 2 4589 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 4590 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 4591 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4592 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 4593 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 4594 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 4595 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 4596 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 4597 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 4598 // CHECK19-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 4599 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* 4600 // CHECK19-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 4601 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4602 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4603 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 4604 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 4605 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4606 // CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 4607 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 4608 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4609 // CHECK19-NEXT: store i8* null, i8** [[TMP13]], align 4 4610 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4611 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 4612 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 4613 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4614 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4615 // CHECK19-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 4616 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4617 // CHECK19-NEXT: store i8* null, i8** [[TMP18]], align 4 4618 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4619 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 4620 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 4621 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4622 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 4623 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 4624 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4625 // CHECK19-NEXT: store i8* null, i8** [[TMP23]], align 4 4626 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4627 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4628 // CHECK19-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 4629 // CHECK19-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 4630 // CHECK19-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) 4631 // CHECK19-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 4632 // CHECK19-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] 4633 // CHECK19: omp_offload.failed2: 4634 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] 4635 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT3]] 4636 // CHECK19: omp_offload.cont3: 4637 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 4638 // CHECK19-NEXT: ret i32 [[TMP30]] 4639 // 4640 // 4641 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 4642 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 4643 // CHECK19-NEXT: entry: 4644 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4645 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4646 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4647 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4648 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4649 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4650 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4651 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4652 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4653 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4654 // CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 4655 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 4656 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 4657 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 4658 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 4659 // CHECK19-NEXT: ret void 4660 // 4661 // 4662 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 4663 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 4664 // CHECK19-NEXT: entry: 4665 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4666 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4667 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4668 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4669 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4670 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4671 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4672 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4673 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4674 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 4675 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 4676 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4677 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4678 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 4679 // CHECK19-NEXT: ret void 4680 // 4681 // 4682 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 4683 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 4684 // CHECK19-NEXT: entry: 4685 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4686 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4687 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4688 // CHECK19-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4689 // CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 4690 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 4691 // CHECK19-NEXT: ret void 4692 // 4693 // 4694 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 4695 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 4696 // CHECK19-NEXT: entry: 4697 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4698 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4699 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4700 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4701 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4702 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4703 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4704 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4705 // CHECK19-NEXT: store double 2.500000e+00, double* [[A]], align 4 4706 // CHECK19-NEXT: ret void 4707 // 4708 // 4709 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 4710 // CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4711 // CHECK19-NEXT: entry: 4712 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4713 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4714 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4715 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4716 // CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 4717 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 4718 // CHECK19-NEXT: ret void 4719 // 4720 // 4721 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 4722 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4723 // CHECK19-NEXT: entry: 4724 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4725 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4726 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4727 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4728 // CHECK19-NEXT: ret void 4729 // 4730 // 4731 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 4732 // CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4733 // CHECK19-NEXT: entry: 4734 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4735 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4736 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4737 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4738 // CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 4739 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 4740 // CHECK19-NEXT: ret void 4741 // 4742 // 4743 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 4744 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4745 // CHECK19-NEXT: entry: 4746 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4747 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4748 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4749 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4750 // CHECK19-NEXT: ret void 4751 // 4752 // 4753 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 4754 // CHECK19-SAME: () #[[ATTR1]] { 4755 // CHECK19-NEXT: entry: 4756 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4757 // CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 4758 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 4759 // CHECK19-NEXT: ret void 4760 // 4761 // 4762 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 4763 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 4764 // CHECK19-NEXT: entry: 4765 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4766 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4767 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4768 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4769 // CHECK19-NEXT: ret void 4770 // 4771 // 4772 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 4773 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 4774 // CHECK19-NEXT: entry: 4775 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4776 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4777 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 4778 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4779 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4780 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 4781 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4782 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4783 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 4784 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 4785 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 4786 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 4787 // CHECK19-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 4788 // CHECK19-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 4789 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 4790 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 4791 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 4792 // CHECK19-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 4793 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 4794 // CHECK19-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 4795 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 4796 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 4797 // CHECK19-NEXT: ret void 4798 // 4799 // 4800 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 4801 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 4802 // CHECK19-NEXT: entry: 4803 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4804 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4805 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4806 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4807 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4808 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4809 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4810 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4811 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 4812 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 4813 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 4814 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4815 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 4816 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4817 // CHECK19-NEXT: ret void 4818 // 4819 // 4820 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4821 // CHECK19-SAME: () #[[ATTR3:[0-9]+]] { 4822 // CHECK19-NEXT: entry: 4823 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 4824 // CHECK19-NEXT: ret void 4825 // 4826 // 4827 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari 4828 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 4829 // CHECK20-NEXT: entry: 4830 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4831 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 4832 // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 4833 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4834 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 4835 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4836 // CHECK20-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 4837 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 4838 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4839 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 4840 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4841 // CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 4842 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4843 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4844 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 4845 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4846 // CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 4847 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4848 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4849 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 4850 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 4851 // CHECK20-NEXT: ret i32 [[TMP6]] 4852 // 4853 // 4854 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4855 // CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4856 // CHECK20-NEXT: entry: 4857 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4858 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4859 // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 4860 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4861 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4862 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4863 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4864 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4865 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4866 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 4867 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 4868 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 4869 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4870 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4871 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4872 // CHECK20-NEXT: store i32 1, i32* [[B]], align 4 4873 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4874 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 4875 // CHECK20-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 4876 // CHECK20-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 4877 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 4878 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[B_CASTED]], align 4 4879 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4 4880 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4881 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4882 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4883 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 4884 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4885 // CHECK20-NEXT: [[TMP7:%.*]] = bitcast i8** [[TMP6]] to %struct.S1** 4886 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP7]], align 4 4887 // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4888 // CHECK20-NEXT: [[TMP9:%.*]] = bitcast i8** [[TMP8]] to double** 4889 // CHECK20-NEXT: store double* [[A]], double** [[TMP9]], align 4 4890 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4891 // CHECK20-NEXT: store i8* null, i8** [[TMP10]], align 4 4892 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4893 // CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 4894 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP12]], align 4 4895 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4896 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 4897 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP14]], align 4 4898 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4899 // CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 4900 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4901 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4902 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 4903 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4904 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4905 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 4906 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4907 // CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 4908 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4909 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4910 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4911 // CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 4912 // CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4913 // CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4914 // CHECK20: omp_offload.failed: 4915 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP3]], i32 [[TMP5]]) #[[ATTR2:[0-9]+]] 4916 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 4917 // CHECK20: omp_offload.cont: 4918 // CHECK20-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4919 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4920 // CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to %struct.S1** 4921 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP27]], align 4 4922 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4923 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to double** 4924 // CHECK20-NEXT: store double* [[A2]], double** [[TMP29]], align 4 4925 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 4926 // CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 4927 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4928 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4929 // CHECK20-NEXT: [[TMP33:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 1, i8** [[TMP31]], i8** [[TMP32]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1024) 4930 // CHECK20-NEXT: [[TMP34:%.*]] = icmp ne i32 [[TMP33]], 0 4931 // CHECK20-NEXT: br i1 [[TMP34]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 4932 // CHECK20: omp_offload.failed6: 4933 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]]) #[[ATTR2]] 4934 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] 4935 // CHECK20: omp_offload.cont7: 4936 // CHECK20-NEXT: [[A8:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 4937 // CHECK20-NEXT: [[TMP35:%.*]] = load double, double* [[A8]], align 4 4938 // CHECK20-NEXT: [[CONV:%.*]] = fptosi double [[TMP35]] to i32 4939 // CHECK20-NEXT: ret i32 [[CONV]] 4940 // 4941 // 4942 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici 4943 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 4944 // CHECK20-NEXT: entry: 4945 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4946 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 4947 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 4948 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 4949 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 4950 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 4951 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 4952 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 4953 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS3:%.*]] = alloca [1 x i8*], align 4 4954 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS4:%.*]] = alloca [1 x i8*], align 4 4955 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS5:%.*]] = alloca [1 x i8*], align 4 4956 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4957 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4958 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 4959 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4960 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4961 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 4962 // CHECK20-NEXT: [[TMP3:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4963 // CHECK20-NEXT: [[TMP4:%.*]] = bitcast i8** [[TMP3]] to i32* 4964 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP4]], align 4 4965 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4966 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4967 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[TMP6]], align 4 4968 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4969 // CHECK20-NEXT: store i8* null, i8** [[TMP7]], align 4 4970 // CHECK20-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4971 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4972 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 4973 // CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP8]], i8** [[TMP9]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP10]]) 4974 // CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4975 // CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4976 // CHECK20: omp_offload.failed: 4977 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]] 4978 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 4979 // CHECK20: omp_offload.cont: 4980 // CHECK20-NEXT: [[TMP13:%.*]] = load i32, i32* [[N_ADDR]], align 4 4981 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP13]] 4982 // CHECK20-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 4983 // CHECK20-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4984 // CHECK20-NEXT: store i32 [[TMP14]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 4985 // CHECK20-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 4986 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4987 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 4988 // CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP17]], align 4 4989 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4990 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 4991 // CHECK20-NEXT: store i32 [[TMP15]], i32* [[TMP19]], align 4 4992 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS5]], i32 0, i32 0 4993 // CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 4994 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS3]], i32 0, i32 0 4995 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS4]], i32 0, i32 0 4996 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 4997 // CHECK20-NEXT: [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 1, i8** [[TMP21]], i8** [[TMP22]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.8, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]]) 4998 // CHECK20-NEXT: [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0 4999 // CHECK20-NEXT: br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]] 5000 // CHECK20: omp_offload.failed6: 5001 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108(i32 [[TMP15]]) #[[ATTR2]] 5002 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT7]] 5003 // CHECK20: omp_offload.cont7: 5004 // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 5005 // CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP26]], 1 5006 // CHECK20-NEXT: ret i32 [[ADD8]] 5007 // 5008 // 5009 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5010 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 5011 // CHECK20-NEXT: entry: 5012 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5013 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 5014 // CHECK20-NEXT: [[B:%.*]] = alloca i16, align 2 5015 // CHECK20-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5016 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5017 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5018 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5019 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 5020 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 5021 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 5022 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5023 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 5024 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 20) 5025 // CHECK20-NEXT: [[TMP1:%.*]] = icmp ne i32 [[TMP0]], 0 5026 // CHECK20-NEXT: br i1 [[TMP1]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5027 // CHECK20: omp_offload.failed: 5028 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88() #[[ATTR2]] 5029 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 5030 // CHECK20: omp_offload.cont: 5031 // CHECK20-NEXT: store i16 1, i16* [[B]], align 2 5032 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[B]], align 2 5033 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[DOTCAPTURE_EXPR_]], align 2 5034 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5035 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 5036 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 5037 // CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[B]], align 2 5038 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16* 5039 // CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV]], align 2 5040 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 5041 // CHECK20-NEXT: [[TMP7:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 5042 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i16* 5043 // CHECK20-NEXT: store i16 [[TMP7]], i16* [[CONV1]], align 2 5044 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5045 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5046 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 5047 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 5048 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5049 // CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* 5050 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 5051 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5052 // CHECK20-NEXT: store i8* null, i8** [[TMP13]], align 4 5053 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5054 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 5055 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP15]], align 4 5056 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5057 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 5058 // CHECK20-NEXT: store i32 [[TMP6]], i32* [[TMP17]], align 4 5059 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5060 // CHECK20-NEXT: store i8* null, i8** [[TMP18]], align 4 5061 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5062 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 5063 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP20]], align 4 5064 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5065 // CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 5066 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[TMP22]], align 4 5067 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5068 // CHECK20-NEXT: store i8* null, i8** [[TMP23]], align 4 5069 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5070 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5071 // CHECK20-NEXT: [[TMP26:%.*]] = load i16, i16* [[DOTCAPTURE_EXPR_]], align 2 5072 // CHECK20-NEXT: [[TMP27:%.*]] = zext i16 [[TMP26]] to i32 5073 // CHECK20-NEXT: [[TMP28:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 3, i8** [[TMP24]], i8** [[TMP25]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP27]]) 5074 // CHECK20-NEXT: [[TMP29:%.*]] = icmp ne i32 [[TMP28]], 0 5075 // CHECK20-NEXT: br i1 [[TMP29]], label [[OMP_OFFLOAD_FAILED2:%.*]], label [[OMP_OFFLOAD_CONT3:%.*]] 5076 // CHECK20: omp_offload.failed2: 5077 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP4]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2]] 5078 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT3]] 5079 // CHECK20: omp_offload.cont3: 5080 // CHECK20-NEXT: [[TMP30:%.*]] = load i32, i32* [[A]], align 4 5081 // CHECK20-NEXT: ret i32 [[TMP30]] 5082 // 5083 // 5084 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 5085 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 5086 // CHECK20-NEXT: entry: 5087 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5088 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5089 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5090 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5091 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5092 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5093 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5094 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5095 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5096 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5097 // CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 5098 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 5099 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 5100 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 5101 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 5102 // CHECK20-NEXT: ret void 5103 // 5104 // 5105 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 5106 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 5107 // CHECK20-NEXT: entry: 5108 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5109 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5110 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5111 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5112 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5113 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5114 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5115 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5116 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5117 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 5118 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 5119 // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5120 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5121 // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 5122 // CHECK20-NEXT: ret void 5123 // 5124 // 5125 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 5126 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 5127 // CHECK20-NEXT: entry: 5128 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5129 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5130 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5131 // CHECK20-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5132 // CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 5133 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 5134 // CHECK20-NEXT: ret void 5135 // 5136 // 5137 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1 5138 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] { 5139 // CHECK20-NEXT: entry: 5140 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5141 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5142 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5143 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5144 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5145 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5146 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5147 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5148 // CHECK20-NEXT: store double 2.500000e+00, double* [[A]], align 4 5149 // CHECK20-NEXT: ret void 5150 // 5151 // 5152 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 5153 // CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 5154 // CHECK20-NEXT: entry: 5155 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5156 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5157 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5158 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5159 // CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 5160 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 5161 // CHECK20-NEXT: ret void 5162 // 5163 // 5164 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 5165 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 5166 // CHECK20-NEXT: entry: 5167 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5168 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5169 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5170 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5171 // CHECK20-NEXT: ret void 5172 // 5173 // 5174 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 5175 // CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 5176 // CHECK20-NEXT: entry: 5177 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5178 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5179 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5180 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5181 // CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 5182 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*)) 5183 // CHECK20-NEXT: ret void 5184 // 5185 // 5186 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 5187 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 5188 // CHECK20-NEXT: entry: 5189 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5190 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5191 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5192 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5193 // CHECK20-NEXT: ret void 5194 // 5195 // 5196 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 5197 // CHECK20-SAME: () #[[ATTR1]] { 5198 // CHECK20-NEXT: entry: 5199 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5200 // CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 5201 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*)) 5202 // CHECK20-NEXT: ret void 5203 // 5204 // 5205 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 5206 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] { 5207 // CHECK20-NEXT: entry: 5208 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5209 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5210 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5211 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5212 // CHECK20-NEXT: ret void 5213 // 5214 // 5215 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 5216 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 5217 // CHECK20-NEXT: entry: 5218 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5219 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5220 // CHECK20-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5221 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5222 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5223 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5224 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5225 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5226 // CHECK20-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5227 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 5228 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 5229 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 5230 // CHECK20-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 5231 // CHECK20-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 5232 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 5233 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 5234 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 5235 // CHECK20-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 5236 // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 5237 // CHECK20-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 5238 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 5239 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 5240 // CHECK20-NEXT: ret void 5241 // 5242 // 5243 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 5244 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] { 5245 // CHECK20-NEXT: entry: 5246 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5247 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5248 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5249 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5250 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5251 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5252 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5253 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5254 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 5255 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 5256 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 5257 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5258 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 5259 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5260 // CHECK20-NEXT: ret void 5261 // 5262 // 5263 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5264 // CHECK20-SAME: () #[[ATTR3:[0-9]+]] { 5265 // CHECK20-NEXT: entry: 5266 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 5267 // CHECK20-NEXT: ret void 5268 // 5269 // 5270 // CHECK21-LABEL: define {{[^@]+}}@_Z3bari 5271 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5272 // CHECK21-NEXT: entry: 5273 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5274 // CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 5275 // CHECK21-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 5276 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5277 // CHECK21-NEXT: store i32 0, i32* [[A]], align 4 5278 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5279 // CHECK21-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 5280 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5281 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5282 // CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5283 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5284 // CHECK21-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 5285 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5286 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5287 // CHECK21-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5288 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5289 // CHECK21-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 5290 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5291 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5292 // CHECK21-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5293 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5294 // CHECK21-NEXT: ret i32 [[TMP6]] 5295 // 5296 // 5297 // CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5298 // CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5299 // CHECK21-NEXT: entry: 5300 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5301 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5302 // CHECK21-NEXT: [[B:%.*]] = alloca i32, align 4 5303 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5304 // CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5305 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5306 // CHECK21-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5307 // CHECK21-NEXT: store i32 1, i32* [[B]], align 4 5308 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5309 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 5310 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 5311 // CHECK21-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 5312 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 5313 // CHECK21-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 5314 // CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5315 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5316 // CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8 5317 // CHECK21-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5318 // CHECK21-NEXT: store double 2.500000e+00, double* [[A2]], align 8 5319 // CHECK21-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5320 // CHECK21-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 5321 // CHECK21-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 5322 // CHECK21-NEXT: ret i32 [[CONV4]] 5323 // 5324 // 5325 // CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici 5326 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 5327 // CHECK21-NEXT: entry: 5328 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5329 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5330 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5331 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5332 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5333 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5334 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5335 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 5336 // CHECK21-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5337 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5338 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 5339 // CHECK21-NEXT: ret i32 [[ADD2]] 5340 // 5341 // 5342 // CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5343 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 5344 // CHECK21-NEXT: entry: 5345 // CHECK21-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5346 // CHECK21-NEXT: [[A:%.*]] = alloca i32, align 4 5347 // CHECK21-NEXT: [[B:%.*]] = alloca i16, align 2 5348 // CHECK21-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5349 // CHECK21-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5350 // CHECK21-NEXT: store i32 0, i32* [[A]], align 4 5351 // CHECK21-NEXT: store i16 1, i16* [[B]], align 2 5352 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 5353 // CHECK21-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 5354 // CHECK21-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 5355 // CHECK21-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5356 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 5357 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 5358 // CHECK21-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5359 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5360 // CHECK21-NEXT: ret i32 [[TMP3]] 5361 // 5362 // 5363 // CHECK22-LABEL: define {{[^@]+}}@_Z3bari 5364 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5365 // CHECK22-NEXT: entry: 5366 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5367 // CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 5368 // CHECK22-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 5369 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5370 // CHECK22-NEXT: store i32 0, i32* [[A]], align 4 5371 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5372 // CHECK22-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 5373 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5374 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5375 // CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5376 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5377 // CHECK22-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 5378 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5379 // CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5380 // CHECK22-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5381 // CHECK22-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5382 // CHECK22-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 5383 // CHECK22-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5384 // CHECK22-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5385 // CHECK22-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5386 // CHECK22-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5387 // CHECK22-NEXT: ret i32 [[TMP6]] 5388 // 5389 // 5390 // CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5391 // CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5392 // CHECK22-NEXT: entry: 5393 // CHECK22-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5394 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5395 // CHECK22-NEXT: [[B:%.*]] = alloca i32, align 4 5396 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5397 // CHECK22-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5398 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5399 // CHECK22-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5400 // CHECK22-NEXT: store i32 1, i32* [[B]], align 4 5401 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5402 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 5403 // CHECK22-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 5404 // CHECK22-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 5405 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 5406 // CHECK22-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 5407 // CHECK22-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5408 // CHECK22-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5409 // CHECK22-NEXT: store double [[ADD]], double* [[A]], align 8 5410 // CHECK22-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5411 // CHECK22-NEXT: store double 2.500000e+00, double* [[A2]], align 8 5412 // CHECK22-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5413 // CHECK22-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 5414 // CHECK22-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 5415 // CHECK22-NEXT: ret i32 [[CONV4]] 5416 // 5417 // 5418 // CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici 5419 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 5420 // CHECK22-NEXT: entry: 5421 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5422 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5423 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5424 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5425 // CHECK22-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5426 // CHECK22-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5427 // CHECK22-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5428 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 5429 // CHECK22-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5430 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5431 // CHECK22-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 5432 // CHECK22-NEXT: ret i32 [[ADD2]] 5433 // 5434 // 5435 // CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5436 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 5437 // CHECK22-NEXT: entry: 5438 // CHECK22-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5439 // CHECK22-NEXT: [[A:%.*]] = alloca i32, align 4 5440 // CHECK22-NEXT: [[B:%.*]] = alloca i16, align 2 5441 // CHECK22-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5442 // CHECK22-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5443 // CHECK22-NEXT: store i32 0, i32* [[A]], align 4 5444 // CHECK22-NEXT: store i16 1, i16* [[B]], align 2 5445 // CHECK22-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 5446 // CHECK22-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 5447 // CHECK22-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 5448 // CHECK22-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5449 // CHECK22-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 5450 // CHECK22-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 5451 // CHECK22-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5452 // CHECK22-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5453 // CHECK22-NEXT: ret i32 [[TMP3]] 5454 // 5455 // 5456 // CHECK23-LABEL: define {{[^@]+}}@_Z3bari 5457 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5458 // CHECK23-NEXT: entry: 5459 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5460 // CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 5461 // CHECK23-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 5462 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5463 // CHECK23-NEXT: store i32 0, i32* [[A]], align 4 5464 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5465 // CHECK23-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 5466 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5467 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5468 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5469 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5470 // CHECK23-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 5471 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5472 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5473 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5474 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5475 // CHECK23-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 5476 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5477 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5478 // CHECK23-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5479 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5480 // CHECK23-NEXT: ret i32 [[TMP6]] 5481 // 5482 // 5483 // CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5484 // CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5485 // CHECK23-NEXT: entry: 5486 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5487 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5488 // CHECK23-NEXT: [[B:%.*]] = alloca i32, align 4 5489 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5490 // CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5491 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5492 // CHECK23-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5493 // CHECK23-NEXT: store i32 1, i32* [[B]], align 4 5494 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5495 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 5496 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 5497 // CHECK23-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 5498 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 5499 // CHECK23-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 5500 // CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5501 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5502 // CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4 5503 // CHECK23-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5504 // CHECK23-NEXT: store double 2.500000e+00, double* [[A2]], align 4 5505 // CHECK23-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5506 // CHECK23-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 5507 // CHECK23-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 5508 // CHECK23-NEXT: ret i32 [[CONV4]] 5509 // 5510 // 5511 // CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici 5512 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 5513 // CHECK23-NEXT: entry: 5514 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5515 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5516 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5517 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5518 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5519 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5520 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5521 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 5522 // CHECK23-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5523 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5524 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 5525 // CHECK23-NEXT: ret i32 [[ADD2]] 5526 // 5527 // 5528 // CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5529 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 5530 // CHECK23-NEXT: entry: 5531 // CHECK23-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5532 // CHECK23-NEXT: [[A:%.*]] = alloca i32, align 4 5533 // CHECK23-NEXT: [[B:%.*]] = alloca i16, align 2 5534 // CHECK23-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5535 // CHECK23-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5536 // CHECK23-NEXT: store i32 0, i32* [[A]], align 4 5537 // CHECK23-NEXT: store i16 1, i16* [[B]], align 2 5538 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 5539 // CHECK23-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 5540 // CHECK23-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 5541 // CHECK23-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5542 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 5543 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 5544 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5545 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5546 // CHECK23-NEXT: ret i32 [[TMP3]] 5547 // 5548 // 5549 // CHECK24-LABEL: define {{[^@]+}}@_Z3bari 5550 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5551 // CHECK24-NEXT: entry: 5552 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5553 // CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 5554 // CHECK24-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 5555 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5556 // CHECK24-NEXT: store i32 0, i32* [[A]], align 4 5557 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5558 // CHECK24-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 5559 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5560 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5561 // CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5562 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5563 // CHECK24-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 5564 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5565 // CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5566 // CHECK24-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5567 // CHECK24-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5568 // CHECK24-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 5569 // CHECK24-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5570 // CHECK24-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5571 // CHECK24-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5572 // CHECK24-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 5573 // CHECK24-NEXT: ret i32 [[TMP6]] 5574 // 5575 // 5576 // CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 5577 // CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 5578 // CHECK24-NEXT: entry: 5579 // CHECK24-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5580 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5581 // CHECK24-NEXT: [[B:%.*]] = alloca i32, align 4 5582 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5583 // CHECK24-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5584 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5585 // CHECK24-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5586 // CHECK24-NEXT: store i32 1, i32* [[B]], align 4 5587 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5588 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 5589 // CHECK24-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 5590 // CHECK24-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 5591 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 5592 // CHECK24-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 5593 // CHECK24-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5594 // CHECK24-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 5595 // CHECK24-NEXT: store double [[ADD]], double* [[A]], align 4 5596 // CHECK24-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5597 // CHECK24-NEXT: store double 2.500000e+00, double* [[A2]], align 4 5598 // CHECK24-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 5599 // CHECK24-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 5600 // CHECK24-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 5601 // CHECK24-NEXT: ret i32 [[CONV4]] 5602 // 5603 // 5604 // CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici 5605 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 5606 // CHECK24-NEXT: entry: 5607 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5608 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5609 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 5610 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5611 // CHECK24-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5612 // CHECK24-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 5613 // CHECK24-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5614 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 5615 // CHECK24-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 5616 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5617 // CHECK24-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 5618 // CHECK24-NEXT: ret i32 [[ADD2]] 5619 // 5620 // 5621 // CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 5622 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 5623 // CHECK24-NEXT: entry: 5624 // CHECK24-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5625 // CHECK24-NEXT: [[A:%.*]] = alloca i32, align 4 5626 // CHECK24-NEXT: [[B:%.*]] = alloca i16, align 2 5627 // CHECK24-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 5628 // CHECK24-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5629 // CHECK24-NEXT: store i32 0, i32* [[A]], align 4 5630 // CHECK24-NEXT: store i16 1, i16* [[B]], align 2 5631 // CHECK24-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 5632 // CHECK24-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 5633 // CHECK24-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 5634 // CHECK24-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 5635 // CHECK24-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 5636 // CHECK24-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 5637 // CHECK24-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5638 // CHECK24-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5639 // CHECK24-NEXT: ret i32 [[TMP3]] 5640 // 5641 // 5642 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 5643 // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 5644 // CHECK25-NEXT: entry: 5645 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5646 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 5647 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5648 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5649 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5650 // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 5651 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5652 // CHECK25-NEXT: ret void 5653 // 5654 // 5655 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. 5656 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5657 // CHECK25-NEXT: entry: 5658 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5659 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5660 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5661 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5662 // CHECK25-NEXT: ret void 5663 // 5664 // 5665 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 5666 // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5667 // CHECK25-NEXT: entry: 5668 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5669 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5670 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5671 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5672 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5673 // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 5674 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 5675 // CHECK25-NEXT: ret void 5676 // 5677 // 5678 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 5679 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5680 // CHECK25-NEXT: entry: 5681 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5682 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5683 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5684 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5685 // CHECK25-NEXT: ret void 5686 // 5687 // 5688 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 5689 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5690 // CHECK25-NEXT: entry: 5691 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5692 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5693 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5694 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5695 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5696 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5697 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5698 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5699 // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5700 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5701 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5702 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 5703 // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 5704 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 5705 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 5706 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 5707 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 5708 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 5709 // CHECK25-NEXT: ret void 5710 // 5711 // 5712 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 5713 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 5714 // CHECK25-NEXT: entry: 5715 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5716 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5717 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5718 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5719 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5720 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5721 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5722 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5723 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5724 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5725 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5726 // CHECK25-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 5727 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 5728 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5729 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 5730 // CHECK25-NEXT: ret void 5731 // 5732 // 5733 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 5734 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 5735 // CHECK25-NEXT: entry: 5736 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5737 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5738 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5739 // CHECK25-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5740 // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 5741 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 5742 // CHECK25-NEXT: ret void 5743 // 5744 // 5745 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 5746 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 5747 // CHECK25-NEXT: entry: 5748 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5749 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5750 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5751 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5752 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5753 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5754 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5755 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5756 // CHECK25-NEXT: store double 2.500000e+00, double* [[A]], align 8 5757 // CHECK25-NEXT: ret void 5758 // 5759 // 5760 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 5761 // CHECK25-SAME: () #[[ATTR0]] { 5762 // CHECK25-NEXT: entry: 5763 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5764 // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 5765 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 5766 // CHECK25-NEXT: ret void 5767 // 5768 // 5769 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 5770 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5771 // CHECK25-NEXT: entry: 5772 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5773 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5774 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5775 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5776 // CHECK25-NEXT: ret void 5777 // 5778 // 5779 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 5780 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5781 // CHECK25-NEXT: entry: 5782 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5783 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5784 // CHECK25-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5785 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5786 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5787 // CHECK25-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5788 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5789 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5790 // CHECK25-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5791 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5792 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 5793 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 5794 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 5795 // CHECK25-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 5796 // CHECK25-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 5797 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 5798 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5799 // CHECK25-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 5800 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 5801 // CHECK25-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 5802 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 5803 // CHECK25-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 5804 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 5805 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 5806 // CHECK25-NEXT: ret void 5807 // 5808 // 5809 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 5810 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 5811 // CHECK25-NEXT: entry: 5812 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5813 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5814 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5815 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5816 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5817 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5818 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5819 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5820 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5821 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 5822 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 5823 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 5824 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5825 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 5826 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 5827 // CHECK25-NEXT: ret void 5828 // 5829 // 5830 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 5831 // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 5832 // CHECK26-NEXT: entry: 5833 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5834 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 5835 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5836 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5837 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5838 // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 5839 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5840 // CHECK26-NEXT: ret void 5841 // 5842 // 5843 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. 5844 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5845 // CHECK26-NEXT: entry: 5846 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5847 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5848 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5849 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5850 // CHECK26-NEXT: ret void 5851 // 5852 // 5853 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 5854 // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5855 // CHECK26-NEXT: entry: 5856 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5857 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5858 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5859 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5860 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5861 // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 5862 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 5863 // CHECK26-NEXT: ret void 5864 // 5865 // 5866 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 5867 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5868 // CHECK26-NEXT: entry: 5869 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5870 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5871 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5872 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5873 // CHECK26-NEXT: ret void 5874 // 5875 // 5876 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 5877 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5878 // CHECK26-NEXT: entry: 5879 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5880 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5881 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5882 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5883 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5884 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5885 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5886 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5887 // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5888 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5889 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 5890 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 8 5891 // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 5892 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 5893 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32* 5894 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV2]], align 4 5895 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[B_CASTED]], align 8 5896 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP4]]) 5897 // CHECK26-NEXT: ret void 5898 // 5899 // 5900 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 5901 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 5902 // CHECK26-NEXT: entry: 5903 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5904 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5905 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5906 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5907 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5908 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5909 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5910 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5911 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5912 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5913 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 5914 // CHECK26-NEXT: [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double 5915 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00 5916 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5917 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 5918 // CHECK26-NEXT: ret void 5919 // 5920 // 5921 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 5922 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 5923 // CHECK26-NEXT: entry: 5924 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5925 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5926 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5927 // CHECK26-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5928 // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 5929 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 5930 // CHECK26-NEXT: ret void 5931 // 5932 // 5933 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 5934 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 5935 // CHECK26-NEXT: entry: 5936 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5937 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5938 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5939 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5940 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5941 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5942 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5943 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5944 // CHECK26-NEXT: store double 2.500000e+00, double* [[A]], align 8 5945 // CHECK26-NEXT: ret void 5946 // 5947 // 5948 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 5949 // CHECK26-SAME: () #[[ATTR0]] { 5950 // CHECK26-NEXT: entry: 5951 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5952 // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 5953 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 5954 // CHECK26-NEXT: ret void 5955 // 5956 // 5957 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 5958 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 5959 // CHECK26-NEXT: entry: 5960 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5961 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5962 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5963 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5964 // CHECK26-NEXT: ret void 5965 // 5966 // 5967 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 5968 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 5969 // CHECK26-NEXT: entry: 5970 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5971 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5972 // CHECK26-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5973 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5974 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5975 // CHECK26-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 5976 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5977 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5978 // CHECK26-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5979 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5980 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 5981 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i16* 5982 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV2]], align 8 5983 // CHECK26-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 5984 // CHECK26-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 5985 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV]], align 8 5986 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5987 // CHECK26-NEXT: store i32 [[TMP3]], i32* [[CONV3]], align 4 5988 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[A_CASTED]], align 8 5989 // CHECK26-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV1]], align 8 5990 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i16* 5991 // CHECK26-NEXT: store i16 [[TMP5]], i16* [[CONV4]], align 2 5992 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 5993 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP4]], i64 [[TMP6]]) 5994 // CHECK26-NEXT: ret void 5995 // 5996 // 5997 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 5998 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] { 5999 // CHECK26-NEXT: entry: 6000 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6001 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6002 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6003 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6004 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6005 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6006 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6007 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6008 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6009 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16* 6010 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8 6011 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP0]] to i32 6012 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 6013 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]] 6014 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 8 6015 // CHECK26-NEXT: ret void 6016 // 6017 // 6018 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 6019 // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 6020 // CHECK27-NEXT: entry: 6021 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6022 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 6023 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6024 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6025 // CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 6026 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 6027 // CHECK27-NEXT: ret void 6028 // 6029 // 6030 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. 6031 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6032 // CHECK27-NEXT: entry: 6033 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6034 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6035 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6036 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6037 // CHECK27-NEXT: ret void 6038 // 6039 // 6040 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 6041 // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6042 // CHECK27-NEXT: entry: 6043 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6044 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6045 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6046 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6047 // CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 6048 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 6049 // CHECK27-NEXT: ret void 6050 // 6051 // 6052 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 6053 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6054 // CHECK27-NEXT: entry: 6055 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6056 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6057 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6058 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6059 // CHECK27-NEXT: ret void 6060 // 6061 // 6062 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 6063 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6064 // CHECK27-NEXT: entry: 6065 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6066 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6067 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6068 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6069 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6070 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6071 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6072 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6073 // CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6074 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6075 // CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 6076 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 6077 // CHECK27-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 6078 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 6079 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 6080 // CHECK27-NEXT: ret void 6081 // 6082 // 6083 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 6084 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 6085 // CHECK27-NEXT: entry: 6086 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6087 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6088 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6089 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6090 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6091 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6092 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6093 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6094 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6095 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 6096 // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 6097 // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6098 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6099 // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 6100 // CHECK27-NEXT: ret void 6101 // 6102 // 6103 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 6104 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 6105 // CHECK27-NEXT: entry: 6106 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6107 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6108 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6109 // CHECK27-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6110 // CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 6111 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 6112 // CHECK27-NEXT: ret void 6113 // 6114 // 6115 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 6116 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 6117 // CHECK27-NEXT: entry: 6118 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6119 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6120 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6121 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6122 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6123 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6124 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6125 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6126 // CHECK27-NEXT: store double 2.500000e+00, double* [[A]], align 4 6127 // CHECK27-NEXT: ret void 6128 // 6129 // 6130 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 6131 // CHECK27-SAME: () #[[ATTR0]] { 6132 // CHECK27-NEXT: entry: 6133 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6134 // CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 6135 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 6136 // CHECK27-NEXT: ret void 6137 // 6138 // 6139 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 6140 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6141 // CHECK27-NEXT: entry: 6142 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6143 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6144 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6145 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6146 // CHECK27-NEXT: ret void 6147 // 6148 // 6149 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 6150 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6151 // CHECK27-NEXT: entry: 6152 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6153 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6154 // CHECK27-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6155 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6156 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6157 // CHECK27-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6158 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6159 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6160 // CHECK27-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6161 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 6162 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 6163 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 6164 // CHECK27-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 6165 // CHECK27-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 6166 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 6167 // CHECK27-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 6168 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 6169 // CHECK27-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 6170 // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 6171 // CHECK27-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 6172 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 6173 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 6174 // CHECK27-NEXT: ret void 6175 // 6176 // 6177 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 6178 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 6179 // CHECK27-NEXT: entry: 6180 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6181 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6182 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6183 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6184 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6185 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6186 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6187 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6188 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 6189 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 6190 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 6191 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6192 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 6193 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 6194 // CHECK27-NEXT: ret void 6195 // 6196 // 6197 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104 6198 // CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] { 6199 // CHECK28-NEXT: entry: 6200 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6201 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 6202 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6203 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6204 // CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 6205 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 6206 // CHECK28-NEXT: ret void 6207 // 6208 // 6209 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. 6210 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6211 // CHECK28-NEXT: entry: 6212 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6213 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6214 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6215 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6216 // CHECK28-NEXT: ret void 6217 // 6218 // 6219 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108 6220 // CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6221 // CHECK28-NEXT: entry: 6222 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6223 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6224 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6225 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6226 // CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP1]]) 6227 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*)) 6228 // CHECK28-NEXT: ret void 6229 // 6230 // 6231 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 6232 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6233 // CHECK28-NEXT: entry: 6234 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6235 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6236 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6237 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6238 // CHECK28-NEXT: ret void 6239 // 6240 // 6241 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121 6242 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6243 // CHECK28-NEXT: entry: 6244 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6245 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6246 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6247 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6248 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6249 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6250 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6251 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6252 // CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6253 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6254 // CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 6255 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[B_ADDR]], align 4 6256 // CHECK28-NEXT: store i32 [[TMP3]], i32* [[B_CASTED]], align 4 6257 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_CASTED]], align 4 6258 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP4]]) 6259 // CHECK28-NEXT: ret void 6260 // 6261 // 6262 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 6263 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 6264 // CHECK28-NEXT: entry: 6265 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6266 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6267 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6268 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6269 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6270 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6271 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6272 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6273 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6274 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4 6275 // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP1]] to double 6276 // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6277 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6278 // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 6279 // CHECK28-NEXT: ret void 6280 // 6281 // 6282 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126 6283 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 6284 // CHECK28-NEXT: entry: 6285 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6286 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6287 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6288 // CHECK28-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6289 // CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1024) 6290 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]]) 6291 // CHECK28-NEXT: ret void 6292 // 6293 // 6294 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 6295 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] { 6296 // CHECK28-NEXT: entry: 6297 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6298 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6299 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6300 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6301 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6302 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6303 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6304 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6305 // CHECK28-NEXT: store double 2.500000e+00, double* [[A]], align 4 6306 // CHECK28-NEXT: ret void 6307 // 6308 // 6309 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l88 6310 // CHECK28-SAME: () #[[ATTR0]] { 6311 // CHECK28-NEXT: entry: 6312 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6313 // CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 20) 6314 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*)) 6315 // CHECK28-NEXT: ret void 6316 // 6317 // 6318 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 6319 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] { 6320 // CHECK28-NEXT: entry: 6321 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6322 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6323 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6324 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6325 // CHECK28-NEXT: ret void 6326 // 6327 // 6328 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93 6329 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 6330 // CHECK28-NEXT: entry: 6331 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6332 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6333 // CHECK28-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6334 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6335 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6336 // CHECK28-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]]) 6337 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6338 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6339 // CHECK28-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6340 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 6341 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i16* 6342 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 4 6343 // CHECK28-NEXT: [[TMP2:%.*]] = sext i16 [[TMP1]] to i32 6344 // CHECK28-NEXT: call void @__kmpc_push_num_threads(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 [[TMP2]]) 6345 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[A_ADDR]], align 4 6346 // CHECK28-NEXT: store i32 [[TMP3]], i32* [[A_CASTED]], align 4 6347 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_CASTED]], align 4 6348 // CHECK28-NEXT: [[TMP5:%.*]] = load i16, i16* [[CONV]], align 4 6349 // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[B_CASTED]] to i16* 6350 // CHECK28-NEXT: store i16 [[TMP5]], i16* [[CONV2]], align 2 6351 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 6352 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP4]], i32 [[TMP6]]) 6353 // CHECK28-NEXT: ret void 6354 // 6355 // 6356 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 6357 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] { 6358 // CHECK28-NEXT: entry: 6359 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6360 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6361 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6362 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6363 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6364 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6365 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6366 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6367 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16* 6368 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4 6369 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 6370 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6371 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]] 6372 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 6373 // CHECK28-NEXT: ret void 6374 // 6375 // 6376 // CHECK29-LABEL: define {{[^@]+}}@_Z3bari 6377 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6378 // CHECK29-NEXT: entry: 6379 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6380 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 6381 // CHECK29-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 6382 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6383 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 6384 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6385 // CHECK29-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 6386 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6387 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6388 // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6389 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6390 // CHECK29-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 6391 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6392 // CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6393 // CHECK29-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6394 // CHECK29-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6395 // CHECK29-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 6396 // CHECK29-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6397 // CHECK29-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6398 // CHECK29-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6399 // CHECK29-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6400 // CHECK29-NEXT: ret i32 [[TMP6]] 6401 // 6402 // 6403 // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6404 // CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6405 // CHECK29-NEXT: entry: 6406 // CHECK29-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6407 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6408 // CHECK29-NEXT: [[B:%.*]] = alloca i32, align 4 6409 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6410 // CHECK29-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6411 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6412 // CHECK29-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6413 // CHECK29-NEXT: store i32 1, i32* [[B]], align 4 6414 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6415 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 6416 // CHECK29-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 6417 // CHECK29-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 6418 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 6419 // CHECK29-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 6420 // CHECK29-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6421 // CHECK29-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6422 // CHECK29-NEXT: store double [[ADD]], double* [[A]], align 8 6423 // CHECK29-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6424 // CHECK29-NEXT: store double 2.500000e+00, double* [[A2]], align 8 6425 // CHECK29-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6426 // CHECK29-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 6427 // CHECK29-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 6428 // CHECK29-NEXT: ret i32 [[CONV4]] 6429 // 6430 // 6431 // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici 6432 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 6433 // CHECK29-NEXT: entry: 6434 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6435 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6436 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6437 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6438 // CHECK29-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6439 // CHECK29-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 6440 // CHECK29-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6441 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 6442 // CHECK29-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6443 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6444 // CHECK29-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 6445 // CHECK29-NEXT: ret i32 [[ADD2]] 6446 // 6447 // 6448 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6449 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 6450 // CHECK29-NEXT: entry: 6451 // CHECK29-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6452 // CHECK29-NEXT: [[A:%.*]] = alloca i32, align 4 6453 // CHECK29-NEXT: [[B:%.*]] = alloca i16, align 2 6454 // CHECK29-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 6455 // CHECK29-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6456 // CHECK29-NEXT: store i32 0, i32* [[A]], align 4 6457 // CHECK29-NEXT: store i16 1, i16* [[B]], align 2 6458 // CHECK29-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 6459 // CHECK29-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 6460 // CHECK29-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 6461 // CHECK29-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6462 // CHECK29-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 6463 // CHECK29-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 6464 // CHECK29-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6465 // CHECK29-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6466 // CHECK29-NEXT: ret i32 [[TMP3]] 6467 // 6468 // 6469 // CHECK30-LABEL: define {{[^@]+}}@_Z3bari 6470 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6471 // CHECK30-NEXT: entry: 6472 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6473 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 6474 // CHECK30-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 6475 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6476 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 6477 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6478 // CHECK30-NEXT: [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP0]]) 6479 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6480 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6481 // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6482 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6483 // CHECK30-NEXT: [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]]) 6484 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6485 // CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6486 // CHECK30-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6487 // CHECK30-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6488 // CHECK30-NEXT: [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]]) 6489 // CHECK30-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6490 // CHECK30-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6491 // CHECK30-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6492 // CHECK30-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6493 // CHECK30-NEXT: ret i32 [[TMP6]] 6494 // 6495 // 6496 // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6497 // CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6498 // CHECK30-NEXT: entry: 6499 // CHECK30-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6500 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6501 // CHECK30-NEXT: [[B:%.*]] = alloca i32, align 4 6502 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6503 // CHECK30-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6504 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6505 // CHECK30-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6506 // CHECK30-NEXT: store i32 1, i32* [[B]], align 4 6507 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6508 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 6509 // CHECK30-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 6510 // CHECK30-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 6511 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 6512 // CHECK30-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 6513 // CHECK30-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6514 // CHECK30-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6515 // CHECK30-NEXT: store double [[ADD]], double* [[A]], align 8 6516 // CHECK30-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6517 // CHECK30-NEXT: store double 2.500000e+00, double* [[A2]], align 8 6518 // CHECK30-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6519 // CHECK30-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 8 6520 // CHECK30-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 6521 // CHECK30-NEXT: ret i32 [[CONV4]] 6522 // 6523 // 6524 // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici 6525 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 6526 // CHECK30-NEXT: entry: 6527 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6528 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6529 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6530 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6531 // CHECK30-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6532 // CHECK30-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 6533 // CHECK30-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6534 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 6535 // CHECK30-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6536 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6537 // CHECK30-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 6538 // CHECK30-NEXT: ret i32 [[ADD2]] 6539 // 6540 // 6541 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6542 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 6543 // CHECK30-NEXT: entry: 6544 // CHECK30-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6545 // CHECK30-NEXT: [[A:%.*]] = alloca i32, align 4 6546 // CHECK30-NEXT: [[B:%.*]] = alloca i16, align 2 6547 // CHECK30-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 6548 // CHECK30-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6549 // CHECK30-NEXT: store i32 0, i32* [[A]], align 4 6550 // CHECK30-NEXT: store i16 1, i16* [[B]], align 2 6551 // CHECK30-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 6552 // CHECK30-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 6553 // CHECK30-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 6554 // CHECK30-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6555 // CHECK30-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 6556 // CHECK30-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 6557 // CHECK30-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6558 // CHECK30-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6559 // CHECK30-NEXT: ret i32 [[TMP3]] 6560 // 6561 // 6562 // CHECK31-LABEL: define {{[^@]+}}@_Z3bari 6563 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6564 // CHECK31-NEXT: entry: 6565 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6566 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 6567 // CHECK31-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6568 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6569 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 6570 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6571 // CHECK31-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 6572 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6573 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6574 // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6575 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6576 // CHECK31-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 6577 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6578 // CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6579 // CHECK31-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6580 // CHECK31-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6581 // CHECK31-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 6582 // CHECK31-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6583 // CHECK31-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6584 // CHECK31-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6585 // CHECK31-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6586 // CHECK31-NEXT: ret i32 [[TMP6]] 6587 // 6588 // 6589 // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6590 // CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6591 // CHECK31-NEXT: entry: 6592 // CHECK31-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6593 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6594 // CHECK31-NEXT: [[B:%.*]] = alloca i32, align 4 6595 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6596 // CHECK31-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6597 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6598 // CHECK31-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6599 // CHECK31-NEXT: store i32 1, i32* [[B]], align 4 6600 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6601 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 6602 // CHECK31-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 6603 // CHECK31-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 6604 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 6605 // CHECK31-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 6606 // CHECK31-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6607 // CHECK31-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6608 // CHECK31-NEXT: store double [[ADD]], double* [[A]], align 4 6609 // CHECK31-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6610 // CHECK31-NEXT: store double 2.500000e+00, double* [[A2]], align 4 6611 // CHECK31-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6612 // CHECK31-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 6613 // CHECK31-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 6614 // CHECK31-NEXT: ret i32 [[CONV4]] 6615 // 6616 // 6617 // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici 6618 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 6619 // CHECK31-NEXT: entry: 6620 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6621 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6622 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6623 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6624 // CHECK31-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6625 // CHECK31-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 6626 // CHECK31-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6627 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 6628 // CHECK31-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6629 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6630 // CHECK31-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 6631 // CHECK31-NEXT: ret i32 [[ADD2]] 6632 // 6633 // 6634 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6635 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 6636 // CHECK31-NEXT: entry: 6637 // CHECK31-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6638 // CHECK31-NEXT: [[A:%.*]] = alloca i32, align 4 6639 // CHECK31-NEXT: [[B:%.*]] = alloca i16, align 2 6640 // CHECK31-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 6641 // CHECK31-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6642 // CHECK31-NEXT: store i32 0, i32* [[A]], align 4 6643 // CHECK31-NEXT: store i16 1, i16* [[B]], align 2 6644 // CHECK31-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 6645 // CHECK31-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 6646 // CHECK31-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 6647 // CHECK31-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6648 // CHECK31-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 6649 // CHECK31-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 6650 // CHECK31-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6651 // CHECK31-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6652 // CHECK31-NEXT: ret i32 [[TMP3]] 6653 // 6654 // 6655 // CHECK32-LABEL: define {{[^@]+}}@_Z3bari 6656 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6657 // CHECK32-NEXT: entry: 6658 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6659 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 6660 // CHECK32-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6661 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6662 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 6663 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6664 // CHECK32-NEXT: [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP0]]) 6665 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6666 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6667 // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6668 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6669 // CHECK32-NEXT: [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]]) 6670 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6671 // CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6672 // CHECK32-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6673 // CHECK32-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6674 // CHECK32-NEXT: [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]]) 6675 // CHECK32-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6676 // CHECK32-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6677 // CHECK32-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6678 // CHECK32-NEXT: [[TMP6:%.*]] = load i32, i32* [[A]], align 4 6679 // CHECK32-NEXT: ret i32 [[TMP6]] 6680 // 6681 // 6682 // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6683 // CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6684 // CHECK32-NEXT: entry: 6685 // CHECK32-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6686 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6687 // CHECK32-NEXT: [[B:%.*]] = alloca i32, align 4 6688 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6689 // CHECK32-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6690 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6691 // CHECK32-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6692 // CHECK32-NEXT: store i32 1, i32* [[B]], align 4 6693 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6694 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[B]], align 4 6695 // CHECK32-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP0]], [[TMP1]] 6696 // CHECK32-NEXT: store i32 [[SUB]], i32* [[DOTCAPTURE_EXPR_]], align 4 6697 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[B]], align 4 6698 // CHECK32-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP2]] to double 6699 // CHECK32-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 6700 // CHECK32-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6701 // CHECK32-NEXT: store double [[ADD]], double* [[A]], align 4 6702 // CHECK32-NEXT: [[A2:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6703 // CHECK32-NEXT: store double 2.500000e+00, double* [[A2]], align 4 6704 // CHECK32-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 6705 // CHECK32-NEXT: [[TMP3:%.*]] = load double, double* [[A3]], align 4 6706 // CHECK32-NEXT: [[CONV4:%.*]] = fptosi double [[TMP3]] to i32 6707 // CHECK32-NEXT: ret i32 [[CONV4]] 6708 // 6709 // 6710 // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici 6711 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 6712 // CHECK32-NEXT: entry: 6713 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6714 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6715 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 6716 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6717 // CHECK32-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6718 // CHECK32-NEXT: store i32 [[TMP0]], i32* [[DOTCAPTURE_EXPR_]], align 4 6719 // CHECK32-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6720 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 32, [[TMP1]] 6721 // CHECK32-NEXT: store i32 [[ADD]], i32* [[DOTCAPTURE_EXPR_1]], align 4 6722 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6723 // CHECK32-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP2]], 1 6724 // CHECK32-NEXT: ret i32 [[ADD2]] 6725 // 6726 // 6727 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6728 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 6729 // CHECK32-NEXT: entry: 6730 // CHECK32-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6731 // CHECK32-NEXT: [[A:%.*]] = alloca i32, align 4 6732 // CHECK32-NEXT: [[B:%.*]] = alloca i16, align 2 6733 // CHECK32-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i16, align 2 6734 // CHECK32-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6735 // CHECK32-NEXT: store i32 0, i32* [[A]], align 4 6736 // CHECK32-NEXT: store i16 1, i16* [[B]], align 2 6737 // CHECK32-NEXT: [[TMP0:%.*]] = load i16, i16* [[B]], align 2 6738 // CHECK32-NEXT: store i16 [[TMP0]], i16* [[DOTCAPTURE_EXPR_]], align 2 6739 // CHECK32-NEXT: [[TMP1:%.*]] = load i16, i16* [[B]], align 2 6740 // CHECK32-NEXT: [[CONV:%.*]] = sext i16 [[TMP1]] to i32 6741 // CHECK32-NEXT: [[TMP2:%.*]] = load i32, i32* [[A]], align 4 6742 // CHECK32-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP2]], [[CONV]] 6743 // CHECK32-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6744 // CHECK32-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6745 // CHECK32-NEXT: ret i32 [[TMP3]] 6746 // 6747