1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
9 
10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6
13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8
16 
17 // Test target codegen - host bc file has to be created first.
18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9
20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10
22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11
24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12
26 
27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13
29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14
31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15
33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16
35 
36 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17
37 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
38 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18
39 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19
40 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
41 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20
42 
43 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21
44 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22
46 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23
47 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24
49 
50 // Test target codegen - host bc file has to be created first.
51 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25
53 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
54 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26
55 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27
57 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
58 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28
59 
60 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29
62 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30
64 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31
66 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32
68 
69 // expected-no-diagnostics
70 #ifndef HEADER
71 #define HEADER
72 
73 
74 
75 
76 // We have 6 target regions
77 
78 
79 
80 // Check target registration is registered as a Ctor.
81 
82 
83 template<typename tx>
84 tx ftemplate(int n) {
85   tx a = 0;
86 
87   #pragma omp target parallel if(parallel: 0)
88   {
89     a += 1;
90   }
91 
92   short b = 1;
93   #pragma omp target parallel if(parallel: 1)
94   {
95     a += b;
96   }
97 
98   return a;
99 }
100 
101 static
102 int fstatic(int n) {
103 
104   #pragma omp target parallel if(n>1)
105   {
106   }
107 
108   #pragma omp target parallel if(target: n-2>2)
109   {
110   }
111 
112   return n+1;
113 }
114 
115 struct S1 {
116   double a;
117 
118   int r1(int n){
119     int b = 1;
120 
121     #pragma omp target parallel if(parallel: n>3)
122     {
123       this->a = (double)b + 1.5;
124     }
125 
126     #pragma omp target parallel if(target: n>4) if(parallel: n>5)
127     {
128       this->a = 2.5;
129     }
130 
131     return (int)a;
132   }
133 };
134 
135 int bar(int n){
136   int a = 0;
137 
138   S1 S;
139   a += S.r1(n);
140 
141   a += fstatic(n);
142 
143   a += ftemplate<int>(n);
144 
145   return a;
146 }
147 
148 
149 
150 
151 
152 
153 
154 
155 
156 
157 
158 
159 
160 
161 // Check that the offloading functions are emitted and that the parallel function
162 // is appropriately guarded.
163 
164 
165 
166 
167 
168 
169 
170 
171 
172 
173 
174 
175 
176 
177 
178 
179 
180 
181 
182 
183 
184 #endif
185 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
186 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
187 // CHECK1-NEXT:  entry:
188 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
189 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
190 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
191 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
192 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
193 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
194 // CHECK1-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
195 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
196 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
197 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
198 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
199 // CHECK1-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
200 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
201 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
202 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
203 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
204 // CHECK1-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
205 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
206 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
207 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
208 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
209 // CHECK1-NEXT:    ret i32 [[TMP6]]
210 //
211 //
212 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
213 // CHECK1-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
214 // CHECK1-NEXT:  entry:
215 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
216 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
217 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
218 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
219 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
220 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
221 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
222 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
223 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
224 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1
225 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8
226 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8
227 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8
228 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8
229 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
230 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
231 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
232 // CHECK1-NEXT:    store i32 1, i32* [[B]], align 4
233 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
234 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
235 // CHECK1-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
236 // CHECK1-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
237 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
238 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
239 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV]], align 4
240 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8
241 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
242 // CHECK1-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
243 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
244 // CHECK1-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
245 // CHECK1-NEXT:    store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
246 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
247 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
248 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
249 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1**
250 // CHECK1-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8
251 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
252 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double**
253 // CHECK1-NEXT:    store double* [[A]], double** [[TMP8]], align 8
254 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
255 // CHECK1-NEXT:    store i8* null, i8** [[TMP9]], align 8
256 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
257 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
258 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP11]], align 8
259 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
260 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
261 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP13]], align 8
262 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
263 // CHECK1-NEXT:    store i8* null, i8** [[TMP14]], align 8
264 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
265 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
266 // CHECK1-NEXT:    store i64 [[TMP4]], i64* [[TMP16]], align 8
267 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
268 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
269 // CHECK1-NEXT:    store i64 [[TMP4]], i64* [[TMP18]], align 8
270 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
271 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
272 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
273 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
274 // CHECK1-NEXT:    [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
275 // CHECK1-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1
276 // CHECK1-NEXT:    [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1
277 // CHECK1-NEXT:    [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
278 // CHECK1-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
279 // CHECK1-NEXT:    br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
280 // CHECK1:       omp_offload.failed:
281 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR2:[0-9]+]]
282 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
283 // CHECK1:       omp_offload.cont:
284 // CHECK1-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
285 // CHECK1-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5
286 // CHECK1-NEXT:    [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8
287 // CHECK1-NEXT:    store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1
288 // CHECK1-NEXT:    [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1
289 // CHECK1-NEXT:    [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1
290 // CHECK1-NEXT:    [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8*
291 // CHECK1-NEXT:    [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8
292 // CHECK1-NEXT:    store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1
293 // CHECK1-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8
294 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4
295 // CHECK1-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4
296 // CHECK1-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
297 // CHECK1:       omp_if.then:
298 // CHECK1-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
299 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
300 // CHECK1-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1**
301 // CHECK1-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8
302 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
303 // CHECK1-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
304 // CHECK1-NEXT:    store double* [[A13]], double** [[TMP33]], align 8
305 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0
306 // CHECK1-NEXT:    store i8* null, i8** [[TMP34]], align 8
307 // CHECK1-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
308 // CHECK1-NEXT:    [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
309 // CHECK1-NEXT:    store i64 [[TMP28]], i64* [[TMP36]], align 8
310 // CHECK1-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
311 // CHECK1-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
312 // CHECK1-NEXT:    store i64 [[TMP28]], i64* [[TMP38]], align 8
313 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1
314 // CHECK1-NEXT:    store i8* null, i8** [[TMP39]], align 8
315 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
316 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
317 // CHECK1-NEXT:    [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1
318 // CHECK1-NEXT:    [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1
319 // CHECK1-NEXT:    [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1
320 // CHECK1-NEXT:    [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]])
321 // CHECK1-NEXT:    [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
322 // CHECK1-NEXT:    br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
323 // CHECK1:       omp_offload.failed18:
324 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]]
325 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT19]]
326 // CHECK1:       omp_offload.cont19:
327 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
328 // CHECK1:       omp_if.else:
329 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]]
330 // CHECK1-NEXT:    br label [[OMP_IF_END]]
331 // CHECK1:       omp_if.end:
332 // CHECK1-NEXT:    [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
333 // CHECK1-NEXT:    [[TMP46:%.*]] = load double, double* [[A20]], align 8
334 // CHECK1-NEXT:    [[CONV21:%.*]] = fptosi double [[TMP46]] to i32
335 // CHECK1-NEXT:    ret i32 [[CONV21]]
336 //
337 //
338 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
339 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
340 // CHECK1-NEXT:  entry:
341 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
342 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
343 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
344 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
345 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
346 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
347 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
348 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
349 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
350 // CHECK1-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
351 // CHECK1-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
352 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
353 // CHECK1-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
354 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
355 // CHECK1-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8
356 // CHECK1-NEXT:    store i8 [[FROMBOOL1]], i8* [[CONV]], align 1
357 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
358 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
359 // CHECK1-NEXT:    [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
360 // CHECK1-NEXT:    br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
361 // CHECK1:       omp_if.then:
362 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
363 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
364 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP5]], align 8
365 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
366 // CHECK1-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
367 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP7]], align 8
368 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
369 // CHECK1-NEXT:    store i8* null, i8** [[TMP8]], align 8
370 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
371 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
372 // CHECK1-NEXT:    [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
373 // CHECK1-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1
374 // CHECK1-NEXT:    [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
375 // CHECK1-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]])
376 // CHECK1-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
377 // CHECK1-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
378 // CHECK1:       omp_offload.failed:
379 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
380 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
381 // CHECK1:       omp_offload.cont:
382 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
383 // CHECK1:       omp_if.else:
384 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
385 // CHECK1-NEXT:    br label [[OMP_IF_END]]
386 // CHECK1:       omp_if.end:
387 // CHECK1-NEXT:    [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4
388 // CHECK1-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2
389 // CHECK1-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2
390 // CHECK1-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]]
391 // CHECK1:       omp_if.then5:
392 // CHECK1-NEXT:    [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
393 // CHECK1-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
394 // CHECK1-NEXT:    br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
395 // CHECK1:       omp_offload.failed6:
396 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
397 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT7]]
398 // CHECK1:       omp_offload.cont7:
399 // CHECK1-NEXT:    br label [[OMP_IF_END9:%.*]]
400 // CHECK1:       omp_if.else8:
401 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
402 // CHECK1-NEXT:    br label [[OMP_IF_END9]]
403 // CHECK1:       omp_if.end9:
404 // CHECK1-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
405 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], 1
406 // CHECK1-NEXT:    ret i32 [[ADD]]
407 //
408 //
409 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
410 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
411 // CHECK1-NEXT:  entry:
412 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
413 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
414 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
415 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
416 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
417 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
418 // CHECK1-NEXT:    [[B:%.*]] = alloca i16, align 2
419 // CHECK1-NEXT:    [[A_CASTED1:%.*]] = alloca i64, align 8
420 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
421 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8
422 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8
423 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8
424 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
425 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
426 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
427 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
428 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
429 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
430 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
431 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
432 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP3]], align 8
433 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
434 // CHECK1-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
435 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP5]], align 8
436 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
437 // CHECK1-NEXT:    store i8* null, i8** [[TMP6]], align 8
438 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
439 // CHECK1-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
440 // CHECK1-NEXT:    [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1)
441 // CHECK1-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
442 // CHECK1-NEXT:    br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
443 // CHECK1:       omp_offload.failed:
444 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR2]]
445 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
446 // CHECK1:       omp_offload.cont:
447 // CHECK1-NEXT:    store i16 1, i16* [[B]], align 2
448 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
449 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32*
450 // CHECK1-NEXT:    store i32 [[TMP11]], i32* [[CONV2]], align 4
451 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8
452 // CHECK1-NEXT:    [[TMP13:%.*]] = load i16, i16* [[B]], align 2
453 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
454 // CHECK1-NEXT:    store i16 [[TMP13]], i16* [[CONV3]], align 2
455 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8
456 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
457 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
458 // CHECK1-NEXT:    store i64 [[TMP12]], i64* [[TMP16]], align 8
459 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
460 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
461 // CHECK1-NEXT:    store i64 [[TMP12]], i64* [[TMP18]], align 8
462 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
463 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
464 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
465 // CHECK1-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
466 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP21]], align 8
467 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
468 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
469 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP23]], align 8
470 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
471 // CHECK1-NEXT:    store i8* null, i8** [[TMP24]], align 8
472 // CHECK1-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
473 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
474 // CHECK1-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
475 // CHECK1-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
476 // CHECK1-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
477 // CHECK1:       omp_offload.failed7:
478 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR2]]
479 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT8]]
480 // CHECK1:       omp_offload.cont8:
481 // CHECK1-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
482 // CHECK1-NEXT:    ret i32 [[TMP29]]
483 //
484 //
485 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
486 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
487 // CHECK1-NEXT:  entry:
488 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
489 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
490 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
491 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
492 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
493 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
494 // CHECK1-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
495 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
496 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
497 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
498 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
499 // CHECK1-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
500 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
501 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
502 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
503 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
504 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[CONV2]], align 4
505 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
506 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
507 // CHECK1-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
508 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
509 // CHECK1:       omp_if.then:
510 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
511 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
512 // CHECK1:       omp_if.else:
513 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
514 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
515 // CHECK1-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]]
516 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
517 // CHECK1-NEXT:    br label [[OMP_IF_END]]
518 // CHECK1:       omp_if.end:
519 // CHECK1-NEXT:    ret void
520 //
521 //
522 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
523 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
524 // CHECK1-NEXT:  entry:
525 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
526 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
527 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
528 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
529 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
530 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
531 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
532 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
533 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
534 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
535 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
536 // CHECK1-NEXT:    [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
537 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
538 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
539 // CHECK1-NEXT:    store double [[ADD]], double* [[A]], align 8
540 // CHECK1-NEXT:    ret void
541 //
542 //
543 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
544 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
545 // CHECK1-NEXT:  entry:
546 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
547 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
548 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
549 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
550 // CHECK1-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
551 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
552 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
553 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
554 // CHECK1-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
555 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
556 // CHECK1-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
557 // CHECK1-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
558 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
559 // CHECK1:       omp_if.then:
560 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
561 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
562 // CHECK1:       omp_if.else:
563 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
564 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
565 // CHECK1-NEXT:    call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]]
566 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
567 // CHECK1-NEXT:    br label [[OMP_IF_END]]
568 // CHECK1:       omp_if.end:
569 // CHECK1-NEXT:    ret void
570 //
571 //
572 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1
573 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
574 // CHECK1-NEXT:  entry:
575 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
576 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
577 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
578 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
579 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
580 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
581 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
582 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
583 // CHECK1-NEXT:    store double 2.500000e+00, double* [[A]], align 8
584 // CHECK1-NEXT:    ret void
585 //
586 //
587 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
588 // CHECK1-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
589 // CHECK1-NEXT:  entry:
590 // CHECK1-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
591 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
592 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
593 // CHECK1-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
594 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
595 // CHECK1-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
596 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
597 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
598 // CHECK1-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
599 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
600 // CHECK1:       omp_if.then:
601 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
602 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
603 // CHECK1:       omp_if.else:
604 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
605 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
606 // CHECK1-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
607 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
608 // CHECK1-NEXT:    br label [[OMP_IF_END]]
609 // CHECK1:       omp_if.end:
610 // CHECK1-NEXT:    ret void
611 //
612 //
613 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
614 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
615 // CHECK1-NEXT:  entry:
616 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
617 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
618 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
619 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
620 // CHECK1-NEXT:    ret void
621 //
622 //
623 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
624 // CHECK1-SAME: () #[[ATTR1]] {
625 // CHECK1-NEXT:  entry:
626 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
627 // CHECK1-NEXT:    ret void
628 //
629 //
630 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
631 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
632 // CHECK1-NEXT:  entry:
633 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
634 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
635 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
636 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
637 // CHECK1-NEXT:    ret void
638 //
639 //
640 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
641 // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR1]] {
642 // CHECK1-NEXT:  entry:
643 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
644 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
645 // CHECK1-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
646 // CHECK1-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
647 // CHECK1-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
648 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
649 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
650 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
651 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
652 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
653 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV1]], align 4
654 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
655 // CHECK1-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
656 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
657 // CHECK1-NEXT:    call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]]
658 // CHECK1-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
659 // CHECK1-NEXT:    ret void
660 //
661 //
662 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8
663 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
664 // CHECK1-NEXT:  entry:
665 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
666 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
667 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
668 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
669 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
670 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
671 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
672 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
673 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
674 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
675 // CHECK1-NEXT:    ret void
676 //
677 //
678 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
679 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
680 // CHECK1-NEXT:  entry:
681 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
682 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
683 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
684 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
685 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
686 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
687 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
688 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
689 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
690 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
691 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
692 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
693 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
694 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
695 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
696 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
697 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
698 // CHECK1-NEXT:    ret void
699 //
700 //
701 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
702 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
703 // CHECK1-NEXT:  entry:
704 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
705 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
706 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
707 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
708 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
709 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
710 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
711 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
712 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
713 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
714 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
715 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
716 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
717 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
718 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
719 // CHECK1-NEXT:    ret void
720 //
721 //
722 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
723 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] {
724 // CHECK1-NEXT:  entry:
725 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
726 // CHECK1-NEXT:    ret void
727 //
728 //
729 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari
730 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
731 // CHECK2-NEXT:  entry:
732 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
733 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
734 // CHECK2-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
735 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
736 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
737 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
738 // CHECK2-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
739 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
740 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
741 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
742 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
743 // CHECK2-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
744 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
745 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
746 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
747 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
748 // CHECK2-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
749 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
750 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
751 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
752 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
753 // CHECK2-NEXT:    ret i32 [[TMP6]]
754 //
755 //
756 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
757 // CHECK2-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
758 // CHECK2-NEXT:  entry:
759 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
760 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
761 // CHECK2-NEXT:    [[B:%.*]] = alloca i32, align 4
762 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
763 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
764 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
765 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
766 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
767 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
768 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1
769 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8
770 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8
771 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8
772 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8
773 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
774 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
775 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
776 // CHECK2-NEXT:    store i32 1, i32* [[B]], align 4
777 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
778 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
779 // CHECK2-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
780 // CHECK2-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
781 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
782 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
783 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV]], align 4
784 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8
785 // CHECK2-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
786 // CHECK2-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
787 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
788 // CHECK2-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
789 // CHECK2-NEXT:    store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
790 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
791 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
792 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
793 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1**
794 // CHECK2-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8
795 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
796 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double**
797 // CHECK2-NEXT:    store double* [[A]], double** [[TMP8]], align 8
798 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
799 // CHECK2-NEXT:    store i8* null, i8** [[TMP9]], align 8
800 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
801 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
802 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP11]], align 8
803 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
804 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
805 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP13]], align 8
806 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
807 // CHECK2-NEXT:    store i8* null, i8** [[TMP14]], align 8
808 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
809 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
810 // CHECK2-NEXT:    store i64 [[TMP4]], i64* [[TMP16]], align 8
811 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
812 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
813 // CHECK2-NEXT:    store i64 [[TMP4]], i64* [[TMP18]], align 8
814 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
815 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
816 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
817 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
818 // CHECK2-NEXT:    [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
819 // CHECK2-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1
820 // CHECK2-NEXT:    [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1
821 // CHECK2-NEXT:    [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
822 // CHECK2-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
823 // CHECK2-NEXT:    br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
824 // CHECK2:       omp_offload.failed:
825 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR2:[0-9]+]]
826 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
827 // CHECK2:       omp_offload.cont:
828 // CHECK2-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
829 // CHECK2-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5
830 // CHECK2-NEXT:    [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8
831 // CHECK2-NEXT:    store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1
832 // CHECK2-NEXT:    [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1
833 // CHECK2-NEXT:    [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1
834 // CHECK2-NEXT:    [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8*
835 // CHECK2-NEXT:    [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8
836 // CHECK2-NEXT:    store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1
837 // CHECK2-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8
838 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4
839 // CHECK2-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4
840 // CHECK2-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
841 // CHECK2:       omp_if.then:
842 // CHECK2-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
843 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
844 // CHECK2-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1**
845 // CHECK2-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8
846 // CHECK2-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
847 // CHECK2-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
848 // CHECK2-NEXT:    store double* [[A13]], double** [[TMP33]], align 8
849 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0
850 // CHECK2-NEXT:    store i8* null, i8** [[TMP34]], align 8
851 // CHECK2-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
852 // CHECK2-NEXT:    [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
853 // CHECK2-NEXT:    store i64 [[TMP28]], i64* [[TMP36]], align 8
854 // CHECK2-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
855 // CHECK2-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
856 // CHECK2-NEXT:    store i64 [[TMP28]], i64* [[TMP38]], align 8
857 // CHECK2-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1
858 // CHECK2-NEXT:    store i8* null, i8** [[TMP39]], align 8
859 // CHECK2-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
860 // CHECK2-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
861 // CHECK2-NEXT:    [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1
862 // CHECK2-NEXT:    [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1
863 // CHECK2-NEXT:    [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1
864 // CHECK2-NEXT:    [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]])
865 // CHECK2-NEXT:    [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
866 // CHECK2-NEXT:    br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
867 // CHECK2:       omp_offload.failed18:
868 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]]
869 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT19]]
870 // CHECK2:       omp_offload.cont19:
871 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
872 // CHECK2:       omp_if.else:
873 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]]
874 // CHECK2-NEXT:    br label [[OMP_IF_END]]
875 // CHECK2:       omp_if.end:
876 // CHECK2-NEXT:    [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
877 // CHECK2-NEXT:    [[TMP46:%.*]] = load double, double* [[A20]], align 8
878 // CHECK2-NEXT:    [[CONV21:%.*]] = fptosi double [[TMP46]] to i32
879 // CHECK2-NEXT:    ret i32 [[CONV21]]
880 //
881 //
882 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
883 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
884 // CHECK2-NEXT:  entry:
885 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
886 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
887 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
888 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
889 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
890 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
891 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
892 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
893 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
894 // CHECK2-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
895 // CHECK2-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
896 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
897 // CHECK2-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
898 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
899 // CHECK2-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8
900 // CHECK2-NEXT:    store i8 [[FROMBOOL1]], i8* [[CONV]], align 1
901 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
902 // CHECK2-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
903 // CHECK2-NEXT:    [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
904 // CHECK2-NEXT:    br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
905 // CHECK2:       omp_if.then:
906 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
907 // CHECK2-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
908 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP5]], align 8
909 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
910 // CHECK2-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
911 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP7]], align 8
912 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
913 // CHECK2-NEXT:    store i8* null, i8** [[TMP8]], align 8
914 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
915 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
916 // CHECK2-NEXT:    [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
917 // CHECK2-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1
918 // CHECK2-NEXT:    [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
919 // CHECK2-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]])
920 // CHECK2-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
921 // CHECK2-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
922 // CHECK2:       omp_offload.failed:
923 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
924 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
925 // CHECK2:       omp_offload.cont:
926 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
927 // CHECK2:       omp_if.else:
928 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
929 // CHECK2-NEXT:    br label [[OMP_IF_END]]
930 // CHECK2:       omp_if.end:
931 // CHECK2-NEXT:    [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4
932 // CHECK2-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2
933 // CHECK2-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2
934 // CHECK2-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]]
935 // CHECK2:       omp_if.then5:
936 // CHECK2-NEXT:    [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
937 // CHECK2-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
938 // CHECK2-NEXT:    br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
939 // CHECK2:       omp_offload.failed6:
940 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
941 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT7]]
942 // CHECK2:       omp_offload.cont7:
943 // CHECK2-NEXT:    br label [[OMP_IF_END9:%.*]]
944 // CHECK2:       omp_if.else8:
945 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
946 // CHECK2-NEXT:    br label [[OMP_IF_END9]]
947 // CHECK2:       omp_if.end9:
948 // CHECK2-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
949 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], 1
950 // CHECK2-NEXT:    ret i32 [[ADD]]
951 //
952 //
953 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
954 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
955 // CHECK2-NEXT:  entry:
956 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
957 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
958 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
959 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
960 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
961 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
962 // CHECK2-NEXT:    [[B:%.*]] = alloca i16, align 2
963 // CHECK2-NEXT:    [[A_CASTED1:%.*]] = alloca i64, align 8
964 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
965 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8
966 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8
967 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8
968 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
969 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
970 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
971 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
972 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
973 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
974 // CHECK2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
975 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
976 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP3]], align 8
977 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
978 // CHECK2-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
979 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP5]], align 8
980 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
981 // CHECK2-NEXT:    store i8* null, i8** [[TMP6]], align 8
982 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
983 // CHECK2-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
984 // CHECK2-NEXT:    [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1)
985 // CHECK2-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
986 // CHECK2-NEXT:    br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
987 // CHECK2:       omp_offload.failed:
988 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR2]]
989 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
990 // CHECK2:       omp_offload.cont:
991 // CHECK2-NEXT:    store i16 1, i16* [[B]], align 2
992 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
993 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32*
994 // CHECK2-NEXT:    store i32 [[TMP11]], i32* [[CONV2]], align 4
995 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8
996 // CHECK2-NEXT:    [[TMP13:%.*]] = load i16, i16* [[B]], align 2
997 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
998 // CHECK2-NEXT:    store i16 [[TMP13]], i16* [[CONV3]], align 2
999 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8
1000 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
1001 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
1002 // CHECK2-NEXT:    store i64 [[TMP12]], i64* [[TMP16]], align 8
1003 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
1004 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
1005 // CHECK2-NEXT:    store i64 [[TMP12]], i64* [[TMP18]], align 8
1006 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
1007 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
1008 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
1009 // CHECK2-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
1010 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP21]], align 8
1011 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
1012 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
1013 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP23]], align 8
1014 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
1015 // CHECK2-NEXT:    store i8* null, i8** [[TMP24]], align 8
1016 // CHECK2-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
1017 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
1018 // CHECK2-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1019 // CHECK2-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1020 // CHECK2-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
1021 // CHECK2:       omp_offload.failed7:
1022 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR2]]
1023 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT8]]
1024 // CHECK2:       omp_offload.cont8:
1025 // CHECK2-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
1026 // CHECK2-NEXT:    ret i32 [[TMP29]]
1027 //
1028 //
1029 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
1030 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
1031 // CHECK2-NEXT:  entry:
1032 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1033 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1034 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1035 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1036 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1037 // CHECK2-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1038 // CHECK2-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1039 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1040 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1041 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1042 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1043 // CHECK2-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1044 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1045 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
1046 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
1047 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1048 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[CONV2]], align 4
1049 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
1050 // CHECK2-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
1051 // CHECK2-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
1052 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1053 // CHECK2:       omp_if.then:
1054 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
1055 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
1056 // CHECK2:       omp_if.else:
1057 // CHECK2-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1058 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1059 // CHECK2-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]]
1060 // CHECK2-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1061 // CHECK2-NEXT:    br label [[OMP_IF_END]]
1062 // CHECK2:       omp_if.end:
1063 // CHECK2-NEXT:    ret void
1064 //
1065 //
1066 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
1067 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
1068 // CHECK2-NEXT:  entry:
1069 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1070 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1071 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1072 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1073 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1074 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1075 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1076 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1077 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1078 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1079 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1080 // CHECK2-NEXT:    [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
1081 // CHECK2-NEXT:    [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
1082 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1083 // CHECK2-NEXT:    store double [[ADD]], double* [[A]], align 8
1084 // CHECK2-NEXT:    ret void
1085 //
1086 //
1087 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
1088 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
1089 // CHECK2-NEXT:  entry:
1090 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1091 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1092 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1093 // CHECK2-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1094 // CHECK2-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1095 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1096 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1097 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1098 // CHECK2-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1099 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
1100 // CHECK2-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
1101 // CHECK2-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
1102 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1103 // CHECK2:       omp_if.then:
1104 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
1105 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
1106 // CHECK2:       omp_if.else:
1107 // CHECK2-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1108 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1109 // CHECK2-NEXT:    call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]]
1110 // CHECK2-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1111 // CHECK2-NEXT:    br label [[OMP_IF_END]]
1112 // CHECK2:       omp_if.end:
1113 // CHECK2-NEXT:    ret void
1114 //
1115 //
1116 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1
1117 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
1118 // CHECK2-NEXT:  entry:
1119 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1120 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1121 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1122 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1123 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1124 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1125 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1126 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1127 // CHECK2-NEXT:    store double 2.500000e+00, double* [[A]], align 8
1128 // CHECK2-NEXT:    ret void
1129 //
1130 //
1131 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
1132 // CHECK2-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
1133 // CHECK2-NEXT:  entry:
1134 // CHECK2-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
1135 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1136 // CHECK2-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1137 // CHECK2-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1138 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1139 // CHECK2-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
1140 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
1141 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
1142 // CHECK2-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
1143 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1144 // CHECK2:       omp_if.then:
1145 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
1146 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
1147 // CHECK2:       omp_if.else:
1148 // CHECK2-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1149 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1150 // CHECK2-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
1151 // CHECK2-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1152 // CHECK2-NEXT:    br label [[OMP_IF_END]]
1153 // CHECK2:       omp_if.end:
1154 // CHECK2-NEXT:    ret void
1155 //
1156 //
1157 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
1158 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
1159 // CHECK2-NEXT:  entry:
1160 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1161 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1162 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1163 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1164 // CHECK2-NEXT:    ret void
1165 //
1166 //
1167 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
1168 // CHECK2-SAME: () #[[ATTR1]] {
1169 // CHECK2-NEXT:  entry:
1170 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
1171 // CHECK2-NEXT:    ret void
1172 //
1173 //
1174 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
1175 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
1176 // CHECK2-NEXT:  entry:
1177 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1178 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1179 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1180 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1181 // CHECK2-NEXT:    ret void
1182 //
1183 //
1184 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
1185 // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR1]] {
1186 // CHECK2-NEXT:  entry:
1187 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1188 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1189 // CHECK2-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1190 // CHECK2-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1191 // CHECK2-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1192 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1193 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1194 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1195 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1196 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1197 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV1]], align 4
1198 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1199 // CHECK2-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1200 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1201 // CHECK2-NEXT:    call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]]
1202 // CHECK2-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1203 // CHECK2-NEXT:    ret void
1204 //
1205 //
1206 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8
1207 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
1208 // CHECK2-NEXT:  entry:
1209 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1210 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1211 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1212 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1213 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1214 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1215 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1216 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1217 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1218 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
1219 // CHECK2-NEXT:    ret void
1220 //
1221 //
1222 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
1223 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
1224 // CHECK2-NEXT:  entry:
1225 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1226 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1227 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1228 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1229 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1230 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1231 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1232 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
1233 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1234 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1235 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
1236 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1237 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
1238 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
1239 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
1240 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
1241 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
1242 // CHECK2-NEXT:    ret void
1243 //
1244 //
1245 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
1246 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
1247 // CHECK2-NEXT:  entry:
1248 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1249 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1250 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1251 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1252 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1253 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1254 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1255 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1256 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1257 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
1258 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
1259 // CHECK2-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
1260 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1261 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
1262 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
1263 // CHECK2-NEXT:    ret void
1264 //
1265 //
1266 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1267 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] {
1268 // CHECK2-NEXT:  entry:
1269 // CHECK2-NEXT:    call void @__tgt_register_requires(i64 1)
1270 // CHECK2-NEXT:    ret void
1271 //
1272 //
1273 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
1274 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
1275 // CHECK3-NEXT:  entry:
1276 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1277 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
1278 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
1279 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1280 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
1281 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1282 // CHECK3-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
1283 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1284 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1285 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
1286 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1287 // CHECK3-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
1288 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1289 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1290 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
1291 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1292 // CHECK3-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
1293 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1294 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1295 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
1296 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
1297 // CHECK3-NEXT:    ret i32 [[TMP6]]
1298 //
1299 //
1300 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1301 // CHECK3-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1302 // CHECK3-NEXT:  entry:
1303 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
1304 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1305 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
1306 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1307 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1308 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
1309 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
1310 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
1311 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
1312 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1
1313 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4
1314 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4
1315 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4
1316 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4
1317 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
1318 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1319 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
1320 // CHECK3-NEXT:    store i32 1, i32* [[B]], align 4
1321 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1322 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
1323 // CHECK3-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
1324 // CHECK3-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
1325 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
1326 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[B_CASTED]], align 4
1327 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4
1328 // CHECK3-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1329 // CHECK3-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
1330 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
1331 // CHECK3-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
1332 // CHECK3-NEXT:    store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
1333 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1334 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1335 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1336 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1**
1337 // CHECK3-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4
1338 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1339 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double**
1340 // CHECK3-NEXT:    store double* [[A]], double** [[TMP8]], align 4
1341 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1342 // CHECK3-NEXT:    store i8* null, i8** [[TMP9]], align 4
1343 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1344 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
1345 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[TMP11]], align 4
1346 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1347 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
1348 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[TMP13]], align 4
1349 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1350 // CHECK3-NEXT:    store i8* null, i8** [[TMP14]], align 4
1351 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1352 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
1353 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[TMP16]], align 4
1354 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1355 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
1356 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[TMP18]], align 4
1357 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1358 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
1359 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1360 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1361 // CHECK3-NEXT:    [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1362 // CHECK3-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1
1363 // CHECK3-NEXT:    [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
1364 // CHECK3-NEXT:    [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
1365 // CHECK3-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
1366 // CHECK3-NEXT:    br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1367 // CHECK3:       omp_offload.failed:
1368 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR2:[0-9]+]]
1369 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1370 // CHECK3:       omp_offload.cont:
1371 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
1372 // CHECK3-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5
1373 // CHECK3-NEXT:    [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8
1374 // CHECK3-NEXT:    store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1
1375 // CHECK3-NEXT:    [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1
1376 // CHECK3-NEXT:    [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1
1377 // CHECK3-NEXT:    [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8*
1378 // CHECK3-NEXT:    [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8
1379 // CHECK3-NEXT:    store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1
1380 // CHECK3-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4
1381 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4
1382 // CHECK3-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4
1383 // CHECK3-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1384 // CHECK3:       omp_if.then:
1385 // CHECK3-NEXT:    [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
1386 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
1387 // CHECK3-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1**
1388 // CHECK3-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4
1389 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
1390 // CHECK3-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
1391 // CHECK3-NEXT:    store double* [[A12]], double** [[TMP33]], align 4
1392 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
1393 // CHECK3-NEXT:    store i8* null, i8** [[TMP34]], align 4
1394 // CHECK3-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
1395 // CHECK3-NEXT:    [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32*
1396 // CHECK3-NEXT:    store i32 [[TMP28]], i32* [[TMP36]], align 4
1397 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
1398 // CHECK3-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32*
1399 // CHECK3-NEXT:    store i32 [[TMP28]], i32* [[TMP38]], align 4
1400 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1
1401 // CHECK3-NEXT:    store i8* null, i8** [[TMP39]], align 4
1402 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
1403 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
1404 // CHECK3-NEXT:    [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1
1405 // CHECK3-NEXT:    [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1
1406 // CHECK3-NEXT:    [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1
1407 // CHECK3-NEXT:    [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]])
1408 // CHECK3-NEXT:    [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
1409 // CHECK3-NEXT:    br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
1410 // CHECK3:       omp_offload.failed17:
1411 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]]
1412 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
1413 // CHECK3:       omp_offload.cont18:
1414 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1415 // CHECK3:       omp_if.else:
1416 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]]
1417 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1418 // CHECK3:       omp_if.end:
1419 // CHECK3-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
1420 // CHECK3-NEXT:    [[TMP46:%.*]] = load double, double* [[A19]], align 4
1421 // CHECK3-NEXT:    [[CONV20:%.*]] = fptosi double [[TMP46]] to i32
1422 // CHECK3-NEXT:    ret i32 [[CONV20]]
1423 //
1424 //
1425 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
1426 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
1427 // CHECK3-NEXT:  entry:
1428 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1429 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1430 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
1431 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
1432 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
1433 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
1434 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1435 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1436 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
1437 // CHECK3-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
1438 // CHECK3-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
1439 // CHECK3-NEXT:    [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1440 // CHECK3-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
1441 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
1442 // CHECK3-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8
1443 // CHECK3-NEXT:    store i8 [[FROMBOOL1]], i8* [[CONV]], align 1
1444 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1445 // CHECK3-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1446 // CHECK3-NEXT:    [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
1447 // CHECK3-NEXT:    br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1448 // CHECK3:       omp_if.then:
1449 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1450 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
1451 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[TMP5]], align 4
1452 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1453 // CHECK3-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
1454 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[TMP7]], align 4
1455 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1456 // CHECK3-NEXT:    store i8* null, i8** [[TMP8]], align 4
1457 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1458 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1459 // CHECK3-NEXT:    [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1460 // CHECK3-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1
1461 // CHECK3-NEXT:    [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
1462 // CHECK3-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]])
1463 // CHECK3-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1464 // CHECK3-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1465 // CHECK3:       omp_offload.failed:
1466 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
1467 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1468 // CHECK3:       omp_offload.cont:
1469 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1470 // CHECK3:       omp_if.else:
1471 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
1472 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1473 // CHECK3:       omp_if.end:
1474 // CHECK3-NEXT:    [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4
1475 // CHECK3-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2
1476 // CHECK3-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2
1477 // CHECK3-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]]
1478 // CHECK3:       omp_if.then5:
1479 // CHECK3-NEXT:    [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
1480 // CHECK3-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
1481 // CHECK3-NEXT:    br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
1482 // CHECK3:       omp_offload.failed6:
1483 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
1484 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT7]]
1485 // CHECK3:       omp_offload.cont7:
1486 // CHECK3-NEXT:    br label [[OMP_IF_END9:%.*]]
1487 // CHECK3:       omp_if.else8:
1488 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
1489 // CHECK3-NEXT:    br label [[OMP_IF_END9]]
1490 // CHECK3:       omp_if.end9:
1491 // CHECK3-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
1492 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], 1
1493 // CHECK3-NEXT:    ret i32 [[ADD]]
1494 //
1495 //
1496 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1497 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
1498 // CHECK3-NEXT:  entry:
1499 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1500 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
1501 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1502 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
1503 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
1504 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
1505 // CHECK3-NEXT:    [[B:%.*]] = alloca i16, align 2
1506 // CHECK3-NEXT:    [[A_CASTED1:%.*]] = alloca i32, align 4
1507 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1508 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4
1509 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4
1510 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4
1511 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1512 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
1513 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1514 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
1515 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
1516 // CHECK3-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1517 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
1518 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP3]], align 4
1519 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1520 // CHECK3-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
1521 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP5]], align 4
1522 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1523 // CHECK3-NEXT:    store i8* null, i8** [[TMP6]], align 4
1524 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1525 // CHECK3-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1526 // CHECK3-NEXT:    [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1)
1527 // CHECK3-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
1528 // CHECK3-NEXT:    br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1529 // CHECK3:       omp_offload.failed:
1530 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR2]]
1531 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1532 // CHECK3:       omp_offload.cont:
1533 // CHECK3-NEXT:    store i16 1, i16* [[B]], align 2
1534 // CHECK3-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
1535 // CHECK3-NEXT:    store i32 [[TMP11]], i32* [[A_CASTED1]], align 4
1536 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4
1537 // CHECK3-NEXT:    [[TMP13:%.*]] = load i16, i16* [[B]], align 2
1538 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
1539 // CHECK3-NEXT:    store i16 [[TMP13]], i16* [[CONV]], align 2
1540 // CHECK3-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4
1541 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
1542 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
1543 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP16]], align 4
1544 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
1545 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
1546 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP18]], align 4
1547 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
1548 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
1549 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
1550 // CHECK3-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
1551 // CHECK3-NEXT:    store i32 [[TMP14]], i32* [[TMP21]], align 4
1552 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
1553 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
1554 // CHECK3-NEXT:    store i32 [[TMP14]], i32* [[TMP23]], align 4
1555 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
1556 // CHECK3-NEXT:    store i8* null, i8** [[TMP24]], align 4
1557 // CHECK3-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
1558 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
1559 // CHECK3-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1560 // CHECK3-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
1561 // CHECK3-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
1562 // CHECK3:       omp_offload.failed5:
1563 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR2]]
1564 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT6]]
1565 // CHECK3:       omp_offload.cont6:
1566 // CHECK3-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
1567 // CHECK3-NEXT:    ret i32 [[TMP29]]
1568 //
1569 //
1570 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
1571 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
1572 // CHECK3-NEXT:  entry:
1573 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
1574 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1575 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
1576 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1577 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1578 // CHECK3-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1579 // CHECK3-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1580 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1581 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
1582 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
1583 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1584 // CHECK3-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
1585 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
1586 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
1587 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[B_CASTED]], align 4
1588 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
1589 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
1590 // CHECK3-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
1591 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1592 // CHECK3:       omp_if.then:
1593 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
1594 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1595 // CHECK3:       omp_if.else:
1596 // CHECK3-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1597 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1598 // CHECK3-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]]
1599 // CHECK3-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1600 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1601 // CHECK3:       omp_if.end:
1602 // CHECK3-NEXT:    ret void
1603 //
1604 //
1605 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1606 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
1607 // CHECK3-NEXT:  entry:
1608 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1609 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1610 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
1611 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1612 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1613 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1614 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
1615 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
1616 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
1617 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
1618 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
1619 // CHECK3-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
1620 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1621 // CHECK3-NEXT:    store double [[ADD]], double* [[A]], align 4
1622 // CHECK3-NEXT:    ret void
1623 //
1624 //
1625 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
1626 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
1627 // CHECK3-NEXT:  entry:
1628 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
1629 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
1630 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1631 // CHECK3-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1632 // CHECK3-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1633 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1634 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
1635 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1636 // CHECK3-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
1637 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
1638 // CHECK3-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
1639 // CHECK3-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
1640 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1641 // CHECK3:       omp_if.then:
1642 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
1643 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1644 // CHECK3:       omp_if.else:
1645 // CHECK3-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1646 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1647 // CHECK3-NEXT:    call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]]
1648 // CHECK3-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1649 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1650 // CHECK3:       omp_if.end:
1651 // CHECK3-NEXT:    ret void
1652 //
1653 //
1654 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1
1655 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
1656 // CHECK3-NEXT:  entry:
1657 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1658 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1659 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
1660 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1661 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1662 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
1663 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
1664 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1665 // CHECK3-NEXT:    store double 2.500000e+00, double* [[A]], align 4
1666 // CHECK3-NEXT:    ret void
1667 //
1668 //
1669 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
1670 // CHECK3-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
1671 // CHECK3-NEXT:  entry:
1672 // CHECK3-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
1673 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1674 // CHECK3-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1675 // CHECK3-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1676 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1677 // CHECK3-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
1678 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
1679 // CHECK3-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
1680 // CHECK3-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
1681 // CHECK3-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1682 // CHECK3:       omp_if.then:
1683 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
1684 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
1685 // CHECK3:       omp_if.else:
1686 // CHECK3-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1687 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1688 // CHECK3-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
1689 // CHECK3-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1690 // CHECK3-NEXT:    br label [[OMP_IF_END]]
1691 // CHECK3:       omp_if.end:
1692 // CHECK3-NEXT:    ret void
1693 //
1694 //
1695 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
1696 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
1697 // CHECK3-NEXT:  entry:
1698 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1699 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1700 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1701 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1702 // CHECK3-NEXT:    ret void
1703 //
1704 //
1705 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
1706 // CHECK3-SAME: () #[[ATTR1]] {
1707 // CHECK3-NEXT:  entry:
1708 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
1709 // CHECK3-NEXT:    ret void
1710 //
1711 //
1712 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
1713 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
1714 // CHECK3-NEXT:  entry:
1715 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1716 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1717 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1718 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1719 // CHECK3-NEXT:    ret void
1720 //
1721 //
1722 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
1723 // CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
1724 // CHECK3-NEXT:  entry:
1725 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1726 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1727 // CHECK3-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
1728 // CHECK3-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
1729 // CHECK3-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
1730 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1731 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
1732 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
1733 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
1734 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
1735 // CHECK3-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1736 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
1737 // CHECK3-NEXT:    call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]]
1738 // CHECK3-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
1739 // CHECK3-NEXT:    ret void
1740 //
1741 //
1742 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8
1743 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
1744 // CHECK3-NEXT:  entry:
1745 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1746 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1747 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1748 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1749 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1750 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
1751 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1752 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1753 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
1754 // CHECK3-NEXT:    ret void
1755 //
1756 //
1757 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
1758 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
1759 // CHECK3-NEXT:  entry:
1760 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1761 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1762 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
1763 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1764 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
1765 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
1766 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
1767 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1768 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
1769 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
1770 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
1771 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
1772 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
1773 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
1774 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
1775 // CHECK3-NEXT:    ret void
1776 //
1777 //
1778 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
1779 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
1780 // CHECK3-NEXT:  entry:
1781 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
1782 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
1783 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1784 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
1785 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
1786 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
1787 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
1788 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
1789 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
1790 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
1791 // CHECK3-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
1792 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
1793 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
1794 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
1795 // CHECK3-NEXT:    ret void
1796 //
1797 //
1798 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1799 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] {
1800 // CHECK3-NEXT:  entry:
1801 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
1802 // CHECK3-NEXT:    ret void
1803 //
1804 //
1805 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari
1806 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
1807 // CHECK4-NEXT:  entry:
1808 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1809 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
1810 // CHECK4-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
1811 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1812 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
1813 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1814 // CHECK4-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
1815 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1816 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1817 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
1818 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1819 // CHECK4-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
1820 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1821 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1822 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
1823 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1824 // CHECK4-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
1825 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1826 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1827 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
1828 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
1829 // CHECK4-NEXT:    ret i32 [[TMP6]]
1830 //
1831 //
1832 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1833 // CHECK4-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1834 // CHECK4-NEXT:  entry:
1835 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
1836 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1837 // CHECK4-NEXT:    [[B:%.*]] = alloca i32, align 4
1838 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1839 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
1840 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
1841 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
1842 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
1843 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
1844 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1
1845 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4
1846 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4
1847 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4
1848 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4
1849 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
1850 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1851 // CHECK4-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
1852 // CHECK4-NEXT:    store i32 1, i32* [[B]], align 4
1853 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1854 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
1855 // CHECK4-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
1856 // CHECK4-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
1857 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
1858 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[B_CASTED]], align 4
1859 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4
1860 // CHECK4-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1861 // CHECK4-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
1862 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
1863 // CHECK4-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
1864 // CHECK4-NEXT:    store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
1865 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1866 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1867 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1868 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1**
1869 // CHECK4-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4
1870 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1871 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double**
1872 // CHECK4-NEXT:    store double* [[A]], double** [[TMP8]], align 4
1873 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1874 // CHECK4-NEXT:    store i8* null, i8** [[TMP9]], align 4
1875 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1876 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
1877 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[TMP11]], align 4
1878 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1879 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
1880 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[TMP13]], align 4
1881 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
1882 // CHECK4-NEXT:    store i8* null, i8** [[TMP14]], align 4
1883 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1884 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
1885 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[TMP16]], align 4
1886 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1887 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
1888 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[TMP18]], align 4
1889 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
1890 // CHECK4-NEXT:    store i8* null, i8** [[TMP19]], align 4
1891 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1892 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1893 // CHECK4-NEXT:    [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1894 // CHECK4-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1
1895 // CHECK4-NEXT:    [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
1896 // CHECK4-NEXT:    [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
1897 // CHECK4-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
1898 // CHECK4-NEXT:    br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1899 // CHECK4:       omp_offload.failed:
1900 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR2:[0-9]+]]
1901 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1902 // CHECK4:       omp_offload.cont:
1903 // CHECK4-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
1904 // CHECK4-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5
1905 // CHECK4-NEXT:    [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8
1906 // CHECK4-NEXT:    store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1
1907 // CHECK4-NEXT:    [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1
1908 // CHECK4-NEXT:    [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1
1909 // CHECK4-NEXT:    [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8*
1910 // CHECK4-NEXT:    [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8
1911 // CHECK4-NEXT:    store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1
1912 // CHECK4-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4
1913 // CHECK4-NEXT:    [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4
1914 // CHECK4-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4
1915 // CHECK4-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1916 // CHECK4:       omp_if.then:
1917 // CHECK4-NEXT:    [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
1918 // CHECK4-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
1919 // CHECK4-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1**
1920 // CHECK4-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4
1921 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
1922 // CHECK4-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
1923 // CHECK4-NEXT:    store double* [[A12]], double** [[TMP33]], align 4
1924 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
1925 // CHECK4-NEXT:    store i8* null, i8** [[TMP34]], align 4
1926 // CHECK4-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
1927 // CHECK4-NEXT:    [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32*
1928 // CHECK4-NEXT:    store i32 [[TMP28]], i32* [[TMP36]], align 4
1929 // CHECK4-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
1930 // CHECK4-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32*
1931 // CHECK4-NEXT:    store i32 [[TMP28]], i32* [[TMP38]], align 4
1932 // CHECK4-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1
1933 // CHECK4-NEXT:    store i8* null, i8** [[TMP39]], align 4
1934 // CHECK4-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
1935 // CHECK4-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
1936 // CHECK4-NEXT:    [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1
1937 // CHECK4-NEXT:    [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1
1938 // CHECK4-NEXT:    [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1
1939 // CHECK4-NEXT:    [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]])
1940 // CHECK4-NEXT:    [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
1941 // CHECK4-NEXT:    br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
1942 // CHECK4:       omp_offload.failed17:
1943 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]]
1944 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
1945 // CHECK4:       omp_offload.cont18:
1946 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
1947 // CHECK4:       omp_if.else:
1948 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]]
1949 // CHECK4-NEXT:    br label [[OMP_IF_END]]
1950 // CHECK4:       omp_if.end:
1951 // CHECK4-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
1952 // CHECK4-NEXT:    [[TMP46:%.*]] = load double, double* [[A19]], align 4
1953 // CHECK4-NEXT:    [[CONV20:%.*]] = fptosi double [[TMP46]] to i32
1954 // CHECK4-NEXT:    ret i32 [[CONV20]]
1955 //
1956 //
1957 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
1958 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
1959 // CHECK4-NEXT:  entry:
1960 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1961 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
1962 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
1963 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
1964 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
1965 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
1966 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1967 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1968 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
1969 // CHECK4-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
1970 // CHECK4-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
1971 // CHECK4-NEXT:    [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1972 // CHECK4-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
1973 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
1974 // CHECK4-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8
1975 // CHECK4-NEXT:    store i8 [[FROMBOOL1]], i8* [[CONV]], align 1
1976 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
1977 // CHECK4-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1978 // CHECK4-NEXT:    [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
1979 // CHECK4-NEXT:    br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1980 // CHECK4:       omp_if.then:
1981 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1982 // CHECK4-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
1983 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[TMP5]], align 4
1984 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1985 // CHECK4-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
1986 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[TMP7]], align 4
1987 // CHECK4-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
1988 // CHECK4-NEXT:    store i8* null, i8** [[TMP8]], align 4
1989 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1990 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1991 // CHECK4-NEXT:    [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
1992 // CHECK4-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1
1993 // CHECK4-NEXT:    [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
1994 // CHECK4-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]])
1995 // CHECK4-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
1996 // CHECK4-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1997 // CHECK4:       omp_offload.failed:
1998 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
1999 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2000 // CHECK4:       omp_offload.cont:
2001 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
2002 // CHECK4:       omp_if.else:
2003 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
2004 // CHECK4-NEXT:    br label [[OMP_IF_END]]
2005 // CHECK4:       omp_if.end:
2006 // CHECK4-NEXT:    [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4
2007 // CHECK4-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2
2008 // CHECK4-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2
2009 // CHECK4-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]]
2010 // CHECK4:       omp_if.then5:
2011 // CHECK4-NEXT:    [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
2012 // CHECK4-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
2013 // CHECK4-NEXT:    br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
2014 // CHECK4:       omp_offload.failed6:
2015 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
2016 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT7]]
2017 // CHECK4:       omp_offload.cont7:
2018 // CHECK4-NEXT:    br label [[OMP_IF_END9:%.*]]
2019 // CHECK4:       omp_if.else8:
2020 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
2021 // CHECK4-NEXT:    br label [[OMP_IF_END9]]
2022 // CHECK4:       omp_if.end9:
2023 // CHECK4-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
2024 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], 1
2025 // CHECK4-NEXT:    ret i32 [[ADD]]
2026 //
2027 //
2028 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
2029 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
2030 // CHECK4-NEXT:  entry:
2031 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2032 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
2033 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2034 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
2035 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
2036 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
2037 // CHECK4-NEXT:    [[B:%.*]] = alloca i16, align 2
2038 // CHECK4-NEXT:    [[A_CASTED1:%.*]] = alloca i32, align 4
2039 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
2040 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4
2041 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4
2042 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4
2043 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2044 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
2045 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
2046 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
2047 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
2048 // CHECK4-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2049 // CHECK4-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
2050 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP3]], align 4
2051 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2052 // CHECK4-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
2053 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP5]], align 4
2054 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2055 // CHECK4-NEXT:    store i8* null, i8** [[TMP6]], align 4
2056 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2057 // CHECK4-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2058 // CHECK4-NEXT:    [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1)
2059 // CHECK4-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
2060 // CHECK4-NEXT:    br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2061 // CHECK4:       omp_offload.failed:
2062 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR2]]
2063 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2064 // CHECK4:       omp_offload.cont:
2065 // CHECK4-NEXT:    store i16 1, i16* [[B]], align 2
2066 // CHECK4-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
2067 // CHECK4-NEXT:    store i32 [[TMP11]], i32* [[A_CASTED1]], align 4
2068 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4
2069 // CHECK4-NEXT:    [[TMP13:%.*]] = load i16, i16* [[B]], align 2
2070 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
2071 // CHECK4-NEXT:    store i16 [[TMP13]], i16* [[CONV]], align 2
2072 // CHECK4-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4
2073 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
2074 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
2075 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP16]], align 4
2076 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
2077 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
2078 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP18]], align 4
2079 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
2080 // CHECK4-NEXT:    store i8* null, i8** [[TMP19]], align 4
2081 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
2082 // CHECK4-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
2083 // CHECK4-NEXT:    store i32 [[TMP14]], i32* [[TMP21]], align 4
2084 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
2085 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
2086 // CHECK4-NEXT:    store i32 [[TMP14]], i32* [[TMP23]], align 4
2087 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
2088 // CHECK4-NEXT:    store i8* null, i8** [[TMP24]], align 4
2089 // CHECK4-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
2090 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
2091 // CHECK4-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2092 // CHECK4-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
2093 // CHECK4-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
2094 // CHECK4:       omp_offload.failed5:
2095 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR2]]
2096 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT6]]
2097 // CHECK4:       omp_offload.cont6:
2098 // CHECK4-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
2099 // CHECK4-NEXT:    ret i32 [[TMP29]]
2100 //
2101 //
2102 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
2103 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
2104 // CHECK4-NEXT:  entry:
2105 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
2106 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
2107 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2108 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
2109 // CHECK4-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2110 // CHECK4-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2111 // CHECK4-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2112 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2113 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
2114 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
2115 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
2116 // CHECK4-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
2117 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2118 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
2119 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[B_CASTED]], align 4
2120 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
2121 // CHECK4-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
2122 // CHECK4-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
2123 // CHECK4-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2124 // CHECK4:       omp_if.then:
2125 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
2126 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
2127 // CHECK4:       omp_if.else:
2128 // CHECK4-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2129 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2130 // CHECK4-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]]
2131 // CHECK4-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2132 // CHECK4-NEXT:    br label [[OMP_IF_END]]
2133 // CHECK4:       omp_if.end:
2134 // CHECK4-NEXT:    ret void
2135 //
2136 //
2137 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
2138 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
2139 // CHECK4-NEXT:  entry:
2140 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2141 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2142 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
2143 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
2144 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2145 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2146 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
2147 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
2148 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
2149 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
2150 // CHECK4-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
2151 // CHECK4-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
2152 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
2153 // CHECK4-NEXT:    store double [[ADD]], double* [[A]], align 4
2154 // CHECK4-NEXT:    ret void
2155 //
2156 //
2157 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
2158 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
2159 // CHECK4-NEXT:  entry:
2160 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
2161 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2162 // CHECK4-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2163 // CHECK4-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2164 // CHECK4-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2165 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2166 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
2167 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
2168 // CHECK4-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
2169 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2170 // CHECK4-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
2171 // CHECK4-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
2172 // CHECK4-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2173 // CHECK4:       omp_if.then:
2174 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
2175 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
2176 // CHECK4:       omp_if.else:
2177 // CHECK4-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2178 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2179 // CHECK4-NEXT:    call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]]
2180 // CHECK4-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2181 // CHECK4-NEXT:    br label [[OMP_IF_END]]
2182 // CHECK4:       omp_if.end:
2183 // CHECK4-NEXT:    ret void
2184 //
2185 //
2186 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1
2187 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
2188 // CHECK4-NEXT:  entry:
2189 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2190 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2191 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
2192 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2193 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2194 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
2195 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
2196 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
2197 // CHECK4-NEXT:    store double 2.500000e+00, double* [[A]], align 4
2198 // CHECK4-NEXT:    ret void
2199 //
2200 //
2201 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
2202 // CHECK4-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
2203 // CHECK4-NEXT:  entry:
2204 // CHECK4-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
2205 // CHECK4-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2206 // CHECK4-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2207 // CHECK4-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2208 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2209 // CHECK4-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
2210 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2211 // CHECK4-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
2212 // CHECK4-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
2213 // CHECK4-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2214 // CHECK4:       omp_if.then:
2215 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
2216 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
2217 // CHECK4:       omp_if.else:
2218 // CHECK4-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2219 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2220 // CHECK4-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
2221 // CHECK4-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2222 // CHECK4-NEXT:    br label [[OMP_IF_END]]
2223 // CHECK4:       omp_if.end:
2224 // CHECK4-NEXT:    ret void
2225 //
2226 //
2227 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
2228 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
2229 // CHECK4-NEXT:  entry:
2230 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2231 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2232 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2233 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2234 // CHECK4-NEXT:    ret void
2235 //
2236 //
2237 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
2238 // CHECK4-SAME: () #[[ATTR1]] {
2239 // CHECK4-NEXT:  entry:
2240 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
2241 // CHECK4-NEXT:    ret void
2242 //
2243 //
2244 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7
2245 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
2246 // CHECK4-NEXT:  entry:
2247 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2248 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2249 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2250 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2251 // CHECK4-NEXT:    ret void
2252 //
2253 //
2254 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
2255 // CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
2256 // CHECK4-NEXT:  entry:
2257 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2258 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2259 // CHECK4-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2260 // CHECK4-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2261 // CHECK4-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2262 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2263 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2264 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
2265 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
2266 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
2267 // CHECK4-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2268 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2269 // CHECK4-NEXT:    call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]]
2270 // CHECK4-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2271 // CHECK4-NEXT:    ret void
2272 //
2273 //
2274 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8
2275 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
2276 // CHECK4-NEXT:  entry:
2277 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2278 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2279 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2280 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2281 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2282 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2283 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2284 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2285 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
2286 // CHECK4-NEXT:    ret void
2287 //
2288 //
2289 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
2290 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
2291 // CHECK4-NEXT:  entry:
2292 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2293 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
2294 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2295 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
2296 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2297 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
2298 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
2299 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2300 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
2301 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
2302 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
2303 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
2304 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
2305 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
2306 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
2307 // CHECK4-NEXT:    ret void
2308 //
2309 //
2310 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
2311 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
2312 // CHECK4-NEXT:  entry:
2313 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2314 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2315 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2316 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
2317 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2318 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2319 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2320 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
2321 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
2322 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
2323 // CHECK4-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
2324 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
2325 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
2326 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
2327 // CHECK4-NEXT:    ret void
2328 //
2329 //
2330 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2331 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] {
2332 // CHECK4-NEXT:  entry:
2333 // CHECK4-NEXT:    call void @__tgt_register_requires(i64 1)
2334 // CHECK4-NEXT:    ret void
2335 //
2336 //
2337 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari
2338 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2339 // CHECK5-NEXT:  entry:
2340 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2341 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
2342 // CHECK5-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
2343 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2344 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
2345 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2346 // CHECK5-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
2347 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
2348 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
2349 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2350 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2351 // CHECK5-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
2352 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2353 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
2354 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
2355 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2356 // CHECK5-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
2357 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
2358 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
2359 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
2360 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
2361 // CHECK5-NEXT:    ret i32 [[TMP6]]
2362 //
2363 //
2364 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
2365 // CHECK5-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
2366 // CHECK5-NEXT:  entry:
2367 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2368 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2369 // CHECK5-NEXT:    [[B:%.*]] = alloca i32, align 4
2370 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2371 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
2372 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2373 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2374 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2375 // CHECK5-NEXT:    store i32 1, i32* [[B]], align 4
2376 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2377 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
2378 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
2379 // CHECK5-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2380 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
2381 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
2382 // CHECK5-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
2383 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
2384 // CHECK5-NEXT:    store double [[ADD]], double* [[A]], align 8
2385 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2386 // CHECK5-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
2387 // CHECK5-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
2388 // CHECK5-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
2389 // CHECK5-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
2390 // CHECK5-NEXT:    store double 2.500000e+00, double* [[A5]], align 8
2391 // CHECK5-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
2392 // CHECK5-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 8
2393 // CHECK5-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
2394 // CHECK5-NEXT:    ret i32 [[CONV7]]
2395 //
2396 //
2397 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
2398 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
2399 // CHECK5-NEXT:  entry:
2400 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2401 // CHECK5-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2402 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2403 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2404 // CHECK5-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
2405 // CHECK5-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
2406 // CHECK5-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2407 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2408 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2409 // CHECK5-NEXT:    ret i32 [[ADD]]
2410 //
2411 //
2412 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
2413 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
2414 // CHECK5-NEXT:  entry:
2415 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2416 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
2417 // CHECK5-NEXT:    [[B:%.*]] = alloca i16, align 2
2418 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2419 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
2420 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
2421 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2422 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2423 // CHECK5-NEXT:    store i16 1, i16* [[B]], align 2
2424 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
2425 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2426 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2427 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
2428 // CHECK5-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
2429 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2430 // CHECK5-NEXT:    ret i32 [[TMP3]]
2431 //
2432 //
2433 // CHECK6-LABEL: define {{[^@]+}}@_Z3bari
2434 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2435 // CHECK6-NEXT:  entry:
2436 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2437 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
2438 // CHECK6-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
2439 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2440 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
2441 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2442 // CHECK6-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
2443 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
2444 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
2445 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2446 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2447 // CHECK6-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
2448 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2449 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
2450 // CHECK6-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
2451 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2452 // CHECK6-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
2453 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
2454 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
2455 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
2456 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
2457 // CHECK6-NEXT:    ret i32 [[TMP6]]
2458 //
2459 //
2460 // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
2461 // CHECK6-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
2462 // CHECK6-NEXT:  entry:
2463 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2464 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2465 // CHECK6-NEXT:    [[B:%.*]] = alloca i32, align 4
2466 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2467 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
2468 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2469 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2470 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2471 // CHECK6-NEXT:    store i32 1, i32* [[B]], align 4
2472 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2473 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
2474 // CHECK6-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
2475 // CHECK6-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2476 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
2477 // CHECK6-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
2478 // CHECK6-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
2479 // CHECK6-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
2480 // CHECK6-NEXT:    store double [[ADD]], double* [[A]], align 8
2481 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2482 // CHECK6-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
2483 // CHECK6-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
2484 // CHECK6-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
2485 // CHECK6-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
2486 // CHECK6-NEXT:    store double 2.500000e+00, double* [[A5]], align 8
2487 // CHECK6-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
2488 // CHECK6-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 8
2489 // CHECK6-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
2490 // CHECK6-NEXT:    ret i32 [[CONV7]]
2491 //
2492 //
2493 // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici
2494 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
2495 // CHECK6-NEXT:  entry:
2496 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2497 // CHECK6-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2498 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2499 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2500 // CHECK6-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
2501 // CHECK6-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
2502 // CHECK6-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2503 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2504 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2505 // CHECK6-NEXT:    ret i32 [[ADD]]
2506 //
2507 //
2508 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
2509 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
2510 // CHECK6-NEXT:  entry:
2511 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2512 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
2513 // CHECK6-NEXT:    [[B:%.*]] = alloca i16, align 2
2514 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2515 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
2516 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
2517 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2518 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2519 // CHECK6-NEXT:    store i16 1, i16* [[B]], align 2
2520 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
2521 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2522 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2523 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
2524 // CHECK6-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
2525 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2526 // CHECK6-NEXT:    ret i32 [[TMP3]]
2527 //
2528 //
2529 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari
2530 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2531 // CHECK7-NEXT:  entry:
2532 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2533 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
2534 // CHECK7-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
2535 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2536 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
2537 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2538 // CHECK7-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
2539 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
2540 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
2541 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2542 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2543 // CHECK7-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
2544 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2545 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
2546 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
2547 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2548 // CHECK7-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
2549 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
2550 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
2551 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
2552 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
2553 // CHECK7-NEXT:    ret i32 [[TMP6]]
2554 //
2555 //
2556 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
2557 // CHECK7-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
2558 // CHECK7-NEXT:  entry:
2559 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
2560 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2561 // CHECK7-NEXT:    [[B:%.*]] = alloca i32, align 4
2562 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2563 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
2564 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
2565 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2566 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
2567 // CHECK7-NEXT:    store i32 1, i32* [[B]], align 4
2568 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2569 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
2570 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
2571 // CHECK7-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2572 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
2573 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
2574 // CHECK7-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
2575 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
2576 // CHECK7-NEXT:    store double [[ADD]], double* [[A]], align 4
2577 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2578 // CHECK7-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
2579 // CHECK7-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
2580 // CHECK7-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
2581 // CHECK7-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
2582 // CHECK7-NEXT:    store double 2.500000e+00, double* [[A5]], align 4
2583 // CHECK7-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
2584 // CHECK7-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 4
2585 // CHECK7-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
2586 // CHECK7-NEXT:    ret i32 [[CONV7]]
2587 //
2588 //
2589 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
2590 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
2591 // CHECK7-NEXT:  entry:
2592 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2593 // CHECK7-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2594 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2595 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2596 // CHECK7-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
2597 // CHECK7-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
2598 // CHECK7-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2599 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2600 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2601 // CHECK7-NEXT:    ret i32 [[ADD]]
2602 //
2603 //
2604 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
2605 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
2606 // CHECK7-NEXT:  entry:
2607 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2608 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
2609 // CHECK7-NEXT:    [[B:%.*]] = alloca i16, align 2
2610 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2611 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
2612 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
2613 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2614 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2615 // CHECK7-NEXT:    store i16 1, i16* [[B]], align 2
2616 // CHECK7-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
2617 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2618 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2619 // CHECK7-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
2620 // CHECK7-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
2621 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2622 // CHECK7-NEXT:    ret i32 [[TMP3]]
2623 //
2624 //
2625 // CHECK8-LABEL: define {{[^@]+}}@_Z3bari
2626 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2627 // CHECK8-NEXT:  entry:
2628 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2629 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
2630 // CHECK8-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
2631 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2632 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
2633 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2634 // CHECK8-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
2635 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
2636 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
2637 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2638 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2639 // CHECK8-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
2640 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2641 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
2642 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
2643 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2644 // CHECK8-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
2645 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
2646 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
2647 // CHECK8-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
2648 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
2649 // CHECK8-NEXT:    ret i32 [[TMP6]]
2650 //
2651 //
2652 // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
2653 // CHECK8-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
2654 // CHECK8-NEXT:  entry:
2655 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
2656 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2657 // CHECK8-NEXT:    [[B:%.*]] = alloca i32, align 4
2658 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2659 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
2660 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
2661 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2662 // CHECK8-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
2663 // CHECK8-NEXT:    store i32 1, i32* [[B]], align 4
2664 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2665 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
2666 // CHECK8-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
2667 // CHECK8-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2668 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
2669 // CHECK8-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
2670 // CHECK8-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
2671 // CHECK8-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
2672 // CHECK8-NEXT:    store double [[ADD]], double* [[A]], align 4
2673 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2674 // CHECK8-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
2675 // CHECK8-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
2676 // CHECK8-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
2677 // CHECK8-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
2678 // CHECK8-NEXT:    store double 2.500000e+00, double* [[A5]], align 4
2679 // CHECK8-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
2680 // CHECK8-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 4
2681 // CHECK8-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
2682 // CHECK8-NEXT:    ret i32 [[CONV7]]
2683 //
2684 //
2685 // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici
2686 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
2687 // CHECK8-NEXT:  entry:
2688 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2689 // CHECK8-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
2690 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2691 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2692 // CHECK8-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
2693 // CHECK8-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
2694 // CHECK8-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
2695 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2696 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2697 // CHECK8-NEXT:    ret i32 [[ADD]]
2698 //
2699 //
2700 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
2701 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
2702 // CHECK8-NEXT:  entry:
2703 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2704 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
2705 // CHECK8-NEXT:    [[B:%.*]] = alloca i16, align 2
2706 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2707 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
2708 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
2709 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2710 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2711 // CHECK8-NEXT:    store i16 1, i16* [[B]], align 2
2712 // CHECK8-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
2713 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
2714 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
2715 // CHECK8-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
2716 // CHECK8-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
2717 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2718 // CHECK8-NEXT:    ret i32 [[TMP3]]
2719 //
2720 //
2721 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
2722 // CHECK9-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
2723 // CHECK9-NEXT:  entry:
2724 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2725 // CHECK9-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2726 // CHECK9-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2727 // CHECK9-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2728 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
2729 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2730 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2731 // CHECK9-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
2732 // CHECK9-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
2733 // CHECK9-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2734 // CHECK9:       omp_if.then:
2735 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2736 // CHECK9-NEXT:    br label [[OMP_IF_END:%.*]]
2737 // CHECK9:       omp_if.else:
2738 // CHECK9-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2739 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2740 // CHECK9-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]]
2741 // CHECK9-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2742 // CHECK9-NEXT:    br label [[OMP_IF_END]]
2743 // CHECK9:       omp_if.end:
2744 // CHECK9-NEXT:    ret void
2745 //
2746 //
2747 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
2748 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
2749 // CHECK9-NEXT:  entry:
2750 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2751 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2752 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2753 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2754 // CHECK9-NEXT:    ret void
2755 //
2756 //
2757 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
2758 // CHECK9-SAME: () #[[ATTR0]] {
2759 // CHECK9-NEXT:  entry:
2760 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
2761 // CHECK9-NEXT:    ret void
2762 //
2763 //
2764 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
2765 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
2766 // CHECK9-NEXT:  entry:
2767 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2768 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2769 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2770 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2771 // CHECK9-NEXT:    ret void
2772 //
2773 //
2774 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
2775 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
2776 // CHECK9-NEXT:  entry:
2777 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2778 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2779 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2780 // CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
2781 // CHECK9-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2782 // CHECK9-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2783 // CHECK9-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2784 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2785 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2786 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
2787 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2788 // CHECK9-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2789 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2790 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2791 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
2792 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
2793 // CHECK9-NEXT:    store i32 [[TMP2]], i32* [[CONV2]], align 4
2794 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
2795 // CHECK9-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
2796 // CHECK9-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
2797 // CHECK9-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2798 // CHECK9:       omp_if.then:
2799 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
2800 // CHECK9-NEXT:    br label [[OMP_IF_END:%.*]]
2801 // CHECK9:       omp_if.else:
2802 // CHECK9-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2803 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2804 // CHECK9-NEXT:    call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]]
2805 // CHECK9-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2806 // CHECK9-NEXT:    br label [[OMP_IF_END]]
2807 // CHECK9:       omp_if.end:
2808 // CHECK9-NEXT:    ret void
2809 //
2810 //
2811 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
2812 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
2813 // CHECK9-NEXT:  entry:
2814 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2815 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2816 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2817 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2818 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2819 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2820 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2821 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
2822 // CHECK9-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2823 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2824 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
2825 // CHECK9-NEXT:    [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
2826 // CHECK9-NEXT:    [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
2827 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
2828 // CHECK9-NEXT:    store double [[ADD]], double* [[A]], align 8
2829 // CHECK9-NEXT:    ret void
2830 //
2831 //
2832 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
2833 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
2834 // CHECK9-NEXT:  entry:
2835 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2836 // CHECK9-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2837 // CHECK9-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2838 // CHECK9-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2839 // CHECK9-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2840 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2841 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2842 // CHECK9-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2843 // CHECK9-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2844 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2845 // CHECK9-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
2846 // CHECK9-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
2847 // CHECK9-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2848 // CHECK9:       omp_if.then:
2849 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
2850 // CHECK9-NEXT:    br label [[OMP_IF_END:%.*]]
2851 // CHECK9:       omp_if.else:
2852 // CHECK9-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2853 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2854 // CHECK9-NEXT:    call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]]
2855 // CHECK9-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2856 // CHECK9-NEXT:    br label [[OMP_IF_END]]
2857 // CHECK9:       omp_if.end:
2858 // CHECK9-NEXT:    ret void
2859 //
2860 //
2861 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
2862 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
2863 // CHECK9-NEXT:  entry:
2864 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2865 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2866 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2867 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2868 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2869 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2870 // CHECK9-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2871 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
2872 // CHECK9-NEXT:    store double 2.500000e+00, double* [[A]], align 8
2873 // CHECK9-NEXT:    ret void
2874 //
2875 //
2876 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
2877 // CHECK9-SAME: (i64 [[A:%.*]]) #[[ATTR0]] {
2878 // CHECK9-NEXT:  entry:
2879 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2880 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2881 // CHECK9-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2882 // CHECK9-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2883 // CHECK9-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2884 // CHECK9-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
2885 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2886 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2887 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
2888 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2889 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[CONV1]], align 4
2890 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
2891 // CHECK9-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2892 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2893 // CHECK9-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]]
2894 // CHECK9-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2895 // CHECK9-NEXT:    ret void
2896 //
2897 //
2898 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
2899 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
2900 // CHECK9-NEXT:  entry:
2901 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2902 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2903 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2904 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2905 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2906 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2907 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2908 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2909 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2910 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
2911 // CHECK9-NEXT:    ret void
2912 //
2913 //
2914 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
2915 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
2916 // CHECK9-NEXT:  entry:
2917 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2918 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2919 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2920 // CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
2921 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2922 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
2923 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2924 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
2925 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
2926 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2927 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
2928 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2929 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
2930 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
2931 // CHECK9-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
2932 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
2933 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
2934 // CHECK9-NEXT:    ret void
2935 //
2936 //
2937 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
2938 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
2939 // CHECK9-NEXT:  entry:
2940 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2941 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2942 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2943 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2944 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2945 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2946 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2947 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
2948 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2949 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
2950 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
2951 // CHECK9-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
2952 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
2953 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
2954 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
2955 // CHECK9-NEXT:    ret void
2956 //
2957 //
2958 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
2959 // CHECK10-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
2960 // CHECK10-NEXT:  entry:
2961 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
2962 // CHECK10-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
2963 // CHECK10-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
2964 // CHECK10-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
2965 // CHECK10-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
2966 // CHECK10-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
2967 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
2968 // CHECK10-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
2969 // CHECK10-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
2970 // CHECK10-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2971 // CHECK10:       omp_if.then:
2972 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2973 // CHECK10-NEXT:    br label [[OMP_IF_END:%.*]]
2974 // CHECK10:       omp_if.else:
2975 // CHECK10-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2976 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
2977 // CHECK10-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]]
2978 // CHECK10-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
2979 // CHECK10-NEXT:    br label [[OMP_IF_END]]
2980 // CHECK10:       omp_if.end:
2981 // CHECK10-NEXT:    ret void
2982 //
2983 //
2984 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
2985 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
2986 // CHECK10-NEXT:  entry:
2987 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2988 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2989 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2990 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2991 // CHECK10-NEXT:    ret void
2992 //
2993 //
2994 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
2995 // CHECK10-SAME: () #[[ATTR0]] {
2996 // CHECK10-NEXT:  entry:
2997 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
2998 // CHECK10-NEXT:    ret void
2999 //
3000 //
3001 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
3002 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
3003 // CHECK10-NEXT:  entry:
3004 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3005 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3006 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3007 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3008 // CHECK10-NEXT:    ret void
3009 //
3010 //
3011 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
3012 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
3013 // CHECK10-NEXT:  entry:
3014 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3015 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3016 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
3017 // CHECK10-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3018 // CHECK10-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3019 // CHECK10-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3020 // CHECK10-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3021 // CHECK10-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3022 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3023 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3024 // CHECK10-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
3025 // CHECK10-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3026 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3027 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
3028 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
3029 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
3030 // CHECK10-NEXT:    store i32 [[TMP2]], i32* [[CONV2]], align 4
3031 // CHECK10-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
3032 // CHECK10-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
3033 // CHECK10-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
3034 // CHECK10-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3035 // CHECK10:       omp_if.then:
3036 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
3037 // CHECK10-NEXT:    br label [[OMP_IF_END:%.*]]
3038 // CHECK10:       omp_if.else:
3039 // CHECK10-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3040 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3041 // CHECK10-NEXT:    call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]]
3042 // CHECK10-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3043 // CHECK10-NEXT:    br label [[OMP_IF_END]]
3044 // CHECK10:       omp_if.end:
3045 // CHECK10-NEXT:    ret void
3046 //
3047 //
3048 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
3049 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
3050 // CHECK10-NEXT:  entry:
3051 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3052 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3053 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3054 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3055 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3056 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3057 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3058 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3059 // CHECK10-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3060 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
3061 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3062 // CHECK10-NEXT:    [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
3063 // CHECK10-NEXT:    [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
3064 // CHECK10-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3065 // CHECK10-NEXT:    store double [[ADD]], double* [[A]], align 8
3066 // CHECK10-NEXT:    ret void
3067 //
3068 //
3069 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
3070 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
3071 // CHECK10-NEXT:  entry:
3072 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3073 // CHECK10-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
3074 // CHECK10-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3075 // CHECK10-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3076 // CHECK10-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3077 // CHECK10-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3078 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3079 // CHECK10-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
3080 // CHECK10-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3081 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
3082 // CHECK10-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
3083 // CHECK10-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
3084 // CHECK10-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3085 // CHECK10:       omp_if.then:
3086 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
3087 // CHECK10-NEXT:    br label [[OMP_IF_END:%.*]]
3088 // CHECK10:       omp_if.else:
3089 // CHECK10-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3090 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3091 // CHECK10-NEXT:    call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]]
3092 // CHECK10-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3093 // CHECK10-NEXT:    br label [[OMP_IF_END]]
3094 // CHECK10:       omp_if.end:
3095 // CHECK10-NEXT:    ret void
3096 //
3097 //
3098 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
3099 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
3100 // CHECK10-NEXT:  entry:
3101 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3102 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3103 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3104 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3105 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3106 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3107 // CHECK10-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3108 // CHECK10-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3109 // CHECK10-NEXT:    store double 2.500000e+00, double* [[A]], align 8
3110 // CHECK10-NEXT:    ret void
3111 //
3112 //
3113 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
3114 // CHECK10-SAME: (i64 [[A:%.*]]) #[[ATTR0]] {
3115 // CHECK10-NEXT:  entry:
3116 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3117 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3118 // CHECK10-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3119 // CHECK10-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3120 // CHECK10-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3121 // CHECK10-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3122 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3123 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3124 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3125 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3126 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[CONV1]], align 4
3127 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
3128 // CHECK10-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3129 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3130 // CHECK10-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]]
3131 // CHECK10-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3132 // CHECK10-NEXT:    ret void
3133 //
3134 //
3135 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
3136 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
3137 // CHECK10-NEXT:  entry:
3138 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3139 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3140 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3141 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3142 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3143 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3144 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3145 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
3146 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3147 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
3148 // CHECK10-NEXT:    ret void
3149 //
3150 //
3151 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
3152 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
3153 // CHECK10-NEXT:  entry:
3154 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3155 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3156 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
3157 // CHECK10-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
3158 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3159 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3160 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3161 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
3162 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
3163 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
3164 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
3165 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
3166 // CHECK10-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
3167 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
3168 // CHECK10-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
3169 // CHECK10-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
3170 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
3171 // CHECK10-NEXT:    ret void
3172 //
3173 //
3174 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
3175 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
3176 // CHECK10-NEXT:  entry:
3177 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3178 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3179 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
3180 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
3181 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3182 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3183 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
3184 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
3185 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
3186 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
3187 // CHECK10-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
3188 // CHECK10-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
3189 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
3190 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
3191 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
3192 // CHECK10-NEXT:    ret void
3193 //
3194 //
3195 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
3196 // CHECK11-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
3197 // CHECK11-NEXT:  entry:
3198 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
3199 // CHECK11-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3200 // CHECK11-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3201 // CHECK11-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3202 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
3203 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3204 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
3205 // CHECK11-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
3206 // CHECK11-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
3207 // CHECK11-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3208 // CHECK11:       omp_if.then:
3209 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3210 // CHECK11-NEXT:    br label [[OMP_IF_END:%.*]]
3211 // CHECK11:       omp_if.else:
3212 // CHECK11-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3213 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3214 // CHECK11-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]]
3215 // CHECK11-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3216 // CHECK11-NEXT:    br label [[OMP_IF_END]]
3217 // CHECK11:       omp_if.end:
3218 // CHECK11-NEXT:    ret void
3219 //
3220 //
3221 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
3222 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
3223 // CHECK11-NEXT:  entry:
3224 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3225 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3226 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3227 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3228 // CHECK11-NEXT:    ret void
3229 //
3230 //
3231 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
3232 // CHECK11-SAME: () #[[ATTR0]] {
3233 // CHECK11-NEXT:  entry:
3234 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
3235 // CHECK11-NEXT:    ret void
3236 //
3237 //
3238 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
3239 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
3240 // CHECK11-NEXT:  entry:
3241 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3242 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3243 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3244 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3245 // CHECK11-NEXT:    ret void
3246 //
3247 //
3248 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
3249 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
3250 // CHECK11-NEXT:  entry:
3251 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3252 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3253 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
3254 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3255 // CHECK11-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3256 // CHECK11-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3257 // CHECK11-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3258 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3259 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3260 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3261 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3262 // CHECK11-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3263 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
3264 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
3265 // CHECK11-NEXT:    store i32 [[TMP2]], i32* [[B_CASTED]], align 4
3266 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
3267 // CHECK11-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
3268 // CHECK11-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
3269 // CHECK11-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3270 // CHECK11:       omp_if.then:
3271 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
3272 // CHECK11-NEXT:    br label [[OMP_IF_END:%.*]]
3273 // CHECK11:       omp_if.else:
3274 // CHECK11-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3275 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3276 // CHECK11-NEXT:    call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]]
3277 // CHECK11-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3278 // CHECK11-NEXT:    br label [[OMP_IF_END]]
3279 // CHECK11:       omp_if.end:
3280 // CHECK11-NEXT:    ret void
3281 //
3282 //
3283 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
3284 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
3285 // CHECK11-NEXT:  entry:
3286 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3287 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3288 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3289 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3290 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3291 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3292 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3293 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3294 // CHECK11-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3295 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
3296 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
3297 // CHECK11-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3298 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3299 // CHECK11-NEXT:    store double [[ADD]], double* [[A]], align 4
3300 // CHECK11-NEXT:    ret void
3301 //
3302 //
3303 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
3304 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
3305 // CHECK11-NEXT:  entry:
3306 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3307 // CHECK11-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
3308 // CHECK11-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3309 // CHECK11-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3310 // CHECK11-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3311 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3312 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3313 // CHECK11-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3314 // CHECK11-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3315 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
3316 // CHECK11-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
3317 // CHECK11-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
3318 // CHECK11-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3319 // CHECK11:       omp_if.then:
3320 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
3321 // CHECK11-NEXT:    br label [[OMP_IF_END:%.*]]
3322 // CHECK11:       omp_if.else:
3323 // CHECK11-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3324 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3325 // CHECK11-NEXT:    call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]]
3326 // CHECK11-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3327 // CHECK11-NEXT:    br label [[OMP_IF_END]]
3328 // CHECK11:       omp_if.end:
3329 // CHECK11-NEXT:    ret void
3330 //
3331 //
3332 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
3333 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
3334 // CHECK11-NEXT:  entry:
3335 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3336 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3337 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3338 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3339 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3340 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3341 // CHECK11-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3342 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3343 // CHECK11-NEXT:    store double 2.500000e+00, double* [[A]], align 4
3344 // CHECK11-NEXT:    ret void
3345 //
3346 //
3347 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
3348 // CHECK11-SAME: (i32 [[A:%.*]]) #[[ATTR0]] {
3349 // CHECK11-NEXT:  entry:
3350 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3351 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3352 // CHECK11-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3353 // CHECK11-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3354 // CHECK11-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3355 // CHECK11-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3356 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3357 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3358 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
3359 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
3360 // CHECK11-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3361 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3362 // CHECK11-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]]
3363 // CHECK11-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3364 // CHECK11-NEXT:    ret void
3365 //
3366 //
3367 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
3368 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
3369 // CHECK11-NEXT:  entry:
3370 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3371 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3372 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3373 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3374 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3375 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3376 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3377 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3378 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
3379 // CHECK11-NEXT:    ret void
3380 //
3381 //
3382 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
3383 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
3384 // CHECK11-NEXT:  entry:
3385 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3386 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3387 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3388 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3389 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3390 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3391 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
3392 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3393 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3394 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3395 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
3396 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
3397 // CHECK11-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
3398 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
3399 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
3400 // CHECK11-NEXT:    ret void
3401 //
3402 //
3403 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
3404 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
3405 // CHECK11-NEXT:  entry:
3406 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3407 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3408 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3409 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3410 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3411 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3412 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3413 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3414 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
3415 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
3416 // CHECK11-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
3417 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3418 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
3419 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
3420 // CHECK11-NEXT:    ret void
3421 //
3422 //
3423 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
3424 // CHECK12-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
3425 // CHECK12-NEXT:  entry:
3426 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
3427 // CHECK12-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3428 // CHECK12-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3429 // CHECK12-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3430 // CHECK12-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
3431 // CHECK12-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3432 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
3433 // CHECK12-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
3434 // CHECK12-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
3435 // CHECK12-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3436 // CHECK12:       omp_if.then:
3437 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3438 // CHECK12-NEXT:    br label [[OMP_IF_END:%.*]]
3439 // CHECK12:       omp_if.else:
3440 // CHECK12-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3441 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3442 // CHECK12-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]]
3443 // CHECK12-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3444 // CHECK12-NEXT:    br label [[OMP_IF_END]]
3445 // CHECK12:       omp_if.end:
3446 // CHECK12-NEXT:    ret void
3447 //
3448 //
3449 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
3450 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
3451 // CHECK12-NEXT:  entry:
3452 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3453 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3454 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3455 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3456 // CHECK12-NEXT:    ret void
3457 //
3458 //
3459 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
3460 // CHECK12-SAME: () #[[ATTR0]] {
3461 // CHECK12-NEXT:  entry:
3462 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
3463 // CHECK12-NEXT:    ret void
3464 //
3465 //
3466 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
3467 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
3468 // CHECK12-NEXT:  entry:
3469 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3470 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3471 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3472 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3473 // CHECK12-NEXT:    ret void
3474 //
3475 //
3476 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
3477 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
3478 // CHECK12-NEXT:  entry:
3479 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3480 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3481 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
3482 // CHECK12-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3483 // CHECK12-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3484 // CHECK12-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3485 // CHECK12-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3486 // CHECK12-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3487 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3488 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3489 // CHECK12-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3490 // CHECK12-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3491 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
3492 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
3493 // CHECK12-NEXT:    store i32 [[TMP2]], i32* [[B_CASTED]], align 4
3494 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
3495 // CHECK12-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
3496 // CHECK12-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
3497 // CHECK12-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3498 // CHECK12:       omp_if.then:
3499 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
3500 // CHECK12-NEXT:    br label [[OMP_IF_END:%.*]]
3501 // CHECK12:       omp_if.else:
3502 // CHECK12-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3503 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3504 // CHECK12-NEXT:    call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]]
3505 // CHECK12-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3506 // CHECK12-NEXT:    br label [[OMP_IF_END]]
3507 // CHECK12:       omp_if.end:
3508 // CHECK12-NEXT:    ret void
3509 //
3510 //
3511 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
3512 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
3513 // CHECK12-NEXT:  entry:
3514 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3515 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3516 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3517 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3518 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3519 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3520 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3521 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3522 // CHECK12-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3523 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
3524 // CHECK12-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
3525 // CHECK12-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3526 // CHECK12-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3527 // CHECK12-NEXT:    store double [[ADD]], double* [[A]], align 4
3528 // CHECK12-NEXT:    ret void
3529 //
3530 //
3531 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
3532 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
3533 // CHECK12-NEXT:  entry:
3534 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3535 // CHECK12-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
3536 // CHECK12-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3537 // CHECK12-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3538 // CHECK12-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3539 // CHECK12-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3540 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3541 // CHECK12-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
3542 // CHECK12-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3543 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
3544 // CHECK12-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
3545 // CHECK12-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
3546 // CHECK12-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3547 // CHECK12:       omp_if.then:
3548 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
3549 // CHECK12-NEXT:    br label [[OMP_IF_END:%.*]]
3550 // CHECK12:       omp_if.else:
3551 // CHECK12-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3552 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3553 // CHECK12-NEXT:    call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]]
3554 // CHECK12-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3555 // CHECK12-NEXT:    br label [[OMP_IF_END]]
3556 // CHECK12:       omp_if.end:
3557 // CHECK12-NEXT:    ret void
3558 //
3559 //
3560 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
3561 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
3562 // CHECK12-NEXT:  entry:
3563 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3564 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3565 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3566 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3567 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3568 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3569 // CHECK12-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3570 // CHECK12-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3571 // CHECK12-NEXT:    store double 2.500000e+00, double* [[A]], align 4
3572 // CHECK12-NEXT:    ret void
3573 //
3574 //
3575 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
3576 // CHECK12-SAME: (i32 [[A:%.*]]) #[[ATTR0]] {
3577 // CHECK12-NEXT:  entry:
3578 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3579 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3580 // CHECK12-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
3581 // CHECK12-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
3582 // CHECK12-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
3583 // CHECK12-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
3584 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3585 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3586 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
3587 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
3588 // CHECK12-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3589 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
3590 // CHECK12-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]]
3591 // CHECK12-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
3592 // CHECK12-NEXT:    ret void
3593 //
3594 //
3595 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
3596 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
3597 // CHECK12-NEXT:  entry:
3598 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3599 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3600 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3601 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3602 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3603 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3604 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3605 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3606 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
3607 // CHECK12-NEXT:    ret void
3608 //
3609 //
3610 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
3611 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
3612 // CHECK12-NEXT:  entry:
3613 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3614 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3615 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3616 // CHECK12-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3617 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3618 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3619 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
3620 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3621 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3622 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3623 // CHECK12-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
3624 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
3625 // CHECK12-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
3626 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
3627 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
3628 // CHECK12-NEXT:    ret void
3629 //
3630 //
3631 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
3632 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
3633 // CHECK12-NEXT:  entry:
3634 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3635 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3636 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3637 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3638 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3639 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3640 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3641 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3642 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
3643 // CHECK12-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
3644 // CHECK12-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
3645 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3646 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
3647 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
3648 // CHECK12-NEXT:    ret void
3649 //
3650 //
3651 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
3652 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3653 // CHECK13-NEXT:  entry:
3654 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3655 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
3656 // CHECK13-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
3657 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3658 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
3659 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3660 // CHECK13-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
3661 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3662 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3663 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3664 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3665 // CHECK13-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
3666 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3667 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3668 // CHECK13-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
3669 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3670 // CHECK13-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
3671 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3672 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3673 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
3674 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
3675 // CHECK13-NEXT:    ret i32 [[TMP6]]
3676 //
3677 //
3678 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3679 // CHECK13-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3680 // CHECK13-NEXT:  entry:
3681 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3682 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3683 // CHECK13-NEXT:    [[B:%.*]] = alloca i32, align 4
3684 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3685 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
3686 // CHECK13-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3687 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3688 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3689 // CHECK13-NEXT:    store i32 1, i32* [[B]], align 4
3690 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3691 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
3692 // CHECK13-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
3693 // CHECK13-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
3694 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
3695 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
3696 // CHECK13-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3697 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3698 // CHECK13-NEXT:    store double [[ADD]], double* [[A]], align 8
3699 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3700 // CHECK13-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
3701 // CHECK13-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
3702 // CHECK13-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
3703 // CHECK13-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
3704 // CHECK13-NEXT:    store double 2.500000e+00, double* [[A5]], align 8
3705 // CHECK13-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
3706 // CHECK13-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 8
3707 // CHECK13-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
3708 // CHECK13-NEXT:    ret i32 [[CONV7]]
3709 //
3710 //
3711 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
3712 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
3713 // CHECK13-NEXT:  entry:
3714 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3715 // CHECK13-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3716 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3717 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3718 // CHECK13-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
3719 // CHECK13-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
3720 // CHECK13-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
3721 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3722 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3723 // CHECK13-NEXT:    ret i32 [[ADD]]
3724 //
3725 //
3726 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3727 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
3728 // CHECK13-NEXT:  entry:
3729 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3730 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
3731 // CHECK13-NEXT:    [[B:%.*]] = alloca i16, align 2
3732 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3733 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
3734 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3735 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3736 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3737 // CHECK13-NEXT:    store i16 1, i16* [[B]], align 2
3738 // CHECK13-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
3739 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
3740 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
3741 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
3742 // CHECK13-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
3743 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3744 // CHECK13-NEXT:    ret i32 [[TMP3]]
3745 //
3746 //
3747 // CHECK14-LABEL: define {{[^@]+}}@_Z3bari
3748 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3749 // CHECK14-NEXT:  entry:
3750 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3751 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
3752 // CHECK14-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
3753 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3754 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
3755 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3756 // CHECK14-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
3757 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3758 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3759 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3760 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3761 // CHECK14-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
3762 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3763 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3764 // CHECK14-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
3765 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3766 // CHECK14-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
3767 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3768 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3769 // CHECK14-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
3770 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
3771 // CHECK14-NEXT:    ret i32 [[TMP6]]
3772 //
3773 //
3774 // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3775 // CHECK14-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3776 // CHECK14-NEXT:  entry:
3777 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
3778 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3779 // CHECK14-NEXT:    [[B:%.*]] = alloca i32, align 4
3780 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3781 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
3782 // CHECK14-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
3783 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3784 // CHECK14-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
3785 // CHECK14-NEXT:    store i32 1, i32* [[B]], align 4
3786 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3787 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
3788 // CHECK14-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
3789 // CHECK14-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
3790 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
3791 // CHECK14-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
3792 // CHECK14-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3793 // CHECK14-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3794 // CHECK14-NEXT:    store double [[ADD]], double* [[A]], align 8
3795 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3796 // CHECK14-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
3797 // CHECK14-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
3798 // CHECK14-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
3799 // CHECK14-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
3800 // CHECK14-NEXT:    store double 2.500000e+00, double* [[A5]], align 8
3801 // CHECK14-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
3802 // CHECK14-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 8
3803 // CHECK14-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
3804 // CHECK14-NEXT:    ret i32 [[CONV7]]
3805 //
3806 //
3807 // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici
3808 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
3809 // CHECK14-NEXT:  entry:
3810 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3811 // CHECK14-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3812 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3813 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3814 // CHECK14-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
3815 // CHECK14-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
3816 // CHECK14-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
3817 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3818 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3819 // CHECK14-NEXT:    ret i32 [[ADD]]
3820 //
3821 //
3822 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3823 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
3824 // CHECK14-NEXT:  entry:
3825 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3826 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
3827 // CHECK14-NEXT:    [[B:%.*]] = alloca i16, align 2
3828 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3829 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
3830 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3831 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3832 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3833 // CHECK14-NEXT:    store i16 1, i16* [[B]], align 2
3834 // CHECK14-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
3835 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
3836 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
3837 // CHECK14-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
3838 // CHECK14-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
3839 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3840 // CHECK14-NEXT:    ret i32 [[TMP3]]
3841 //
3842 //
3843 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
3844 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3845 // CHECK15-NEXT:  entry:
3846 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3847 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
3848 // CHECK15-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
3849 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3850 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
3851 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3852 // CHECK15-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
3853 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3854 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3855 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3856 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3857 // CHECK15-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
3858 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3859 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3860 // CHECK15-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
3861 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3862 // CHECK15-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
3863 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3864 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3865 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
3866 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
3867 // CHECK15-NEXT:    ret i32 [[TMP6]]
3868 //
3869 //
3870 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3871 // CHECK15-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3872 // CHECK15-NEXT:  entry:
3873 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3874 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3875 // CHECK15-NEXT:    [[B:%.*]] = alloca i32, align 4
3876 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3877 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
3878 // CHECK15-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3879 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3880 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3881 // CHECK15-NEXT:    store i32 1, i32* [[B]], align 4
3882 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3883 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
3884 // CHECK15-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
3885 // CHECK15-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
3886 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
3887 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
3888 // CHECK15-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3889 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3890 // CHECK15-NEXT:    store double [[ADD]], double* [[A]], align 4
3891 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3892 // CHECK15-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
3893 // CHECK15-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
3894 // CHECK15-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
3895 // CHECK15-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
3896 // CHECK15-NEXT:    store double 2.500000e+00, double* [[A5]], align 4
3897 // CHECK15-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
3898 // CHECK15-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 4
3899 // CHECK15-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
3900 // CHECK15-NEXT:    ret i32 [[CONV7]]
3901 //
3902 //
3903 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
3904 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
3905 // CHECK15-NEXT:  entry:
3906 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3907 // CHECK15-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3908 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3909 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3910 // CHECK15-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
3911 // CHECK15-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
3912 // CHECK15-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
3913 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3914 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3915 // CHECK15-NEXT:    ret i32 [[ADD]]
3916 //
3917 //
3918 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3919 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
3920 // CHECK15-NEXT:  entry:
3921 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3922 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
3923 // CHECK15-NEXT:    [[B:%.*]] = alloca i16, align 2
3924 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3925 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
3926 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3927 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3928 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3929 // CHECK15-NEXT:    store i16 1, i16* [[B]], align 2
3930 // CHECK15-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
3931 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
3932 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
3933 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
3934 // CHECK15-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
3935 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3936 // CHECK15-NEXT:    ret i32 [[TMP3]]
3937 //
3938 //
3939 // CHECK16-LABEL: define {{[^@]+}}@_Z3bari
3940 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3941 // CHECK16-NEXT:  entry:
3942 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3943 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
3944 // CHECK16-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
3945 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3946 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
3947 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3948 // CHECK16-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
3949 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3950 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3951 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3952 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3953 // CHECK16-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
3954 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3955 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3956 // CHECK16-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
3957 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3958 // CHECK16-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
3959 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3960 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3961 // CHECK16-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
3962 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
3963 // CHECK16-NEXT:    ret i32 [[TMP6]]
3964 //
3965 //
3966 // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3967 // CHECK16-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3968 // CHECK16-NEXT:  entry:
3969 // CHECK16-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3970 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3971 // CHECK16-NEXT:    [[B:%.*]] = alloca i32, align 4
3972 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
3973 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
3974 // CHECK16-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3975 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3976 // CHECK16-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3977 // CHECK16-NEXT:    store i32 1, i32* [[B]], align 4
3978 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3979 // CHECK16-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
3980 // CHECK16-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
3981 // CHECK16-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
3982 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
3983 // CHECK16-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
3984 // CHECK16-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3985 // CHECK16-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3986 // CHECK16-NEXT:    store double [[ADD]], double* [[A]], align 4
3987 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3988 // CHECK16-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
3989 // CHECK16-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
3990 // CHECK16-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
3991 // CHECK16-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
3992 // CHECK16-NEXT:    store double 2.500000e+00, double* [[A5]], align 4
3993 // CHECK16-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
3994 // CHECK16-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 4
3995 // CHECK16-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
3996 // CHECK16-NEXT:    ret i32 [[CONV7]]
3997 //
3998 //
3999 // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici
4000 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4001 // CHECK16-NEXT:  entry:
4002 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4003 // CHECK16-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4004 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4005 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4006 // CHECK16-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
4007 // CHECK16-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
4008 // CHECK16-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
4009 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4010 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
4011 // CHECK16-NEXT:    ret i32 [[ADD]]
4012 //
4013 //
4014 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4015 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
4016 // CHECK16-NEXT:  entry:
4017 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4018 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
4019 // CHECK16-NEXT:    [[B:%.*]] = alloca i16, align 2
4020 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4021 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
4022 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4023 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4024 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4025 // CHECK16-NEXT:    store i16 1, i16* [[B]], align 2
4026 // CHECK16-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
4027 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4028 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
4029 // CHECK16-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
4030 // CHECK16-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
4031 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4032 // CHECK16-NEXT:    ret i32 [[TMP3]]
4033 //
4034 //
4035 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
4036 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
4037 // CHECK17-NEXT:  entry:
4038 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4039 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
4040 // CHECK17-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
4041 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4042 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
4043 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4044 // CHECK17-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
4045 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
4046 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4047 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4048 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4049 // CHECK17-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
4050 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4051 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4052 // CHECK17-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
4053 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4054 // CHECK17-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
4055 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4056 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4057 // CHECK17-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4058 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
4059 // CHECK17-NEXT:    ret i32 [[TMP6]]
4060 //
4061 //
4062 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4063 // CHECK17-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
4064 // CHECK17-NEXT:  entry:
4065 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4066 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4067 // CHECK17-NEXT:    [[B:%.*]] = alloca i32, align 4
4068 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4069 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
4070 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
4071 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
4072 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
4073 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
4074 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1
4075 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8
4076 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8
4077 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8
4078 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8
4079 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4080 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4081 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4082 // CHECK17-NEXT:    store i32 1, i32* [[B]], align 4
4083 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4084 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
4085 // CHECK17-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
4086 // CHECK17-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
4087 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
4088 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
4089 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV]], align 4
4090 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8
4091 // CHECK17-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4092 // CHECK17-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
4093 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
4094 // CHECK17-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
4095 // CHECK17-NEXT:    store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
4096 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
4097 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
4098 // CHECK17-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4099 // CHECK17-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1**
4100 // CHECK17-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8
4101 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4102 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double**
4103 // CHECK17-NEXT:    store double* [[A]], double** [[TMP8]], align 8
4104 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4105 // CHECK17-NEXT:    store i8* null, i8** [[TMP9]], align 8
4106 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4107 // CHECK17-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
4108 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP11]], align 8
4109 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4110 // CHECK17-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
4111 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP13]], align 8
4112 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
4113 // CHECK17-NEXT:    store i8* null, i8** [[TMP14]], align 8
4114 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4115 // CHECK17-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
4116 // CHECK17-NEXT:    store i64 [[TMP4]], i64* [[TMP16]], align 8
4117 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4118 // CHECK17-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
4119 // CHECK17-NEXT:    store i64 [[TMP4]], i64* [[TMP18]], align 8
4120 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
4121 // CHECK17-NEXT:    store i8* null, i8** [[TMP19]], align 8
4122 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4123 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4124 // CHECK17-NEXT:    [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4125 // CHECK17-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1
4126 // CHECK17-NEXT:    [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1
4127 // CHECK17-NEXT:    [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
4128 // CHECK17-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
4129 // CHECK17-NEXT:    br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4130 // CHECK17:       omp_offload.failed:
4131 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR2:[0-9]+]]
4132 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4133 // CHECK17:       omp_offload.cont:
4134 // CHECK17-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
4135 // CHECK17-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5
4136 // CHECK17-NEXT:    [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8
4137 // CHECK17-NEXT:    store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1
4138 // CHECK17-NEXT:    [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1
4139 // CHECK17-NEXT:    [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1
4140 // CHECK17-NEXT:    [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8*
4141 // CHECK17-NEXT:    [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8
4142 // CHECK17-NEXT:    store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1
4143 // CHECK17-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8
4144 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4
4145 // CHECK17-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4
4146 // CHECK17-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4147 // CHECK17:       omp_if.then:
4148 // CHECK17-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
4149 // CHECK17-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
4150 // CHECK17-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1**
4151 // CHECK17-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8
4152 // CHECK17-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
4153 // CHECK17-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
4154 // CHECK17-NEXT:    store double* [[A13]], double** [[TMP33]], align 8
4155 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0
4156 // CHECK17-NEXT:    store i8* null, i8** [[TMP34]], align 8
4157 // CHECK17-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
4158 // CHECK17-NEXT:    [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
4159 // CHECK17-NEXT:    store i64 [[TMP28]], i64* [[TMP36]], align 8
4160 // CHECK17-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
4161 // CHECK17-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
4162 // CHECK17-NEXT:    store i64 [[TMP28]], i64* [[TMP38]], align 8
4163 // CHECK17-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1
4164 // CHECK17-NEXT:    store i8* null, i8** [[TMP39]], align 8
4165 // CHECK17-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
4166 // CHECK17-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
4167 // CHECK17-NEXT:    [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1
4168 // CHECK17-NEXT:    [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1
4169 // CHECK17-NEXT:    [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1
4170 // CHECK17-NEXT:    [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]])
4171 // CHECK17-NEXT:    [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
4172 // CHECK17-NEXT:    br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
4173 // CHECK17:       omp_offload.failed18:
4174 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]]
4175 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT19]]
4176 // CHECK17:       omp_offload.cont19:
4177 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
4178 // CHECK17:       omp_if.else:
4179 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]]
4180 // CHECK17-NEXT:    br label [[OMP_IF_END]]
4181 // CHECK17:       omp_if.end:
4182 // CHECK17-NEXT:    [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
4183 // CHECK17-NEXT:    [[TMP46:%.*]] = load double, double* [[A20]], align 8
4184 // CHECK17-NEXT:    [[CONV21:%.*]] = fptosi double [[TMP46]] to i32
4185 // CHECK17-NEXT:    ret i32 [[CONV21]]
4186 //
4187 //
4188 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
4189 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
4190 // CHECK17-NEXT:  entry:
4191 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4192 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4193 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
4194 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
4195 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
4196 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
4197 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4198 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4199 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
4200 // CHECK17-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
4201 // CHECK17-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
4202 // CHECK17-NEXT:    [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4203 // CHECK17-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
4204 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
4205 // CHECK17-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8
4206 // CHECK17-NEXT:    store i8 [[FROMBOOL1]], i8* [[CONV]], align 1
4207 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
4208 // CHECK17-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4209 // CHECK17-NEXT:    [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
4210 // CHECK17-NEXT:    br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4211 // CHECK17:       omp_if.then:
4212 // CHECK17-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4213 // CHECK17-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
4214 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP5]], align 8
4215 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4216 // CHECK17-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
4217 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP7]], align 8
4218 // CHECK17-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4219 // CHECK17-NEXT:    store i8* null, i8** [[TMP8]], align 8
4220 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4221 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4222 // CHECK17-NEXT:    [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4223 // CHECK17-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1
4224 // CHECK17-NEXT:    [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
4225 // CHECK17-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]])
4226 // CHECK17-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
4227 // CHECK17-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4228 // CHECK17:       omp_offload.failed:
4229 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
4230 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4231 // CHECK17:       omp_offload.cont:
4232 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
4233 // CHECK17:       omp_if.else:
4234 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
4235 // CHECK17-NEXT:    br label [[OMP_IF_END]]
4236 // CHECK17:       omp_if.end:
4237 // CHECK17-NEXT:    [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4
4238 // CHECK17-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2
4239 // CHECK17-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2
4240 // CHECK17-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]]
4241 // CHECK17:       omp_if.then5:
4242 // CHECK17-NEXT:    [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
4243 // CHECK17-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
4244 // CHECK17-NEXT:    br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
4245 // CHECK17:       omp_offload.failed6:
4246 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
4247 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT7]]
4248 // CHECK17:       omp_offload.cont7:
4249 // CHECK17-NEXT:    br label [[OMP_IF_END9:%.*]]
4250 // CHECK17:       omp_if.else8:
4251 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
4252 // CHECK17-NEXT:    br label [[OMP_IF_END9]]
4253 // CHECK17:       omp_if.end9:
4254 // CHECK17-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
4255 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], 1
4256 // CHECK17-NEXT:    ret i32 [[ADD]]
4257 //
4258 //
4259 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4260 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
4261 // CHECK17-NEXT:  entry:
4262 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4263 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
4264 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4265 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
4266 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
4267 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
4268 // CHECK17-NEXT:    [[B:%.*]] = alloca i16, align 2
4269 // CHECK17-NEXT:    [[A_CASTED1:%.*]] = alloca i64, align 8
4270 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
4271 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8
4272 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8
4273 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8
4274 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4275 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
4276 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4277 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4278 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
4279 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
4280 // CHECK17-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4281 // CHECK17-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
4282 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP3]], align 8
4283 // CHECK17-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4284 // CHECK17-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
4285 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP5]], align 8
4286 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4287 // CHECK17-NEXT:    store i8* null, i8** [[TMP6]], align 8
4288 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4289 // CHECK17-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4290 // CHECK17-NEXT:    [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1)
4291 // CHECK17-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
4292 // CHECK17-NEXT:    br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4293 // CHECK17:       omp_offload.failed:
4294 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR2]]
4295 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4296 // CHECK17:       omp_offload.cont:
4297 // CHECK17-NEXT:    store i16 1, i16* [[B]], align 2
4298 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
4299 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32*
4300 // CHECK17-NEXT:    store i32 [[TMP11]], i32* [[CONV2]], align 4
4301 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8
4302 // CHECK17-NEXT:    [[TMP13:%.*]] = load i16, i16* [[B]], align 2
4303 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
4304 // CHECK17-NEXT:    store i16 [[TMP13]], i16* [[CONV3]], align 2
4305 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8
4306 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
4307 // CHECK17-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
4308 // CHECK17-NEXT:    store i64 [[TMP12]], i64* [[TMP16]], align 8
4309 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
4310 // CHECK17-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
4311 // CHECK17-NEXT:    store i64 [[TMP12]], i64* [[TMP18]], align 8
4312 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
4313 // CHECK17-NEXT:    store i8* null, i8** [[TMP19]], align 8
4314 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
4315 // CHECK17-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
4316 // CHECK17-NEXT:    store i64 [[TMP14]], i64* [[TMP21]], align 8
4317 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
4318 // CHECK17-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
4319 // CHECK17-NEXT:    store i64 [[TMP14]], i64* [[TMP23]], align 8
4320 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
4321 // CHECK17-NEXT:    store i8* null, i8** [[TMP24]], align 8
4322 // CHECK17-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
4323 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
4324 // CHECK17-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4325 // CHECK17-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4326 // CHECK17-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
4327 // CHECK17:       omp_offload.failed7:
4328 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR2]]
4329 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT8]]
4330 // CHECK17:       omp_offload.cont8:
4331 // CHECK17-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
4332 // CHECK17-NEXT:    ret i32 [[TMP29]]
4333 //
4334 //
4335 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
4336 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
4337 // CHECK17-NEXT:  entry:
4338 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4339 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
4340 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4341 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
4342 // CHECK17-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4343 // CHECK17-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
4344 // CHECK17-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
4345 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
4346 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4347 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
4348 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
4349 // CHECK17-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4350 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
4351 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
4352 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
4353 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
4354 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[CONV2]], align 4
4355 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
4356 // CHECK17-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
4357 // CHECK17-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
4358 // CHECK17-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4359 // CHECK17:       omp_if.then:
4360 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
4361 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
4362 // CHECK17:       omp_if.else:
4363 // CHECK17-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4364 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
4365 // CHECK17-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]]
4366 // CHECK17-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4367 // CHECK17-NEXT:    br label [[OMP_IF_END]]
4368 // CHECK17:       omp_if.end:
4369 // CHECK17-NEXT:    ret void
4370 //
4371 //
4372 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
4373 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
4374 // CHECK17-NEXT:  entry:
4375 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4376 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4377 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4378 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
4379 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4380 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4381 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4382 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
4383 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4384 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
4385 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
4386 // CHECK17-NEXT:    [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
4387 // CHECK17-NEXT:    [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
4388 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
4389 // CHECK17-NEXT:    store double [[ADD]], double* [[A]], align 8
4390 // CHECK17-NEXT:    ret void
4391 //
4392 //
4393 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
4394 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
4395 // CHECK17-NEXT:  entry:
4396 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4397 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4398 // CHECK17-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4399 // CHECK17-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
4400 // CHECK17-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
4401 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
4402 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4403 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
4404 // CHECK17-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4405 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
4406 // CHECK17-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
4407 // CHECK17-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
4408 // CHECK17-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4409 // CHECK17:       omp_if.then:
4410 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
4411 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
4412 // CHECK17:       omp_if.else:
4413 // CHECK17-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4414 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
4415 // CHECK17-NEXT:    call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]]
4416 // CHECK17-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4417 // CHECK17-NEXT:    br label [[OMP_IF_END]]
4418 // CHECK17:       omp_if.end:
4419 // CHECK17-NEXT:    ret void
4420 //
4421 //
4422 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1
4423 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
4424 // CHECK17-NEXT:  entry:
4425 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4426 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4427 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4428 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4429 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4430 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4431 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4432 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
4433 // CHECK17-NEXT:    store double 2.500000e+00, double* [[A]], align 8
4434 // CHECK17-NEXT:    ret void
4435 //
4436 //
4437 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
4438 // CHECK17-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
4439 // CHECK17-NEXT:  entry:
4440 // CHECK17-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4441 // CHECK17-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4442 // CHECK17-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
4443 // CHECK17-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
4444 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
4445 // CHECK17-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
4446 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
4447 // CHECK17-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
4448 // CHECK17-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
4449 // CHECK17-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4450 // CHECK17:       omp_if.then:
4451 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
4452 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
4453 // CHECK17:       omp_if.else:
4454 // CHECK17-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4455 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
4456 // CHECK17-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
4457 // CHECK17-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4458 // CHECK17-NEXT:    br label [[OMP_IF_END]]
4459 // CHECK17:       omp_if.end:
4460 // CHECK17-NEXT:    ret void
4461 //
4462 //
4463 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
4464 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
4465 // CHECK17-NEXT:  entry:
4466 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4467 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4468 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4469 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4470 // CHECK17-NEXT:    ret void
4471 //
4472 //
4473 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
4474 // CHECK17-SAME: () #[[ATTR1]] {
4475 // CHECK17-NEXT:  entry:
4476 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
4477 // CHECK17-NEXT:    ret void
4478 //
4479 //
4480 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
4481 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
4482 // CHECK17-NEXT:  entry:
4483 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4484 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4485 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4486 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4487 // CHECK17-NEXT:    ret void
4488 //
4489 //
4490 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
4491 // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR1]] {
4492 // CHECK17-NEXT:  entry:
4493 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4494 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4495 // CHECK17-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4496 // CHECK17-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
4497 // CHECK17-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
4498 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
4499 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4500 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4501 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
4502 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4503 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV1]], align 4
4504 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
4505 // CHECK17-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4506 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
4507 // CHECK17-NEXT:    call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]]
4508 // CHECK17-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4509 // CHECK17-NEXT:    ret void
4510 //
4511 //
4512 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..8
4513 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
4514 // CHECK17-NEXT:  entry:
4515 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4516 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4517 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4518 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4519 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4520 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4521 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4522 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
4523 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4524 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
4525 // CHECK17-NEXT:    ret void
4526 //
4527 //
4528 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
4529 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
4530 // CHECK17-NEXT:  entry:
4531 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4532 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
4533 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4534 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
4535 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4536 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
4537 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4538 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
4539 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
4540 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4541 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
4542 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
4543 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
4544 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
4545 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
4546 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
4547 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
4548 // CHECK17-NEXT:    ret void
4549 //
4550 //
4551 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
4552 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
4553 // CHECK17-NEXT:  entry:
4554 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4555 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4556 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
4557 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
4558 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4559 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4560 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
4561 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
4562 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
4563 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
4564 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
4565 // CHECK17-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
4566 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
4567 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
4568 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
4569 // CHECK17-NEXT:    ret void
4570 //
4571 //
4572 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4573 // CHECK17-SAME: () #[[ATTR3:[0-9]+]] {
4574 // CHECK17-NEXT:  entry:
4575 // CHECK17-NEXT:    call void @__tgt_register_requires(i64 1)
4576 // CHECK17-NEXT:    ret void
4577 //
4578 //
4579 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari
4580 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
4581 // CHECK18-NEXT:  entry:
4582 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4583 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
4584 // CHECK18-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
4585 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4586 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
4587 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4588 // CHECK18-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
4589 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
4590 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4591 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4592 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4593 // CHECK18-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
4594 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4595 // CHECK18-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4596 // CHECK18-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
4597 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4598 // CHECK18-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
4599 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4600 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4601 // CHECK18-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4602 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
4603 // CHECK18-NEXT:    ret i32 [[TMP6]]
4604 //
4605 //
4606 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4607 // CHECK18-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
4608 // CHECK18-NEXT:  entry:
4609 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4610 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4611 // CHECK18-NEXT:    [[B:%.*]] = alloca i32, align 4
4612 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4613 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
4614 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
4615 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
4616 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
4617 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
4618 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_5:%.*]] = alloca i8, align 1
4619 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED9:%.*]] = alloca i64, align 8
4620 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [2 x i8*], align 8
4621 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS15:%.*]] = alloca [2 x i8*], align 8
4622 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [2 x i8*], align 8
4623 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4624 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4625 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4626 // CHECK18-NEXT:    store i32 1, i32* [[B]], align 4
4627 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4628 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
4629 // CHECK18-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
4630 // CHECK18-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
4631 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
4632 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
4633 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV]], align 4
4634 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[B_CASTED]], align 8
4635 // CHECK18-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4636 // CHECK18-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
4637 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
4638 // CHECK18-NEXT:    [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8
4639 // CHECK18-NEXT:    store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1
4640 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
4641 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
4642 // CHECK18-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4643 // CHECK18-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1**
4644 // CHECK18-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 8
4645 // CHECK18-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4646 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double**
4647 // CHECK18-NEXT:    store double* [[A]], double** [[TMP8]], align 8
4648 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4649 // CHECK18-NEXT:    store i8* null, i8** [[TMP9]], align 8
4650 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4651 // CHECK18-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
4652 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP11]], align 8
4653 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4654 // CHECK18-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
4655 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP13]], align 8
4656 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
4657 // CHECK18-NEXT:    store i8* null, i8** [[TMP14]], align 8
4658 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4659 // CHECK18-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
4660 // CHECK18-NEXT:    store i64 [[TMP4]], i64* [[TMP16]], align 8
4661 // CHECK18-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4662 // CHECK18-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
4663 // CHECK18-NEXT:    store i64 [[TMP4]], i64* [[TMP18]], align 8
4664 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
4665 // CHECK18-NEXT:    store i8* null, i8** [[TMP19]], align 8
4666 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4667 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4668 // CHECK18-NEXT:    [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4669 // CHECK18-NEXT:    [[TOBOOL4:%.*]] = trunc i8 [[TMP22]] to i1
4670 // CHECK18-NEXT:    [[TMP23:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1
4671 // CHECK18-NEXT:    [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
4672 // CHECK18-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
4673 // CHECK18-NEXT:    br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4674 // CHECK18:       omp_offload.failed:
4675 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i64 [[TMP2]], i64 [[TMP4]]) #[[ATTR2:[0-9]+]]
4676 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4677 // CHECK18:       omp_offload.cont:
4678 // CHECK18-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
4679 // CHECK18-NEXT:    [[CMP6:%.*]] = icmp sgt i32 [[TMP26]], 5
4680 // CHECK18-NEXT:    [[FROMBOOL7:%.*]] = zext i1 [[CMP6]] to i8
4681 // CHECK18-NEXT:    store i8 [[FROMBOOL7]], i8* [[DOTCAPTURE_EXPR_5]], align 1
4682 // CHECK18-NEXT:    [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1
4683 // CHECK18-NEXT:    [[TOBOOL8:%.*]] = trunc i8 [[TMP27]] to i1
4684 // CHECK18-NEXT:    [[CONV10:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED9]] to i8*
4685 // CHECK18-NEXT:    [[FROMBOOL11:%.*]] = zext i1 [[TOBOOL8]] to i8
4686 // CHECK18-NEXT:    store i8 [[FROMBOOL11]], i8* [[CONV10]], align 1
4687 // CHECK18-NEXT:    [[TMP28:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED9]], align 8
4688 // CHECK18-NEXT:    [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4
4689 // CHECK18-NEXT:    [[CMP12:%.*]] = icmp sgt i32 [[TMP29]], 4
4690 // CHECK18-NEXT:    br i1 [[CMP12]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4691 // CHECK18:       omp_if.then:
4692 // CHECK18-NEXT:    [[A13:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
4693 // CHECK18-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
4694 // CHECK18-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1**
4695 // CHECK18-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 8
4696 // CHECK18-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
4697 // CHECK18-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
4698 // CHECK18-NEXT:    store double* [[A13]], double** [[TMP33]], align 8
4699 // CHECK18-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 0
4700 // CHECK18-NEXT:    store i8* null, i8** [[TMP34]], align 8
4701 // CHECK18-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1
4702 // CHECK18-NEXT:    [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i64*
4703 // CHECK18-NEXT:    store i64 [[TMP28]], i64* [[TMP36]], align 8
4704 // CHECK18-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1
4705 // CHECK18-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i64*
4706 // CHECK18-NEXT:    store i64 [[TMP28]], i64* [[TMP38]], align 8
4707 // CHECK18-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i64 0, i64 1
4708 // CHECK18-NEXT:    store i8* null, i8** [[TMP39]], align 8
4709 // CHECK18-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0
4710 // CHECK18-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0
4711 // CHECK18-NEXT:    [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_5]], align 1
4712 // CHECK18-NEXT:    [[TOBOOL17:%.*]] = trunc i8 [[TMP42]] to i1
4713 // CHECK18-NEXT:    [[TMP43:%.*]] = select i1 [[TOBOOL17]], i32 0, i32 1
4714 // CHECK18-NEXT:    [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]])
4715 // CHECK18-NEXT:    [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
4716 // CHECK18-NEXT:    br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]]
4717 // CHECK18:       omp_offload.failed18:
4718 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]]
4719 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT19]]
4720 // CHECK18:       omp_offload.cont19:
4721 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
4722 // CHECK18:       omp_if.else:
4723 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i64 [[TMP28]]) #[[ATTR2]]
4724 // CHECK18-NEXT:    br label [[OMP_IF_END]]
4725 // CHECK18:       omp_if.end:
4726 // CHECK18-NEXT:    [[A20:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
4727 // CHECK18-NEXT:    [[TMP46:%.*]] = load double, double* [[A20]], align 8
4728 // CHECK18-NEXT:    [[CONV21:%.*]] = fptosi double [[TMP46]] to i32
4729 // CHECK18-NEXT:    ret i32 [[CONV21]]
4730 //
4731 //
4732 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici
4733 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
4734 // CHECK18-NEXT:  entry:
4735 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4736 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
4737 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8
4738 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
4739 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
4740 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
4741 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4742 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4743 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
4744 // CHECK18-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
4745 // CHECK18-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
4746 // CHECK18-NEXT:    [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4747 // CHECK18-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
4748 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*
4749 // CHECK18-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8
4750 // CHECK18-NEXT:    store i8 [[FROMBOOL1]], i8* [[CONV]], align 1
4751 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8
4752 // CHECK18-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4753 // CHECK18-NEXT:    [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
4754 // CHECK18-NEXT:    br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4755 // CHECK18:       omp_if.then:
4756 // CHECK18-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4757 // CHECK18-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
4758 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP5]], align 8
4759 // CHECK18-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4760 // CHECK18-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i64*
4761 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP7]], align 8
4762 // CHECK18-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4763 // CHECK18-NEXT:    store i8* null, i8** [[TMP8]], align 8
4764 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4765 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4766 // CHECK18-NEXT:    [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
4767 // CHECK18-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1
4768 // CHECK18-NEXT:    [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
4769 // CHECK18-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]])
4770 // CHECK18-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
4771 // CHECK18-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4772 // CHECK18:       omp_offload.failed:
4773 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
4774 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4775 // CHECK18:       omp_offload.cont:
4776 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
4777 // CHECK18:       omp_if.else:
4778 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i64 [[TMP2]]) #[[ATTR2]]
4779 // CHECK18-NEXT:    br label [[OMP_IF_END]]
4780 // CHECK18:       omp_if.end:
4781 // CHECK18-NEXT:    [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4
4782 // CHECK18-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2
4783 // CHECK18-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2
4784 // CHECK18-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]]
4785 // CHECK18:       omp_if.then5:
4786 // CHECK18-NEXT:    [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
4787 // CHECK18-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
4788 // CHECK18-NEXT:    br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
4789 // CHECK18:       omp_offload.failed6:
4790 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
4791 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT7]]
4792 // CHECK18:       omp_offload.cont7:
4793 // CHECK18-NEXT:    br label [[OMP_IF_END9:%.*]]
4794 // CHECK18:       omp_if.else8:
4795 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
4796 // CHECK18-NEXT:    br label [[OMP_IF_END9]]
4797 // CHECK18:       omp_if.end9:
4798 // CHECK18-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
4799 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], 1
4800 // CHECK18-NEXT:    ret i32 [[ADD]]
4801 //
4802 //
4803 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4804 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
4805 // CHECK18-NEXT:  entry:
4806 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4807 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
4808 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
4809 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
4810 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
4811 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
4812 // CHECK18-NEXT:    [[B:%.*]] = alloca i16, align 2
4813 // CHECK18-NEXT:    [[A_CASTED1:%.*]] = alloca i64, align 8
4814 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
4815 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS4:%.*]] = alloca [2 x i8*], align 8
4816 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS5:%.*]] = alloca [2 x i8*], align 8
4817 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS6:%.*]] = alloca [2 x i8*], align 8
4818 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4819 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
4820 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4821 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
4822 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
4823 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
4824 // CHECK18-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4825 // CHECK18-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i64*
4826 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP3]], align 8
4827 // CHECK18-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4828 // CHECK18-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i64*
4829 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP5]], align 8
4830 // CHECK18-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
4831 // CHECK18-NEXT:    store i8* null, i8** [[TMP6]], align 8
4832 // CHECK18-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4833 // CHECK18-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4834 // CHECK18-NEXT:    [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1)
4835 // CHECK18-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
4836 // CHECK18-NEXT:    br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4837 // CHECK18:       omp_offload.failed:
4838 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i64 [[TMP1]]) #[[ATTR2]]
4839 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4840 // CHECK18:       omp_offload.cont:
4841 // CHECK18-NEXT:    store i16 1, i16* [[B]], align 2
4842 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
4843 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED1]] to i32*
4844 // CHECK18-NEXT:    store i32 [[TMP11]], i32* [[CONV2]], align 4
4845 // CHECK18-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED1]], align 8
4846 // CHECK18-NEXT:    [[TMP13:%.*]] = load i16, i16* [[B]], align 2
4847 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
4848 // CHECK18-NEXT:    store i16 [[TMP13]], i16* [[CONV3]], align 2
4849 // CHECK18-NEXT:    [[TMP14:%.*]] = load i64, i64* [[B_CASTED]], align 8
4850 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
4851 // CHECK18-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
4852 // CHECK18-NEXT:    store i64 [[TMP12]], i64* [[TMP16]], align 8
4853 // CHECK18-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
4854 // CHECK18-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
4855 // CHECK18-NEXT:    store i64 [[TMP12]], i64* [[TMP18]], align 8
4856 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 0
4857 // CHECK18-NEXT:    store i8* null, i8** [[TMP19]], align 8
4858 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 1
4859 // CHECK18-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i64*
4860 // CHECK18-NEXT:    store i64 [[TMP14]], i64* [[TMP21]], align 8
4861 // CHECK18-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 1
4862 // CHECK18-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
4863 // CHECK18-NEXT:    store i64 [[TMP14]], i64* [[TMP23]], align 8
4864 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS6]], i64 0, i64 1
4865 // CHECK18-NEXT:    store i8* null, i8** [[TMP24]], align 8
4866 // CHECK18-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS4]], i32 0, i32 0
4867 // CHECK18-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS5]], i32 0, i32 0
4868 // CHECK18-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4869 // CHECK18-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
4870 // CHECK18-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED7:%.*]], label [[OMP_OFFLOAD_CONT8:%.*]]
4871 // CHECK18:       omp_offload.failed7:
4872 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR2]]
4873 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT8]]
4874 // CHECK18:       omp_offload.cont8:
4875 // CHECK18-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
4876 // CHECK18-NEXT:    ret i32 [[TMP29]]
4877 //
4878 //
4879 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
4880 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
4881 // CHECK18-NEXT:  entry:
4882 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4883 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
4884 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4885 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
4886 // CHECK18-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4887 // CHECK18-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
4888 // CHECK18-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
4889 // CHECK18-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
4890 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4891 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
4892 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
4893 // CHECK18-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4894 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
4895 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
4896 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
4897 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
4898 // CHECK18-NEXT:    store i32 [[TMP2]], i32* [[CONV2]], align 4
4899 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
4900 // CHECK18-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
4901 // CHECK18-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
4902 // CHECK18-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4903 // CHECK18:       omp_if.then:
4904 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
4905 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
4906 // CHECK18:       omp_if.else:
4907 // CHECK18-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4908 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
4909 // CHECK18-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR2]]
4910 // CHECK18-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4911 // CHECK18-NEXT:    br label [[OMP_IF_END]]
4912 // CHECK18:       omp_if.end:
4913 // CHECK18-NEXT:    ret void
4914 //
4915 //
4916 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
4917 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
4918 // CHECK18-NEXT:  entry:
4919 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4920 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4921 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4922 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
4923 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4924 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4925 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4926 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
4927 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4928 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
4929 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
4930 // CHECK18-NEXT:    [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
4931 // CHECK18-NEXT:    [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
4932 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
4933 // CHECK18-NEXT:    store double [[ADD]], double* [[A]], align 8
4934 // CHECK18-NEXT:    ret void
4935 //
4936 //
4937 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
4938 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
4939 // CHECK18-NEXT:  entry:
4940 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4941 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4942 // CHECK18-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4943 // CHECK18-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
4944 // CHECK18-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
4945 // CHECK18-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
4946 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4947 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
4948 // CHECK18-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4949 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
4950 // CHECK18-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
4951 // CHECK18-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
4952 // CHECK18-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4953 // CHECK18:       omp_if.then:
4954 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
4955 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
4956 // CHECK18:       omp_if.else:
4957 // CHECK18-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4958 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
4959 // CHECK18-NEXT:    call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]]
4960 // CHECK18-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4961 // CHECK18-NEXT:    br label [[OMP_IF_END]]
4962 // CHECK18:       omp_if.end:
4963 // CHECK18-NEXT:    ret void
4964 //
4965 //
4966 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..1
4967 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
4968 // CHECK18-NEXT:  entry:
4969 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
4970 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
4971 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4972 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
4973 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
4974 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4975 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4976 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
4977 // CHECK18-NEXT:    store double 2.500000e+00, double* [[A]], align 8
4978 // CHECK18-NEXT:    ret void
4979 //
4980 //
4981 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
4982 // CHECK18-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
4983 // CHECK18-NEXT:  entry:
4984 // CHECK18-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
4985 // CHECK18-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
4986 // CHECK18-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
4987 // CHECK18-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
4988 // CHECK18-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
4989 // CHECK18-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
4990 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
4991 // CHECK18-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
4992 // CHECK18-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
4993 // CHECK18-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4994 // CHECK18:       omp_if.then:
4995 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
4996 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
4997 // CHECK18:       omp_if.else:
4998 // CHECK18-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
4999 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
5000 // CHECK18-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
5001 // CHECK18-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5002 // CHECK18-NEXT:    br label [[OMP_IF_END]]
5003 // CHECK18:       omp_if.end:
5004 // CHECK18-NEXT:    ret void
5005 //
5006 //
5007 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
5008 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
5009 // CHECK18-NEXT:  entry:
5010 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5011 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5012 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5013 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5014 // CHECK18-NEXT:    ret void
5015 //
5016 //
5017 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
5018 // CHECK18-SAME: () #[[ATTR1]] {
5019 // CHECK18-NEXT:  entry:
5020 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
5021 // CHECK18-NEXT:    ret void
5022 //
5023 //
5024 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
5025 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
5026 // CHECK18-NEXT:  entry:
5027 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5028 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5029 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5030 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5031 // CHECK18-NEXT:    ret void
5032 //
5033 //
5034 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
5035 // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR1]] {
5036 // CHECK18-NEXT:  entry:
5037 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5038 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5039 // CHECK18-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
5040 // CHECK18-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
5041 // CHECK18-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
5042 // CHECK18-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
5043 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5044 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5045 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
5046 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5047 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV1]], align 4
5048 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
5049 // CHECK18-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5050 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
5051 // CHECK18-NEXT:    call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR2]]
5052 // CHECK18-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5053 // CHECK18-NEXT:    ret void
5054 //
5055 //
5056 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..8
5057 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR1]] {
5058 // CHECK18-NEXT:  entry:
5059 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5060 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5061 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5062 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5063 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5064 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5065 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5066 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5067 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5068 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
5069 // CHECK18-NEXT:    ret void
5070 //
5071 //
5072 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
5073 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
5074 // CHECK18-NEXT:  entry:
5075 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5076 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5077 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5078 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
5079 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5080 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
5081 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5082 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
5083 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5084 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5085 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
5086 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
5087 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
5088 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
5089 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
5090 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
5091 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
5092 // CHECK18-NEXT:    ret void
5093 //
5094 //
5095 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
5096 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR1]] {
5097 // CHECK18-NEXT:  entry:
5098 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5099 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5100 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5101 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5102 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5103 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5104 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5105 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
5106 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5107 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
5108 // CHECK18-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
5109 // CHECK18-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
5110 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
5111 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
5112 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
5113 // CHECK18-NEXT:    ret void
5114 //
5115 //
5116 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5117 // CHECK18-SAME: () #[[ATTR3:[0-9]+]] {
5118 // CHECK18-NEXT:  entry:
5119 // CHECK18-NEXT:    call void @__tgt_register_requires(i64 1)
5120 // CHECK18-NEXT:    ret void
5121 //
5122 //
5123 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari
5124 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
5125 // CHECK19-NEXT:  entry:
5126 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5127 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
5128 // CHECK19-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
5129 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5130 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
5131 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5132 // CHECK19-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
5133 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
5134 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
5135 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
5136 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5137 // CHECK19-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
5138 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
5139 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
5140 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
5141 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
5142 // CHECK19-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
5143 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
5144 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
5145 // CHECK19-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
5146 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
5147 // CHECK19-NEXT:    ret i32 [[TMP6]]
5148 //
5149 //
5150 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
5151 // CHECK19-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
5152 // CHECK19-NEXT:  entry:
5153 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5154 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5155 // CHECK19-NEXT:    [[B:%.*]] = alloca i32, align 4
5156 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5157 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5158 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5159 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
5160 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
5161 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
5162 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1
5163 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4
5164 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4
5165 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4
5166 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4
5167 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5168 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5169 // CHECK19-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5170 // CHECK19-NEXT:    store i32 1, i32* [[B]], align 4
5171 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5172 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
5173 // CHECK19-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
5174 // CHECK19-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
5175 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
5176 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[B_CASTED]], align 4
5177 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4
5178 // CHECK19-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5179 // CHECK19-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
5180 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
5181 // CHECK19-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
5182 // CHECK19-NEXT:    store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
5183 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5184 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
5185 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5186 // CHECK19-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1**
5187 // CHECK19-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4
5188 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5189 // CHECK19-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double**
5190 // CHECK19-NEXT:    store double* [[A]], double** [[TMP8]], align 4
5191 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5192 // CHECK19-NEXT:    store i8* null, i8** [[TMP9]], align 4
5193 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5194 // CHECK19-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
5195 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[TMP11]], align 4
5196 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5197 // CHECK19-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
5198 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[TMP13]], align 4
5199 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5200 // CHECK19-NEXT:    store i8* null, i8** [[TMP14]], align 4
5201 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5202 // CHECK19-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
5203 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[TMP16]], align 4
5204 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5205 // CHECK19-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
5206 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[TMP18]], align 4
5207 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5208 // CHECK19-NEXT:    store i8* null, i8** [[TMP19]], align 4
5209 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5210 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5211 // CHECK19-NEXT:    [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5212 // CHECK19-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1
5213 // CHECK19-NEXT:    [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
5214 // CHECK19-NEXT:    [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
5215 // CHECK19-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
5216 // CHECK19-NEXT:    br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5217 // CHECK19:       omp_offload.failed:
5218 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR2:[0-9]+]]
5219 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5220 // CHECK19:       omp_offload.cont:
5221 // CHECK19-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
5222 // CHECK19-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5
5223 // CHECK19-NEXT:    [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8
5224 // CHECK19-NEXT:    store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1
5225 // CHECK19-NEXT:    [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1
5226 // CHECK19-NEXT:    [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1
5227 // CHECK19-NEXT:    [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8*
5228 // CHECK19-NEXT:    [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8
5229 // CHECK19-NEXT:    store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1
5230 // CHECK19-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4
5231 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4
5232 // CHECK19-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4
5233 // CHECK19-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5234 // CHECK19:       omp_if.then:
5235 // CHECK19-NEXT:    [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
5236 // CHECK19-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
5237 // CHECK19-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1**
5238 // CHECK19-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4
5239 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
5240 // CHECK19-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
5241 // CHECK19-NEXT:    store double* [[A12]], double** [[TMP33]], align 4
5242 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
5243 // CHECK19-NEXT:    store i8* null, i8** [[TMP34]], align 4
5244 // CHECK19-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
5245 // CHECK19-NEXT:    [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32*
5246 // CHECK19-NEXT:    store i32 [[TMP28]], i32* [[TMP36]], align 4
5247 // CHECK19-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
5248 // CHECK19-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32*
5249 // CHECK19-NEXT:    store i32 [[TMP28]], i32* [[TMP38]], align 4
5250 // CHECK19-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1
5251 // CHECK19-NEXT:    store i8* null, i8** [[TMP39]], align 4
5252 // CHECK19-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
5253 // CHECK19-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
5254 // CHECK19-NEXT:    [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1
5255 // CHECK19-NEXT:    [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1
5256 // CHECK19-NEXT:    [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1
5257 // CHECK19-NEXT:    [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]])
5258 // CHECK19-NEXT:    [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
5259 // CHECK19-NEXT:    br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
5260 // CHECK19:       omp_offload.failed17:
5261 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]]
5262 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
5263 // CHECK19:       omp_offload.cont18:
5264 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
5265 // CHECK19:       omp_if.else:
5266 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]]
5267 // CHECK19-NEXT:    br label [[OMP_IF_END]]
5268 // CHECK19:       omp_if.end:
5269 // CHECK19-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
5270 // CHECK19-NEXT:    [[TMP46:%.*]] = load double, double* [[A19]], align 4
5271 // CHECK19-NEXT:    [[CONV20:%.*]] = fptosi double [[TMP46]] to i32
5272 // CHECK19-NEXT:    ret i32 [[CONV20]]
5273 //
5274 //
5275 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
5276 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
5277 // CHECK19-NEXT:  entry:
5278 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5279 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5280 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5281 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
5282 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
5283 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
5284 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5285 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5286 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
5287 // CHECK19-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
5288 // CHECK19-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
5289 // CHECK19-NEXT:    [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5290 // CHECK19-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
5291 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
5292 // CHECK19-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8
5293 // CHECK19-NEXT:    store i8 [[FROMBOOL1]], i8* [[CONV]], align 1
5294 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5295 // CHECK19-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5296 // CHECK19-NEXT:    [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
5297 // CHECK19-NEXT:    br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5298 // CHECK19:       omp_if.then:
5299 // CHECK19-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5300 // CHECK19-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
5301 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[TMP5]], align 4
5302 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5303 // CHECK19-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
5304 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[TMP7]], align 4
5305 // CHECK19-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5306 // CHECK19-NEXT:    store i8* null, i8** [[TMP8]], align 4
5307 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5308 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5309 // CHECK19-NEXT:    [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5310 // CHECK19-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1
5311 // CHECK19-NEXT:    [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
5312 // CHECK19-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]])
5313 // CHECK19-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
5314 // CHECK19-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5315 // CHECK19:       omp_offload.failed:
5316 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
5317 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5318 // CHECK19:       omp_offload.cont:
5319 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
5320 // CHECK19:       omp_if.else:
5321 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
5322 // CHECK19-NEXT:    br label [[OMP_IF_END]]
5323 // CHECK19:       omp_if.end:
5324 // CHECK19-NEXT:    [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4
5325 // CHECK19-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2
5326 // CHECK19-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2
5327 // CHECK19-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]]
5328 // CHECK19:       omp_if.then5:
5329 // CHECK19-NEXT:    [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
5330 // CHECK19-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
5331 // CHECK19-NEXT:    br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
5332 // CHECK19:       omp_offload.failed6:
5333 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
5334 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT7]]
5335 // CHECK19:       omp_offload.cont7:
5336 // CHECK19-NEXT:    br label [[OMP_IF_END9:%.*]]
5337 // CHECK19:       omp_if.else8:
5338 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
5339 // CHECK19-NEXT:    br label [[OMP_IF_END9]]
5340 // CHECK19:       omp_if.end9:
5341 // CHECK19-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
5342 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], 1
5343 // CHECK19-NEXT:    ret i32 [[ADD]]
5344 //
5345 //
5346 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
5347 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
5348 // CHECK19-NEXT:  entry:
5349 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5350 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
5351 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5352 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
5353 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
5354 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
5355 // CHECK19-NEXT:    [[B:%.*]] = alloca i16, align 2
5356 // CHECK19-NEXT:    [[A_CASTED1:%.*]] = alloca i32, align 4
5357 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5358 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4
5359 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4
5360 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4
5361 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5362 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
5363 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
5364 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
5365 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
5366 // CHECK19-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5367 // CHECK19-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
5368 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP3]], align 4
5369 // CHECK19-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5370 // CHECK19-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
5371 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP5]], align 4
5372 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5373 // CHECK19-NEXT:    store i8* null, i8** [[TMP6]], align 4
5374 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5375 // CHECK19-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5376 // CHECK19-NEXT:    [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1)
5377 // CHECK19-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
5378 // CHECK19-NEXT:    br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5379 // CHECK19:       omp_offload.failed:
5380 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR2]]
5381 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5382 // CHECK19:       omp_offload.cont:
5383 // CHECK19-NEXT:    store i16 1, i16* [[B]], align 2
5384 // CHECK19-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
5385 // CHECK19-NEXT:    store i32 [[TMP11]], i32* [[A_CASTED1]], align 4
5386 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4
5387 // CHECK19-NEXT:    [[TMP13:%.*]] = load i16, i16* [[B]], align 2
5388 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
5389 // CHECK19-NEXT:    store i16 [[TMP13]], i16* [[CONV]], align 2
5390 // CHECK19-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4
5391 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
5392 // CHECK19-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
5393 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[TMP16]], align 4
5394 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
5395 // CHECK19-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
5396 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[TMP18]], align 4
5397 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
5398 // CHECK19-NEXT:    store i8* null, i8** [[TMP19]], align 4
5399 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
5400 // CHECK19-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
5401 // CHECK19-NEXT:    store i32 [[TMP14]], i32* [[TMP21]], align 4
5402 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
5403 // CHECK19-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
5404 // CHECK19-NEXT:    store i32 [[TMP14]], i32* [[TMP23]], align 4
5405 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
5406 // CHECK19-NEXT:    store i8* null, i8** [[TMP24]], align 4
5407 // CHECK19-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
5408 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
5409 // CHECK19-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
5410 // CHECK19-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
5411 // CHECK19-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
5412 // CHECK19:       omp_offload.failed5:
5413 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR2]]
5414 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT6]]
5415 // CHECK19:       omp_offload.cont6:
5416 // CHECK19-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
5417 // CHECK19-NEXT:    ret i32 [[TMP29]]
5418 //
5419 //
5420 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
5421 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
5422 // CHECK19-NEXT:  entry:
5423 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5424 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5425 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
5426 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5427 // CHECK19-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
5428 // CHECK19-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
5429 // CHECK19-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
5430 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
5431 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5432 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5433 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5434 // CHECK19-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5435 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
5436 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
5437 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[B_CASTED]], align 4
5438 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
5439 // CHECK19-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
5440 // CHECK19-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
5441 // CHECK19-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5442 // CHECK19:       omp_if.then:
5443 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
5444 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
5445 // CHECK19:       omp_if.else:
5446 // CHECK19-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5447 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
5448 // CHECK19-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]]
5449 // CHECK19-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5450 // CHECK19-NEXT:    br label [[OMP_IF_END]]
5451 // CHECK19:       omp_if.end:
5452 // CHECK19-NEXT:    ret void
5453 //
5454 //
5455 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
5456 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
5457 // CHECK19-NEXT:  entry:
5458 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5459 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5460 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5461 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5462 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5463 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5464 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5465 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5466 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5467 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
5468 // CHECK19-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
5469 // CHECK19-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
5470 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
5471 // CHECK19-NEXT:    store double [[ADD]], double* [[A]], align 4
5472 // CHECK19-NEXT:    ret void
5473 //
5474 //
5475 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
5476 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
5477 // CHECK19-NEXT:  entry:
5478 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5479 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
5480 // CHECK19-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
5481 // CHECK19-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
5482 // CHECK19-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
5483 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
5484 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5485 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5486 // CHECK19-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5487 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
5488 // CHECK19-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
5489 // CHECK19-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
5490 // CHECK19-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5491 // CHECK19:       omp_if.then:
5492 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
5493 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
5494 // CHECK19:       omp_if.else:
5495 // CHECK19-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5496 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
5497 // CHECK19-NEXT:    call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]]
5498 // CHECK19-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5499 // CHECK19-NEXT:    br label [[OMP_IF_END]]
5500 // CHECK19:       omp_if.end:
5501 // CHECK19-NEXT:    ret void
5502 //
5503 //
5504 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1
5505 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
5506 // CHECK19-NEXT:  entry:
5507 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5508 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5509 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5510 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5511 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5512 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5513 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5514 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
5515 // CHECK19-NEXT:    store double 2.500000e+00, double* [[A]], align 4
5516 // CHECK19-NEXT:    ret void
5517 //
5518 //
5519 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
5520 // CHECK19-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
5521 // CHECK19-NEXT:  entry:
5522 // CHECK19-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
5523 // CHECK19-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
5524 // CHECK19-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
5525 // CHECK19-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
5526 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
5527 // CHECK19-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5528 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
5529 // CHECK19-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
5530 // CHECK19-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
5531 // CHECK19-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5532 // CHECK19:       omp_if.then:
5533 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
5534 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
5535 // CHECK19:       omp_if.else:
5536 // CHECK19-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5537 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
5538 // CHECK19-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
5539 // CHECK19-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5540 // CHECK19-NEXT:    br label [[OMP_IF_END]]
5541 // CHECK19:       omp_if.end:
5542 // CHECK19-NEXT:    ret void
5543 //
5544 //
5545 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
5546 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
5547 // CHECK19-NEXT:  entry:
5548 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5549 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5550 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5551 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5552 // CHECK19-NEXT:    ret void
5553 //
5554 //
5555 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
5556 // CHECK19-SAME: () #[[ATTR1]] {
5557 // CHECK19-NEXT:  entry:
5558 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
5559 // CHECK19-NEXT:    ret void
5560 //
5561 //
5562 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7
5563 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
5564 // CHECK19-NEXT:  entry:
5565 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5566 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5567 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5568 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5569 // CHECK19-NEXT:    ret void
5570 //
5571 //
5572 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
5573 // CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
5574 // CHECK19-NEXT:  entry:
5575 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5576 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5577 // CHECK19-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
5578 // CHECK19-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
5579 // CHECK19-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
5580 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
5581 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5582 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5583 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
5584 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
5585 // CHECK19-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5586 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
5587 // CHECK19-NEXT:    call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]]
5588 // CHECK19-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5589 // CHECK19-NEXT:    ret void
5590 //
5591 //
5592 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..8
5593 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
5594 // CHECK19-NEXT:  entry:
5595 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5596 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5597 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5598 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5599 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5600 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5601 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5602 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5603 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
5604 // CHECK19-NEXT:    ret void
5605 //
5606 //
5607 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
5608 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
5609 // CHECK19-NEXT:  entry:
5610 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5611 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5612 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5613 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5614 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5615 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5616 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
5617 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
5618 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
5619 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
5620 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
5621 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
5622 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
5623 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
5624 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
5625 // CHECK19-NEXT:    ret void
5626 //
5627 //
5628 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
5629 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
5630 // CHECK19-NEXT:  entry:
5631 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5632 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5633 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
5634 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5635 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5636 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5637 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
5638 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5639 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
5640 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
5641 // CHECK19-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
5642 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
5643 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
5644 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
5645 // CHECK19-NEXT:    ret void
5646 //
5647 //
5648 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
5649 // CHECK19-SAME: () #[[ATTR3:[0-9]+]] {
5650 // CHECK19-NEXT:  entry:
5651 // CHECK19-NEXT:    call void @__tgt_register_requires(i64 1)
5652 // CHECK19-NEXT:    ret void
5653 //
5654 //
5655 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari
5656 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
5657 // CHECK20-NEXT:  entry:
5658 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5659 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
5660 // CHECK20-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
5661 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5662 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
5663 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5664 // CHECK20-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
5665 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
5666 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
5667 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
5668 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5669 // CHECK20-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
5670 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
5671 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
5672 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
5673 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
5674 // CHECK20-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
5675 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
5676 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
5677 // CHECK20-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
5678 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
5679 // CHECK20-NEXT:    ret i32 [[TMP6]]
5680 //
5681 //
5682 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
5683 // CHECK20-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
5684 // CHECK20-NEXT:  entry:
5685 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5686 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5687 // CHECK20-NEXT:    [[B:%.*]] = alloca i32, align 4
5688 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5689 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5690 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5691 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
5692 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
5693 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
5694 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_4:%.*]] = alloca i8, align 1
5695 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED8:%.*]] = alloca i32, align 4
5696 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [2 x i8*], align 4
5697 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [2 x i8*], align 4
5698 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [2 x i8*], align 4
5699 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5700 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5701 // CHECK20-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5702 // CHECK20-NEXT:    store i32 1, i32* [[B]], align 4
5703 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5704 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
5705 // CHECK20-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
5706 // CHECK20-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
5707 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
5708 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[B_CASTED]], align 4
5709 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_CASTED]], align 4
5710 // CHECK20-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5711 // CHECK20-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP3]] to i1
5712 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
5713 // CHECK20-NEXT:    [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8
5714 // CHECK20-NEXT:    store i8 [[FROMBOOL2]], i8* [[CONV]], align 1
5715 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5716 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
5717 // CHECK20-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5718 // CHECK20-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to %struct.S1**
5719 // CHECK20-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP6]], align 4
5720 // CHECK20-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5721 // CHECK20-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to double**
5722 // CHECK20-NEXT:    store double* [[A]], double** [[TMP8]], align 4
5723 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5724 // CHECK20-NEXT:    store i8* null, i8** [[TMP9]], align 4
5725 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
5726 // CHECK20-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
5727 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[TMP11]], align 4
5728 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
5729 // CHECK20-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
5730 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[TMP13]], align 4
5731 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
5732 // CHECK20-NEXT:    store i8* null, i8** [[TMP14]], align 4
5733 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
5734 // CHECK20-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
5735 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[TMP16]], align 4
5736 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
5737 // CHECK20-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
5738 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[TMP18]], align 4
5739 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
5740 // CHECK20-NEXT:    store i8* null, i8** [[TMP19]], align 4
5741 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5742 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5743 // CHECK20-NEXT:    [[TMP22:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5744 // CHECK20-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP22]] to i1
5745 // CHECK20-NEXT:    [[TMP23:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
5746 // CHECK20-NEXT:    [[TMP24:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1:[0-9]+]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP23]])
5747 // CHECK20-NEXT:    [[TMP25:%.*]] = icmp ne i32 [[TMP24]], 0
5748 // CHECK20-NEXT:    br i1 [[TMP25]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5749 // CHECK20:       omp_offload.failed:
5750 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121(%struct.S1* [[THIS1]], i32 [[TMP2]], i32 [[TMP4]]) #[[ATTR2:[0-9]+]]
5751 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5752 // CHECK20:       omp_offload.cont:
5753 // CHECK20-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
5754 // CHECK20-NEXT:    [[CMP5:%.*]] = icmp sgt i32 [[TMP26]], 5
5755 // CHECK20-NEXT:    [[FROMBOOL6:%.*]] = zext i1 [[CMP5]] to i8
5756 // CHECK20-NEXT:    store i8 [[FROMBOOL6]], i8* [[DOTCAPTURE_EXPR_4]], align 1
5757 // CHECK20-NEXT:    [[TMP27:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1
5758 // CHECK20-NEXT:    [[TOBOOL7:%.*]] = trunc i8 [[TMP27]] to i1
5759 // CHECK20-NEXT:    [[CONV9:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED8]] to i8*
5760 // CHECK20-NEXT:    [[FROMBOOL10:%.*]] = zext i1 [[TOBOOL7]] to i8
5761 // CHECK20-NEXT:    store i8 [[FROMBOOL10]], i8* [[CONV9]], align 1
5762 // CHECK20-NEXT:    [[TMP28:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED8]], align 4
5763 // CHECK20-NEXT:    [[TMP29:%.*]] = load i32, i32* [[N_ADDR]], align 4
5764 // CHECK20-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP29]], 4
5765 // CHECK20-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5766 // CHECK20:       omp_if.then:
5767 // CHECK20-NEXT:    [[A12:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
5768 // CHECK20-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
5769 // CHECK20-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to %struct.S1**
5770 // CHECK20-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP31]], align 4
5771 // CHECK20-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
5772 // CHECK20-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to double**
5773 // CHECK20-NEXT:    store double* [[A12]], double** [[TMP33]], align 4
5774 // CHECK20-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
5775 // CHECK20-NEXT:    store i8* null, i8** [[TMP34]], align 4
5776 // CHECK20-NEXT:    [[TMP35:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
5777 // CHECK20-NEXT:    [[TMP36:%.*]] = bitcast i8** [[TMP35]] to i32*
5778 // CHECK20-NEXT:    store i32 [[TMP28]], i32* [[TMP36]], align 4
5779 // CHECK20-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
5780 // CHECK20-NEXT:    [[TMP38:%.*]] = bitcast i8** [[TMP37]] to i32*
5781 // CHECK20-NEXT:    store i32 [[TMP28]], i32* [[TMP38]], align 4
5782 // CHECK20-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1
5783 // CHECK20-NEXT:    store i8* null, i8** [[TMP39]], align 4
5784 // CHECK20-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
5785 // CHECK20-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
5786 // CHECK20-NEXT:    [[TMP42:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_4]], align 1
5787 // CHECK20-NEXT:    [[TOBOOL16:%.*]] = trunc i8 [[TMP42]] to i1
5788 // CHECK20-NEXT:    [[TMP43:%.*]] = select i1 [[TOBOOL16]], i32 0, i32 1
5789 // CHECK20-NEXT:    [[TMP44:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126.region_id, i32 2, i8** [[TMP40]], i8** [[TMP41]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.2, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.3, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP43]])
5790 // CHECK20-NEXT:    [[TMP45:%.*]] = icmp ne i32 [[TMP44]], 0
5791 // CHECK20-NEXT:    br i1 [[TMP45]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]]
5792 // CHECK20:       omp_offload.failed17:
5793 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]]
5794 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT18]]
5795 // CHECK20:       omp_offload.cont18:
5796 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
5797 // CHECK20:       omp_if.else:
5798 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126(%struct.S1* [[THIS1]], i32 [[TMP28]]) #[[ATTR2]]
5799 // CHECK20-NEXT:    br label [[OMP_IF_END]]
5800 // CHECK20:       omp_if.end:
5801 // CHECK20-NEXT:    [[A19:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
5802 // CHECK20-NEXT:    [[TMP46:%.*]] = load double, double* [[A19]], align 4
5803 // CHECK20-NEXT:    [[CONV20:%.*]] = fptosi double [[TMP46]] to i32
5804 // CHECK20-NEXT:    ret i32 [[CONV20]]
5805 //
5806 //
5807 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici
5808 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
5809 // CHECK20-NEXT:  entry:
5810 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5811 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
5812 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4
5813 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
5814 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
5815 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
5816 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5817 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5818 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
5819 // CHECK20-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
5820 // CHECK20-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
5821 // CHECK20-NEXT:    [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5822 // CHECK20-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
5823 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8*
5824 // CHECK20-NEXT:    [[FROMBOOL1:%.*]] = zext i1 [[TOBOOL]] to i8
5825 // CHECK20-NEXT:    store i8 [[FROMBOOL1]], i8* [[CONV]], align 1
5826 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4
5827 // CHECK20-NEXT:    [[TMP3:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5828 // CHECK20-NEXT:    [[TOBOOL2:%.*]] = trunc i8 [[TMP3]] to i1
5829 // CHECK20-NEXT:    br i1 [[TOBOOL2]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5830 // CHECK20:       omp_if.then:
5831 // CHECK20-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5832 // CHECK20-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
5833 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[TMP5]], align 4
5834 // CHECK20-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5835 // CHECK20-NEXT:    [[TMP7:%.*]] = bitcast i8** [[TMP6]] to i32*
5836 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[TMP7]], align 4
5837 // CHECK20-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5838 // CHECK20-NEXT:    store i8* null, i8** [[TMP8]], align 4
5839 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5840 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5841 // CHECK20-NEXT:    [[TMP11:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1
5842 // CHECK20-NEXT:    [[TOBOOL3:%.*]] = trunc i8 [[TMP11]] to i1
5843 // CHECK20-NEXT:    [[TMP12:%.*]] = select i1 [[TOBOOL3]], i32 0, i32 1
5844 // CHECK20-NEXT:    [[TMP13:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104.region_id, i32 1, i8** [[TMP9]], i8** [[TMP10]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP12]])
5845 // CHECK20-NEXT:    [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0
5846 // CHECK20-NEXT:    br i1 [[TMP14]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5847 // CHECK20:       omp_offload.failed:
5848 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
5849 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5850 // CHECK20:       omp_offload.cont:
5851 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
5852 // CHECK20:       omp_if.else:
5853 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104(i32 [[TMP2]]) #[[ATTR2]]
5854 // CHECK20-NEXT:    br label [[OMP_IF_END]]
5855 // CHECK20:       omp_if.end:
5856 // CHECK20-NEXT:    [[TMP15:%.*]] = load i32, i32* [[N_ADDR]], align 4
5857 // CHECK20-NEXT:    [[SUB:%.*]] = sub nsw i32 [[TMP15]], 2
5858 // CHECK20-NEXT:    [[CMP4:%.*]] = icmp sgt i32 [[SUB]], 2
5859 // CHECK20-NEXT:    br i1 [[CMP4]], label [[OMP_IF_THEN5:%.*]], label [[OMP_IF_ELSE8:%.*]]
5860 // CHECK20:       omp_if.then5:
5861 // CHECK20-NEXT:    [[TMP16:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0)
5862 // CHECK20-NEXT:    [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0
5863 // CHECK20-NEXT:    br i1 [[TMP17]], label [[OMP_OFFLOAD_FAILED6:%.*]], label [[OMP_OFFLOAD_CONT7:%.*]]
5864 // CHECK20:       omp_offload.failed6:
5865 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
5866 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT7]]
5867 // CHECK20:       omp_offload.cont7:
5868 // CHECK20-NEXT:    br label [[OMP_IF_END9:%.*]]
5869 // CHECK20:       omp_if.else8:
5870 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108() #[[ATTR2]]
5871 // CHECK20-NEXT:    br label [[OMP_IF_END9]]
5872 // CHECK20:       omp_if.end9:
5873 // CHECK20-NEXT:    [[TMP18:%.*]] = load i32, i32* [[N_ADDR]], align 4
5874 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP18]], 1
5875 // CHECK20-NEXT:    ret i32 [[ADD]]
5876 //
5877 //
5878 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
5879 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
5880 // CHECK20-NEXT:  entry:
5881 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5882 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
5883 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
5884 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
5885 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
5886 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
5887 // CHECK20-NEXT:    [[B:%.*]] = alloca i16, align 2
5888 // CHECK20-NEXT:    [[A_CASTED1:%.*]] = alloca i32, align 4
5889 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5890 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS2:%.*]] = alloca [2 x i8*], align 4
5891 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS3:%.*]] = alloca [2 x i8*], align 4
5892 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS4:%.*]] = alloca [2 x i8*], align 4
5893 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5894 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
5895 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
5896 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
5897 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
5898 // CHECK20-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5899 // CHECK20-NEXT:    [[TMP3:%.*]] = bitcast i8** [[TMP2]] to i32*
5900 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP3]], align 4
5901 // CHECK20-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5902 // CHECK20-NEXT:    [[TMP5:%.*]] = bitcast i8** [[TMP4]] to i32*
5903 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP5]], align 4
5904 // CHECK20-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
5905 // CHECK20-NEXT:    store i8* null, i8** [[TMP6]], align 4
5906 // CHECK20-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
5907 // CHECK20-NEXT:    [[TMP8:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
5908 // CHECK20-NEXT:    [[TMP9:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87.region_id, i32 1, i8** [[TMP7]], i8** [[TMP8]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes.9, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 1)
5909 // CHECK20-NEXT:    [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0
5910 // CHECK20-NEXT:    br i1 [[TMP10]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
5911 // CHECK20:       omp_offload.failed:
5912 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87(i32 [[TMP1]]) #[[ATTR2]]
5913 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
5914 // CHECK20:       omp_offload.cont:
5915 // CHECK20-NEXT:    store i16 1, i16* [[B]], align 2
5916 // CHECK20-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
5917 // CHECK20-NEXT:    store i32 [[TMP11]], i32* [[A_CASTED1]], align 4
5918 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[A_CASTED1]], align 4
5919 // CHECK20-NEXT:    [[TMP13:%.*]] = load i16, i16* [[B]], align 2
5920 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_CASTED]] to i16*
5921 // CHECK20-NEXT:    store i16 [[TMP13]], i16* [[CONV]], align 2
5922 // CHECK20-NEXT:    [[TMP14:%.*]] = load i32, i32* [[B_CASTED]], align 4
5923 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
5924 // CHECK20-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
5925 // CHECK20-NEXT:    store i32 [[TMP12]], i32* [[TMP16]], align 4
5926 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
5927 // CHECK20-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
5928 // CHECK20-NEXT:    store i32 [[TMP12]], i32* [[TMP18]], align 4
5929 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 0
5930 // CHECK20-NEXT:    store i8* null, i8** [[TMP19]], align 4
5931 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 1
5932 // CHECK20-NEXT:    [[TMP21:%.*]] = bitcast i8** [[TMP20]] to i32*
5933 // CHECK20-NEXT:    store i32 [[TMP14]], i32* [[TMP21]], align 4
5934 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 1
5935 // CHECK20-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
5936 // CHECK20-NEXT:    store i32 [[TMP14]], i32* [[TMP23]], align 4
5937 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS4]], i32 0, i32 1
5938 // CHECK20-NEXT:    store i8* null, i8** [[TMP24]], align 4
5939 // CHECK20-NEXT:    [[TMP25:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS2]], i32 0, i32 0
5940 // CHECK20-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS3]], i32 0, i32 0
5941 // CHECK20-NEXT:    [[TMP27:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93.region_id, i32 2, i8** [[TMP25]], i8** [[TMP26]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
5942 // CHECK20-NEXT:    [[TMP28:%.*]] = icmp ne i32 [[TMP27]], 0
5943 // CHECK20-NEXT:    br i1 [[TMP28]], label [[OMP_OFFLOAD_FAILED5:%.*]], label [[OMP_OFFLOAD_CONT6:%.*]]
5944 // CHECK20:       omp_offload.failed5:
5945 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93(i32 [[TMP12]], i32 [[TMP14]]) #[[ATTR2]]
5946 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT6]]
5947 // CHECK20:       omp_offload.cont6:
5948 // CHECK20-NEXT:    [[TMP29:%.*]] = load i32, i32* [[A]], align 4
5949 // CHECK20-NEXT:    ret i32 [[TMP29]]
5950 //
5951 //
5952 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
5953 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] {
5954 // CHECK20-NEXT:  entry:
5955 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5956 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5957 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
5958 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
5959 // CHECK20-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
5960 // CHECK20-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
5961 // CHECK20-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
5962 // CHECK20-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
5963 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5964 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5965 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
5966 // CHECK20-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5967 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
5968 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
5969 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[B_CASTED]], align 4
5970 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
5971 // CHECK20-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
5972 // CHECK20-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
5973 // CHECK20-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
5974 // CHECK20:       omp_if.then:
5975 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
5976 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
5977 // CHECK20:       omp_if.else:
5978 // CHECK20-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5979 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
5980 // CHECK20-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR2]]
5981 // CHECK20-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
5982 // CHECK20-NEXT:    br label [[OMP_IF_END]]
5983 // CHECK20:       omp_if.end:
5984 // CHECK20-NEXT:    ret void
5985 //
5986 //
5987 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
5988 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
5989 // CHECK20-NEXT:  entry:
5990 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
5991 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
5992 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5993 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
5994 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
5995 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
5996 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5997 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
5998 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5999 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
6000 // CHECK20-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
6001 // CHECK20-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6002 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6003 // CHECK20-NEXT:    store double [[ADD]], double* [[A]], align 4
6004 // CHECK20-NEXT:    ret void
6005 //
6006 //
6007 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
6008 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
6009 // CHECK20-NEXT:  entry:
6010 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6011 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
6012 // CHECK20-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6013 // CHECK20-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6014 // CHECK20-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6015 // CHECK20-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
6016 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6017 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6018 // CHECK20-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6019 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
6020 // CHECK20-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
6021 // CHECK20-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
6022 // CHECK20-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6023 // CHECK20:       omp_if.then:
6024 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
6025 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
6026 // CHECK20:       omp_if.else:
6027 // CHECK20-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6028 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6029 // CHECK20-NEXT:    call void @.omp_outlined..1(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR2]]
6030 // CHECK20-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6031 // CHECK20-NEXT:    br label [[OMP_IF_END]]
6032 // CHECK20:       omp_if.end:
6033 // CHECK20-NEXT:    ret void
6034 //
6035 //
6036 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..1
6037 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR1]] {
6038 // CHECK20-NEXT:  entry:
6039 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6040 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6041 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6042 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6043 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6044 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6045 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6046 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6047 // CHECK20-NEXT:    store double 2.500000e+00, double* [[A]], align 4
6048 // CHECK20-NEXT:    ret void
6049 //
6050 //
6051 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
6052 // CHECK20-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] {
6053 // CHECK20-NEXT:  entry:
6054 // CHECK20-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
6055 // CHECK20-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6056 // CHECK20-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6057 // CHECK20-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6058 // CHECK20-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
6059 // CHECK20-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
6060 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
6061 // CHECK20-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
6062 // CHECK20-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
6063 // CHECK20-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6064 // CHECK20:       omp_if.then:
6065 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*))
6066 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
6067 // CHECK20:       omp_if.else:
6068 // CHECK20-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6069 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6070 // CHECK20-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR2]]
6071 // CHECK20-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6072 // CHECK20-NEXT:    br label [[OMP_IF_END]]
6073 // CHECK20:       omp_if.end:
6074 // CHECK20-NEXT:    ret void
6075 //
6076 //
6077 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
6078 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
6079 // CHECK20-NEXT:  entry:
6080 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6081 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6082 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6083 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6084 // CHECK20-NEXT:    ret void
6085 //
6086 //
6087 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
6088 // CHECK20-SAME: () #[[ATTR1]] {
6089 // CHECK20-NEXT:  entry:
6090 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..7 to void (i32*, i32*, ...)*))
6091 // CHECK20-NEXT:    ret void
6092 //
6093 //
6094 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7
6095 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1]] {
6096 // CHECK20-NEXT:  entry:
6097 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6098 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6099 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6100 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6101 // CHECK20-NEXT:    ret void
6102 //
6103 //
6104 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
6105 // CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR1]] {
6106 // CHECK20-NEXT:  entry:
6107 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6108 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6109 // CHECK20-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6110 // CHECK20-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6111 // CHECK20-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6112 // CHECK20-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
6113 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6114 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6115 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6116 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6117 // CHECK20-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6118 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6119 // CHECK20-NEXT:    call void @.omp_outlined..8(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR2]]
6120 // CHECK20-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6121 // CHECK20-NEXT:    ret void
6122 //
6123 //
6124 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..8
6125 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR1]] {
6126 // CHECK20-NEXT:  entry:
6127 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6128 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6129 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6130 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6131 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6132 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6133 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6134 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6135 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6136 // CHECK20-NEXT:    ret void
6137 //
6138 //
6139 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
6140 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
6141 // CHECK20-NEXT:  entry:
6142 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6143 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6144 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6145 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6146 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6147 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6148 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
6149 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6150 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6151 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6152 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
6153 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
6154 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
6155 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
6156 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
6157 // CHECK20-NEXT:    ret void
6158 //
6159 //
6160 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
6161 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR1]] {
6162 // CHECK20-NEXT:  entry:
6163 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6164 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6165 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6166 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6167 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6168 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6169 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6170 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6171 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
6172 // CHECK20-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
6173 // CHECK20-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
6174 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6175 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
6176 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6177 // CHECK20-NEXT:    ret void
6178 //
6179 //
6180 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
6181 // CHECK20-SAME: () #[[ATTR3:[0-9]+]] {
6182 // CHECK20-NEXT:  entry:
6183 // CHECK20-NEXT:    call void @__tgt_register_requires(i64 1)
6184 // CHECK20-NEXT:    ret void
6185 //
6186 //
6187 // CHECK21-LABEL: define {{[^@]+}}@_Z3bari
6188 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
6189 // CHECK21-NEXT:  entry:
6190 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6191 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
6192 // CHECK21-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
6193 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6194 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
6195 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6196 // CHECK21-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
6197 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6198 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6199 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6200 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6201 // CHECK21-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
6202 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6203 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6204 // CHECK21-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
6205 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6206 // CHECK21-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
6207 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6208 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6209 // CHECK21-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6210 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
6211 // CHECK21-NEXT:    ret i32 [[TMP6]]
6212 //
6213 //
6214 // CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6215 // CHECK21-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6216 // CHECK21-NEXT:  entry:
6217 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6218 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6219 // CHECK21-NEXT:    [[B:%.*]] = alloca i32, align 4
6220 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6221 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
6222 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6223 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6224 // CHECK21-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6225 // CHECK21-NEXT:    store i32 1, i32* [[B]], align 4
6226 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6227 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
6228 // CHECK21-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6229 // CHECK21-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
6230 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
6231 // CHECK21-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
6232 // CHECK21-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6233 // CHECK21-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6234 // CHECK21-NEXT:    store double [[ADD]], double* [[A]], align 8
6235 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6236 // CHECK21-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
6237 // CHECK21-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
6238 // CHECK21-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
6239 // CHECK21-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
6240 // CHECK21-NEXT:    store double 2.500000e+00, double* [[A5]], align 8
6241 // CHECK21-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
6242 // CHECK21-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 8
6243 // CHECK21-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
6244 // CHECK21-NEXT:    ret i32 [[CONV7]]
6245 //
6246 //
6247 // CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici
6248 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
6249 // CHECK21-NEXT:  entry:
6250 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6251 // CHECK21-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6252 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6253 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6254 // CHECK21-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
6255 // CHECK21-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6256 // CHECK21-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
6257 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6258 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6259 // CHECK21-NEXT:    ret i32 [[ADD]]
6260 //
6261 //
6262 // CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6263 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
6264 // CHECK21-NEXT:  entry:
6265 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6266 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
6267 // CHECK21-NEXT:    [[B:%.*]] = alloca i16, align 2
6268 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6269 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
6270 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6271 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6272 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6273 // CHECK21-NEXT:    store i16 1, i16* [[B]], align 2
6274 // CHECK21-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
6275 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
6276 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
6277 // CHECK21-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
6278 // CHECK21-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
6279 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6280 // CHECK21-NEXT:    ret i32 [[TMP3]]
6281 //
6282 //
6283 // CHECK22-LABEL: define {{[^@]+}}@_Z3bari
6284 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
6285 // CHECK22-NEXT:  entry:
6286 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6287 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
6288 // CHECK22-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
6289 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6290 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
6291 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6292 // CHECK22-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
6293 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6294 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6295 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6296 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6297 // CHECK22-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
6298 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6299 // CHECK22-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6300 // CHECK22-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
6301 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6302 // CHECK22-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
6303 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6304 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6305 // CHECK22-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6306 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
6307 // CHECK22-NEXT:    ret i32 [[TMP6]]
6308 //
6309 //
6310 // CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6311 // CHECK22-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6312 // CHECK22-NEXT:  entry:
6313 // CHECK22-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6314 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6315 // CHECK22-NEXT:    [[B:%.*]] = alloca i32, align 4
6316 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6317 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
6318 // CHECK22-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6319 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6320 // CHECK22-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6321 // CHECK22-NEXT:    store i32 1, i32* [[B]], align 4
6322 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6323 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
6324 // CHECK22-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6325 // CHECK22-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
6326 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
6327 // CHECK22-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
6328 // CHECK22-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6329 // CHECK22-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6330 // CHECK22-NEXT:    store double [[ADD]], double* [[A]], align 8
6331 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6332 // CHECK22-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
6333 // CHECK22-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
6334 // CHECK22-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
6335 // CHECK22-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
6336 // CHECK22-NEXT:    store double 2.500000e+00, double* [[A5]], align 8
6337 // CHECK22-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
6338 // CHECK22-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 8
6339 // CHECK22-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
6340 // CHECK22-NEXT:    ret i32 [[CONV7]]
6341 //
6342 //
6343 // CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici
6344 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
6345 // CHECK22-NEXT:  entry:
6346 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6347 // CHECK22-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6348 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6349 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6350 // CHECK22-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
6351 // CHECK22-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6352 // CHECK22-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
6353 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6354 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6355 // CHECK22-NEXT:    ret i32 [[ADD]]
6356 //
6357 //
6358 // CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6359 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
6360 // CHECK22-NEXT:  entry:
6361 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6362 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
6363 // CHECK22-NEXT:    [[B:%.*]] = alloca i16, align 2
6364 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6365 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
6366 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6367 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6368 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6369 // CHECK22-NEXT:    store i16 1, i16* [[B]], align 2
6370 // CHECK22-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
6371 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
6372 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
6373 // CHECK22-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
6374 // CHECK22-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
6375 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6376 // CHECK22-NEXT:    ret i32 [[TMP3]]
6377 //
6378 //
6379 // CHECK23-LABEL: define {{[^@]+}}@_Z3bari
6380 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
6381 // CHECK23-NEXT:  entry:
6382 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6383 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
6384 // CHECK23-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
6385 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6386 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
6387 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6388 // CHECK23-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
6389 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6390 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6391 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6392 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6393 // CHECK23-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
6394 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6395 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6396 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
6397 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6398 // CHECK23-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
6399 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6400 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6401 // CHECK23-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6402 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
6403 // CHECK23-NEXT:    ret i32 [[TMP6]]
6404 //
6405 //
6406 // CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6407 // CHECK23-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6408 // CHECK23-NEXT:  entry:
6409 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6410 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6411 // CHECK23-NEXT:    [[B:%.*]] = alloca i32, align 4
6412 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6413 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
6414 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6415 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6416 // CHECK23-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6417 // CHECK23-NEXT:    store i32 1, i32* [[B]], align 4
6418 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6419 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
6420 // CHECK23-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6421 // CHECK23-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
6422 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
6423 // CHECK23-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
6424 // CHECK23-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6425 // CHECK23-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6426 // CHECK23-NEXT:    store double [[ADD]], double* [[A]], align 4
6427 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6428 // CHECK23-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
6429 // CHECK23-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
6430 // CHECK23-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
6431 // CHECK23-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
6432 // CHECK23-NEXT:    store double 2.500000e+00, double* [[A5]], align 4
6433 // CHECK23-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
6434 // CHECK23-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 4
6435 // CHECK23-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
6436 // CHECK23-NEXT:    ret i32 [[CONV7]]
6437 //
6438 //
6439 // CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici
6440 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
6441 // CHECK23-NEXT:  entry:
6442 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6443 // CHECK23-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6444 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6445 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6446 // CHECK23-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
6447 // CHECK23-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6448 // CHECK23-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
6449 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6450 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6451 // CHECK23-NEXT:    ret i32 [[ADD]]
6452 //
6453 //
6454 // CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6455 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
6456 // CHECK23-NEXT:  entry:
6457 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6458 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
6459 // CHECK23-NEXT:    [[B:%.*]] = alloca i16, align 2
6460 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6461 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
6462 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6463 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6464 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6465 // CHECK23-NEXT:    store i16 1, i16* [[B]], align 2
6466 // CHECK23-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
6467 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
6468 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
6469 // CHECK23-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
6470 // CHECK23-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
6471 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6472 // CHECK23-NEXT:    ret i32 [[TMP3]]
6473 //
6474 //
6475 // CHECK24-LABEL: define {{[^@]+}}@_Z3bari
6476 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
6477 // CHECK24-NEXT:  entry:
6478 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6479 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
6480 // CHECK24-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
6481 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6482 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
6483 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6484 // CHECK24-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
6485 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6486 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6487 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6488 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6489 // CHECK24-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
6490 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6491 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6492 // CHECK24-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
6493 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6494 // CHECK24-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
6495 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6496 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6497 // CHECK24-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6498 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
6499 // CHECK24-NEXT:    ret i32 [[TMP6]]
6500 //
6501 //
6502 // CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6503 // CHECK24-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6504 // CHECK24-NEXT:  entry:
6505 // CHECK24-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6506 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6507 // CHECK24-NEXT:    [[B:%.*]] = alloca i32, align 4
6508 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6509 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
6510 // CHECK24-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6511 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6512 // CHECK24-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6513 // CHECK24-NEXT:    store i32 1, i32* [[B]], align 4
6514 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6515 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
6516 // CHECK24-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6517 // CHECK24-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
6518 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
6519 // CHECK24-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
6520 // CHECK24-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6521 // CHECK24-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
6522 // CHECK24-NEXT:    store double [[ADD]], double* [[A]], align 4
6523 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6524 // CHECK24-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
6525 // CHECK24-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
6526 // CHECK24-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
6527 // CHECK24-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
6528 // CHECK24-NEXT:    store double 2.500000e+00, double* [[A5]], align 4
6529 // CHECK24-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
6530 // CHECK24-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 4
6531 // CHECK24-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
6532 // CHECK24-NEXT:    ret i32 [[CONV7]]
6533 //
6534 //
6535 // CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici
6536 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
6537 // CHECK24-NEXT:  entry:
6538 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6539 // CHECK24-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
6540 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6541 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6542 // CHECK24-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
6543 // CHECK24-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
6544 // CHECK24-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
6545 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6546 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6547 // CHECK24-NEXT:    ret i32 [[ADD]]
6548 //
6549 //
6550 // CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
6551 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
6552 // CHECK24-NEXT:  entry:
6553 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6554 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
6555 // CHECK24-NEXT:    [[B:%.*]] = alloca i16, align 2
6556 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6557 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
6558 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
6559 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6560 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6561 // CHECK24-NEXT:    store i16 1, i16* [[B]], align 2
6562 // CHECK24-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
6563 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
6564 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
6565 // CHECK24-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
6566 // CHECK24-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
6567 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6568 // CHECK24-NEXT:    ret i32 [[TMP3]]
6569 //
6570 //
6571 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
6572 // CHECK25-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
6573 // CHECK25-NEXT:  entry:
6574 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6575 // CHECK25-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6576 // CHECK25-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6577 // CHECK25-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6578 // CHECK25-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
6579 // CHECK25-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
6580 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
6581 // CHECK25-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
6582 // CHECK25-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
6583 // CHECK25-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6584 // CHECK25:       omp_if.then:
6585 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
6586 // CHECK25-NEXT:    br label [[OMP_IF_END:%.*]]
6587 // CHECK25:       omp_if.else:
6588 // CHECK25-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6589 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6590 // CHECK25-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]]
6591 // CHECK25-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6592 // CHECK25-NEXT:    br label [[OMP_IF_END]]
6593 // CHECK25:       omp_if.end:
6594 // CHECK25-NEXT:    ret void
6595 //
6596 //
6597 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
6598 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
6599 // CHECK25-NEXT:  entry:
6600 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6601 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6602 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6603 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6604 // CHECK25-NEXT:    ret void
6605 //
6606 //
6607 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
6608 // CHECK25-SAME: () #[[ATTR0]] {
6609 // CHECK25-NEXT:  entry:
6610 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
6611 // CHECK25-NEXT:    ret void
6612 //
6613 //
6614 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
6615 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
6616 // CHECK25-NEXT:  entry:
6617 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6618 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6619 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6620 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6621 // CHECK25-NEXT:    ret void
6622 //
6623 //
6624 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
6625 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
6626 // CHECK25-NEXT:  entry:
6627 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6628 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
6629 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6630 // CHECK25-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
6631 // CHECK25-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6632 // CHECK25-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6633 // CHECK25-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6634 // CHECK25-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
6635 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6636 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
6637 // CHECK25-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
6638 // CHECK25-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6639 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6640 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
6641 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
6642 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
6643 // CHECK25-NEXT:    store i32 [[TMP2]], i32* [[CONV2]], align 4
6644 // CHECK25-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
6645 // CHECK25-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
6646 // CHECK25-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
6647 // CHECK25-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6648 // CHECK25:       omp_if.then:
6649 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
6650 // CHECK25-NEXT:    br label [[OMP_IF_END:%.*]]
6651 // CHECK25:       omp_if.else:
6652 // CHECK25-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6653 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6654 // CHECK25-NEXT:    call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]]
6655 // CHECK25-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6656 // CHECK25-NEXT:    br label [[OMP_IF_END]]
6657 // CHECK25:       omp_if.end:
6658 // CHECK25-NEXT:    ret void
6659 //
6660 //
6661 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
6662 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
6663 // CHECK25-NEXT:  entry:
6664 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6665 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6666 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6667 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
6668 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6669 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6670 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6671 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
6672 // CHECK25-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6673 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6674 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6675 // CHECK25-NEXT:    [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
6676 // CHECK25-NEXT:    [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
6677 // CHECK25-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6678 // CHECK25-NEXT:    store double [[ADD]], double* [[A]], align 8
6679 // CHECK25-NEXT:    ret void
6680 //
6681 //
6682 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
6683 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
6684 // CHECK25-NEXT:  entry:
6685 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6686 // CHECK25-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6687 // CHECK25-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6688 // CHECK25-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6689 // CHECK25-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6690 // CHECK25-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
6691 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6692 // CHECK25-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
6693 // CHECK25-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6694 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
6695 // CHECK25-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
6696 // CHECK25-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
6697 // CHECK25-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6698 // CHECK25:       omp_if.then:
6699 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
6700 // CHECK25-NEXT:    br label [[OMP_IF_END:%.*]]
6701 // CHECK25:       omp_if.else:
6702 // CHECK25-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6703 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6704 // CHECK25-NEXT:    call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]]
6705 // CHECK25-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6706 // CHECK25-NEXT:    br label [[OMP_IF_END]]
6707 // CHECK25:       omp_if.end:
6708 // CHECK25-NEXT:    ret void
6709 //
6710 //
6711 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
6712 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
6713 // CHECK25-NEXT:  entry:
6714 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6715 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6716 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6717 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6718 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6719 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6720 // CHECK25-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6721 // CHECK25-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6722 // CHECK25-NEXT:    store double 2.500000e+00, double* [[A]], align 8
6723 // CHECK25-NEXT:    ret void
6724 //
6725 //
6726 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
6727 // CHECK25-SAME: (i64 [[A:%.*]]) #[[ATTR0]] {
6728 // CHECK25-NEXT:  entry:
6729 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6730 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6731 // CHECK25-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6732 // CHECK25-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6733 // CHECK25-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6734 // CHECK25-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
6735 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
6736 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6737 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6738 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6739 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[CONV1]], align 4
6740 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
6741 // CHECK25-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6742 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6743 // CHECK25-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]]
6744 // CHECK25-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6745 // CHECK25-NEXT:    ret void
6746 //
6747 //
6748 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
6749 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
6750 // CHECK25-NEXT:  entry:
6751 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6752 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6753 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6754 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6755 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6756 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
6757 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6758 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6759 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6760 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
6761 // CHECK25-NEXT:    ret void
6762 //
6763 //
6764 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
6765 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
6766 // CHECK25-NEXT:  entry:
6767 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6768 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
6769 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6770 // CHECK25-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
6771 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
6772 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
6773 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6774 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
6775 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6776 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6777 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
6778 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
6779 // CHECK25-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
6780 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
6781 // CHECK25-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
6782 // CHECK25-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
6783 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
6784 // CHECK25-NEXT:    ret void
6785 //
6786 //
6787 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
6788 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
6789 // CHECK25-NEXT:  entry:
6790 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6791 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6792 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6793 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
6794 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6795 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6796 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
6797 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
6798 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6799 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
6800 // CHECK25-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
6801 // CHECK25-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
6802 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6803 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
6804 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
6805 // CHECK25-NEXT:    ret void
6806 //
6807 //
6808 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
6809 // CHECK26-SAME: (i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
6810 // CHECK26-NEXT:  entry:
6811 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6812 // CHECK26-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6813 // CHECK26-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6814 // CHECK26-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6815 // CHECK26-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
6816 // CHECK26-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
6817 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
6818 // CHECK26-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 8
6819 // CHECK26-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
6820 // CHECK26-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6821 // CHECK26:       omp_if.then:
6822 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
6823 // CHECK26-NEXT:    br label [[OMP_IF_END:%.*]]
6824 // CHECK26:       omp_if.else:
6825 // CHECK26-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6826 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6827 // CHECK26-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]]
6828 // CHECK26-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6829 // CHECK26-NEXT:    br label [[OMP_IF_END]]
6830 // CHECK26:       omp_if.end:
6831 // CHECK26-NEXT:    ret void
6832 //
6833 //
6834 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
6835 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
6836 // CHECK26-NEXT:  entry:
6837 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6838 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6839 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6840 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6841 // CHECK26-NEXT:    ret void
6842 //
6843 //
6844 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
6845 // CHECK26-SAME: () #[[ATTR0]] {
6846 // CHECK26-NEXT:  entry:
6847 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
6848 // CHECK26-NEXT:    ret void
6849 //
6850 //
6851 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
6852 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
6853 // CHECK26-NEXT:  entry:
6854 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6855 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6856 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6857 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6858 // CHECK26-NEXT:    ret void
6859 //
6860 //
6861 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
6862 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
6863 // CHECK26-NEXT:  entry:
6864 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6865 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
6866 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6867 // CHECK26-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
6868 // CHECK26-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6869 // CHECK26-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6870 // CHECK26-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6871 // CHECK26-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
6872 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6873 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
6874 // CHECK26-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
6875 // CHECK26-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6876 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6877 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
6878 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[CONV]], align 8
6879 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[B_CASTED]] to i32*
6880 // CHECK26-NEXT:    store i32 [[TMP2]], i32* [[CONV2]], align 4
6881 // CHECK26-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
6882 // CHECK26-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV1]], align 8
6883 // CHECK26-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
6884 // CHECK26-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6885 // CHECK26:       omp_if.then:
6886 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP3]])
6887 // CHECK26-NEXT:    br label [[OMP_IF_END:%.*]]
6888 // CHECK26:       omp_if.else:
6889 // CHECK26-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6890 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6891 // CHECK26-NEXT:    call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP3]]) #[[ATTR1]]
6892 // CHECK26-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6893 // CHECK26-NEXT:    br label [[OMP_IF_END]]
6894 // CHECK26:       omp_if.end:
6895 // CHECK26-NEXT:    ret void
6896 //
6897 //
6898 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
6899 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
6900 // CHECK26-NEXT:  entry:
6901 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6902 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6903 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6904 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
6905 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6906 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6907 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6908 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
6909 // CHECK26-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6910 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
6911 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6912 // CHECK26-NEXT:    [[CONV1:%.*]] = sitofp i32 [[TMP1]] to double
6913 // CHECK26-NEXT:    [[ADD:%.*]] = fadd double [[CONV1]], 1.500000e+00
6914 // CHECK26-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6915 // CHECK26-NEXT:    store double [[ADD]], double* [[A]], align 8
6916 // CHECK26-NEXT:    ret void
6917 //
6918 //
6919 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
6920 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
6921 // CHECK26-NEXT:  entry:
6922 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6923 // CHECK26-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8
6924 // CHECK26-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6925 // CHECK26-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6926 // CHECK26-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6927 // CHECK26-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
6928 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6929 // CHECK26-NEXT:    store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8
6930 // CHECK26-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6931 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*
6932 // CHECK26-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 8
6933 // CHECK26-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
6934 // CHECK26-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
6935 // CHECK26:       omp_if.then:
6936 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
6937 // CHECK26-NEXT:    br label [[OMP_IF_END:%.*]]
6938 // CHECK26:       omp_if.else:
6939 // CHECK26-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6940 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6941 // CHECK26-NEXT:    call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]]
6942 // CHECK26-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6943 // CHECK26-NEXT:    br label [[OMP_IF_END]]
6944 // CHECK26:       omp_if.end:
6945 // CHECK26-NEXT:    ret void
6946 //
6947 //
6948 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
6949 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
6950 // CHECK26-NEXT:  entry:
6951 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6952 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6953 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6954 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6955 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6956 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6957 // CHECK26-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6958 // CHECK26-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6959 // CHECK26-NEXT:    store double 2.500000e+00, double* [[A]], align 8
6960 // CHECK26-NEXT:    ret void
6961 //
6962 //
6963 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
6964 // CHECK26-SAME: (i64 [[A:%.*]]) #[[ATTR0]] {
6965 // CHECK26-NEXT:  entry:
6966 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6967 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6968 // CHECK26-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
6969 // CHECK26-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
6970 // CHECK26-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
6971 // CHECK26-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
6972 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
6973 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6974 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6975 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6976 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[CONV1]], align 4
6977 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
6978 // CHECK26-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6979 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
6980 // CHECK26-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i64 [[TMP2]]) #[[ATTR1]]
6981 // CHECK26-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
6982 // CHECK26-NEXT:    ret void
6983 //
6984 //
6985 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
6986 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR0]] {
6987 // CHECK26-NEXT:  entry:
6988 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6989 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6990 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6991 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6992 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6993 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
6994 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6995 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
6996 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6997 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
6998 // CHECK26-NEXT:    ret void
6999 //
7000 //
7001 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
7002 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
7003 // CHECK26-NEXT:  entry:
7004 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7005 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
7006 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7007 // CHECK26-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
7008 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7009 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
7010 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7011 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
7012 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
7013 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7014 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
7015 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
7016 // CHECK26-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
7017 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i16*
7018 // CHECK26-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
7019 // CHECK26-NEXT:    [[TMP3:%.*]] = load i64, i64* [[B_CASTED]], align 8
7020 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
7021 // CHECK26-NEXT:    ret void
7022 //
7023 //
7024 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
7025 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[B:%.*]]) #[[ATTR0]] {
7026 // CHECK26-NEXT:  entry:
7027 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7028 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7029 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
7030 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
7031 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7032 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7033 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
7034 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
7035 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
7036 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[B_ADDR]] to i16*
7037 // CHECK26-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV1]], align 8
7038 // CHECK26-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP0]] to i32
7039 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
7040 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV2]]
7041 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
7042 // CHECK26-NEXT:    ret void
7043 //
7044 //
7045 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
7046 // CHECK27-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
7047 // CHECK27-NEXT:  entry:
7048 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7049 // CHECK27-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
7050 // CHECK27-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
7051 // CHECK27-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
7052 // CHECK27-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
7053 // CHECK27-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7054 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7055 // CHECK27-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
7056 // CHECK27-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
7057 // CHECK27-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7058 // CHECK27:       omp_if.then:
7059 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
7060 // CHECK27-NEXT:    br label [[OMP_IF_END:%.*]]
7061 // CHECK27:       omp_if.else:
7062 // CHECK27-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7063 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
7064 // CHECK27-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]]
7065 // CHECK27-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7066 // CHECK27-NEXT:    br label [[OMP_IF_END]]
7067 // CHECK27:       omp_if.end:
7068 // CHECK27-NEXT:    ret void
7069 //
7070 //
7071 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
7072 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
7073 // CHECK27-NEXT:  entry:
7074 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7075 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7076 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7077 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7078 // CHECK27-NEXT:    ret void
7079 //
7080 //
7081 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
7082 // CHECK27-SAME: () #[[ATTR0]] {
7083 // CHECK27-NEXT:  entry:
7084 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
7085 // CHECK27-NEXT:    ret void
7086 //
7087 //
7088 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
7089 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
7090 // CHECK27-NEXT:  entry:
7091 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7092 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7093 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7094 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7095 // CHECK27-NEXT:    ret void
7096 //
7097 //
7098 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
7099 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
7100 // CHECK27-NEXT:  entry:
7101 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7102 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7103 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7104 // CHECK27-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
7105 // CHECK27-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
7106 // CHECK27-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
7107 // CHECK27-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
7108 // CHECK27-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
7109 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7110 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7111 // CHECK27-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7112 // CHECK27-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7113 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7114 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
7115 // CHECK27-NEXT:    store i32 [[TMP2]], i32* [[B_CASTED]], align 4
7116 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
7117 // CHECK27-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
7118 // CHECK27-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
7119 // CHECK27-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7120 // CHECK27:       omp_if.then:
7121 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
7122 // CHECK27-NEXT:    br label [[OMP_IF_END:%.*]]
7123 // CHECK27:       omp_if.else:
7124 // CHECK27-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7125 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
7126 // CHECK27-NEXT:    call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]]
7127 // CHECK27-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7128 // CHECK27-NEXT:    br label [[OMP_IF_END]]
7129 // CHECK27:       omp_if.end:
7130 // CHECK27-NEXT:    ret void
7131 //
7132 //
7133 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
7134 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
7135 // CHECK27-NEXT:  entry:
7136 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7137 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7138 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7139 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7140 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7141 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7142 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7143 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7144 // CHECK27-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7145 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
7146 // CHECK27-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
7147 // CHECK27-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
7148 // CHECK27-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
7149 // CHECK27-NEXT:    store double [[ADD]], double* [[A]], align 4
7150 // CHECK27-NEXT:    ret void
7151 //
7152 //
7153 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
7154 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
7155 // CHECK27-NEXT:  entry:
7156 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7157 // CHECK27-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7158 // CHECK27-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
7159 // CHECK27-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
7160 // CHECK27-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
7161 // CHECK27-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
7162 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7163 // CHECK27-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7164 // CHECK27-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7165 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7166 // CHECK27-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
7167 // CHECK27-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
7168 // CHECK27-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7169 // CHECK27:       omp_if.then:
7170 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
7171 // CHECK27-NEXT:    br label [[OMP_IF_END:%.*]]
7172 // CHECK27:       omp_if.else:
7173 // CHECK27-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7174 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
7175 // CHECK27-NEXT:    call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]]
7176 // CHECK27-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7177 // CHECK27-NEXT:    br label [[OMP_IF_END]]
7178 // CHECK27:       omp_if.end:
7179 // CHECK27-NEXT:    ret void
7180 //
7181 //
7182 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3
7183 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
7184 // CHECK27-NEXT:  entry:
7185 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7186 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7187 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7188 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7189 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7190 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7191 // CHECK27-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7192 // CHECK27-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
7193 // CHECK27-NEXT:    store double 2.500000e+00, double* [[A]], align 4
7194 // CHECK27-NEXT:    ret void
7195 //
7196 //
7197 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
7198 // CHECK27-SAME: (i32 [[A:%.*]]) #[[ATTR0]] {
7199 // CHECK27-NEXT:  entry:
7200 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7201 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7202 // CHECK27-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
7203 // CHECK27-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
7204 // CHECK27-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
7205 // CHECK27-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
7206 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7207 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7208 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7209 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7210 // CHECK27-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7211 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
7212 // CHECK27-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]]
7213 // CHECK27-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7214 // CHECK27-NEXT:    ret void
7215 //
7216 //
7217 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
7218 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
7219 // CHECK27-NEXT:  entry:
7220 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7221 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7222 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7223 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7224 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7225 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7226 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
7227 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7228 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
7229 // CHECK27-NEXT:    ret void
7230 //
7231 //
7232 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
7233 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
7234 // CHECK27-NEXT:  entry:
7235 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7236 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7237 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7238 // CHECK27-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
7239 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7240 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7241 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
7242 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
7243 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
7244 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
7245 // CHECK27-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
7246 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
7247 // CHECK27-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
7248 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
7249 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
7250 // CHECK27-NEXT:    ret void
7251 //
7252 //
7253 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
7254 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
7255 // CHECK27-NEXT:  entry:
7256 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7257 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7258 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7259 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7260 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7261 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7262 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7263 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7264 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
7265 // CHECK27-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
7266 // CHECK27-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
7267 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7268 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
7269 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
7270 // CHECK27-NEXT:    ret void
7271 //
7272 //
7273 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l104
7274 // CHECK28-SAME: (i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] {
7275 // CHECK28-NEXT:  entry:
7276 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7277 // CHECK28-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
7278 // CHECK28-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
7279 // CHECK28-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
7280 // CHECK28-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
7281 // CHECK28-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7282 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7283 // CHECK28-NEXT:    [[TMP1:%.*]] = load i8, i8* [[CONV]], align 4
7284 // CHECK28-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP1]] to i1
7285 // CHECK28-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7286 // CHECK28:       omp_if.then:
7287 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
7288 // CHECK28-NEXT:    br label [[OMP_IF_END:%.*]]
7289 // CHECK28:       omp_if.else:
7290 // CHECK28-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7291 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
7292 // CHECK28-NEXT:    call void @.omp_outlined.(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]]) #[[ATTR1:[0-9]+]]
7293 // CHECK28-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7294 // CHECK28-NEXT:    br label [[OMP_IF_END]]
7295 // CHECK28:       omp_if.end:
7296 // CHECK28-NEXT:    ret void
7297 //
7298 //
7299 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
7300 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
7301 // CHECK28-NEXT:  entry:
7302 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7303 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7304 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7305 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7306 // CHECK28-NEXT:    ret void
7307 //
7308 //
7309 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l108
7310 // CHECK28-SAME: () #[[ATTR0]] {
7311 // CHECK28-NEXT:  entry:
7312 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*))
7313 // CHECK28-NEXT:    ret void
7314 //
7315 //
7316 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
7317 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
7318 // CHECK28-NEXT:  entry:
7319 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7320 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7321 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7322 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7323 // CHECK28-NEXT:    ret void
7324 //
7325 //
7326 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l121
7327 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
7328 // CHECK28-NEXT:  entry:
7329 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7330 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7331 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7332 // CHECK28-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
7333 // CHECK28-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
7334 // CHECK28-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
7335 // CHECK28-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
7336 // CHECK28-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
7337 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7338 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7339 // CHECK28-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7340 // CHECK28-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7341 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7342 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[B_ADDR]], align 4
7343 // CHECK28-NEXT:    store i32 [[TMP2]], i32* [[B_CASTED]], align 4
7344 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
7345 // CHECK28-NEXT:    [[TMP4:%.*]] = load i8, i8* [[CONV]], align 4
7346 // CHECK28-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1
7347 // CHECK28-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7348 // CHECK28:       omp_if.then:
7349 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP3]])
7350 // CHECK28-NEXT:    br label [[OMP_IF_END:%.*]]
7351 // CHECK28:       omp_if.else:
7352 // CHECK28-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7353 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
7354 // CHECK28-NEXT:    call void @.omp_outlined..2(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP3]]) #[[ATTR1]]
7355 // CHECK28-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7356 // CHECK28-NEXT:    br label [[OMP_IF_END]]
7357 // CHECK28:       omp_if.end:
7358 // CHECK28-NEXT:    ret void
7359 //
7360 //
7361 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
7362 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
7363 // CHECK28-NEXT:  entry:
7364 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7365 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7366 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7367 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7368 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7369 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7370 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7371 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7372 // CHECK28-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7373 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B_ADDR]], align 4
7374 // CHECK28-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
7375 // CHECK28-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
7376 // CHECK28-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
7377 // CHECK28-NEXT:    store double [[ADD]], double* [[A]], align 4
7378 // CHECK28-NEXT:    ret void
7379 //
7380 //
7381 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l126
7382 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] {
7383 // CHECK28-NEXT:  entry:
7384 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7385 // CHECK28-NEXT:    [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4
7386 // CHECK28-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
7387 // CHECK28-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
7388 // CHECK28-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
7389 // CHECK28-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
7390 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7391 // CHECK28-NEXT:    store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4
7392 // CHECK28-NEXT:    [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7393 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8*
7394 // CHECK28-NEXT:    [[TMP2:%.*]] = load i8, i8* [[CONV]], align 4
7395 // CHECK28-NEXT:    [[TOBOOL:%.*]] = trunc i8 [[TMP2]] to i1
7396 // CHECK28-NEXT:    br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7397 // CHECK28:       omp_if.then:
7398 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]])
7399 // CHECK28-NEXT:    br label [[OMP_IF_END:%.*]]
7400 // CHECK28:       omp_if.else:
7401 // CHECK28-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7402 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
7403 // CHECK28-NEXT:    call void @.omp_outlined..3(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]]) #[[ATTR1]]
7404 // CHECK28-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7405 // CHECK28-NEXT:    br label [[OMP_IF_END]]
7406 // CHECK28:       omp_if.end:
7407 // CHECK28-NEXT:    ret void
7408 //
7409 //
7410 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3
7411 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]]) #[[ATTR0]] {
7412 // CHECK28-NEXT:  entry:
7413 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7414 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7415 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7416 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7417 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7418 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7419 // CHECK28-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7420 // CHECK28-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
7421 // CHECK28-NEXT:    store double 2.500000e+00, double* [[A]], align 4
7422 // CHECK28-NEXT:    ret void
7423 //
7424 //
7425 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l87
7426 // CHECK28-SAME: (i32 [[A:%.*]]) #[[ATTR0]] {
7427 // CHECK28-NEXT:  entry:
7428 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7429 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7430 // CHECK28-NEXT:    [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4
7431 // CHECK28-NEXT:    [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4
7432 // CHECK28-NEXT:    store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4
7433 // CHECK28-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
7434 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7435 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7436 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
7437 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
7438 // CHECK28-NEXT:    call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7439 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4
7440 // CHECK28-NEXT:    call void @.omp_outlined..4(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], i32 [[TMP2]]) #[[ATTR1]]
7441 // CHECK28-NEXT:    call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]])
7442 // CHECK28-NEXT:    ret void
7443 //
7444 //
7445 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
7446 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR0]] {
7447 // CHECK28-NEXT:  entry:
7448 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7449 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7450 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7451 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7452 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7453 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7454 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
7455 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7456 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
7457 // CHECK28-NEXT:    ret void
7458 //
7459 //
7460 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l93
7461 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
7462 // CHECK28-NEXT:  entry:
7463 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7464 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7465 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
7466 // CHECK28-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
7467 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7468 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7469 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
7470 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
7471 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
7472 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
7473 // CHECK28-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
7474 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[B_CASTED]] to i16*
7475 // CHECK28-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
7476 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[B_CASTED]], align 4
7477 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
7478 // CHECK28-NEXT:    ret void
7479 //
7480 //
7481 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
7482 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) #[[ATTR0]] {
7483 // CHECK28-NEXT:  entry:
7484 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
7485 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
7486 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
7487 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
7488 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
7489 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
7490 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
7491 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
7492 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[B_ADDR]] to i16*
7493 // CHECK28-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
7494 // CHECK28-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
7495 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
7496 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CONV1]]
7497 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
7498 // CHECK28-NEXT:    ret void
7499 //
7500 //
7501 // CHECK29-LABEL: define {{[^@]+}}@_Z3bari
7502 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7503 // CHECK29-NEXT:  entry:
7504 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7505 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
7506 // CHECK29-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
7507 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7508 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
7509 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7510 // CHECK29-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
7511 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7512 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7513 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7514 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7515 // CHECK29-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
7516 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7517 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7518 // CHECK29-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7519 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7520 // CHECK29-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
7521 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7522 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7523 // CHECK29-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7524 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7525 // CHECK29-NEXT:    ret i32 [[TMP6]]
7526 //
7527 //
7528 // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7529 // CHECK29-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7530 // CHECK29-NEXT:  entry:
7531 // CHECK29-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7532 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7533 // CHECK29-NEXT:    [[B:%.*]] = alloca i32, align 4
7534 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7535 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
7536 // CHECK29-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7537 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7538 // CHECK29-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7539 // CHECK29-NEXT:    store i32 1, i32* [[B]], align 4
7540 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7541 // CHECK29-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
7542 // CHECK29-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
7543 // CHECK29-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
7544 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
7545 // CHECK29-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
7546 // CHECK29-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
7547 // CHECK29-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7548 // CHECK29-NEXT:    store double [[ADD]], double* [[A]], align 8
7549 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7550 // CHECK29-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
7551 // CHECK29-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
7552 // CHECK29-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
7553 // CHECK29-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7554 // CHECK29-NEXT:    store double 2.500000e+00, double* [[A5]], align 8
7555 // CHECK29-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7556 // CHECK29-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 8
7557 // CHECK29-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
7558 // CHECK29-NEXT:    ret i32 [[CONV7]]
7559 //
7560 //
7561 // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici
7562 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7563 // CHECK29-NEXT:  entry:
7564 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7565 // CHECK29-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7566 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7567 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7568 // CHECK29-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
7569 // CHECK29-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
7570 // CHECK29-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
7571 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7572 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7573 // CHECK29-NEXT:    ret i32 [[ADD]]
7574 //
7575 //
7576 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7577 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
7578 // CHECK29-NEXT:  entry:
7579 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7580 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
7581 // CHECK29-NEXT:    [[B:%.*]] = alloca i16, align 2
7582 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7583 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
7584 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7585 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7586 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7587 // CHECK29-NEXT:    store i16 1, i16* [[B]], align 2
7588 // CHECK29-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
7589 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7590 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
7591 // CHECK29-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
7592 // CHECK29-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
7593 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7594 // CHECK29-NEXT:    ret i32 [[TMP3]]
7595 //
7596 //
7597 // CHECK30-LABEL: define {{[^@]+}}@_Z3bari
7598 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7599 // CHECK30-NEXT:  entry:
7600 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7601 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
7602 // CHECK30-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
7603 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7604 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
7605 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7606 // CHECK30-NEXT:    [[CALL:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 signext [[TMP0]])
7607 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7608 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7609 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7610 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7611 // CHECK30-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP2]])
7612 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7613 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7614 // CHECK30-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7615 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7616 // CHECK30-NEXT:    [[CALL3:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP4]])
7617 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7618 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7619 // CHECK30-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7620 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7621 // CHECK30-NEXT:    ret i32 [[TMP6]]
7622 //
7623 //
7624 // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7625 // CHECK30-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7626 // CHECK30-NEXT:  entry:
7627 // CHECK30-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7628 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7629 // CHECK30-NEXT:    [[B:%.*]] = alloca i32, align 4
7630 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7631 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
7632 // CHECK30-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7633 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7634 // CHECK30-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7635 // CHECK30-NEXT:    store i32 1, i32* [[B]], align 4
7636 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7637 // CHECK30-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
7638 // CHECK30-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
7639 // CHECK30-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
7640 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
7641 // CHECK30-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
7642 // CHECK30-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
7643 // CHECK30-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7644 // CHECK30-NEXT:    store double [[ADD]], double* [[A]], align 8
7645 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7646 // CHECK30-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
7647 // CHECK30-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
7648 // CHECK30-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
7649 // CHECK30-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7650 // CHECK30-NEXT:    store double 2.500000e+00, double* [[A5]], align 8
7651 // CHECK30-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7652 // CHECK30-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 8
7653 // CHECK30-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
7654 // CHECK30-NEXT:    ret i32 [[CONV7]]
7655 //
7656 //
7657 // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici
7658 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7659 // CHECK30-NEXT:  entry:
7660 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7661 // CHECK30-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7662 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7663 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7664 // CHECK30-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
7665 // CHECK30-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
7666 // CHECK30-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
7667 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7668 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7669 // CHECK30-NEXT:    ret i32 [[ADD]]
7670 //
7671 //
7672 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7673 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
7674 // CHECK30-NEXT:  entry:
7675 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7676 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
7677 // CHECK30-NEXT:    [[B:%.*]] = alloca i16, align 2
7678 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7679 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
7680 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7681 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7682 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7683 // CHECK30-NEXT:    store i16 1, i16* [[B]], align 2
7684 // CHECK30-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
7685 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7686 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
7687 // CHECK30-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
7688 // CHECK30-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
7689 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7690 // CHECK30-NEXT:    ret i32 [[TMP3]]
7691 //
7692 //
7693 // CHECK31-LABEL: define {{[^@]+}}@_Z3bari
7694 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7695 // CHECK31-NEXT:  entry:
7696 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7697 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
7698 // CHECK31-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
7699 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7700 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
7701 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7702 // CHECK31-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
7703 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7704 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7705 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7706 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7707 // CHECK31-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
7708 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7709 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7710 // CHECK31-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7711 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7712 // CHECK31-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
7713 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7714 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7715 // CHECK31-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7716 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7717 // CHECK31-NEXT:    ret i32 [[TMP6]]
7718 //
7719 //
7720 // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7721 // CHECK31-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7722 // CHECK31-NEXT:  entry:
7723 // CHECK31-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7724 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7725 // CHECK31-NEXT:    [[B:%.*]] = alloca i32, align 4
7726 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7727 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
7728 // CHECK31-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7729 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7730 // CHECK31-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7731 // CHECK31-NEXT:    store i32 1, i32* [[B]], align 4
7732 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7733 // CHECK31-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
7734 // CHECK31-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
7735 // CHECK31-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
7736 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
7737 // CHECK31-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
7738 // CHECK31-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
7739 // CHECK31-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7740 // CHECK31-NEXT:    store double [[ADD]], double* [[A]], align 4
7741 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7742 // CHECK31-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
7743 // CHECK31-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
7744 // CHECK31-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
7745 // CHECK31-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7746 // CHECK31-NEXT:    store double 2.500000e+00, double* [[A5]], align 4
7747 // CHECK31-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7748 // CHECK31-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 4
7749 // CHECK31-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
7750 // CHECK31-NEXT:    ret i32 [[CONV7]]
7751 //
7752 //
7753 // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici
7754 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7755 // CHECK31-NEXT:  entry:
7756 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7757 // CHECK31-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7758 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7759 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7760 // CHECK31-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
7761 // CHECK31-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
7762 // CHECK31-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
7763 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7764 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7765 // CHECK31-NEXT:    ret i32 [[ADD]]
7766 //
7767 //
7768 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7769 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
7770 // CHECK31-NEXT:  entry:
7771 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7772 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
7773 // CHECK31-NEXT:    [[B:%.*]] = alloca i16, align 2
7774 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7775 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
7776 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7777 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7778 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7779 // CHECK31-NEXT:    store i16 1, i16* [[B]], align 2
7780 // CHECK31-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
7781 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7782 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
7783 // CHECK31-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
7784 // CHECK31-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
7785 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7786 // CHECK31-NEXT:    ret i32 [[TMP3]]
7787 //
7788 //
7789 // CHECK32-LABEL: define {{[^@]+}}@_Z3bari
7790 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7791 // CHECK32-NEXT:  entry:
7792 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7793 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
7794 // CHECK32-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
7795 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7796 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
7797 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7798 // CHECK32-NEXT:    [[CALL:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull dereferenceable(8) [[S]], i32 [[TMP0]])
7799 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7800 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7801 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7802 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7803 // CHECK32-NEXT:    [[CALL1:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP2]])
7804 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7805 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7806 // CHECK32-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7807 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7808 // CHECK32-NEXT:    [[CALL3:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP4]])
7809 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7810 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7811 // CHECK32-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7812 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7813 // CHECK32-NEXT:    ret i32 [[TMP6]]
7814 //
7815 //
7816 // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7817 // CHECK32-SAME: (%struct.S1* nonnull dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7818 // CHECK32-NEXT:  entry:
7819 // CHECK32-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7820 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7821 // CHECK32-NEXT:    [[B:%.*]] = alloca i32, align 4
7822 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7823 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_2:%.*]] = alloca i8, align 1
7824 // CHECK32-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7825 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7826 // CHECK32-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7827 // CHECK32-NEXT:    store i32 1, i32* [[B]], align 4
7828 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7829 // CHECK32-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3
7830 // CHECK32-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
7831 // CHECK32-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
7832 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[B]], align 4
7833 // CHECK32-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to double
7834 // CHECK32-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
7835 // CHECK32-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7836 // CHECK32-NEXT:    store double [[ADD]], double* [[A]], align 4
7837 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7838 // CHECK32-NEXT:    [[CMP3:%.*]] = icmp sgt i32 [[TMP2]], 5
7839 // CHECK32-NEXT:    [[FROMBOOL4:%.*]] = zext i1 [[CMP3]] to i8
7840 // CHECK32-NEXT:    store i8 [[FROMBOOL4]], i8* [[DOTCAPTURE_EXPR_2]], align 1
7841 // CHECK32-NEXT:    [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7842 // CHECK32-NEXT:    store double 2.500000e+00, double* [[A5]], align 4
7843 // CHECK32-NEXT:    [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7844 // CHECK32-NEXT:    [[TMP3:%.*]] = load double, double* [[A6]], align 4
7845 // CHECK32-NEXT:    [[CONV7:%.*]] = fptosi double [[TMP3]] to i32
7846 // CHECK32-NEXT:    ret i32 [[CONV7]]
7847 //
7848 //
7849 // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici
7850 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7851 // CHECK32-NEXT:  entry:
7852 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7853 // CHECK32-NEXT:    [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1
7854 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7855 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7856 // CHECK32-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 1
7857 // CHECK32-NEXT:    [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8
7858 // CHECK32-NEXT:    store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1
7859 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7860 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
7861 // CHECK32-NEXT:    ret i32 [[ADD]]
7862 //
7863 //
7864 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7865 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
7866 // CHECK32-NEXT:  entry:
7867 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7868 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
7869 // CHECK32-NEXT:    [[B:%.*]] = alloca i16, align 2
7870 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7871 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
7872 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7873 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7874 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7875 // CHECK32-NEXT:    store i16 1, i16* [[B]], align 2
7876 // CHECK32-NEXT:    [[TMP1:%.*]] = load i16, i16* [[B]], align 2
7877 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7878 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A]], align 4
7879 // CHECK32-NEXT:    [[ADD1:%.*]] = add nsw i32 [[TMP2]], [[CONV]]
7880 // CHECK32-NEXT:    store i32 [[ADD1]], i32* [[A]], align 4
7881 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7882 // CHECK32-NEXT:    ret i32 [[TMP3]]
7883 //
7884