1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 23 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 26 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 27 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 28 29 // Test target codegen - host bc file has to be created first. 30 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 35 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 36 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 37 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 39 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 40 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 42 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 43 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 46 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 48 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 50 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 51 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 55 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 60 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 61 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 62 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 63 64 // expected-no-diagnostics 65 #ifndef HEADER 66 #define HEADER 67 68 69 70 // We have 8 target regions, but only 7 that actually will generate offloading 71 // code, only 6 will have mapped arguments, and only 4 have all-constant map 72 // sizes. 73 74 75 76 // Check target registration is registered as a Ctor. 77 78 79 template<typename tx, typename ty> 80 struct TT{ 81 tx X; 82 ty Y; 83 }; 84 85 long long get_val() { return 0; } 86 87 int foo(int n) { 88 int a = 0; 89 short aa = 0; 90 float b[10]; 91 float bn[n]; 92 double c[5][10]; 93 double cn[5][n]; 94 TT<long long, char> d; 95 96 #pragma omp target parallel for simd nowait 97 for (int i = 3; i < 32; i += 5) { 98 } 99 100 long long k = get_val(); 101 #pragma omp target parallel for simd if(target: 0) linear(k : 3) schedule(dynamic) 102 for (int i = 10; i > 1; i--) { 103 a += 1; 104 } 105 106 107 int lin = 12; 108 #pragma omp target parallel for simd if(target: 1) linear(lin, a : get_val()) 109 for (unsigned long long it = 2000; it >= 600; it-=400) { 110 aa += 1; 111 } 112 113 114 115 116 #pragma omp target parallel for simd if(target: n>10) 117 for (short it = 6; it <= 20; it-=-4) { 118 a += 1; 119 aa += 1; 120 } 121 122 // We capture 3 VLA sizes in this target region 123 124 125 126 127 128 // The names below are not necessarily consistent with the names used for the 129 // addresses above as some are repeated. 130 131 132 133 134 135 136 137 138 139 140 #pragma omp target parallel for simd if(target: n>20) schedule(static, a) 141 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 142 a += 1; 143 b[2] += 1.0; 144 bn[3] += 1.0; 145 c[1][2] += 1.0; 146 cn[1][3] += 1.0; 147 d.X += 1; 148 d.Y += 1; 149 } 150 151 return a; 152 } 153 154 // Check that the offloading functions are emitted and that the arguments are 155 // correct and loaded correctly for the target regions in foo(). 156 157 158 159 160 // Create stack storage and store argument in there. 161 162 // Create stack storage and store argument in there. 163 164 // Create stack storage and store argument in there. 165 166 // Create local storage for each capture. 167 168 169 170 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 171 172 template<typename tx> 173 tx ftemplate(int n) { 174 tx a = 0; 175 short aa = 0; 176 tx b[10]; 177 178 #pragma omp target parallel for simd if(target: n>40) 179 for (long long i = -10; i < 10; i += 3) { 180 a += 1; 181 aa += 1; 182 b[2] += 1; 183 } 184 185 return a; 186 } 187 188 static 189 int fstatic(int n) { 190 int a = 0; 191 short aa = 0; 192 char aaa = 0; 193 int b[10]; 194 195 #pragma omp target parallel for simd if(target: n>50) 196 for (unsigned i=100; i<10; i+=10) { 197 a += 1; 198 aa += 1; 199 aaa += 1; 200 b[2] += 1; 201 } 202 203 return a; 204 } 205 206 struct S1 { 207 double a; 208 209 int r1(int n){ 210 int b = n+1; 211 short int c[2][n]; 212 213 #ifdef OMP5 214 #pragma omp target parallel for simd if(n>60) nontemporal(a) 215 #else 216 #pragma omp target parallel for simd if(target: n>60) 217 #endif // OMP5 218 for (unsigned long long it = 2000; it >= 600; it -= 400) { 219 this->a = (double)b + 1.5; 220 c[1][1] = ++a; 221 } 222 223 return c[1][1] + (int)b; 224 } 225 }; 226 227 int bar(int n){ 228 int a = 0; 229 230 a += foo(n); 231 232 S1 S; 233 a += S.r1(n); 234 235 a += fstatic(n); 236 237 a += ftemplate<int>(n); 238 239 return a; 240 } 241 242 243 244 // We capture 2 VLA sizes in this target region 245 246 247 // The names below are not necessarily consistent with the names used for the 248 // addresses above as some are repeated. 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 // Check that the offloading functions are emitted and that the arguments are 269 // correct and loaded correctly for the target regions of the callees of bar(). 270 271 // Create local storage for each capture. 272 // Store captures in the context. 273 274 275 276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 277 278 279 // Create local storage for each capture. 280 // Store captures in the context. 281 282 283 284 285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 286 287 // Create local storage for each capture. 288 // Store captures in the context. 289 290 291 292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 293 294 295 #endif 296 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv 297 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 298 // CHECK1-NEXT: entry: 299 // CHECK1-NEXT: ret i64 0 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 303 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 306 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 307 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 308 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 309 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 310 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 311 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 312 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 314 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 315 // CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8 316 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 317 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 325 // CHECK1-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 326 // CHECK1-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 329 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 330 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 331 // CHECK1-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 336 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 337 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 338 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 339 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 340 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 341 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 342 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 343 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 344 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 345 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 346 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 347 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 348 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 349 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 350 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 351 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 352 // CHECK1-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 353 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 354 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 355 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]]) 356 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 357 // CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8 358 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 359 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 360 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 361 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 362 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[K]], align 8 363 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[K_CASTED]], align 8 364 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8 365 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]] 366 // CHECK1-NEXT: store i32 12, i32* [[LIN]], align 4 367 // CHECK1-NEXT: [[TMP15:%.*]] = load i16, i16* [[AA]], align 2 368 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 369 // CHECK1-NEXT: store i16 [[TMP15]], i16* [[CONV2]], align 2 370 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8 371 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4 372 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 373 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[CONV3]], align 4 374 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 375 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[A]], align 4 376 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 377 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV5]], align 4 378 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8 379 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 380 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 381 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP22]], align 8 382 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 383 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 384 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP24]], align 8 385 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 386 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 387 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 388 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 389 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 390 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 391 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 392 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP29]], align 8 393 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 394 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 395 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 396 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 397 // CHECK1-NEXT: store i64 [[TMP20]], i64* [[TMP32]], align 8 398 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 399 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64* 400 // CHECK1-NEXT: store i64 [[TMP20]], i64* [[TMP34]], align 8 401 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 402 // CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8 403 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 404 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 405 // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 406 // CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 407 // CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 408 // CHECK1: omp_offload.failed: 409 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]] 410 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 411 // CHECK1: omp_offload.cont: 412 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 413 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 414 // CHECK1-NEXT: store i32 [[TMP40]], i32* [[CONV7]], align 4 415 // CHECK1-NEXT: [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8 416 // CHECK1-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2 417 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 418 // CHECK1-NEXT: store i16 [[TMP42]], i16* [[CONV9]], align 2 419 // CHECK1-NEXT: [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 420 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4 421 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10 422 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 423 // CHECK1: omp_if.then: 424 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 425 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 426 // CHECK1-NEXT: store i64 [[TMP41]], i64* [[TMP46]], align 8 427 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 428 // CHECK1-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 429 // CHECK1-NEXT: store i64 [[TMP41]], i64* [[TMP48]], align 8 430 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 431 // CHECK1-NEXT: store i8* null, i8** [[TMP49]], align 8 432 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 433 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 434 // CHECK1-NEXT: store i64 [[TMP43]], i64* [[TMP51]], align 8 435 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 436 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 437 // CHECK1-NEXT: store i64 [[TMP43]], i64* [[TMP53]], align 8 438 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 439 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8 440 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 441 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 442 // CHECK1-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 443 // CHECK1-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 444 // CHECK1-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 445 // CHECK1: omp_offload.failed13: 446 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]] 447 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT14]] 448 // CHECK1: omp_offload.cont14: 449 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 450 // CHECK1: omp_if.else: 451 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]] 452 // CHECK1-NEXT: br label [[OMP_IF_END]] 453 // CHECK1: omp_if.end: 454 // CHECK1-NEXT: [[TMP59:%.*]] = load i32, i32* [[A]], align 4 455 // CHECK1-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4 456 // CHECK1-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4 457 // CHECK1-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 458 // CHECK1-NEXT: store i32 [[TMP60]], i32* [[CONV16]], align 4 459 // CHECK1-NEXT: [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8 460 // CHECK1-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 461 // CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 462 // CHECK1-NEXT: store i32 [[TMP62]], i32* [[CONV17]], align 4 463 // CHECK1-NEXT: [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 464 // CHECK1-NEXT: [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4 465 // CHECK1-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20 466 // CHECK1-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 467 // CHECK1: omp_if.then19: 468 // CHECK1-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4 469 // CHECK1-NEXT: [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]] 470 // CHECK1-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8 471 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 472 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP68]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 473 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 474 // CHECK1-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* 475 // CHECK1-NEXT: store i64 [[TMP61]], i64* [[TMP70]], align 8 476 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 477 // CHECK1-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 478 // CHECK1-NEXT: store i64 [[TMP61]], i64* [[TMP72]], align 8 479 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 480 // CHECK1-NEXT: store i8* null, i8** [[TMP73]], align 8 481 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 482 // CHECK1-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]** 483 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8 484 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 485 // CHECK1-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]** 486 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8 487 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 488 // CHECK1-NEXT: store i8* null, i8** [[TMP78]], align 8 489 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 490 // CHECK1-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* 491 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP80]], align 8 492 // CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 493 // CHECK1-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 494 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP82]], align 8 495 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 496 // CHECK1-NEXT: store i8* null, i8** [[TMP83]], align 8 497 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 498 // CHECK1-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float** 499 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP85]], align 8 500 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 501 // CHECK1-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float** 502 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP87]], align 8 503 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 504 // CHECK1-NEXT: store i64 [[TMP65]], i64* [[TMP88]], align 8 505 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 506 // CHECK1-NEXT: store i8* null, i8** [[TMP89]], align 8 507 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 508 // CHECK1-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]** 509 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 8 510 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 511 // CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]** 512 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8 513 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 514 // CHECK1-NEXT: store i8* null, i8** [[TMP94]], align 8 515 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 516 // CHECK1-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* 517 // CHECK1-NEXT: store i64 5, i64* [[TMP96]], align 8 518 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 519 // CHECK1-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* 520 // CHECK1-NEXT: store i64 5, i64* [[TMP98]], align 8 521 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 522 // CHECK1-NEXT: store i8* null, i8** [[TMP99]], align 8 523 // CHECK1-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 524 // CHECK1-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* 525 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP101]], align 8 526 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 527 // CHECK1-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64* 528 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP103]], align 8 529 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 530 // CHECK1-NEXT: store i8* null, i8** [[TMP104]], align 8 531 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 532 // CHECK1-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to double** 533 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP106]], align 8 534 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 535 // CHECK1-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to double** 536 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP108]], align 8 537 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 538 // CHECK1-NEXT: store i64 [[TMP67]], i64* [[TMP109]], align 8 539 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 540 // CHECK1-NEXT: store i8* null, i8** [[TMP110]], align 8 541 // CHECK1-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 542 // CHECK1-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to %struct.TT** 543 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP112]], align 8 544 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 545 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to %struct.TT** 546 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP114]], align 8 547 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 548 // CHECK1-NEXT: store i8* null, i8** [[TMP115]], align 8 549 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 550 // CHECK1-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 551 // CHECK1-NEXT: store i64 [[TMP63]], i64* [[TMP117]], align 8 552 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 553 // CHECK1-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 554 // CHECK1-NEXT: store i64 [[TMP63]], i64* [[TMP119]], align 8 555 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 556 // CHECK1-NEXT: store i8* null, i8** [[TMP120]], align 8 557 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 558 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 559 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 560 // CHECK1-NEXT: [[TMP124:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP121]], i8** [[TMP122]], i64* [[TMP123]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 561 // CHECK1-NEXT: [[TMP125:%.*]] = icmp ne i32 [[TMP124]], 0 562 // CHECK1-NEXT: br i1 [[TMP125]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 563 // CHECK1: omp_offload.failed23: 564 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]] 565 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT24]] 566 // CHECK1: omp_offload.cont24: 567 // CHECK1-NEXT: br label [[OMP_IF_END26:%.*]] 568 // CHECK1: omp_if.else25: 569 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]] 570 // CHECK1-NEXT: br label [[OMP_IF_END26]] 571 // CHECK1: omp_if.end26: 572 // CHECK1-NEXT: [[TMP126:%.*]] = load i32, i32* [[A]], align 4 573 // CHECK1-NEXT: [[TMP127:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 574 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP127]]) 575 // CHECK1-NEXT: ret i32 [[TMP126]] 576 // 577 // 578 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 579 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 580 // CHECK1-NEXT: entry: 581 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 582 // CHECK1-NEXT: ret void 583 // 584 // 585 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 586 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 587 // CHECK1-NEXT: entry: 588 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 589 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 590 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 591 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 592 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 593 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 594 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 595 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 596 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 597 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 598 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 599 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 600 // CHECK1-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 601 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 602 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 603 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 604 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 605 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 606 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 607 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 608 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 609 // CHECK1: cond.true: 610 // CHECK1-NEXT: br label [[COND_END:%.*]] 611 // CHECK1: cond.false: 612 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 613 // CHECK1-NEXT: br label [[COND_END]] 614 // CHECK1: cond.end: 615 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 616 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 617 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 618 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 619 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 620 // CHECK1: omp.inner.for.cond: 621 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 622 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 623 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 624 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 625 // CHECK1: omp.inner.for.body: 626 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 627 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 628 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 629 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 630 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 631 // CHECK1: omp.body.continue: 632 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 633 // CHECK1: omp.inner.for.inc: 634 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 635 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 636 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 637 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 638 // CHECK1: omp.inner.for.end: 639 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 640 // CHECK1: omp.loop.exit: 641 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 642 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 643 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 644 // CHECK1-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 645 // CHECK1: .omp.final.then: 646 // CHECK1-NEXT: store i32 33, i32* [[I]], align 4 647 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 648 // CHECK1: .omp.final.done: 649 // CHECK1-NEXT: ret void 650 // 651 // 652 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 653 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 654 // CHECK1-NEXT: entry: 655 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 656 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 657 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 658 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 659 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 660 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 661 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 662 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 663 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 664 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 665 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 666 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 667 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 668 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 669 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 670 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 671 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 672 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 673 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 674 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 675 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 676 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 677 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 678 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 679 // CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 680 // CHECK1-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 681 // CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 682 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 683 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 684 // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 685 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 686 // CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 687 // CHECK1: omp_offload.failed.i: 688 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 689 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 690 // CHECK1: .omp_outlined..1.exit: 691 // CHECK1-NEXT: ret i32 0 692 // 693 // 694 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 695 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 696 // CHECK1-NEXT: entry: 697 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 698 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 699 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 700 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 701 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 702 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 703 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 704 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 705 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 706 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 707 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 708 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 709 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 710 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 711 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 712 // CHECK1-NEXT: ret void 713 // 714 // 715 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 716 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 717 // CHECK1-NEXT: entry: 718 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 719 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 720 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 721 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 722 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 723 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 724 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 725 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 726 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 727 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 728 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 729 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 730 // CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8 731 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 732 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 733 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 734 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 735 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 736 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 737 // CHECK1-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 738 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 739 // CHECK1-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 740 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 741 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 742 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 743 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 744 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 745 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 746 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 747 // CHECK1: omp.dispatch.cond: 748 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 749 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 750 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 751 // CHECK1: omp.dispatch.body: 752 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 753 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 754 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 755 // CHECK1: omp.inner.for.cond: 756 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 757 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26 758 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 759 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 760 // CHECK1: omp.inner.for.body: 761 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 762 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 763 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 764 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26 765 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26 766 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 767 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 768 // CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 769 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 770 // CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26 771 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26 772 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 773 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26 774 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 775 // CHECK1: omp.body.continue: 776 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 777 // CHECK1: omp.inner.for.inc: 778 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 779 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 780 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 781 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 782 // CHECK1: omp.inner.for.end: 783 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 784 // CHECK1: omp.dispatch.inc: 785 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 786 // CHECK1: omp.dispatch.end: 787 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 788 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 789 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 790 // CHECK1: .omp.final.then: 791 // CHECK1-NEXT: store i32 1, i32* [[I]], align 4 792 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 793 // CHECK1: .omp.final.done: 794 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 795 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 796 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 797 // CHECK1: .omp.linear.pu: 798 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[K1]], align 8 799 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[K_ADDR]], align 8 800 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 801 // CHECK1: .omp.linear.pu.done: 802 // CHECK1-NEXT: ret void 803 // 804 // 805 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 806 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 807 // CHECK1-NEXT: entry: 808 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 809 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 810 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 811 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 812 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 813 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 814 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 815 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 816 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 817 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 818 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 819 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 820 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 821 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 822 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 823 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 824 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 825 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 826 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 827 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 828 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 829 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 830 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 831 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 832 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 833 // CHECK1-NEXT: ret void 834 // 835 // 836 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 837 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 838 // CHECK1-NEXT: entry: 839 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 840 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 841 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 842 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 843 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 844 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 845 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 846 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 847 // CHECK1-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 848 // CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 849 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 850 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 851 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 852 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 853 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 854 // CHECK1-NEXT: [[LIN4:%.*]] = alloca i32, align 4 855 // CHECK1-NEXT: [[A5:%.*]] = alloca i32, align 4 856 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 857 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 858 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 859 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 860 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 861 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 862 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 863 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 864 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 865 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 866 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 867 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 868 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 869 // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 870 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 871 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 872 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 873 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 874 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 875 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 876 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 877 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 878 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 879 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 880 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 881 // CHECK1: cond.true: 882 // CHECK1-NEXT: br label [[COND_END:%.*]] 883 // CHECK1: cond.false: 884 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 885 // CHECK1-NEXT: br label [[COND_END]] 886 // CHECK1: cond.end: 887 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 888 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 889 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 890 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 891 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 892 // CHECK1: omp.inner.for.cond: 893 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 894 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29 895 // CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 896 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 897 // CHECK1: omp.inner.for.body: 898 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 899 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 900 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 901 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29 902 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29 903 // CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 904 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 905 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29 906 // CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 907 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 908 // CHECK1-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 909 // CHECK1-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29 910 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29 911 // CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 912 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 913 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29 914 // CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 915 // CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 916 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 917 // CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29 918 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29 919 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 920 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 921 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 922 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29 923 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 924 // CHECK1: omp.body.continue: 925 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 926 // CHECK1: omp.inner.for.inc: 927 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 928 // CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 929 // CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 930 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 931 // CHECK1: omp.inner.for.end: 932 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 933 // CHECK1: omp.loop.exit: 934 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 935 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 936 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 937 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 938 // CHECK1: .omp.final.then: 939 // CHECK1-NEXT: store i64 400, i64* [[IT]], align 8 940 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 941 // CHECK1: .omp.final.done: 942 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 943 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 944 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 945 // CHECK1: .omp.linear.pu: 946 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 947 // CHECK1-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 948 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 949 // CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 950 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 951 // CHECK1: .omp.linear.pu.done: 952 // CHECK1-NEXT: ret void 953 // 954 // 955 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 956 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 957 // CHECK1-NEXT: entry: 958 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 959 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 960 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 961 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 962 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 963 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 964 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 965 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 966 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 967 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 968 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 969 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 970 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 971 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 972 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 973 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 974 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 975 // CHECK1-NEXT: ret void 976 // 977 // 978 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 979 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 980 // CHECK1-NEXT: entry: 981 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 982 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 983 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 984 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 985 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 986 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 987 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 988 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 989 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 990 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 991 // CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2 992 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 993 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 994 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 995 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 996 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 997 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 998 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 999 // CHECK1-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 1000 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1001 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1002 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1003 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1004 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1005 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1006 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 1007 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1008 // CHECK1: cond.true: 1009 // CHECK1-NEXT: br label [[COND_END:%.*]] 1010 // CHECK1: cond.false: 1011 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1012 // CHECK1-NEXT: br label [[COND_END]] 1013 // CHECK1: cond.end: 1014 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1015 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1016 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1017 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1018 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1019 // CHECK1: omp.inner.for.cond: 1020 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 1021 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32 1022 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1023 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1024 // CHECK1: omp.inner.for.body: 1025 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 1026 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 1027 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 1028 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 1029 // CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32 1030 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32 1031 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 1032 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32 1033 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32 1034 // CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 1035 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 1036 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 1037 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32 1038 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1039 // CHECK1: omp.body.continue: 1040 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1041 // CHECK1: omp.inner.for.inc: 1042 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 1043 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 1044 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 1045 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 1046 // CHECK1: omp.inner.for.end: 1047 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1048 // CHECK1: omp.loop.exit: 1049 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 1050 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1051 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1052 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1053 // CHECK1: .omp.final.then: 1054 // CHECK1-NEXT: store i16 22, i16* [[IT]], align 2 1055 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1056 // CHECK1: .omp.final.done: 1057 // CHECK1-NEXT: ret void 1058 // 1059 // 1060 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 1061 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1062 // CHECK1-NEXT: entry: 1063 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1064 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1065 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1066 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1067 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1068 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1069 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1070 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1071 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1072 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1073 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1074 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1075 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1076 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1077 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1078 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1079 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1080 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1081 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1082 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1083 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1084 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1085 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1086 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1087 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1088 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1089 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1090 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1091 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1092 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1093 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1094 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1095 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1096 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1097 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 1098 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1099 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 1100 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 1101 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 1102 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1103 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 1104 // CHECK1-NEXT: ret void 1105 // 1106 // 1107 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 1108 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1109 // CHECK1-NEXT: entry: 1110 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1111 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1112 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1113 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1114 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1115 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1116 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1117 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1118 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1119 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1120 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1121 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1122 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1123 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1124 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1125 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1126 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1127 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1128 // CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1 1129 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1130 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1131 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1132 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1133 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1134 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1135 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1136 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1137 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1138 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1139 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1140 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1141 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1142 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1143 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1144 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1145 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1146 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1147 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1148 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1149 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1150 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1151 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1152 // CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 1153 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1154 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1155 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 1156 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1157 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1158 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1159 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1160 // CHECK1: omp.dispatch.cond: 1161 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1162 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 1163 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1164 // CHECK1: cond.true: 1165 // CHECK1-NEXT: br label [[COND_END:%.*]] 1166 // CHECK1: cond.false: 1167 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1168 // CHECK1-NEXT: br label [[COND_END]] 1169 // CHECK1: cond.end: 1170 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1171 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1172 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1173 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1174 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1175 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1176 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1177 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1178 // CHECK1: omp.dispatch.body: 1179 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1180 // CHECK1: omp.inner.for.cond: 1181 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 1182 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 1183 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1184 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1185 // CHECK1: omp.inner.for.body: 1186 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 1187 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1188 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 1189 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 1190 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35 1191 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35 1192 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 1193 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35 1194 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1195 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35 1196 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 1197 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1198 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1199 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35 1200 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1201 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35 1202 // CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 1203 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 1204 // CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 1205 // CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35 1206 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1207 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 1208 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35 1209 // CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 1210 // CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35 1211 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1212 // CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 1213 // CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 1214 // CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35 1215 // CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 1216 // CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35 1217 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1218 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35 1219 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 1220 // CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35 1221 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1222 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35 1223 // CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 1224 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 1225 // CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 1226 // CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35 1227 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1228 // CHECK1: omp.body.continue: 1229 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1230 // CHECK1: omp.inner.for.inc: 1231 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 1232 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 1233 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 1234 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 1235 // CHECK1: omp.inner.for.end: 1236 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1237 // CHECK1: omp.dispatch.inc: 1238 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1239 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1240 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1241 // CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 1242 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1243 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1244 // CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1245 // CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 1246 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1247 // CHECK1: omp.dispatch.end: 1248 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 1249 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1250 // CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1251 // CHECK1-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1252 // CHECK1: .omp.final.then: 1253 // CHECK1-NEXT: store i8 96, i8* [[IT]], align 1 1254 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1255 // CHECK1: .omp.final.done: 1256 // CHECK1-NEXT: ret void 1257 // 1258 // 1259 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1260 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1261 // CHECK1-NEXT: entry: 1262 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1263 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1264 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1265 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1266 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1267 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1268 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1269 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1270 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1271 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1272 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1273 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1274 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1275 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1276 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1277 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1278 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1279 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1280 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1281 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1282 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1283 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1284 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1285 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1286 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1287 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1288 // CHECK1-NEXT: ret i32 [[TMP8]] 1289 // 1290 // 1291 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1292 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1293 // CHECK1-NEXT: entry: 1294 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1295 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1296 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1297 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1298 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1299 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1300 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1301 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1302 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1303 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1304 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1305 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1306 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1307 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1308 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1309 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1310 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1311 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1312 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1313 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1314 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1315 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1316 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1317 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1318 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1319 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1320 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1321 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1322 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1323 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1324 // CHECK1: omp_if.then: 1325 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1326 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1327 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1328 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1329 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 1330 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1331 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1332 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1333 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1334 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1335 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 1336 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1337 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1338 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1339 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1340 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1341 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1342 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1343 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1344 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1345 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 1346 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1347 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1348 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 1349 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1350 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1351 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 1352 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1353 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 1354 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1355 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1356 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1357 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1358 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1359 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1360 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1361 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 1362 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1363 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1364 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1365 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1366 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1367 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1368 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1369 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1370 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1371 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 1372 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1373 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1374 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1375 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1376 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1377 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1378 // CHECK1: omp_offload.failed: 1379 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1380 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1381 // CHECK1: omp_offload.cont: 1382 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1383 // CHECK1: omp_if.else: 1384 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1385 // CHECK1-NEXT: br label [[OMP_IF_END]] 1386 // CHECK1: omp_if.end: 1387 // CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 1388 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 1389 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1390 // CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1391 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 1392 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 1393 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 1394 // CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1395 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 1396 // CHECK1-NEXT: ret i32 [[ADD4]] 1397 // 1398 // 1399 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1400 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1401 // CHECK1-NEXT: entry: 1402 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1403 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1404 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1405 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1406 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1407 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1408 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1409 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1410 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1411 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1412 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1413 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1414 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1415 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1416 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1417 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1418 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1419 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1420 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1421 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1422 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1423 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1424 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1425 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1426 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1427 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1428 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1429 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1430 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1431 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1432 // CHECK1: omp_if.then: 1433 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1434 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1435 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1436 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1437 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1438 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1439 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1440 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1441 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1442 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1443 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1444 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1445 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1446 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1447 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1448 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1449 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1450 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1451 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1452 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1453 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1454 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1455 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1456 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1457 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1458 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1459 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1460 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1461 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1462 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1463 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1464 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1465 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1466 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1467 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1468 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1469 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1470 // CHECK1: omp_offload.failed: 1471 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1472 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1473 // CHECK1: omp_offload.cont: 1474 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1475 // CHECK1: omp_if.else: 1476 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1477 // CHECK1-NEXT: br label [[OMP_IF_END]] 1478 // CHECK1: omp_if.end: 1479 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1480 // CHECK1-NEXT: ret i32 [[TMP31]] 1481 // 1482 // 1483 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1484 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1485 // CHECK1-NEXT: entry: 1486 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1487 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1488 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1489 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1490 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1491 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1492 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1493 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1494 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1495 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1496 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1497 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1498 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1499 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1500 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1501 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1502 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1503 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1504 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1505 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1506 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1507 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1508 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1509 // CHECK1: omp_if.then: 1510 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1511 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1512 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1513 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1514 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1515 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1516 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1517 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1518 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1519 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1520 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1521 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1522 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1523 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1524 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1525 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1526 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1527 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1528 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1529 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1530 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1531 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1532 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1533 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1534 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1535 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1536 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1537 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1538 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1539 // CHECK1: omp_offload.failed: 1540 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1541 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1542 // CHECK1: omp_offload.cont: 1543 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1544 // CHECK1: omp_if.else: 1545 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1546 // CHECK1-NEXT: br label [[OMP_IF_END]] 1547 // CHECK1: omp_if.end: 1548 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1549 // CHECK1-NEXT: ret i32 [[TMP24]] 1550 // 1551 // 1552 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 1553 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1554 // CHECK1-NEXT: entry: 1555 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1556 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1557 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1558 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1559 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1560 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1561 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1562 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1563 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1564 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1565 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1566 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1567 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1568 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1569 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1570 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1571 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1572 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1573 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1574 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1575 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1576 // CHECK1-NEXT: ret void 1577 // 1578 // 1579 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 1580 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1581 // CHECK1-NEXT: entry: 1582 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1583 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1584 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1585 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1586 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1587 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1588 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1589 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1590 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1591 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1592 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1593 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1594 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1595 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 1596 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1597 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1598 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1599 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1600 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1601 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1602 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1603 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1604 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1605 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1606 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1607 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1608 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1609 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 1610 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1611 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1612 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1613 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1614 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1615 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1616 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 1617 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1618 // CHECK1: cond.true: 1619 // CHECK1-NEXT: br label [[COND_END:%.*]] 1620 // CHECK1: cond.false: 1621 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1622 // CHECK1-NEXT: br label [[COND_END]] 1623 // CHECK1: cond.end: 1624 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1625 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1626 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1627 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 1628 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1629 // CHECK1: omp.inner.for.cond: 1630 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 1631 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38 1632 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 1633 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1634 // CHECK1: omp.inner.for.body: 1635 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 1636 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 1637 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 1638 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38 1639 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38 1640 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 1641 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 1642 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1643 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !38 1644 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1645 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !38 1646 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1647 // CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !38 1648 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 1649 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1650 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 1651 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1652 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !38 1653 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1654 // CHECK1: omp.body.continue: 1655 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1656 // CHECK1: omp.inner.for.inc: 1657 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 1658 // CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 1659 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 1660 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] 1661 // CHECK1: omp.inner.for.end: 1662 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1663 // CHECK1: omp.loop.exit: 1664 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1665 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1666 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 1667 // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1668 // CHECK1: .omp.final.then: 1669 // CHECK1-NEXT: store i64 400, i64* [[IT]], align 8 1670 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1671 // CHECK1: .omp.final.done: 1672 // CHECK1-NEXT: ret void 1673 // 1674 // 1675 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 1676 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1677 // CHECK1-NEXT: entry: 1678 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1679 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1680 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1681 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1682 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1683 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1684 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1685 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1686 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1687 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1688 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1689 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1690 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1691 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1692 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1693 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1694 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1695 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1696 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1697 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1698 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1699 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1700 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1701 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1702 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1703 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1704 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1705 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1706 // CHECK1-NEXT: ret void 1707 // 1708 // 1709 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1710 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1711 // CHECK1-NEXT: entry: 1712 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1713 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1714 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1715 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1716 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1717 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1718 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1719 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1720 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1721 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1722 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1723 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1724 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1725 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1726 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1727 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1728 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1729 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1730 // CHECK1-NEXT: ret void 1731 // 1732 // 1733 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 1734 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1735 // CHECK1-NEXT: entry: 1736 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1737 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1738 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1739 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1740 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1741 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1742 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1743 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1744 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1745 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1746 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1747 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1748 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1749 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1750 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1751 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1752 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1753 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1754 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1755 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1756 // CHECK1-NEXT: ret void 1757 // 1758 // 1759 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1760 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1761 // CHECK1-NEXT: entry: 1762 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1763 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1764 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1765 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1766 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1767 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1768 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1769 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1770 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1771 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1772 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1773 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 1774 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1775 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1776 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1777 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1778 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1779 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1780 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1781 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1782 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1783 // CHECK1-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 1784 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1785 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1786 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1787 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1788 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1789 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1790 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 1791 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1792 // CHECK1: cond.true: 1793 // CHECK1-NEXT: br label [[COND_END:%.*]] 1794 // CHECK1: cond.false: 1795 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1796 // CHECK1-NEXT: br label [[COND_END]] 1797 // CHECK1: cond.end: 1798 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1799 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1800 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1801 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 1802 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1803 // CHECK1: omp.inner.for.cond: 1804 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41 1805 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !41 1806 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 1807 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1808 // CHECK1: omp.inner.for.body: 1809 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41 1810 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 1811 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 1812 // CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !41 1813 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !41 1814 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 1815 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !41 1816 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !41 1817 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 1818 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 1819 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 1820 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !41 1821 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1822 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 1823 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 1824 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !41 1825 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1826 // CHECK1: omp.body.continue: 1827 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1828 // CHECK1: omp.inner.for.inc: 1829 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41 1830 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 1831 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !41 1832 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] 1833 // CHECK1: omp.inner.for.end: 1834 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1835 // CHECK1: omp.loop.exit: 1836 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1837 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1838 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1839 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1840 // CHECK1: .omp.final.then: 1841 // CHECK1-NEXT: store i64 11, i64* [[I]], align 8 1842 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1843 // CHECK1: .omp.final.done: 1844 // CHECK1-NEXT: ret void 1845 // 1846 // 1847 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1848 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { 1849 // CHECK1-NEXT: entry: 1850 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1851 // CHECK1-NEXT: ret void 1852 // 1853 // 1854 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv 1855 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1856 // CHECK3-NEXT: entry: 1857 // CHECK3-NEXT: ret i64 0 1858 // 1859 // 1860 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1861 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 1862 // CHECK3-NEXT: entry: 1863 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1864 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1865 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1866 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1867 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1868 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1869 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1870 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1871 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1872 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 1873 // CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8 1874 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1875 // CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4 1876 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1877 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 1878 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 1879 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 1880 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 1881 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 1882 // CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 1883 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 1884 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 1885 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 1886 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 1887 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 1888 // CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 1889 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 1890 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 1891 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 1892 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 1893 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 1894 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 1895 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1896 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1897 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1898 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1899 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1900 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1901 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 1902 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 1903 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1904 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 1905 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 1906 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 1907 // CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 1908 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 1909 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 1910 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]]) 1911 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 1912 // CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8 1913 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 1914 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 1915 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 1916 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]] 1917 // CHECK3-NEXT: store i32 12, i32* [[LIN]], align 4 1918 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 1919 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1920 // CHECK3-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 1921 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1922 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4 1923 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4 1924 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 1925 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 1926 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[A_CASTED2]], align 4 1927 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4 1928 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1929 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 1930 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 1931 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1932 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 1933 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP20]], align 4 1934 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1935 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 1936 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1937 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 1938 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 1939 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1940 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 1941 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP25]], align 4 1942 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1943 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 1944 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1945 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1946 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[TMP28]], align 4 1947 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1948 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1949 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[TMP30]], align 4 1950 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1951 // CHECK3-NEXT: store i8* null, i8** [[TMP31]], align 4 1952 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1953 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1954 // CHECK3-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1955 // CHECK3-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 1956 // CHECK3-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1957 // CHECK3: omp_offload.failed: 1958 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]] 1959 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1960 // CHECK3: omp_offload.cont: 1961 // CHECK3-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 1962 // CHECK3-NEXT: store i32 [[TMP36]], i32* [[A_CASTED3]], align 4 1963 // CHECK3-NEXT: [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4 1964 // CHECK3-NEXT: [[TMP38:%.*]] = load i16, i16* [[AA]], align 2 1965 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 1966 // CHECK3-NEXT: store i16 [[TMP38]], i16* [[CONV5]], align 2 1967 // CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 1968 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4 1969 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10 1970 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1971 // CHECK3: omp_if.then: 1972 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 1973 // CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32* 1974 // CHECK3-NEXT: store i32 [[TMP37]], i32* [[TMP42]], align 4 1975 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 1976 // CHECK3-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* 1977 // CHECK3-NEXT: store i32 [[TMP37]], i32* [[TMP44]], align 4 1978 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 1979 // CHECK3-NEXT: store i8* null, i8** [[TMP45]], align 4 1980 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 1981 // CHECK3-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* 1982 // CHECK3-NEXT: store i32 [[TMP39]], i32* [[TMP47]], align 4 1983 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 1984 // CHECK3-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32* 1985 // CHECK3-NEXT: store i32 [[TMP39]], i32* [[TMP49]], align 4 1986 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 1987 // CHECK3-NEXT: store i8* null, i8** [[TMP50]], align 4 1988 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 1989 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 1990 // CHECK3-NEXT: [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1991 // CHECK3-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0 1992 // CHECK3-NEXT: br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 1993 // CHECK3: omp_offload.failed9: 1994 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]] 1995 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] 1996 // CHECK3: omp_offload.cont10: 1997 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1998 // CHECK3: omp_if.else: 1999 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]] 2000 // CHECK3-NEXT: br label [[OMP_IF_END]] 2001 // CHECK3: omp_if.end: 2002 // CHECK3-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 2003 // CHECK3-NEXT: store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4 2004 // CHECK3-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 2005 // CHECK3-NEXT: store i32 [[TMP56]], i32* [[A_CASTED11]], align 4 2006 // CHECK3-NEXT: [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4 2007 // CHECK3-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2008 // CHECK3-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2009 // CHECK3-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2010 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4 2011 // CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20 2012 // CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 2013 // CHECK3: omp_if.then13: 2014 // CHECK3-NEXT: [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4 2015 // CHECK3-NEXT: [[TMP62:%.*]] = sext i32 [[TMP61]] to i64 2016 // CHECK3-NEXT: [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]] 2017 // CHECK3-NEXT: [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8 2018 // CHECK3-NEXT: [[TMP65:%.*]] = sext i32 [[TMP64]] to i64 2019 // CHECK3-NEXT: [[TMP66:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2020 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP66]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 2021 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2022 // CHECK3-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 2023 // CHECK3-NEXT: store i32 [[TMP57]], i32* [[TMP68]], align 4 2024 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2025 // CHECK3-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 2026 // CHECK3-NEXT: store i32 [[TMP57]], i32* [[TMP70]], align 4 2027 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 2028 // CHECK3-NEXT: store i8* null, i8** [[TMP71]], align 4 2029 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 2030 // CHECK3-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]** 2031 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4 2032 // CHECK3-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 2033 // CHECK3-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]** 2034 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4 2035 // CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 2036 // CHECK3-NEXT: store i8* null, i8** [[TMP76]], align 4 2037 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 2038 // CHECK3-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* 2039 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP78]], align 4 2040 // CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 2041 // CHECK3-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* 2042 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP80]], align 4 2043 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 2044 // CHECK3-NEXT: store i8* null, i8** [[TMP81]], align 4 2045 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 2046 // CHECK3-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to float** 2047 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP83]], align 4 2048 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 2049 // CHECK3-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float** 2050 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP85]], align 4 2051 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2052 // CHECK3-NEXT: store i64 [[TMP62]], i64* [[TMP86]], align 4 2053 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 2054 // CHECK3-NEXT: store i8* null, i8** [[TMP87]], align 4 2055 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 2056 // CHECK3-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to [5 x [10 x double]]** 2057 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP89]], align 4 2058 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 2059 // CHECK3-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]** 2060 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4 2061 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 2062 // CHECK3-NEXT: store i8* null, i8** [[TMP92]], align 4 2063 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 2064 // CHECK3-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32* 2065 // CHECK3-NEXT: store i32 5, i32* [[TMP94]], align 4 2066 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 2067 // CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* 2068 // CHECK3-NEXT: store i32 5, i32* [[TMP96]], align 4 2069 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 2070 // CHECK3-NEXT: store i8* null, i8** [[TMP97]], align 4 2071 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 2072 // CHECK3-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 2073 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP99]], align 4 2074 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 2075 // CHECK3-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* 2076 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP101]], align 4 2077 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 2078 // CHECK3-NEXT: store i8* null, i8** [[TMP102]], align 4 2079 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 2080 // CHECK3-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to double** 2081 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP104]], align 4 2082 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 2083 // CHECK3-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to double** 2084 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP106]], align 4 2085 // CHECK3-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2086 // CHECK3-NEXT: store i64 [[TMP65]], i64* [[TMP107]], align 4 2087 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 2088 // CHECK3-NEXT: store i8* null, i8** [[TMP108]], align 4 2089 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 2090 // CHECK3-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to %struct.TT** 2091 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP110]], align 4 2092 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 2093 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to %struct.TT** 2094 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP112]], align 4 2095 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 2096 // CHECK3-NEXT: store i8* null, i8** [[TMP113]], align 4 2097 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 2098 // CHECK3-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 2099 // CHECK3-NEXT: store i32 [[TMP59]], i32* [[TMP115]], align 4 2100 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 2101 // CHECK3-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 2102 // CHECK3-NEXT: store i32 [[TMP59]], i32* [[TMP117]], align 4 2103 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 2104 // CHECK3-NEXT: store i8* null, i8** [[TMP118]], align 4 2105 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 2106 // CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 2107 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2108 // CHECK3-NEXT: [[TMP122:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP119]], i8** [[TMP120]], i64* [[TMP121]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2109 // CHECK3-NEXT: [[TMP123:%.*]] = icmp ne i32 [[TMP122]], 0 2110 // CHECK3-NEXT: br i1 [[TMP123]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 2111 // CHECK3: omp_offload.failed17: 2112 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]] 2113 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT18]] 2114 // CHECK3: omp_offload.cont18: 2115 // CHECK3-NEXT: br label [[OMP_IF_END20:%.*]] 2116 // CHECK3: omp_if.else19: 2117 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]] 2118 // CHECK3-NEXT: br label [[OMP_IF_END20]] 2119 // CHECK3: omp_if.end20: 2120 // CHECK3-NEXT: [[TMP124:%.*]] = load i32, i32* [[A]], align 4 2121 // CHECK3-NEXT: [[TMP125:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2122 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP125]]) 2123 // CHECK3-NEXT: ret i32 [[TMP124]] 2124 // 2125 // 2126 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 2127 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 2128 // CHECK3-NEXT: entry: 2129 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2130 // CHECK3-NEXT: ret void 2131 // 2132 // 2133 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2134 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 2135 // CHECK3-NEXT: entry: 2136 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2137 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2138 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2139 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2140 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2141 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2142 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2143 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2144 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2145 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2146 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2147 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2148 // CHECK3-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 2149 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2150 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2151 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2152 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2153 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2154 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2155 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 2156 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2157 // CHECK3: cond.true: 2158 // CHECK3-NEXT: br label [[COND_END:%.*]] 2159 // CHECK3: cond.false: 2160 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2161 // CHECK3-NEXT: br label [[COND_END]] 2162 // CHECK3: cond.end: 2163 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2164 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2165 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2166 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2167 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2168 // CHECK3: omp.inner.for.cond: 2169 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2170 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 2171 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2172 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2173 // CHECK3: omp.inner.for.body: 2174 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2175 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 2176 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 2177 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 2178 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2179 // CHECK3: omp.body.continue: 2180 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2181 // CHECK3: omp.inner.for.inc: 2182 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2183 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2184 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 2185 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2186 // CHECK3: omp.inner.for.end: 2187 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2188 // CHECK3: omp.loop.exit: 2189 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2190 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2191 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2192 // CHECK3-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2193 // CHECK3: .omp.final.then: 2194 // CHECK3-NEXT: store i32 33, i32* [[I]], align 4 2195 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2196 // CHECK3: .omp.final.done: 2197 // CHECK3-NEXT: ret void 2198 // 2199 // 2200 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2201 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2202 // CHECK3-NEXT: entry: 2203 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2204 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 2205 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 2206 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 2207 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 2208 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 2209 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2210 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 2211 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2212 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2213 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2214 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2215 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2216 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2217 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2218 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 2219 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2220 // CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2221 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 2222 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2223 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 2224 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 2225 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 2226 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 2227 // CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 2228 // CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 2229 // CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 2230 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 2231 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 2232 // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 2233 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2234 // CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2235 // CHECK3: omp_offload.failed.i: 2236 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 2237 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2238 // CHECK3: .omp_outlined..1.exit: 2239 // CHECK3-NEXT: ret i32 0 2240 // 2241 // 2242 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2243 // CHECK3-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2244 // CHECK3-NEXT: entry: 2245 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2246 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 2247 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2248 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2249 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 2250 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 2251 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2252 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2253 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2254 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 2255 // CHECK3-NEXT: ret void 2256 // 2257 // 2258 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2259 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2260 // CHECK3-NEXT: entry: 2261 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2262 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2263 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2264 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 2265 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2266 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2267 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 2268 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2269 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2270 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2271 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2272 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2273 // CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8 2274 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2275 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2276 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2277 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 2278 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 2279 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 2280 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 2281 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2282 // CHECK3-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 2283 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2284 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2285 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2286 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2287 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 2288 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 2289 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2290 // CHECK3: omp.dispatch.cond: 2291 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2292 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 2293 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2294 // CHECK3: omp.dispatch.body: 2295 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2296 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2297 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2298 // CHECK3: omp.inner.for.cond: 2299 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 2300 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 2301 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2302 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2303 // CHECK3: omp.inner.for.body: 2304 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 2305 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 2306 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 2307 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27 2308 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27 2309 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 2310 // CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 2311 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 2312 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 2313 // CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27 2314 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27 2315 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 2316 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27 2317 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2318 // CHECK3: omp.body.continue: 2319 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2320 // CHECK3: omp.inner.for.inc: 2321 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 2322 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2323 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 2324 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 2325 // CHECK3: omp.inner.for.end: 2326 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2327 // CHECK3: omp.dispatch.inc: 2328 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2329 // CHECK3: omp.dispatch.end: 2330 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2331 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2332 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2333 // CHECK3: .omp.final.then: 2334 // CHECK3-NEXT: store i32 1, i32* [[I]], align 4 2335 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2336 // CHECK3: .omp.final.done: 2337 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2338 // CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 2339 // CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2340 // CHECK3: .omp.linear.pu: 2341 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[K1]], align 8 2342 // CHECK3-NEXT: store i64 [[TMP17]], i64* [[TMP0]], align 8 2343 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2344 // CHECK3: .omp.linear.pu.done: 2345 // CHECK3-NEXT: ret void 2346 // 2347 // 2348 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 2349 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2350 // CHECK3-NEXT: entry: 2351 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2352 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2353 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2354 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2355 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 2356 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2357 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2358 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 2359 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2360 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2361 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2362 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2363 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2364 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2365 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 2366 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 2367 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 2368 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 2369 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 2370 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 2371 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 2372 // CHECK3-NEXT: ret void 2373 // 2374 // 2375 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2376 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 2377 // CHECK3-NEXT: entry: 2378 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2379 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2380 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2381 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2382 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2383 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2384 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 2385 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 2386 // CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 2387 // CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 2388 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2389 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2390 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2391 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2392 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 2393 // CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4 2394 // CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4 2395 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2396 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2397 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2398 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 2399 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2400 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2401 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 2402 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 2403 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2404 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 2405 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2406 // CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 2407 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2408 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 2409 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2410 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2411 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2412 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2413 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 2414 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2415 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2416 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 2417 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2418 // CHECK3: cond.true: 2419 // CHECK3-NEXT: br label [[COND_END:%.*]] 2420 // CHECK3: cond.false: 2421 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2422 // CHECK3-NEXT: br label [[COND_END]] 2423 // CHECK3: cond.end: 2424 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2425 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2426 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2427 // CHECK3-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 2428 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2429 // CHECK3: omp.inner.for.cond: 2430 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 2431 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30 2432 // CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 2433 // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2434 // CHECK3: omp.inner.for.body: 2435 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 2436 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 2437 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 2438 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30 2439 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30 2440 // CHECK3-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 2441 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 2442 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30 2443 // CHECK3-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 2444 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 2445 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 2446 // CHECK3-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30 2447 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30 2448 // CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 2449 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 2450 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30 2451 // CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 2452 // CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 2453 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 2454 // CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30 2455 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30 2456 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 2457 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 2458 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 2459 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30 2460 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2461 // CHECK3: omp.body.continue: 2462 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2463 // CHECK3: omp.inner.for.inc: 2464 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 2465 // CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 2466 // CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 2467 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 2468 // CHECK3: omp.inner.for.end: 2469 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2470 // CHECK3: omp.loop.exit: 2471 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2472 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2473 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 2474 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2475 // CHECK3: .omp.final.then: 2476 // CHECK3-NEXT: store i64 400, i64* [[IT]], align 8 2477 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2478 // CHECK3: .omp.final.done: 2479 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2480 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2481 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2482 // CHECK3: .omp.linear.pu: 2483 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 2484 // CHECK3-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 2485 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 2486 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 2487 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2488 // CHECK3: .omp.linear.pu.done: 2489 // CHECK3-NEXT: ret void 2490 // 2491 // 2492 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 2493 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2494 // CHECK3-NEXT: entry: 2495 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2496 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2497 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2498 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2499 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2500 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2501 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2502 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2503 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2504 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2505 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2506 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2507 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2508 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2509 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2510 // CHECK3-NEXT: ret void 2511 // 2512 // 2513 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 2514 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 2515 // CHECK3-NEXT: entry: 2516 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2517 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2518 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2519 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2520 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2521 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 2522 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2523 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2524 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2525 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2526 // CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2 2527 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2528 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2529 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2530 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2531 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2532 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2533 // CHECK3-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 2534 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2535 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2536 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2537 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2538 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2539 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2540 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 2541 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2542 // CHECK3: cond.true: 2543 // CHECK3-NEXT: br label [[COND_END:%.*]] 2544 // CHECK3: cond.false: 2545 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2546 // CHECK3-NEXT: br label [[COND_END]] 2547 // CHECK3: cond.end: 2548 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2549 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2550 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2551 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2552 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2553 // CHECK3: omp.inner.for.cond: 2554 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 2555 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 2556 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2557 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2558 // CHECK3: omp.inner.for.body: 2559 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 2560 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 2561 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 2562 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2563 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33 2564 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 2565 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 2566 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 2567 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33 2568 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 2569 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 2570 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 2571 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33 2572 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2573 // CHECK3: omp.body.continue: 2574 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2575 // CHECK3: omp.inner.for.inc: 2576 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 2577 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 2578 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 2579 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 2580 // CHECK3: omp.inner.for.end: 2581 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2582 // CHECK3: omp.loop.exit: 2583 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2584 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2585 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2586 // CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2587 // CHECK3: .omp.final.then: 2588 // CHECK3-NEXT: store i16 22, i16* [[IT]], align 2 2589 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2590 // CHECK3: .omp.final.done: 2591 // CHECK3-NEXT: ret void 2592 // 2593 // 2594 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 2595 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2596 // CHECK3-NEXT: entry: 2597 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2598 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2599 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2600 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2601 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2602 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2603 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2604 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2605 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2606 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2607 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2608 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2609 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2610 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2611 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2612 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2613 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2614 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2615 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2616 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2617 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2618 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2619 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2620 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2621 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2622 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2623 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2624 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2625 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2626 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2627 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2628 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2629 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2630 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2631 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2632 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2633 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 2634 // CHECK3-NEXT: ret void 2635 // 2636 // 2637 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 2638 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 2639 // CHECK3-NEXT: entry: 2640 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2641 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2642 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2643 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2644 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2645 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2646 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2647 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2648 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2649 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2650 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2651 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2652 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2653 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2654 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2655 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2656 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2657 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2658 // CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1 2659 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2660 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2661 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2662 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2663 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2664 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2665 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2666 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2667 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2668 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2669 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2670 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2671 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2672 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2673 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2674 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2675 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2676 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2677 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2678 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2679 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2680 // CHECK3-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 2681 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2682 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2683 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2684 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2685 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2686 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2687 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2688 // CHECK3: omp.dispatch.cond: 2689 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2690 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 2691 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2692 // CHECK3: cond.true: 2693 // CHECK3-NEXT: br label [[COND_END:%.*]] 2694 // CHECK3: cond.false: 2695 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2696 // CHECK3-NEXT: br label [[COND_END]] 2697 // CHECK3: cond.end: 2698 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2699 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2700 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2701 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2702 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2703 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2704 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2705 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2706 // CHECK3: omp.dispatch.body: 2707 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2708 // CHECK3: omp.inner.for.cond: 2709 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 2710 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36 2711 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2712 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2713 // CHECK3: omp.inner.for.body: 2714 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 2715 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2716 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 2717 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 2718 // CHECK3-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36 2719 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36 2720 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 2721 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36 2722 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2723 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36 2724 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 2725 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 2726 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 2727 // CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36 2728 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2729 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36 2730 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 2731 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 2732 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 2733 // CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36 2734 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2735 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 2736 // CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36 2737 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 2738 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36 2739 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 2740 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 2741 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 2742 // CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36 2743 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 2744 // CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36 2745 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2746 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36 2747 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 2748 // CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36 2749 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2750 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36 2751 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 2752 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 2753 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 2754 // CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36 2755 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2756 // CHECK3: omp.body.continue: 2757 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2758 // CHECK3: omp.inner.for.inc: 2759 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 2760 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 2761 // CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 2762 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 2763 // CHECK3: omp.inner.for.end: 2764 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2765 // CHECK3: omp.dispatch.inc: 2766 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2767 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2768 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2769 // CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 2770 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2771 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2772 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2773 // CHECK3-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 2774 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2775 // CHECK3: omp.dispatch.end: 2776 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 2777 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2778 // CHECK3-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2779 // CHECK3-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2780 // CHECK3: .omp.final.then: 2781 // CHECK3-NEXT: store i8 96, i8* [[IT]], align 1 2782 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2783 // CHECK3: .omp.final.done: 2784 // CHECK3-NEXT: ret void 2785 // 2786 // 2787 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2788 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2789 // CHECK3-NEXT: entry: 2790 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2791 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2792 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2793 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2794 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2795 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2796 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2797 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2798 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2799 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2800 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2801 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2802 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2803 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2804 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2805 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2806 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2807 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2808 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2809 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2810 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2811 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2812 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2813 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2814 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2815 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2816 // CHECK3-NEXT: ret i32 [[TMP8]] 2817 // 2818 // 2819 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2820 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2821 // CHECK3-NEXT: entry: 2822 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2823 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2824 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2825 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2826 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2827 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2828 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2829 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2830 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2831 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2832 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2833 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2834 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2835 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2836 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2837 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 2838 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2839 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2840 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2841 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2842 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2843 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2844 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 2845 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 2846 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 2847 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2848 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 2849 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2850 // CHECK3: omp_if.then: 2851 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2852 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 2853 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 2854 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 2855 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2856 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 2857 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2858 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 2859 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 2860 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2861 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 2862 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 2863 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2864 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 2865 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2866 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 2867 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 2868 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2869 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 2870 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 2871 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2872 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 2873 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2874 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 2875 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 2876 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2877 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 2878 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 2879 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2880 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 2881 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2882 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2883 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 2884 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2885 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 2886 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 2887 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2888 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 2889 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2890 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 2891 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 2892 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2893 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 2894 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 2895 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2896 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 2897 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2898 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 2899 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2900 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2901 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2902 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2903 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 2904 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2905 // CHECK3: omp_offload.failed: 2906 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 2907 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2908 // CHECK3: omp_offload.cont: 2909 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2910 // CHECK3: omp_if.else: 2911 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 2912 // CHECK3-NEXT: br label [[OMP_IF_END]] 2913 // CHECK3: omp_if.end: 2914 // CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 2915 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 2916 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 2917 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 2918 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 2919 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 2920 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 2921 // CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2922 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 2923 // CHECK3-NEXT: ret i32 [[ADD3]] 2924 // 2925 // 2926 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 2927 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2928 // CHECK3-NEXT: entry: 2929 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2930 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2931 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2932 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 2933 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2934 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2935 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2936 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 2937 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2938 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2939 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2940 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2941 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2942 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2943 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 2944 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2945 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2946 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2947 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2948 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2949 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 2950 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2951 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 2952 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 2953 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 2954 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 2955 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2956 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 2957 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2958 // CHECK3: omp_if.then: 2959 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2960 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2961 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 2962 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2963 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 2964 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 2965 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2966 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 2967 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2968 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2969 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2970 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2971 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 2972 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 2973 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2974 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 2975 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2976 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2977 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 2978 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2979 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 2980 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 2981 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2982 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 2983 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2984 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 2985 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 2986 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2987 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 2988 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 2989 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2990 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 2991 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2992 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2993 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2994 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2995 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2996 // CHECK3: omp_offload.failed: 2997 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 2998 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2999 // CHECK3: omp_offload.cont: 3000 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3001 // CHECK3: omp_if.else: 3002 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3003 // CHECK3-NEXT: br label [[OMP_IF_END]] 3004 // CHECK3: omp_if.end: 3005 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 3006 // CHECK3-NEXT: ret i32 [[TMP31]] 3007 // 3008 // 3009 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3010 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3011 // CHECK3-NEXT: entry: 3012 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3013 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3014 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3015 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3016 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3017 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3018 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3019 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3020 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3021 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3022 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3023 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3024 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3025 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3026 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3027 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3028 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3029 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3030 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3031 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3032 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3033 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3034 // CHECK3: omp_if.then: 3035 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3036 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 3037 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 3038 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3039 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3040 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3041 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3042 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 3043 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3044 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 3045 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 3046 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3047 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3048 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3049 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3050 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 3051 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3052 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3053 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 3054 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3055 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3056 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 3057 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3058 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3059 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3060 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3061 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3062 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3063 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3064 // CHECK3: omp_offload.failed: 3065 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3066 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3067 // CHECK3: omp_offload.cont: 3068 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3069 // CHECK3: omp_if.else: 3070 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3071 // CHECK3-NEXT: br label [[OMP_IF_END]] 3072 // CHECK3: omp_if.end: 3073 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 3074 // CHECK3-NEXT: ret i32 [[TMP24]] 3075 // 3076 // 3077 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 3078 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3079 // CHECK3-NEXT: entry: 3080 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3081 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3082 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3083 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3084 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3085 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3086 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3087 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3088 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3089 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3090 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3091 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3092 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3093 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3094 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3095 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3096 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3097 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3098 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3099 // CHECK3-NEXT: ret void 3100 // 3101 // 3102 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 3103 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3104 // CHECK3-NEXT: entry: 3105 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3106 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3107 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3108 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3109 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3110 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3111 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3112 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3113 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3114 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3115 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3116 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3117 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3118 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 3119 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3120 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3121 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3122 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3123 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3124 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3125 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3126 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3127 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3128 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3129 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3130 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3131 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 3132 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3133 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3134 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3135 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3136 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3137 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3138 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 3139 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3140 // CHECK3: cond.true: 3141 // CHECK3-NEXT: br label [[COND_END:%.*]] 3142 // CHECK3: cond.false: 3143 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3144 // CHECK3-NEXT: br label [[COND_END]] 3145 // CHECK3: cond.end: 3146 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3147 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3148 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3149 // CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 3150 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3151 // CHECK3: omp.inner.for.cond: 3152 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39 3153 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39 3154 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 3155 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3156 // CHECK3: omp.inner.for.body: 3157 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39 3158 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 3159 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3160 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39 3161 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39 3162 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3163 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3164 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3165 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4, !llvm.access.group !39 3166 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3167 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !39 3168 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3169 // CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !39 3170 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 3171 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 3172 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 3173 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3174 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !39 3175 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3176 // CHECK3: omp.body.continue: 3177 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3178 // CHECK3: omp.inner.for.inc: 3179 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39 3180 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 3181 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39 3182 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 3183 // CHECK3: omp.inner.for.end: 3184 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3185 // CHECK3: omp.loop.exit: 3186 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3187 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3188 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 3189 // CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3190 // CHECK3: .omp.final.then: 3191 // CHECK3-NEXT: store i64 400, i64* [[IT]], align 8 3192 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3193 // CHECK3: .omp.final.done: 3194 // CHECK3-NEXT: ret void 3195 // 3196 // 3197 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 3198 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3199 // CHECK3-NEXT: entry: 3200 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3201 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3202 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3203 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3204 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3205 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3206 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3207 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3208 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3209 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3210 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3211 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3212 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3213 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3214 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3215 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3216 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3217 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3218 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3219 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 3220 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3221 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 3222 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3223 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 3224 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3225 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 3226 // CHECK3-NEXT: ret void 3227 // 3228 // 3229 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 3230 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3231 // CHECK3-NEXT: entry: 3232 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3233 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3234 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3235 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3236 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3237 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3238 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3239 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3240 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3241 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3242 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3243 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3244 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3245 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3246 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3247 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3248 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3249 // CHECK3-NEXT: ret void 3250 // 3251 // 3252 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 3253 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3254 // CHECK3-NEXT: entry: 3255 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3256 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3257 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3258 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3259 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3260 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3261 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3262 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3263 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3264 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3265 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3266 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3267 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3268 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3269 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3270 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3271 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3272 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3273 // CHECK3-NEXT: ret void 3274 // 3275 // 3276 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 3277 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3278 // CHECK3-NEXT: entry: 3279 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3280 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3281 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3282 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3283 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3284 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3285 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3286 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3287 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3288 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3289 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3290 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 3291 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3292 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3293 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3294 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3295 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3296 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3297 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3298 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3299 // CHECK3-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 3300 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3301 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3302 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3303 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3304 // CHECK3-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3305 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3306 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 3307 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3308 // CHECK3: cond.true: 3309 // CHECK3-NEXT: br label [[COND_END:%.*]] 3310 // CHECK3: cond.false: 3311 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3312 // CHECK3-NEXT: br label [[COND_END]] 3313 // CHECK3: cond.end: 3314 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3315 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3316 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3317 // CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 3318 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3319 // CHECK3: omp.inner.for.cond: 3320 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42 3321 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !42 3322 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 3323 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3324 // CHECK3: omp.inner.for.body: 3325 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42 3326 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 3327 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 3328 // CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !42 3329 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !42 3330 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 3331 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !42 3332 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !42 3333 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 3334 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 3335 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 3336 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !42 3337 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3338 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 3339 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 3340 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !42 3341 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3342 // CHECK3: omp.body.continue: 3343 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3344 // CHECK3: omp.inner.for.inc: 3345 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42 3346 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 3347 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !42 3348 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] 3349 // CHECK3: omp.inner.for.end: 3350 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3351 // CHECK3: omp.loop.exit: 3352 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 3353 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3354 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3355 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3356 // CHECK3: .omp.final.then: 3357 // CHECK3-NEXT: store i64 11, i64* [[I]], align 8 3358 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3359 // CHECK3: .omp.final.done: 3360 // CHECK3-NEXT: ret void 3361 // 3362 // 3363 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3364 // CHECK3-SAME: () #[[ATTR8:[0-9]+]] { 3365 // CHECK3-NEXT: entry: 3366 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3367 // CHECK3-NEXT: ret void 3368 // 3369 // 3370 // CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv 3371 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 3372 // CHECK5-NEXT: entry: 3373 // CHECK5-NEXT: ret i64 0 3374 // 3375 // 3376 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi 3377 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 3378 // CHECK5-NEXT: entry: 3379 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3380 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 3381 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 3382 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3383 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3384 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3385 // CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3386 // CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3387 // CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 3388 // CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 3389 // CHECK5-NEXT: [[K:%.*]] = alloca i64, align 8 3390 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3391 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 3392 // CHECK5-NEXT: [[LIN:%.*]] = alloca i32, align 4 3393 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3394 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 3395 // CHECK5-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 3396 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3397 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3398 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3399 // CHECK5-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 3400 // CHECK5-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 3401 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 3402 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 3403 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 3404 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3405 // CHECK5-NEXT: [[A_CASTED15:%.*]] = alloca i64, align 8 3406 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3407 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS20:%.*]] = alloca [10 x i8*], align 8 3408 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS21:%.*]] = alloca [10 x i8*], align 8 3409 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS22:%.*]] = alloca [10 x i8*], align 8 3410 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 3411 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 3412 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3413 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 3414 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 3415 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3416 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 3417 // CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 3418 // CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 3419 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 3420 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 3421 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3422 // CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 3423 // CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 3424 // CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 3425 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 3426 // CHECK5-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 3427 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 3428 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 3429 // CHECK5-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]]) 3430 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 3431 // CHECK5-NEXT: store i64 [[CALL]], i64* [[K]], align 8 3432 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 3433 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3434 // CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 3435 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 3436 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[K]], align 8 3437 // CHECK5-NEXT: store i64 [[TMP13]], i64* [[K_CASTED]], align 8 3438 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8 3439 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]] 3440 // CHECK5-NEXT: store i32 12, i32* [[LIN]], align 4 3441 // CHECK5-NEXT: [[TMP15:%.*]] = load i16, i16* [[AA]], align 2 3442 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3443 // CHECK5-NEXT: store i16 [[TMP15]], i16* [[CONV2]], align 2 3444 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3445 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4 3446 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 3447 // CHECK5-NEXT: store i32 [[TMP17]], i32* [[CONV3]], align 4 3448 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 3449 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[A]], align 4 3450 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 3451 // CHECK5-NEXT: store i32 [[TMP19]], i32* [[CONV5]], align 4 3452 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8 3453 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3454 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 3455 // CHECK5-NEXT: store i64 [[TMP16]], i64* [[TMP22]], align 8 3456 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3457 // CHECK5-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 3458 // CHECK5-NEXT: store i64 [[TMP16]], i64* [[TMP24]], align 8 3459 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3460 // CHECK5-NEXT: store i8* null, i8** [[TMP25]], align 8 3461 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3462 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 3463 // CHECK5-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 3464 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3465 // CHECK5-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 3466 // CHECK5-NEXT: store i64 [[TMP18]], i64* [[TMP29]], align 8 3467 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3468 // CHECK5-NEXT: store i8* null, i8** [[TMP30]], align 8 3469 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3470 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 3471 // CHECK5-NEXT: store i64 [[TMP20]], i64* [[TMP32]], align 8 3472 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3473 // CHECK5-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64* 3474 // CHECK5-NEXT: store i64 [[TMP20]], i64* [[TMP34]], align 8 3475 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3476 // CHECK5-NEXT: store i8* null, i8** [[TMP35]], align 8 3477 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3478 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3479 // CHECK5-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP36]], i8** [[TMP37]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3480 // CHECK5-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 3481 // CHECK5-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3482 // CHECK5: omp_offload.failed: 3483 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]] 3484 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3485 // CHECK5: omp_offload.cont: 3486 // CHECK5-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 3487 // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 3488 // CHECK5-NEXT: store i32 [[TMP40]], i32* [[CONV7]], align 4 3489 // CHECK5-NEXT: [[TMP41:%.*]] = load i64, i64* [[A_CASTED6]], align 8 3490 // CHECK5-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2 3491 // CHECK5-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 3492 // CHECK5-NEXT: store i16 [[TMP42]], i16* [[CONV9]], align 2 3493 // CHECK5-NEXT: [[TMP43:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 3494 // CHECK5-NEXT: [[TMP44:%.*]] = load i32, i32* [[N_ADDR]], align 4 3495 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP44]], 10 3496 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3497 // CHECK5: omp_if.then: 3498 // CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 3499 // CHECK5-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 3500 // CHECK5-NEXT: store i64 [[TMP41]], i64* [[TMP46]], align 8 3501 // CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 3502 // CHECK5-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to i64* 3503 // CHECK5-NEXT: store i64 [[TMP41]], i64* [[TMP48]], align 8 3504 // CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 3505 // CHECK5-NEXT: store i8* null, i8** [[TMP49]], align 8 3506 // CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 3507 // CHECK5-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 3508 // CHECK5-NEXT: store i64 [[TMP43]], i64* [[TMP51]], align 8 3509 // CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 3510 // CHECK5-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 3511 // CHECK5-NEXT: store i64 [[TMP43]], i64* [[TMP53]], align 8 3512 // CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 3513 // CHECK5-NEXT: store i8* null, i8** [[TMP54]], align 8 3514 // CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 3515 // CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 3516 // CHECK5-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP55]], i8** [[TMP56]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3517 // CHECK5-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 3518 // CHECK5-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED13:%.*]], label [[OMP_OFFLOAD_CONT14:%.*]] 3519 // CHECK5: omp_offload.failed13: 3520 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]] 3521 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT14]] 3522 // CHECK5: omp_offload.cont14: 3523 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 3524 // CHECK5: omp_if.else: 3525 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP41]], i64 [[TMP43]]) #[[ATTR4]] 3526 // CHECK5-NEXT: br label [[OMP_IF_END]] 3527 // CHECK5: omp_if.end: 3528 // CHECK5-NEXT: [[TMP59:%.*]] = load i32, i32* [[A]], align 4 3529 // CHECK5-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_]], align 4 3530 // CHECK5-NEXT: [[TMP60:%.*]] = load i32, i32* [[A]], align 4 3531 // CHECK5-NEXT: [[CONV16:%.*]] = bitcast i64* [[A_CASTED15]] to i32* 3532 // CHECK5-NEXT: store i32 [[TMP60]], i32* [[CONV16]], align 4 3533 // CHECK5-NEXT: [[TMP61:%.*]] = load i64, i64* [[A_CASTED15]], align 8 3534 // CHECK5-NEXT: [[TMP62:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3535 // CHECK5-NEXT: [[CONV17:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3536 // CHECK5-NEXT: store i32 [[TMP62]], i32* [[CONV17]], align 4 3537 // CHECK5-NEXT: [[TMP63:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3538 // CHECK5-NEXT: [[TMP64:%.*]] = load i32, i32* [[N_ADDR]], align 4 3539 // CHECK5-NEXT: [[CMP18:%.*]] = icmp sgt i32 [[TMP64]], 20 3540 // CHECK5-NEXT: br i1 [[CMP18]], label [[OMP_IF_THEN19:%.*]], label [[OMP_IF_ELSE25:%.*]] 3541 // CHECK5: omp_if.then19: 3542 // CHECK5-NEXT: [[TMP65:%.*]] = mul nuw i64 [[TMP2]], 4 3543 // CHECK5-NEXT: [[TMP66:%.*]] = mul nuw i64 5, [[TMP5]] 3544 // CHECK5-NEXT: [[TMP67:%.*]] = mul nuw i64 [[TMP66]], 8 3545 // CHECK5-NEXT: [[TMP68:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3546 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP68]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 3547 // CHECK5-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 3548 // CHECK5-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i64* 3549 // CHECK5-NEXT: store i64 [[TMP61]], i64* [[TMP70]], align 8 3550 // CHECK5-NEXT: [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 3551 // CHECK5-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to i64* 3552 // CHECK5-NEXT: store i64 [[TMP61]], i64* [[TMP72]], align 8 3553 // CHECK5-NEXT: [[TMP73:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 0 3554 // CHECK5-NEXT: store i8* null, i8** [[TMP73]], align 8 3555 // CHECK5-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 1 3556 // CHECK5-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]** 3557 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 8 3558 // CHECK5-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 1 3559 // CHECK5-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to [10 x float]** 3560 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP77]], align 8 3561 // CHECK5-NEXT: [[TMP78:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 1 3562 // CHECK5-NEXT: store i8* null, i8** [[TMP78]], align 8 3563 // CHECK5-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 2 3564 // CHECK5-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* 3565 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP80]], align 8 3566 // CHECK5-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 2 3567 // CHECK5-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 3568 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP82]], align 8 3569 // CHECK5-NEXT: [[TMP83:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 2 3570 // CHECK5-NEXT: store i8* null, i8** [[TMP83]], align 8 3571 // CHECK5-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 3 3572 // CHECK5-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float** 3573 // CHECK5-NEXT: store float* [[VLA]], float** [[TMP85]], align 8 3574 // CHECK5-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 3 3575 // CHECK5-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to float** 3576 // CHECK5-NEXT: store float* [[VLA]], float** [[TMP87]], align 8 3577 // CHECK5-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3578 // CHECK5-NEXT: store i64 [[TMP65]], i64* [[TMP88]], align 8 3579 // CHECK5-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 3 3580 // CHECK5-NEXT: store i8* null, i8** [[TMP89]], align 8 3581 // CHECK5-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 4 3582 // CHECK5-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]** 3583 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 8 3584 // CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 4 3585 // CHECK5-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [5 x [10 x double]]** 3586 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP93]], align 8 3587 // CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 4 3588 // CHECK5-NEXT: store i8* null, i8** [[TMP94]], align 8 3589 // CHECK5-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 5 3590 // CHECK5-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i64* 3591 // CHECK5-NEXT: store i64 5, i64* [[TMP96]], align 8 3592 // CHECK5-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 5 3593 // CHECK5-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* 3594 // CHECK5-NEXT: store i64 5, i64* [[TMP98]], align 8 3595 // CHECK5-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 5 3596 // CHECK5-NEXT: store i8* null, i8** [[TMP99]], align 8 3597 // CHECK5-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 6 3598 // CHECK5-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i64* 3599 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP101]], align 8 3600 // CHECK5-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 6 3601 // CHECK5-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to i64* 3602 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP103]], align 8 3603 // CHECK5-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 6 3604 // CHECK5-NEXT: store i8* null, i8** [[TMP104]], align 8 3605 // CHECK5-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 7 3606 // CHECK5-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to double** 3607 // CHECK5-NEXT: store double* [[VLA1]], double** [[TMP106]], align 8 3608 // CHECK5-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 7 3609 // CHECK5-NEXT: [[TMP108:%.*]] = bitcast i8** [[TMP107]] to double** 3610 // CHECK5-NEXT: store double* [[VLA1]], double** [[TMP108]], align 8 3611 // CHECK5-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3612 // CHECK5-NEXT: store i64 [[TMP67]], i64* [[TMP109]], align 8 3613 // CHECK5-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 7 3614 // CHECK5-NEXT: store i8* null, i8** [[TMP110]], align 8 3615 // CHECK5-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 8 3616 // CHECK5-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to %struct.TT** 3617 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP112]], align 8 3618 // CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 8 3619 // CHECK5-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to %struct.TT** 3620 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP114]], align 8 3621 // CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 8 3622 // CHECK5-NEXT: store i8* null, i8** [[TMP115]], align 8 3623 // CHECK5-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 9 3624 // CHECK5-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i64* 3625 // CHECK5-NEXT: store i64 [[TMP63]], i64* [[TMP117]], align 8 3626 // CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 9 3627 // CHECK5-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 3628 // CHECK5-NEXT: store i64 [[TMP63]], i64* [[TMP119]], align 8 3629 // CHECK5-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS22]], i64 0, i64 9 3630 // CHECK5-NEXT: store i8* null, i8** [[TMP120]], align 8 3631 // CHECK5-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS20]], i32 0, i32 0 3632 // CHECK5-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS21]], i32 0, i32 0 3633 // CHECK5-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3634 // CHECK5-NEXT: [[TMP124:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP121]], i8** [[TMP122]], i64* [[TMP123]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3635 // CHECK5-NEXT: [[TMP125:%.*]] = icmp ne i32 [[TMP124]], 0 3636 // CHECK5-NEXT: br i1 [[TMP125]], label [[OMP_OFFLOAD_FAILED23:%.*]], label [[OMP_OFFLOAD_CONT24:%.*]] 3637 // CHECK5: omp_offload.failed23: 3638 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]] 3639 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT24]] 3640 // CHECK5: omp_offload.cont24: 3641 // CHECK5-NEXT: br label [[OMP_IF_END26:%.*]] 3642 // CHECK5: omp_if.else25: 3643 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP61]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP63]]) #[[ATTR4]] 3644 // CHECK5-NEXT: br label [[OMP_IF_END26]] 3645 // CHECK5: omp_if.end26: 3646 // CHECK5-NEXT: [[TMP126:%.*]] = load i32, i32* [[A]], align 4 3647 // CHECK5-NEXT: [[TMP127:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3648 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP127]]) 3649 // CHECK5-NEXT: ret i32 [[TMP126]] 3650 // 3651 // 3652 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 3653 // CHECK5-SAME: () #[[ATTR2:[0-9]+]] { 3654 // CHECK5-NEXT: entry: 3655 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 3656 // CHECK5-NEXT: ret void 3657 // 3658 // 3659 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 3660 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 3661 // CHECK5-NEXT: entry: 3662 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3663 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3664 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3665 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3666 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3667 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3668 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3669 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3670 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3671 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3672 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3673 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3674 // CHECK5-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 3675 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3676 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3677 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3678 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 3679 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3680 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3681 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 3682 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3683 // CHECK5: cond.true: 3684 // CHECK5-NEXT: br label [[COND_END:%.*]] 3685 // CHECK5: cond.false: 3686 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3687 // CHECK5-NEXT: br label [[COND_END]] 3688 // CHECK5: cond.end: 3689 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 3690 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3691 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3692 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3693 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3694 // CHECK5: omp.inner.for.cond: 3695 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 3696 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !10 3697 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3698 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3699 // CHECK5: omp.inner.for.body: 3700 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 3701 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 3702 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 3703 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !10 3704 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3705 // CHECK5: omp.body.continue: 3706 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3707 // CHECK5: omp.inner.for.inc: 3708 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 3709 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 3710 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !10 3711 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 3712 // CHECK5: omp.inner.for.end: 3713 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3714 // CHECK5: omp.loop.exit: 3715 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 3716 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3717 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 3718 // CHECK5-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3719 // CHECK5: .omp.final.then: 3720 // CHECK5-NEXT: store i32 33, i32* [[I]], align 4 3721 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 3722 // CHECK5: .omp.final.done: 3723 // CHECK5-NEXT: ret void 3724 // 3725 // 3726 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. 3727 // CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 3728 // CHECK5-NEXT: entry: 3729 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 3730 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 3731 // CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 3732 // CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 3733 // CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 3734 // CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 3735 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 3736 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 3737 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 3738 // CHECK5-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 3739 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 3740 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 3741 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 3742 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 3743 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 3744 // CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 3745 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 3746 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 3747 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 3748 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 3749 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 3750 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 3751 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 3752 // CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 3753 // CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 3754 // CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 3755 // CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 3756 // CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 3757 // CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 3758 // CHECK5-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 3759 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 3760 // CHECK5-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 3761 // CHECK5: omp_offload.failed.i: 3762 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 3763 // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 3764 // CHECK5: .omp_outlined..1.exit: 3765 // CHECK5-NEXT: ret i32 0 3766 // 3767 // 3768 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 3769 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 3770 // CHECK5-NEXT: entry: 3771 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3772 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 3773 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3774 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 3775 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3776 // CHECK5-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 3777 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3778 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 3779 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3780 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 3781 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 3782 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 3783 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 3784 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 3785 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 3786 // CHECK5-NEXT: ret void 3787 // 3788 // 3789 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 3790 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 3791 // CHECK5-NEXT: entry: 3792 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3793 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3794 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3795 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 3796 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3797 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3798 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 3799 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3800 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3801 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3802 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3803 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3804 // CHECK5-NEXT: [[K1:%.*]] = alloca i64, align 8 3805 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3806 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3807 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3808 // CHECK5-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 3809 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3810 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 3811 // CHECK5-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 3812 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3813 // CHECK5-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 3814 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3815 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3816 // CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3817 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3818 // CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 3819 // CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 3820 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3821 // CHECK5: omp.dispatch.cond: 3822 // CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 3823 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 3824 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3825 // CHECK5: omp.dispatch.body: 3826 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3827 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 3828 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3829 // CHECK5: omp.inner.for.cond: 3830 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 3831 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !26 3832 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 3833 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3834 // CHECK5: omp.inner.for.body: 3835 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 3836 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 3837 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 3838 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !26 3839 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !26 3840 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 3841 // CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 3842 // CHECK5-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 3843 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 3844 // CHECK5-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !26 3845 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26 3846 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 3847 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !26 3848 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3849 // CHECK5: omp.body.continue: 3850 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3851 // CHECK5: omp.inner.for.inc: 3852 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 3853 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 3854 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !26 3855 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 3856 // CHECK5: omp.inner.for.end: 3857 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3858 // CHECK5: omp.dispatch.inc: 3859 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 3860 // CHECK5: omp.dispatch.end: 3861 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3862 // CHECK5-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 3863 // CHECK5-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3864 // CHECK5: .omp.final.then: 3865 // CHECK5-NEXT: store i32 1, i32* [[I]], align 4 3866 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 3867 // CHECK5: .omp.final.done: 3868 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3869 // CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 3870 // CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 3871 // CHECK5: .omp.linear.pu: 3872 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[K1]], align 8 3873 // CHECK5-NEXT: store i64 [[TMP16]], i64* [[K_ADDR]], align 8 3874 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 3875 // CHECK5: .omp.linear.pu.done: 3876 // CHECK5-NEXT: ret void 3877 // 3878 // 3879 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 3880 // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 3881 // CHECK5-NEXT: entry: 3882 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3883 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 3884 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3885 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3886 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 3887 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3888 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3889 // CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 3890 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3891 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3892 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 3893 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3894 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3895 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3896 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 3897 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3898 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 3899 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 3900 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 3901 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 3902 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 3903 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3904 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 3905 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 3906 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 3907 // CHECK5-NEXT: ret void 3908 // 3909 // 3910 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 3911 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 3912 // CHECK5-NEXT: entry: 3913 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3914 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3915 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 3916 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 3917 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 3918 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3919 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 3920 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 3921 // CHECK5-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 3922 // CHECK5-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 3923 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3924 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3925 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3926 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3927 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 3928 // CHECK5-NEXT: [[LIN4:%.*]] = alloca i32, align 4 3929 // CHECK5-NEXT: [[A5:%.*]] = alloca i32, align 4 3930 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3931 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3932 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 3933 // CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 3934 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 3935 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 3936 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 3937 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 3938 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 3939 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 3940 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 3941 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 3942 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 3943 // CHECK5-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 3944 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3945 // CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 3946 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3947 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3948 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3949 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 3950 // CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 3951 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3952 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3953 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 3954 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3955 // CHECK5: cond.true: 3956 // CHECK5-NEXT: br label [[COND_END:%.*]] 3957 // CHECK5: cond.false: 3958 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3959 // CHECK5-NEXT: br label [[COND_END]] 3960 // CHECK5: cond.end: 3961 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 3962 // CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3963 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3964 // CHECK5-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 3965 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3966 // CHECK5: omp.inner.for.cond: 3967 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 3968 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29 3969 // CHECK5-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 3970 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3971 // CHECK5: omp.inner.for.body: 3972 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 3973 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 3974 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3975 // CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !29 3976 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !29 3977 // CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 3978 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 3979 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29 3980 // CHECK5-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 3981 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 3982 // CHECK5-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 3983 // CHECK5-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !29 3984 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !29 3985 // CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 3986 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 3987 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !29 3988 // CHECK5-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 3989 // CHECK5-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 3990 // CHECK5-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 3991 // CHECK5-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !29 3992 // CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !29 3993 // CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 3994 // CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 3995 // CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 3996 // CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !29 3997 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3998 // CHECK5: omp.body.continue: 3999 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4000 // CHECK5: omp.inner.for.inc: 4001 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 4002 // CHECK5-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 4003 // CHECK5-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 4004 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 4005 // CHECK5: omp.inner.for.end: 4006 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4007 // CHECK5: omp.loop.exit: 4008 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 4009 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4010 // CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 4011 // CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4012 // CHECK5: .omp.final.then: 4013 // CHECK5-NEXT: store i64 400, i64* [[IT]], align 8 4014 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4015 // CHECK5: .omp.final.done: 4016 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4017 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 4018 // CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4019 // CHECK5: .omp.linear.pu: 4020 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 4021 // CHECK5-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 4022 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 4023 // CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 4024 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4025 // CHECK5: .omp.linear.pu.done: 4026 // CHECK5-NEXT: ret void 4027 // 4028 // 4029 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 4030 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 4031 // CHECK5-NEXT: entry: 4032 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4033 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4034 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4035 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4036 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4037 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4038 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4039 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4040 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4041 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4042 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 4043 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4044 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4045 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4046 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 4047 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4048 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 4049 // CHECK5-NEXT: ret void 4050 // 4051 // 4052 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 4053 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 4054 // CHECK5-NEXT: entry: 4055 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4056 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4057 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4058 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4059 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4060 // CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 2 4061 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4062 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4063 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4064 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4065 // CHECK5-NEXT: [[IT:%.*]] = alloca i16, align 2 4066 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4067 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4068 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4069 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4070 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4071 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4072 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4073 // CHECK5-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 4074 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4075 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4076 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4077 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4078 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4079 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4080 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 4081 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4082 // CHECK5: cond.true: 4083 // CHECK5-NEXT: br label [[COND_END:%.*]] 4084 // CHECK5: cond.false: 4085 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4086 // CHECK5-NEXT: br label [[COND_END]] 4087 // CHECK5: cond.end: 4088 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4089 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4090 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4091 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4092 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4093 // CHECK5: omp.inner.for.cond: 4094 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 4095 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !32 4096 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4097 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4098 // CHECK5: omp.inner.for.body: 4099 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 4100 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 4101 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 4102 // CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 4103 // CHECK5-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !32 4104 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32 4105 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 4106 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !32 4107 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32 4108 // CHECK5-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 4109 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 4110 // CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 4111 // CHECK5-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !32 4112 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4113 // CHECK5: omp.body.continue: 4114 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4115 // CHECK5: omp.inner.for.inc: 4116 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 4117 // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 4118 // CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !32 4119 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 4120 // CHECK5: omp.inner.for.end: 4121 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4122 // CHECK5: omp.loop.exit: 4123 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4124 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4125 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4126 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4127 // CHECK5: .omp.final.then: 4128 // CHECK5-NEXT: store i16 22, i16* [[IT]], align 2 4129 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4130 // CHECK5: .omp.final.done: 4131 // CHECK5-NEXT: ret void 4132 // 4133 // 4134 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 4135 // CHECK5-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4136 // CHECK5-NEXT: entry: 4137 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4138 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4139 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4140 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4141 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4142 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4143 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4144 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4145 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4146 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4147 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4148 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4149 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4150 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4151 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4152 // CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4153 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4154 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4155 // CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4156 // CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4157 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4158 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4159 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4160 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4161 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4162 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4163 // CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4164 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4165 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4166 // CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4167 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4168 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4169 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4170 // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4171 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 4172 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 4173 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 4174 // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 4175 // CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 4176 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4177 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 4178 // CHECK5-NEXT: ret void 4179 // 4180 // 4181 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 4182 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 4183 // CHECK5-NEXT: entry: 4184 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4185 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4186 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4187 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4188 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4189 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4190 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4191 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4192 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4193 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4194 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4195 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4196 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4197 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 4198 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4199 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4200 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4201 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4202 // CHECK5-NEXT: [[IT:%.*]] = alloca i8, align 1 4203 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4204 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4205 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4206 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4207 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4208 // CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4209 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4210 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4211 // CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4212 // CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4213 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4214 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4215 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4216 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4217 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4218 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4219 // CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4220 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4221 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4222 // CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4223 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4224 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4225 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4226 // CHECK5-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 4227 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4228 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4229 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 4230 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4231 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4232 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4233 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4234 // CHECK5: omp.dispatch.cond: 4235 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4236 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 4237 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4238 // CHECK5: cond.true: 4239 // CHECK5-NEXT: br label [[COND_END:%.*]] 4240 // CHECK5: cond.false: 4241 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4242 // CHECK5-NEXT: br label [[COND_END]] 4243 // CHECK5: cond.end: 4244 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4245 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4246 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4247 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 4248 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4249 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4250 // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4251 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4252 // CHECK5: omp.dispatch.body: 4253 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4254 // CHECK5: omp.inner.for.cond: 4255 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 4256 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !35 4257 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4258 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4259 // CHECK5: omp.inner.for.body: 4260 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 4261 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4262 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 4263 // CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 4264 // CHECK5-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !35 4265 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !35 4266 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 4267 // CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !35 4268 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 4269 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !35 4270 // CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 4271 // CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 4272 // CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 4273 // CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !35 4274 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 4275 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !35 4276 // CHECK5-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 4277 // CHECK5-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 4278 // CHECK5-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 4279 // CHECK5-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !35 4280 // CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 4281 // CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 4282 // CHECK5-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !35 4283 // CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 4284 // CHECK5-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !35 4285 // CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 4286 // CHECK5-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 4287 // CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 4288 // CHECK5-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !35 4289 // CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 4290 // CHECK5-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !35 4291 // CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4292 // CHECK5-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !35 4293 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 4294 // CHECK5-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !35 4295 // CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4296 // CHECK5-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !35 4297 // CHECK5-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 4298 // CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 4299 // CHECK5-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 4300 // CHECK5-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !35 4301 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4302 // CHECK5: omp.body.continue: 4303 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4304 // CHECK5: omp.inner.for.inc: 4305 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 4306 // CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 4307 // CHECK5-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !35 4308 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 4309 // CHECK5: omp.inner.for.end: 4310 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4311 // CHECK5: omp.dispatch.inc: 4312 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4313 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4314 // CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4315 // CHECK5-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 4316 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4317 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4318 // CHECK5-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4319 // CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 4320 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 4321 // CHECK5: omp.dispatch.end: 4322 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4323 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4324 // CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 4325 // CHECK5-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4326 // CHECK5: .omp.final.then: 4327 // CHECK5-NEXT: store i8 96, i8* [[IT]], align 1 4328 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4329 // CHECK5: .omp.final.done: 4330 // CHECK5-NEXT: ret void 4331 // 4332 // 4333 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari 4334 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4335 // CHECK5-NEXT: entry: 4336 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4337 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4338 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 4339 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4340 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4341 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4342 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 4343 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 4344 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4345 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 4346 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4347 // CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 4348 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4349 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4350 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 4351 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4352 // CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 4353 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4354 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4355 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 4356 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4357 // CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 4358 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 4359 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 4360 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 4361 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 4362 // CHECK5-NEXT: ret i32 [[TMP8]] 4363 // 4364 // 4365 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4366 // CHECK5-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4367 // CHECK5-NEXT: entry: 4368 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4369 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4370 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 4371 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4372 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4373 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4374 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4375 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4376 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8 4377 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8 4378 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8 4379 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8 4380 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4381 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4382 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4383 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4384 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4385 // CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 4386 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4387 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 4388 // CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 4389 // CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 4390 // CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 4391 // CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 4392 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 4393 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 4394 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 4395 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 4396 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 4397 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 4398 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4399 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 4400 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8 4401 // CHECK5-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4402 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 4403 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 4404 // CHECK5-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 4405 // CHECK5-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 4406 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4407 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4408 // CHECK5-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1 4409 // CHECK5-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4410 // CHECK5: omp_if.then: 4411 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 4412 // CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]] 4413 // CHECK5-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2 4414 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 4415 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 bitcast ([6 x i64]* @.offload_sizes.11 to i8*), i64 48, i1 false) 4416 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4417 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1** 4418 // CHECK5-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 8 4419 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4420 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double** 4421 // CHECK5-NEXT: store double* [[A]], double** [[TMP17]], align 8 4422 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4423 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 4424 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4425 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 4426 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP20]], align 8 4427 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4428 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 4429 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP22]], align 8 4430 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4431 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 4432 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4433 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 4434 // CHECK5-NEXT: store i64 2, i64* [[TMP25]], align 8 4435 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4436 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 4437 // CHECK5-NEXT: store i64 2, i64* [[TMP27]], align 8 4438 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4439 // CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 4440 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4441 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 4442 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP30]], align 8 4443 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4444 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 4445 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP32]], align 8 4446 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4447 // CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 4448 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4449 // CHECK5-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 4450 // CHECK5-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 4451 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4452 // CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 4453 // CHECK5-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 4454 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4455 // CHECK5-NEXT: store i64 [[TMP12]], i64* [[TMP38]], align 8 4456 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4457 // CHECK5-NEXT: store i8* null, i8** [[TMP39]], align 8 4458 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4459 // CHECK5-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 4460 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP41]], align 8 4461 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4462 // CHECK5-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* 4463 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP43]], align 8 4464 // CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4465 // CHECK5-NEXT: store i8* null, i8** [[TMP44]], align 8 4466 // CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4467 // CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4468 // CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4469 // CHECK5-NEXT: [[TMP48:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4470 // CHECK5-NEXT: [[TOBOOL5:%.*]] = trunc i8 [[TMP48]] to i1 4471 // CHECK5-NEXT: [[TMP49:%.*]] = select i1 [[TOBOOL5]], i32 0, i32 1 4472 // CHECK5-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP45]], i8** [[TMP46]], i64* [[TMP47]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP49]]) 4473 // CHECK5-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 4474 // CHECK5-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4475 // CHECK5: omp_offload.failed: 4476 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4477 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4478 // CHECK5: omp_offload.cont: 4479 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4480 // CHECK5: omp_if.else: 4481 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4482 // CHECK5-NEXT: br label [[OMP_IF_END]] 4483 // CHECK5: omp_if.end: 4484 // CHECK5-NEXT: [[TMP52:%.*]] = mul nsw i64 1, [[TMP2]] 4485 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP52]] 4486 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 4487 // CHECK5-NEXT: [[TMP53:%.*]] = load i16, i16* [[ARRAYIDX6]], align 2 4488 // CHECK5-NEXT: [[CONV7:%.*]] = sext i16 [[TMP53]] to i32 4489 // CHECK5-NEXT: [[TMP54:%.*]] = load i32, i32* [[B]], align 4 4490 // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], [[TMP54]] 4491 // CHECK5-NEXT: [[TMP55:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4492 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP55]]) 4493 // CHECK5-NEXT: ret i32 [[ADD8]] 4494 // 4495 // 4496 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici 4497 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4498 // CHECK5-NEXT: entry: 4499 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4500 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4501 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4502 // CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 4503 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4504 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4505 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4506 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4507 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 4508 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 4509 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 4510 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4511 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4512 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 4513 // CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 4514 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4515 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4516 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 4517 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4518 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4519 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4520 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4521 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4522 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 4523 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 4524 // CHECK5-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 4525 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 4526 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4527 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4528 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4529 // CHECK5: omp_if.then: 4530 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4531 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 4532 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 4533 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4534 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 4535 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 4536 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4537 // CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 4538 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4539 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 4540 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 4541 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4542 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 4543 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 4544 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4545 // CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 4546 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4547 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 4548 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 4549 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4550 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 4551 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 4552 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4553 // CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8 4554 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4555 // CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 4556 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 4557 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4558 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 4559 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 4560 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4561 // CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8 4562 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4563 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4564 // CHECK5-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4565 // CHECK5-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 4566 // CHECK5-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4567 // CHECK5: omp_offload.failed: 4568 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4569 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4570 // CHECK5: omp_offload.cont: 4571 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4572 // CHECK5: omp_if.else: 4573 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4574 // CHECK5-NEXT: br label [[OMP_IF_END]] 4575 // CHECK5: omp_if.end: 4576 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 4577 // CHECK5-NEXT: ret i32 [[TMP31]] 4578 // 4579 // 4580 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4581 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 4582 // CHECK5-NEXT: entry: 4583 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4584 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4585 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4586 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4587 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4588 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4589 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 4590 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 4591 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 4592 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4593 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4594 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 4595 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4596 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4597 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 4598 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4599 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4600 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4601 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4602 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4603 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4604 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4605 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4606 // CHECK5: omp_if.then: 4607 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4608 // CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 4609 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 4610 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4611 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 4612 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 4613 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4614 // CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8 4615 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4616 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 4617 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 4618 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4619 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 4620 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 4621 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4622 // CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8 4623 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4624 // CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 4625 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 4626 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4627 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 4628 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 4629 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4630 // CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8 4631 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4632 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4633 // CHECK5-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4634 // CHECK5-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4635 // CHECK5-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4636 // CHECK5: omp_offload.failed: 4637 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4638 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4639 // CHECK5: omp_offload.cont: 4640 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4641 // CHECK5: omp_if.else: 4642 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4643 // CHECK5-NEXT: br label [[OMP_IF_END]] 4644 // CHECK5: omp_if.end: 4645 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 4646 // CHECK5-NEXT: ret i32 [[TMP24]] 4647 // 4648 // 4649 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 4650 // CHECK5-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4651 // CHECK5-NEXT: entry: 4652 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4653 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4654 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4655 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4656 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4657 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4658 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4659 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4660 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 4661 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 4662 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 4663 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4664 // CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4665 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4666 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4667 // CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4668 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4669 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4670 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4671 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4672 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4673 // CHECK5-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4674 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 4675 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4 4676 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4677 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4 4678 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 4679 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 4680 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 4681 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 4682 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 4683 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 4684 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4685 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1 4686 // CHECK5-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 4687 // CHECK5-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4688 // CHECK5: omp_if.then: 4689 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) 4690 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4691 // CHECK5: omp_if.else: 4692 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 4693 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 4694 // CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 4695 // CHECK5-NEXT: call void @.omp_outlined..10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR4]] 4696 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 4697 // CHECK5-NEXT: br label [[OMP_IF_END]] 4698 // CHECK5: omp_if.end: 4699 // CHECK5-NEXT: ret void 4700 // 4701 // 4702 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 4703 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 4704 // CHECK5-NEXT: entry: 4705 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4706 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4707 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4708 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4709 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4710 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4711 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4712 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4713 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4714 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4715 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4716 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4717 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4718 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4719 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 4720 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4721 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4722 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4723 // CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4724 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4725 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4726 // CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4727 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4728 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4729 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4730 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4731 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4732 // CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4733 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 4734 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4735 // CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 4736 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4737 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4738 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1 4739 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 4740 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4741 // CHECK5: omp_if.then: 4742 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4743 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 4744 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4745 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4746 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 4747 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4748 // CHECK5: cond.true: 4749 // CHECK5-NEXT: br label [[COND_END:%.*]] 4750 // CHECK5: cond.false: 4751 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4752 // CHECK5-NEXT: br label [[COND_END]] 4753 // CHECK5: cond.end: 4754 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 4755 // CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4756 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4757 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 4758 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4759 // CHECK5: omp.inner.for.cond: 4760 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 4761 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !38 4762 // CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 4763 // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4764 // CHECK5: omp.inner.for.body: 4765 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 4766 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 4767 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4768 // CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !38 4769 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !38 4770 // CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double 4771 // CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00 4772 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4773 // CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group !38 4774 // CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4775 // CHECK5-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38 4776 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 4777 // CHECK5-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group !38 4778 // CHECK5-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 4779 // CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 4780 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]] 4781 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 4782 // CHECK5-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !38 4783 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4784 // CHECK5: omp.body.continue: 4785 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4786 // CHECK5: omp.inner.for.inc: 4787 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 4788 // CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1 4789 // CHECK5-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !38 4790 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 4791 // CHECK5: omp.inner.for.end: 4792 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4793 // CHECK5: omp_if.else: 4794 // CHECK5-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4795 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 4796 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4797 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4798 // CHECK5-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3 4799 // CHECK5-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] 4800 // CHECK5: cond.true11: 4801 // CHECK5-NEXT: br label [[COND_END13:%.*]] 4802 // CHECK5: cond.false12: 4803 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4804 // CHECK5-NEXT: br label [[COND_END13]] 4805 // CHECK5: cond.end13: 4806 // CHECK5-NEXT: [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ] 4807 // CHECK5-NEXT: store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8 4808 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4809 // CHECK5-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 4810 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND15:%.*]] 4811 // CHECK5: omp.inner.for.cond15: 4812 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4813 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4814 // CHECK5-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 4815 // CHECK5-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]] 4816 // CHECK5: omp.inner.for.body17: 4817 // CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4818 // CHECK5-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400 4819 // CHECK5-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]] 4820 // CHECK5-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8 4821 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4 4822 // CHECK5-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double 4823 // CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00 4824 // CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4825 // CHECK5-NEXT: store double [[ADD21]], double* [[A22]], align 8 4826 // CHECK5-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4827 // CHECK5-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8 4828 // CHECK5-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00 4829 // CHECK5-NEXT: store double [[INC24]], double* [[A23]], align 8 4830 // CHECK5-NEXT: [[CONV25:%.*]] = fptosi double [[INC24]] to i16 4831 // CHECK5-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 4832 // CHECK5-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]] 4833 // CHECK5-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1 4834 // CHECK5-NEXT: store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2 4835 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] 4836 // CHECK5: omp.body.continue28: 4837 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC29:%.*]] 4838 // CHECK5: omp.inner.for.inc29: 4839 // CHECK5-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 4840 // CHECK5-NEXT: [[ADD30:%.*]] = add i64 [[TMP28]], 1 4841 // CHECK5-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 4842 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP42:![0-9]+]] 4843 // CHECK5: omp.inner.for.end31: 4844 // CHECK5-NEXT: br label [[OMP_IF_END]] 4845 // CHECK5: omp_if.end: 4846 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4847 // CHECK5: omp.loop.exit: 4848 // CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4849 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 4850 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 4851 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4852 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 4853 // CHECK5-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4854 // CHECK5: .omp.final.then: 4855 // CHECK5-NEXT: store i64 400, i64* [[IT]], align 8 4856 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4857 // CHECK5: .omp.final.done: 4858 // CHECK5-NEXT: ret void 4859 // 4860 // 4861 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 4862 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4863 // CHECK5-NEXT: entry: 4864 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4865 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4866 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4867 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4868 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4869 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4870 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4871 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4872 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4873 // CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4874 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4875 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4876 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4877 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4878 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4879 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4880 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4881 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 4882 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4883 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4884 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4885 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 4886 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4887 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 4888 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 4889 // CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 4890 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 4891 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 4892 // CHECK5-NEXT: ret void 4893 // 4894 // 4895 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..13 4896 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 4897 // CHECK5-NEXT: entry: 4898 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4899 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4900 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4901 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4902 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4903 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4904 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4905 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4906 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4907 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4908 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4909 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4910 // CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4911 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4912 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4913 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4914 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4915 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4916 // CHECK5-NEXT: ret void 4917 // 4918 // 4919 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 4920 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4921 // CHECK5-NEXT: entry: 4922 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4923 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4924 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4925 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4926 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4927 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4928 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4929 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4930 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4931 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4932 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4933 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4934 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4935 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 4936 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4937 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4938 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4939 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 4940 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4941 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 4942 // CHECK5-NEXT: ret void 4943 // 4944 // 4945 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..16 4946 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 4947 // CHECK5-NEXT: entry: 4948 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4949 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4950 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4951 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4952 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4953 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4954 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4955 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4956 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4957 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4958 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4959 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 4960 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4961 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4962 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4963 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4964 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4965 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4966 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4967 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4968 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4969 // CHECK5-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 4970 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4971 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4972 // CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4973 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4974 // CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4975 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4976 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 4977 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4978 // CHECK5: cond.true: 4979 // CHECK5-NEXT: br label [[COND_END:%.*]] 4980 // CHECK5: cond.false: 4981 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4982 // CHECK5-NEXT: br label [[COND_END]] 4983 // CHECK5: cond.end: 4984 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 4985 // CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4986 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4987 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 4988 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4989 // CHECK5: omp.inner.for.cond: 4990 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44 4991 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !44 4992 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 4993 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4994 // CHECK5: omp.inner.for.body: 4995 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44 4996 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 4997 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 4998 // CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !44 4999 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !44 5000 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 5001 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !44 5002 // CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !44 5003 // CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 5004 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 5005 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 5006 // CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !44 5007 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 5008 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 5009 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 5010 // CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !44 5011 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5012 // CHECK5: omp.body.continue: 5013 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5014 // CHECK5: omp.inner.for.inc: 5015 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44 5016 // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 5017 // CHECK5-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !44 5018 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] 5019 // CHECK5: omp.inner.for.end: 5020 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5021 // CHECK5: omp.loop.exit: 5022 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 5023 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5024 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5025 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5026 // CHECK5: .omp.final.then: 5027 // CHECK5-NEXT: store i64 11, i64* [[I]], align 8 5028 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5029 // CHECK5: .omp.final.done: 5030 // CHECK5-NEXT: ret void 5031 // 5032 // 5033 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5034 // CHECK5-SAME: () #[[ATTR8:[0-9]+]] { 5035 // CHECK5-NEXT: entry: 5036 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) 5037 // CHECK5-NEXT: ret void 5038 // 5039 // 5040 // CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv 5041 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 5042 // CHECK7-NEXT: entry: 5043 // CHECK7-NEXT: ret i64 0 5044 // 5045 // 5046 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi 5047 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5048 // CHECK7-NEXT: entry: 5049 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5050 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 5051 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 5052 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5053 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5054 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5055 // CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5056 // CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5057 // CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 5058 // CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 5059 // CHECK7-NEXT: [[K:%.*]] = alloca i64, align 8 5060 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5061 // CHECK7-NEXT: [[LIN:%.*]] = alloca i32, align 4 5062 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5063 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5064 // CHECK7-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 5065 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 5066 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 5067 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 5068 // CHECK7-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 5069 // CHECK7-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 5070 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 5071 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 5072 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 5073 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5074 // CHECK7-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 5075 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5076 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [10 x i8*], align 4 5077 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [10 x i8*], align 4 5078 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [10 x i8*], align 4 5079 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5080 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 5081 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5082 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 5083 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 5084 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5085 // CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 5086 // CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 5087 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 5088 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5089 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 5090 // CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 5091 // CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 5092 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 5093 // CHECK7-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 5094 // CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 5095 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 5096 // CHECK7-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]]) 5097 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5098 // CHECK7-NEXT: store i64 [[CALL]], i64* [[K]], align 8 5099 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 5100 // CHECK7-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 5101 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 5102 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]] 5103 // CHECK7-NEXT: store i32 12, i32* [[LIN]], align 4 5104 // CHECK7-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 5105 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5106 // CHECK7-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 5107 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5108 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4 5109 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4 5110 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 5111 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 5112 // CHECK7-NEXT: store i32 [[TMP15]], i32* [[A_CASTED2]], align 4 5113 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4 5114 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5115 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 5116 // CHECK7-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 5117 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5118 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 5119 // CHECK7-NEXT: store i32 [[TMP12]], i32* [[TMP20]], align 4 5120 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5121 // CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 5122 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5123 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 5124 // CHECK7-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 5125 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5126 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 5127 // CHECK7-NEXT: store i32 [[TMP14]], i32* [[TMP25]], align 4 5128 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5129 // CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 5130 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5131 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 5132 // CHECK7-NEXT: store i32 [[TMP16]], i32* [[TMP28]], align 4 5133 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5134 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 5135 // CHECK7-NEXT: store i32 [[TMP16]], i32* [[TMP30]], align 4 5136 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5137 // CHECK7-NEXT: store i8* null, i8** [[TMP31]], align 4 5138 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5139 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5140 // CHECK7-NEXT: [[TMP34:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, i32 3, i8** [[TMP32]], i8** [[TMP33]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5141 // CHECK7-NEXT: [[TMP35:%.*]] = icmp ne i32 [[TMP34]], 0 5142 // CHECK7-NEXT: br i1 [[TMP35]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5143 // CHECK7: omp_offload.failed: 5144 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]] 5145 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5146 // CHECK7: omp_offload.cont: 5147 // CHECK7-NEXT: [[TMP36:%.*]] = load i32, i32* [[A]], align 4 5148 // CHECK7-NEXT: store i32 [[TMP36]], i32* [[A_CASTED3]], align 4 5149 // CHECK7-NEXT: [[TMP37:%.*]] = load i32, i32* [[A_CASTED3]], align 4 5150 // CHECK7-NEXT: [[TMP38:%.*]] = load i16, i16* [[AA]], align 2 5151 // CHECK7-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 5152 // CHECK7-NEXT: store i16 [[TMP38]], i16* [[CONV5]], align 2 5153 // CHECK7-NEXT: [[TMP39:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 5154 // CHECK7-NEXT: [[TMP40:%.*]] = load i32, i32* [[N_ADDR]], align 4 5155 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP40]], 10 5156 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5157 // CHECK7: omp_if.then: 5158 // CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5159 // CHECK7-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32* 5160 // CHECK7-NEXT: store i32 [[TMP37]], i32* [[TMP42]], align 4 5161 // CHECK7-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5162 // CHECK7-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* 5163 // CHECK7-NEXT: store i32 [[TMP37]], i32* [[TMP44]], align 4 5164 // CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 5165 // CHECK7-NEXT: store i8* null, i8** [[TMP45]], align 4 5166 // CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 5167 // CHECK7-NEXT: [[TMP47:%.*]] = bitcast i8** [[TMP46]] to i32* 5168 // CHECK7-NEXT: store i32 [[TMP39]], i32* [[TMP47]], align 4 5169 // CHECK7-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 5170 // CHECK7-NEXT: [[TMP49:%.*]] = bitcast i8** [[TMP48]] to i32* 5171 // CHECK7-NEXT: store i32 [[TMP39]], i32* [[TMP49]], align 4 5172 // CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 5173 // CHECK7-NEXT: store i8* null, i8** [[TMP50]], align 4 5174 // CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5175 // CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5176 // CHECK7-NEXT: [[TMP53:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, i32 2, i8** [[TMP51]], i8** [[TMP52]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5177 // CHECK7-NEXT: [[TMP54:%.*]] = icmp ne i32 [[TMP53]], 0 5178 // CHECK7-NEXT: br i1 [[TMP54]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 5179 // CHECK7: omp_offload.failed9: 5180 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]] 5181 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT10]] 5182 // CHECK7: omp_offload.cont10: 5183 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 5184 // CHECK7: omp_if.else: 5185 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP37]], i32 [[TMP39]]) #[[ATTR4]] 5186 // CHECK7-NEXT: br label [[OMP_IF_END]] 5187 // CHECK7: omp_if.end: 5188 // CHECK7-NEXT: [[TMP55:%.*]] = load i32, i32* [[A]], align 4 5189 // CHECK7-NEXT: store i32 [[TMP55]], i32* [[DOTCAPTURE_EXPR_]], align 4 5190 // CHECK7-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 5191 // CHECK7-NEXT: store i32 [[TMP56]], i32* [[A_CASTED11]], align 4 5192 // CHECK7-NEXT: [[TMP57:%.*]] = load i32, i32* [[A_CASTED11]], align 4 5193 // CHECK7-NEXT: [[TMP58:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5194 // CHECK7-NEXT: store i32 [[TMP58]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5195 // CHECK7-NEXT: [[TMP59:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5196 // CHECK7-NEXT: [[TMP60:%.*]] = load i32, i32* [[N_ADDR]], align 4 5197 // CHECK7-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP60]], 20 5198 // CHECK7-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE19:%.*]] 5199 // CHECK7: omp_if.then13: 5200 // CHECK7-NEXT: [[TMP61:%.*]] = mul nuw i32 [[TMP1]], 4 5201 // CHECK7-NEXT: [[TMP62:%.*]] = sext i32 [[TMP61]] to i64 5202 // CHECK7-NEXT: [[TMP63:%.*]] = mul nuw i32 5, [[TMP3]] 5203 // CHECK7-NEXT: [[TMP64:%.*]] = mul nuw i32 [[TMP63]], 8 5204 // CHECK7-NEXT: [[TMP65:%.*]] = sext i32 [[TMP64]] to i64 5205 // CHECK7-NEXT: [[TMP66:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 5206 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP66]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 5207 // CHECK7-NEXT: [[TMP67:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5208 // CHECK7-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to i32* 5209 // CHECK7-NEXT: store i32 [[TMP57]], i32* [[TMP68]], align 4 5210 // CHECK7-NEXT: [[TMP69:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5211 // CHECK7-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to i32* 5212 // CHECK7-NEXT: store i32 [[TMP57]], i32* [[TMP70]], align 4 5213 // CHECK7-NEXT: [[TMP71:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 5214 // CHECK7-NEXT: store i8* null, i8** [[TMP71]], align 4 5215 // CHECK7-NEXT: [[TMP72:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 5216 // CHECK7-NEXT: [[TMP73:%.*]] = bitcast i8** [[TMP72]] to [10 x float]** 5217 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP73]], align 4 5218 // CHECK7-NEXT: [[TMP74:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 5219 // CHECK7-NEXT: [[TMP75:%.*]] = bitcast i8** [[TMP74]] to [10 x float]** 5220 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP75]], align 4 5221 // CHECK7-NEXT: [[TMP76:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 5222 // CHECK7-NEXT: store i8* null, i8** [[TMP76]], align 4 5223 // CHECK7-NEXT: [[TMP77:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 5224 // CHECK7-NEXT: [[TMP78:%.*]] = bitcast i8** [[TMP77]] to i32* 5225 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP78]], align 4 5226 // CHECK7-NEXT: [[TMP79:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 5227 // CHECK7-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* 5228 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP80]], align 4 5229 // CHECK7-NEXT: [[TMP81:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 5230 // CHECK7-NEXT: store i8* null, i8** [[TMP81]], align 4 5231 // CHECK7-NEXT: [[TMP82:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 5232 // CHECK7-NEXT: [[TMP83:%.*]] = bitcast i8** [[TMP82]] to float** 5233 // CHECK7-NEXT: store float* [[VLA]], float** [[TMP83]], align 4 5234 // CHECK7-NEXT: [[TMP84:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 5235 // CHECK7-NEXT: [[TMP85:%.*]] = bitcast i8** [[TMP84]] to float** 5236 // CHECK7-NEXT: store float* [[VLA]], float** [[TMP85]], align 4 5237 // CHECK7-NEXT: [[TMP86:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5238 // CHECK7-NEXT: store i64 [[TMP62]], i64* [[TMP86]], align 4 5239 // CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 5240 // CHECK7-NEXT: store i8* null, i8** [[TMP87]], align 4 5241 // CHECK7-NEXT: [[TMP88:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 5242 // CHECK7-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to [5 x [10 x double]]** 5243 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP89]], align 4 5244 // CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 5245 // CHECK7-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [5 x [10 x double]]** 5246 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP91]], align 4 5247 // CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 5248 // CHECK7-NEXT: store i8* null, i8** [[TMP92]], align 4 5249 // CHECK7-NEXT: [[TMP93:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 5250 // CHECK7-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to i32* 5251 // CHECK7-NEXT: store i32 5, i32* [[TMP94]], align 4 5252 // CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 5253 // CHECK7-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* 5254 // CHECK7-NEXT: store i32 5, i32* [[TMP96]], align 4 5255 // CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 5256 // CHECK7-NEXT: store i8* null, i8** [[TMP97]], align 4 5257 // CHECK7-NEXT: [[TMP98:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 5258 // CHECK7-NEXT: [[TMP99:%.*]] = bitcast i8** [[TMP98]] to i32* 5259 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP99]], align 4 5260 // CHECK7-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 5261 // CHECK7-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to i32* 5262 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP101]], align 4 5263 // CHECK7-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 5264 // CHECK7-NEXT: store i8* null, i8** [[TMP102]], align 4 5265 // CHECK7-NEXT: [[TMP103:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 5266 // CHECK7-NEXT: [[TMP104:%.*]] = bitcast i8** [[TMP103]] to double** 5267 // CHECK7-NEXT: store double* [[VLA1]], double** [[TMP104]], align 4 5268 // CHECK7-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 5269 // CHECK7-NEXT: [[TMP106:%.*]] = bitcast i8** [[TMP105]] to double** 5270 // CHECK7-NEXT: store double* [[VLA1]], double** [[TMP106]], align 4 5271 // CHECK7-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5272 // CHECK7-NEXT: store i64 [[TMP65]], i64* [[TMP107]], align 4 5273 // CHECK7-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 5274 // CHECK7-NEXT: store i8* null, i8** [[TMP108]], align 4 5275 // CHECK7-NEXT: [[TMP109:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 5276 // CHECK7-NEXT: [[TMP110:%.*]] = bitcast i8** [[TMP109]] to %struct.TT** 5277 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP110]], align 4 5278 // CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 5279 // CHECK7-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to %struct.TT** 5280 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP112]], align 4 5281 // CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 5282 // CHECK7-NEXT: store i8* null, i8** [[TMP113]], align 4 5283 // CHECK7-NEXT: [[TMP114:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 9 5284 // CHECK7-NEXT: [[TMP115:%.*]] = bitcast i8** [[TMP114]] to i32* 5285 // CHECK7-NEXT: store i32 [[TMP59]], i32* [[TMP115]], align 4 5286 // CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 9 5287 // CHECK7-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 5288 // CHECK7-NEXT: store i32 [[TMP59]], i32* [[TMP117]], align 4 5289 // CHECK7-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 9 5290 // CHECK7-NEXT: store i8* null, i8** [[TMP118]], align 4 5291 // CHECK7-NEXT: [[TMP119:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 5292 // CHECK7-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 5293 // CHECK7-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5294 // CHECK7-NEXT: [[TMP122:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, i32 10, i8** [[TMP119]], i8** [[TMP120]], i64* [[TMP121]], i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5295 // CHECK7-NEXT: [[TMP123:%.*]] = icmp ne i32 [[TMP122]], 0 5296 // CHECK7-NEXT: br i1 [[TMP123]], label [[OMP_OFFLOAD_FAILED17:%.*]], label [[OMP_OFFLOAD_CONT18:%.*]] 5297 // CHECK7: omp_offload.failed17: 5298 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]] 5299 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT18]] 5300 // CHECK7: omp_offload.cont18: 5301 // CHECK7-NEXT: br label [[OMP_IF_END20:%.*]] 5302 // CHECK7: omp_if.else19: 5303 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP57]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP59]]) #[[ATTR4]] 5304 // CHECK7-NEXT: br label [[OMP_IF_END20]] 5305 // CHECK7: omp_if.end20: 5306 // CHECK7-NEXT: [[TMP124:%.*]] = load i32, i32* [[A]], align 4 5307 // CHECK7-NEXT: [[TMP125:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5308 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP125]]) 5309 // CHECK7-NEXT: ret i32 [[TMP124]] 5310 // 5311 // 5312 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 5313 // CHECK7-SAME: () #[[ATTR2:[0-9]+]] { 5314 // CHECK7-NEXT: entry: 5315 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5316 // CHECK7-NEXT: ret void 5317 // 5318 // 5319 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. 5320 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 5321 // CHECK7-NEXT: entry: 5322 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5323 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5324 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5325 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5326 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5327 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5328 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5329 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5330 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5331 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5332 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5333 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5334 // CHECK7-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 5335 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5336 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5337 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5338 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5339 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5340 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5341 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 5342 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5343 // CHECK7: cond.true: 5344 // CHECK7-NEXT: br label [[COND_END:%.*]] 5345 // CHECK7: cond.false: 5346 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5347 // CHECK7-NEXT: br label [[COND_END]] 5348 // CHECK7: cond.end: 5349 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5350 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5351 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5352 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5353 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5354 // CHECK7: omp.inner.for.cond: 5355 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 5356 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 5357 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5358 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5359 // CHECK7: omp.inner.for.body: 5360 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 5361 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 5362 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 5363 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 5364 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5365 // CHECK7: omp.body.continue: 5366 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5367 // CHECK7: omp.inner.for.inc: 5368 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 5369 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 5370 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 5371 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 5372 // CHECK7: omp.inner.for.end: 5373 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5374 // CHECK7: omp.loop.exit: 5375 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5376 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5377 // CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 5378 // CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5379 // CHECK7: .omp.final.then: 5380 // CHECK7-NEXT: store i32 33, i32* [[I]], align 4 5381 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5382 // CHECK7: .omp.final.done: 5383 // CHECK7-NEXT: ret void 5384 // 5385 // 5386 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. 5387 // CHECK7-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 5388 // CHECK7-NEXT: entry: 5389 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 5390 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 5391 // CHECK7-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 5392 // CHECK7-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 5393 // CHECK7-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 5394 // CHECK7-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 5395 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 5396 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 5397 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 5398 // CHECK7-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5399 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 5400 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5401 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 5402 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 5403 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 5404 // CHECK7-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 5405 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 5406 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 5407 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 5408 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 5409 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 5410 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 5411 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 5412 // CHECK7-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 5413 // CHECK7-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 5414 // CHECK7-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 5415 // CHECK7-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 5416 // CHECK7-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 5417 // CHECK7-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 5418 // CHECK7-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 5419 // CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 5420 // CHECK7-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 5421 // CHECK7: omp_offload.failed.i: 5422 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 5423 // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 5424 // CHECK7: .omp_outlined..1.exit: 5425 // CHECK7-NEXT: ret i32 0 5426 // 5427 // 5428 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 5429 // CHECK7-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5430 // CHECK7-NEXT: entry: 5431 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5432 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 5433 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5434 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5435 // CHECK7-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 5436 // CHECK7-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 5437 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5438 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5439 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5440 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 5441 // CHECK7-NEXT: ret void 5442 // 5443 // 5444 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 5445 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5446 // CHECK7-NEXT: entry: 5447 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5448 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5449 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5450 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 5451 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5452 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5453 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 5454 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5455 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5456 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5457 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5458 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5459 // CHECK7-NEXT: [[K1:%.*]] = alloca i64, align 8 5460 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5461 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5462 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5463 // CHECK7-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 5464 // CHECK7-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 5465 // CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 5466 // CHECK7-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 5467 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5468 // CHECK7-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 5469 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5470 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5471 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5472 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5473 // CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 5474 // CHECK7-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 5475 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5476 // CHECK7: omp.dispatch.cond: 5477 // CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 5478 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 5479 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5480 // CHECK7: omp.dispatch.body: 5481 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5482 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 5483 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5484 // CHECK7: omp.inner.for.cond: 5485 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 5486 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !27 5487 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5488 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5489 // CHECK7: omp.inner.for.body: 5490 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 5491 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5492 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 5493 // CHECK7-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group !27 5494 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !27 5495 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 5496 // CHECK7-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 5497 // CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 5498 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 5499 // CHECK7-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group !27 5500 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !27 5501 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 5502 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !27 5503 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5504 // CHECK7: omp.body.continue: 5505 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5506 // CHECK7: omp.inner.for.inc: 5507 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 5508 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5509 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !27 5510 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 5511 // CHECK7: omp.inner.for.end: 5512 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5513 // CHECK7: omp.dispatch.inc: 5514 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 5515 // CHECK7: omp.dispatch.end: 5516 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5517 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5518 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5519 // CHECK7: .omp.final.then: 5520 // CHECK7-NEXT: store i32 1, i32* [[I]], align 4 5521 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5522 // CHECK7: .omp.final.done: 5523 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5524 // CHECK7-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 5525 // CHECK7-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5526 // CHECK7: .omp.linear.pu: 5527 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[K1]], align 8 5528 // CHECK7-NEXT: store i64 [[TMP17]], i64* [[TMP0]], align 8 5529 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5530 // CHECK7: .omp.linear.pu.done: 5531 // CHECK7-NEXT: ret void 5532 // 5533 // 5534 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 5535 // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 5536 // CHECK7-NEXT: entry: 5537 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5538 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5539 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5540 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5541 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5542 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5543 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5544 // CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 5545 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5546 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5547 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5548 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5549 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 5550 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5551 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 5552 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 5553 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 5554 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 5555 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 5556 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 5557 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 5558 // CHECK7-NEXT: ret void 5559 // 5560 // 5561 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 5562 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 5563 // CHECK7-NEXT: entry: 5564 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5565 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5566 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5567 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 5568 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5569 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5570 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 5571 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 5572 // CHECK7-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 5573 // CHECK7-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 5574 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5575 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5576 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5577 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5578 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 5579 // CHECK7-NEXT: [[LIN2:%.*]] = alloca i32, align 4 5580 // CHECK7-NEXT: [[A3:%.*]] = alloca i32, align 4 5581 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5582 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5583 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5584 // CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 5585 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5586 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5587 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 5588 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 5589 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5590 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 5591 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5592 // CHECK7-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 5593 // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5594 // CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 5595 // CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5596 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5597 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5598 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5599 // CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 5600 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5601 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5602 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 5603 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5604 // CHECK7: cond.true: 5605 // CHECK7-NEXT: br label [[COND_END:%.*]] 5606 // CHECK7: cond.false: 5607 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5608 // CHECK7-NEXT: br label [[COND_END]] 5609 // CHECK7: cond.end: 5610 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 5611 // CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5612 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5613 // CHECK7-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 5614 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5615 // CHECK7: omp.inner.for.cond: 5616 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 5617 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30 5618 // CHECK7-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 5619 // CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5620 // CHECK7: omp.inner.for.body: 5621 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 5622 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 5623 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5624 // CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !30 5625 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !30 5626 // CHECK7-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 5627 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 5628 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30 5629 // CHECK7-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 5630 // CHECK7-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 5631 // CHECK7-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 5632 // CHECK7-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !30 5633 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !30 5634 // CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 5635 // CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 5636 // CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !30 5637 // CHECK7-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 5638 // CHECK7-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 5639 // CHECK7-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 5640 // CHECK7-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !30 5641 // CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30 5642 // CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 5643 // CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 5644 // CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 5645 // CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !30 5646 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5647 // CHECK7: omp.body.continue: 5648 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5649 // CHECK7: omp.inner.for.inc: 5650 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 5651 // CHECK7-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 5652 // CHECK7-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 5653 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 5654 // CHECK7: omp.inner.for.end: 5655 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5656 // CHECK7: omp.loop.exit: 5657 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 5658 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5659 // CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 5660 // CHECK7-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5661 // CHECK7: .omp.final.then: 5662 // CHECK7-NEXT: store i64 400, i64* [[IT]], align 8 5663 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5664 // CHECK7: .omp.final.done: 5665 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5666 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 5667 // CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 5668 // CHECK7: .omp.linear.pu: 5669 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 5670 // CHECK7-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 5671 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 5672 // CHECK7-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 5673 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 5674 // CHECK7: .omp.linear.pu.done: 5675 // CHECK7-NEXT: ret void 5676 // 5677 // 5678 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 5679 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 5680 // CHECK7-NEXT: entry: 5681 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5682 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5683 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5684 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5685 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5686 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5687 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5688 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5689 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5690 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5691 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5692 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5693 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 5694 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5695 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 5696 // CHECK7-NEXT: ret void 5697 // 5698 // 5699 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 5700 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 5701 // CHECK7-NEXT: entry: 5702 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5703 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5704 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5705 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5706 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5707 // CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 2 5708 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5709 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5710 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5711 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5712 // CHECK7-NEXT: [[IT:%.*]] = alloca i16, align 2 5713 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5714 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5715 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5716 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5717 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5718 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5719 // CHECK7-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 5720 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5721 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5722 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5723 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5724 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5725 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5726 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 5727 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5728 // CHECK7: cond.true: 5729 // CHECK7-NEXT: br label [[COND_END:%.*]] 5730 // CHECK7: cond.false: 5731 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5732 // CHECK7-NEXT: br label [[COND_END]] 5733 // CHECK7: cond.end: 5734 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5735 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5736 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5737 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5738 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5739 // CHECK7: omp.inner.for.cond: 5740 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 5741 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !33 5742 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5743 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5744 // CHECK7: omp.inner.for.body: 5745 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 5746 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 5747 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 5748 // CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 5749 // CHECK7-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !33 5750 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 5751 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 5752 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 5753 // CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33 5754 // CHECK7-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 5755 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 5756 // CHECK7-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 5757 // CHECK7-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !33 5758 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5759 // CHECK7: omp.body.continue: 5760 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5761 // CHECK7: omp.inner.for.inc: 5762 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 5763 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 5764 // CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !33 5765 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 5766 // CHECK7: omp.inner.for.end: 5767 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5768 // CHECK7: omp.loop.exit: 5769 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5770 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5771 // CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 5772 // CHECK7-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5773 // CHECK7: .omp.final.then: 5774 // CHECK7-NEXT: store i16 22, i16* [[IT]], align 2 5775 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5776 // CHECK7: .omp.final.done: 5777 // CHECK7-NEXT: ret void 5778 // 5779 // 5780 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 5781 // CHECK7-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 5782 // CHECK7-NEXT: entry: 5783 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5784 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5785 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5786 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5787 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5788 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5789 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5790 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5791 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5792 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5793 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5794 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5795 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5796 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5797 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5798 // CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5799 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5800 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5801 // CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5802 // CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5803 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5804 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5805 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5806 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5807 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5808 // CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5809 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5810 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5811 // CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5812 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5813 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5814 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 5815 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 5816 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5817 // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5818 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5819 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 5820 // CHECK7-NEXT: ret void 5821 // 5822 // 5823 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 5824 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 5825 // CHECK7-NEXT: entry: 5826 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5827 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5828 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5829 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5830 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5831 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5832 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5833 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5834 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5835 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5836 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5837 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 5838 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5839 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 5840 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5841 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5842 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5843 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5844 // CHECK7-NEXT: [[IT:%.*]] = alloca i8, align 1 5845 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5846 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5847 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5848 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5849 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5850 // CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5851 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5852 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5853 // CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5854 // CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5855 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5856 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5857 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5858 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5859 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5860 // CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5861 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5862 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5863 // CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5864 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5865 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5866 // CHECK7-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 5867 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5868 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5869 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 5870 // CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5871 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 5872 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 5873 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5874 // CHECK7: omp.dispatch.cond: 5875 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5876 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 5877 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5878 // CHECK7: cond.true: 5879 // CHECK7-NEXT: br label [[COND_END:%.*]] 5880 // CHECK7: cond.false: 5881 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5882 // CHECK7-NEXT: br label [[COND_END]] 5883 // CHECK7: cond.end: 5884 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 5885 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5886 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5887 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 5888 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 5889 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5890 // CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 5891 // CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5892 // CHECK7: omp.dispatch.body: 5893 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5894 // CHECK7: omp.inner.for.cond: 5895 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 5896 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !36 5897 // CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 5898 // CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5899 // CHECK7: omp.inner.for.body: 5900 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 5901 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 5902 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 5903 // CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 5904 // CHECK7-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !36 5905 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !36 5906 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 5907 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !36 5908 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 5909 // CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !36 5910 // CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 5911 // CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 5912 // CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 5913 // CHECK7-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !36 5914 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 5915 // CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !36 5916 // CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 5917 // CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 5918 // CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 5919 // CHECK7-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !36 5920 // CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 5921 // CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 5922 // CHECK7-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !36 5923 // CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 5924 // CHECK7-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !36 5925 // CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 5926 // CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 5927 // CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 5928 // CHECK7-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !36 5929 // CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 5930 // CHECK7-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !36 5931 // CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 5932 // CHECK7-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !36 5933 // CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 5934 // CHECK7-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !36 5935 // CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 5936 // CHECK7-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !36 5937 // CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 5938 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 5939 // CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 5940 // CHECK7-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !36 5941 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5942 // CHECK7: omp.body.continue: 5943 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5944 // CHECK7: omp.inner.for.inc: 5945 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 5946 // CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 5947 // CHECK7-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !36 5948 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 5949 // CHECK7: omp.inner.for.end: 5950 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5951 // CHECK7: omp.dispatch.inc: 5952 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5953 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5954 // CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 5955 // CHECK7-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 5956 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5957 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 5958 // CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 5959 // CHECK7-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 5960 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 5961 // CHECK7: omp.dispatch.end: 5962 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 5963 // CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5964 // CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 5965 // CHECK7-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5966 // CHECK7: .omp.final.then: 5967 // CHECK7-NEXT: store i8 96, i8* [[IT]], align 1 5968 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5969 // CHECK7: .omp.final.done: 5970 // CHECK7-NEXT: ret void 5971 // 5972 // 5973 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari 5974 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5975 // CHECK7-NEXT: entry: 5976 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5977 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 5978 // CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 5979 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5980 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 5981 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 5982 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 5983 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 5984 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 5985 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 5986 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 5987 // CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 5988 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 5989 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 5990 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 5991 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5992 // CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 5993 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 5994 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 5995 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 5996 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 5997 // CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 5998 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 5999 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6000 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6001 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6002 // CHECK7-NEXT: ret i32 [[TMP8]] 6003 // 6004 // 6005 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6006 // CHECK7-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6007 // CHECK7-NEXT: entry: 6008 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6009 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6010 // CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 6011 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6012 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6013 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6014 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6015 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6016 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4 6017 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4 6018 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4 6019 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4 6020 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6021 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6022 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6023 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6024 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6025 // CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6026 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6027 // CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6028 // CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 6029 // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6030 // CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6031 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6032 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6033 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 6034 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 6035 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 6036 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 6037 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 6038 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 6039 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6040 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 6041 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* 6042 // CHECK7-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 6043 // CHECK7-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 6044 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6045 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6046 // CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 6047 // CHECK7-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6048 // CHECK7: omp_if.then: 6049 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6050 // CHECK7-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]] 6051 // CHECK7-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2 6052 // CHECK7-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 6053 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 6054 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 bitcast ([6 x i64]* @.offload_sizes.11 to i8*), i32 48, i1 false) 6055 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6056 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1** 6057 // CHECK7-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 4 6058 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6059 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double** 6060 // CHECK7-NEXT: store double* [[A]], double** [[TMP17]], align 4 6061 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6062 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 6063 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6064 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 6065 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP20]], align 4 6066 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6067 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 6068 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP22]], align 4 6069 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6070 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 6071 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6072 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 6073 // CHECK7-NEXT: store i32 2, i32* [[TMP25]], align 4 6074 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6075 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 6076 // CHECK7-NEXT: store i32 2, i32* [[TMP27]], align 4 6077 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6078 // CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 6079 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6080 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 6081 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 6082 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6083 // CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* 6084 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 6085 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6086 // CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 6087 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6088 // CHECK7-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 6089 // CHECK7-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 6090 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6091 // CHECK7-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 6092 // CHECK7-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 6093 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6094 // CHECK7-NEXT: store i64 [[TMP12]], i64* [[TMP38]], align 4 6095 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6096 // CHECK7-NEXT: store i8* null, i8** [[TMP39]], align 4 6097 // CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 6098 // CHECK7-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* 6099 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP41]], align 4 6100 // CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 6101 // CHECK7-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32* 6102 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP43]], align 4 6103 // CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 6104 // CHECK7-NEXT: store i8* null, i8** [[TMP44]], align 4 6105 // CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6106 // CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6107 // CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6108 // CHECK7-NEXT: [[TMP48:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6109 // CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP48]] to i1 6110 // CHECK7-NEXT: [[TMP49:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 6111 // CHECK7-NEXT: [[TMP50:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, i32 6, i8** [[TMP45]], i8** [[TMP46]], i64* [[TMP47]], i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 [[TMP49]]) 6112 // CHECK7-NEXT: [[TMP51:%.*]] = icmp ne i32 [[TMP50]], 0 6113 // CHECK7-NEXT: br i1 [[TMP51]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6114 // CHECK7: omp_offload.failed: 6115 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6116 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6117 // CHECK7: omp_offload.cont: 6118 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6119 // CHECK7: omp_if.else: 6120 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6121 // CHECK7-NEXT: br label [[OMP_IF_END]] 6122 // CHECK7: omp_if.end: 6123 // CHECK7-NEXT: [[TMP52:%.*]] = mul nsw i32 1, [[TMP1]] 6124 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP52]] 6125 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6126 // CHECK7-NEXT: [[TMP53:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2 6127 // CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP53]] to i32 6128 // CHECK7-NEXT: [[TMP54:%.*]] = load i32, i32* [[B]], align 4 6129 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP54]] 6130 // CHECK7-NEXT: [[TMP55:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6131 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP55]]) 6132 // CHECK7-NEXT: ret i32 [[ADD7]] 6133 // 6134 // 6135 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici 6136 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6137 // CHECK7-NEXT: entry: 6138 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6139 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6140 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6141 // CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 6142 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6143 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6144 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6145 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6146 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 6147 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 6148 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 6149 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6150 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6151 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 6152 // CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 6153 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6154 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6155 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6156 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6157 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6158 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 6159 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6160 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 6161 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 6162 // CHECK7-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 6163 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 6164 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6165 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6166 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6167 // CHECK7: omp_if.then: 6168 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6169 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 6170 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 6171 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6172 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 6173 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 6174 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6175 // CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 6176 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6177 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 6178 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 6179 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6180 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 6181 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 6182 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6183 // CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 6184 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6185 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 6186 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 6187 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6188 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 6189 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 6190 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6191 // CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 6192 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6193 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 6194 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 6195 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6196 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 6197 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 6198 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6199 // CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 6200 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6201 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6202 // CHECK7-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6203 // CHECK7-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 6204 // CHECK7-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6205 // CHECK7: omp_offload.failed: 6206 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6207 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6208 // CHECK7: omp_offload.cont: 6209 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6210 // CHECK7: omp_if.else: 6211 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6212 // CHECK7-NEXT: br label [[OMP_IF_END]] 6213 // CHECK7: omp_if.end: 6214 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 6215 // CHECK7-NEXT: ret i32 [[TMP31]] 6216 // 6217 // 6218 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6219 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 6220 // CHECK7-NEXT: entry: 6221 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6222 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6223 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6224 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6225 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6226 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6227 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 6228 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 6229 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 6230 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6231 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6232 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 6233 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6234 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6235 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6236 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6237 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6238 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 6239 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6240 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6241 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6242 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6243 // CHECK7: omp_if.then: 6244 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6245 // CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 6246 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 6247 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6248 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 6249 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 6250 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6251 // CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4 6252 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6253 // CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 6254 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 6255 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6256 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 6257 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 6258 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6259 // CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4 6260 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6261 // CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 6262 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 6263 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6264 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 6265 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 6266 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6267 // CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4 6268 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6269 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6270 // CHECK7-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB2]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6271 // CHECK7-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 6272 // CHECK7-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6273 // CHECK7: omp_offload.failed: 6274 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6275 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6276 // CHECK7: omp_offload.cont: 6277 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6278 // CHECK7: omp_if.else: 6279 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6280 // CHECK7-NEXT: br label [[OMP_IF_END]] 6281 // CHECK7: omp_if.end: 6282 // CHECK7-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 6283 // CHECK7-NEXT: ret i32 [[TMP24]] 6284 // 6285 // 6286 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 6287 // CHECK7-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6288 // CHECK7-NEXT: entry: 6289 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6290 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6291 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6292 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6293 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6294 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6295 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6296 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6297 // CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 6298 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 6299 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 6300 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6301 // CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6302 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6303 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6304 // CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6305 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6306 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6307 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6308 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6309 // CHECK7-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6310 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 6311 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 6312 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 6313 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 6314 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1 6315 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 6316 // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* 6317 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 6318 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 6319 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6320 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1 6321 // CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 6322 // CHECK7-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6323 // CHECK7: omp_if.then: 6324 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) 6325 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6326 // CHECK7: omp_if.else: 6327 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 6328 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 6329 // CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 6330 // CHECK7-NEXT: call void @.omp_outlined..10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR4]] 6331 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 6332 // CHECK7-NEXT: br label [[OMP_IF_END]] 6333 // CHECK7: omp_if.end: 6334 // CHECK7-NEXT: ret void 6335 // 6336 // 6337 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 6338 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 6339 // CHECK7-NEXT: entry: 6340 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6341 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6342 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6343 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6344 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6345 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6346 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6347 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6348 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6349 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6350 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6351 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6352 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6353 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6354 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 6355 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6356 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6357 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6358 // CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6359 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6360 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6361 // CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6362 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6363 // CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6364 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6365 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6366 // CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6367 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 6368 // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6369 // CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 6370 // CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6371 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6372 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 6373 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 6374 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6375 // CHECK7: omp_if.then: 6376 // CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6377 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 6378 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6379 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6380 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 6381 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6382 // CHECK7: cond.true: 6383 // CHECK7-NEXT: br label [[COND_END:%.*]] 6384 // CHECK7: cond.false: 6385 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6386 // CHECK7-NEXT: br label [[COND_END]] 6387 // CHECK7: cond.end: 6388 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 6389 // CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6390 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6391 // CHECK7-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 6392 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6393 // CHECK7: omp.inner.for.cond: 6394 // CHECK7-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39 6395 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !39 6396 // CHECK7-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 6397 // CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6398 // CHECK7: omp.inner.for.body: 6399 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39 6400 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 6401 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6402 // CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !39 6403 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !39 6404 // CHECK7-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double 6405 // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 6406 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6407 // CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4, !nontemporal !40, !llvm.access.group !39 6408 // CHECK7-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6409 // CHECK7-NEXT: [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39 6410 // CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 6411 // CHECK7-NEXT: store double [[INC]], double* [[A5]], align 4, !nontemporal !40, !llvm.access.group !39 6412 // CHECK7-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 6413 // CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 6414 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]] 6415 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6416 // CHECK7-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !39 6417 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6418 // CHECK7: omp.body.continue: 6419 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6420 // CHECK7: omp.inner.for.inc: 6421 // CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39 6422 // CHECK7-NEXT: [[ADD8:%.*]] = add i64 [[TMP16]], 1 6423 // CHECK7-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !39 6424 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] 6425 // CHECK7: omp.inner.for.end: 6426 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6427 // CHECK7: omp_if.else: 6428 // CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6429 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 6430 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6431 // CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6432 // CHECK7-NEXT: [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3 6433 // CHECK7-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] 6434 // CHECK7: cond.true10: 6435 // CHECK7-NEXT: br label [[COND_END12:%.*]] 6436 // CHECK7: cond.false11: 6437 // CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6438 // CHECK7-NEXT: br label [[COND_END12]] 6439 // CHECK7: cond.end12: 6440 // CHECK7-NEXT: [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ] 6441 // CHECK7-NEXT: store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8 6442 // CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6443 // CHECK7-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 6444 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND14:%.*]] 6445 // CHECK7: omp.inner.for.cond14: 6446 // CHECK7-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6447 // CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6448 // CHECK7-NEXT: [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 6449 // CHECK7-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]] 6450 // CHECK7: omp.inner.for.body16: 6451 // CHECK7-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6452 // CHECK7-NEXT: [[MUL17:%.*]] = mul i64 [[TMP24]], 400 6453 // CHECK7-NEXT: [[SUB18:%.*]] = sub i64 2000, [[MUL17]] 6454 // CHECK7-NEXT: store i64 [[SUB18]], i64* [[IT]], align 8 6455 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4 6456 // CHECK7-NEXT: [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double 6457 // CHECK7-NEXT: [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00 6458 // CHECK7-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6459 // CHECK7-NEXT: store double [[ADD20]], double* [[A21]], align 4 6460 // CHECK7-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6461 // CHECK7-NEXT: [[TMP26:%.*]] = load double, double* [[A22]], align 4 6462 // CHECK7-NEXT: [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00 6463 // CHECK7-NEXT: store double [[INC23]], double* [[A22]], align 4 6464 // CHECK7-NEXT: [[CONV24:%.*]] = fptosi double [[INC23]] to i16 6465 // CHECK7-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 6466 // CHECK7-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]] 6467 // CHECK7-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1 6468 // CHECK7-NEXT: store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2 6469 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] 6470 // CHECK7: omp.body.continue27: 6471 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] 6472 // CHECK7: omp.inner.for.inc28: 6473 // CHECK7-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6474 // CHECK7-NEXT: [[ADD29:%.*]] = add i64 [[TMP28]], 1 6475 // CHECK7-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8 6476 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP43:![0-9]+]] 6477 // CHECK7: omp.inner.for.end30: 6478 // CHECK7-NEXT: br label [[OMP_IF_END]] 6479 // CHECK7: omp_if.end: 6480 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6481 // CHECK7: omp.loop.exit: 6482 // CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6483 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 6484 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 6485 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6486 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 6487 // CHECK7-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6488 // CHECK7: .omp.final.then: 6489 // CHECK7-NEXT: store i64 400, i64* [[IT]], align 8 6490 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6491 // CHECK7: .omp.final.done: 6492 // CHECK7-NEXT: ret void 6493 // 6494 // 6495 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 6496 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6497 // CHECK7-NEXT: entry: 6498 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6499 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6500 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6501 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6502 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6503 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6504 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6505 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6506 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6507 // CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 6508 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6509 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6510 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 6511 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6512 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6513 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 6514 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 6515 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 6516 // CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6517 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 6518 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6519 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 6520 // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 6521 // CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 6522 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 6523 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 6524 // CHECK7-NEXT: ret void 6525 // 6526 // 6527 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..13 6528 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6529 // CHECK7-NEXT: entry: 6530 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6531 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6532 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6533 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6534 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 6535 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6536 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6537 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 6538 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6539 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6540 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6541 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6542 // CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 6543 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6544 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6545 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 6546 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6547 // CHECK7-NEXT: ret void 6548 // 6549 // 6550 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 6551 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6552 // CHECK7-NEXT: entry: 6553 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6554 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6555 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6556 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6557 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6558 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6559 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6560 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6561 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6562 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6563 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6564 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 6565 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 6566 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 6567 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6568 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 6569 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6570 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 6571 // CHECK7-NEXT: ret void 6572 // 6573 // 6574 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..16 6575 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6576 // CHECK7-NEXT: entry: 6577 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6578 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6579 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6580 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6581 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 6582 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6583 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6584 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6585 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6586 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6587 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6588 // CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 6589 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6590 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6591 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6592 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6593 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 6594 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6595 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 6596 // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6597 // CHECK7-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 6598 // CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6599 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6600 // CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6601 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 6602 // CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6603 // CHECK7-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6604 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 6605 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6606 // CHECK7: cond.true: 6607 // CHECK7-NEXT: br label [[COND_END:%.*]] 6608 // CHECK7: cond.false: 6609 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6610 // CHECK7-NEXT: br label [[COND_END]] 6611 // CHECK7: cond.end: 6612 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 6613 // CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6614 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6615 // CHECK7-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 6616 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6617 // CHECK7: omp.inner.for.cond: 6618 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45 6619 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !45 6620 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 6621 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6622 // CHECK7: omp.inner.for.body: 6623 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45 6624 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 6625 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 6626 // CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !45 6627 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !45 6628 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 6629 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !45 6630 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !45 6631 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 6632 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6633 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6634 // CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !45 6635 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 6636 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 6637 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 6638 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !45 6639 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6640 // CHECK7: omp.body.continue: 6641 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6642 // CHECK7: omp.inner.for.inc: 6643 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45 6644 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 6645 // CHECK7-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !45 6646 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] 6647 // CHECK7: omp.inner.for.end: 6648 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6649 // CHECK7: omp.loop.exit: 6650 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 6651 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6652 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 6653 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6654 // CHECK7: .omp.final.then: 6655 // CHECK7-NEXT: store i64 11, i64* [[I]], align 8 6656 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6657 // CHECK7: .omp.final.done: 6658 // CHECK7-NEXT: ret void 6659 // 6660 // 6661 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 6662 // CHECK7-SAME: () #[[ATTR8:[0-9]+]] { 6663 // CHECK7-NEXT: entry: 6664 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) 6665 // CHECK7-NEXT: ret void 6666 // 6667 // 6668 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv 6669 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 6670 // CHECK9-NEXT: entry: 6671 // CHECK9-NEXT: ret i64 0 6672 // 6673 // 6674 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi 6675 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 6676 // CHECK9-NEXT: entry: 6677 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6678 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 6679 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 6680 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 6681 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6682 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6683 // CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 6684 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6685 // CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 6686 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 6687 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6688 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6689 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6690 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 6691 // CHECK9-NEXT: [[K:%.*]] = alloca i64, align 8 6692 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 6693 // CHECK9-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 6694 // CHECK9-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 6695 // CHECK9-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 6696 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 6697 // CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 4 6698 // CHECK9-NEXT: [[K8:%.*]] = alloca i64, align 8 6699 // CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 4 6700 // CHECK9-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 6701 // CHECK9-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 6702 // CHECK9-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 6703 // CHECK9-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 6704 // CHECK9-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 6705 // CHECK9-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 6706 // CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 6707 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 6708 // CHECK9-NEXT: [[LIN27:%.*]] = alloca i32, align 4 6709 // CHECK9-NEXT: [[A28:%.*]] = alloca i32, align 4 6710 // CHECK9-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 6711 // CHECK9-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 6712 // CHECK9-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 6713 // CHECK9-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 6714 // CHECK9-NEXT: [[IT53:%.*]] = alloca i16, align 2 6715 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 6716 // CHECK9-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 6717 // CHECK9-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 6718 // CHECK9-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 6719 // CHECK9-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 6720 // CHECK9-NEXT: [[IT72:%.*]] = alloca i8, align 1 6721 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6722 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 6723 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 6724 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6725 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 6726 // CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6727 // CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 6728 // CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 6729 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 6730 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 6731 // CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 6732 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 6733 // CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 6734 // CHECK9-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 6735 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6736 // CHECK9-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 6737 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6738 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 6739 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6740 // CHECK9: omp.inner.for.cond: 6741 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 6742 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 6743 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 6744 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6745 // CHECK9: omp.inner.for.body: 6746 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 6747 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 6748 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 6749 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 6750 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6751 // CHECK9: omp.body.continue: 6752 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6753 // CHECK9: omp.inner.for.inc: 6754 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 6755 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 6756 // CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 6757 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 6758 // CHECK9: omp.inner.for.end: 6759 // CHECK9-NEXT: store i32 33, i32* [[I]], align 4 6760 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 6761 // CHECK9-NEXT: store i64 [[CALL]], i64* [[K]], align 8 6762 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 6763 // CHECK9-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 6764 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 6765 // CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4 6766 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8 6767 // CHECK9-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8 6768 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 6769 // CHECK9: omp.inner.for.cond9: 6770 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 6771 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6 6772 // CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 6773 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 6774 // CHECK9: omp.inner.for.body11: 6775 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 6776 // CHECK9-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 6777 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 6778 // CHECK9-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6 6779 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6 6780 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 6781 // CHECK9-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 6782 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 6783 // CHECK9-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 6784 // CHECK9-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6 6785 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6 6786 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 6787 // CHECK9-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6 6788 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 6789 // CHECK9: omp.body.continue16: 6790 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 6791 // CHECK9: omp.inner.for.inc17: 6792 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 6793 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 6794 // CHECK9-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 6795 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 6796 // CHECK9: omp.inner.for.end19: 6797 // CHECK9-NEXT: store i32 1, i32* [[I7]], align 4 6798 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[K8]], align 8 6799 // CHECK9-NEXT: store i64 [[TMP20]], i64* [[K]], align 8 6800 // CHECK9-NEXT: store i32 12, i32* [[LIN]], align 4 6801 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 6802 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 6803 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 6804 // CHECK9-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV23]], align 8 6805 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4 6806 // CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START24]], align 4 6807 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 6808 // CHECK9-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START25]], align 4 6809 // CHECK9-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 6810 // CHECK9-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 6811 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 6812 // CHECK9: omp.inner.for.cond29: 6813 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 6814 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !9 6815 // CHECK9-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 6816 // CHECK9-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 6817 // CHECK9: omp.inner.for.body31: 6818 // CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 6819 // CHECK9-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 6820 // CHECK9-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 6821 // CHECK9-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !9 6822 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !9 6823 // CHECK9-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 6824 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 6825 // CHECK9-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 6826 // CHECK9-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 6827 // CHECK9-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 6828 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 6829 // CHECK9-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !9 6830 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9 6831 // CHECK9-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 6832 // CHECK9-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 6833 // CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 6834 // CHECK9-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 6835 // CHECK9-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 6836 // CHECK9-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 6837 // CHECK9-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !9 6838 // CHECK9-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9 6839 // CHECK9-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 6840 // CHECK9-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 6841 // CHECK9-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 6842 // CHECK9-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !9 6843 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 6844 // CHECK9: omp.body.continue45: 6845 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 6846 // CHECK9: omp.inner.for.inc46: 6847 // CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 6848 // CHECK9-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 6849 // CHECK9-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 6850 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 6851 // CHECK9: omp.inner.for.end48: 6852 // CHECK9-NEXT: store i64 400, i64* [[IT]], align 8 6853 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN27]], align 4 6854 // CHECK9-NEXT: store i32 [[TMP35]], i32* [[LIN]], align 4 6855 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[A28]], align 4 6856 // CHECK9-NEXT: store i32 [[TMP36]], i32* [[A]], align 4 6857 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 6858 // CHECK9-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 6859 // CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 6860 // CHECK9-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV52]], align 4 6861 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 6862 // CHECK9: omp.inner.for.cond54: 6863 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 6864 // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !12 6865 // CHECK9-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 6866 // CHECK9-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 6867 // CHECK9: omp.inner.for.body56: 6868 // CHECK9-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 6869 // CHECK9-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 6870 // CHECK9-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 6871 // CHECK9-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 6872 // CHECK9-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !12 6873 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12 6874 // CHECK9-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 6875 // CHECK9-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !12 6876 // CHECK9-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12 6877 // CHECK9-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 6878 // CHECK9-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 6879 // CHECK9-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 6880 // CHECK9-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !12 6881 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 6882 // CHECK9: omp.body.continue64: 6883 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 6884 // CHECK9: omp.inner.for.inc65: 6885 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 6886 // CHECK9-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 6887 // CHECK9-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 6888 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 6889 // CHECK9: omp.inner.for.end67: 6890 // CHECK9-NEXT: store i16 22, i16* [[IT53]], align 2 6891 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 6892 // CHECK9-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 6893 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 6894 // CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 6895 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 6896 // CHECK9-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV71]], align 4 6897 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 6898 // CHECK9: omp.inner.for.cond73: 6899 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 6900 // CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !15 6901 // CHECK9-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 6902 // CHECK9-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 6903 // CHECK9: omp.inner.for.body75: 6904 // CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 6905 // CHECK9-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 6906 // CHECK9-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 6907 // CHECK9-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 6908 // CHECK9-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !15 6909 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15 6910 // CHECK9-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 6911 // CHECK9-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !15 6912 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 6913 // CHECK9-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15 6914 // CHECK9-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 6915 // CHECK9-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 6916 // CHECK9-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 6917 // CHECK9-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15 6918 // CHECK9-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 6919 // CHECK9-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 6920 // CHECK9-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 6921 // CHECK9-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 6922 // CHECK9-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 6923 // CHECK9-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 6924 // CHECK9-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 6925 // CHECK9-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i64 0, i64 2 6926 // CHECK9-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 6927 // CHECK9-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 6928 // CHECK9-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 6929 // CHECK9-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 6930 // CHECK9-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP53]] 6931 // CHECK9-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i64 3 6932 // CHECK9-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 6933 // CHECK9-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 6934 // CHECK9-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 6935 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 6936 // CHECK9-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15 6937 // CHECK9-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 6938 // CHECK9-NEXT: store i64 [[ADD93]], i64* [[X]], align 8, !llvm.access.group !15 6939 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 6940 // CHECK9-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15 6941 // CHECK9-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 6942 // CHECK9-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 6943 // CHECK9-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 6944 // CHECK9-NEXT: store i8 [[CONV96]], i8* [[Y]], align 8, !llvm.access.group !15 6945 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 6946 // CHECK9: omp.body.continue97: 6947 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 6948 // CHECK9: omp.inner.for.inc98: 6949 // CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 6950 // CHECK9-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 6951 // CHECK9-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 6952 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 6953 // CHECK9: omp.inner.for.end100: 6954 // CHECK9-NEXT: store i8 96, i8* [[IT72]], align 1 6955 // CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4 6956 // CHECK9-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6957 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP59]]) 6958 // CHECK9-NEXT: ret i32 [[TMP58]] 6959 // 6960 // 6961 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari 6962 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 6963 // CHECK9-NEXT: entry: 6964 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6965 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 6966 // CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 6967 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6968 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 6969 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6970 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 6971 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6972 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6973 // CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6974 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6975 // CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 6976 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6977 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6978 // CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6979 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6980 // CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 6981 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6982 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6983 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6984 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6985 // CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 6986 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6987 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6988 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6989 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6990 // CHECK9-NEXT: ret i32 [[TMP8]] 6991 // 6992 // 6993 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6994 // CHECK9-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6995 // CHECK9-NEXT: entry: 6996 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6997 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6998 // CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 6999 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7000 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7001 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7002 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7003 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7004 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7005 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7006 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7007 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7008 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7009 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7010 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7011 // CHECK9-NEXT: store i32 [[ADD]], i32* [[B]], align 4 7012 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7013 // CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7014 // CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 7015 // CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 7016 // CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 7017 // CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 7018 // CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 7019 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7020 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 7021 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7022 // CHECK9-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 7023 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7024 // CHECK9: omp.inner.for.cond: 7025 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 7026 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 7027 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]] 7028 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7029 // CHECK9: omp.inner.for.body: 7030 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 7031 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400 7032 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7033 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 7034 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18 7035 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 7036 // CHECK9-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 7037 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 7038 // CHECK9-NEXT: store double [[ADD2]], double* [[A]], align 8, !llvm.access.group !18 7039 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 7040 // CHECK9-NEXT: [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group !18 7041 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 7042 // CHECK9-NEXT: store double [[INC]], double* [[A3]], align 8, !llvm.access.group !18 7043 // CHECK9-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7044 // CHECK9-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] 7045 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]] 7046 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7047 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !18 7048 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7049 // CHECK9: omp.body.continue: 7050 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7051 // CHECK9: omp.inner.for.inc: 7052 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 7053 // CHECK9-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1 7054 // CHECK9-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 7055 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 7056 // CHECK9: omp.inner.for.end: 7057 // CHECK9-NEXT: store i64 400, i64* [[IT]], align 8 7058 // CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 7059 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] 7060 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 7061 // CHECK9-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 7062 // CHECK9-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32 7063 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4 7064 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]] 7065 // CHECK9-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7066 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) 7067 // CHECK9-NEXT: ret i32 [[ADD10]] 7068 // 7069 // 7070 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici 7071 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7072 // CHECK9-NEXT: entry: 7073 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7074 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7075 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7076 // CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 7077 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7078 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7079 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7080 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7081 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7082 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7083 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 7084 // CHECK9-NEXT: store i8 0, i8* [[AAA]], align 1 7085 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7086 // CHECK9-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 7087 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7088 // CHECK9-NEXT: ret i32 [[TMP0]] 7089 // 7090 // 7091 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7092 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 7093 // CHECK9-NEXT: entry: 7094 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7095 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7096 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7097 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7098 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7099 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7100 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7101 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7102 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7103 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7104 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7105 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 7106 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7107 // CHECK9-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 7108 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7109 // CHECK9-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 7110 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7111 // CHECK9: omp.inner.for.cond: 7112 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 7113 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !21 7114 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 7115 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7116 // CHECK9: omp.inner.for.body: 7117 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 7118 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 7119 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7120 // CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !21 7121 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !21 7122 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7123 // CHECK9-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !21 7124 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !21 7125 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7126 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7127 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7128 // CHECK9-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !21 7129 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 7130 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 7131 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7132 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !21 7133 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7134 // CHECK9: omp.body.continue: 7135 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7136 // CHECK9: omp.inner.for.inc: 7137 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 7138 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 7139 // CHECK9-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !21 7140 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 7141 // CHECK9: omp.inner.for.end: 7142 // CHECK9-NEXT: store i64 11, i64* [[I]], align 8 7143 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7144 // CHECK9-NEXT: ret i32 [[TMP8]] 7145 // 7146 // 7147 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv 7148 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 7149 // CHECK11-NEXT: entry: 7150 // CHECK11-NEXT: ret i64 0 7151 // 7152 // 7153 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi 7154 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7155 // CHECK11-NEXT: entry: 7156 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7157 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7158 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7159 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7160 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 7161 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7162 // CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7163 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 7164 // CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 7165 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7166 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7167 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7168 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7169 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7170 // CHECK11-NEXT: [[K:%.*]] = alloca i64, align 8 7171 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7172 // CHECK11-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7173 // CHECK11-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7174 // CHECK11-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7175 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7176 // CHECK11-NEXT: [[I7:%.*]] = alloca i32, align 4 7177 // CHECK11-NEXT: [[K8:%.*]] = alloca i64, align 8 7178 // CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 4 7179 // CHECK11-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 7180 // CHECK11-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7181 // CHECK11-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7182 // CHECK11-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7183 // CHECK11-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7184 // CHECK11-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7185 // CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7186 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 7187 // CHECK11-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7188 // CHECK11-NEXT: [[A28:%.*]] = alloca i32, align 4 7189 // CHECK11-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7190 // CHECK11-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7191 // CHECK11-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7192 // CHECK11-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7193 // CHECK11-NEXT: [[IT53:%.*]] = alloca i16, align 2 7194 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7195 // CHECK11-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7196 // CHECK11-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7197 // CHECK11-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7198 // CHECK11-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7199 // CHECK11-NEXT: [[IT72:%.*]] = alloca i8, align 1 7200 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7201 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 7202 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 7203 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7204 // CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 7205 // CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 7206 // CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 7207 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 7208 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7209 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 7210 // CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 7211 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 7212 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7213 // CHECK11-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 7214 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7215 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 7216 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7217 // CHECK11: omp.inner.for.cond: 7218 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 7219 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 7220 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7221 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7222 // CHECK11: omp.inner.for.body: 7223 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 7224 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 7225 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7226 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 7227 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7228 // CHECK11: omp.body.continue: 7229 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7230 // CHECK11: omp.inner.for.inc: 7231 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 7232 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 7233 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 7234 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7235 // CHECK11: omp.inner.for.end: 7236 // CHECK11-NEXT: store i32 33, i32* [[I]], align 4 7237 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7238 // CHECK11-NEXT: store i64 [[CALL]], i64* [[K]], align 8 7239 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 7240 // CHECK11-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 7241 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 7242 // CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4 7243 // CHECK11-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8 7244 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8 7245 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7246 // CHECK11: omp.inner.for.cond9: 7247 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 7248 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7 7249 // CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 7250 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7251 // CHECK11: omp.inner.for.body11: 7252 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 7253 // CHECK11-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 7254 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7255 // CHECK11-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7 7256 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7 7257 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 7258 // CHECK11-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 7259 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7260 // CHECK11-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 7261 // CHECK11-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7 7262 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7 7263 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 7264 // CHECK11-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7 7265 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7266 // CHECK11: omp.body.continue16: 7267 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7268 // CHECK11: omp.inner.for.inc17: 7269 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 7270 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 7271 // CHECK11-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 7272 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 7273 // CHECK11: omp.inner.for.end19: 7274 // CHECK11-NEXT: store i32 1, i32* [[I7]], align 4 7275 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[K8]], align 8 7276 // CHECK11-NEXT: store i64 [[TMP18]], i64* [[K]], align 8 7277 // CHECK11-NEXT: store i32 12, i32* [[LIN]], align 4 7278 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 7279 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 7280 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 7281 // CHECK11-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV23]], align 8 7282 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4 7283 // CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START24]], align 4 7284 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 7285 // CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START25]], align 4 7286 // CHECK11-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7287 // CHECK11-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 7288 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7289 // CHECK11: omp.inner.for.cond29: 7290 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 7291 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !10 7292 // CHECK11-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 7293 // CHECK11-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7294 // CHECK11: omp.inner.for.body31: 7295 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 7296 // CHECK11-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 7297 // CHECK11-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7298 // CHECK11-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !10 7299 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !10 7300 // CHECK11-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 7301 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 7302 // CHECK11-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 7303 // CHECK11-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 7304 // CHECK11-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7305 // CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7306 // CHECK11-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !10 7307 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10 7308 // CHECK11-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 7309 // CHECK11-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 7310 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 7311 // CHECK11-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 7312 // CHECK11-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7313 // CHECK11-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7314 // CHECK11-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !10 7315 // CHECK11-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 7316 // CHECK11-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 7317 // CHECK11-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7318 // CHECK11-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7319 // CHECK11-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !10 7320 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7321 // CHECK11: omp.body.continue45: 7322 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7323 // CHECK11: omp.inner.for.inc46: 7324 // CHECK11-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 7325 // CHECK11-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 7326 // CHECK11-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 7327 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 7328 // CHECK11: omp.inner.for.end48: 7329 // CHECK11-NEXT: store i64 400, i64* [[IT]], align 8 7330 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[LIN27]], align 4 7331 // CHECK11-NEXT: store i32 [[TMP33]], i32* [[LIN]], align 4 7332 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[A28]], align 4 7333 // CHECK11-NEXT: store i32 [[TMP34]], i32* [[A]], align 4 7334 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 7335 // CHECK11-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 7336 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 7337 // CHECK11-NEXT: store i32 [[TMP35]], i32* [[DOTOMP_IV52]], align 4 7338 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7339 // CHECK11: omp.inner.for.cond54: 7340 // CHECK11-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 7341 // CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !13 7342 // CHECK11-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 7343 // CHECK11-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7344 // CHECK11: omp.inner.for.body56: 7345 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 7346 // CHECK11-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 7347 // CHECK11-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7348 // CHECK11-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7349 // CHECK11-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !13 7350 // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 7351 // CHECK11-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 7352 // CHECK11-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !13 7353 // CHECK11-NEXT: [[TMP40:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 7354 // CHECK11-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 7355 // CHECK11-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7356 // CHECK11-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7357 // CHECK11-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !13 7358 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7359 // CHECK11: omp.body.continue64: 7360 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7361 // CHECK11: omp.inner.for.inc65: 7362 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 7363 // CHECK11-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 7364 // CHECK11-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 7365 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 7366 // CHECK11: omp.inner.for.end67: 7367 // CHECK11-NEXT: store i16 22, i16* [[IT53]], align 2 7368 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, i32* [[A]], align 4 7369 // CHECK11-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 7370 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 7371 // CHECK11-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 7372 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 7373 // CHECK11-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV71]], align 4 7374 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7375 // CHECK11: omp.inner.for.cond73: 7376 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 7377 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !16 7378 // CHECK11-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 7379 // CHECK11-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7380 // CHECK11: omp.inner.for.body75: 7381 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 7382 // CHECK11-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 7383 // CHECK11-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7384 // CHECK11-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7385 // CHECK11-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !16 7386 // CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 7387 // CHECK11-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 7388 // CHECK11-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !16 7389 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 7390 // CHECK11-NEXT: [[TMP48:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 7391 // CHECK11-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 7392 // CHECK11-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7393 // CHECK11-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7394 // CHECK11-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 7395 // CHECK11-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 7396 // CHECK11-NEXT: [[TMP49:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 7397 // CHECK11-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 7398 // CHECK11-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7399 // CHECK11-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7400 // CHECK11-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 7401 // CHECK11-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 7402 // CHECK11-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i32 0, i32 2 7403 // CHECK11-NEXT: [[TMP50:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 7404 // CHECK11-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 7405 // CHECK11-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 7406 // CHECK11-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 7407 // CHECK11-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP51]] 7408 // CHECK11-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i32 3 7409 // CHECK11-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 7410 // CHECK11-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 7411 // CHECK11-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 7412 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 7413 // CHECK11-NEXT: [[TMP53:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16 7414 // CHECK11-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 7415 // CHECK11-NEXT: store i64 [[ADD93]], i64* [[X]], align 4, !llvm.access.group !16 7416 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 7417 // CHECK11-NEXT: [[TMP54:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16 7418 // CHECK11-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 7419 // CHECK11-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7420 // CHECK11-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7421 // CHECK11-NEXT: store i8 [[CONV96]], i8* [[Y]], align 4, !llvm.access.group !16 7422 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7423 // CHECK11: omp.body.continue97: 7424 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7425 // CHECK11: omp.inner.for.inc98: 7426 // CHECK11-NEXT: [[TMP55:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 7427 // CHECK11-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 7428 // CHECK11-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 7429 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 7430 // CHECK11: omp.inner.for.end100: 7431 // CHECK11-NEXT: store i8 96, i8* [[IT72]], align 1 7432 // CHECK11-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 7433 // CHECK11-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 7434 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) 7435 // CHECK11-NEXT: ret i32 [[TMP56]] 7436 // 7437 // 7438 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari 7439 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7440 // CHECK11-NEXT: entry: 7441 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7442 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7443 // CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 7444 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7445 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 7446 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7447 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 7448 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 7449 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7450 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 7451 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7452 // CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 7453 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 7454 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7455 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 7456 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7457 // CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 7458 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 7459 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7460 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 7461 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7462 // CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 7463 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7464 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7465 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 7466 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7467 // CHECK11-NEXT: ret i32 [[TMP8]] 7468 // 7469 // 7470 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7471 // CHECK11-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7472 // CHECK11-NEXT: entry: 7473 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 7474 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7475 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 7476 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 7477 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7478 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 7479 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7480 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7481 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7482 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 7483 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 7484 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7485 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 7486 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7487 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7488 // CHECK11-NEXT: store i32 [[ADD]], i32* [[B]], align 4 7489 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7490 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 7491 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 7492 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 7493 // CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 7494 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 7495 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7496 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 7497 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7498 // CHECK11-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8 7499 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7500 // CHECK11: omp.inner.for.cond: 7501 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 7502 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19 7503 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]] 7504 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7505 // CHECK11: omp.inner.for.body: 7506 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 7507 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400 7508 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7509 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19 7510 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 7511 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double 7512 // CHECK11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 7513 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 7514 // CHECK11-NEXT: store double [[ADD2]], double* [[A]], align 4, !llvm.access.group !19 7515 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 7516 // CHECK11-NEXT: [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group !19 7517 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 7518 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4, !llvm.access.group !19 7519 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7520 // CHECK11-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] 7521 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]] 7522 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 7523 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group !19 7524 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7525 // CHECK11: omp.body.continue: 7526 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7527 // CHECK11: omp.inner.for.inc: 7528 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 7529 // CHECK11-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1 7530 // CHECK11-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 7531 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 7532 // CHECK11: omp.inner.for.end: 7533 // CHECK11-NEXT: store i64 400, i64* [[IT]], align 8 7534 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 7535 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] 7536 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 7537 // CHECK11-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 7538 // CHECK11-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32 7539 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4 7540 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]] 7541 // CHECK11-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 7542 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 7543 // CHECK11-NEXT: ret i32 [[ADD10]] 7544 // 7545 // 7546 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici 7547 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7548 // CHECK11-NEXT: entry: 7549 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7550 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7551 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7552 // CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 7553 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7554 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7555 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7556 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7557 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7558 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 7559 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 7560 // CHECK11-NEXT: store i8 0, i8* [[AAA]], align 1 7561 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7562 // CHECK11-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 7563 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7564 // CHECK11-NEXT: ret i32 [[TMP0]] 7565 // 7566 // 7567 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7568 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 7569 // CHECK11-NEXT: entry: 7570 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7571 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7572 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7573 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7574 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 7575 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7576 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7577 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7578 // CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8 7579 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7580 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 7581 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 7582 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7583 // CHECK11-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 7584 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7585 // CHECK11-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 7586 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7587 // CHECK11: omp.inner.for.cond: 7588 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 7589 // CHECK11-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !22 7590 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 7591 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7592 // CHECK11: omp.inner.for.body: 7593 // CHECK11-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 7594 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 7595 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7596 // CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !22 7597 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !22 7598 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7599 // CHECK11-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !22 7600 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !22 7601 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7602 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7603 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7604 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !22 7605 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 7606 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 7607 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7608 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !22 7609 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7610 // CHECK11: omp.body.continue: 7611 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7612 // CHECK11: omp.inner.for.inc: 7613 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 7614 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 7615 // CHECK11-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !22 7616 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 7617 // CHECK11: omp.inner.for.end: 7618 // CHECK11-NEXT: store i64 11, i64* [[I]], align 8 7619 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7620 // CHECK11-NEXT: ret i32 [[TMP8]] 7621 // 7622 // 7623 // CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv 7624 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { 7625 // CHECK13-NEXT: entry: 7626 // CHECK13-NEXT: ret i64 0 7627 // 7628 // 7629 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi 7630 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7631 // CHECK13-NEXT: entry: 7632 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7633 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 7634 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 7635 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7636 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7637 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7638 // CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7639 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7640 // CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7641 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 7642 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7643 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7644 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7645 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 7646 // CHECK13-NEXT: [[K:%.*]] = alloca i64, align 8 7647 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7648 // CHECK13-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7649 // CHECK13-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7650 // CHECK13-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7651 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7652 // CHECK13-NEXT: [[I7:%.*]] = alloca i32, align 4 7653 // CHECK13-NEXT: [[K8:%.*]] = alloca i64, align 8 7654 // CHECK13-NEXT: [[LIN:%.*]] = alloca i32, align 4 7655 // CHECK13-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 7656 // CHECK13-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7657 // CHECK13-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7658 // CHECK13-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7659 // CHECK13-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7660 // CHECK13-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7661 // CHECK13-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7662 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 7663 // CHECK13-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7664 // CHECK13-NEXT: [[A28:%.*]] = alloca i32, align 4 7665 // CHECK13-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7666 // CHECK13-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7667 // CHECK13-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7668 // CHECK13-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7669 // CHECK13-NEXT: [[IT53:%.*]] = alloca i16, align 2 7670 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7671 // CHECK13-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7672 // CHECK13-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7673 // CHECK13-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7674 // CHECK13-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7675 // CHECK13-NEXT: [[IT72:%.*]] = alloca i8, align 1 7676 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7677 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 7678 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 7679 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7680 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 7681 // CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 7682 // CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 7683 // CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 7684 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 7685 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 7686 // CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 7687 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 7688 // CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 7689 // CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 7690 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7691 // CHECK13-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 7692 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7693 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 7694 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7695 // CHECK13: omp.inner.for.cond: 7696 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 7697 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !2 7698 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 7699 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7700 // CHECK13: omp.inner.for.body: 7701 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 7702 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 7703 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7704 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !2 7705 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7706 // CHECK13: omp.body.continue: 7707 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7708 // CHECK13: omp.inner.for.inc: 7709 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 7710 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 7711 // CHECK13-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !2 7712 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 7713 // CHECK13: omp.inner.for.end: 7714 // CHECK13-NEXT: store i32 33, i32* [[I]], align 4 7715 // CHECK13-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7716 // CHECK13-NEXT: store i64 [[CALL]], i64* [[K]], align 8 7717 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 7718 // CHECK13-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 7719 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 7720 // CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4 7721 // CHECK13-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8 7722 // CHECK13-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8 7723 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7724 // CHECK13: omp.inner.for.cond9: 7725 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 7726 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !6 7727 // CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 7728 // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7729 // CHECK13: omp.inner.for.body11: 7730 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 7731 // CHECK13-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 7732 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7733 // CHECK13-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !6 7734 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !6 7735 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 7736 // CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 7737 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7738 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 7739 // CHECK13-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !6 7740 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !6 7741 // CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 7742 // CHECK13-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !6 7743 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7744 // CHECK13: omp.body.continue16: 7745 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7746 // CHECK13: omp.inner.for.inc17: 7747 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 7748 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 7749 // CHECK13-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !6 7750 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 7751 // CHECK13: omp.inner.for.end19: 7752 // CHECK13-NEXT: store i32 1, i32* [[I7]], align 4 7753 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[K8]], align 8 7754 // CHECK13-NEXT: store i64 [[TMP20]], i64* [[K]], align 8 7755 // CHECK13-NEXT: store i32 12, i32* [[LIN]], align 4 7756 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 7757 // CHECK13-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 7758 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 7759 // CHECK13-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV23]], align 8 7760 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4 7761 // CHECK13-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START24]], align 4 7762 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 7763 // CHECK13-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START25]], align 4 7764 // CHECK13-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7765 // CHECK13-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 7766 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7767 // CHECK13: omp.inner.for.cond29: 7768 // CHECK13-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 7769 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !9 7770 // CHECK13-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 7771 // CHECK13-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7772 // CHECK13: omp.inner.for.body31: 7773 // CHECK13-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 7774 // CHECK13-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 7775 // CHECK13-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7776 // CHECK13-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !9 7777 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !9 7778 // CHECK13-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 7779 // CHECK13-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 7780 // CHECK13-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 7781 // CHECK13-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 7782 // CHECK13-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7783 // CHECK13-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7784 // CHECK13-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !9 7785 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !9 7786 // CHECK13-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 7787 // CHECK13-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 7788 // CHECK13-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !9 7789 // CHECK13-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 7790 // CHECK13-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7791 // CHECK13-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7792 // CHECK13-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !9 7793 // CHECK13-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !9 7794 // CHECK13-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 7795 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7796 // CHECK13-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7797 // CHECK13-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !9 7798 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7799 // CHECK13: omp.body.continue45: 7800 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7801 // CHECK13: omp.inner.for.inc46: 7802 // CHECK13-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 7803 // CHECK13-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 7804 // CHECK13-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !9 7805 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 7806 // CHECK13: omp.inner.for.end48: 7807 // CHECK13-NEXT: store i64 400, i64* [[IT]], align 8 7808 // CHECK13-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN27]], align 4 7809 // CHECK13-NEXT: store i32 [[TMP35]], i32* [[LIN]], align 4 7810 // CHECK13-NEXT: [[TMP36:%.*]] = load i32, i32* [[A28]], align 4 7811 // CHECK13-NEXT: store i32 [[TMP36]], i32* [[A]], align 4 7812 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 7813 // CHECK13-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 7814 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 7815 // CHECK13-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV52]], align 4 7816 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7817 // CHECK13: omp.inner.for.cond54: 7818 // CHECK13-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 7819 // CHECK13-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !12 7820 // CHECK13-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 7821 // CHECK13-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7822 // CHECK13: omp.inner.for.body56: 7823 // CHECK13-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 7824 // CHECK13-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 7825 // CHECK13-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7826 // CHECK13-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7827 // CHECK13-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !12 7828 // CHECK13-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !12 7829 // CHECK13-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 7830 // CHECK13-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !12 7831 // CHECK13-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !12 7832 // CHECK13-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 7833 // CHECK13-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7834 // CHECK13-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7835 // CHECK13-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !12 7836 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7837 // CHECK13: omp.body.continue64: 7838 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7839 // CHECK13: omp.inner.for.inc65: 7840 // CHECK13-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 7841 // CHECK13-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 7842 // CHECK13-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !12 7843 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 7844 // CHECK13: omp.inner.for.end67: 7845 // CHECK13-NEXT: store i16 22, i16* [[IT53]], align 2 7846 // CHECK13-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 7847 // CHECK13-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 7848 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 7849 // CHECK13-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 7850 // CHECK13-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 7851 // CHECK13-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV71]], align 4 7852 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7853 // CHECK13: omp.inner.for.cond73: 7854 // CHECK13-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 7855 // CHECK13-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !15 7856 // CHECK13-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 7857 // CHECK13-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7858 // CHECK13: omp.inner.for.body75: 7859 // CHECK13-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 7860 // CHECK13-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 7861 // CHECK13-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7862 // CHECK13-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7863 // CHECK13-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !15 7864 // CHECK13-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !15 7865 // CHECK13-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 7866 // CHECK13-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !15 7867 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 7868 // CHECK13-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !15 7869 // CHECK13-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 7870 // CHECK13-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7871 // CHECK13-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7872 // CHECK13-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !15 7873 // CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 7874 // CHECK13-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 7875 // CHECK13-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 7876 // CHECK13-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7877 // CHECK13-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7878 // CHECK13-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !15 7879 // CHECK13-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 7880 // CHECK13-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i64 0, i64 2 7881 // CHECK13-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 7882 // CHECK13-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 7883 // CHECK13-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !15 7884 // CHECK13-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 7885 // CHECK13-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP53]] 7886 // CHECK13-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i64 3 7887 // CHECK13-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 7888 // CHECK13-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 7889 // CHECK13-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !15 7890 // CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 7891 // CHECK13-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !15 7892 // CHECK13-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 7893 // CHECK13-NEXT: store i64 [[ADD93]], i64* [[X]], align 8, !llvm.access.group !15 7894 // CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 7895 // CHECK13-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !15 7896 // CHECK13-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 7897 // CHECK13-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7898 // CHECK13-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7899 // CHECK13-NEXT: store i8 [[CONV96]], i8* [[Y]], align 8, !llvm.access.group !15 7900 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7901 // CHECK13: omp.body.continue97: 7902 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7903 // CHECK13: omp.inner.for.inc98: 7904 // CHECK13-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 7905 // CHECK13-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 7906 // CHECK13-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !15 7907 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 7908 // CHECK13: omp.inner.for.end100: 7909 // CHECK13-NEXT: store i8 96, i8* [[IT72]], align 1 7910 // CHECK13-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4 7911 // CHECK13-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7912 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP59]]) 7913 // CHECK13-NEXT: ret i32 [[TMP58]] 7914 // 7915 // 7916 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari 7917 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7918 // CHECK13-NEXT: entry: 7919 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7920 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 7921 // CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 7922 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7923 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 7924 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7925 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 7926 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 7927 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7928 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 7929 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7930 // CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 7931 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 7932 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7933 // CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 7934 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7935 // CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 7936 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 7937 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7938 // CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 7939 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7940 // CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 7941 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7942 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7943 // CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 7944 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7945 // CHECK13-NEXT: ret i32 [[TMP8]] 7946 // 7947 // 7948 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7949 // CHECK13-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7950 // CHECK13-NEXT: entry: 7951 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7952 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7953 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 7954 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7955 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7956 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 7957 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 7958 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7959 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7960 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7961 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 7962 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7963 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7964 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7965 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7966 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7967 // CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 7968 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7969 // CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7970 // CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 7971 // CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 7972 // CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 7973 // CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 7974 // CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 7975 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 7976 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 7977 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 7978 // CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 7979 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7980 // CHECK13-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 7981 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7982 // CHECK13-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 7983 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 7984 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 7985 // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7986 // CHECK13: omp_if.then: 7987 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7988 // CHECK13: omp.inner.for.cond: 7989 // CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 7990 // CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 7991 // CHECK13-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]] 7992 // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7993 // CHECK13: omp.inner.for.body: 7994 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 7995 // CHECK13-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400 7996 // CHECK13-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7997 // CHECK13-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 7998 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !18 7999 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double 8000 // CHECK13-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8001 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8002 // CHECK13-NEXT: store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group !18 8003 // CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8004 // CHECK13-NEXT: [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18 8005 // CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 8006 // CHECK13-NEXT: store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group !18 8007 // CHECK13-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8008 // CHECK13-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 8009 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] 8010 // CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 8011 // CHECK13-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !18 8012 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8013 // CHECK13: omp.body.continue: 8014 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8015 // CHECK13: omp.inner.for.inc: 8016 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 8017 // CHECK13-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1 8018 // CHECK13-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 8019 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 8020 // CHECK13: omp.inner.for.end: 8021 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]] 8022 // CHECK13: omp_if.else: 8023 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 8024 // CHECK13: omp.inner.for.cond8: 8025 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8026 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8027 // CHECK13-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]] 8028 // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 8029 // CHECK13: omp.inner.for.body10: 8030 // CHECK13-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8031 // CHECK13-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400 8032 // CHECK13-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 8033 // CHECK13-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8 8034 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4 8035 // CHECK13-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double 8036 // CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 8037 // CHECK13-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8038 // CHECK13-NEXT: store double [[ADD14]], double* [[A15]], align 8 8039 // CHECK13-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8040 // CHECK13-NEXT: [[TMP19:%.*]] = load double, double* [[A16]], align 8 8041 // CHECK13-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00 8042 // CHECK13-NEXT: store double [[INC17]], double* [[A16]], align 8 8043 // CHECK13-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 8044 // CHECK13-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] 8045 // CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]] 8046 // CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1 8047 // CHECK13-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2 8048 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 8049 // CHECK13: omp.body.continue21: 8050 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 8051 // CHECK13: omp.inner.for.inc22: 8052 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8053 // CHECK13-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1 8054 // CHECK13-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8 8055 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]] 8056 // CHECK13: omp.inner.for.end24: 8057 // CHECK13-NEXT: br label [[OMP_IF_END]] 8058 // CHECK13: omp_if.end: 8059 // CHECK13-NEXT: store i64 400, i64* [[IT]], align 8 8060 // CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] 8061 // CHECK13-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]] 8062 // CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1 8063 // CHECK13-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2 8064 // CHECK13-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32 8065 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4 8066 // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]] 8067 // CHECK13-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 8068 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) 8069 // CHECK13-NEXT: ret i32 [[ADD28]] 8070 // 8071 // 8072 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici 8073 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8074 // CHECK13-NEXT: entry: 8075 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8076 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8077 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8078 // CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 8079 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8080 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8081 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8082 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8083 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8084 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8085 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 8086 // CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 8087 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8088 // CHECK13-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 8089 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8090 // CHECK13-NEXT: ret i32 [[TMP0]] 8091 // 8092 // 8093 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8094 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 8095 // CHECK13-NEXT: entry: 8096 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8097 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8098 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8099 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8100 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 8101 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8102 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8103 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8104 // CHECK13-NEXT: [[I:%.*]] = alloca i64, align 8 8105 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8106 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8107 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 8108 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8109 // CHECK13-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 8110 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8111 // CHECK13-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 8112 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8113 // CHECK13: omp.inner.for.cond: 8114 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 8115 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !24 8116 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8117 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8118 // CHECK13: omp.inner.for.body: 8119 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 8120 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8121 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8122 // CHECK13-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !24 8123 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !24 8124 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8125 // CHECK13-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !24 8126 // CHECK13-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !24 8127 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8128 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8129 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8130 // CHECK13-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !24 8131 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 8132 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 8133 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8134 // CHECK13-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !24 8135 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8136 // CHECK13: omp.body.continue: 8137 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8138 // CHECK13: omp.inner.for.inc: 8139 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 8140 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 8141 // CHECK13-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !24 8142 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 8143 // CHECK13: omp.inner.for.end: 8144 // CHECK13-NEXT: store i64 11, i64* [[I]], align 8 8145 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8146 // CHECK13-NEXT: ret i32 [[TMP8]] 8147 // 8148 // 8149 // CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv 8150 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { 8151 // CHECK15-NEXT: entry: 8152 // CHECK15-NEXT: ret i64 0 8153 // 8154 // 8155 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi 8156 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8157 // CHECK15-NEXT: entry: 8158 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8159 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8160 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8161 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8162 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8163 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8164 // CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8165 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 8166 // CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 8167 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8168 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8169 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8170 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8171 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 8172 // CHECK15-NEXT: [[K:%.*]] = alloca i64, align 8 8173 // CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 8174 // CHECK15-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 8175 // CHECK15-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 8176 // CHECK15-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 8177 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 8178 // CHECK15-NEXT: [[I7:%.*]] = alloca i32, align 4 8179 // CHECK15-NEXT: [[K8:%.*]] = alloca i64, align 8 8180 // CHECK15-NEXT: [[LIN:%.*]] = alloca i32, align 4 8181 // CHECK15-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 8182 // CHECK15-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 8183 // CHECK15-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 8184 // CHECK15-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 8185 // CHECK15-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 8186 // CHECK15-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 8187 // CHECK15-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8188 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 8189 // CHECK15-NEXT: [[LIN27:%.*]] = alloca i32, align 4 8190 // CHECK15-NEXT: [[A28:%.*]] = alloca i32, align 4 8191 // CHECK15-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 8192 // CHECK15-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 8193 // CHECK15-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 8194 // CHECK15-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 8195 // CHECK15-NEXT: [[IT53:%.*]] = alloca i16, align 2 8196 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8197 // CHECK15-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 8198 // CHECK15-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 8199 // CHECK15-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 8200 // CHECK15-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 8201 // CHECK15-NEXT: [[IT72:%.*]] = alloca i8, align 1 8202 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8203 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 8204 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 8205 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8206 // CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 8207 // CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 8208 // CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 8209 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 8210 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8211 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 8212 // CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 8213 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 8214 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8215 // CHECK15-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 8216 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8217 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 8218 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8219 // CHECK15: omp.inner.for.cond: 8220 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 8221 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !3 8222 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8223 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8224 // CHECK15: omp.inner.for.body: 8225 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 8226 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 8227 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8228 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !3 8229 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8230 // CHECK15: omp.body.continue: 8231 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8232 // CHECK15: omp.inner.for.inc: 8233 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 8234 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 8235 // CHECK15-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !3 8236 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 8237 // CHECK15: omp.inner.for.end: 8238 // CHECK15-NEXT: store i32 33, i32* [[I]], align 4 8239 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 8240 // CHECK15-NEXT: store i64 [[CALL]], i64* [[K]], align 8 8241 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 8242 // CHECK15-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 8243 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 8244 // CHECK15-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4 8245 // CHECK15-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8 8246 // CHECK15-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8 8247 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 8248 // CHECK15: omp.inner.for.cond9: 8249 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 8250 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group !7 8251 // CHECK15-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 8252 // CHECK15-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8253 // CHECK15: omp.inner.for.body11: 8254 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 8255 // CHECK15-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 8256 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 8257 // CHECK15-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group !7 8258 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group !7 8259 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 8260 // CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 8261 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 8262 // CHECK15-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 8263 // CHECK15-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group !7 8264 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !7 8265 // CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 8266 // CHECK15-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group !7 8267 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8268 // CHECK15: omp.body.continue16: 8269 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8270 // CHECK15: omp.inner.for.inc17: 8271 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 8272 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 8273 // CHECK15-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group !7 8274 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 8275 // CHECK15: omp.inner.for.end19: 8276 // CHECK15-NEXT: store i32 1, i32* [[I7]], align 4 8277 // CHECK15-NEXT: [[TMP18:%.*]] = load i64, i64* [[K8]], align 8 8278 // CHECK15-NEXT: store i64 [[TMP18]], i64* [[K]], align 8 8279 // CHECK15-NEXT: store i32 12, i32* [[LIN]], align 4 8280 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 8281 // CHECK15-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 8282 // CHECK15-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 8283 // CHECK15-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV23]], align 8 8284 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4 8285 // CHECK15-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START24]], align 4 8286 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 8287 // CHECK15-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START25]], align 4 8288 // CHECK15-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 8289 // CHECK15-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 8290 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 8291 // CHECK15: omp.inner.for.cond29: 8292 // CHECK15-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 8293 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group !10 8294 // CHECK15-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 8295 // CHECK15-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 8296 // CHECK15: omp.inner.for.body31: 8297 // CHECK15-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 8298 // CHECK15-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 8299 // CHECK15-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 8300 // CHECK15-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group !10 8301 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group !10 8302 // CHECK15-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 8303 // CHECK15-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 8304 // CHECK15-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 8305 // CHECK15-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 8306 // CHECK15-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 8307 // CHECK15-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 8308 // CHECK15-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group !10 8309 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group !10 8310 // CHECK15-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 8311 // CHECK15-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 8312 // CHECK15-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !10 8313 // CHECK15-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 8314 // CHECK15-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 8315 // CHECK15-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 8316 // CHECK15-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group !10 8317 // CHECK15-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !10 8318 // CHECK15-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 8319 // CHECK15-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 8320 // CHECK15-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 8321 // CHECK15-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group !10 8322 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 8323 // CHECK15: omp.body.continue45: 8324 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 8325 // CHECK15: omp.inner.for.inc46: 8326 // CHECK15-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 8327 // CHECK15-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 8328 // CHECK15-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group !10 8329 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 8330 // CHECK15: omp.inner.for.end48: 8331 // CHECK15-NEXT: store i64 400, i64* [[IT]], align 8 8332 // CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[LIN27]], align 4 8333 // CHECK15-NEXT: store i32 [[TMP33]], i32* [[LIN]], align 4 8334 // CHECK15-NEXT: [[TMP34:%.*]] = load i32, i32* [[A28]], align 4 8335 // CHECK15-NEXT: store i32 [[TMP34]], i32* [[A]], align 4 8336 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 8337 // CHECK15-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 8338 // CHECK15-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 8339 // CHECK15-NEXT: store i32 [[TMP35]], i32* [[DOTOMP_IV52]], align 4 8340 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 8341 // CHECK15: omp.inner.for.cond54: 8342 // CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 8343 // CHECK15-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group !13 8344 // CHECK15-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 8345 // CHECK15-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 8346 // CHECK15: omp.inner.for.body56: 8347 // CHECK15-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 8348 // CHECK15-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 8349 // CHECK15-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 8350 // CHECK15-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 8351 // CHECK15-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group !13 8352 // CHECK15-NEXT: [[TMP39:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !13 8353 // CHECK15-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 8354 // CHECK15-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group !13 8355 // CHECK15-NEXT: [[TMP40:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !13 8356 // CHECK15-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 8357 // CHECK15-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 8358 // CHECK15-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 8359 // CHECK15-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group !13 8360 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 8361 // CHECK15: omp.body.continue64: 8362 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 8363 // CHECK15: omp.inner.for.inc65: 8364 // CHECK15-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 8365 // CHECK15-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 8366 // CHECK15-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group !13 8367 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 8368 // CHECK15: omp.inner.for.end67: 8369 // CHECK15-NEXT: store i16 22, i16* [[IT53]], align 2 8370 // CHECK15-NEXT: [[TMP42:%.*]] = load i32, i32* [[A]], align 4 8371 // CHECK15-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 8372 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 8373 // CHECK15-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 8374 // CHECK15-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 8375 // CHECK15-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV71]], align 4 8376 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 8377 // CHECK15: omp.inner.for.cond73: 8378 // CHECK15-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 8379 // CHECK15-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group !16 8380 // CHECK15-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 8381 // CHECK15-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 8382 // CHECK15: omp.inner.for.body75: 8383 // CHECK15-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 8384 // CHECK15-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 8385 // CHECK15-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 8386 // CHECK15-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 8387 // CHECK15-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group !16 8388 // CHECK15-NEXT: [[TMP47:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !16 8389 // CHECK15-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 8390 // CHECK15-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group !16 8391 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 8392 // CHECK15-NEXT: [[TMP48:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !16 8393 // CHECK15-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 8394 // CHECK15-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 8395 // CHECK15-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 8396 // CHECK15-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group !16 8397 // CHECK15-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 8398 // CHECK15-NEXT: [[TMP49:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 8399 // CHECK15-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 8400 // CHECK15-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 8401 // CHECK15-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 8402 // CHECK15-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group !16 8403 // CHECK15-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 8404 // CHECK15-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i32 0, i32 2 8405 // CHECK15-NEXT: [[TMP50:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 8406 // CHECK15-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 8407 // CHECK15-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group !16 8408 // CHECK15-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 8409 // CHECK15-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP51]] 8410 // CHECK15-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i32 3 8411 // CHECK15-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 8412 // CHECK15-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 8413 // CHECK15-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group !16 8414 // CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 8415 // CHECK15-NEXT: [[TMP53:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !16 8416 // CHECK15-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 8417 // CHECK15-NEXT: store i64 [[ADD93]], i64* [[X]], align 4, !llvm.access.group !16 8418 // CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 8419 // CHECK15-NEXT: [[TMP54:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !16 8420 // CHECK15-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 8421 // CHECK15-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 8422 // CHECK15-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 8423 // CHECK15-NEXT: store i8 [[CONV96]], i8* [[Y]], align 4, !llvm.access.group !16 8424 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 8425 // CHECK15: omp.body.continue97: 8426 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 8427 // CHECK15: omp.inner.for.inc98: 8428 // CHECK15-NEXT: [[TMP55:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 8429 // CHECK15-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 8430 // CHECK15-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group !16 8431 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 8432 // CHECK15: omp.inner.for.end100: 8433 // CHECK15-NEXT: store i8 96, i8* [[IT72]], align 1 8434 // CHECK15-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 8435 // CHECK15-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8436 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) 8437 // CHECK15-NEXT: ret i32 [[TMP56]] 8438 // 8439 // 8440 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari 8441 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8442 // CHECK15-NEXT: entry: 8443 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8444 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8445 // CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 8446 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8447 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 8448 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8449 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 8450 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 8451 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8452 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8453 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8454 // CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 8455 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 8456 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8457 // CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 8458 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8459 // CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 8460 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8461 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8462 // CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 8463 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8464 // CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 8465 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8466 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8467 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 8468 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8469 // CHECK15-NEXT: ret i32 [[TMP8]] 8470 // 8471 // 8472 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8473 // CHECK15-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8474 // CHECK15-NEXT: entry: 8475 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8476 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8477 // CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 8478 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8479 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8480 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8481 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 8482 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8483 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8484 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8485 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 8486 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8487 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8488 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8489 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8490 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8491 // CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 8492 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8493 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8494 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 8495 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 8496 // CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 8497 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 8498 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8499 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 8500 // CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 8501 // CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 8502 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8503 // CHECK15-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8504 // CHECK15-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8505 // CHECK15-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 8506 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 8507 // CHECK15-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 8508 // CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8509 // CHECK15: omp_if.then: 8510 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8511 // CHECK15: omp.inner.for.cond: 8512 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 8513 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !19 8514 // CHECK15-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 8515 // CHECK15-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8516 // CHECK15: omp.inner.for.body: 8517 // CHECK15-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 8518 // CHECK15-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 8519 // CHECK15-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8520 // CHECK15-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !19 8521 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group !19 8522 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 8523 // CHECK15-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8524 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8525 // CHECK15-NEXT: store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group !19 8526 // CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8527 // CHECK15-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19 8528 // CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 8529 // CHECK15-NEXT: store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group !19 8530 // CHECK15-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8531 // CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 8532 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] 8533 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8534 // CHECK15-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !19 8535 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8536 // CHECK15: omp.body.continue: 8537 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8538 // CHECK15: omp.inner.for.inc: 8539 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 8540 // CHECK15-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1 8541 // CHECK15-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !19 8542 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 8543 // CHECK15: omp.inner.for.end: 8544 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] 8545 // CHECK15: omp_if.else: 8546 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 8547 // CHECK15: omp.inner.for.cond8: 8548 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8549 // CHECK15-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8550 // CHECK15-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]] 8551 // CHECK15-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 8552 // CHECK15: omp.inner.for.body10: 8553 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8554 // CHECK15-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400 8555 // CHECK15-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 8556 // CHECK15-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8 8557 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 8558 // CHECK15-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double 8559 // CHECK15-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 8560 // CHECK15-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8561 // CHECK15-NEXT: store double [[ADD14]], double* [[A15]], align 4 8562 // CHECK15-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8563 // CHECK15-NEXT: [[TMP18:%.*]] = load double, double* [[A16]], align 4 8564 // CHECK15-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00 8565 // CHECK15-NEXT: store double [[INC17]], double* [[A16]], align 4 8566 // CHECK15-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 8567 // CHECK15-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] 8568 // CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]] 8569 // CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1 8570 // CHECK15-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2 8571 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 8572 // CHECK15: omp.body.continue21: 8573 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 8574 // CHECK15: omp.inner.for.inc22: 8575 // CHECK15-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8576 // CHECK15-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1 8577 // CHECK15-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8 8578 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]] 8579 // CHECK15: omp.inner.for.end24: 8580 // CHECK15-NEXT: br label [[OMP_IF_END]] 8581 // CHECK15: omp_if.end: 8582 // CHECK15-NEXT: store i64 400, i64* [[IT]], align 8 8583 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] 8584 // CHECK15-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]] 8585 // CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1 8586 // CHECK15-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2 8587 // CHECK15-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32 8588 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4 8589 // CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]] 8590 // CHECK15-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8591 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 8592 // CHECK15-NEXT: ret i32 [[ADD28]] 8593 // 8594 // 8595 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici 8596 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8597 // CHECK15-NEXT: entry: 8598 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8599 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8600 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8601 // CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 8602 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8603 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8604 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8605 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8606 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8607 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 8608 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 8609 // CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 8610 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8611 // CHECK15-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 8612 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8613 // CHECK15-NEXT: ret i32 [[TMP0]] 8614 // 8615 // 8616 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8617 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 8618 // CHECK15-NEXT: entry: 8619 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8620 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8621 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8622 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8623 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 8624 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8625 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8626 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8627 // CHECK15-NEXT: [[I:%.*]] = alloca i64, align 8 8628 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8629 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 8630 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 8631 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8632 // CHECK15-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 8633 // CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8634 // CHECK15-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 8635 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8636 // CHECK15: omp.inner.for.cond: 8637 // CHECK15-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 8638 // CHECK15-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !25 8639 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8640 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8641 // CHECK15: omp.inner.for.body: 8642 // CHECK15-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 8643 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8644 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8645 // CHECK15-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !25 8646 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group !25 8647 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8648 // CHECK15-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group !25 8649 // CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group !25 8650 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8651 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8652 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8653 // CHECK15-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group !25 8654 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 8655 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 8656 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8657 // CHECK15-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !25 8658 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8659 // CHECK15: omp.body.continue: 8660 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8661 // CHECK15: omp.inner.for.inc: 8662 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 8663 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 8664 // CHECK15-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !25 8665 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 8666 // CHECK15: omp.inner.for.end: 8667 // CHECK15-NEXT: store i64 11, i64* [[I]], align 8 8668 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8669 // CHECK15-NEXT: ret i32 [[TMP8]] 8670 // 8671 // 8672 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 8673 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { 8674 // CHECK17-NEXT: entry: 8675 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 8676 // CHECK17-NEXT: ret void 8677 // 8678 // 8679 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 8680 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 8681 // CHECK17-NEXT: entry: 8682 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8683 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8684 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8685 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 8686 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8687 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8688 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8689 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8690 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 8691 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8692 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8693 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8694 // CHECK17-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 8695 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8696 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8697 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8698 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 8699 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8700 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8701 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 8702 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8703 // CHECK17: cond.true: 8704 // CHECK17-NEXT: br label [[COND_END:%.*]] 8705 // CHECK17: cond.false: 8706 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8707 // CHECK17-NEXT: br label [[COND_END]] 8708 // CHECK17: cond.end: 8709 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 8710 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8711 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8712 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 8713 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8714 // CHECK17: omp.inner.for.cond: 8715 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 8716 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 8717 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8718 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8719 // CHECK17: omp.inner.for.body: 8720 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 8721 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 8722 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8723 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 8724 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8725 // CHECK17: omp.body.continue: 8726 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8727 // CHECK17: omp.inner.for.inc: 8728 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 8729 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 8730 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 8731 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 8732 // CHECK17: omp.inner.for.end: 8733 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8734 // CHECK17: omp.loop.exit: 8735 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 8736 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 8737 // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 8738 // CHECK17-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 8739 // CHECK17: .omp.final.then: 8740 // CHECK17-NEXT: store i32 33, i32* [[I]], align 4 8741 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 8742 // CHECK17: .omp.final.done: 8743 // CHECK17-NEXT: ret void 8744 // 8745 // 8746 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 8747 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 8748 // CHECK17-NEXT: entry: 8749 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8750 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 8751 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8752 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8753 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 8754 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8755 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8756 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 8757 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8758 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8759 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 8760 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8761 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 8762 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8763 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 8764 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8765 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 8766 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 8767 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 8768 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 8769 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 8770 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8771 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 8772 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 8773 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 8774 // CHECK17-NEXT: ret void 8775 // 8776 // 8777 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 8778 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 8779 // CHECK17-NEXT: entry: 8780 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8781 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8782 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8783 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 8784 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8785 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8786 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 8787 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 8788 // CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 8789 // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8790 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8791 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8792 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8793 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8794 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 8795 // CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4 8796 // CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4 8797 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8798 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8799 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8800 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 8801 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8802 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8803 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 8804 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8805 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 8806 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 8807 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 8808 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 8809 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 8810 // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 8811 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8812 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8813 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8814 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8815 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8816 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 8817 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 8818 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8819 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8820 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 8821 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8822 // CHECK17: cond.true: 8823 // CHECK17-NEXT: br label [[COND_END:%.*]] 8824 // CHECK17: cond.false: 8825 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8826 // CHECK17-NEXT: br label [[COND_END]] 8827 // CHECK17: cond.end: 8828 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 8829 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8830 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8831 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 8832 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8833 // CHECK17: omp.inner.for.cond: 8834 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 8835 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17 8836 // CHECK17-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 8837 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8838 // CHECK17: omp.inner.for.body: 8839 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 8840 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 8841 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8842 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17 8843 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17 8844 // CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 8845 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 8846 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 8847 // CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 8848 // CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 8849 // CHECK17-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 8850 // CHECK17-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17 8851 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17 8852 // CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 8853 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 8854 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 8855 // CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 8856 // CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 8857 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 8858 // CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17 8859 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17 8860 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 8861 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 8862 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 8863 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17 8864 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8865 // CHECK17: omp.body.continue: 8866 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8867 // CHECK17: omp.inner.for.inc: 8868 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 8869 // CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 8870 // CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 8871 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 8872 // CHECK17: omp.inner.for.end: 8873 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8874 // CHECK17: omp.loop.exit: 8875 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 8876 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 8877 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 8878 // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 8879 // CHECK17: .omp.final.then: 8880 // CHECK17-NEXT: store i64 400, i64* [[IT]], align 8 8881 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 8882 // CHECK17: .omp.final.done: 8883 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 8884 // CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 8885 // CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 8886 // CHECK17: .omp.linear.pu: 8887 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 8888 // CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 8889 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 8890 // CHECK17-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 8891 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 8892 // CHECK17: .omp.linear.pu.done: 8893 // CHECK17-NEXT: ret void 8894 // 8895 // 8896 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv 8897 // CHECK17-SAME: () #[[ATTR3:[0-9]+]] { 8898 // CHECK17-NEXT: entry: 8899 // CHECK17-NEXT: ret i64 0 8900 // 8901 // 8902 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 8903 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 8904 // CHECK17-NEXT: entry: 8905 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8906 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8907 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 8908 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 8909 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8910 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8911 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8912 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8913 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 8914 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8915 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 8916 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 8917 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 8918 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8919 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 8920 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8921 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 8922 // CHECK17-NEXT: ret void 8923 // 8924 // 8925 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 8926 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 8927 // CHECK17-NEXT: entry: 8928 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8929 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8930 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8931 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8932 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8933 // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 8934 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8935 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8936 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8937 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8938 // CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2 8939 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8940 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8941 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8942 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8943 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8944 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8945 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8946 // CHECK17-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 8947 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8948 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8949 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8950 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 8951 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8952 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8953 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 8954 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8955 // CHECK17: cond.true: 8956 // CHECK17-NEXT: br label [[COND_END:%.*]] 8957 // CHECK17: cond.false: 8958 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8959 // CHECK17-NEXT: br label [[COND_END]] 8960 // CHECK17: cond.end: 8961 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 8962 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8963 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8964 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 8965 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8966 // CHECK17: omp.inner.for.cond: 8967 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 8968 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 8969 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8970 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8971 // CHECK17: omp.inner.for.body: 8972 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 8973 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 8974 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 8975 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 8976 // CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20 8977 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20 8978 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 8979 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20 8980 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20 8981 // CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 8982 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 8983 // CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 8984 // CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20 8985 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8986 // CHECK17: omp.body.continue: 8987 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8988 // CHECK17: omp.inner.for.inc: 8989 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 8990 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 8991 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 8992 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 8993 // CHECK17: omp.inner.for.end: 8994 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8995 // CHECK17: omp.loop.exit: 8996 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 8997 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 8998 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 8999 // CHECK17-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9000 // CHECK17: .omp.final.then: 9001 // CHECK17-NEXT: store i16 22, i16* [[IT]], align 2 9002 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9003 // CHECK17: .omp.final.done: 9004 // CHECK17-NEXT: ret void 9005 // 9006 // 9007 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 9008 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9009 // CHECK17-NEXT: entry: 9010 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9011 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 9012 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9013 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 9014 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 9015 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9016 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9017 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 9018 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 9019 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9020 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9021 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 9022 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9023 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 9024 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9025 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 9026 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 9027 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9028 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 9029 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 9030 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 9031 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 9032 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9033 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 9034 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9035 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 9036 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 9037 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9038 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 9039 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 9040 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 9041 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 9042 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 9043 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9044 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 9045 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 9046 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 9047 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 9048 // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 9049 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 9050 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 9051 // CHECK17-NEXT: ret void 9052 // 9053 // 9054 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 9055 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 9056 // CHECK17-NEXT: entry: 9057 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9058 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9059 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9060 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 9061 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9062 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 9063 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 9064 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9065 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9066 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 9067 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 9068 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9069 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9070 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 9071 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9072 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9073 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9074 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9075 // CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1 9076 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9077 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9078 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9079 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 9080 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9081 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 9082 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 9083 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9084 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 9085 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 9086 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 9087 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 9088 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9089 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 9090 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9091 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 9092 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 9093 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9094 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 9095 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 9096 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 9097 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 9098 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9099 // CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 9100 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9101 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9102 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 9103 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9104 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 9105 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 9106 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9107 // CHECK17: omp.dispatch.cond: 9108 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9109 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 9110 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9111 // CHECK17: cond.true: 9112 // CHECK17-NEXT: br label [[COND_END:%.*]] 9113 // CHECK17: cond.false: 9114 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9115 // CHECK17-NEXT: br label [[COND_END]] 9116 // CHECK17: cond.end: 9117 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 9118 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9119 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9120 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 9121 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9122 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9123 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 9124 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9125 // CHECK17: omp.dispatch.body: 9126 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9127 // CHECK17: omp.inner.for.cond: 9128 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 9129 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 9130 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 9131 // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9132 // CHECK17: omp.inner.for.body: 9133 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 9134 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 9135 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 9136 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 9137 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23 9138 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23 9139 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 9140 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23 9141 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 9142 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 9143 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 9144 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 9145 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 9146 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 9147 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 9148 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 9149 // CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 9150 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 9151 // CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 9152 // CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 9153 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 9154 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 9155 // CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23 9156 // CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 9157 // CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23 9158 // CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 9159 // CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 9160 // CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 9161 // CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23 9162 // CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 9163 // CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23 9164 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 9165 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23 9166 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 9167 // CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23 9168 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 9169 // CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23 9170 // CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 9171 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 9172 // CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 9173 // CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23 9174 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9175 // CHECK17: omp.body.continue: 9176 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9177 // CHECK17: omp.inner.for.inc: 9178 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 9179 // CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 9180 // CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 9181 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 9182 // CHECK17: omp.inner.for.end: 9183 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9184 // CHECK17: omp.dispatch.inc: 9185 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9186 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9187 // CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 9188 // CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 9189 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9190 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9191 // CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 9192 // CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 9193 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 9194 // CHECK17: omp.dispatch.end: 9195 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 9196 // CHECK17-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9197 // CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 9198 // CHECK17-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9199 // CHECK17: .omp.final.then: 9200 // CHECK17-NEXT: store i8 96, i8* [[IT]], align 1 9201 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9202 // CHECK17: .omp.final.done: 9203 // CHECK17-NEXT: ret void 9204 // 9205 // 9206 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 9207 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9208 // CHECK17-NEXT: entry: 9209 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9210 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9211 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9212 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9213 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9214 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9215 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 9216 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9217 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9218 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 9219 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9220 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9221 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9222 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 9223 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9224 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9225 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9226 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 9227 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 9228 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 9229 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9230 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 9231 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9232 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 9233 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 9234 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 9235 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 9236 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 9237 // CHECK17-NEXT: ret void 9238 // 9239 // 9240 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 9241 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9242 // CHECK17-NEXT: entry: 9243 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9244 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9245 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9246 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9247 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9248 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9249 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9250 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9251 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9252 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9253 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9254 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9255 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 9256 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9257 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9258 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9259 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 9260 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9261 // CHECK17-NEXT: ret void 9262 // 9263 // 9264 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 9265 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 9266 // CHECK17-NEXT: entry: 9267 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 9268 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9269 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9270 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9271 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 9272 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 9273 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 9274 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 9275 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9276 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9277 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 9278 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 9279 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 9280 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9281 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9282 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 9283 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 9284 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 9285 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 9286 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 9287 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 9288 // CHECK17-NEXT: ret void 9289 // 9290 // 9291 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 9292 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 9293 // CHECK17-NEXT: entry: 9294 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9295 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9296 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 9297 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9298 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9299 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9300 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 9301 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9302 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9303 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9304 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9305 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9306 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9307 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 9308 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9309 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9310 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 9311 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 9312 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9313 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9314 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 9315 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 9316 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 9317 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9318 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9319 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 9320 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9321 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9322 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9323 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9324 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9325 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9326 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9327 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9328 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 9329 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9330 // CHECK17: cond.true: 9331 // CHECK17-NEXT: br label [[COND_END:%.*]] 9332 // CHECK17: cond.false: 9333 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9334 // CHECK17-NEXT: br label [[COND_END]] 9335 // CHECK17: cond.end: 9336 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9337 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9338 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9339 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 9340 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9341 // CHECK17: omp.inner.for.cond: 9342 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 9343 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26 9344 // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 9345 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9346 // CHECK17: omp.inner.for.body: 9347 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 9348 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 9349 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9350 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26 9351 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26 9352 // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 9353 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 9354 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 9355 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group !26 9356 // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 9357 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group !26 9358 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 9359 // CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group !26 9360 // CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 9361 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 9362 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 9363 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 9364 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !26 9365 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9366 // CHECK17: omp.body.continue: 9367 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9368 // CHECK17: omp.inner.for.inc: 9369 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 9370 // CHECK17-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 9371 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 9372 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 9373 // CHECK17: omp.inner.for.end: 9374 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9375 // CHECK17: omp.loop.exit: 9376 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9377 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9378 // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 9379 // CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9380 // CHECK17: .omp.final.then: 9381 // CHECK17-NEXT: store i64 400, i64* [[IT]], align 8 9382 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9383 // CHECK17: .omp.final.done: 9384 // CHECK17-NEXT: ret void 9385 // 9386 // 9387 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 9388 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9389 // CHECK17-NEXT: entry: 9390 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9391 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9392 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9393 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9394 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9395 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9396 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9397 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9398 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9399 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9400 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9401 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9402 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9403 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 9404 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 9405 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 9406 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9407 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 9408 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9409 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 9410 // CHECK17-NEXT: ret void 9411 // 9412 // 9413 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 9414 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9415 // CHECK17-NEXT: entry: 9416 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9417 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9418 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9419 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9420 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9421 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9422 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9423 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9424 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9425 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9426 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9427 // CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8 9428 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9429 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9430 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9431 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9432 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9433 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9434 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9435 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9436 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9437 // CHECK17-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 9438 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9439 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9440 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9441 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 9442 // CHECK17-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9443 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9444 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 9445 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9446 // CHECK17: cond.true: 9447 // CHECK17-NEXT: br label [[COND_END:%.*]] 9448 // CHECK17: cond.false: 9449 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9450 // CHECK17-NEXT: br label [[COND_END]] 9451 // CHECK17: cond.end: 9452 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 9453 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9454 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9455 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 9456 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9457 // CHECK17: omp.inner.for.cond: 9458 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 9459 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !29 9460 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 9461 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9462 // CHECK17: omp.inner.for.body: 9463 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 9464 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 9465 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9466 // CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !29 9467 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !29 9468 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 9469 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !29 9470 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !29 9471 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 9472 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 9473 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 9474 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !29 9475 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 9476 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !29 9477 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 9478 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !29 9479 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9480 // CHECK17: omp.body.continue: 9481 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9482 // CHECK17: omp.inner.for.inc: 9483 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 9484 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 9485 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !29 9486 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 9487 // CHECK17: omp.inner.for.end: 9488 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9489 // CHECK17: omp.loop.exit: 9490 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 9491 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9492 // CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 9493 // CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9494 // CHECK17: .omp.final.then: 9495 // CHECK17-NEXT: store i64 11, i64* [[I]], align 8 9496 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9497 // CHECK17: .omp.final.done: 9498 // CHECK17-NEXT: ret void 9499 // 9500 // 9501 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 9502 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { 9503 // CHECK19-NEXT: entry: 9504 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 9505 // CHECK19-NEXT: ret void 9506 // 9507 // 9508 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 9509 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 9510 // CHECK19-NEXT: entry: 9511 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9512 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9513 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9514 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 9515 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9516 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9517 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9518 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9519 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 9520 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9521 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9522 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9523 // CHECK19-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 9524 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9525 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9526 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9527 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9528 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9529 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9530 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 9531 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9532 // CHECK19: cond.true: 9533 // CHECK19-NEXT: br label [[COND_END:%.*]] 9534 // CHECK19: cond.false: 9535 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9536 // CHECK19-NEXT: br label [[COND_END]] 9537 // CHECK19: cond.end: 9538 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9539 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9540 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9541 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9542 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9543 // CHECK19: omp.inner.for.cond: 9544 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 9545 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 9546 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9547 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9548 // CHECK19: omp.inner.for.body: 9549 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 9550 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 9551 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 9552 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 9553 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9554 // CHECK19: omp.body.continue: 9555 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9556 // CHECK19: omp.inner.for.inc: 9557 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 9558 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9559 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 9560 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 9561 // CHECK19: omp.inner.for.end: 9562 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9563 // CHECK19: omp.loop.exit: 9564 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9565 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9566 // CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 9567 // CHECK19-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9568 // CHECK19: .omp.final.then: 9569 // CHECK19-NEXT: store i32 33, i32* [[I]], align 4 9570 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 9571 // CHECK19: .omp.final.done: 9572 // CHECK19-NEXT: ret void 9573 // 9574 // 9575 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 9576 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 9577 // CHECK19-NEXT: entry: 9578 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9579 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9580 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9581 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9582 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 9583 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9584 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9585 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 9586 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9587 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9588 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9589 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9590 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 9591 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9592 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 9593 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 9594 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 9595 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 9596 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 9597 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 9598 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 9599 // CHECK19-NEXT: ret void 9600 // 9601 // 9602 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 9603 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 9604 // CHECK19-NEXT: entry: 9605 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9606 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9607 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9608 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 9609 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9610 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9611 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 9612 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 9613 // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 9614 // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 9615 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9616 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9617 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9618 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9619 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 9620 // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 9621 // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 9622 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9623 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9624 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9625 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 9626 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9627 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9628 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 9629 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 9630 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9631 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 9632 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 9633 // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 9634 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9635 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9636 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9637 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9638 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9639 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 9640 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 9641 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9642 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9643 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 9644 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9645 // CHECK19: cond.true: 9646 // CHECK19-NEXT: br label [[COND_END:%.*]] 9647 // CHECK19: cond.false: 9648 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9649 // CHECK19-NEXT: br label [[COND_END]] 9650 // CHECK19: cond.end: 9651 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9652 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9653 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9654 // CHECK19-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 9655 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9656 // CHECK19: omp.inner.for.cond: 9657 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 9658 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 9659 // CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9660 // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9661 // CHECK19: omp.inner.for.body: 9662 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 9663 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9664 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9665 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 9666 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18 9667 // CHECK19-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 9668 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 9669 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 9670 // CHECK19-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 9671 // CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 9672 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 9673 // CHECK19-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18 9674 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18 9675 // CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 9676 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 9677 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 9678 // CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 9679 // CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 9680 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 9681 // CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18 9682 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18 9683 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 9684 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 9685 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 9686 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18 9687 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9688 // CHECK19: omp.body.continue: 9689 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9690 // CHECK19: omp.inner.for.inc: 9691 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 9692 // CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 9693 // CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 9694 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 9695 // CHECK19: omp.inner.for.end: 9696 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9697 // CHECK19: omp.loop.exit: 9698 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 9699 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9700 // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 9701 // CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9702 // CHECK19: .omp.final.then: 9703 // CHECK19-NEXT: store i64 400, i64* [[IT]], align 8 9704 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 9705 // CHECK19: .omp.final.done: 9706 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9707 // CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 9708 // CHECK19-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 9709 // CHECK19: .omp.linear.pu: 9710 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 9711 // CHECK19-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 9712 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 9713 // CHECK19-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 9714 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 9715 // CHECK19: .omp.linear.pu.done: 9716 // CHECK19-NEXT: ret void 9717 // 9718 // 9719 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv 9720 // CHECK19-SAME: () #[[ATTR3:[0-9]+]] { 9721 // CHECK19-NEXT: entry: 9722 // CHECK19-NEXT: ret i64 0 9723 // 9724 // 9725 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 9726 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 9727 // CHECK19-NEXT: entry: 9728 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9729 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9730 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9731 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9732 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9733 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9734 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9735 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9736 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9737 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9738 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 9739 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9740 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 9741 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9742 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 9743 // CHECK19-NEXT: ret void 9744 // 9745 // 9746 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 9747 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 9748 // CHECK19-NEXT: entry: 9749 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9750 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9751 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9752 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9753 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9754 // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 9755 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9756 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9757 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9758 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9759 // CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2 9760 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9761 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9762 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9763 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9764 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9765 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9766 // CHECK19-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 9767 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9768 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9769 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9770 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9771 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9772 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9773 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 9774 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9775 // CHECK19: cond.true: 9776 // CHECK19-NEXT: br label [[COND_END:%.*]] 9777 // CHECK19: cond.false: 9778 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9779 // CHECK19-NEXT: br label [[COND_END]] 9780 // CHECK19: cond.end: 9781 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9782 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9783 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9784 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9785 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9786 // CHECK19: omp.inner.for.cond: 9787 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 9788 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 9789 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9790 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9791 // CHECK19: omp.inner.for.body: 9792 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 9793 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 9794 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 9795 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 9796 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21 9797 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21 9798 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 9799 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21 9800 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21 9801 // CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 9802 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 9803 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 9804 // CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21 9805 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9806 // CHECK19: omp.body.continue: 9807 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9808 // CHECK19: omp.inner.for.inc: 9809 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 9810 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 9811 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 9812 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 9813 // CHECK19: omp.inner.for.end: 9814 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9815 // CHECK19: omp.loop.exit: 9816 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9817 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9818 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 9819 // CHECK19-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9820 // CHECK19: .omp.final.then: 9821 // CHECK19-NEXT: store i16 22, i16* [[IT]], align 2 9822 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 9823 // CHECK19: .omp.final.done: 9824 // CHECK19-NEXT: ret void 9825 // 9826 // 9827 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 9828 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9829 // CHECK19-NEXT: entry: 9830 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9831 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9832 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9833 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9834 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9835 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9836 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9837 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9838 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9839 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 9840 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9841 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 9842 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9843 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9844 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9845 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9846 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9847 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9848 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9849 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9850 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9851 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9852 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9853 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9854 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9855 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9856 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9857 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9858 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9859 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9860 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 9861 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 9862 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 9863 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9864 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 9865 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 9866 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 9867 // CHECK19-NEXT: ret void 9868 // 9869 // 9870 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 9871 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 9872 // CHECK19-NEXT: entry: 9873 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9874 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9875 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9876 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9877 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9878 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9879 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9880 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9881 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9882 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9883 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9884 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 9885 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9886 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 9887 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9888 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9889 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9890 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9891 // CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1 9892 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9893 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9894 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9895 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9896 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9897 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9898 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9899 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9900 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9901 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9902 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9903 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9904 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9905 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9906 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9907 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9908 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9909 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9910 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9911 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9912 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9913 // CHECK19-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 9914 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9915 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9916 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 9917 // CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9918 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 9919 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 9920 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9921 // CHECK19: omp.dispatch.cond: 9922 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9923 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 9924 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9925 // CHECK19: cond.true: 9926 // CHECK19-NEXT: br label [[COND_END:%.*]] 9927 // CHECK19: cond.false: 9928 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9929 // CHECK19-NEXT: br label [[COND_END]] 9930 // CHECK19: cond.end: 9931 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 9932 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9933 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9934 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 9935 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9936 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9937 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 9938 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9939 // CHECK19: omp.dispatch.body: 9940 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9941 // CHECK19: omp.inner.for.cond: 9942 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 9943 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 9944 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 9945 // CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9946 // CHECK19: omp.inner.for.body: 9947 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 9948 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 9949 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 9950 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 9951 // CHECK19-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24 9952 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24 9953 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 9954 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24 9955 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 9956 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 9957 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 9958 // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 9959 // CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 9960 // CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 9961 // CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 9962 // CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 9963 // CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 9964 // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 9965 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 9966 // CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 9967 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 9968 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 9969 // CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 9970 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 9971 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 9972 // CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 9973 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 9974 // CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 9975 // CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 9976 // CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 9977 // CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 9978 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 9979 // CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24 9980 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 9981 // CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24 9982 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 9983 // CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24 9984 // CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 9985 // CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 9986 // CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 9987 // CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24 9988 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9989 // CHECK19: omp.body.continue: 9990 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9991 // CHECK19: omp.inner.for.inc: 9992 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 9993 // CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 9994 // CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 9995 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 9996 // CHECK19: omp.inner.for.end: 9997 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9998 // CHECK19: omp.dispatch.inc: 9999 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10000 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10001 // CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 10002 // CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 10003 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10004 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10005 // CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 10006 // CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 10007 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 10008 // CHECK19: omp.dispatch.end: 10009 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 10010 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10011 // CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 10012 // CHECK19-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10013 // CHECK19: .omp.final.then: 10014 // CHECK19-NEXT: store i8 96, i8* [[IT]], align 1 10015 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10016 // CHECK19: .omp.final.done: 10017 // CHECK19-NEXT: ret void 10018 // 10019 // 10020 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 10021 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10022 // CHECK19-NEXT: entry: 10023 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10024 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10025 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10026 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10027 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10028 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10029 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 10030 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10031 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10032 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 10033 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10034 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10035 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 10036 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10037 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10038 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 10039 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 10040 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 10041 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10042 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 10043 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10044 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 10045 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 10046 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 10047 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 10048 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 10049 // CHECK19-NEXT: ret void 10050 // 10051 // 10052 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 10053 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10054 // CHECK19-NEXT: entry: 10055 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10056 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10057 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10058 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10059 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10060 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10061 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10062 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10063 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10064 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10065 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10066 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10067 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 10068 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10069 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10070 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 10071 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10072 // CHECK19-NEXT: ret void 10073 // 10074 // 10075 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 10076 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10077 // CHECK19-NEXT: entry: 10078 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 10079 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10080 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10081 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10082 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 10083 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 10084 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 10085 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 10086 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10087 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10088 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 10089 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 10090 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10091 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10092 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 10093 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 10094 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 10095 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 10096 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 10097 // CHECK19-NEXT: ret void 10098 // 10099 // 10100 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 10101 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10102 // CHECK19-NEXT: entry: 10103 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10104 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10105 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 10106 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10107 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10108 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10109 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 10110 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10111 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10112 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10113 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10114 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10115 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10116 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 10117 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10118 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10119 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 10120 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 10121 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10122 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10123 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 10124 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 10125 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10126 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10127 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 10128 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10129 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 10130 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10131 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10132 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10133 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 10134 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10135 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10136 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 10137 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10138 // CHECK19: cond.true: 10139 // CHECK19-NEXT: br label [[COND_END:%.*]] 10140 // CHECK19: cond.false: 10141 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10142 // CHECK19-NEXT: br label [[COND_END]] 10143 // CHECK19: cond.end: 10144 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 10145 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 10146 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 10147 // CHECK19-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 10148 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10149 // CHECK19: omp.inner.for.cond: 10150 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 10151 // CHECK19-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27 10152 // CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 10153 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10154 // CHECK19: omp.inner.for.body: 10155 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 10156 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 10157 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10158 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27 10159 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27 10160 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 10161 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 10162 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 10163 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4, !llvm.access.group !27 10164 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 10165 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group !27 10166 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 10167 // CHECK19-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group !27 10168 // CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10169 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 10170 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 10171 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 10172 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group !27 10173 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10174 // CHECK19: omp.body.continue: 10175 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10176 // CHECK19: omp.inner.for.inc: 10177 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 10178 // CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 10179 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 10180 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 10181 // CHECK19: omp.inner.for.end: 10182 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10183 // CHECK19: omp.loop.exit: 10184 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 10185 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10186 // CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 10187 // CHECK19-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10188 // CHECK19: .omp.final.then: 10189 // CHECK19-NEXT: store i64 400, i64* [[IT]], align 8 10190 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10191 // CHECK19: .omp.final.done: 10192 // CHECK19-NEXT: ret void 10193 // 10194 // 10195 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 10196 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10197 // CHECK19-NEXT: entry: 10198 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10199 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10200 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10201 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10202 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10203 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10204 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10205 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10206 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10207 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10208 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10209 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 10210 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 10211 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 10212 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10213 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 10214 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10215 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 10216 // CHECK19-NEXT: ret void 10217 // 10218 // 10219 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 10220 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10221 // CHECK19-NEXT: entry: 10222 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10223 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10224 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10225 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10226 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10227 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10228 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10229 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10230 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10231 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10232 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10233 // CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8 10234 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10235 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10236 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10237 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10238 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10239 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10240 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10241 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10242 // CHECK19-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 10243 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10244 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10245 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10246 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10247 // CHECK19-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10248 // CHECK19-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10249 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 10250 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10251 // CHECK19: cond.true: 10252 // CHECK19-NEXT: br label [[COND_END:%.*]] 10253 // CHECK19: cond.false: 10254 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10255 // CHECK19-NEXT: br label [[COND_END]] 10256 // CHECK19: cond.end: 10257 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 10258 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 10259 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 10260 // CHECK19-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 10261 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10262 // CHECK19: omp.inner.for.cond: 10263 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 10264 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !30 10265 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 10266 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10267 // CHECK19: omp.inner.for.body: 10268 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 10269 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 10270 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 10271 // CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !30 10272 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !30 10273 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 10274 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !30 10275 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !30 10276 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 10277 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10278 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10279 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !30 10280 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 10281 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !30 10282 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 10283 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !30 10284 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10285 // CHECK19: omp.body.continue: 10286 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10287 // CHECK19: omp.inner.for.inc: 10288 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 10289 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 10290 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !30 10291 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 10292 // CHECK19: omp.inner.for.end: 10293 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10294 // CHECK19: omp.loop.exit: 10295 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 10296 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10297 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 10298 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10299 // CHECK19: .omp.final.then: 10300 // CHECK19-NEXT: store i64 11, i64* [[I]], align 8 10301 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10302 // CHECK19: .omp.final.done: 10303 // CHECK19-NEXT: ret void 10304 // 10305 // 10306 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 10307 // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { 10308 // CHECK21-NEXT: entry: 10309 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10310 // CHECK21-NEXT: ret void 10311 // 10312 // 10313 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. 10314 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10315 // CHECK21-NEXT: entry: 10316 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10317 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10318 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10319 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 10320 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10321 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10322 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10323 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10324 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 10325 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10326 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10327 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10328 // CHECK21-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 10329 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10330 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10331 // CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10332 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10333 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10334 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10335 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 10336 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10337 // CHECK21: cond.true: 10338 // CHECK21-NEXT: br label [[COND_END:%.*]] 10339 // CHECK21: cond.false: 10340 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10341 // CHECK21-NEXT: br label [[COND_END]] 10342 // CHECK21: cond.end: 10343 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10344 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10345 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10346 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10347 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10348 // CHECK21: omp.inner.for.cond: 10349 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 10350 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !11 10351 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10352 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10353 // CHECK21: omp.inner.for.body: 10354 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 10355 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 10356 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 10357 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !11 10358 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10359 // CHECK21: omp.body.continue: 10360 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10361 // CHECK21: omp.inner.for.inc: 10362 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 10363 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10364 // CHECK21-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !11 10365 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 10366 // CHECK21: omp.inner.for.end: 10367 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10368 // CHECK21: omp.loop.exit: 10369 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10370 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10371 // CHECK21-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 10372 // CHECK21-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10373 // CHECK21: .omp.final.then: 10374 // CHECK21-NEXT: store i32 33, i32* [[I]], align 4 10375 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10376 // CHECK21: .omp.final.done: 10377 // CHECK21-NEXT: ret void 10378 // 10379 // 10380 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 10381 // CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 10382 // CHECK21-NEXT: entry: 10383 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10384 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10385 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10386 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10387 // CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 10388 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10389 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10390 // CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 10391 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10392 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10393 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 10394 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10395 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10396 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10397 // CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 10398 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10399 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 10400 // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 10401 // CHECK21-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 10402 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 10403 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 10404 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10405 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 10406 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 10407 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 10408 // CHECK21-NEXT: ret void 10409 // 10410 // 10411 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 10412 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 10413 // CHECK21-NEXT: entry: 10414 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10415 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10416 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10417 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10418 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10419 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10420 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 10421 // CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 10422 // CHECK21-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 10423 // CHECK21-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 10424 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10425 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10426 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10427 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10428 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 10429 // CHECK21-NEXT: [[LIN4:%.*]] = alloca i32, align 4 10430 // CHECK21-NEXT: [[A5:%.*]] = alloca i32, align 4 10431 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10432 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10433 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10434 // CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 10435 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10436 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10437 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 10438 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10439 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 10440 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 10441 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 10442 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 10443 // CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 10444 // CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 10445 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10446 // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 10447 // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10448 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10449 // CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10450 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 10451 // CHECK21-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 10452 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10453 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10454 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 10455 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10456 // CHECK21: cond.true: 10457 // CHECK21-NEXT: br label [[COND_END:%.*]] 10458 // CHECK21: cond.false: 10459 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10460 // CHECK21-NEXT: br label [[COND_END]] 10461 // CHECK21: cond.end: 10462 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 10463 // CHECK21-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 10464 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 10465 // CHECK21-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 10466 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10467 // CHECK21: omp.inner.for.cond: 10468 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 10469 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !17 10470 // CHECK21-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 10471 // CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10472 // CHECK21: omp.inner.for.body: 10473 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 10474 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 10475 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10476 // CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !17 10477 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !17 10478 // CHECK21-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 10479 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 10480 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 10481 // CHECK21-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 10482 // CHECK21-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 10483 // CHECK21-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 10484 // CHECK21-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group !17 10485 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group !17 10486 // CHECK21-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 10487 // CHECK21-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 10488 // CHECK21-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !17 10489 // CHECK21-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 10490 // CHECK21-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 10491 // CHECK21-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 10492 // CHECK21-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group !17 10493 // CHECK21-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !17 10494 // CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 10495 // CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 10496 // CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 10497 // CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group !17 10498 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10499 // CHECK21: omp.body.continue: 10500 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10501 // CHECK21: omp.inner.for.inc: 10502 // CHECK21-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 10503 // CHECK21-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 10504 // CHECK21-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !17 10505 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 10506 // CHECK21: omp.inner.for.end: 10507 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10508 // CHECK21: omp.loop.exit: 10509 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 10510 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10511 // CHECK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 10512 // CHECK21-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10513 // CHECK21: .omp.final.then: 10514 // CHECK21-NEXT: store i64 400, i64* [[IT]], align 8 10515 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10516 // CHECK21: .omp.final.done: 10517 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10518 // CHECK21-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 10519 // CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10520 // CHECK21: .omp.linear.pu: 10521 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 10522 // CHECK21-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 10523 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 10524 // CHECK21-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 10525 // CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10526 // CHECK21: .omp.linear.pu.done: 10527 // CHECK21-NEXT: ret void 10528 // 10529 // 10530 // CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv 10531 // CHECK21-SAME: () #[[ATTR3:[0-9]+]] { 10532 // CHECK21-NEXT: entry: 10533 // CHECK21-NEXT: ret i64 0 10534 // 10535 // 10536 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 10537 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 10538 // CHECK21-NEXT: entry: 10539 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10540 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10541 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10542 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10543 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10544 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10545 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10546 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10547 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10548 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10549 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 10550 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10551 // CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10552 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10553 // CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 10554 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10555 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 10556 // CHECK21-NEXT: ret void 10557 // 10558 // 10559 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 10560 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 10561 // CHECK21-NEXT: entry: 10562 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10563 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10564 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10565 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10566 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10567 // CHECK21-NEXT: [[TMP:%.*]] = alloca i16, align 2 10568 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10569 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10570 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10571 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10572 // CHECK21-NEXT: [[IT:%.*]] = alloca i16, align 2 10573 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10574 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10575 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10576 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10577 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10578 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10579 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10580 // CHECK21-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 10581 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10582 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10583 // CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10584 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10585 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10586 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10587 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 10588 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10589 // CHECK21: cond.true: 10590 // CHECK21-NEXT: br label [[COND_END:%.*]] 10591 // CHECK21: cond.false: 10592 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10593 // CHECK21-NEXT: br label [[COND_END]] 10594 // CHECK21: cond.end: 10595 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10596 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10597 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10598 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10599 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10600 // CHECK21: omp.inner.for.cond: 10601 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 10602 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !20 10603 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10604 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10605 // CHECK21: omp.inner.for.body: 10606 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 10607 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 10608 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 10609 // CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 10610 // CHECK21-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group !20 10611 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !20 10612 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 10613 // CHECK21-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group !20 10614 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !20 10615 // CHECK21-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 10616 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 10617 // CHECK21-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 10618 // CHECK21-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group !20 10619 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10620 // CHECK21: omp.body.continue: 10621 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10622 // CHECK21: omp.inner.for.inc: 10623 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 10624 // CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 10625 // CHECK21-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !20 10626 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 10627 // CHECK21: omp.inner.for.end: 10628 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10629 // CHECK21: omp.loop.exit: 10630 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10631 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10632 // CHECK21-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 10633 // CHECK21-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10634 // CHECK21: .omp.final.then: 10635 // CHECK21-NEXT: store i16 22, i16* [[IT]], align 2 10636 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10637 // CHECK21: .omp.final.done: 10638 // CHECK21-NEXT: ret void 10639 // 10640 // 10641 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 10642 // CHECK21-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10643 // CHECK21-NEXT: entry: 10644 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10645 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10646 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10647 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10648 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10649 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10650 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10651 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10652 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10653 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10654 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10655 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 10656 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10657 // CHECK21-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10658 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10659 // CHECK21-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10660 // CHECK21-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10661 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10662 // CHECK21-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10663 // CHECK21-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10664 // CHECK21-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10665 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 10666 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10667 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10668 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10669 // CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10670 // CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10671 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10672 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10673 // CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10674 // CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10675 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 10676 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10677 // CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10678 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 10679 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 10680 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 10681 // CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 10682 // CHECK21-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 10683 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 10684 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 10685 // CHECK21-NEXT: ret void 10686 // 10687 // 10688 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 10689 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 10690 // CHECK21-NEXT: entry: 10691 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10692 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10693 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10694 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10695 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10696 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10697 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10698 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10699 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10700 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10701 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10702 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10703 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10704 // CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1 10705 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10706 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10707 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10708 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10709 // CHECK21-NEXT: [[IT:%.*]] = alloca i8, align 1 10710 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10711 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10712 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10713 // CHECK21-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10714 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10715 // CHECK21-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10716 // CHECK21-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10717 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10718 // CHECK21-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10719 // CHECK21-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10720 // CHECK21-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10721 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 10722 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10723 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10724 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10725 // CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10726 // CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10727 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10728 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10729 // CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10730 // CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10731 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 10732 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10733 // CHECK21-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 10734 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10735 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10736 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 10737 // CHECK21-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10738 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 10739 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 10740 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10741 // CHECK21: omp.dispatch.cond: 10742 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10743 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 10744 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10745 // CHECK21: cond.true: 10746 // CHECK21-NEXT: br label [[COND_END:%.*]] 10747 // CHECK21: cond.false: 10748 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10749 // CHECK21-NEXT: br label [[COND_END]] 10750 // CHECK21: cond.end: 10751 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 10752 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10753 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10754 // CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 10755 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10756 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10757 // CHECK21-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 10758 // CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10759 // CHECK21: omp.dispatch.body: 10760 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10761 // CHECK21: omp.inner.for.cond: 10762 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 10763 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !23 10764 // CHECK21-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 10765 // CHECK21-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10766 // CHECK21: omp.inner.for.body: 10767 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 10768 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 10769 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 10770 // CHECK21-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 10771 // CHECK21-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group !23 10772 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !23 10773 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 10774 // CHECK21-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group !23 10775 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 10776 // CHECK21-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !23 10777 // CHECK21-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 10778 // CHECK21-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 10779 // CHECK21-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 10780 // CHECK21-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group !23 10781 // CHECK21-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 10782 // CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 10783 // CHECK21-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 10784 // CHECK21-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 10785 // CHECK21-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 10786 // CHECK21-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group !23 10787 // CHECK21-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 10788 // CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 10789 // CHECK21-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group !23 10790 // CHECK21-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 10791 // CHECK21-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group !23 10792 // CHECK21-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 10793 // CHECK21-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 10794 // CHECK21-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 10795 // CHECK21-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group !23 10796 // CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 10797 // CHECK21-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group !23 10798 // CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10799 // CHECK21-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group !23 10800 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 10801 // CHECK21-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group !23 10802 // CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10803 // CHECK21-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group !23 10804 // CHECK21-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 10805 // CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 10806 // CHECK21-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 10807 // CHECK21-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group !23 10808 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10809 // CHECK21: omp.body.continue: 10810 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10811 // CHECK21: omp.inner.for.inc: 10812 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 10813 // CHECK21-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 10814 // CHECK21-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !23 10815 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 10816 // CHECK21: omp.inner.for.end: 10817 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10818 // CHECK21: omp.dispatch.inc: 10819 // CHECK21-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10820 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10821 // CHECK21-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 10822 // CHECK21-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 10823 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10824 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10825 // CHECK21-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 10826 // CHECK21-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 10827 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]] 10828 // CHECK21: omp.dispatch.end: 10829 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 10830 // CHECK21-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10831 // CHECK21-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 10832 // CHECK21-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10833 // CHECK21: .omp.final.then: 10834 // CHECK21-NEXT: store i8 96, i8* [[IT]], align 1 10835 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10836 // CHECK21: .omp.final.done: 10837 // CHECK21-NEXT: ret void 10838 // 10839 // 10840 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 10841 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10842 // CHECK21-NEXT: entry: 10843 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10844 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10845 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10846 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10847 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10848 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10849 // CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 10850 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10851 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10852 // CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10853 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10854 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10855 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10856 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10857 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10858 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10859 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10860 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 10861 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10862 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10863 // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10864 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 10865 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10866 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 10867 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 10868 // CHECK21-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 10869 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 10870 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 10871 // CHECK21-NEXT: ret void 10872 // 10873 // 10874 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 10875 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10876 // CHECK21-NEXT: entry: 10877 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10878 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10879 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10880 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10881 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10882 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10883 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10884 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 10885 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10886 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10887 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10888 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10889 // CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10890 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10891 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10892 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10893 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10894 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10895 // CHECK21-NEXT: ret void 10896 // 10897 // 10898 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 10899 // CHECK21-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10900 // CHECK21-NEXT: entry: 10901 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10902 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10903 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10904 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10905 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10906 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10907 // CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10908 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 10909 // CHECK21-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 10910 // CHECK21-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 10911 // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 10912 // CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10913 // CHECK21-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10914 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10915 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10916 // CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10917 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 10918 // CHECK21-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10919 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10920 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10921 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10922 // CHECK21-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10923 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 10924 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4 10925 // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10926 // CHECK21-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4 10927 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 10928 // CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 10929 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 10930 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 10931 // CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 10932 // CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 10933 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 10934 // CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1 10935 // CHECK21-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 10936 // CHECK21-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10937 // CHECK21: omp_if.then: 10938 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) 10939 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 10940 // CHECK21: omp_if.else: 10941 // CHECK21-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 10942 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 10943 // CHECK21-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 10944 // CHECK21-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] 10945 // CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 10946 // CHECK21-NEXT: br label [[OMP_IF_END]] 10947 // CHECK21: omp_if.end: 10948 // CHECK21-NEXT: ret void 10949 // 10950 // 10951 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 10952 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 10953 // CHECK21-NEXT: entry: 10954 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10955 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10956 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10957 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10958 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10959 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10960 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10961 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 10962 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10963 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 10964 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10965 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10966 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10967 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10968 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 10969 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10970 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10971 // CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10972 // CHECK21-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10973 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10974 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10975 // CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10976 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 10977 // CHECK21-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10978 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10979 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10980 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10981 // CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10982 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 10983 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10984 // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 10985 // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10986 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10987 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1 10988 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 10989 // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 10990 // CHECK21: omp_if.then: 10991 // CHECK21-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10992 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 10993 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10994 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10995 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 10996 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10997 // CHECK21: cond.true: 10998 // CHECK21-NEXT: br label [[COND_END:%.*]] 10999 // CHECK21: cond.false: 11000 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11001 // CHECK21-NEXT: br label [[COND_END]] 11002 // CHECK21: cond.end: 11003 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 11004 // CHECK21-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11005 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11006 // CHECK21-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 11007 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11008 // CHECK21: omp.inner.for.cond: 11009 // CHECK21-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 11010 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !26 11011 // CHECK21-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 11012 // CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11013 // CHECK21: omp.inner.for.body: 11014 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 11015 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 11016 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11017 // CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !26 11018 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !26 11019 // CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double 11020 // CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00 11021 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11022 // CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group !26 11023 // CHECK21-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11024 // CHECK21-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26 11025 // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 11026 // CHECK21-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group !26 11027 // CHECK21-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 11028 // CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 11029 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]] 11030 // CHECK21-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 11031 // CHECK21-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group !26 11032 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11033 // CHECK21: omp.body.continue: 11034 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11035 // CHECK21: omp.inner.for.inc: 11036 // CHECK21-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 11037 // CHECK21-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1 11038 // CHECK21-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !26 11039 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 11040 // CHECK21: omp.inner.for.end: 11041 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 11042 // CHECK21: omp_if.else: 11043 // CHECK21-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11044 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 11045 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11046 // CHECK21-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11047 // CHECK21-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3 11048 // CHECK21-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] 11049 // CHECK21: cond.true11: 11050 // CHECK21-NEXT: br label [[COND_END13:%.*]] 11051 // CHECK21: cond.false12: 11052 // CHECK21-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11053 // CHECK21-NEXT: br label [[COND_END13]] 11054 // CHECK21: cond.end13: 11055 // CHECK21-NEXT: [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ] 11056 // CHECK21-NEXT: store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8 11057 // CHECK21-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11058 // CHECK21-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 11059 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND15:%.*]] 11060 // CHECK21: omp.inner.for.cond15: 11061 // CHECK21-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11062 // CHECK21-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11063 // CHECK21-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 11064 // CHECK21-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]] 11065 // CHECK21: omp.inner.for.body17: 11066 // CHECK21-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11067 // CHECK21-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400 11068 // CHECK21-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]] 11069 // CHECK21-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8 11070 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4 11071 // CHECK21-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double 11072 // CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00 11073 // CHECK21-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11074 // CHECK21-NEXT: store double [[ADD21]], double* [[A22]], align 8 11075 // CHECK21-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11076 // CHECK21-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8 11077 // CHECK21-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00 11078 // CHECK21-NEXT: store double [[INC24]], double* [[A23]], align 8 11079 // CHECK21-NEXT: [[CONV25:%.*]] = fptosi double [[INC24]] to i16 11080 // CHECK21-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 11081 // CHECK21-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]] 11082 // CHECK21-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1 11083 // CHECK21-NEXT: store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2 11084 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] 11085 // CHECK21: omp.body.continue28: 11086 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC29:%.*]] 11087 // CHECK21: omp.inner.for.inc29: 11088 // CHECK21-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11089 // CHECK21-NEXT: [[ADD30:%.*]] = add i64 [[TMP28]], 1 11090 // CHECK21-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 11091 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP30:![0-9]+]] 11092 // CHECK21: omp.inner.for.end31: 11093 // CHECK21-NEXT: br label [[OMP_IF_END]] 11094 // CHECK21: omp_if.end: 11095 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11096 // CHECK21: omp.loop.exit: 11097 // CHECK21-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11098 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 11099 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 11100 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11101 // CHECK21-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 11102 // CHECK21-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11103 // CHECK21: .omp.final.then: 11104 // CHECK21-NEXT: store i64 400, i64* [[IT]], align 8 11105 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11106 // CHECK21: .omp.final.done: 11107 // CHECK21-NEXT: ret void 11108 // 11109 // 11110 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 11111 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11112 // CHECK21-NEXT: entry: 11113 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11114 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11115 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11116 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11117 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11118 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11119 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11120 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11121 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11122 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11123 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11124 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11125 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11126 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 11127 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11128 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 11129 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11130 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 11131 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11132 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 11133 // CHECK21-NEXT: ret void 11134 // 11135 // 11136 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 11137 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11138 // CHECK21-NEXT: entry: 11139 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11140 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11141 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11142 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11143 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11144 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11145 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 11146 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11147 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11148 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11149 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11150 // CHECK21-NEXT: [[I:%.*]] = alloca i64, align 8 11151 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11152 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11153 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11154 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11155 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11156 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11157 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11158 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11159 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11160 // CHECK21-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 11161 // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11162 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11163 // CHECK21-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11164 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 11165 // CHECK21-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11166 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11167 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 11168 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11169 // CHECK21: cond.true: 11170 // CHECK21-NEXT: br label [[COND_END:%.*]] 11171 // CHECK21: cond.false: 11172 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11173 // CHECK21-NEXT: br label [[COND_END]] 11174 // CHECK21: cond.end: 11175 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 11176 // CHECK21-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11177 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11178 // CHECK21-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 11179 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11180 // CHECK21: omp.inner.for.cond: 11181 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 11182 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !32 11183 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 11184 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11185 // CHECK21: omp.inner.for.body: 11186 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 11187 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 11188 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 11189 // CHECK21-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !32 11190 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group !32 11191 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 11192 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group !32 11193 // CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group !32 11194 // CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 11195 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 11196 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 11197 // CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group !32 11198 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 11199 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !32 11200 // CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 11201 // CHECK21-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !32 11202 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11203 // CHECK21: omp.body.continue: 11204 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11205 // CHECK21: omp.inner.for.inc: 11206 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 11207 // CHECK21-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 11208 // CHECK21-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !32 11209 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 11210 // CHECK21: omp.inner.for.end: 11211 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11212 // CHECK21: omp.loop.exit: 11213 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 11214 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11215 // CHECK21-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 11216 // CHECK21-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11217 // CHECK21: .omp.final.then: 11218 // CHECK21-NEXT: store i64 11, i64* [[I]], align 8 11219 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11220 // CHECK21: .omp.final.done: 11221 // CHECK21-NEXT: ret void 11222 // 11223 // 11224 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 11225 // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { 11226 // CHECK23-NEXT: entry: 11227 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 11228 // CHECK23-NEXT: ret void 11229 // 11230 // 11231 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. 11232 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 11233 // CHECK23-NEXT: entry: 11234 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11235 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11236 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11237 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 11238 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11239 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11240 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11241 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11242 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 11243 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11244 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11245 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11246 // CHECK23-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 11247 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11248 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11249 // CHECK23-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11250 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 11251 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11252 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11253 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 11254 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11255 // CHECK23: cond.true: 11256 // CHECK23-NEXT: br label [[COND_END:%.*]] 11257 // CHECK23: cond.false: 11258 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11259 // CHECK23-NEXT: br label [[COND_END]] 11260 // CHECK23: cond.end: 11261 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11262 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11263 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11264 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11265 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11266 // CHECK23: omp.inner.for.cond: 11267 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 11268 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !12 11269 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11270 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11271 // CHECK23: omp.inner.for.body: 11272 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 11273 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 11274 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 11275 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group !12 11276 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11277 // CHECK23: omp.body.continue: 11278 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11279 // CHECK23: omp.inner.for.inc: 11280 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 11281 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 11282 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !12 11283 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 11284 // CHECK23: omp.inner.for.end: 11285 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11286 // CHECK23: omp.loop.exit: 11287 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11288 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11289 // CHECK23-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 11290 // CHECK23-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11291 // CHECK23: .omp.final.then: 11292 // CHECK23-NEXT: store i32 33, i32* [[I]], align 4 11293 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11294 // CHECK23: .omp.final.done: 11295 // CHECK23-NEXT: ret void 11296 // 11297 // 11298 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 11299 // CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 11300 // CHECK23-NEXT: entry: 11301 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11302 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11303 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11304 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11305 // CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 11306 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11307 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11308 // CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 11309 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11310 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11311 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 11312 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11313 // CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 11314 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11315 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 11316 // CHECK23-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 11317 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 11318 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 11319 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 11320 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 11321 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 11322 // CHECK23-NEXT: ret void 11323 // 11324 // 11325 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 11326 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 11327 // CHECK23-NEXT: entry: 11328 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11329 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11330 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11331 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11332 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11333 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11334 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 11335 // CHECK23-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 11336 // CHECK23-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 11337 // CHECK23-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 11338 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11339 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11340 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11341 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11342 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 11343 // CHECK23-NEXT: [[LIN2:%.*]] = alloca i32, align 4 11344 // CHECK23-NEXT: [[A3:%.*]] = alloca i32, align 4 11345 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11346 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11347 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11348 // CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 11349 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11350 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11351 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 11352 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 11353 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11354 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 11355 // CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 11356 // CHECK23-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 11357 // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11358 // CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 11359 // CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11360 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11361 // CHECK23-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11362 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 11363 // CHECK23-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 11364 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11365 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11366 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 11367 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11368 // CHECK23: cond.true: 11369 // CHECK23-NEXT: br label [[COND_END:%.*]] 11370 // CHECK23: cond.false: 11371 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11372 // CHECK23-NEXT: br label [[COND_END]] 11373 // CHECK23: cond.end: 11374 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 11375 // CHECK23-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11376 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11377 // CHECK23-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 11378 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11379 // CHECK23: omp.inner.for.cond: 11380 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 11381 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !18 11382 // CHECK23-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 11383 // CHECK23-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11384 // CHECK23: omp.inner.for.body: 11385 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 11386 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 11387 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11388 // CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !18 11389 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group !18 11390 // CHECK23-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 11391 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 11392 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 11393 // CHECK23-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 11394 // CHECK23-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 11395 // CHECK23-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 11396 // CHECK23-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group !18 11397 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group !18 11398 // CHECK23-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 11399 // CHECK23-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 11400 // CHECK23-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group !18 11401 // CHECK23-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 11402 // CHECK23-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 11403 // CHECK23-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 11404 // CHECK23-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group !18 11405 // CHECK23-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !18 11406 // CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 11407 // CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 11408 // CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 11409 // CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group !18 11410 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11411 // CHECK23: omp.body.continue: 11412 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11413 // CHECK23: omp.inner.for.inc: 11414 // CHECK23-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 11415 // CHECK23-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 11416 // CHECK23-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !18 11417 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 11418 // CHECK23: omp.inner.for.end: 11419 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11420 // CHECK23: omp.loop.exit: 11421 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 11422 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11423 // CHECK23-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 11424 // CHECK23-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11425 // CHECK23: .omp.final.then: 11426 // CHECK23-NEXT: store i64 400, i64* [[IT]], align 8 11427 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11428 // CHECK23: .omp.final.done: 11429 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11430 // CHECK23-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 11431 // CHECK23-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 11432 // CHECK23: .omp.linear.pu: 11433 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 11434 // CHECK23-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 11435 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 11436 // CHECK23-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 11437 // CHECK23-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 11438 // CHECK23: .omp.linear.pu.done: 11439 // CHECK23-NEXT: ret void 11440 // 11441 // 11442 // CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv 11443 // CHECK23-SAME: () #[[ATTR3:[0-9]+]] { 11444 // CHECK23-NEXT: entry: 11445 // CHECK23-NEXT: ret i64 0 11446 // 11447 // 11448 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 11449 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 11450 // CHECK23-NEXT: entry: 11451 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11452 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11453 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11454 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11455 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11456 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11457 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11458 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11459 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 11460 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 11461 // CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11462 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11463 // CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 11464 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11465 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 11466 // CHECK23-NEXT: ret void 11467 // 11468 // 11469 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 11470 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 11471 // CHECK23-NEXT: entry: 11472 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11473 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11474 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11475 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11476 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11477 // CHECK23-NEXT: [[TMP:%.*]] = alloca i16, align 2 11478 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11479 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11480 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11481 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11482 // CHECK23-NEXT: [[IT:%.*]] = alloca i16, align 2 11483 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11484 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11485 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11486 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11487 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11488 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11489 // CHECK23-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 11490 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11491 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11492 // CHECK23-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11493 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 11494 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11495 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11496 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 11497 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11498 // CHECK23: cond.true: 11499 // CHECK23-NEXT: br label [[COND_END:%.*]] 11500 // CHECK23: cond.false: 11501 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11502 // CHECK23-NEXT: br label [[COND_END]] 11503 // CHECK23: cond.end: 11504 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11505 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11506 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11507 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11508 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11509 // CHECK23: omp.inner.for.cond: 11510 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 11511 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !21 11512 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11513 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11514 // CHECK23: omp.inner.for.body: 11515 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 11516 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 11517 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 11518 // CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 11519 // CHECK23-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group !21 11520 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !21 11521 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 11522 // CHECK23-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group !21 11523 // CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !21 11524 // CHECK23-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 11525 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 11526 // CHECK23-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 11527 // CHECK23-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group !21 11528 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11529 // CHECK23: omp.body.continue: 11530 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11531 // CHECK23: omp.inner.for.inc: 11532 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 11533 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 11534 // CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !21 11535 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 11536 // CHECK23: omp.inner.for.end: 11537 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11538 // CHECK23: omp.loop.exit: 11539 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11540 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11541 // CHECK23-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 11542 // CHECK23-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11543 // CHECK23: .omp.final.then: 11544 // CHECK23-NEXT: store i16 22, i16* [[IT]], align 2 11545 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11546 // CHECK23: .omp.final.done: 11547 // CHECK23-NEXT: ret void 11548 // 11549 // 11550 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 11551 // CHECK23-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11552 // CHECK23-NEXT: entry: 11553 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11554 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11555 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11556 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11557 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11558 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11559 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11560 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11561 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11562 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11563 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11564 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 11565 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11566 // CHECK23-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11567 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11568 // CHECK23-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11569 // CHECK23-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11570 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11571 // CHECK23-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11572 // CHECK23-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11573 // CHECK23-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11574 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 11575 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11576 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11577 // CHECK23-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11578 // CHECK23-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11579 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11580 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11581 // CHECK23-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11582 // CHECK23-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11583 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 11584 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 11585 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 11586 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 11587 // CHECK23-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 11588 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 11589 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 11590 // CHECK23-NEXT: ret void 11591 // 11592 // 11593 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 11594 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 11595 // CHECK23-NEXT: entry: 11596 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11597 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11598 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11599 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11600 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11601 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11602 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11603 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11604 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11605 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11606 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11607 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11608 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11609 // CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1 11610 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11611 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11612 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11613 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11614 // CHECK23-NEXT: [[IT:%.*]] = alloca i8, align 1 11615 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11616 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11617 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11618 // CHECK23-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11619 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11620 // CHECK23-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11621 // CHECK23-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11622 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11623 // CHECK23-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11624 // CHECK23-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11625 // CHECK23-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11626 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 11627 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11628 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11629 // CHECK23-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11630 // CHECK23-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11631 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11632 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11633 // CHECK23-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11634 // CHECK23-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11635 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11636 // CHECK23-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 11637 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11638 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11639 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 11640 // CHECK23-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11641 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 11642 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 11643 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 11644 // CHECK23: omp.dispatch.cond: 11645 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11646 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 11647 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11648 // CHECK23: cond.true: 11649 // CHECK23-NEXT: br label [[COND_END:%.*]] 11650 // CHECK23: cond.false: 11651 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11652 // CHECK23-NEXT: br label [[COND_END]] 11653 // CHECK23: cond.end: 11654 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 11655 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11656 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11657 // CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 11658 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11659 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11660 // CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 11661 // CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 11662 // CHECK23: omp.dispatch.body: 11663 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11664 // CHECK23: omp.inner.for.cond: 11665 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 11666 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !24 11667 // CHECK23-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 11668 // CHECK23-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11669 // CHECK23: omp.inner.for.body: 11670 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 11671 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 11672 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 11673 // CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 11674 // CHECK23-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group !24 11675 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !24 11676 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 11677 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group !24 11678 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 11679 // CHECK23-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !24 11680 // CHECK23-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 11681 // CHECK23-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 11682 // CHECK23-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 11683 // CHECK23-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group !24 11684 // CHECK23-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 11685 // CHECK23-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 11686 // CHECK23-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 11687 // CHECK23-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 11688 // CHECK23-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 11689 // CHECK23-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group !24 11690 // CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 11691 // CHECK23-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 11692 // CHECK23-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 11693 // CHECK23-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 11694 // CHECK23-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group !24 11695 // CHECK23-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 11696 // CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 11697 // CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 11698 // CHECK23-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 11699 // CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 11700 // CHECK23-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group !24 11701 // CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 11702 // CHECK23-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group !24 11703 // CHECK23-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 11704 // CHECK23-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group !24 11705 // CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 11706 // CHECK23-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group !24 11707 // CHECK23-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 11708 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 11709 // CHECK23-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 11710 // CHECK23-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group !24 11711 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11712 // CHECK23: omp.body.continue: 11713 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11714 // CHECK23: omp.inner.for.inc: 11715 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 11716 // CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 11717 // CHECK23-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !24 11718 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 11719 // CHECK23: omp.inner.for.end: 11720 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 11721 // CHECK23: omp.dispatch.inc: 11722 // CHECK23-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11723 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 11724 // CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 11725 // CHECK23-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 11726 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11727 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 11728 // CHECK23-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 11729 // CHECK23-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 11730 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]] 11731 // CHECK23: omp.dispatch.end: 11732 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 11733 // CHECK23-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11734 // CHECK23-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 11735 // CHECK23-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11736 // CHECK23: .omp.final.then: 11737 // CHECK23-NEXT: store i8 96, i8* [[IT]], align 1 11738 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11739 // CHECK23: .omp.final.done: 11740 // CHECK23-NEXT: ret void 11741 // 11742 // 11743 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 11744 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11745 // CHECK23-NEXT: entry: 11746 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11747 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11748 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11749 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11750 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11751 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11752 // CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 11753 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11754 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11755 // CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11756 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11757 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11758 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11759 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11760 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11761 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11762 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11763 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11764 // CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11765 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 11766 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11767 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 11768 // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 11769 // CHECK23-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 11770 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 11771 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 11772 // CHECK23-NEXT: ret void 11773 // 11774 // 11775 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 11776 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11777 // CHECK23-NEXT: entry: 11778 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11779 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11780 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11781 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11782 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11783 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11784 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11785 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 11786 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11787 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11788 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11789 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11790 // CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11791 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11792 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11793 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11794 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11795 // CHECK23-NEXT: ret void 11796 // 11797 // 11798 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 11799 // CHECK23-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11800 // CHECK23-NEXT: entry: 11801 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11802 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11803 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11804 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11805 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11806 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11807 // CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 11808 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 11809 // CHECK23-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 11810 // CHECK23-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 11811 // CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 11812 // CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11813 // CHECK23-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11814 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11815 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11816 // CHECK23-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11817 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 11818 // CHECK23-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11819 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11820 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11821 // CHECK23-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11822 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 11823 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 11824 // CHECK23-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 11825 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 11826 // CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1 11827 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 11828 // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* 11829 // CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 11830 // CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 11831 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 11832 // CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1 11833 // CHECK23-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 11834 // CHECK23-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11835 // CHECK23: omp_if.then: 11836 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) 11837 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 11838 // CHECK23: omp_if.else: 11839 // CHECK23-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 11840 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 11841 // CHECK23-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 11842 // CHECK23-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]] 11843 // CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 11844 // CHECK23-NEXT: br label [[OMP_IF_END]] 11845 // CHECK23: omp_if.end: 11846 // CHECK23-NEXT: ret void 11847 // 11848 // 11849 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 11850 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 11851 // CHECK23-NEXT: entry: 11852 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11853 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11854 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11855 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11856 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11857 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11858 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11859 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 11860 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11861 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 11862 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11863 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11864 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11865 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11866 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 11867 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11868 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11869 // CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11870 // CHECK23-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11871 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11872 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11873 // CHECK23-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11874 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 11875 // CHECK23-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11876 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11877 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11878 // CHECK23-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11879 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 11880 // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11881 // CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 11882 // CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11883 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11884 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 11885 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 11886 // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11887 // CHECK23: omp_if.then: 11888 // CHECK23-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11889 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 11890 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11891 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11892 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 11893 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11894 // CHECK23: cond.true: 11895 // CHECK23-NEXT: br label [[COND_END:%.*]] 11896 // CHECK23: cond.false: 11897 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11898 // CHECK23-NEXT: br label [[COND_END]] 11899 // CHECK23: cond.end: 11900 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 11901 // CHECK23-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11902 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11903 // CHECK23-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 11904 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11905 // CHECK23: omp.inner.for.cond: 11906 // CHECK23-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 11907 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !27 11908 // CHECK23-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 11909 // CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11910 // CHECK23: omp.inner.for.body: 11911 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 11912 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 11913 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11914 // CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group !27 11915 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group !27 11916 // CHECK23-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double 11917 // CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 11918 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11919 // CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4, !nontemporal !28, !llvm.access.group !27 11920 // CHECK23-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11921 // CHECK23-NEXT: [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27 11922 // CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 11923 // CHECK23-NEXT: store double [[INC]], double* [[A5]], align 4, !nontemporal !28, !llvm.access.group !27 11924 // CHECK23-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 11925 // CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 11926 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]] 11927 // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 11928 // CHECK23-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group !27 11929 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11930 // CHECK23: omp.body.continue: 11931 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11932 // CHECK23: omp.inner.for.inc: 11933 // CHECK23-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 11934 // CHECK23-NEXT: [[ADD8:%.*]] = add i64 [[TMP16]], 1 11935 // CHECK23-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !27 11936 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 11937 // CHECK23: omp.inner.for.end: 11938 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 11939 // CHECK23: omp_if.else: 11940 // CHECK23-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11941 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 11942 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11943 // CHECK23-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11944 // CHECK23-NEXT: [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3 11945 // CHECK23-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] 11946 // CHECK23: cond.true10: 11947 // CHECK23-NEXT: br label [[COND_END12:%.*]] 11948 // CHECK23: cond.false11: 11949 // CHECK23-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11950 // CHECK23-NEXT: br label [[COND_END12]] 11951 // CHECK23: cond.end12: 11952 // CHECK23-NEXT: [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ] 11953 // CHECK23-NEXT: store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8 11954 // CHECK23-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11955 // CHECK23-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 11956 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND14:%.*]] 11957 // CHECK23: omp.inner.for.cond14: 11958 // CHECK23-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11959 // CHECK23-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11960 // CHECK23-NEXT: [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 11961 // CHECK23-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]] 11962 // CHECK23: omp.inner.for.body16: 11963 // CHECK23-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11964 // CHECK23-NEXT: [[MUL17:%.*]] = mul i64 [[TMP24]], 400 11965 // CHECK23-NEXT: [[SUB18:%.*]] = sub i64 2000, [[MUL17]] 11966 // CHECK23-NEXT: store i64 [[SUB18]], i64* [[IT]], align 8 11967 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4 11968 // CHECK23-NEXT: [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double 11969 // CHECK23-NEXT: [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00 11970 // CHECK23-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11971 // CHECK23-NEXT: store double [[ADD20]], double* [[A21]], align 4 11972 // CHECK23-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11973 // CHECK23-NEXT: [[TMP26:%.*]] = load double, double* [[A22]], align 4 11974 // CHECK23-NEXT: [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00 11975 // CHECK23-NEXT: store double [[INC23]], double* [[A22]], align 4 11976 // CHECK23-NEXT: [[CONV24:%.*]] = fptosi double [[INC23]] to i16 11977 // CHECK23-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 11978 // CHECK23-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]] 11979 // CHECK23-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1 11980 // CHECK23-NEXT: store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2 11981 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] 11982 // CHECK23: omp.body.continue27: 11983 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] 11984 // CHECK23: omp.inner.for.inc28: 11985 // CHECK23-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11986 // CHECK23-NEXT: [[ADD29:%.*]] = add i64 [[TMP28]], 1 11987 // CHECK23-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8 11988 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP31:![0-9]+]] 11989 // CHECK23: omp.inner.for.end30: 11990 // CHECK23-NEXT: br label [[OMP_IF_END]] 11991 // CHECK23: omp_if.end: 11992 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11993 // CHECK23: omp.loop.exit: 11994 // CHECK23-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11995 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 11996 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 11997 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11998 // CHECK23-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 11999 // CHECK23-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12000 // CHECK23: .omp.final.then: 12001 // CHECK23-NEXT: store i64 400, i64* [[IT]], align 8 12002 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12003 // CHECK23: .omp.final.done: 12004 // CHECK23-NEXT: ret void 12005 // 12006 // 12007 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 12008 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12009 // CHECK23-NEXT: entry: 12010 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12011 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12012 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12013 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12014 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12015 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12016 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12017 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12018 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12019 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12020 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 12021 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 12022 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 12023 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 12024 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12025 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 12026 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12027 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 12028 // CHECK23-NEXT: ret void 12029 // 12030 // 12031 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 12032 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 12033 // CHECK23-NEXT: entry: 12034 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12035 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12036 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12037 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12038 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12039 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12040 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 12041 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12042 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12043 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12044 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12045 // CHECK23-NEXT: [[I:%.*]] = alloca i64, align 8 12046 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12047 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12048 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12049 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12050 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12051 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12052 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12053 // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 12054 // CHECK23-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 12055 // CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 12056 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12057 // CHECK23-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12058 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 12059 // CHECK23-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 12060 // CHECK23-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12061 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 12062 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12063 // CHECK23: cond.true: 12064 // CHECK23-NEXT: br label [[COND_END:%.*]] 12065 // CHECK23: cond.false: 12066 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12067 // CHECK23-NEXT: br label [[COND_END]] 12068 // CHECK23: cond.end: 12069 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 12070 // CHECK23-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 12071 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 12072 // CHECK23-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 12073 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12074 // CHECK23: omp.inner.for.cond: 12075 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 12076 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !33 12077 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 12078 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12079 // CHECK23: omp.inner.for.body: 12080 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 12081 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 12082 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 12083 // CHECK23-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group !33 12084 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group !33 12085 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 12086 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group !33 12087 // CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group !33 12088 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 12089 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 12090 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 12091 // CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group !33 12092 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 12093 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 12094 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 12095 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group !33 12096 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12097 // CHECK23: omp.body.continue: 12098 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12099 // CHECK23: omp.inner.for.inc: 12100 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 12101 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 12102 // CHECK23-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !33 12103 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 12104 // CHECK23: omp.inner.for.end: 12105 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12106 // CHECK23: omp.loop.exit: 12107 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 12108 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12109 // CHECK23-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 12110 // CHECK23-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12111 // CHECK23: .omp.final.then: 12112 // CHECK23-NEXT: store i64 11, i64* [[I]], align 8 12113 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12114 // CHECK23: .omp.final.done: 12115 // CHECK23-NEXT: ret void 12116 // 12117