1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK3 9 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 10 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 13 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK7 15 16 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 17 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 18 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 23 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 26 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 27 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 28 29 // Test target codegen - host bc file has to be created first. 30 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 32 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK17 34 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 35 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 36 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 37 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK19 38 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 39 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 40 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK21 42 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 43 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 44 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK23 46 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 48 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 50 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK9 51 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 53 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK11 55 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 57 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK13 59 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 60 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 61 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 62 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=50 -DOMP5 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck -allow-deprecated-dag-overlap %s --check-prefix=CHECK15 63 64 // expected-no-diagnostics 65 #ifndef HEADER 66 #define HEADER 67 68 69 70 // We have 8 target regions, but only 7 that actually will generate offloading 71 // code, only 6 will have mapped arguments, and only 4 have all-constant map 72 // sizes. 73 74 75 76 // Check target registration is registered as a Ctor. 77 78 79 template<typename tx, typename ty> 80 struct TT{ 81 tx X; 82 ty Y; 83 }; 84 85 long long get_val() { return 0; } 86 87 int foo(int n) { 88 int a = 0; 89 short aa = 0; 90 float b[10]; 91 float bn[n]; 92 double c[5][10]; 93 double cn[5][n]; 94 TT<long long, char> d; 95 96 #pragma omp target parallel for simd nowait 97 for (int i = 3; i < 32; i += 5) { 98 } 99 100 long long k = get_val(); 101 #pragma omp target parallel for simd if(target: 0) linear(k : 3) schedule(dynamic) 102 for (int i = 10; i > 1; i--) { 103 a += 1; 104 } 105 106 107 int lin = 12; 108 #pragma omp target parallel for simd if(target: 1) linear(lin, a : get_val()) 109 for (unsigned long long it = 2000; it >= 600; it-=400) { 110 aa += 1; 111 } 112 113 114 115 116 #pragma omp target parallel for simd if(target: n>10) 117 for (short it = 6; it <= 20; it-=-4) { 118 a += 1; 119 aa += 1; 120 } 121 122 // We capture 3 VLA sizes in this target region 123 124 125 126 127 128 // The names below are not necessarily consistent with the names used for the 129 // addresses above as some are repeated. 130 131 132 133 134 135 136 137 138 139 140 #pragma omp target parallel for simd if(target: n>20) schedule(static, a) 141 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 142 a += 1; 143 b[2] += 1.0; 144 bn[3] += 1.0; 145 c[1][2] += 1.0; 146 cn[1][3] += 1.0; 147 d.X += 1; 148 d.Y += 1; 149 } 150 151 return a; 152 } 153 154 // Check that the offloading functions are emitted and that the arguments are 155 // correct and loaded correctly for the target regions in foo(). 156 157 158 159 160 // Create stack storage and store argument in there. 161 162 // Create stack storage and store argument in there. 163 164 // Create stack storage and store argument in there. 165 166 // Create local storage for each capture. 167 168 169 170 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 171 172 template<typename tx> 173 tx ftemplate(int n) { 174 tx a = 0; 175 short aa = 0; 176 tx b[10]; 177 178 #pragma omp target parallel for simd if(target: n>40) 179 for (long long i = -10; i < 10; i += 3) { 180 a += 1; 181 aa += 1; 182 b[2] += 1; 183 } 184 185 return a; 186 } 187 188 static 189 int fstatic(int n) { 190 int a = 0; 191 short aa = 0; 192 char aaa = 0; 193 int b[10]; 194 195 #pragma omp target parallel for simd if(target: n>50) 196 for (unsigned i=100; i<10; i+=10) { 197 a += 1; 198 aa += 1; 199 aaa += 1; 200 b[2] += 1; 201 } 202 203 return a; 204 } 205 206 struct S1 { 207 double a; 208 209 int r1(int n){ 210 int b = n+1; 211 short int c[2][n]; 212 213 #ifdef OMP5 214 #pragma omp target parallel for simd if(n>60) nontemporal(a) 215 #else 216 #pragma omp target parallel for simd if(target: n>60) 217 #endif // OMP5 218 for (unsigned long long it = 2000; it >= 600; it -= 400) { 219 this->a = (double)b + 1.5; 220 c[1][1] = ++a; 221 } 222 223 return c[1][1] + (int)b; 224 } 225 }; 226 227 int bar(int n){ 228 int a = 0; 229 230 a += foo(n); 231 232 S1 S; 233 a += S.r1(n); 234 235 a += fstatic(n); 236 237 a += ftemplate<int>(n); 238 239 return a; 240 } 241 242 243 244 // We capture 2 VLA sizes in this target region 245 246 247 // The names below are not necessarily consistent with the names used for the 248 // addresses above as some are repeated. 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 // Check that the offloading functions are emitted and that the arguments are 269 // correct and loaded correctly for the target regions of the callees of bar(). 270 271 // Create local storage for each capture. 272 // Store captures in the context. 273 274 275 276 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 277 278 279 // Create local storage for each capture. 280 // Store captures in the context. 281 282 283 284 285 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 286 287 // Create local storage for each capture. 288 // Store captures in the context. 289 290 291 292 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 293 294 295 #endif 296 // CHECK1-LABEL: define {{[^@]+}}@_Z7get_valv 297 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 298 // CHECK1-NEXT: entry: 299 // CHECK1-NEXT: ret i64 0 300 // 301 // 302 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 303 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 304 // CHECK1-NEXT: entry: 305 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 306 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 307 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 308 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 309 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 310 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 311 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 312 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 314 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 315 // CHECK1-NEXT: [[K:%.*]] = alloca i64, align 8 316 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 317 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[LIN:%.*]] = alloca i32, align 4 319 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 320 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 321 // CHECK1-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 322 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 323 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 324 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 325 // CHECK1-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 326 // CHECK1-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 327 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 328 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 329 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 330 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 331 // CHECK1-NEXT: [[A_CASTED16:%.*]] = alloca i64, align 8 332 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 333 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [10 x i8*], align 8 334 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [10 x i8*], align 8 335 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [10 x i8*], align 8 336 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 337 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 338 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 339 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 340 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 341 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 342 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 343 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 344 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 345 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 346 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 347 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 348 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 349 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 350 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 351 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 352 // CHECK1-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 353 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 354 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 355 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]]) 356 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 357 // CHECK1-NEXT: store i64 [[CALL]], i64* [[K]], align 8 358 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 359 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 360 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 361 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 362 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[K]], align 8 363 // CHECK1-NEXT: store i64 [[TMP13]], i64* [[K_CASTED]], align 8 364 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8 365 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]] 366 // CHECK1-NEXT: store i32 12, i32* [[LIN]], align 4 367 // CHECK1-NEXT: [[TMP15:%.*]] = load i16, i16* [[AA]], align 2 368 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 369 // CHECK1-NEXT: store i16 [[TMP15]], i16* [[CONV2]], align 2 370 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8 371 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4 372 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 373 // CHECK1-NEXT: store i32 [[TMP17]], i32* [[CONV3]], align 4 374 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 375 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[A]], align 4 376 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 377 // CHECK1-NEXT: store i32 [[TMP19]], i32* [[CONV5]], align 4 378 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8 379 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 380 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 381 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP22]], align 8 382 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 383 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 384 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[TMP24]], align 8 385 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 386 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 387 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 388 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 389 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 390 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 391 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 392 // CHECK1-NEXT: store i64 [[TMP18]], i64* [[TMP29]], align 8 393 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 394 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 395 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 396 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 397 // CHECK1-NEXT: store i64 [[TMP20]], i64* [[TMP32]], align 8 398 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 399 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64* 400 // CHECK1-NEXT: store i64 [[TMP20]], i64* [[TMP34]], align 8 401 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 402 // CHECK1-NEXT: store i8* null, i8** [[TMP35]], align 8 403 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 404 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 405 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 406 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 407 // CHECK1-NEXT: store i32 1, i32* [[TMP38]], align 4 408 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 409 // CHECK1-NEXT: store i32 3, i32* [[TMP39]], align 4 410 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 411 // CHECK1-NEXT: store i8** [[TMP36]], i8*** [[TMP40]], align 8 412 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 413 // CHECK1-NEXT: store i8** [[TMP37]], i8*** [[TMP41]], align 8 414 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 415 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP42]], align 8 416 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 417 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP43]], align 8 418 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 419 // CHECK1-NEXT: store i8** null, i8*** [[TMP44]], align 8 420 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 421 // CHECK1-NEXT: store i8** null, i8*** [[TMP45]], align 8 422 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 423 // CHECK1-NEXT: store i64 0, i64* [[TMP46]], align 8 424 // CHECK1-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 425 // CHECK1-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 426 // CHECK1-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 427 // CHECK1: omp_offload.failed: 428 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]] 429 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 430 // CHECK1: omp_offload.cont: 431 // CHECK1-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4 432 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 433 // CHECK1-NEXT: store i32 [[TMP49]], i32* [[CONV7]], align 4 434 // CHECK1-NEXT: [[TMP50:%.*]] = load i64, i64* [[A_CASTED6]], align 8 435 // CHECK1-NEXT: [[TMP51:%.*]] = load i16, i16* [[AA]], align 2 436 // CHECK1-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 437 // CHECK1-NEXT: store i16 [[TMP51]], i16* [[CONV9]], align 2 438 // CHECK1-NEXT: [[TMP52:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 439 // CHECK1-NEXT: [[TMP53:%.*]] = load i32, i32* [[N_ADDR]], align 4 440 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP53]], 10 441 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 442 // CHECK1: omp_if.then: 443 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 444 // CHECK1-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i64* 445 // CHECK1-NEXT: store i64 [[TMP50]], i64* [[TMP55]], align 8 446 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 447 // CHECK1-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to i64* 448 // CHECK1-NEXT: store i64 [[TMP50]], i64* [[TMP57]], align 8 449 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 450 // CHECK1-NEXT: store i8* null, i8** [[TMP58]], align 8 451 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 452 // CHECK1-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* 453 // CHECK1-NEXT: store i64 [[TMP52]], i64* [[TMP60]], align 8 454 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 455 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 456 // CHECK1-NEXT: store i64 [[TMP52]], i64* [[TMP62]], align 8 457 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 458 // CHECK1-NEXT: store i8* null, i8** [[TMP63]], align 8 459 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 460 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 461 // CHECK1-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 462 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0 463 // CHECK1-NEXT: store i32 1, i32* [[TMP66]], align 4 464 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1 465 // CHECK1-NEXT: store i32 2, i32* [[TMP67]], align 4 466 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2 467 // CHECK1-NEXT: store i8** [[TMP64]], i8*** [[TMP68]], align 8 468 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3 469 // CHECK1-NEXT: store i8** [[TMP65]], i8*** [[TMP69]], align 8 470 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4 471 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP70]], align 8 472 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5 473 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP71]], align 8 474 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6 475 // CHECK1-NEXT: store i8** null, i8*** [[TMP72]], align 8 476 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7 477 // CHECK1-NEXT: store i8** null, i8*** [[TMP73]], align 8 478 // CHECK1-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8 479 // CHECK1-NEXT: store i64 0, i64* [[TMP74]], align 8 480 // CHECK1-NEXT: [[TMP75:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]]) 481 // CHECK1-NEXT: [[TMP76:%.*]] = icmp ne i32 [[TMP75]], 0 482 // CHECK1-NEXT: br i1 [[TMP76]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] 483 // CHECK1: omp_offload.failed14: 484 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP50]], i64 [[TMP52]]) #[[ATTR4]] 485 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT15]] 486 // CHECK1: omp_offload.cont15: 487 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 488 // CHECK1: omp_if.else: 489 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP50]], i64 [[TMP52]]) #[[ATTR4]] 490 // CHECK1-NEXT: br label [[OMP_IF_END]] 491 // CHECK1: omp_if.end: 492 // CHECK1-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 493 // CHECK1-NEXT: store i32 [[TMP77]], i32* [[DOTCAPTURE_EXPR_]], align 4 494 // CHECK1-NEXT: [[TMP78:%.*]] = load i32, i32* [[A]], align 4 495 // CHECK1-NEXT: [[CONV17:%.*]] = bitcast i64* [[A_CASTED16]] to i32* 496 // CHECK1-NEXT: store i32 [[TMP78]], i32* [[CONV17]], align 4 497 // CHECK1-NEXT: [[TMP79:%.*]] = load i64, i64* [[A_CASTED16]], align 8 498 // CHECK1-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 499 // CHECK1-NEXT: [[CONV18:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 500 // CHECK1-NEXT: store i32 [[TMP80]], i32* [[CONV18]], align 4 501 // CHECK1-NEXT: [[TMP81:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 502 // CHECK1-NEXT: [[TMP82:%.*]] = load i32, i32* [[N_ADDR]], align 4 503 // CHECK1-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[TMP82]], 20 504 // CHECK1-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]] 505 // CHECK1: omp_if.then20: 506 // CHECK1-NEXT: [[TMP83:%.*]] = mul nuw i64 [[TMP2]], 4 507 // CHECK1-NEXT: [[TMP84:%.*]] = mul nuw i64 5, [[TMP5]] 508 // CHECK1-NEXT: [[TMP85:%.*]] = mul nuw i64 [[TMP84]], 8 509 // CHECK1-NEXT: [[TMP86:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 510 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP86]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 511 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 512 // CHECK1-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* 513 // CHECK1-NEXT: store i64 [[TMP79]], i64* [[TMP88]], align 8 514 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 515 // CHECK1-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* 516 // CHECK1-NEXT: store i64 [[TMP79]], i64* [[TMP90]], align 8 517 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 518 // CHECK1-NEXT: store i8* null, i8** [[TMP91]], align 8 519 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 520 // CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [10 x float]** 521 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP93]], align 8 522 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 523 // CHECK1-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [10 x float]** 524 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP95]], align 8 525 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 526 // CHECK1-NEXT: store i8* null, i8** [[TMP96]], align 8 527 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 528 // CHECK1-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* 529 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP98]], align 8 530 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 531 // CHECK1-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i64* 532 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP100]], align 8 533 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 534 // CHECK1-NEXT: store i8* null, i8** [[TMP101]], align 8 535 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 536 // CHECK1-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to float** 537 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP103]], align 8 538 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 539 // CHECK1-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to float** 540 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP105]], align 8 541 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 542 // CHECK1-NEXT: store i64 [[TMP83]], i64* [[TMP106]], align 8 543 // CHECK1-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 544 // CHECK1-NEXT: store i8* null, i8** [[TMP107]], align 8 545 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4 546 // CHECK1-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to [5 x [10 x double]]** 547 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP109]], align 8 548 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4 549 // CHECK1-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to [5 x [10 x double]]** 550 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP111]], align 8 551 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 4 552 // CHECK1-NEXT: store i8* null, i8** [[TMP112]], align 8 553 // CHECK1-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5 554 // CHECK1-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* 555 // CHECK1-NEXT: store i64 5, i64* [[TMP114]], align 8 556 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5 557 // CHECK1-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to i64* 558 // CHECK1-NEXT: store i64 5, i64* [[TMP116]], align 8 559 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 5 560 // CHECK1-NEXT: store i8* null, i8** [[TMP117]], align 8 561 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6 562 // CHECK1-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 563 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP119]], align 8 564 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6 565 // CHECK1-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i64* 566 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP121]], align 8 567 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 6 568 // CHECK1-NEXT: store i8* null, i8** [[TMP122]], align 8 569 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7 570 // CHECK1-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** 571 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP124]], align 8 572 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7 573 // CHECK1-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to double** 574 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP126]], align 8 575 // CHECK1-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 576 // CHECK1-NEXT: store i64 [[TMP85]], i64* [[TMP127]], align 8 577 // CHECK1-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 7 578 // CHECK1-NEXT: store i8* null, i8** [[TMP128]], align 8 579 // CHECK1-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8 580 // CHECK1-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to %struct.TT** 581 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP130]], align 8 582 // CHECK1-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8 583 // CHECK1-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to %struct.TT** 584 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP132]], align 8 585 // CHECK1-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 8 586 // CHECK1-NEXT: store i8* null, i8** [[TMP133]], align 8 587 // CHECK1-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 9 588 // CHECK1-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64* 589 // CHECK1-NEXT: store i64 [[TMP81]], i64* [[TMP135]], align 8 590 // CHECK1-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 9 591 // CHECK1-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* 592 // CHECK1-NEXT: store i64 [[TMP81]], i64* [[TMP137]], align 8 593 // CHECK1-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 9 594 // CHECK1-NEXT: store i8* null, i8** [[TMP138]], align 8 595 // CHECK1-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 596 // CHECK1-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 597 // CHECK1-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 598 // CHECK1-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 599 // CHECK1-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 0 600 // CHECK1-NEXT: store i32 1, i32* [[TMP142]], align 4 601 // CHECK1-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 1 602 // CHECK1-NEXT: store i32 10, i32* [[TMP143]], align 4 603 // CHECK1-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 2 604 // CHECK1-NEXT: store i8** [[TMP139]], i8*** [[TMP144]], align 8 605 // CHECK1-NEXT: [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 3 606 // CHECK1-NEXT: store i8** [[TMP140]], i8*** [[TMP145]], align 8 607 // CHECK1-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 4 608 // CHECK1-NEXT: store i64* [[TMP141]], i64** [[TMP146]], align 8 609 // CHECK1-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 5 610 // CHECK1-NEXT: store i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP147]], align 8 611 // CHECK1-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 6 612 // CHECK1-NEXT: store i8** null, i8*** [[TMP148]], align 8 613 // CHECK1-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 7 614 // CHECK1-NEXT: store i8** null, i8*** [[TMP149]], align 8 615 // CHECK1-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 8 616 // CHECK1-NEXT: store i64 0, i64* [[TMP150]], align 8 617 // CHECK1-NEXT: [[TMP151:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]]) 618 // CHECK1-NEXT: [[TMP152:%.*]] = icmp ne i32 [[TMP151]], 0 619 // CHECK1-NEXT: br i1 [[TMP152]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] 620 // CHECK1: omp_offload.failed25: 621 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP79]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP81]]) #[[ATTR4]] 622 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT26]] 623 // CHECK1: omp_offload.cont26: 624 // CHECK1-NEXT: br label [[OMP_IF_END28:%.*]] 625 // CHECK1: omp_if.else27: 626 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP79]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP81]]) #[[ATTR4]] 627 // CHECK1-NEXT: br label [[OMP_IF_END28]] 628 // CHECK1: omp_if.end28: 629 // CHECK1-NEXT: [[TMP153:%.*]] = load i32, i32* [[A]], align 4 630 // CHECK1-NEXT: [[TMP154:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 631 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP154]]) 632 // CHECK1-NEXT: ret i32 [[TMP153]] 633 // 634 // 635 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 636 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 637 // CHECK1-NEXT: entry: 638 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 639 // CHECK1-NEXT: ret void 640 // 641 // 642 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 643 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 644 // CHECK1-NEXT: entry: 645 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 646 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 647 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 648 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 649 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 650 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 651 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 652 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 653 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 654 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 655 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 656 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 657 // CHECK1-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 658 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 659 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 660 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 661 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 662 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 663 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 664 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 665 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 666 // CHECK1: cond.true: 667 // CHECK1-NEXT: br label [[COND_END:%.*]] 668 // CHECK1: cond.false: 669 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 670 // CHECK1-NEXT: br label [[COND_END]] 671 // CHECK1: cond.end: 672 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 673 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 674 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 675 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 676 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 677 // CHECK1: omp.inner.for.cond: 678 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 679 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 680 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 681 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 682 // CHECK1: omp.inner.for.body: 683 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 684 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 685 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 686 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 687 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 688 // CHECK1: omp.body.continue: 689 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 690 // CHECK1: omp.inner.for.inc: 691 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 692 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 693 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 694 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 695 // CHECK1: omp.inner.for.end: 696 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 697 // CHECK1: omp.loop.exit: 698 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 699 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 700 // CHECK1-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 701 // CHECK1-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 702 // CHECK1: .omp.final.then: 703 // CHECK1-NEXT: store i32 33, i32* [[I]], align 4 704 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 705 // CHECK1: .omp.final.done: 706 // CHECK1-NEXT: ret void 707 // 708 // 709 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 710 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 711 // CHECK1-NEXT: entry: 712 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 713 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 714 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 715 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 716 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 717 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 718 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 719 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 720 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 721 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 722 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 723 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 724 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 725 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 726 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 727 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 728 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 729 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 730 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 731 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 732 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 733 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 734 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 735 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 736 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 737 // CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 738 // CHECK1-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 739 // CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 740 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 741 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 742 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0 743 // CHECK1-NEXT: store i32 1, i32* [[TMP11]], align 4, !noalias !25 744 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1 745 // CHECK1-NEXT: store i32 0, i32* [[TMP12]], align 4, !noalias !25 746 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2 747 // CHECK1-NEXT: store i8** null, i8*** [[TMP13]], align 8, !noalias !25 748 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3 749 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8, !noalias !25 750 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4 751 // CHECK1-NEXT: store i64* null, i64** [[TMP15]], align 8, !noalias !25 752 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5 753 // CHECK1-NEXT: store i64* null, i64** [[TMP16]], align 8, !noalias !25 754 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6 755 // CHECK1-NEXT: store i8** null, i8*** [[TMP17]], align 8, !noalias !25 756 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7 757 // CHECK1-NEXT: store i8** null, i8*** [[TMP18]], align 8, !noalias !25 758 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8 759 // CHECK1-NEXT: store i64 0, i64* [[TMP19]], align 8, !noalias !25 760 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) 761 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 762 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 763 // CHECK1: omp_offload.failed.i: 764 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 765 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 766 // CHECK1: .omp_outlined..1.exit: 767 // CHECK1-NEXT: ret i32 0 768 // 769 // 770 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 771 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 772 // CHECK1-NEXT: entry: 773 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 774 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 775 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 776 // CHECK1-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 777 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 778 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 779 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 780 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 781 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 782 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 783 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 784 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 785 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 786 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 787 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 788 // CHECK1-NEXT: ret void 789 // 790 // 791 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 792 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 793 // CHECK1-NEXT: entry: 794 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 795 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 796 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 797 // CHECK1-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 798 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 799 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 800 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 801 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 802 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 803 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 804 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 805 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 806 // CHECK1-NEXT: [[K1:%.*]] = alloca i64, align 8 807 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 808 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 809 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 810 // CHECK1-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 811 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 812 // CHECK1-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 813 // CHECK1-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 814 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 815 // CHECK1-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 816 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 817 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 818 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 819 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 820 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 821 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 35, i32 0, i32 8, i32 1, i32 1) 822 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 823 // CHECK1: omp.dispatch.cond: 824 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 825 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 826 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 827 // CHECK1: omp.dispatch.body: 828 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 829 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 830 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 831 // CHECK1: omp.inner.for.cond: 832 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] 833 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] 834 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 835 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 836 // CHECK1: omp.inner.for.body: 837 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 838 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 839 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 840 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP26]] 841 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]] 842 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 843 // CHECK1-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 844 // CHECK1-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 845 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 846 // CHECK1-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group [[ACC_GRP26]] 847 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP26]] 848 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 849 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP26]] 850 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 851 // CHECK1: omp.body.continue: 852 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 853 // CHECK1: omp.inner.for.inc: 854 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 855 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 856 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 857 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 858 // CHECK1: omp.inner.for.end: 859 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 860 // CHECK1: omp.dispatch.inc: 861 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 862 // CHECK1: omp.dispatch.end: 863 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 864 // CHECK1-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 865 // CHECK1-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 866 // CHECK1: .omp.final.then: 867 // CHECK1-NEXT: store i32 1, i32* [[I]], align 4 868 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 869 // CHECK1: .omp.final.done: 870 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 871 // CHECK1-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 872 // CHECK1-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 873 // CHECK1: .omp.linear.pu: 874 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[K1]], align 8 875 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[K_ADDR]], align 8 876 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 877 // CHECK1: .omp.linear.pu.done: 878 // CHECK1-NEXT: ret void 879 // 880 // 881 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 882 // CHECK1-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 883 // CHECK1-NEXT: entry: 884 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 885 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 886 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 887 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 888 // CHECK1-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 889 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 890 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 891 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 892 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 893 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 894 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 895 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 896 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 897 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 898 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 899 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 900 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 901 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 902 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 903 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 904 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 905 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 906 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 907 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 908 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 909 // CHECK1-NEXT: ret void 910 // 911 // 912 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 913 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 914 // CHECK1-NEXT: entry: 915 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 916 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 917 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 918 // CHECK1-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 919 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 920 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 921 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 922 // CHECK1-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 923 // CHECK1-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 924 // CHECK1-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 925 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 926 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 927 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 928 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 929 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 930 // CHECK1-NEXT: [[LIN4:%.*]] = alloca i32, align 4 931 // CHECK1-NEXT: [[A5:%.*]] = alloca i32, align 4 932 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 933 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 934 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 935 // CHECK1-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 936 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 937 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 938 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 939 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 940 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 941 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 942 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 943 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 944 // CHECK1-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 945 // CHECK1-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 946 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 947 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 948 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 949 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 950 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 951 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 952 // CHECK1-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 953 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 954 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 955 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 956 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 957 // CHECK1: cond.true: 958 // CHECK1-NEXT: br label [[COND_END:%.*]] 959 // CHECK1: cond.false: 960 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 961 // CHECK1-NEXT: br label [[COND_END]] 962 // CHECK1: cond.end: 963 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 964 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 965 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 966 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 967 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 968 // CHECK1: omp.inner.for.cond: 969 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 970 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 971 // CHECK1-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 972 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 973 // CHECK1: omp.inner.for.body: 974 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 975 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 976 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 977 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP29]] 978 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]] 979 // CHECK1-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 980 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 981 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 982 // CHECK1-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 983 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 984 // CHECK1-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 985 // CHECK1-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group [[ACC_GRP29]] 986 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group [[ACC_GRP29]] 987 // CHECK1-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 988 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 989 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 990 // CHECK1-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 991 // CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 992 // CHECK1-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 993 // CHECK1-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group [[ACC_GRP29]] 994 // CHECK1-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP29]] 995 // CHECK1-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 996 // CHECK1-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 997 // CHECK1-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 998 // CHECK1-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP29]] 999 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1000 // CHECK1: omp.body.continue: 1001 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1002 // CHECK1: omp.inner.for.inc: 1003 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 1004 // CHECK1-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 1005 // CHECK1-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 1006 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 1007 // CHECK1: omp.inner.for.end: 1008 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1009 // CHECK1: omp.loop.exit: 1010 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 1011 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1012 // CHECK1-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 1013 // CHECK1-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1014 // CHECK1: .omp.final.then: 1015 // CHECK1-NEXT: store i64 400, i64* [[IT]], align 8 1016 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1017 // CHECK1: .omp.final.done: 1018 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1019 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1020 // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 1021 // CHECK1: .omp.linear.pu: 1022 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 1023 // CHECK1-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 1024 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 1025 // CHECK1-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 1026 // CHECK1-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 1027 // CHECK1: .omp.linear.pu.done: 1028 // CHECK1-NEXT: ret void 1029 // 1030 // 1031 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 1032 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1033 // CHECK1-NEXT: entry: 1034 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1035 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1036 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1037 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1038 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1039 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1040 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1041 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1042 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1043 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1044 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 1045 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1046 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1047 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1048 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 1049 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1050 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 1051 // CHECK1-NEXT: ret void 1052 // 1053 // 1054 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 1055 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 1056 // CHECK1-NEXT: entry: 1057 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1058 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1059 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1060 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1061 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1062 // CHECK1-NEXT: [[TMP:%.*]] = alloca i16, align 2 1063 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1064 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1065 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1066 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1067 // CHECK1-NEXT: [[IT:%.*]] = alloca i16, align 2 1068 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1069 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1070 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1071 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1072 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1073 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1074 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1075 // CHECK1-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 1076 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1077 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1078 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1079 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 1080 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1081 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1082 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 1083 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1084 // CHECK1: cond.true: 1085 // CHECK1-NEXT: br label [[COND_END:%.*]] 1086 // CHECK1: cond.false: 1087 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1088 // CHECK1-NEXT: br label [[COND_END]] 1089 // CHECK1: cond.end: 1090 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 1091 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1092 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1093 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 1094 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1095 // CHECK1: omp.inner.for.cond: 1096 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] 1097 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] 1098 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 1099 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1100 // CHECK1: omp.inner.for.body: 1101 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1102 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 1103 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 1104 // CHECK1-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 1105 // CHECK1-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group [[ACC_GRP32]] 1106 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP32]] 1107 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 1108 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP32]] 1109 // CHECK1-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP32]] 1110 // CHECK1-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 1111 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 1112 // CHECK1-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 1113 // CHECK1-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP32]] 1114 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1115 // CHECK1: omp.body.continue: 1116 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1117 // CHECK1: omp.inner.for.inc: 1118 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1119 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 1120 // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 1121 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 1122 // CHECK1: omp.inner.for.end: 1123 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1124 // CHECK1: omp.loop.exit: 1125 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 1126 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1127 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1128 // CHECK1-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1129 // CHECK1: .omp.final.then: 1130 // CHECK1-NEXT: store i16 22, i16* [[IT]], align 2 1131 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1132 // CHECK1: .omp.final.done: 1133 // CHECK1-NEXT: ret void 1134 // 1135 // 1136 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 1137 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 1138 // CHECK1-NEXT: entry: 1139 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1140 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1141 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1142 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1143 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1144 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1145 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1146 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1147 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1148 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1149 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1150 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1151 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1152 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1153 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1154 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1155 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1156 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1157 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1158 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1159 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1160 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1161 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1162 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1163 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1164 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1165 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1166 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1167 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1168 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1169 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1170 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1171 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1172 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1173 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 1174 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1175 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 1176 // CHECK1-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 1177 // CHECK1-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 1178 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1179 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 1180 // CHECK1-NEXT: ret void 1181 // 1182 // 1183 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 1184 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 1185 // CHECK1-NEXT: entry: 1186 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1187 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1188 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1189 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1190 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1191 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1192 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1193 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1194 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1195 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1196 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1197 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1198 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1199 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1200 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1201 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1202 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1203 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1204 // CHECK1-NEXT: [[IT:%.*]] = alloca i8, align 1 1205 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1206 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1207 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1208 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1209 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1210 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1211 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1212 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1213 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1214 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1215 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1216 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1217 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1218 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1219 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1220 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1221 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1222 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1223 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1224 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1225 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1226 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 1227 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1228 // CHECK1-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 1229 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1230 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1231 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 1232 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1233 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1234 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 1235 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1236 // CHECK1: omp.dispatch.cond: 1237 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1238 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 1239 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1240 // CHECK1: cond.true: 1241 // CHECK1-NEXT: br label [[COND_END:%.*]] 1242 // CHECK1: cond.false: 1243 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1244 // CHECK1-NEXT: br label [[COND_END]] 1245 // CHECK1: cond.end: 1246 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1247 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1248 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1249 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1250 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1251 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1252 // CHECK1-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1253 // CHECK1-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1254 // CHECK1: omp.dispatch.body: 1255 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1256 // CHECK1: omp.inner.for.cond: 1257 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] 1258 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] 1259 // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 1260 // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1261 // CHECK1: omp.inner.for.body: 1262 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1263 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 1264 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 1265 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 1266 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group [[ACC_GRP35]] 1267 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP35]] 1268 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 1269 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP35]] 1270 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1271 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 1272 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 1273 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1274 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1275 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 1276 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1277 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP35]] 1278 // CHECK1-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 1279 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 1280 // CHECK1-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 1281 // CHECK1-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP35]] 1282 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1283 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 1284 // CHECK1-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]] 1285 // CHECK1-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 1286 // CHECK1-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]] 1287 // CHECK1-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 1288 // CHECK1-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 1289 // CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 1290 // CHECK1-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group [[ACC_GRP35]] 1291 // CHECK1-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 1292 // CHECK1-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group [[ACC_GRP35]] 1293 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1294 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 1295 // CHECK1-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 1296 // CHECK1-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 1297 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1298 // CHECK1-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 1299 // CHECK1-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 1300 // CHECK1-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 1301 // CHECK1-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 1302 // CHECK1-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 1303 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1304 // CHECK1: omp.body.continue: 1305 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1306 // CHECK1: omp.inner.for.inc: 1307 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1308 // CHECK1-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 1309 // CHECK1-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 1310 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 1311 // CHECK1: omp.inner.for.end: 1312 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1313 // CHECK1: omp.dispatch.inc: 1314 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1315 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1316 // CHECK1-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 1317 // CHECK1-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 1318 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1319 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1320 // CHECK1-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 1321 // CHECK1-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 1322 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1323 // CHECK1: omp.dispatch.end: 1324 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 1325 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1326 // CHECK1-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 1327 // CHECK1-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1328 // CHECK1: .omp.final.then: 1329 // CHECK1-NEXT: store i8 96, i8* [[IT]], align 1 1330 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1331 // CHECK1: .omp.final.done: 1332 // CHECK1-NEXT: ret void 1333 // 1334 // 1335 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 1336 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1337 // CHECK1-NEXT: entry: 1338 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1339 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1340 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1341 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1342 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1343 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1344 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1345 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1346 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1347 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1348 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1349 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1350 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1351 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1352 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1353 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1354 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1355 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1356 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1357 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1358 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1359 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1360 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1361 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1362 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1363 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1364 // CHECK1-NEXT: ret i32 [[TMP8]] 1365 // 1366 // 1367 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1368 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1369 // CHECK1-NEXT: entry: 1370 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1371 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1372 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 1373 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1374 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1375 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1376 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1377 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1378 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1379 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1380 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1381 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1382 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1383 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1384 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1385 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1386 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1387 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1388 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1389 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1390 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1391 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1392 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1393 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1394 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1395 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1396 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1397 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1398 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1399 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1400 // CHECK1: omp_if.then: 1401 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1402 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1403 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1404 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1405 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 1406 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1407 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1408 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1409 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1410 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1411 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 1412 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1413 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 1414 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1415 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1416 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1417 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1418 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1419 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1420 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1421 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 1422 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1423 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1424 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 1425 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1426 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1427 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 1428 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1429 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 1430 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1431 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1432 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1433 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1434 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1435 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1436 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1437 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 1438 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1439 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1440 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1441 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1442 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1443 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1444 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1445 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1446 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1447 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 1448 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1449 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1450 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1451 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1452 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1453 // CHECK1-NEXT: store i32 1, i32* [[TMP40]], align 4 1454 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1455 // CHECK1-NEXT: store i32 5, i32* [[TMP41]], align 4 1456 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1457 // CHECK1-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8 1458 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1459 // CHECK1-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 8 1460 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1461 // CHECK1-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 8 1462 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1463 // CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP45]], align 8 1464 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1465 // CHECK1-NEXT: store i8** null, i8*** [[TMP46]], align 8 1466 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1467 // CHECK1-NEXT: store i8** null, i8*** [[TMP47]], align 8 1468 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1469 // CHECK1-NEXT: store i64 0, i64* [[TMP48]], align 8 1470 // CHECK1-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1471 // CHECK1-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 1472 // CHECK1-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1473 // CHECK1: omp_offload.failed: 1474 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1475 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1476 // CHECK1: omp_offload.cont: 1477 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1478 // CHECK1: omp_if.else: 1479 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1480 // CHECK1-NEXT: br label [[OMP_IF_END]] 1481 // CHECK1: omp_if.end: 1482 // CHECK1-NEXT: [[TMP51:%.*]] = mul nsw i64 1, [[TMP2]] 1483 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP51]] 1484 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1485 // CHECK1-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1486 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP52]] to i32 1487 // CHECK1-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4 1488 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP53]] 1489 // CHECK1-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1490 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP54]]) 1491 // CHECK1-NEXT: ret i32 [[ADD4]] 1492 // 1493 // 1494 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1495 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1496 // CHECK1-NEXT: entry: 1497 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1498 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1499 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1500 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1501 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1502 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1503 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1504 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1505 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1506 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1507 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1508 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1509 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1510 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1511 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1512 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1513 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1514 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1515 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1516 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1517 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1518 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1519 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1520 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1521 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1522 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1523 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1524 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1525 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1526 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1527 // CHECK1: omp_if.then: 1528 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1529 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1530 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1531 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1532 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1533 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1534 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1535 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1536 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1537 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1538 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1539 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1540 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1541 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1542 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1543 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1544 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1545 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1546 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1547 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1548 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1549 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1550 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1551 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1552 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1553 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1554 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1555 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1556 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1557 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1558 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1559 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1560 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1561 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1562 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1563 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1564 // CHECK1-NEXT: store i32 1, i32* [[TMP29]], align 4 1565 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1566 // CHECK1-NEXT: store i32 4, i32* [[TMP30]], align 4 1567 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1568 // CHECK1-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 8 1569 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1570 // CHECK1-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8 1571 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1572 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 8 1573 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1574 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 8 1575 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1576 // CHECK1-NEXT: store i8** null, i8*** [[TMP35]], align 8 1577 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1578 // CHECK1-NEXT: store i8** null, i8*** [[TMP36]], align 8 1579 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1580 // CHECK1-NEXT: store i64 0, i64* [[TMP37]], align 8 1581 // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1582 // CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 1583 // CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1584 // CHECK1: omp_offload.failed: 1585 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1586 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1587 // CHECK1: omp_offload.cont: 1588 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1589 // CHECK1: omp_if.else: 1590 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1591 // CHECK1-NEXT: br label [[OMP_IF_END]] 1592 // CHECK1: omp_if.end: 1593 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 1594 // CHECK1-NEXT: ret i32 [[TMP40]] 1595 // 1596 // 1597 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1598 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1599 // CHECK1-NEXT: entry: 1600 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1601 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1602 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1603 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1604 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1605 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1606 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1607 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1608 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1609 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1610 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1611 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1612 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1613 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1614 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1615 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1616 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1617 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1618 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1619 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1620 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1621 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1622 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1623 // CHECK1: omp_if.then: 1624 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1625 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1626 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1627 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1628 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1629 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1630 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1631 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1632 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1633 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1634 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1635 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1636 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1637 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1638 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1639 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1640 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1641 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1642 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1643 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1644 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1645 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1646 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1647 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1648 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1649 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1650 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1651 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1652 // CHECK1-NEXT: store i32 1, i32* [[TMP22]], align 4 1653 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1654 // CHECK1-NEXT: store i32 3, i32* [[TMP23]], align 4 1655 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1656 // CHECK1-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8 1657 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1658 // CHECK1-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 8 1659 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1660 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 8 1661 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1662 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 8 1663 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1664 // CHECK1-NEXT: store i8** null, i8*** [[TMP28]], align 8 1665 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1666 // CHECK1-NEXT: store i8** null, i8*** [[TMP29]], align 8 1667 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1668 // CHECK1-NEXT: store i64 0, i64* [[TMP30]], align 8 1669 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1670 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1671 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1672 // CHECK1: omp_offload.failed: 1673 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1674 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1675 // CHECK1: omp_offload.cont: 1676 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1677 // CHECK1: omp_if.else: 1678 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1679 // CHECK1-NEXT: br label [[OMP_IF_END]] 1680 // CHECK1: omp_if.end: 1681 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4 1682 // CHECK1-NEXT: ret i32 [[TMP33]] 1683 // 1684 // 1685 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 1686 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1687 // CHECK1-NEXT: entry: 1688 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1689 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1690 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1691 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1692 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1693 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1694 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1695 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1696 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1697 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1698 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1699 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1700 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1701 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1702 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1703 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1704 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1705 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1706 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1707 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1708 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1709 // CHECK1-NEXT: ret void 1710 // 1711 // 1712 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 1713 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1714 // CHECK1-NEXT: entry: 1715 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1716 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1717 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1718 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1719 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1720 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1721 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1722 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1723 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1724 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1725 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1726 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1727 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1728 // CHECK1-NEXT: [[IT:%.*]] = alloca i64, align 8 1729 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1730 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1731 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1732 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1733 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1734 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1735 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1736 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1737 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1738 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1739 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1740 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1741 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1742 // CHECK1-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 1743 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1744 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1745 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1746 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1747 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1748 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1749 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 1750 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1751 // CHECK1: cond.true: 1752 // CHECK1-NEXT: br label [[COND_END:%.*]] 1753 // CHECK1: cond.false: 1754 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1755 // CHECK1-NEXT: br label [[COND_END]] 1756 // CHECK1: cond.end: 1757 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1758 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1759 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1760 // CHECK1-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 1761 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1762 // CHECK1: omp.inner.for.cond: 1763 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]] 1764 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]] 1765 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 1766 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1767 // CHECK1: omp.inner.for.body: 1768 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1769 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 1770 // CHECK1-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 1771 // CHECK1-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP38]] 1772 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP38]] 1773 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 1774 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 1775 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1776 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group [[ACC_GRP38]] 1777 // CHECK1-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1778 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group [[ACC_GRP38]] 1779 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 1780 // CHECK1-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group [[ACC_GRP38]] 1781 // CHECK1-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 1782 // CHECK1-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 1783 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 1784 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1785 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP38]] 1786 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1787 // CHECK1: omp.body.continue: 1788 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1789 // CHECK1: omp.inner.for.inc: 1790 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1791 // CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 1792 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 1793 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP39:![0-9]+]] 1794 // CHECK1: omp.inner.for.end: 1795 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1796 // CHECK1: omp.loop.exit: 1797 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1798 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1799 // CHECK1-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 1800 // CHECK1-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1801 // CHECK1: .omp.final.then: 1802 // CHECK1-NEXT: store i64 400, i64* [[IT]], align 8 1803 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1804 // CHECK1: .omp.final.done: 1805 // CHECK1-NEXT: ret void 1806 // 1807 // 1808 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 1809 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1810 // CHECK1-NEXT: entry: 1811 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1812 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1813 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1814 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1815 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1816 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1817 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1818 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1819 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1820 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1821 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1822 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1823 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1824 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1825 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1826 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1827 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1828 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1829 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1830 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1831 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1832 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1833 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1834 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1835 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1836 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1837 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1838 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1839 // CHECK1-NEXT: ret void 1840 // 1841 // 1842 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1843 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1844 // CHECK1-NEXT: entry: 1845 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1846 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1847 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1848 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1849 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1850 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1851 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1852 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1853 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1854 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1855 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1856 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1857 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1858 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1859 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1860 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1861 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1862 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1863 // CHECK1-NEXT: ret void 1864 // 1865 // 1866 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 1867 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1868 // CHECK1-NEXT: entry: 1869 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1870 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1871 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1872 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1873 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1874 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1875 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1876 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1877 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1878 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1879 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1880 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1881 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1882 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1883 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1884 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1885 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1886 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1887 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1888 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1889 // CHECK1-NEXT: ret void 1890 // 1891 // 1892 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1893 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1894 // CHECK1-NEXT: entry: 1895 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1896 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1897 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1898 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1899 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1900 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1901 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 1902 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1903 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1904 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1905 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1906 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 1907 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1908 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1909 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1910 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1911 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1912 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1913 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1914 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1915 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1916 // CHECK1-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 1917 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1918 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1919 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1920 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1921 // CHECK1-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 1922 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1923 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 1924 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1925 // CHECK1: cond.true: 1926 // CHECK1-NEXT: br label [[COND_END:%.*]] 1927 // CHECK1: cond.false: 1928 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1929 // CHECK1-NEXT: br label [[COND_END]] 1930 // CHECK1: cond.end: 1931 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 1932 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1933 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1934 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 1935 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1936 // CHECK1: omp.inner.for.cond: 1937 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41:![0-9]+]] 1938 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP41]] 1939 // CHECK1-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 1940 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1941 // CHECK1: omp.inner.for.body: 1942 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1943 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 1944 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 1945 // CHECK1-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP41]] 1946 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP41]] 1947 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 1948 // CHECK1-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP41]] 1949 // CHECK1-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP41]] 1950 // CHECK1-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 1951 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 1952 // CHECK1-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 1953 // CHECK1-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP41]] 1954 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1955 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] 1956 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 1957 // CHECK1-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP41]] 1958 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1959 // CHECK1: omp.body.continue: 1960 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1961 // CHECK1: omp.inner.for.inc: 1962 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1963 // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 1964 // CHECK1-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP41]] 1965 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP42:![0-9]+]] 1966 // CHECK1: omp.inner.for.end: 1967 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1968 // CHECK1: omp.loop.exit: 1969 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 1970 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 1971 // CHECK1-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 1972 // CHECK1-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 1973 // CHECK1: .omp.final.then: 1974 // CHECK1-NEXT: store i64 11, i64* [[I]], align 8 1975 // CHECK1-NEXT: br label [[DOTOMP_FINAL_DONE]] 1976 // CHECK1: .omp.final.done: 1977 // CHECK1-NEXT: ret void 1978 // 1979 // 1980 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1981 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { 1982 // CHECK1-NEXT: entry: 1983 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1984 // CHECK1-NEXT: ret void 1985 // 1986 // 1987 // CHECK3-LABEL: define {{[^@]+}}@_Z7get_valv 1988 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 1989 // CHECK3-NEXT: entry: 1990 // CHECK3-NEXT: ret i64 0 1991 // 1992 // 1993 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1994 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 1995 // CHECK3-NEXT: entry: 1996 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1997 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1998 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1999 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 2000 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2001 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2002 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 2003 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2004 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 2005 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 2006 // CHECK3-NEXT: [[K:%.*]] = alloca i64, align 8 2007 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2008 // CHECK3-NEXT: [[LIN:%.*]] = alloca i32, align 4 2009 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2010 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 2011 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 2012 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 2013 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 2014 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 2015 // CHECK3-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 2016 // CHECK3-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 2017 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 2018 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 2019 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 2020 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 2021 // CHECK3-NEXT: [[A_CASTED12:%.*]] = alloca i32, align 4 2022 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2023 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS15:%.*]] = alloca [10 x i8*], align 4 2024 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS16:%.*]] = alloca [10 x i8*], align 4 2025 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS17:%.*]] = alloca [10 x i8*], align 4 2026 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 2027 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 2028 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2029 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2030 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2031 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2032 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2033 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2034 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 2035 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2036 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2037 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 2038 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 2039 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 2040 // CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 2041 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 2042 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 2043 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]]) 2044 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2045 // CHECK3-NEXT: store i64 [[CALL]], i64* [[K]], align 8 2046 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 2047 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 2048 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 2049 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]] 2050 // CHECK3-NEXT: store i32 12, i32* [[LIN]], align 4 2051 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 2052 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2053 // CHECK3-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 2054 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2055 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4 2056 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4 2057 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 2058 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 2059 // CHECK3-NEXT: store i32 [[TMP15]], i32* [[A_CASTED2]], align 4 2060 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4 2061 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2062 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2063 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 2064 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2065 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 2066 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP20]], align 4 2067 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2068 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 2069 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2070 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 2071 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 2072 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2073 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2074 // CHECK3-NEXT: store i32 [[TMP14]], i32* [[TMP25]], align 4 2075 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2076 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 2077 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2078 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 2079 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[TMP28]], align 4 2080 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2081 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 2082 // CHECK3-NEXT: store i32 [[TMP16]], i32* [[TMP30]], align 4 2083 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2084 // CHECK3-NEXT: store i8* null, i8** [[TMP31]], align 4 2085 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2086 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2087 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2088 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 2089 // CHECK3-NEXT: store i32 1, i32* [[TMP34]], align 4 2090 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 2091 // CHECK3-NEXT: store i32 3, i32* [[TMP35]], align 4 2092 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 2093 // CHECK3-NEXT: store i8** [[TMP32]], i8*** [[TMP36]], align 4 2094 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 2095 // CHECK3-NEXT: store i8** [[TMP33]], i8*** [[TMP37]], align 4 2096 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 2097 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP38]], align 4 2098 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 2099 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP39]], align 4 2100 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 2101 // CHECK3-NEXT: store i8** null, i8*** [[TMP40]], align 4 2102 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 2103 // CHECK3-NEXT: store i8** null, i8*** [[TMP41]], align 4 2104 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 2105 // CHECK3-NEXT: store i64 0, i64* [[TMP42]], align 8 2106 // CHECK3-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 2107 // CHECK3-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 2108 // CHECK3-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2109 // CHECK3: omp_offload.failed: 2110 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]] 2111 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2112 // CHECK3: omp_offload.cont: 2113 // CHECK3-NEXT: [[TMP45:%.*]] = load i32, i32* [[A]], align 4 2114 // CHECK3-NEXT: store i32 [[TMP45]], i32* [[A_CASTED3]], align 4 2115 // CHECK3-NEXT: [[TMP46:%.*]] = load i32, i32* [[A_CASTED3]], align 4 2116 // CHECK3-NEXT: [[TMP47:%.*]] = load i16, i16* [[AA]], align 2 2117 // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 2118 // CHECK3-NEXT: store i16 [[TMP47]], i16* [[CONV5]], align 2 2119 // CHECK3-NEXT: [[TMP48:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 2120 // CHECK3-NEXT: [[TMP49:%.*]] = load i32, i32* [[N_ADDR]], align 4 2121 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP49]], 10 2122 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2123 // CHECK3: omp_if.then: 2124 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2125 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 2126 // CHECK3-NEXT: store i32 [[TMP46]], i32* [[TMP51]], align 4 2127 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2128 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 2129 // CHECK3-NEXT: store i32 [[TMP46]], i32* [[TMP53]], align 4 2130 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 2131 // CHECK3-NEXT: store i8* null, i8** [[TMP54]], align 4 2132 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 2133 // CHECK3-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* 2134 // CHECK3-NEXT: store i32 [[TMP48]], i32* [[TMP56]], align 4 2135 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 2136 // CHECK3-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* 2137 // CHECK3-NEXT: store i32 [[TMP48]], i32* [[TMP58]], align 4 2138 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 2139 // CHECK3-NEXT: store i8* null, i8** [[TMP59]], align 4 2140 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 2141 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 2142 // CHECK3-NEXT: [[KERNEL_ARGS9:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2143 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 0 2144 // CHECK3-NEXT: store i32 1, i32* [[TMP62]], align 4 2145 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 1 2146 // CHECK3-NEXT: store i32 2, i32* [[TMP63]], align 4 2147 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 2 2148 // CHECK3-NEXT: store i8** [[TMP60]], i8*** [[TMP64]], align 4 2149 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 3 2150 // CHECK3-NEXT: store i8** [[TMP61]], i8*** [[TMP65]], align 4 2151 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 4 2152 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP66]], align 4 2153 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 5 2154 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP67]], align 4 2155 // CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 6 2156 // CHECK3-NEXT: store i8** null, i8*** [[TMP68]], align 4 2157 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 7 2158 // CHECK3-NEXT: store i8** null, i8*** [[TMP69]], align 4 2159 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 8 2160 // CHECK3-NEXT: store i64 0, i64* [[TMP70]], align 8 2161 // CHECK3-NEXT: [[TMP71:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]]) 2162 // CHECK3-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0 2163 // CHECK3-NEXT: br i1 [[TMP72]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 2164 // CHECK3: omp_offload.failed10: 2165 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP46]], i32 [[TMP48]]) #[[ATTR4]] 2166 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT11]] 2167 // CHECK3: omp_offload.cont11: 2168 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2169 // CHECK3: omp_if.else: 2170 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP46]], i32 [[TMP48]]) #[[ATTR4]] 2171 // CHECK3-NEXT: br label [[OMP_IF_END]] 2172 // CHECK3: omp_if.end: 2173 // CHECK3-NEXT: [[TMP73:%.*]] = load i32, i32* [[A]], align 4 2174 // CHECK3-NEXT: store i32 [[TMP73]], i32* [[DOTCAPTURE_EXPR_]], align 4 2175 // CHECK3-NEXT: [[TMP74:%.*]] = load i32, i32* [[A]], align 4 2176 // CHECK3-NEXT: store i32 [[TMP74]], i32* [[A_CASTED12]], align 4 2177 // CHECK3-NEXT: [[TMP75:%.*]] = load i32, i32* [[A_CASTED12]], align 4 2178 // CHECK3-NEXT: [[TMP76:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 2179 // CHECK3-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2180 // CHECK3-NEXT: [[TMP77:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2181 // CHECK3-NEXT: [[TMP78:%.*]] = load i32, i32* [[N_ADDR]], align 4 2182 // CHECK3-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP78]], 20 2183 // CHECK3-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN14:%.*]], label [[OMP_IF_ELSE21:%.*]] 2184 // CHECK3: omp_if.then14: 2185 // CHECK3-NEXT: [[TMP79:%.*]] = mul nuw i32 [[TMP1]], 4 2186 // CHECK3-NEXT: [[TMP80:%.*]] = sext i32 [[TMP79]] to i64 2187 // CHECK3-NEXT: [[TMP81:%.*]] = mul nuw i32 5, [[TMP3]] 2188 // CHECK3-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP81]], 8 2189 // CHECK3-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 2190 // CHECK3-NEXT: [[TMP84:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2191 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP84]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 2192 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0 2193 // CHECK3-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* 2194 // CHECK3-NEXT: store i32 [[TMP75]], i32* [[TMP86]], align 4 2195 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0 2196 // CHECK3-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 2197 // CHECK3-NEXT: store i32 [[TMP75]], i32* [[TMP88]], align 4 2198 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 0 2199 // CHECK3-NEXT: store i8* null, i8** [[TMP89]], align 4 2200 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 1 2201 // CHECK3-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [10 x float]** 2202 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP91]], align 4 2203 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 1 2204 // CHECK3-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [10 x float]** 2205 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP93]], align 4 2206 // CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 1 2207 // CHECK3-NEXT: store i8* null, i8** [[TMP94]], align 4 2208 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 2 2209 // CHECK3-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* 2210 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP96]], align 4 2211 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 2 2212 // CHECK3-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* 2213 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP98]], align 4 2214 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 2 2215 // CHECK3-NEXT: store i8* null, i8** [[TMP99]], align 4 2216 // CHECK3-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 3 2217 // CHECK3-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to float** 2218 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP101]], align 4 2219 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 3 2220 // CHECK3-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to float** 2221 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP103]], align 4 2222 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2223 // CHECK3-NEXT: store i64 [[TMP80]], i64* [[TMP104]], align 4 2224 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 3 2225 // CHECK3-NEXT: store i8* null, i8** [[TMP105]], align 4 2226 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 4 2227 // CHECK3-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [5 x [10 x double]]** 2228 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP107]], align 4 2229 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 4 2230 // CHECK3-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to [5 x [10 x double]]** 2231 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP109]], align 4 2232 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 4 2233 // CHECK3-NEXT: store i8* null, i8** [[TMP110]], align 4 2234 // CHECK3-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 5 2235 // CHECK3-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* 2236 // CHECK3-NEXT: store i32 5, i32* [[TMP112]], align 4 2237 // CHECK3-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 5 2238 // CHECK3-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* 2239 // CHECK3-NEXT: store i32 5, i32* [[TMP114]], align 4 2240 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 5 2241 // CHECK3-NEXT: store i8* null, i8** [[TMP115]], align 4 2242 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 6 2243 // CHECK3-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 2244 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP117]], align 4 2245 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 6 2246 // CHECK3-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32* 2247 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP119]], align 4 2248 // CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 6 2249 // CHECK3-NEXT: store i8* null, i8** [[TMP120]], align 4 2250 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 7 2251 // CHECK3-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** 2252 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP122]], align 4 2253 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 7 2254 // CHECK3-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** 2255 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP124]], align 4 2256 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2257 // CHECK3-NEXT: store i64 [[TMP83]], i64* [[TMP125]], align 4 2258 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 7 2259 // CHECK3-NEXT: store i8* null, i8** [[TMP126]], align 4 2260 // CHECK3-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 8 2261 // CHECK3-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to %struct.TT** 2262 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP128]], align 4 2263 // CHECK3-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 8 2264 // CHECK3-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to %struct.TT** 2265 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP130]], align 4 2266 // CHECK3-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 8 2267 // CHECK3-NEXT: store i8* null, i8** [[TMP131]], align 4 2268 // CHECK3-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 9 2269 // CHECK3-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i32* 2270 // CHECK3-NEXT: store i32 [[TMP77]], i32* [[TMP133]], align 4 2271 // CHECK3-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 9 2272 // CHECK3-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32* 2273 // CHECK3-NEXT: store i32 [[TMP77]], i32* [[TMP135]], align 4 2274 // CHECK3-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 9 2275 // CHECK3-NEXT: store i8* null, i8** [[TMP136]], align 4 2276 // CHECK3-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0 2277 // CHECK3-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0 2278 // CHECK3-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2279 // CHECK3-NEXT: [[KERNEL_ARGS18:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 2280 // CHECK3-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 0 2281 // CHECK3-NEXT: store i32 1, i32* [[TMP140]], align 4 2282 // CHECK3-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 1 2283 // CHECK3-NEXT: store i32 10, i32* [[TMP141]], align 4 2284 // CHECK3-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 2 2285 // CHECK3-NEXT: store i8** [[TMP137]], i8*** [[TMP142]], align 4 2286 // CHECK3-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 3 2287 // CHECK3-NEXT: store i8** [[TMP138]], i8*** [[TMP143]], align 4 2288 // CHECK3-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 4 2289 // CHECK3-NEXT: store i64* [[TMP139]], i64** [[TMP144]], align 4 2290 // CHECK3-NEXT: [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 5 2291 // CHECK3-NEXT: store i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP145]], align 4 2292 // CHECK3-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 6 2293 // CHECK3-NEXT: store i8** null, i8*** [[TMP146]], align 4 2294 // CHECK3-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 7 2295 // CHECK3-NEXT: store i8** null, i8*** [[TMP147]], align 4 2296 // CHECK3-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 8 2297 // CHECK3-NEXT: store i64 0, i64* [[TMP148]], align 8 2298 // CHECK3-NEXT: [[TMP149:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]]) 2299 // CHECK3-NEXT: [[TMP150:%.*]] = icmp ne i32 [[TMP149]], 0 2300 // CHECK3-NEXT: br i1 [[TMP150]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 2301 // CHECK3: omp_offload.failed19: 2302 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP75]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP77]]) #[[ATTR4]] 2303 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT20]] 2304 // CHECK3: omp_offload.cont20: 2305 // CHECK3-NEXT: br label [[OMP_IF_END22:%.*]] 2306 // CHECK3: omp_if.else21: 2307 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP75]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP77]]) #[[ATTR4]] 2308 // CHECK3-NEXT: br label [[OMP_IF_END22]] 2309 // CHECK3: omp_if.end22: 2310 // CHECK3-NEXT: [[TMP151:%.*]] = load i32, i32* [[A]], align 4 2311 // CHECK3-NEXT: [[TMP152:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2312 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP152]]) 2313 // CHECK3-NEXT: ret i32 [[TMP151]] 2314 // 2315 // 2316 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 2317 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 2318 // CHECK3-NEXT: entry: 2319 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2320 // CHECK3-NEXT: ret void 2321 // 2322 // 2323 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2324 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 2325 // CHECK3-NEXT: entry: 2326 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2327 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2328 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2329 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2330 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2331 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2332 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2333 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2334 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2335 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2336 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2337 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2338 // CHECK3-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 2339 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2340 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2341 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2342 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2343 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2344 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2345 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 2346 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2347 // CHECK3: cond.true: 2348 // CHECK3-NEXT: br label [[COND_END:%.*]] 2349 // CHECK3: cond.false: 2350 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2351 // CHECK3-NEXT: br label [[COND_END]] 2352 // CHECK3: cond.end: 2353 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2354 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2355 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2356 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2357 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2358 // CHECK3: omp.inner.for.cond: 2359 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 2360 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 2361 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2362 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2363 // CHECK3: omp.inner.for.body: 2364 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2365 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 2366 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 2367 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 2368 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2369 // CHECK3: omp.body.continue: 2370 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2371 // CHECK3: omp.inner.for.inc: 2372 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2373 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 2374 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 2375 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2376 // CHECK3: omp.inner.for.end: 2377 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2378 // CHECK3: omp.loop.exit: 2379 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2380 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2381 // CHECK3-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 2382 // CHECK3-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2383 // CHECK3: .omp.final.then: 2384 // CHECK3-NEXT: store i32 33, i32* [[I]], align 4 2385 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2386 // CHECK3: .omp.final.done: 2387 // CHECK3-NEXT: ret void 2388 // 2389 // 2390 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2391 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2392 // CHECK3-NEXT: entry: 2393 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2394 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 2395 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 2396 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 2397 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 2398 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 2399 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2400 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2401 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 2402 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2403 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2404 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2405 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2406 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2407 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2408 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2409 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 2410 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2411 // CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2412 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 2413 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2414 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 2415 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 2416 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 2417 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 2418 // CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 2419 // CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 2420 // CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 2421 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 2422 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 2423 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0 2424 // CHECK3-NEXT: store i32 1, i32* [[TMP11]], align 4, !noalias !26 2425 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1 2426 // CHECK3-NEXT: store i32 0, i32* [[TMP12]], align 4, !noalias !26 2427 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2 2428 // CHECK3-NEXT: store i8** null, i8*** [[TMP13]], align 4, !noalias !26 2429 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3 2430 // CHECK3-NEXT: store i8** null, i8*** [[TMP14]], align 4, !noalias !26 2431 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4 2432 // CHECK3-NEXT: store i64* null, i64** [[TMP15]], align 4, !noalias !26 2433 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5 2434 // CHECK3-NEXT: store i64* null, i64** [[TMP16]], align 4, !noalias !26 2435 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6 2436 // CHECK3-NEXT: store i8** null, i8*** [[TMP17]], align 4, !noalias !26 2437 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7 2438 // CHECK3-NEXT: store i8** null, i8*** [[TMP18]], align 4, !noalias !26 2439 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8 2440 // CHECK3-NEXT: store i64 0, i64* [[TMP19]], align 8, !noalias !26 2441 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) 2442 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2443 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2444 // CHECK3: omp_offload.failed.i: 2445 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 2446 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2447 // CHECK3: .omp_outlined..1.exit: 2448 // CHECK3-NEXT: ret i32 0 2449 // 2450 // 2451 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 2452 // CHECK3-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2453 // CHECK3-NEXT: entry: 2454 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2455 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 2456 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2457 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2458 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 2459 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 2460 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2461 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2462 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2463 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 2464 // CHECK3-NEXT: ret void 2465 // 2466 // 2467 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2468 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 2469 // CHECK3-NEXT: entry: 2470 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2471 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2472 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2473 // CHECK3-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 2474 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2475 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2476 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 2477 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2478 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2479 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2480 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2481 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2482 // CHECK3-NEXT: [[K1:%.*]] = alloca i64, align 8 2483 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2484 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2485 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2486 // CHECK3-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 2487 // CHECK3-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 2488 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 2489 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 2490 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2491 // CHECK3-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 2492 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2493 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2494 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2495 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2496 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 2497 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 35, i32 0, i32 8, i32 1, i32 1) 2498 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2499 // CHECK3: omp.dispatch.cond: 2500 // CHECK3-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2501 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 2502 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2503 // CHECK3: omp.dispatch.body: 2504 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2505 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 2506 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2507 // CHECK3: omp.inner.for.cond: 2508 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 2509 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 2510 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 2511 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2512 // CHECK3: omp.inner.for.body: 2513 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2514 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 2515 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 2516 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 2517 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]] 2518 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2519 // CHECK3-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 2520 // CHECK3-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 2521 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 2522 // CHECK3-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group [[ACC_GRP27]] 2523 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 2524 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 2525 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 2526 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2527 // CHECK3: omp.body.continue: 2528 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2529 // CHECK3: omp.inner.for.inc: 2530 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2531 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 2532 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 2533 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 2534 // CHECK3: omp.inner.for.end: 2535 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2536 // CHECK3: omp.dispatch.inc: 2537 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2538 // CHECK3: omp.dispatch.end: 2539 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2540 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 2541 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2542 // CHECK3: .omp.final.then: 2543 // CHECK3-NEXT: store i32 1, i32* [[I]], align 4 2544 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2545 // CHECK3: .omp.final.done: 2546 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2547 // CHECK3-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 2548 // CHECK3-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2549 // CHECK3: .omp.linear.pu: 2550 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[K1]], align 8 2551 // CHECK3-NEXT: store i64 [[TMP17]], i64* [[TMP0]], align 8 2552 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2553 // CHECK3: .omp.linear.pu.done: 2554 // CHECK3-NEXT: ret void 2555 // 2556 // 2557 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 2558 // CHECK3-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 2559 // CHECK3-NEXT: entry: 2560 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2561 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2562 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2563 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2564 // CHECK3-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 2565 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2566 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2567 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 2568 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2569 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2570 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2571 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2572 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2573 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2574 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 2575 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 2576 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 2577 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 2578 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 2579 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 2580 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 2581 // CHECK3-NEXT: ret void 2582 // 2583 // 2584 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2585 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 2586 // CHECK3-NEXT: entry: 2587 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2588 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2589 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2590 // CHECK3-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 2591 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2592 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2593 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 2594 // CHECK3-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 2595 // CHECK3-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 2596 // CHECK3-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 2597 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2598 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2599 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2600 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2601 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 2602 // CHECK3-NEXT: [[LIN2:%.*]] = alloca i32, align 4 2603 // CHECK3-NEXT: [[A3:%.*]] = alloca i32, align 4 2604 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2605 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2606 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2607 // CHECK3-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 2608 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2609 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2610 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 2611 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 2612 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2613 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 2614 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 2615 // CHECK3-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 2616 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2617 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 2618 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2619 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2620 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2621 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 2622 // CHECK3-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 2623 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 2624 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2625 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 2626 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2627 // CHECK3: cond.true: 2628 // CHECK3-NEXT: br label [[COND_END:%.*]] 2629 // CHECK3: cond.false: 2630 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2631 // CHECK3-NEXT: br label [[COND_END]] 2632 // CHECK3: cond.end: 2633 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 2634 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2635 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2636 // CHECK3-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 2637 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2638 // CHECK3: omp.inner.for.cond: 2639 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 2640 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 2641 // CHECK3-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 2642 // CHECK3-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2643 // CHECK3: omp.inner.for.body: 2644 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2645 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 2646 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 2647 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP30]] 2648 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]] 2649 // CHECK3-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 2650 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2651 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 2652 // CHECK3-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 2653 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 2654 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 2655 // CHECK3-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]] 2656 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]] 2657 // CHECK3-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 2658 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2659 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 2660 // CHECK3-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 2661 // CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 2662 // CHECK3-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 2663 // CHECK3-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group [[ACC_GRP30]] 2664 // CHECK3-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP30]] 2665 // CHECK3-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 2666 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 2667 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 2668 // CHECK3-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP30]] 2669 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2670 // CHECK3: omp.body.continue: 2671 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2672 // CHECK3: omp.inner.for.inc: 2673 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2674 // CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 2675 // CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 2676 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 2677 // CHECK3: omp.inner.for.end: 2678 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2679 // CHECK3: omp.loop.exit: 2680 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 2681 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2682 // CHECK3-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 2683 // CHECK3-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2684 // CHECK3: .omp.final.then: 2685 // CHECK3-NEXT: store i64 400, i64* [[IT]], align 8 2686 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2687 // CHECK3: .omp.final.done: 2688 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2689 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2690 // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 2691 // CHECK3: .omp.linear.pu: 2692 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 2693 // CHECK3-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 2694 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 2695 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 2696 // CHECK3-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 2697 // CHECK3: .omp.linear.pu.done: 2698 // CHECK3-NEXT: ret void 2699 // 2700 // 2701 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 2702 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2703 // CHECK3-NEXT: entry: 2704 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2705 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2706 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2707 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2708 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2709 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2710 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2711 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2712 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2713 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2714 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2715 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2716 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2717 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2718 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2719 // CHECK3-NEXT: ret void 2720 // 2721 // 2722 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 2723 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 2724 // CHECK3-NEXT: entry: 2725 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2726 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2727 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2728 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2729 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2730 // CHECK3-NEXT: [[TMP:%.*]] = alloca i16, align 2 2731 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2732 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2733 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2734 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2735 // CHECK3-NEXT: [[IT:%.*]] = alloca i16, align 2 2736 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2737 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2738 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2739 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2740 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2741 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2742 // CHECK3-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 2743 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2744 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2745 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2746 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 2747 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2748 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2749 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 2750 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2751 // CHECK3: cond.true: 2752 // CHECK3-NEXT: br label [[COND_END:%.*]] 2753 // CHECK3: cond.false: 2754 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2755 // CHECK3-NEXT: br label [[COND_END]] 2756 // CHECK3: cond.end: 2757 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 2758 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2759 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2760 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 2761 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2762 // CHECK3: omp.inner.for.cond: 2763 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 2764 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 2765 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 2766 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2767 // CHECK3: omp.inner.for.body: 2768 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2769 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 2770 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 2771 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2772 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group [[ACC_GRP33]] 2773 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 2774 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 2775 // CHECK3-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 2776 // CHECK3-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP33]] 2777 // CHECK3-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 2778 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 2779 // CHECK3-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 2780 // CHECK3-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP33]] 2781 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2782 // CHECK3: omp.body.continue: 2783 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2784 // CHECK3: omp.inner.for.inc: 2785 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2786 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 2787 // CHECK3-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 2788 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 2789 // CHECK3: omp.inner.for.end: 2790 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2791 // CHECK3: omp.loop.exit: 2792 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 2793 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2794 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2795 // CHECK3-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2796 // CHECK3: .omp.final.then: 2797 // CHECK3-NEXT: store i16 22, i16* [[IT]], align 2 2798 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2799 // CHECK3: .omp.final.done: 2800 // CHECK3-NEXT: ret void 2801 // 2802 // 2803 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 2804 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 2805 // CHECK3-NEXT: entry: 2806 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2807 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2808 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2809 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2810 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2811 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2812 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2813 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2814 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2815 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2816 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2817 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 2818 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2819 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2820 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2821 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2822 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2823 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2824 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2825 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2826 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2827 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2828 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2829 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2830 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2831 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2832 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2833 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2834 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2835 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2836 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2837 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2838 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2839 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2840 // CHECK3-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2841 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 2842 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 2843 // CHECK3-NEXT: ret void 2844 // 2845 // 2846 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 2847 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 2848 // CHECK3-NEXT: entry: 2849 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2850 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2851 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2852 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2853 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2854 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2855 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2856 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2857 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2858 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2859 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2860 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 2861 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2862 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 2863 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2864 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2865 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2866 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2867 // CHECK3-NEXT: [[IT:%.*]] = alloca i8, align 1 2868 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2869 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2870 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2871 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2872 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2873 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2874 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2875 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2876 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2877 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2878 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2879 // CHECK3-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2880 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2881 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2882 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2883 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2884 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2885 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2886 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2887 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2888 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2889 // CHECK3-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 2890 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2891 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2892 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 2893 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2894 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2895 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 2896 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2897 // CHECK3: omp.dispatch.cond: 2898 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2899 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 2900 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2901 // CHECK3: cond.true: 2902 // CHECK3-NEXT: br label [[COND_END:%.*]] 2903 // CHECK3: cond.false: 2904 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2905 // CHECK3-NEXT: br label [[COND_END]] 2906 // CHECK3: cond.end: 2907 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2908 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2909 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2910 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2911 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2912 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2913 // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2914 // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2915 // CHECK3: omp.dispatch.body: 2916 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2917 // CHECK3: omp.inner.for.cond: 2918 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 2919 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 2920 // CHECK3-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 2921 // CHECK3-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2922 // CHECK3: omp.inner.for.body: 2923 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2924 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 2925 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 2926 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 2927 // CHECK3-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group [[ACC_GRP36]] 2928 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 2929 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 2930 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 2931 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2932 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 2933 // CHECK3-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 2934 // CHECK3-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 2935 // CHECK3-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 2936 // CHECK3-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 2937 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2938 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 2939 // CHECK3-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 2940 // CHECK3-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 2941 // CHECK3-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 2942 // CHECK3-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 2943 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2944 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 2945 // CHECK3-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 2946 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 2947 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 2948 // CHECK3-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 2949 // CHECK3-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 2950 // CHECK3-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 2951 // CHECK3-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 2952 // CHECK3-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 2953 // CHECK3-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 2954 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2955 // CHECK3-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 2956 // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 2957 // CHECK3-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 2958 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2959 // CHECK3-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 2960 // CHECK3-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 2961 // CHECK3-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 2962 // CHECK3-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 2963 // CHECK3-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 2964 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2965 // CHECK3: omp.body.continue: 2966 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2967 // CHECK3: omp.inner.for.inc: 2968 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2969 // CHECK3-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 2970 // CHECK3-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 2971 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 2972 // CHECK3: omp.inner.for.end: 2973 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2974 // CHECK3: omp.dispatch.inc: 2975 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2976 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2977 // CHECK3-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 2978 // CHECK3-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 2979 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2980 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2981 // CHECK3-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 2982 // CHECK3-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 2983 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2984 // CHECK3: omp.dispatch.end: 2985 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 2986 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 2987 // CHECK3-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 2988 // CHECK3-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 2989 // CHECK3: .omp.final.then: 2990 // CHECK3-NEXT: store i8 96, i8* [[IT]], align 1 2991 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 2992 // CHECK3: .omp.final.done: 2993 // CHECK3-NEXT: ret void 2994 // 2995 // 2996 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2997 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2998 // CHECK3-NEXT: entry: 2999 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3000 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3001 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3002 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3003 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3004 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3005 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 3006 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3007 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3008 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3009 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3010 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 3011 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3012 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3013 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3014 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3015 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 3016 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3017 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3018 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3019 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3020 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 3021 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3022 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 3023 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 3024 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 3025 // CHECK3-NEXT: ret i32 [[TMP8]] 3026 // 3027 // 3028 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3029 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3030 // CHECK3-NEXT: entry: 3031 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3032 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3033 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 3034 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3035 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3036 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3037 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 3038 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 3039 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 3040 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 3041 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3042 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3043 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3044 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3045 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3046 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 3047 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3048 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3049 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3050 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 3051 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 3052 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3053 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 3054 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3055 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3056 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3057 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3058 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3059 // CHECK3: omp_if.then: 3060 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3061 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3062 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3063 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3064 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3065 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 3066 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3067 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 3068 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 3069 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3070 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 3071 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 3072 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3073 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 3074 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3075 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 3076 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 3077 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3078 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 3079 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 3080 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3081 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 3082 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3083 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 3084 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 3085 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3086 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 3087 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 3088 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3089 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 3090 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3091 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3092 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 3093 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3094 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 3095 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 3096 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3097 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 3098 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3099 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 3100 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 3101 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3102 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 3103 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 3104 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3105 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 3106 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3107 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 3108 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3109 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3110 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3111 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3112 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 3113 // CHECK3-NEXT: store i32 1, i32* [[TMP40]], align 4 3114 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 3115 // CHECK3-NEXT: store i32 5, i32* [[TMP41]], align 4 3116 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 3117 // CHECK3-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4 3118 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 3119 // CHECK3-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 4 3120 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 3121 // CHECK3-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 4 3122 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 3123 // CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP45]], align 4 3124 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 3125 // CHECK3-NEXT: store i8** null, i8*** [[TMP46]], align 4 3126 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 3127 // CHECK3-NEXT: store i8** null, i8*** [[TMP47]], align 4 3128 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 3129 // CHECK3-NEXT: store i64 0, i64* [[TMP48]], align 8 3130 // CHECK3-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 3131 // CHECK3-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 3132 // CHECK3-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3133 // CHECK3: omp_offload.failed: 3134 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 3135 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3136 // CHECK3: omp_offload.cont: 3137 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3138 // CHECK3: omp_if.else: 3139 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 3140 // CHECK3-NEXT: br label [[OMP_IF_END]] 3141 // CHECK3: omp_if.end: 3142 // CHECK3-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP1]] 3143 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP51]] 3144 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3145 // CHECK3-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 3146 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP52]] to i32 3147 // CHECK3-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4 3148 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP53]] 3149 // CHECK3-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3150 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP54]]) 3151 // CHECK3-NEXT: ret i32 [[ADD3]] 3152 // 3153 // 3154 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 3155 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3156 // CHECK3-NEXT: entry: 3157 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3158 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3159 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3160 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 3161 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3162 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3163 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3164 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3165 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 3166 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 3167 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 3168 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3169 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3170 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3171 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 3172 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3173 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3174 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3175 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3176 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3177 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3178 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3179 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 3180 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3181 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 3182 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3183 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3184 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3185 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3186 // CHECK3: omp_if.then: 3187 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3188 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3189 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3190 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3191 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3192 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3193 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3194 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 3195 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3196 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3197 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3198 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3199 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 3200 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 3201 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3202 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 3203 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3204 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 3205 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 3206 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3207 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 3208 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 3209 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3210 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 3211 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3212 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 3213 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 3214 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3215 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 3216 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 3217 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3218 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 3219 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3220 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3221 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3222 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 3223 // CHECK3-NEXT: store i32 1, i32* [[TMP29]], align 4 3224 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 3225 // CHECK3-NEXT: store i32 4, i32* [[TMP30]], align 4 3226 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 3227 // CHECK3-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4 3228 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 3229 // CHECK3-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 4 3230 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 3231 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 4 3232 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 3233 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 4 3234 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 3235 // CHECK3-NEXT: store i8** null, i8*** [[TMP35]], align 4 3236 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 3237 // CHECK3-NEXT: store i8** null, i8*** [[TMP36]], align 4 3238 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 3239 // CHECK3-NEXT: store i64 0, i64* [[TMP37]], align 8 3240 // CHECK3-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 3241 // CHECK3-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 3242 // CHECK3-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3243 // CHECK3: omp_offload.failed: 3244 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3245 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3246 // CHECK3: omp_offload.cont: 3247 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3248 // CHECK3: omp_if.else: 3249 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3250 // CHECK3-NEXT: br label [[OMP_IF_END]] 3251 // CHECK3: omp_if.end: 3252 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 3253 // CHECK3-NEXT: ret i32 [[TMP40]] 3254 // 3255 // 3256 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3257 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3258 // CHECK3-NEXT: entry: 3259 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3260 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3261 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3262 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3263 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3264 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3265 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3266 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3267 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3268 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3269 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3270 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3271 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3272 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3273 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3274 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3275 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3276 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3277 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3278 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3279 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3280 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3281 // CHECK3: omp_if.then: 3282 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3283 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 3284 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 3285 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3286 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3287 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3288 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3289 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 3290 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3291 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 3292 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 3293 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3294 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3295 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3296 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3297 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 3298 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3299 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3300 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 3301 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3302 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3303 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 3304 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3305 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3306 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3307 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3308 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3309 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 3310 // CHECK3-NEXT: store i32 1, i32* [[TMP22]], align 4 3311 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 3312 // CHECK3-NEXT: store i32 3, i32* [[TMP23]], align 4 3313 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 3314 // CHECK3-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4 3315 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 3316 // CHECK3-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 4 3317 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 3318 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 4 3319 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 3320 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 4 3321 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 3322 // CHECK3-NEXT: store i8** null, i8*** [[TMP28]], align 4 3323 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 3324 // CHECK3-NEXT: store i8** null, i8*** [[TMP29]], align 4 3325 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 3326 // CHECK3-NEXT: store i64 0, i64* [[TMP30]], align 8 3327 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 3328 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 3329 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3330 // CHECK3: omp_offload.failed: 3331 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3332 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3333 // CHECK3: omp_offload.cont: 3334 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3335 // CHECK3: omp_if.else: 3336 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3337 // CHECK3-NEXT: br label [[OMP_IF_END]] 3338 // CHECK3: omp_if.end: 3339 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4 3340 // CHECK3-NEXT: ret i32 [[TMP33]] 3341 // 3342 // 3343 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 3344 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3345 // CHECK3-NEXT: entry: 3346 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3347 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3348 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3349 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3350 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3351 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3352 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3353 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3354 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3355 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3356 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3357 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3358 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3359 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3360 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3361 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3362 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3363 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3364 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3365 // CHECK3-NEXT: ret void 3366 // 3367 // 3368 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 3369 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3370 // CHECK3-NEXT: entry: 3371 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3372 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3373 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3374 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3375 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3376 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3377 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3378 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3379 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3380 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3381 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3382 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3383 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3384 // CHECK3-NEXT: [[IT:%.*]] = alloca i64, align 8 3385 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3386 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3387 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3388 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3389 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3390 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3391 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3392 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3393 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3394 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3395 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3396 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3397 // CHECK3-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 3398 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3399 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3400 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3401 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3402 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3403 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3404 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 3405 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3406 // CHECK3: cond.true: 3407 // CHECK3-NEXT: br label [[COND_END:%.*]] 3408 // CHECK3: cond.false: 3409 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3410 // CHECK3-NEXT: br label [[COND_END]] 3411 // CHECK3: cond.end: 3412 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3413 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3414 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3415 // CHECK3-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 3416 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3417 // CHECK3: omp.inner.for.cond: 3418 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]] 3419 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]] 3420 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 3421 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3422 // CHECK3: omp.inner.for.body: 3423 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3424 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 3425 // CHECK3-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 3426 // CHECK3-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP39]] 3427 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] 3428 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 3429 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3430 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3431 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4, !llvm.access.group [[ACC_GRP39]] 3432 // CHECK3-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3433 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group [[ACC_GRP39]] 3434 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 3435 // CHECK3-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group [[ACC_GRP39]] 3436 // CHECK3-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 3437 // CHECK3-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 3438 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 3439 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3440 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP39]] 3441 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3442 // CHECK3: omp.body.continue: 3443 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3444 // CHECK3: omp.inner.for.inc: 3445 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3446 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 3447 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 3448 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 3449 // CHECK3: omp.inner.for.end: 3450 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3451 // CHECK3: omp.loop.exit: 3452 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3453 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3454 // CHECK3-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 3455 // CHECK3-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3456 // CHECK3: .omp.final.then: 3457 // CHECK3-NEXT: store i64 400, i64* [[IT]], align 8 3458 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3459 // CHECK3: .omp.final.done: 3460 // CHECK3-NEXT: ret void 3461 // 3462 // 3463 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 3464 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3465 // CHECK3-NEXT: entry: 3466 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3467 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3468 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3469 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3470 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3471 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3472 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3473 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3474 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3475 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3476 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3477 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3478 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3479 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3480 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3481 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3482 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3483 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3484 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3485 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 3486 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3487 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 3488 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3489 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 3490 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3491 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 3492 // CHECK3-NEXT: ret void 3493 // 3494 // 3495 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 3496 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3497 // CHECK3-NEXT: entry: 3498 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3499 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3500 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3501 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3502 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3503 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3504 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3505 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3506 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3507 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3508 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3509 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3510 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3511 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3512 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3513 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3514 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3515 // CHECK3-NEXT: ret void 3516 // 3517 // 3518 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 3519 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3520 // CHECK3-NEXT: entry: 3521 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3522 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3523 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3524 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3525 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3526 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3527 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3528 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3529 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3530 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3531 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3532 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3533 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3534 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3535 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3536 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3537 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3538 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3539 // CHECK3-NEXT: ret void 3540 // 3541 // 3542 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 3543 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3544 // CHECK3-NEXT: entry: 3545 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3546 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3547 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3548 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3549 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3550 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3551 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 4 3552 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3553 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3554 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3555 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3556 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 3557 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3558 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3559 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3560 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3561 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3562 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3563 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3564 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3565 // CHECK3-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 3566 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3567 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3568 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3569 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3570 // CHECK3-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 3571 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3572 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 3573 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3574 // CHECK3: cond.true: 3575 // CHECK3-NEXT: br label [[COND_END:%.*]] 3576 // CHECK3: cond.false: 3577 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3578 // CHECK3-NEXT: br label [[COND_END]] 3579 // CHECK3: cond.end: 3580 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 3581 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3582 // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3583 // CHECK3-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 3584 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3585 // CHECK3: omp.inner.for.cond: 3586 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42:![0-9]+]] 3587 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP42]] 3588 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 3589 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3590 // CHECK3: omp.inner.for.body: 3591 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3592 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 3593 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 3594 // CHECK3-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP42]] 3595 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] 3596 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 3597 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP42]] 3598 // CHECK3-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP42]] 3599 // CHECK3-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 3600 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 3601 // CHECK3-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 3602 // CHECK3-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP42]] 3603 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3604 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] 3605 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 3606 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP42]] 3607 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3608 // CHECK3: omp.body.continue: 3609 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3610 // CHECK3: omp.inner.for.inc: 3611 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3612 // CHECK3-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 3613 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP42]] 3614 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP43:![0-9]+]] 3615 // CHECK3: omp.inner.for.end: 3616 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3617 // CHECK3: omp.loop.exit: 3618 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 3619 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 3620 // CHECK3-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 3621 // CHECK3-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 3622 // CHECK3: .omp.final.then: 3623 // CHECK3-NEXT: store i64 11, i64* [[I]], align 8 3624 // CHECK3-NEXT: br label [[DOTOMP_FINAL_DONE]] 3625 // CHECK3: .omp.final.done: 3626 // CHECK3-NEXT: ret void 3627 // 3628 // 3629 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3630 // CHECK3-SAME: () #[[ATTR8:[0-9]+]] { 3631 // CHECK3-NEXT: entry: 3632 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3633 // CHECK3-NEXT: ret void 3634 // 3635 // 3636 // CHECK5-LABEL: define {{[^@]+}}@_Z7get_valv 3637 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] { 3638 // CHECK5-NEXT: entry: 3639 // CHECK5-NEXT: ret i64 0 3640 // 3641 // 3642 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi 3643 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 3644 // CHECK5-NEXT: entry: 3645 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3646 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 3647 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 3648 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3649 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3650 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3651 // CHECK5-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3652 // CHECK5-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 3653 // CHECK5-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 3654 // CHECK5-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 3655 // CHECK5-NEXT: [[K:%.*]] = alloca i64, align 8 3656 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 3657 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 3658 // CHECK5-NEXT: [[LIN:%.*]] = alloca i32, align 4 3659 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 3660 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 3661 // CHECK5-NEXT: [[A_CASTED4:%.*]] = alloca i64, align 8 3662 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 3663 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 3664 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 3665 // CHECK5-NEXT: [[A_CASTED6:%.*]] = alloca i64, align 8 3666 // CHECK5-NEXT: [[AA_CASTED8:%.*]] = alloca i64, align 8 3667 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS10:%.*]] = alloca [2 x i8*], align 8 3668 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS11:%.*]] = alloca [2 x i8*], align 8 3669 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS12:%.*]] = alloca [2 x i8*], align 8 3670 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 3671 // CHECK5-NEXT: [[A_CASTED16:%.*]] = alloca i64, align 8 3672 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3673 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS21:%.*]] = alloca [10 x i8*], align 8 3674 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS22:%.*]] = alloca [10 x i8*], align 8 3675 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS23:%.*]] = alloca [10 x i8*], align 8 3676 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 8 3677 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 3678 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3679 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 3680 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 3681 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3682 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 3683 // CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 3684 // CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 3685 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 3686 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 3687 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3688 // CHECK5-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 3689 // CHECK5-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 3690 // CHECK5-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 3691 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 3692 // CHECK5-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 3693 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 3694 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 3695 // CHECK5-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP7]]) 3696 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 3697 // CHECK5-NEXT: store i64 [[CALL]], i64* [[K]], align 8 3698 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 3699 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 3700 // CHECK5-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 3701 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 3702 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[K]], align 8 3703 // CHECK5-NEXT: store i64 [[TMP13]], i64* [[K_CASTED]], align 8 3704 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[K_CASTED]], align 8 3705 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i64 [[TMP12]], i64 [[TMP14]]) #[[ATTR4:[0-9]+]] 3706 // CHECK5-NEXT: store i32 12, i32* [[LIN]], align 4 3707 // CHECK5-NEXT: [[TMP15:%.*]] = load i16, i16* [[AA]], align 2 3708 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 3709 // CHECK5-NEXT: store i16 [[TMP15]], i16* [[CONV2]], align 2 3710 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[AA_CASTED]], align 8 3711 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[LIN]], align 4 3712 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 3713 // CHECK5-NEXT: store i32 [[TMP17]], i32* [[CONV3]], align 4 3714 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 3715 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[A]], align 4 3716 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED4]] to i32* 3717 // CHECK5-NEXT: store i32 [[TMP19]], i32* [[CONV5]], align 4 3718 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[A_CASTED4]], align 8 3719 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3720 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 3721 // CHECK5-NEXT: store i64 [[TMP16]], i64* [[TMP22]], align 8 3722 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3723 // CHECK5-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 3724 // CHECK5-NEXT: store i64 [[TMP16]], i64* [[TMP24]], align 8 3725 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 3726 // CHECK5-NEXT: store i8* null, i8** [[TMP25]], align 8 3727 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3728 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 3729 // CHECK5-NEXT: store i64 [[TMP18]], i64* [[TMP27]], align 8 3730 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3731 // CHECK5-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 3732 // CHECK5-NEXT: store i64 [[TMP18]], i64* [[TMP29]], align 8 3733 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 3734 // CHECK5-NEXT: store i8* null, i8** [[TMP30]], align 8 3735 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3736 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 3737 // CHECK5-NEXT: store i64 [[TMP20]], i64* [[TMP32]], align 8 3738 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3739 // CHECK5-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i64* 3740 // CHECK5-NEXT: store i64 [[TMP20]], i64* [[TMP34]], align 8 3741 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 3742 // CHECK5-NEXT: store i8* null, i8** [[TMP35]], align 8 3743 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3744 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3745 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 3746 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 3747 // CHECK5-NEXT: store i32 1, i32* [[TMP38]], align 4 3748 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 3749 // CHECK5-NEXT: store i32 3, i32* [[TMP39]], align 4 3750 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 3751 // CHECK5-NEXT: store i8** [[TMP36]], i8*** [[TMP40]], align 8 3752 // CHECK5-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 3753 // CHECK5-NEXT: store i8** [[TMP37]], i8*** [[TMP41]], align 8 3754 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 3755 // CHECK5-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP42]], align 8 3756 // CHECK5-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 3757 // CHECK5-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP43]], align 8 3758 // CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 3759 // CHECK5-NEXT: store i8** null, i8*** [[TMP44]], align 8 3760 // CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 3761 // CHECK5-NEXT: store i8** null, i8*** [[TMP45]], align 8 3762 // CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 3763 // CHECK5-NEXT: store i64 0, i64* [[TMP46]], align 8 3764 // CHECK5-NEXT: [[TMP47:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 3765 // CHECK5-NEXT: [[TMP48:%.*]] = icmp ne i32 [[TMP47]], 0 3766 // CHECK5-NEXT: br i1 [[TMP48]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3767 // CHECK5: omp_offload.failed: 3768 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i64 [[TMP16]], i64 [[TMP18]], i64 [[TMP20]]) #[[ATTR4]] 3769 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 3770 // CHECK5: omp_offload.cont: 3771 // CHECK5-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4 3772 // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[A_CASTED6]] to i32* 3773 // CHECK5-NEXT: store i32 [[TMP49]], i32* [[CONV7]], align 4 3774 // CHECK5-NEXT: [[TMP50:%.*]] = load i64, i64* [[A_CASTED6]], align 8 3775 // CHECK5-NEXT: [[TMP51:%.*]] = load i16, i16* [[AA]], align 2 3776 // CHECK5-NEXT: [[CONV9:%.*]] = bitcast i64* [[AA_CASTED8]] to i16* 3777 // CHECK5-NEXT: store i16 [[TMP51]], i16* [[CONV9]], align 2 3778 // CHECK5-NEXT: [[TMP52:%.*]] = load i64, i64* [[AA_CASTED8]], align 8 3779 // CHECK5-NEXT: [[TMP53:%.*]] = load i32, i32* [[N_ADDR]], align 4 3780 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP53]], 10 3781 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3782 // CHECK5: omp_if.then: 3783 // CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 3784 // CHECK5-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i64* 3785 // CHECK5-NEXT: store i64 [[TMP50]], i64* [[TMP55]], align 8 3786 // CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 3787 // CHECK5-NEXT: [[TMP57:%.*]] = bitcast i8** [[TMP56]] to i64* 3788 // CHECK5-NEXT: store i64 [[TMP50]], i64* [[TMP57]], align 8 3789 // CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 0 3790 // CHECK5-NEXT: store i8* null, i8** [[TMP58]], align 8 3791 // CHECK5-NEXT: [[TMP59:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 1 3792 // CHECK5-NEXT: [[TMP60:%.*]] = bitcast i8** [[TMP59]] to i64* 3793 // CHECK5-NEXT: store i64 [[TMP52]], i64* [[TMP60]], align 8 3794 // CHECK5-NEXT: [[TMP61:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 1 3795 // CHECK5-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 3796 // CHECK5-NEXT: store i64 [[TMP52]], i64* [[TMP62]], align 8 3797 // CHECK5-NEXT: [[TMP63:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS12]], i64 0, i64 1 3798 // CHECK5-NEXT: store i8* null, i8** [[TMP63]], align 8 3799 // CHECK5-NEXT: [[TMP64:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS10]], i32 0, i32 0 3800 // CHECK5-NEXT: [[TMP65:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS11]], i32 0, i32 0 3801 // CHECK5-NEXT: [[KERNEL_ARGS13:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 3802 // CHECK5-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 0 3803 // CHECK5-NEXT: store i32 1, i32* [[TMP66]], align 4 3804 // CHECK5-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 1 3805 // CHECK5-NEXT: store i32 2, i32* [[TMP67]], align 4 3806 // CHECK5-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 2 3807 // CHECK5-NEXT: store i8** [[TMP64]], i8*** [[TMP68]], align 8 3808 // CHECK5-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 3 3809 // CHECK5-NEXT: store i8** [[TMP65]], i8*** [[TMP69]], align 8 3810 // CHECK5-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 4 3811 // CHECK5-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP70]], align 8 3812 // CHECK5-NEXT: [[TMP71:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 5 3813 // CHECK5-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP71]], align 8 3814 // CHECK5-NEXT: [[TMP72:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 6 3815 // CHECK5-NEXT: store i8** null, i8*** [[TMP72]], align 8 3816 // CHECK5-NEXT: [[TMP73:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 7 3817 // CHECK5-NEXT: store i8** null, i8*** [[TMP73]], align 8 3818 // CHECK5-NEXT: [[TMP74:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]], i32 0, i32 8 3819 // CHECK5-NEXT: store i64 0, i64* [[TMP74]], align 8 3820 // CHECK5-NEXT: [[TMP75:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS13]]) 3821 // CHECK5-NEXT: [[TMP76:%.*]] = icmp ne i32 [[TMP75]], 0 3822 // CHECK5-NEXT: br i1 [[TMP76]], label [[OMP_OFFLOAD_FAILED14:%.*]], label [[OMP_OFFLOAD_CONT15:%.*]] 3823 // CHECK5: omp_offload.failed14: 3824 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP50]], i64 [[TMP52]]) #[[ATTR4]] 3825 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT15]] 3826 // CHECK5: omp_offload.cont15: 3827 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 3828 // CHECK5: omp_if.else: 3829 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i64 [[TMP50]], i64 [[TMP52]]) #[[ATTR4]] 3830 // CHECK5-NEXT: br label [[OMP_IF_END]] 3831 // CHECK5: omp_if.end: 3832 // CHECK5-NEXT: [[TMP77:%.*]] = load i32, i32* [[A]], align 4 3833 // CHECK5-NEXT: store i32 [[TMP77]], i32* [[DOTCAPTURE_EXPR_]], align 4 3834 // CHECK5-NEXT: [[TMP78:%.*]] = load i32, i32* [[A]], align 4 3835 // CHECK5-NEXT: [[CONV17:%.*]] = bitcast i64* [[A_CASTED16]] to i32* 3836 // CHECK5-NEXT: store i32 [[TMP78]], i32* [[CONV17]], align 4 3837 // CHECK5-NEXT: [[TMP79:%.*]] = load i64, i64* [[A_CASTED16]], align 8 3838 // CHECK5-NEXT: [[TMP80:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 3839 // CHECK5-NEXT: [[CONV18:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 3840 // CHECK5-NEXT: store i32 [[TMP80]], i32* [[CONV18]], align 4 3841 // CHECK5-NEXT: [[TMP81:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3842 // CHECK5-NEXT: [[TMP82:%.*]] = load i32, i32* [[N_ADDR]], align 4 3843 // CHECK5-NEXT: [[CMP19:%.*]] = icmp sgt i32 [[TMP82]], 20 3844 // CHECK5-NEXT: br i1 [[CMP19]], label [[OMP_IF_THEN20:%.*]], label [[OMP_IF_ELSE27:%.*]] 3845 // CHECK5: omp_if.then20: 3846 // CHECK5-NEXT: [[TMP83:%.*]] = mul nuw i64 [[TMP2]], 4 3847 // CHECK5-NEXT: [[TMP84:%.*]] = mul nuw i64 5, [[TMP5]] 3848 // CHECK5-NEXT: [[TMP85:%.*]] = mul nuw i64 [[TMP84]], 8 3849 // CHECK5-NEXT: [[TMP86:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3850 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP86]], i8* align 8 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i64 80, i1 false) 3851 // CHECK5-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 3852 // CHECK5-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* 3853 // CHECK5-NEXT: store i64 [[TMP79]], i64* [[TMP88]], align 8 3854 // CHECK5-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 3855 // CHECK5-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to i64* 3856 // CHECK5-NEXT: store i64 [[TMP79]], i64* [[TMP90]], align 8 3857 // CHECK5-NEXT: [[TMP91:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 0 3858 // CHECK5-NEXT: store i8* null, i8** [[TMP91]], align 8 3859 // CHECK5-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 1 3860 // CHECK5-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [10 x float]** 3861 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP93]], align 8 3862 // CHECK5-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 1 3863 // CHECK5-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to [10 x float]** 3864 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP95]], align 8 3865 // CHECK5-NEXT: [[TMP96:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 1 3866 // CHECK5-NEXT: store i8* null, i8** [[TMP96]], align 8 3867 // CHECK5-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 2 3868 // CHECK5-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i64* 3869 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP98]], align 8 3870 // CHECK5-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 2 3871 // CHECK5-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i64* 3872 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP100]], align 8 3873 // CHECK5-NEXT: [[TMP101:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 2 3874 // CHECK5-NEXT: store i8* null, i8** [[TMP101]], align 8 3875 // CHECK5-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 3 3876 // CHECK5-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to float** 3877 // CHECK5-NEXT: store float* [[VLA]], float** [[TMP103]], align 8 3878 // CHECK5-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 3 3879 // CHECK5-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to float** 3880 // CHECK5-NEXT: store float* [[VLA]], float** [[TMP105]], align 8 3881 // CHECK5-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3882 // CHECK5-NEXT: store i64 [[TMP83]], i64* [[TMP106]], align 8 3883 // CHECK5-NEXT: [[TMP107:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 3 3884 // CHECK5-NEXT: store i8* null, i8** [[TMP107]], align 8 3885 // CHECK5-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 4 3886 // CHECK5-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to [5 x [10 x double]]** 3887 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP109]], align 8 3888 // CHECK5-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 4 3889 // CHECK5-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to [5 x [10 x double]]** 3890 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP111]], align 8 3891 // CHECK5-NEXT: [[TMP112:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 4 3892 // CHECK5-NEXT: store i8* null, i8** [[TMP112]], align 8 3893 // CHECK5-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 5 3894 // CHECK5-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i64* 3895 // CHECK5-NEXT: store i64 5, i64* [[TMP114]], align 8 3896 // CHECK5-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 5 3897 // CHECK5-NEXT: [[TMP116:%.*]] = bitcast i8** [[TMP115]] to i64* 3898 // CHECK5-NEXT: store i64 5, i64* [[TMP116]], align 8 3899 // CHECK5-NEXT: [[TMP117:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 5 3900 // CHECK5-NEXT: store i8* null, i8** [[TMP117]], align 8 3901 // CHECK5-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 6 3902 // CHECK5-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i64* 3903 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP119]], align 8 3904 // CHECK5-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 6 3905 // CHECK5-NEXT: [[TMP121:%.*]] = bitcast i8** [[TMP120]] to i64* 3906 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP121]], align 8 3907 // CHECK5-NEXT: [[TMP122:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 6 3908 // CHECK5-NEXT: store i8* null, i8** [[TMP122]], align 8 3909 // CHECK5-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 7 3910 // CHECK5-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** 3911 // CHECK5-NEXT: store double* [[VLA1]], double** [[TMP124]], align 8 3912 // CHECK5-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 7 3913 // CHECK5-NEXT: [[TMP126:%.*]] = bitcast i8** [[TMP125]] to double** 3914 // CHECK5-NEXT: store double* [[VLA1]], double** [[TMP126]], align 8 3915 // CHECK5-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3916 // CHECK5-NEXT: store i64 [[TMP85]], i64* [[TMP127]], align 8 3917 // CHECK5-NEXT: [[TMP128:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 7 3918 // CHECK5-NEXT: store i8* null, i8** [[TMP128]], align 8 3919 // CHECK5-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 8 3920 // CHECK5-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to %struct.TT** 3921 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP130]], align 8 3922 // CHECK5-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 8 3923 // CHECK5-NEXT: [[TMP132:%.*]] = bitcast i8** [[TMP131]] to %struct.TT** 3924 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP132]], align 8 3925 // CHECK5-NEXT: [[TMP133:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 8 3926 // CHECK5-NEXT: store i8* null, i8** [[TMP133]], align 8 3927 // CHECK5-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 9 3928 // CHECK5-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i64* 3929 // CHECK5-NEXT: store i64 [[TMP81]], i64* [[TMP135]], align 8 3930 // CHECK5-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 9 3931 // CHECK5-NEXT: [[TMP137:%.*]] = bitcast i8** [[TMP136]] to i64* 3932 // CHECK5-NEXT: store i64 [[TMP81]], i64* [[TMP137]], align 8 3933 // CHECK5-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS23]], i64 0, i64 9 3934 // CHECK5-NEXT: store i8* null, i8** [[TMP138]], align 8 3935 // CHECK5-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS21]], i32 0, i32 0 3936 // CHECK5-NEXT: [[TMP140:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS22]], i32 0, i32 0 3937 // CHECK5-NEXT: [[TMP141:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3938 // CHECK5-NEXT: [[KERNEL_ARGS24:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 3939 // CHECK5-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 0 3940 // CHECK5-NEXT: store i32 1, i32* [[TMP142]], align 4 3941 // CHECK5-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 1 3942 // CHECK5-NEXT: store i32 10, i32* [[TMP143]], align 4 3943 // CHECK5-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 2 3944 // CHECK5-NEXT: store i8** [[TMP139]], i8*** [[TMP144]], align 8 3945 // CHECK5-NEXT: [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 3 3946 // CHECK5-NEXT: store i8** [[TMP140]], i8*** [[TMP145]], align 8 3947 // CHECK5-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 4 3948 // CHECK5-NEXT: store i64* [[TMP141]], i64** [[TMP146]], align 8 3949 // CHECK5-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 5 3950 // CHECK5-NEXT: store i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP147]], align 8 3951 // CHECK5-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 6 3952 // CHECK5-NEXT: store i8** null, i8*** [[TMP148]], align 8 3953 // CHECK5-NEXT: [[TMP149:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 7 3954 // CHECK5-NEXT: store i8** null, i8*** [[TMP149]], align 8 3955 // CHECK5-NEXT: [[TMP150:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]], i32 0, i32 8 3956 // CHECK5-NEXT: store i64 0, i64* [[TMP150]], align 8 3957 // CHECK5-NEXT: [[TMP151:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS24]]) 3958 // CHECK5-NEXT: [[TMP152:%.*]] = icmp ne i32 [[TMP151]], 0 3959 // CHECK5-NEXT: br i1 [[TMP152]], label [[OMP_OFFLOAD_FAILED25:%.*]], label [[OMP_OFFLOAD_CONT26:%.*]] 3960 // CHECK5: omp_offload.failed25: 3961 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP79]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP81]]) #[[ATTR4]] 3962 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT26]] 3963 // CHECK5: omp_offload.cont26: 3964 // CHECK5-NEXT: br label [[OMP_IF_END28:%.*]] 3965 // CHECK5: omp_if.else27: 3966 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i64 [[TMP79]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]], i64 [[TMP81]]) #[[ATTR4]] 3967 // CHECK5-NEXT: br label [[OMP_IF_END28]] 3968 // CHECK5: omp_if.end28: 3969 // CHECK5-NEXT: [[TMP153:%.*]] = load i32, i32* [[A]], align 4 3970 // CHECK5-NEXT: [[TMP154:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3971 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP154]]) 3972 // CHECK5-NEXT: ret i32 [[TMP153]] 3973 // 3974 // 3975 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 3976 // CHECK5-SAME: () #[[ATTR2:[0-9]+]] { 3977 // CHECK5-NEXT: entry: 3978 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 3979 // CHECK5-NEXT: ret void 3980 // 3981 // 3982 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 3983 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 3984 // CHECK5-NEXT: entry: 3985 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3986 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3987 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3988 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 3989 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3990 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3991 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3992 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3993 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 3994 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3995 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3996 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3997 // CHECK5-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 3998 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3999 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4000 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4001 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4002 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4003 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4004 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 4005 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4006 // CHECK5: cond.true: 4007 // CHECK5-NEXT: br label [[COND_END:%.*]] 4008 // CHECK5: cond.false: 4009 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4010 // CHECK5-NEXT: br label [[COND_END]] 4011 // CHECK5: cond.end: 4012 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4013 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4014 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4015 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4016 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4017 // CHECK5: omp.inner.for.cond: 4018 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10:![0-9]+]] 4019 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP10]] 4020 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4021 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4022 // CHECK5: omp.inner.for.body: 4023 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 4024 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 4025 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 4026 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP10]] 4027 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4028 // CHECK5: omp.body.continue: 4029 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4030 // CHECK5: omp.inner.for.inc: 4031 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 4032 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 4033 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP10]] 4034 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 4035 // CHECK5: omp.inner.for.end: 4036 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4037 // CHECK5: omp.loop.exit: 4038 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4039 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4040 // CHECK5-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 4041 // CHECK5-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4042 // CHECK5: .omp.final.then: 4043 // CHECK5-NEXT: store i32 33, i32* [[I]], align 4 4044 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4045 // CHECK5: .omp.final.done: 4046 // CHECK5-NEXT: ret void 4047 // 4048 // 4049 // CHECK5-LABEL: define {{[^@]+}}@.omp_task_entry. 4050 // CHECK5-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 4051 // CHECK5-NEXT: entry: 4052 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 4053 // CHECK5-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 4054 // CHECK5-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 4055 // CHECK5-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 4056 // CHECK5-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 4057 // CHECK5-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 4058 // CHECK5-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4059 // CHECK5-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 4060 // CHECK5-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 4061 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 4062 // CHECK5-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 4063 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 4064 // CHECK5-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 4065 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 4066 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 4067 // CHECK5-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 4068 // CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 4069 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 4070 // CHECK5-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 4071 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 4072 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 4073 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META21:![0-9]+]]) 4074 // CHECK5-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META23:![0-9]+]]) 4075 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !25 4076 // CHECK5-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !25 4077 // CHECK5-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !25 4078 // CHECK5-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !25 4079 // CHECK5-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !25 4080 // CHECK5-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 4081 // CHECK5-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !25 4082 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0 4083 // CHECK5-NEXT: store i32 1, i32* [[TMP11]], align 4, !noalias !25 4084 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1 4085 // CHECK5-NEXT: store i32 0, i32* [[TMP12]], align 4, !noalias !25 4086 // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2 4087 // CHECK5-NEXT: store i8** null, i8*** [[TMP13]], align 8, !noalias !25 4088 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3 4089 // CHECK5-NEXT: store i8** null, i8*** [[TMP14]], align 8, !noalias !25 4090 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4 4091 // CHECK5-NEXT: store i64* null, i64** [[TMP15]], align 8, !noalias !25 4092 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5 4093 // CHECK5-NEXT: store i64* null, i64** [[TMP16]], align 8, !noalias !25 4094 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6 4095 // CHECK5-NEXT: store i8** null, i8*** [[TMP17]], align 8, !noalias !25 4096 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7 4097 // CHECK5-NEXT: store i8** null, i8*** [[TMP18]], align 8, !noalias !25 4098 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8 4099 // CHECK5-NEXT: store i64 0, i64* [[TMP19]], align 8, !noalias !25 4100 // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) 4101 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 4102 // CHECK5-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 4103 // CHECK5: omp_offload.failed.i: 4104 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 4105 // CHECK5-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 4106 // CHECK5: .omp_outlined..1.exit: 4107 // CHECK5-NEXT: ret i32 0 4108 // 4109 // 4110 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 4111 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 4112 // CHECK5-NEXT: entry: 4113 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4114 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 4115 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4116 // CHECK5-NEXT: [[K_CASTED:%.*]] = alloca i64, align 8 4117 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4118 // CHECK5-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 4119 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4120 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4121 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4122 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 4123 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4124 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[K_ADDR]], align 8 4125 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[K_CASTED]], align 8 4126 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[K_CASTED]], align 8 4127 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 4128 // CHECK5-NEXT: ret void 4129 // 4130 // 4131 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 4132 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[K:%.*]]) #[[ATTR3]] { 4133 // CHECK5-NEXT: entry: 4134 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4135 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4136 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4137 // CHECK5-NEXT: [[K_ADDR:%.*]] = alloca i64, align 8 4138 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4139 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4140 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 4141 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4142 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4143 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4144 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4145 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4146 // CHECK5-NEXT: [[K1:%.*]] = alloca i64, align 8 4147 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4148 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4149 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4150 // CHECK5-NEXT: store i64 [[K]], i64* [[K_ADDR]], align 8 4151 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4152 // CHECK5-NEXT: [[TMP0:%.*]] = load i64, i64* [[K_ADDR]], align 8 4153 // CHECK5-NEXT: store i64 [[TMP0]], i64* [[DOTLINEAR_START]], align 8 4154 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4155 // CHECK5-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 4156 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4157 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4158 // CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4159 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4160 // CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP2]]) 4161 // CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 4162 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4163 // CHECK5: omp.dispatch.cond: 4164 // CHECK5-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP2]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4165 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP3]], 0 4166 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4167 // CHECK5: omp.dispatch.body: 4168 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4169 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4170 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4171 // CHECK5: omp.inner.for.cond: 4172 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26:![0-9]+]] 4173 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP26]] 4174 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4175 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4176 // CHECK5: omp.inner.for.body: 4177 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4178 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 1 4179 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 4180 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP26]] 4181 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP26]] 4182 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4183 // CHECK5-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP9]], 3 4184 // CHECK5-NEXT: [[CONV3:%.*]] = sext i32 [[MUL2]] to i64 4185 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP8]], [[CONV3]] 4186 // CHECK5-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group [[ACC_GRP26]] 4187 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP26]] 4188 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP10]], 1 4189 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP26]] 4190 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4191 // CHECK5: omp.body.continue: 4192 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4193 // CHECK5: omp.inner.for.inc: 4194 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4195 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP11]], 1 4196 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP26]] 4197 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 4198 // CHECK5: omp.inner.for.end: 4199 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4200 // CHECK5: omp.dispatch.inc: 4201 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 4202 // CHECK5: omp.dispatch.end: 4203 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4204 // CHECK5-NEXT: [[TMP13:%.*]] = icmp ne i32 [[TMP12]], 0 4205 // CHECK5-NEXT: br i1 [[TMP13]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4206 // CHECK5: .omp.final.then: 4207 // CHECK5-NEXT: store i32 1, i32* [[I]], align 4 4208 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4209 // CHECK5: .omp.final.done: 4210 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4211 // CHECK5-NEXT: [[TMP15:%.*]] = icmp ne i32 [[TMP14]], 0 4212 // CHECK5-NEXT: br i1 [[TMP15]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4213 // CHECK5: .omp.linear.pu: 4214 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[K1]], align 8 4215 // CHECK5-NEXT: store i64 [[TMP16]], i64* [[K_ADDR]], align 8 4216 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4217 // CHECK5: .omp.linear.pu.done: 4218 // CHECK5-NEXT: ret void 4219 // 4220 // 4221 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 4222 // CHECK5-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR2]] { 4223 // CHECK5-NEXT: entry: 4224 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4225 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 4226 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4227 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4228 // CHECK5-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 4229 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4230 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4231 // CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 4232 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4233 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4234 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 4235 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4236 // CHECK5-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4237 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4238 // CHECK5-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 4239 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4240 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 4241 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 4242 // CHECK5-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 4243 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 4244 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 4245 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4246 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 4247 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 4248 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 4249 // CHECK5-NEXT: ret void 4250 // 4251 // 4252 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 4253 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 4254 // CHECK5-NEXT: entry: 4255 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4256 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4257 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4258 // CHECK5-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 4259 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4260 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4261 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4262 // CHECK5-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 4263 // CHECK5-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 4264 // CHECK5-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 4265 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4266 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4267 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4268 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4269 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 4270 // CHECK5-NEXT: [[LIN4:%.*]] = alloca i32, align 4 4271 // CHECK5-NEXT: [[A5:%.*]] = alloca i32, align 4 4272 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4273 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4274 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4275 // CHECK5-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 4276 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4277 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4278 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 4279 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4280 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 4281 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 4282 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 4283 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 4284 // CHECK5-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 4285 // CHECK5-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 4286 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4287 // CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 4288 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4289 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4290 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4291 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 4292 // CHECK5-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 4293 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 4294 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4295 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 4296 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4297 // CHECK5: cond.true: 4298 // CHECK5-NEXT: br label [[COND_END:%.*]] 4299 // CHECK5: cond.false: 4300 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 4301 // CHECK5-NEXT: br label [[COND_END]] 4302 // CHECK5: cond.end: 4303 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 4304 // CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 4305 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4306 // CHECK5-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 4307 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4308 // CHECK5: omp.inner.for.cond: 4309 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 4310 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 4311 // CHECK5-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 4312 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4313 // CHECK5: omp.inner.for.body: 4314 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4315 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 4316 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 4317 // CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP29]] 4318 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP29]] 4319 // CHECK5-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 4320 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4321 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 4322 // CHECK5-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 4323 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 4324 // CHECK5-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 4325 // CHECK5-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group [[ACC_GRP29]] 4326 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group [[ACC_GRP29]] 4327 // CHECK5-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 4328 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4329 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP29]] 4330 // CHECK5-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 4331 // CHECK5-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 4332 // CHECK5-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 4333 // CHECK5-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group [[ACC_GRP29]] 4334 // CHECK5-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP29]] 4335 // CHECK5-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 4336 // CHECK5-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 4337 // CHECK5-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 4338 // CHECK5-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP29]] 4339 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4340 // CHECK5: omp.body.continue: 4341 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4342 // CHECK5: omp.inner.for.inc: 4343 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4344 // CHECK5-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 4345 // CHECK5-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 4346 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 4347 // CHECK5: omp.inner.for.end: 4348 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4349 // CHECK5: omp.loop.exit: 4350 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 4351 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4352 // CHECK5-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 4353 // CHECK5-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4354 // CHECK5: .omp.final.then: 4355 // CHECK5-NEXT: store i64 400, i64* [[IT]], align 8 4356 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4357 // CHECK5: .omp.final.done: 4358 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4359 // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 4360 // CHECK5-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 4361 // CHECK5: .omp.linear.pu: 4362 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 4363 // CHECK5-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 4364 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 4365 // CHECK5-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 4366 // CHECK5-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 4367 // CHECK5: .omp.linear.pu.done: 4368 // CHECK5-NEXT: ret void 4369 // 4370 // 4371 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 4372 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 4373 // CHECK5-NEXT: entry: 4374 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4375 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4376 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4377 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4378 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4379 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4380 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4381 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4382 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4383 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4384 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 4385 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4386 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4387 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4388 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 4389 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4390 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 4391 // CHECK5-NEXT: ret void 4392 // 4393 // 4394 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 4395 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 4396 // CHECK5-NEXT: entry: 4397 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4398 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4399 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4400 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4401 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4402 // CHECK5-NEXT: [[TMP:%.*]] = alloca i16, align 2 4403 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4404 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4405 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4406 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4407 // CHECK5-NEXT: [[IT:%.*]] = alloca i16, align 2 4408 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4409 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4410 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4411 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4412 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4413 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4414 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4415 // CHECK5-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 4416 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4417 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4418 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4419 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 4420 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4421 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4422 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 4423 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4424 // CHECK5: cond.true: 4425 // CHECK5-NEXT: br label [[COND_END:%.*]] 4426 // CHECK5: cond.false: 4427 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4428 // CHECK5-NEXT: br label [[COND_END]] 4429 // CHECK5: cond.end: 4430 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 4431 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4432 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4433 // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 4434 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4435 // CHECK5: omp.inner.for.cond: 4436 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32:![0-9]+]] 4437 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP32]] 4438 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 4439 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4440 // CHECK5: omp.inner.for.body: 4441 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4442 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 4443 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 4444 // CHECK5-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 4445 // CHECK5-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group [[ACC_GRP32]] 4446 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP32]] 4447 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 4448 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP32]] 4449 // CHECK5-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP32]] 4450 // CHECK5-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 4451 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 4452 // CHECK5-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 4453 // CHECK5-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP32]] 4454 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4455 // CHECK5: omp.body.continue: 4456 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4457 // CHECK5: omp.inner.for.inc: 4458 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4459 // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 4460 // CHECK5-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP32]] 4461 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 4462 // CHECK5: omp.inner.for.end: 4463 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4464 // CHECK5: omp.loop.exit: 4465 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 4466 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4467 // CHECK5-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 4468 // CHECK5-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4469 // CHECK5: .omp.final.then: 4470 // CHECK5-NEXT: store i16 22, i16* [[IT]], align 2 4471 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4472 // CHECK5: .omp.final.done: 4473 // CHECK5-NEXT: ret void 4474 // 4475 // 4476 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 4477 // CHECK5-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 4478 // CHECK5-NEXT: entry: 4479 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4480 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4481 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4482 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4483 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4484 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4485 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4486 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4487 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4488 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4489 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4490 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4491 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4492 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4493 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4494 // CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4495 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4496 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4497 // CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4498 // CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4499 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4500 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4501 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4502 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4503 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4504 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4505 // CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4506 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4507 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4508 // CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4509 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4510 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4511 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4512 // CHECK5-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4513 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 4514 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 4515 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 4516 // CHECK5-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 4517 // CHECK5-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 4518 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4519 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 4520 // CHECK5-NEXT: ret void 4521 // 4522 // 4523 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 4524 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 4525 // CHECK5-NEXT: entry: 4526 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4527 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4528 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4529 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4530 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4531 // CHECK5-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4532 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4533 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4534 // CHECK5-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4535 // CHECK5-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4536 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4537 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4538 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4539 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 4540 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4541 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4542 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4543 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4544 // CHECK5-NEXT: [[IT:%.*]] = alloca i8, align 1 4545 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4546 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4547 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4548 // CHECK5-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4549 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4550 // CHECK5-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4551 // CHECK5-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4552 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4553 // CHECK5-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4554 // CHECK5-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4555 // CHECK5-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4556 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4557 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4558 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4559 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4560 // CHECK5-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4561 // CHECK5-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4562 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4563 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4564 // CHECK5-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4565 // CHECK5-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4566 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 4567 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4568 // CHECK5-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 4569 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4570 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4571 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 4572 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4573 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4574 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 4575 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4576 // CHECK5: omp.dispatch.cond: 4577 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4578 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 4579 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4580 // CHECK5: cond.true: 4581 // CHECK5-NEXT: br label [[COND_END:%.*]] 4582 // CHECK5: cond.false: 4583 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4584 // CHECK5-NEXT: br label [[COND_END]] 4585 // CHECK5: cond.end: 4586 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4587 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4588 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4589 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 4590 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4591 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4592 // CHECK5-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4593 // CHECK5-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4594 // CHECK5: omp.dispatch.body: 4595 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4596 // CHECK5: omp.inner.for.cond: 4597 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35:![0-9]+]] 4598 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP35]] 4599 // CHECK5-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 4600 // CHECK5-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4601 // CHECK5: omp.inner.for.body: 4602 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4603 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 4604 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 4605 // CHECK5-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 4606 // CHECK5-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group [[ACC_GRP35]] 4607 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP35]] 4608 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 4609 // CHECK5-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP35]] 4610 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 4611 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 4612 // CHECK5-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 4613 // CHECK5-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 4614 // CHECK5-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 4615 // CHECK5-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP35]] 4616 // CHECK5-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 4617 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP35]] 4618 // CHECK5-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 4619 // CHECK5-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 4620 // CHECK5-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 4621 // CHECK5-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP35]] 4622 // CHECK5-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 4623 // CHECK5-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 4624 // CHECK5-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]] 4625 // CHECK5-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 4626 // CHECK5-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP35]] 4627 // CHECK5-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 4628 // CHECK5-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 4629 // CHECK5-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 4630 // CHECK5-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group [[ACC_GRP35]] 4631 // CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 4632 // CHECK5-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group [[ACC_GRP35]] 4633 // CHECK5-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4634 // CHECK5-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 4635 // CHECK5-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 4636 // CHECK5-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group [[ACC_GRP35]] 4637 // CHECK5-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4638 // CHECK5-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 4639 // CHECK5-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 4640 // CHECK5-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 4641 // CHECK5-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 4642 // CHECK5-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP35]] 4643 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4644 // CHECK5: omp.body.continue: 4645 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4646 // CHECK5: omp.inner.for.inc: 4647 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4648 // CHECK5-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 4649 // CHECK5-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP35]] 4650 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP36:![0-9]+]] 4651 // CHECK5: omp.inner.for.end: 4652 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4653 // CHECK5: omp.dispatch.inc: 4654 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4655 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4656 // CHECK5-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 4657 // CHECK5-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 4658 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4659 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4660 // CHECK5-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 4661 // CHECK5-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 4662 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]] 4663 // CHECK5: omp.dispatch.end: 4664 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4665 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 4666 // CHECK5-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 4667 // CHECK5-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 4668 // CHECK5: .omp.final.then: 4669 // CHECK5-NEXT: store i8 96, i8* [[IT]], align 1 4670 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 4671 // CHECK5: .omp.final.done: 4672 // CHECK5-NEXT: ret void 4673 // 4674 // 4675 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari 4676 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4677 // CHECK5-NEXT: entry: 4678 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4679 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4680 // CHECK5-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 4681 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4682 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4683 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4684 // CHECK5-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 4685 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 4686 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 4687 // CHECK5-NEXT: store i32 [[ADD]], i32* [[A]], align 4 4688 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 4689 // CHECK5-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 4690 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 4691 // CHECK5-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 4692 // CHECK5-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 4693 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4694 // CHECK5-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 4695 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 4696 // CHECK5-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 4697 // CHECK5-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 4698 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4699 // CHECK5-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 4700 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 4701 // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 4702 // CHECK5-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 4703 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 4704 // CHECK5-NEXT: ret i32 [[TMP8]] 4705 // 4706 // 4707 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 4708 // CHECK5-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 4709 // CHECK5-NEXT: entry: 4710 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4711 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4712 // CHECK5-NEXT: [[B:%.*]] = alloca i32, align 4 4713 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4714 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4715 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4716 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4717 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4718 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 8 4719 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 8 4720 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 8 4721 // CHECK5-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 8 4722 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4723 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4724 // CHECK5-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4725 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4726 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4727 // CHECK5-NEXT: store i32 [[ADD]], i32* [[B]], align 4 4728 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 4729 // CHECK5-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 4730 // CHECK5-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 4731 // CHECK5-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 4732 // CHECK5-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 4733 // CHECK5-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 4734 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 4735 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 4736 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 4737 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 4738 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 4739 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[B]], align 4 4740 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4741 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[CONV]], align 4 4742 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[B_CASTED]], align 8 4743 // CHECK5-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4744 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP8]] to i1 4745 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 4746 // CHECK5-NEXT: [[FROMBOOL3:%.*]] = zext i1 [[TOBOOL]] to i8 4747 // CHECK5-NEXT: store i8 [[FROMBOOL3]], i8* [[CONV2]], align 1 4748 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 4749 // CHECK5-NEXT: [[TMP10:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4750 // CHECK5-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP10]] to i1 4751 // CHECK5-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4752 // CHECK5: omp_if.then: 4753 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 4754 // CHECK5-NEXT: [[TMP11:%.*]] = mul nuw i64 2, [[TMP2]] 4755 // CHECK5-NEXT: [[TMP12:%.*]] = mul nuw i64 [[TMP11]], 2 4756 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 4757 // CHECK5-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP13]], i8* align 8 bitcast ([6 x i64]* @.offload_sizes.11 to i8*), i64 48, i1 false) 4758 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4759 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1** 4760 // CHECK5-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 8 4761 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4762 // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double** 4763 // CHECK5-NEXT: store double* [[A]], double** [[TMP17]], align 8 4764 // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4765 // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 8 4766 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4767 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 4768 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP20]], align 8 4769 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4770 // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 4771 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[TMP22]], align 8 4772 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4773 // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 8 4774 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4775 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 4776 // CHECK5-NEXT: store i64 2, i64* [[TMP25]], align 8 4777 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4778 // CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 4779 // CHECK5-NEXT: store i64 2, i64* [[TMP27]], align 8 4780 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4781 // CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 8 4782 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4783 // CHECK5-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 4784 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP30]], align 8 4785 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4786 // CHECK5-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 4787 // CHECK5-NEXT: store i64 [[TMP2]], i64* [[TMP32]], align 8 4788 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4789 // CHECK5-NEXT: store i8* null, i8** [[TMP33]], align 8 4790 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 4791 // CHECK5-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 4792 // CHECK5-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 4793 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 4794 // CHECK5-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 4795 // CHECK5-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 4796 // CHECK5-NEXT: [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 4797 // CHECK5-NEXT: store i64 [[TMP12]], i64* [[TMP38]], align 8 4798 // CHECK5-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 4799 // CHECK5-NEXT: store i8* null, i8** [[TMP39]], align 8 4800 // CHECK5-NEXT: [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 4801 // CHECK5-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 4802 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP41]], align 8 4803 // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 4804 // CHECK5-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* 4805 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[TMP43]], align 8 4806 // CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 5 4807 // CHECK5-NEXT: store i8* null, i8** [[TMP44]], align 8 4808 // CHECK5-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4809 // CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4810 // CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 4811 // CHECK5-NEXT: [[TMP48:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4812 // CHECK5-NEXT: [[TOBOOL5:%.*]] = trunc i8 [[TMP48]] to i1 4813 // CHECK5-NEXT: [[TMP49:%.*]] = select i1 [[TOBOOL5]], i32 0, i32 1 4814 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4815 // CHECK5-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 4816 // CHECK5-NEXT: store i32 1, i32* [[TMP50]], align 4 4817 // CHECK5-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 4818 // CHECK5-NEXT: store i32 6, i32* [[TMP51]], align 4 4819 // CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 4820 // CHECK5-NEXT: store i8** [[TMP45]], i8*** [[TMP52]], align 8 4821 // CHECK5-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 4822 // CHECK5-NEXT: store i8** [[TMP46]], i8*** [[TMP53]], align 8 4823 // CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 4824 // CHECK5-NEXT: store i64* [[TMP47]], i64** [[TMP54]], align 8 4825 // CHECK5-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 4826 // CHECK5-NEXT: store i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP55]], align 8 4827 // CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 4828 // CHECK5-NEXT: store i8** null, i8*** [[TMP56]], align 8 4829 // CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 4830 // CHECK5-NEXT: store i8** null, i8*** [[TMP57]], align 8 4831 // CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 4832 // CHECK5-NEXT: store i64 0, i64* [[TMP58]], align 8 4833 // CHECK5-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 [[TMP49]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 4834 // CHECK5-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 4835 // CHECK5-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4836 // CHECK5: omp_offload.failed: 4837 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4838 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4839 // CHECK5: omp_offload.cont: 4840 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4841 // CHECK5: omp_if.else: 4842 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i64 [[TMP7]], i64 2, i64 [[TMP2]], i16* [[VLA]], i64 [[TMP9]]) #[[ATTR4]] 4843 // CHECK5-NEXT: br label [[OMP_IF_END]] 4844 // CHECK5: omp_if.end: 4845 // CHECK5-NEXT: [[TMP61:%.*]] = mul nsw i64 1, [[TMP2]] 4846 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP61]] 4847 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 4848 // CHECK5-NEXT: [[TMP62:%.*]] = load i16, i16* [[ARRAYIDX6]], align 2 4849 // CHECK5-NEXT: [[CONV7:%.*]] = sext i16 [[TMP62]] to i32 4850 // CHECK5-NEXT: [[TMP63:%.*]] = load i32, i32* [[B]], align 4 4851 // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i32 [[CONV7]], [[TMP63]] 4852 // CHECK5-NEXT: [[TMP64:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4853 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP64]]) 4854 // CHECK5-NEXT: ret i32 [[ADD8]] 4855 // 4856 // 4857 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici 4858 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 4859 // CHECK5-NEXT: entry: 4860 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4861 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4862 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4863 // CHECK5-NEXT: [[AAA:%.*]] = alloca i8, align 1 4864 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4865 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4866 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4867 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4868 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 4869 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 4870 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 4871 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4872 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4873 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 4874 // CHECK5-NEXT: store i8 0, i8* [[AAA]], align 1 4875 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4876 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4877 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 4878 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4879 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4880 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4881 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4882 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4883 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 4884 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 4885 // CHECK5-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 4886 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 4887 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4888 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4889 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4890 // CHECK5: omp_if.then: 4891 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4892 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 4893 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 4894 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4895 // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 4896 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 4897 // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4898 // CHECK5-NEXT: store i8* null, i8** [[TMP11]], align 8 4899 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4900 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 4901 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 4902 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4903 // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 4904 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 4905 // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 4906 // CHECK5-NEXT: store i8* null, i8** [[TMP16]], align 8 4907 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4908 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 4909 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 4910 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4911 // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 4912 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 4913 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 4914 // CHECK5-NEXT: store i8* null, i8** [[TMP21]], align 8 4915 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4916 // CHECK5-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 4917 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 4918 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4919 // CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 4920 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 4921 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 4922 // CHECK5-NEXT: store i8* null, i8** [[TMP26]], align 8 4923 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4924 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4925 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 4926 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 4927 // CHECK5-NEXT: store i32 1, i32* [[TMP29]], align 4 4928 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 4929 // CHECK5-NEXT: store i32 4, i32* [[TMP30]], align 4 4930 // CHECK5-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 4931 // CHECK5-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 8 4932 // CHECK5-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 4933 // CHECK5-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8 4934 // CHECK5-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 4935 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 8 4936 // CHECK5-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 4937 // CHECK5-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 8 4938 // CHECK5-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 4939 // CHECK5-NEXT: store i8** null, i8*** [[TMP35]], align 8 4940 // CHECK5-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 4941 // CHECK5-NEXT: store i8** null, i8*** [[TMP36]], align 8 4942 // CHECK5-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 4943 // CHECK5-NEXT: store i64 0, i64* [[TMP37]], align 8 4944 // CHECK5-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 4945 // CHECK5-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 4946 // CHECK5-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4947 // CHECK5: omp_offload.failed: 4948 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4949 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 4950 // CHECK5: omp_offload.cont: 4951 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 4952 // CHECK5: omp_if.else: 4953 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4954 // CHECK5-NEXT: br label [[OMP_IF_END]] 4955 // CHECK5: omp_if.end: 4956 // CHECK5-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 4957 // CHECK5-NEXT: ret i32 [[TMP40]] 4958 // 4959 // 4960 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4961 // CHECK5-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 4962 // CHECK5-NEXT: entry: 4963 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4964 // CHECK5-NEXT: [[A:%.*]] = alloca i32, align 4 4965 // CHECK5-NEXT: [[AA:%.*]] = alloca i16, align 2 4966 // CHECK5-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4967 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4968 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4969 // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 4970 // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 4971 // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 4972 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4973 // CHECK5-NEXT: store i32 0, i32* [[A]], align 4 4974 // CHECK5-NEXT: store i16 0, i16* [[AA]], align 2 4975 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4976 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4977 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 4978 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4979 // CHECK5-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4980 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4981 // CHECK5-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 4982 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4983 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4984 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4985 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4986 // CHECK5: omp_if.then: 4987 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4988 // CHECK5-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 4989 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 4990 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4991 // CHECK5-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 4992 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 4993 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 4994 // CHECK5-NEXT: store i8* null, i8** [[TMP9]], align 8 4995 // CHECK5-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4996 // CHECK5-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 4997 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 4998 // CHECK5-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4999 // CHECK5-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 5000 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 5001 // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 5002 // CHECK5-NEXT: store i8* null, i8** [[TMP14]], align 8 5003 // CHECK5-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5004 // CHECK5-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 5005 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 5006 // CHECK5-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5007 // CHECK5-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 5008 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 5009 // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 5010 // CHECK5-NEXT: store i8* null, i8** [[TMP19]], align 8 5011 // CHECK5-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5012 // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5013 // CHECK5-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 5014 // CHECK5-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 5015 // CHECK5-NEXT: store i32 1, i32* [[TMP22]], align 4 5016 // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 5017 // CHECK5-NEXT: store i32 3, i32* [[TMP23]], align 4 5018 // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 5019 // CHECK5-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8 5020 // CHECK5-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 5021 // CHECK5-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 8 5022 // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 5023 // CHECK5-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 8 5024 // CHECK5-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 5025 // CHECK5-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 8 5026 // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 5027 // CHECK5-NEXT: store i8** null, i8*** [[TMP28]], align 8 5028 // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 5029 // CHECK5-NEXT: store i8** null, i8*** [[TMP29]], align 8 5030 // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 5031 // CHECK5-NEXT: store i64 0, i64* [[TMP30]], align 8 5032 // CHECK5-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 5033 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 5034 // CHECK5-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5035 // CHECK5: omp_offload.failed: 5036 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 5037 // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] 5038 // CHECK5: omp_offload.cont: 5039 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 5040 // CHECK5: omp_if.else: 5041 // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 5042 // CHECK5-NEXT: br label [[OMP_IF_END]] 5043 // CHECK5: omp_if.end: 5044 // CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4 5045 // CHECK5-NEXT: ret i32 [[TMP33]] 5046 // 5047 // 5048 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 5049 // CHECK5-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 5050 // CHECK5-NEXT: entry: 5051 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5052 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5053 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5054 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5055 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 5056 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5057 // CHECK5-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5058 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 5059 // CHECK5-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 5060 // CHECK5-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 5061 // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 5062 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5063 // CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5064 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5065 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5066 // CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 5067 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5068 // CHECK5-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5069 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5070 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5071 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5072 // CHECK5-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8 5073 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 5074 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4 5075 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* 5076 // CHECK5-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4 5077 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 5078 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 5079 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 5080 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 5081 // CHECK5-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 5082 // CHECK5-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 5083 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 5084 // CHECK5-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1 5085 // CHECK5-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 5086 // CHECK5-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5087 // CHECK5: omp_if.then: 5088 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) 5089 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 5090 // CHECK5: omp_if.else: 5091 // CHECK5-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 5092 // CHECK5-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 5093 // CHECK5-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 5094 // CHECK5-NEXT: call void @.omp_outlined..10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR4]] 5095 // CHECK5-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 5096 // CHECK5-NEXT: br label [[OMP_IF_END]] 5097 // CHECK5: omp_if.end: 5098 // CHECK5-NEXT: ret void 5099 // 5100 // 5101 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..10 5102 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 5103 // CHECK5-NEXT: entry: 5104 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5105 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5106 // CHECK5-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5107 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5108 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5109 // CHECK5-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5110 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 5111 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 5112 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5113 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 5114 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5115 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5116 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5117 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5118 // CHECK5-NEXT: [[IT:%.*]] = alloca i64, align 8 5119 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5120 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5121 // CHECK5-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5122 // CHECK5-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5123 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5124 // CHECK5-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5125 // CHECK5-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 5126 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 5127 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5128 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5129 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5130 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5131 // CHECK5-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 5132 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 5133 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5134 // CHECK5-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 5135 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5136 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5137 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1 5138 // CHECK5-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 5139 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5140 // CHECK5: omp_if.then: 5141 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5142 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 5143 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5144 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5145 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 5146 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5147 // CHECK5: cond.true: 5148 // CHECK5-NEXT: br label [[COND_END:%.*]] 5149 // CHECK5: cond.false: 5150 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5151 // CHECK5-NEXT: br label [[COND_END]] 5152 // CHECK5: cond.end: 5153 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 5154 // CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5155 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5156 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 5157 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5158 // CHECK5: omp.inner.for.cond: 5159 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38:![0-9]+]] 5160 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP38]] 5161 // CHECK5-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 5162 // CHECK5-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5163 // CHECK5: omp.inner.for.body: 5164 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 5165 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 5166 // CHECK5-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 5167 // CHECK5-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP38]] 5168 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP38]] 5169 // CHECK5-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double 5170 // CHECK5-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00 5171 // CHECK5-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5172 // CHECK5-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !39, !llvm.access.group [[ACC_GRP38]] 5173 // CHECK5-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5174 // CHECK5-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !39, !llvm.access.group [[ACC_GRP38]] 5175 // CHECK5-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 5176 // CHECK5-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !39, !llvm.access.group [[ACC_GRP38]] 5177 // CHECK5-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 5178 // CHECK5-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 5179 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]] 5180 // CHECK5-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 5181 // CHECK5-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group [[ACC_GRP38]] 5182 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5183 // CHECK5: omp.body.continue: 5184 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5185 // CHECK5: omp.inner.for.inc: 5186 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 5187 // CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1 5188 // CHECK5-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP38]] 5189 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP40:![0-9]+]] 5190 // CHECK5: omp.inner.for.end: 5191 // CHECK5-NEXT: br label [[OMP_IF_END:%.*]] 5192 // CHECK5: omp_if.else: 5193 // CHECK5-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5194 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 5195 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5196 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5197 // CHECK5-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3 5198 // CHECK5-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] 5199 // CHECK5: cond.true11: 5200 // CHECK5-NEXT: br label [[COND_END13:%.*]] 5201 // CHECK5: cond.false12: 5202 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5203 // CHECK5-NEXT: br label [[COND_END13]] 5204 // CHECK5: cond.end13: 5205 // CHECK5-NEXT: [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ] 5206 // CHECK5-NEXT: store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8 5207 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5208 // CHECK5-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 5209 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND15:%.*]] 5210 // CHECK5: omp.inner.for.cond15: 5211 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5212 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5213 // CHECK5-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 5214 // CHECK5-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]] 5215 // CHECK5: omp.inner.for.body17: 5216 // CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5217 // CHECK5-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400 5218 // CHECK5-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]] 5219 // CHECK5-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8 5220 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4 5221 // CHECK5-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double 5222 // CHECK5-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00 5223 // CHECK5-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5224 // CHECK5-NEXT: store double [[ADD21]], double* [[A22]], align 8 5225 // CHECK5-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5226 // CHECK5-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8 5227 // CHECK5-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00 5228 // CHECK5-NEXT: store double [[INC24]], double* [[A23]], align 8 5229 // CHECK5-NEXT: [[CONV25:%.*]] = fptosi double [[INC24]] to i16 5230 // CHECK5-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 5231 // CHECK5-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]] 5232 // CHECK5-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1 5233 // CHECK5-NEXT: store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2 5234 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] 5235 // CHECK5: omp.body.continue28: 5236 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC29:%.*]] 5237 // CHECK5: omp.inner.for.inc29: 5238 // CHECK5-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 5239 // CHECK5-NEXT: [[ADD30:%.*]] = add i64 [[TMP28]], 1 5240 // CHECK5-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 5241 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP42:![0-9]+]] 5242 // CHECK5: omp.inner.for.end31: 5243 // CHECK5-NEXT: br label [[OMP_IF_END]] 5244 // CHECK5: omp_if.end: 5245 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5246 // CHECK5: omp.loop.exit: 5247 // CHECK5-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5248 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 5249 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 5250 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5251 // CHECK5-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 5252 // CHECK5-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5253 // CHECK5: .omp.final.then: 5254 // CHECK5-NEXT: store i64 400, i64* [[IT]], align 8 5255 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5256 // CHECK5: .omp.final.done: 5257 // CHECK5-NEXT: ret void 5258 // 5259 // 5260 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 5261 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5262 // CHECK5-NEXT: entry: 5263 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5264 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5265 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5266 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5267 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5268 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5269 // CHECK5-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 5270 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5271 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5272 // CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 5273 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5274 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5275 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5276 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 5277 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5278 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5279 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5280 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 5281 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 5282 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 5283 // CHECK5-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5284 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 5285 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5286 // CHECK5-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 5287 // CHECK5-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 5288 // CHECK5-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 5289 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 5290 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 5291 // CHECK5-NEXT: ret void 5292 // 5293 // 5294 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..13 5295 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5296 // CHECK5-NEXT: entry: 5297 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5298 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5299 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5300 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5301 // CHECK5-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5302 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5303 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5304 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5305 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5306 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5307 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5308 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5309 // CHECK5-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 5310 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5311 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5312 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5313 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 5314 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5315 // CHECK5-NEXT: ret void 5316 // 5317 // 5318 // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 5319 // CHECK5-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 5320 // CHECK5-NEXT: entry: 5321 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5322 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5323 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5324 // CHECK5-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5325 // CHECK5-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5326 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5327 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5328 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5329 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5330 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5331 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5332 // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5333 // CHECK5-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5334 // CHECK5-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 5335 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 5336 // CHECK5-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 5337 // CHECK5-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5338 // CHECK5-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 5339 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5340 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 5341 // CHECK5-NEXT: ret void 5342 // 5343 // 5344 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..16 5345 // CHECK5-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 5346 // CHECK5-NEXT: entry: 5347 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5348 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5349 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5350 // CHECK5-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5351 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5352 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5353 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 5354 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5355 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5356 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5357 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5358 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 5359 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5360 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5361 // CHECK5-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5362 // CHECK5-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5363 // CHECK5-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5364 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5365 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5366 // CHECK5-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5367 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 5368 // CHECK5-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 5369 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 5370 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5371 // CHECK5-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 5372 // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5373 // CHECK5-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 5374 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5375 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 5376 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5377 // CHECK5: cond.true: 5378 // CHECK5-NEXT: br label [[COND_END:%.*]] 5379 // CHECK5: cond.false: 5380 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 5381 // CHECK5-NEXT: br label [[COND_END]] 5382 // CHECK5: cond.end: 5383 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 5384 // CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 5385 // CHECK5-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 5386 // CHECK5-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 5387 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5388 // CHECK5: omp.inner.for.cond: 5389 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44:![0-9]+]] 5390 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP44]] 5391 // CHECK5-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 5392 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5393 // CHECK5: omp.inner.for.body: 5394 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5395 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 5396 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 5397 // CHECK5-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP44]] 5398 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP44]] 5399 // CHECK5-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 5400 // CHECK5-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP44]] 5401 // CHECK5-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP44]] 5402 // CHECK5-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 5403 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 5404 // CHECK5-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 5405 // CHECK5-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP44]] 5406 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 5407 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] 5408 // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 5409 // CHECK5-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP44]] 5410 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5411 // CHECK5: omp.body.continue: 5412 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5413 // CHECK5: omp.inner.for.inc: 5414 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5415 // CHECK5-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 5416 // CHECK5-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP44]] 5417 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP45:![0-9]+]] 5418 // CHECK5: omp.inner.for.end: 5419 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5420 // CHECK5: omp.loop.exit: 5421 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 5422 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5423 // CHECK5-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5424 // CHECK5-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5425 // CHECK5: .omp.final.then: 5426 // CHECK5-NEXT: store i64 11, i64* [[I]], align 8 5427 // CHECK5-NEXT: br label [[DOTOMP_FINAL_DONE]] 5428 // CHECK5: .omp.final.done: 5429 // CHECK5-NEXT: ret void 5430 // 5431 // 5432 // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 5433 // CHECK5-SAME: () #[[ATTR8:[0-9]+]] { 5434 // CHECK5-NEXT: entry: 5435 // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) 5436 // CHECK5-NEXT: ret void 5437 // 5438 // 5439 // CHECK7-LABEL: define {{[^@]+}}@_Z7get_valv 5440 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 5441 // CHECK7-NEXT: entry: 5442 // CHECK7-NEXT: ret i64 0 5443 // 5444 // 5445 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi 5446 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 5447 // CHECK7-NEXT: entry: 5448 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5449 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 5450 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 5451 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5452 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 5453 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 5454 // CHECK7-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5455 // CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 5456 // CHECK7-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 5457 // CHECK7-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 5458 // CHECK7-NEXT: [[K:%.*]] = alloca i64, align 8 5459 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5460 // CHECK7-NEXT: [[LIN:%.*]] = alloca i32, align 4 5461 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5462 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 5463 // CHECK7-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 5464 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 5465 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 5466 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 5467 // CHECK7-NEXT: [[A_CASTED3:%.*]] = alloca i32, align 4 5468 // CHECK7-NEXT: [[AA_CASTED4:%.*]] = alloca i32, align 4 5469 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS6:%.*]] = alloca [2 x i8*], align 4 5470 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS7:%.*]] = alloca [2 x i8*], align 4 5471 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS8:%.*]] = alloca [2 x i8*], align 4 5472 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 5473 // CHECK7-NEXT: [[A_CASTED12:%.*]] = alloca i32, align 4 5474 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 5475 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS15:%.*]] = alloca [10 x i8*], align 4 5476 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS16:%.*]] = alloca [10 x i8*], align 4 5477 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS17:%.*]] = alloca [10 x i8*], align 4 5478 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [10 x i64], align 4 5479 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 5480 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5481 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 5482 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 5483 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5484 // CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 5485 // CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 5486 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 5487 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 5488 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 5489 // CHECK7-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 5490 // CHECK7-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 5491 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 5492 // CHECK7-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 5493 // CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 5494 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 5495 // CHECK7-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]], i8* [[TMP5]]) 5496 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 5497 // CHECK7-NEXT: store i64 [[CALL]], i64* [[K]], align 8 5498 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 5499 // CHECK7-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 5500 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 5501 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101(i32 [[TMP10]], i64* [[K]]) #[[ATTR4:[0-9]+]] 5502 // CHECK7-NEXT: store i32 12, i32* [[LIN]], align 4 5503 // CHECK7-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 5504 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5505 // CHECK7-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 5506 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5507 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[LIN]], align 4 5508 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[LIN_CASTED]], align 4 5509 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 5510 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4 5511 // CHECK7-NEXT: store i32 [[TMP15]], i32* [[A_CASTED2]], align 4 5512 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[A_CASTED2]], align 4 5513 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5514 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 5515 // CHECK7-NEXT: store i32 [[TMP12]], i32* [[TMP18]], align 4 5516 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5517 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 5518 // CHECK7-NEXT: store i32 [[TMP12]], i32* [[TMP20]], align 4 5519 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 5520 // CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 5521 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 5522 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 5523 // CHECK7-NEXT: store i32 [[TMP14]], i32* [[TMP23]], align 4 5524 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 5525 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 5526 // CHECK7-NEXT: store i32 [[TMP14]], i32* [[TMP25]], align 4 5527 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 5528 // CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 5529 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 5530 // CHECK7-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 5531 // CHECK7-NEXT: store i32 [[TMP16]], i32* [[TMP28]], align 4 5532 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 5533 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 5534 // CHECK7-NEXT: store i32 [[TMP16]], i32* [[TMP30]], align 4 5535 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 5536 // CHECK7-NEXT: store i8* null, i8** [[TMP31]], align 4 5537 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5538 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5539 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 5540 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 5541 // CHECK7-NEXT: store i32 1, i32* [[TMP34]], align 4 5542 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 5543 // CHECK7-NEXT: store i32 3, i32* [[TMP35]], align 4 5544 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 5545 // CHECK7-NEXT: store i8** [[TMP32]], i8*** [[TMP36]], align 4 5546 // CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 5547 // CHECK7-NEXT: store i8** [[TMP33]], i8*** [[TMP37]], align 4 5548 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 5549 // CHECK7-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP38]], align 4 5550 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 5551 // CHECK7-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP39]], align 4 5552 // CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 5553 // CHECK7-NEXT: store i8** null, i8*** [[TMP40]], align 4 5554 // CHECK7-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 5555 // CHECK7-NEXT: store i8** null, i8*** [[TMP41]], align 4 5556 // CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 5557 // CHECK7-NEXT: store i64 0, i64* [[TMP42]], align 8 5558 // CHECK7-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 5559 // CHECK7-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 5560 // CHECK7-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5561 // CHECK7: omp_offload.failed: 5562 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108(i32 [[TMP12]], i32 [[TMP14]], i32 [[TMP16]]) #[[ATTR4]] 5563 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 5564 // CHECK7: omp_offload.cont: 5565 // CHECK7-NEXT: [[TMP45:%.*]] = load i32, i32* [[A]], align 4 5566 // CHECK7-NEXT: store i32 [[TMP45]], i32* [[A_CASTED3]], align 4 5567 // CHECK7-NEXT: [[TMP46:%.*]] = load i32, i32* [[A_CASTED3]], align 4 5568 // CHECK7-NEXT: [[TMP47:%.*]] = load i16, i16* [[AA]], align 2 5569 // CHECK7-NEXT: [[CONV5:%.*]] = bitcast i32* [[AA_CASTED4]] to i16* 5570 // CHECK7-NEXT: store i16 [[TMP47]], i16* [[CONV5]], align 2 5571 // CHECK7-NEXT: [[TMP48:%.*]] = load i32, i32* [[AA_CASTED4]], align 4 5572 // CHECK7-NEXT: [[TMP49:%.*]] = load i32, i32* [[N_ADDR]], align 4 5573 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP49]], 10 5574 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 5575 // CHECK7: omp_if.then: 5576 // CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5577 // CHECK7-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 5578 // CHECK7-NEXT: store i32 [[TMP46]], i32* [[TMP51]], align 4 5579 // CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5580 // CHECK7-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 5581 // CHECK7-NEXT: store i32 [[TMP46]], i32* [[TMP53]], align 4 5582 // CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 0 5583 // CHECK7-NEXT: store i8* null, i8** [[TMP54]], align 4 5584 // CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 1 5585 // CHECK7-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to i32* 5586 // CHECK7-NEXT: store i32 [[TMP48]], i32* [[TMP56]], align 4 5587 // CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 1 5588 // CHECK7-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to i32* 5589 // CHECK7-NEXT: store i32 [[TMP48]], i32* [[TMP58]], align 4 5590 // CHECK7-NEXT: [[TMP59:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS8]], i32 0, i32 1 5591 // CHECK7-NEXT: store i8* null, i8** [[TMP59]], align 4 5592 // CHECK7-NEXT: [[TMP60:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS6]], i32 0, i32 0 5593 // CHECK7-NEXT: [[TMP61:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS7]], i32 0, i32 0 5594 // CHECK7-NEXT: [[KERNEL_ARGS9:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 5595 // CHECK7-NEXT: [[TMP62:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 0 5596 // CHECK7-NEXT: store i32 1, i32* [[TMP62]], align 4 5597 // CHECK7-NEXT: [[TMP63:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 1 5598 // CHECK7-NEXT: store i32 2, i32* [[TMP63]], align 4 5599 // CHECK7-NEXT: [[TMP64:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 2 5600 // CHECK7-NEXT: store i8** [[TMP60]], i8*** [[TMP64]], align 4 5601 // CHECK7-NEXT: [[TMP65:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 3 5602 // CHECK7-NEXT: store i8** [[TMP61]], i8*** [[TMP65]], align 4 5603 // CHECK7-NEXT: [[TMP66:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 4 5604 // CHECK7-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP66]], align 4 5605 // CHECK7-NEXT: [[TMP67:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 5 5606 // CHECK7-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP67]], align 4 5607 // CHECK7-NEXT: [[TMP68:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 6 5608 // CHECK7-NEXT: store i8** null, i8*** [[TMP68]], align 4 5609 // CHECK7-NEXT: [[TMP69:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 7 5610 // CHECK7-NEXT: store i8** null, i8*** [[TMP69]], align 4 5611 // CHECK7-NEXT: [[TMP70:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]], i32 0, i32 8 5612 // CHECK7-NEXT: store i64 0, i64* [[TMP70]], align 8 5613 // CHECK7-NEXT: [[TMP71:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS9]]) 5614 // CHECK7-NEXT: [[TMP72:%.*]] = icmp ne i32 [[TMP71]], 0 5615 // CHECK7-NEXT: br i1 [[TMP72]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 5616 // CHECK7: omp_offload.failed10: 5617 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP46]], i32 [[TMP48]]) #[[ATTR4]] 5618 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT11]] 5619 // CHECK7: omp_offload.cont11: 5620 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 5621 // CHECK7: omp_if.else: 5622 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116(i32 [[TMP46]], i32 [[TMP48]]) #[[ATTR4]] 5623 // CHECK7-NEXT: br label [[OMP_IF_END]] 5624 // CHECK7: omp_if.end: 5625 // CHECK7-NEXT: [[TMP73:%.*]] = load i32, i32* [[A]], align 4 5626 // CHECK7-NEXT: store i32 [[TMP73]], i32* [[DOTCAPTURE_EXPR_]], align 4 5627 // CHECK7-NEXT: [[TMP74:%.*]] = load i32, i32* [[A]], align 4 5628 // CHECK7-NEXT: store i32 [[TMP74]], i32* [[A_CASTED12]], align 4 5629 // CHECK7-NEXT: [[TMP75:%.*]] = load i32, i32* [[A_CASTED12]], align 4 5630 // CHECK7-NEXT: [[TMP76:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 5631 // CHECK7-NEXT: store i32 [[TMP76]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5632 // CHECK7-NEXT: [[TMP77:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 5633 // CHECK7-NEXT: [[TMP78:%.*]] = load i32, i32* [[N_ADDR]], align 4 5634 // CHECK7-NEXT: [[CMP13:%.*]] = icmp sgt i32 [[TMP78]], 20 5635 // CHECK7-NEXT: br i1 [[CMP13]], label [[OMP_IF_THEN14:%.*]], label [[OMP_IF_ELSE21:%.*]] 5636 // CHECK7: omp_if.then14: 5637 // CHECK7-NEXT: [[TMP79:%.*]] = mul nuw i32 [[TMP1]], 4 5638 // CHECK7-NEXT: [[TMP80:%.*]] = sext i32 [[TMP79]] to i64 5639 // CHECK7-NEXT: [[TMP81:%.*]] = mul nuw i32 5, [[TMP3]] 5640 // CHECK7-NEXT: [[TMP82:%.*]] = mul nuw i32 [[TMP81]], 8 5641 // CHECK7-NEXT: [[TMP83:%.*]] = sext i32 [[TMP82]] to i64 5642 // CHECK7-NEXT: [[TMP84:%.*]] = bitcast [10 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 5643 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP84]], i8* align 4 bitcast ([10 x i64]* @.offload_sizes.8 to i8*), i32 80, i1 false) 5644 // CHECK7-NEXT: [[TMP85:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0 5645 // CHECK7-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* 5646 // CHECK7-NEXT: store i32 [[TMP75]], i32* [[TMP86]], align 4 5647 // CHECK7-NEXT: [[TMP87:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0 5648 // CHECK7-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 5649 // CHECK7-NEXT: store i32 [[TMP75]], i32* [[TMP88]], align 4 5650 // CHECK7-NEXT: [[TMP89:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 0 5651 // CHECK7-NEXT: store i8* null, i8** [[TMP89]], align 4 5652 // CHECK7-NEXT: [[TMP90:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 1 5653 // CHECK7-NEXT: [[TMP91:%.*]] = bitcast i8** [[TMP90]] to [10 x float]** 5654 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP91]], align 4 5655 // CHECK7-NEXT: [[TMP92:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 1 5656 // CHECK7-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to [10 x float]** 5657 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP93]], align 4 5658 // CHECK7-NEXT: [[TMP94:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 1 5659 // CHECK7-NEXT: store i8* null, i8** [[TMP94]], align 4 5660 // CHECK7-NEXT: [[TMP95:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 2 5661 // CHECK7-NEXT: [[TMP96:%.*]] = bitcast i8** [[TMP95]] to i32* 5662 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP96]], align 4 5663 // CHECK7-NEXT: [[TMP97:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 2 5664 // CHECK7-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to i32* 5665 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP98]], align 4 5666 // CHECK7-NEXT: [[TMP99:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 2 5667 // CHECK7-NEXT: store i8* null, i8** [[TMP99]], align 4 5668 // CHECK7-NEXT: [[TMP100:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 3 5669 // CHECK7-NEXT: [[TMP101:%.*]] = bitcast i8** [[TMP100]] to float** 5670 // CHECK7-NEXT: store float* [[VLA]], float** [[TMP101]], align 4 5671 // CHECK7-NEXT: [[TMP102:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 3 5672 // CHECK7-NEXT: [[TMP103:%.*]] = bitcast i8** [[TMP102]] to float** 5673 // CHECK7-NEXT: store float* [[VLA]], float** [[TMP103]], align 4 5674 // CHECK7-NEXT: [[TMP104:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 5675 // CHECK7-NEXT: store i64 [[TMP80]], i64* [[TMP104]], align 4 5676 // CHECK7-NEXT: [[TMP105:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 3 5677 // CHECK7-NEXT: store i8* null, i8** [[TMP105]], align 4 5678 // CHECK7-NEXT: [[TMP106:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 4 5679 // CHECK7-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to [5 x [10 x double]]** 5680 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP107]], align 4 5681 // CHECK7-NEXT: [[TMP108:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 4 5682 // CHECK7-NEXT: [[TMP109:%.*]] = bitcast i8** [[TMP108]] to [5 x [10 x double]]** 5683 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP109]], align 4 5684 // CHECK7-NEXT: [[TMP110:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 4 5685 // CHECK7-NEXT: store i8* null, i8** [[TMP110]], align 4 5686 // CHECK7-NEXT: [[TMP111:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 5 5687 // CHECK7-NEXT: [[TMP112:%.*]] = bitcast i8** [[TMP111]] to i32* 5688 // CHECK7-NEXT: store i32 5, i32* [[TMP112]], align 4 5689 // CHECK7-NEXT: [[TMP113:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 5 5690 // CHECK7-NEXT: [[TMP114:%.*]] = bitcast i8** [[TMP113]] to i32* 5691 // CHECK7-NEXT: store i32 5, i32* [[TMP114]], align 4 5692 // CHECK7-NEXT: [[TMP115:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 5 5693 // CHECK7-NEXT: store i8* null, i8** [[TMP115]], align 4 5694 // CHECK7-NEXT: [[TMP116:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 6 5695 // CHECK7-NEXT: [[TMP117:%.*]] = bitcast i8** [[TMP116]] to i32* 5696 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP117]], align 4 5697 // CHECK7-NEXT: [[TMP118:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 6 5698 // CHECK7-NEXT: [[TMP119:%.*]] = bitcast i8** [[TMP118]] to i32* 5699 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP119]], align 4 5700 // CHECK7-NEXT: [[TMP120:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 6 5701 // CHECK7-NEXT: store i8* null, i8** [[TMP120]], align 4 5702 // CHECK7-NEXT: [[TMP121:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 7 5703 // CHECK7-NEXT: [[TMP122:%.*]] = bitcast i8** [[TMP121]] to double** 5704 // CHECK7-NEXT: store double* [[VLA1]], double** [[TMP122]], align 4 5705 // CHECK7-NEXT: [[TMP123:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 7 5706 // CHECK7-NEXT: [[TMP124:%.*]] = bitcast i8** [[TMP123]] to double** 5707 // CHECK7-NEXT: store double* [[VLA1]], double** [[TMP124]], align 4 5708 // CHECK7-NEXT: [[TMP125:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 5709 // CHECK7-NEXT: store i64 [[TMP83]], i64* [[TMP125]], align 4 5710 // CHECK7-NEXT: [[TMP126:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 7 5711 // CHECK7-NEXT: store i8* null, i8** [[TMP126]], align 4 5712 // CHECK7-NEXT: [[TMP127:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 8 5713 // CHECK7-NEXT: [[TMP128:%.*]] = bitcast i8** [[TMP127]] to %struct.TT** 5714 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP128]], align 4 5715 // CHECK7-NEXT: [[TMP129:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 8 5716 // CHECK7-NEXT: [[TMP130:%.*]] = bitcast i8** [[TMP129]] to %struct.TT** 5717 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP130]], align 4 5718 // CHECK7-NEXT: [[TMP131:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 8 5719 // CHECK7-NEXT: store i8* null, i8** [[TMP131]], align 4 5720 // CHECK7-NEXT: [[TMP132:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 9 5721 // CHECK7-NEXT: [[TMP133:%.*]] = bitcast i8** [[TMP132]] to i32* 5722 // CHECK7-NEXT: store i32 [[TMP77]], i32* [[TMP133]], align 4 5723 // CHECK7-NEXT: [[TMP134:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 9 5724 // CHECK7-NEXT: [[TMP135:%.*]] = bitcast i8** [[TMP134]] to i32* 5725 // CHECK7-NEXT: store i32 [[TMP77]], i32* [[TMP135]], align 4 5726 // CHECK7-NEXT: [[TMP136:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_MAPPERS17]], i32 0, i32 9 5727 // CHECK7-NEXT: store i8* null, i8** [[TMP136]], align 4 5728 // CHECK7-NEXT: [[TMP137:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_BASEPTRS15]], i32 0, i32 0 5729 // CHECK7-NEXT: [[TMP138:%.*]] = getelementptr inbounds [10 x i8*], [10 x i8*]* [[DOTOFFLOAD_PTRS16]], i32 0, i32 0 5730 // CHECK7-NEXT: [[TMP139:%.*]] = getelementptr inbounds [10 x i64], [10 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 5731 // CHECK7-NEXT: [[KERNEL_ARGS18:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 5732 // CHECK7-NEXT: [[TMP140:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 0 5733 // CHECK7-NEXT: store i32 1, i32* [[TMP140]], align 4 5734 // CHECK7-NEXT: [[TMP141:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 1 5735 // CHECK7-NEXT: store i32 10, i32* [[TMP141]], align 4 5736 // CHECK7-NEXT: [[TMP142:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 2 5737 // CHECK7-NEXT: store i8** [[TMP137]], i8*** [[TMP142]], align 4 5738 // CHECK7-NEXT: [[TMP143:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 3 5739 // CHECK7-NEXT: store i8** [[TMP138]], i8*** [[TMP143]], align 4 5740 // CHECK7-NEXT: [[TMP144:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 4 5741 // CHECK7-NEXT: store i64* [[TMP139]], i64** [[TMP144]], align 4 5742 // CHECK7-NEXT: [[TMP145:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 5 5743 // CHECK7-NEXT: store i64* getelementptr inbounds ([10 x i64], [10 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP145]], align 4 5744 // CHECK7-NEXT: [[TMP146:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 6 5745 // CHECK7-NEXT: store i8** null, i8*** [[TMP146]], align 4 5746 // CHECK7-NEXT: [[TMP147:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 7 5747 // CHECK7-NEXT: store i8** null, i8*** [[TMP147]], align 4 5748 // CHECK7-NEXT: [[TMP148:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]], i32 0, i32 8 5749 // CHECK7-NEXT: store i64 0, i64* [[TMP148]], align 8 5750 // CHECK7-NEXT: [[TMP149:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS18]]) 5751 // CHECK7-NEXT: [[TMP150:%.*]] = icmp ne i32 [[TMP149]], 0 5752 // CHECK7-NEXT: br i1 [[TMP150]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 5753 // CHECK7: omp_offload.failed19: 5754 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP75]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP77]]) #[[ATTR4]] 5755 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT20]] 5756 // CHECK7: omp_offload.cont20: 5757 // CHECK7-NEXT: br label [[OMP_IF_END22:%.*]] 5758 // CHECK7: omp_if.else21: 5759 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140(i32 [[TMP75]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]], i32 [[TMP77]]) #[[ATTR4]] 5760 // CHECK7-NEXT: br label [[OMP_IF_END22]] 5761 // CHECK7: omp_if.end22: 5762 // CHECK7-NEXT: [[TMP151:%.*]] = load i32, i32* [[A]], align 4 5763 // CHECK7-NEXT: [[TMP152:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 5764 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP152]]) 5765 // CHECK7-NEXT: ret i32 [[TMP151]] 5766 // 5767 // 5768 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 5769 // CHECK7-SAME: () #[[ATTR2:[0-9]+]] { 5770 // CHECK7-NEXT: entry: 5771 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5772 // CHECK7-NEXT: ret void 5773 // 5774 // 5775 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined. 5776 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 5777 // CHECK7-NEXT: entry: 5778 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5779 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5780 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5781 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5782 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5783 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5784 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5785 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5786 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5787 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5788 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5789 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5790 // CHECK7-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 5791 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5792 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5793 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5794 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 5795 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 5796 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5797 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 5798 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 5799 // CHECK7: cond.true: 5800 // CHECK7-NEXT: br label [[COND_END:%.*]] 5801 // CHECK7: cond.false: 5802 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 5803 // CHECK7-NEXT: br label [[COND_END]] 5804 // CHECK7: cond.end: 5805 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 5806 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 5807 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5808 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 5809 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5810 // CHECK7: omp.inner.for.cond: 5811 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 5812 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 5813 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 5814 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5815 // CHECK7: omp.inner.for.body: 5816 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5817 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 5818 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 5819 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 5820 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5821 // CHECK7: omp.body.continue: 5822 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5823 // CHECK7: omp.inner.for.inc: 5824 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5825 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 5826 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 5827 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 5828 // CHECK7: omp.inner.for.end: 5829 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 5830 // CHECK7: omp.loop.exit: 5831 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 5832 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5833 // CHECK7-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 5834 // CHECK7-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5835 // CHECK7: .omp.final.then: 5836 // CHECK7-NEXT: store i32 33, i32* [[I]], align 4 5837 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5838 // CHECK7: .omp.final.done: 5839 // CHECK7-NEXT: ret void 5840 // 5841 // 5842 // CHECK7-LABEL: define {{[^@]+}}@.omp_task_entry. 5843 // CHECK7-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 5844 // CHECK7-NEXT: entry: 5845 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 5846 // CHECK7-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 5847 // CHECK7-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 5848 // CHECK7-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 5849 // CHECK7-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 5850 // CHECK7-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 5851 // CHECK7-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 5852 // CHECK7-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 5853 // CHECK7-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 5854 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 5855 // CHECK7-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5856 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 5857 // CHECK7-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 5858 // CHECK7-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 5859 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 5860 // CHECK7-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 5861 // CHECK7-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 5862 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 5863 // CHECK7-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 5864 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 5865 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 5866 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META22:![0-9]+]]) 5867 // CHECK7-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META24:![0-9]+]]) 5868 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !26 5869 // CHECK7-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !26 5870 // CHECK7-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !26 5871 // CHECK7-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !26 5872 // CHECK7-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !26 5873 // CHECK7-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 5874 // CHECK7-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !26 5875 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0 5876 // CHECK7-NEXT: store i32 1, i32* [[TMP11]], align 4, !noalias !26 5877 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1 5878 // CHECK7-NEXT: store i32 0, i32* [[TMP12]], align 4, !noalias !26 5879 // CHECK7-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2 5880 // CHECK7-NEXT: store i8** null, i8*** [[TMP13]], align 4, !noalias !26 5881 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3 5882 // CHECK7-NEXT: store i8** null, i8*** [[TMP14]], align 4, !noalias !26 5883 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4 5884 // CHECK7-NEXT: store i64* null, i64** [[TMP15]], align 4, !noalias !26 5885 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5 5886 // CHECK7-NEXT: store i64* null, i64** [[TMP16]], align 4, !noalias !26 5887 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6 5888 // CHECK7-NEXT: store i8** null, i8*** [[TMP17]], align 4, !noalias !26 5889 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7 5890 // CHECK7-NEXT: store i8** null, i8*** [[TMP18]], align 4, !noalias !26 5891 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8 5892 // CHECK7-NEXT: store i64 0, i64* [[TMP19]], align 8, !noalias !26 5893 // CHECK7-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) 5894 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 5895 // CHECK7-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 5896 // CHECK7: omp_offload.failed.i: 5897 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96() #[[ATTR4]] 5898 // CHECK7-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 5899 // CHECK7: .omp_outlined..1.exit: 5900 // CHECK7-NEXT: ret i32 0 5901 // 5902 // 5903 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l101 5904 // CHECK7-SAME: (i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5905 // CHECK7-NEXT: entry: 5906 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5907 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 5908 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5909 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5910 // CHECK7-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 5911 // CHECK7-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 5912 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5913 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5914 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5915 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i64*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], i64* [[TMP0]]) 5916 // CHECK7-NEXT: ret void 5917 // 5918 // 5919 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..2 5920 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i64* noundef nonnull align 4 dereferenceable(8) [[K:%.*]]) #[[ATTR3]] { 5921 // CHECK7-NEXT: entry: 5922 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5923 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5924 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5925 // CHECK7-NEXT: [[K_ADDR:%.*]] = alloca i64*, align 4 5926 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5927 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 5928 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 5929 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5930 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5931 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5932 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5933 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 5934 // CHECK7-NEXT: [[K1:%.*]] = alloca i64, align 8 5935 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5936 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5937 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5938 // CHECK7-NEXT: store i64* [[K]], i64** [[K_ADDR]], align 4 5939 // CHECK7-NEXT: [[TMP0:%.*]] = load i64*, i64** [[K_ADDR]], align 4 5940 // CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[TMP0]], align 8 5941 // CHECK7-NEXT: store i64 [[TMP1]], i64* [[DOTLINEAR_START]], align 8 5942 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 5943 // CHECK7-NEXT: store i32 8, i32* [[DOTOMP_UB]], align 4 5944 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 5945 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 5946 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5947 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 5948 // CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 5949 // CHECK7-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32 1073741859, i32 0, i32 8, i32 1, i32 1) 5950 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 5951 // CHECK7: omp.dispatch.cond: 5952 // CHECK7-NEXT: [[TMP4:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP3]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 5953 // CHECK7-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP4]], 0 5954 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 5955 // CHECK7: omp.dispatch.body: 5956 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 5957 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_IV]], align 4 5958 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 5959 // CHECK7: omp.inner.for.cond: 5960 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27:![0-9]+]] 5961 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP27]] 5962 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP6]], [[TMP7]] 5963 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 5964 // CHECK7: omp.inner.for.body: 5965 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5966 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP8]], 1 5967 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL]] 5968 // CHECK7-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP27]] 5969 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP27]] 5970 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5971 // CHECK7-NEXT: [[MUL2:%.*]] = mul nsw i32 [[TMP10]], 3 5972 // CHECK7-NEXT: [[CONV:%.*]] = sext i32 [[MUL2]] to i64 5973 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 [[TMP9]], [[CONV]] 5974 // CHECK7-NEXT: store i64 [[ADD]], i64* [[K1]], align 8, !llvm.access.group [[ACC_GRP27]] 5975 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 5976 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP11]], 1 5977 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 5978 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 5979 // CHECK7: omp.body.continue: 5980 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 5981 // CHECK7: omp.inner.for.inc: 5982 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5983 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP12]], 1 5984 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP27]] 5985 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 5986 // CHECK7: omp.inner.for.end: 5987 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 5988 // CHECK7: omp.dispatch.inc: 5989 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 5990 // CHECK7: omp.dispatch.end: 5991 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5992 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 5993 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 5994 // CHECK7: .omp.final.then: 5995 // CHECK7-NEXT: store i32 1, i32* [[I]], align 4 5996 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 5997 // CHECK7: .omp.final.done: 5998 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 5999 // CHECK7-NEXT: [[TMP16:%.*]] = icmp ne i32 [[TMP15]], 0 6000 // CHECK7-NEXT: br i1 [[TMP16]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 6001 // CHECK7: .omp.linear.pu: 6002 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[K1]], align 8 6003 // CHECK7-NEXT: store i64 [[TMP17]], i64* [[TMP0]], align 8 6004 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 6005 // CHECK7: .omp.linear.pu.done: 6006 // CHECK7-NEXT: ret void 6007 // 6008 // 6009 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 6010 // CHECK7-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR2]] { 6011 // CHECK7-NEXT: entry: 6012 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6013 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 6014 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6015 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6016 // CHECK7-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 6017 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6018 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6019 // CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 6020 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6021 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6022 // CHECK7-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6023 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6024 // CHECK7-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 6025 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6026 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 6027 // CHECK7-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 6028 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 6029 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 6030 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 6031 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 6032 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 6033 // CHECK7-NEXT: ret void 6034 // 6035 // 6036 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..3 6037 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 6038 // CHECK7-NEXT: entry: 6039 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6040 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6041 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6042 // CHECK7-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 6043 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6044 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6045 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6046 // CHECK7-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 6047 // CHECK7-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 6048 // CHECK7-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 6049 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6050 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6051 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6052 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6053 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 6054 // CHECK7-NEXT: [[LIN2:%.*]] = alloca i32, align 4 6055 // CHECK7-NEXT: [[A3:%.*]] = alloca i32, align 4 6056 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6057 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6058 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6059 // CHECK7-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 6060 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6061 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6062 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 6063 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 6064 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 6065 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 6066 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 6067 // CHECK7-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 6068 // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6069 // CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 6070 // CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6071 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6072 // CHECK7-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6073 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 6074 // CHECK7-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3]], i32 [[TMP3]]) 6075 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6076 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6077 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 6078 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6079 // CHECK7: cond.true: 6080 // CHECK7-NEXT: br label [[COND_END:%.*]] 6081 // CHECK7: cond.false: 6082 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6083 // CHECK7-NEXT: br label [[COND_END]] 6084 // CHECK7: cond.end: 6085 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 6086 // CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6087 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6088 // CHECK7-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 6089 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6090 // CHECK7: omp.inner.for.cond: 6091 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 6092 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 6093 // CHECK7-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 6094 // CHECK7-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6095 // CHECK7: omp.inner.for.body: 6096 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 6097 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 6098 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6099 // CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP30]] 6100 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP30]] 6101 // CHECK7-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 6102 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 6103 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 6104 // CHECK7-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 6105 // CHECK7-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 6106 // CHECK7-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 6107 // CHECK7-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group [[ACC_GRP30]] 6108 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP30]] 6109 // CHECK7-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 6110 // CHECK7-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 6111 // CHECK7-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP30]] 6112 // CHECK7-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 6113 // CHECK7-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 6114 // CHECK7-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 6115 // CHECK7-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group [[ACC_GRP30]] 6116 // CHECK7-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP30]] 6117 // CHECK7-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 6118 // CHECK7-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 6119 // CHECK7-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 6120 // CHECK7-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP30]] 6121 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6122 // CHECK7: omp.body.continue: 6123 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6124 // CHECK7: omp.inner.for.inc: 6125 // CHECK7-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 6126 // CHECK7-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 6127 // CHECK7-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 6128 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 6129 // CHECK7: omp.inner.for.end: 6130 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6131 // CHECK7: omp.loop.exit: 6132 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 6133 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6134 // CHECK7-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 6135 // CHECK7-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6136 // CHECK7: .omp.final.then: 6137 // CHECK7-NEXT: store i64 400, i64* [[IT]], align 8 6138 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6139 // CHECK7: .omp.final.done: 6140 // CHECK7-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6141 // CHECK7-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 6142 // CHECK7-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 6143 // CHECK7: .omp.linear.pu: 6144 // CHECK7-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 6145 // CHECK7-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 6146 // CHECK7-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 6147 // CHECK7-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 6148 // CHECK7-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 6149 // CHECK7: .omp.linear.pu.done: 6150 // CHECK7-NEXT: ret void 6151 // 6152 // 6153 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 6154 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 6155 // CHECK7-NEXT: entry: 6156 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6157 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6158 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6159 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6160 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6161 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6162 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6163 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 6164 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6165 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6166 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 6167 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6168 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 6169 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6170 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 6171 // CHECK7-NEXT: ret void 6172 // 6173 // 6174 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..4 6175 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 6176 // CHECK7-NEXT: entry: 6177 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6178 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6179 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6180 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 6181 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6182 // CHECK7-NEXT: [[TMP:%.*]] = alloca i16, align 2 6183 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6184 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6185 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6186 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6187 // CHECK7-NEXT: [[IT:%.*]] = alloca i16, align 2 6188 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6189 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6190 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6191 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 6192 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 6193 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6194 // CHECK7-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 6195 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6196 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6197 // CHECK7-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6198 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 6199 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6200 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6201 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 6202 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6203 // CHECK7: cond.true: 6204 // CHECK7-NEXT: br label [[COND_END:%.*]] 6205 // CHECK7: cond.false: 6206 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6207 // CHECK7-NEXT: br label [[COND_END]] 6208 // CHECK7: cond.end: 6209 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 6210 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6211 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6212 // CHECK7-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 6213 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6214 // CHECK7: omp.inner.for.cond: 6215 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33:![0-9]+]] 6216 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP33]] 6217 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 6218 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6219 // CHECK7: omp.inner.for.body: 6220 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 6221 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 6222 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 6223 // CHECK7-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 6224 // CHECK7-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group [[ACC_GRP33]] 6225 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 6226 // CHECK7-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 6227 // CHECK7-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 6228 // CHECK7-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP33]] 6229 // CHECK7-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 6230 // CHECK7-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 6231 // CHECK7-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 6232 // CHECK7-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP33]] 6233 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6234 // CHECK7: omp.body.continue: 6235 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6236 // CHECK7: omp.inner.for.inc: 6237 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 6238 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 6239 // CHECK7-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP33]] 6240 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 6241 // CHECK7: omp.inner.for.end: 6242 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6243 // CHECK7: omp.loop.exit: 6244 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 6245 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6246 // CHECK7-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 6247 // CHECK7-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6248 // CHECK7: .omp.final.then: 6249 // CHECK7-NEXT: store i16 22, i16* [[IT]], align 2 6250 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6251 // CHECK7: .omp.final.done: 6252 // CHECK7-NEXT: ret void 6253 // 6254 // 6255 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 6256 // CHECK7-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6257 // CHECK7-NEXT: entry: 6258 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6259 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 6260 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6261 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 6262 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 6263 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6264 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6265 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 6266 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 6267 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6268 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6269 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6270 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6271 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 6272 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6273 // CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 6274 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 6275 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6276 // CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 6277 // CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 6278 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 6279 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6280 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 6281 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6282 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 6283 // CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 6284 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6285 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 6286 // CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 6287 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 6288 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 6289 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 6290 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 6291 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6292 // CHECK7-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6293 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6294 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 6295 // CHECK7-NEXT: ret void 6296 // 6297 // 6298 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..7 6299 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 6300 // CHECK7-NEXT: entry: 6301 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6302 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6303 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 6304 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 6305 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6306 // CHECK7-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 6307 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 6308 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6309 // CHECK7-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 6310 // CHECK7-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 6311 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 6312 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6313 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6314 // CHECK7-NEXT: [[TMP:%.*]] = alloca i8, align 1 6315 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6316 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6317 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6318 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6319 // CHECK7-NEXT: [[IT:%.*]] = alloca i8, align 1 6320 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6321 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6322 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 6323 // CHECK7-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 6324 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6325 // CHECK7-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 6326 // CHECK7-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 6327 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6328 // CHECK7-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 6329 // CHECK7-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 6330 // CHECK7-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 6331 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6332 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 6333 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6334 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 6335 // CHECK7-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 6336 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6337 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 6338 // CHECK7-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 6339 // CHECK7-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 6340 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6341 // CHECK7-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 6342 // CHECK7-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6343 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6344 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6345 // CHECK7-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6346 // CHECK7-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 6347 // CHECK7-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 6348 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6349 // CHECK7: omp.dispatch.cond: 6350 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6351 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 6352 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6353 // CHECK7: cond.true: 6354 // CHECK7-NEXT: br label [[COND_END:%.*]] 6355 // CHECK7: cond.false: 6356 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6357 // CHECK7-NEXT: br label [[COND_END]] 6358 // CHECK7: cond.end: 6359 // CHECK7-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6360 // CHECK7-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6361 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6362 // CHECK7-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 6363 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6364 // CHECK7-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6365 // CHECK7-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6366 // CHECK7-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6367 // CHECK7: omp.dispatch.body: 6368 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6369 // CHECK7: omp.inner.for.cond: 6370 // CHECK7-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36:![0-9]+]] 6371 // CHECK7-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP36]] 6372 // CHECK7-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 6373 // CHECK7-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6374 // CHECK7: omp.inner.for.body: 6375 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6376 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 6377 // CHECK7-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 6378 // CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 6379 // CHECK7-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group [[ACC_GRP36]] 6380 // CHECK7-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 6381 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 6382 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP36]] 6383 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 6384 // CHECK7-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 6385 // CHECK7-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 6386 // CHECK7-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 6387 // CHECK7-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 6388 // CHECK7-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP36]] 6389 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 6390 // CHECK7-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 6391 // CHECK7-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 6392 // CHECK7-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 6393 // CHECK7-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 6394 // CHECK7-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP36]] 6395 // CHECK7-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 6396 // CHECK7-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 6397 // CHECK7-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 6398 // CHECK7-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 6399 // CHECK7-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP36]] 6400 // CHECK7-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 6401 // CHECK7-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 6402 // CHECK7-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 6403 // CHECK7-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 6404 // CHECK7-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 6405 // CHECK7-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP36]] 6406 // CHECK7-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6407 // CHECK7-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 6408 // CHECK7-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 6409 // CHECK7-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group [[ACC_GRP36]] 6410 // CHECK7-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6411 // CHECK7-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 6412 // CHECK7-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 6413 // CHECK7-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 6414 // CHECK7-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 6415 // CHECK7-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP36]] 6416 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6417 // CHECK7: omp.body.continue: 6418 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6419 // CHECK7: omp.inner.for.inc: 6420 // CHECK7-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6421 // CHECK7-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 6422 // CHECK7-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP36]] 6423 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP37:![0-9]+]] 6424 // CHECK7: omp.inner.for.end: 6425 // CHECK7-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6426 // CHECK7: omp.dispatch.inc: 6427 // CHECK7-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6428 // CHECK7-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6429 // CHECK7-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 6430 // CHECK7-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 6431 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6432 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6433 // CHECK7-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 6434 // CHECK7-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 6435 // CHECK7-NEXT: br label [[OMP_DISPATCH_COND]] 6436 // CHECK7: omp.dispatch.end: 6437 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 6438 // CHECK7-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 6439 // CHECK7-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 6440 // CHECK7-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 6441 // CHECK7: .omp.final.then: 6442 // CHECK7-NEXT: store i8 96, i8* [[IT]], align 1 6443 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 6444 // CHECK7: .omp.final.done: 6445 // CHECK7-NEXT: ret void 6446 // 6447 // 6448 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari 6449 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6450 // CHECK7-NEXT: entry: 6451 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6452 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6453 // CHECK7-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 6454 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6455 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6456 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6457 // CHECK7-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 6458 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6459 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6460 // CHECK7-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6461 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6462 // CHECK7-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 6463 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6464 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6465 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6466 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6467 // CHECK7-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 6468 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6469 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6470 // CHECK7-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6471 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6472 // CHECK7-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 6473 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6474 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6475 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6476 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6477 // CHECK7-NEXT: ret i32 [[TMP8]] 6478 // 6479 // 6480 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6481 // CHECK7-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6482 // CHECK7-NEXT: entry: 6483 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6484 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6485 // CHECK7-NEXT: [[B:%.*]] = alloca i32, align 4 6486 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 6487 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 6488 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6489 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6490 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6491 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [6 x i8*], align 4 6492 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [6 x i8*], align 4 6493 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [6 x i8*], align 4 6494 // CHECK7-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [6 x i64], align 4 6495 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6496 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6497 // CHECK7-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6498 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6499 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6500 // CHECK7-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6501 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6502 // CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6503 // CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 6504 // CHECK7-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 6505 // CHECK7-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 6506 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 6507 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6508 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 6509 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 6510 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 6511 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 6512 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 6513 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 6514 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6515 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 6516 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* 6517 // CHECK7-NEXT: [[FROMBOOL2:%.*]] = zext i1 [[TOBOOL]] to i8 6518 // CHECK7-NEXT: store i8 [[FROMBOOL2]], i8* [[CONV]], align 1 6519 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6520 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6521 // CHECK7-NEXT: [[TOBOOL3:%.*]] = trunc i8 [[TMP9]] to i1 6522 // CHECK7-NEXT: br i1 [[TOBOOL3]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6523 // CHECK7: omp_if.then: 6524 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6525 // CHECK7-NEXT: [[TMP10:%.*]] = mul nuw i32 2, [[TMP1]] 6526 // CHECK7-NEXT: [[TMP11:%.*]] = mul nuw i32 [[TMP10]], 2 6527 // CHECK7-NEXT: [[TMP12:%.*]] = sext i32 [[TMP11]] to i64 6528 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast [6 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 6529 // CHECK7-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP13]], i8* align 4 bitcast ([6 x i64]* @.offload_sizes.11 to i8*), i32 48, i1 false) 6530 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6531 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to %struct.S1** 6532 // CHECK7-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP15]], align 4 6533 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6534 // CHECK7-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to double** 6535 // CHECK7-NEXT: store double* [[A]], double** [[TMP17]], align 4 6536 // CHECK7-NEXT: [[TMP18:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6537 // CHECK7-NEXT: store i8* null, i8** [[TMP18]], align 4 6538 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6539 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 6540 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP20]], align 4 6541 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6542 // CHECK7-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 6543 // CHECK7-NEXT: store i32 [[TMP6]], i32* [[TMP22]], align 4 6544 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6545 // CHECK7-NEXT: store i8* null, i8** [[TMP23]], align 4 6546 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6547 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 6548 // CHECK7-NEXT: store i32 2, i32* [[TMP25]], align 4 6549 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6550 // CHECK7-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 6551 // CHECK7-NEXT: store i32 2, i32* [[TMP27]], align 4 6552 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6553 // CHECK7-NEXT: store i8* null, i8** [[TMP28]], align 4 6554 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6555 // CHECK7-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 6556 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP30]], align 4 6557 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6558 // CHECK7-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i32* 6559 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP32]], align 4 6560 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6561 // CHECK7-NEXT: store i8* null, i8** [[TMP33]], align 4 6562 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6563 // CHECK7-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 6564 // CHECK7-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 6565 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6566 // CHECK7-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 6567 // CHECK7-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 6568 // CHECK7-NEXT: [[TMP38:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6569 // CHECK7-NEXT: store i64 [[TMP12]], i64* [[TMP38]], align 4 6570 // CHECK7-NEXT: [[TMP39:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 6571 // CHECK7-NEXT: store i8* null, i8** [[TMP39]], align 4 6572 // CHECK7-NEXT: [[TMP40:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 5 6573 // CHECK7-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i32* 6574 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP41]], align 4 6575 // CHECK7-NEXT: [[TMP42:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 5 6576 // CHECK7-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32* 6577 // CHECK7-NEXT: store i32 [[TMP8]], i32* [[TMP43]], align 4 6578 // CHECK7-NEXT: [[TMP44:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 5 6579 // CHECK7-NEXT: store i8* null, i8** [[TMP44]], align 4 6580 // CHECK7-NEXT: [[TMP45:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6581 // CHECK7-NEXT: [[TMP46:%.*]] = getelementptr inbounds [6 x i8*], [6 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6582 // CHECK7-NEXT: [[TMP47:%.*]] = getelementptr inbounds [6 x i64], [6 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6583 // CHECK7-NEXT: [[TMP48:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6584 // CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP48]] to i1 6585 // CHECK7-NEXT: [[TMP49:%.*]] = select i1 [[TOBOOL4]], i32 0, i32 1 6586 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6587 // CHECK7-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 6588 // CHECK7-NEXT: store i32 1, i32* [[TMP50]], align 4 6589 // CHECK7-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 6590 // CHECK7-NEXT: store i32 6, i32* [[TMP51]], align 4 6591 // CHECK7-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 6592 // CHECK7-NEXT: store i8** [[TMP45]], i8*** [[TMP52]], align 4 6593 // CHECK7-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 6594 // CHECK7-NEXT: store i8** [[TMP46]], i8*** [[TMP53]], align 4 6595 // CHECK7-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 6596 // CHECK7-NEXT: store i64* [[TMP47]], i64** [[TMP54]], align 4 6597 // CHECK7-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 6598 // CHECK7-NEXT: store i64* getelementptr inbounds ([6 x i64], [6 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP55]], align 4 6599 // CHECK7-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 6600 // CHECK7-NEXT: store i8** null, i8*** [[TMP56]], align 4 6601 // CHECK7-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 6602 // CHECK7-NEXT: store i8** null, i8*** [[TMP57]], align 4 6603 // CHECK7-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 6604 // CHECK7-NEXT: store i64 0, i64* [[TMP58]], align 8 6605 // CHECK7-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 [[TMP49]], i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 6606 // CHECK7-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 6607 // CHECK7-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6608 // CHECK7: omp_offload.failed: 6609 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6610 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6611 // CHECK7: omp_offload.cont: 6612 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6613 // CHECK7: omp_if.else: 6614 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214(%struct.S1* [[THIS1]], i32 [[TMP6]], i32 2, i32 [[TMP1]], i16* [[VLA]], i32 [[TMP8]]) #[[ATTR4]] 6615 // CHECK7-NEXT: br label [[OMP_IF_END]] 6616 // CHECK7: omp_if.end: 6617 // CHECK7-NEXT: [[TMP61:%.*]] = mul nsw i32 1, [[TMP1]] 6618 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP61]] 6619 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6620 // CHECK7-NEXT: [[TMP62:%.*]] = load i16, i16* [[ARRAYIDX5]], align 2 6621 // CHECK7-NEXT: [[CONV6:%.*]] = sext i16 [[TMP62]] to i32 6622 // CHECK7-NEXT: [[TMP63:%.*]] = load i32, i32* [[B]], align 4 6623 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], [[TMP63]] 6624 // CHECK7-NEXT: [[TMP64:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 6625 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP64]]) 6626 // CHECK7-NEXT: ret i32 [[ADD7]] 6627 // 6628 // 6629 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici 6630 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 6631 // CHECK7-NEXT: entry: 6632 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6633 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6634 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6635 // CHECK7-NEXT: [[AAA:%.*]] = alloca i8, align 1 6636 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6637 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6638 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6639 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 6640 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 6641 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 6642 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 6643 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6644 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6645 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 6646 // CHECK7-NEXT: store i8 0, i8* [[AAA]], align 1 6647 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6648 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6649 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6650 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6651 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6652 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 6653 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6654 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 6655 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 6656 // CHECK7-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 6657 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 6658 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6659 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6660 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6661 // CHECK7: omp_if.then: 6662 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6663 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 6664 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 6665 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6666 // CHECK7-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 6667 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 6668 // CHECK7-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6669 // CHECK7-NEXT: store i8* null, i8** [[TMP11]], align 4 6670 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6671 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 6672 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 6673 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6674 // CHECK7-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 6675 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 6676 // CHECK7-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6677 // CHECK7-NEXT: store i8* null, i8** [[TMP16]], align 4 6678 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6679 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 6680 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 6681 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6682 // CHECK7-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 6683 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 6684 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6685 // CHECK7-NEXT: store i8* null, i8** [[TMP21]], align 4 6686 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6687 // CHECK7-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 6688 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 6689 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6690 // CHECK7-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 6691 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 6692 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 6693 // CHECK7-NEXT: store i8* null, i8** [[TMP26]], align 4 6694 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6695 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6696 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6697 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 6698 // CHECK7-NEXT: store i32 1, i32* [[TMP29]], align 4 6699 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 6700 // CHECK7-NEXT: store i32 4, i32* [[TMP30]], align 4 6701 // CHECK7-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 6702 // CHECK7-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4 6703 // CHECK7-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 6704 // CHECK7-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 4 6705 // CHECK7-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 6706 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 4 6707 // CHECK7-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 6708 // CHECK7-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 4 6709 // CHECK7-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 6710 // CHECK7-NEXT: store i8** null, i8*** [[TMP35]], align 4 6711 // CHECK7-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 6712 // CHECK7-NEXT: store i8** null, i8*** [[TMP36]], align 4 6713 // CHECK7-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 6714 // CHECK7-NEXT: store i64 0, i64* [[TMP37]], align 8 6715 // CHECK7-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 6716 // CHECK7-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 6717 // CHECK7-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6718 // CHECK7: omp_offload.failed: 6719 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6720 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6721 // CHECK7: omp_offload.cont: 6722 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6723 // CHECK7: omp_if.else: 6724 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6725 // CHECK7-NEXT: br label [[OMP_IF_END]] 6726 // CHECK7: omp_if.end: 6727 // CHECK7-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 6728 // CHECK7-NEXT: ret i32 [[TMP40]] 6729 // 6730 // 6731 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6732 // CHECK7-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 6733 // CHECK7-NEXT: entry: 6734 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6735 // CHECK7-NEXT: [[A:%.*]] = alloca i32, align 4 6736 // CHECK7-NEXT: [[AA:%.*]] = alloca i16, align 2 6737 // CHECK7-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6738 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 6739 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 6740 // CHECK7-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 6741 // CHECK7-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 6742 // CHECK7-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 6743 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6744 // CHECK7-NEXT: store i32 0, i32* [[A]], align 4 6745 // CHECK7-NEXT: store i16 0, i16* [[AA]], align 2 6746 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6747 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 6748 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 6749 // CHECK7-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6750 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 6751 // CHECK7-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 6752 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 6753 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6754 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6755 // CHECK7-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6756 // CHECK7: omp_if.then: 6757 // CHECK7-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6758 // CHECK7-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 6759 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 6760 // CHECK7-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6761 // CHECK7-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 6762 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 6763 // CHECK7-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 6764 // CHECK7-NEXT: store i8* null, i8** [[TMP9]], align 4 6765 // CHECK7-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6766 // CHECK7-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 6767 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 6768 // CHECK7-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6769 // CHECK7-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 6770 // CHECK7-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 6771 // CHECK7-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 6772 // CHECK7-NEXT: store i8* null, i8** [[TMP14]], align 4 6773 // CHECK7-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6774 // CHECK7-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 6775 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 6776 // CHECK7-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6777 // CHECK7-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 6778 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 6779 // CHECK7-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 6780 // CHECK7-NEXT: store i8* null, i8** [[TMP19]], align 4 6781 // CHECK7-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6782 // CHECK7-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6783 // CHECK7-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 6784 // CHECK7-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 6785 // CHECK7-NEXT: store i32 1, i32* [[TMP22]], align 4 6786 // CHECK7-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 6787 // CHECK7-NEXT: store i32 3, i32* [[TMP23]], align 4 6788 // CHECK7-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 6789 // CHECK7-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4 6790 // CHECK7-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 6791 // CHECK7-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 4 6792 // CHECK7-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 6793 // CHECK7-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 4 6794 // CHECK7-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 6795 // CHECK7-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 4 6796 // CHECK7-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 6797 // CHECK7-NEXT: store i8** null, i8*** [[TMP28]], align 4 6798 // CHECK7-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 6799 // CHECK7-NEXT: store i8** null, i8*** [[TMP29]], align 4 6800 // CHECK7-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 6801 // CHECK7-NEXT: store i64 0, i64* [[TMP30]], align 8 6802 // CHECK7-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB2]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 6803 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 6804 // CHECK7-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6805 // CHECK7: omp_offload.failed: 6806 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6807 // CHECK7-NEXT: br label [[OMP_OFFLOAD_CONT]] 6808 // CHECK7: omp_offload.cont: 6809 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6810 // CHECK7: omp_if.else: 6811 // CHECK7-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6812 // CHECK7-NEXT: br label [[OMP_IF_END]] 6813 // CHECK7: omp_if.end: 6814 // CHECK7-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4 6815 // CHECK7-NEXT: ret i32 [[TMP33]] 6816 // 6817 // 6818 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 6819 // CHECK7-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2]] { 6820 // CHECK7-NEXT: entry: 6821 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6822 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6823 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6824 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6825 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6826 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6827 // CHECK7-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 6828 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 6829 // CHECK7-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 6830 // CHECK7-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 6831 // CHECK7-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 6832 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6833 // CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6834 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6835 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6836 // CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6837 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6838 // CHECK7-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6839 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6840 // CHECK7-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6841 // CHECK7-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6842 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 6843 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 6844 // CHECK7-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 6845 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 6846 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1 6847 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 6848 // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* 6849 // CHECK7-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 6850 // CHECK7-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 6851 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 6852 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1 6853 // CHECK7-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 6854 // CHECK7-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6855 // CHECK7: omp_if.then: 6856 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) 6857 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6858 // CHECK7: omp_if.else: 6859 // CHECK7-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 6860 // CHECK7-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 6861 // CHECK7-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 6862 // CHECK7-NEXT: call void @.omp_outlined..10(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR4]] 6863 // CHECK7-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 6864 // CHECK7-NEXT: br label [[OMP_IF_END]] 6865 // CHECK7: omp_if.end: 6866 // CHECK7-NEXT: ret void 6867 // 6868 // 6869 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..10 6870 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR3]] { 6871 // CHECK7-NEXT: entry: 6872 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 6873 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 6874 // CHECK7-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 6875 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 6876 // CHECK7-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 6877 // CHECK7-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 6878 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 6879 // CHECK7-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 6880 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6881 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 6882 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6883 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6884 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6885 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6886 // CHECK7-NEXT: [[IT:%.*]] = alloca i64, align 8 6887 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 6888 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 6889 // CHECK7-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 6890 // CHECK7-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 6891 // CHECK7-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 6892 // CHECK7-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 6893 // CHECK7-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 6894 // CHECK7-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 6895 // CHECK7-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 6896 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 6897 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 6898 // CHECK7-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 6899 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 6900 // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6901 // CHECK7-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 6902 // CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6903 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6904 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 6905 // CHECK7-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 6906 // CHECK7-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6907 // CHECK7: omp_if.then: 6908 // CHECK7-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6909 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 6910 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6911 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6912 // CHECK7-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 6913 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6914 // CHECK7: cond.true: 6915 // CHECK7-NEXT: br label [[COND_END:%.*]] 6916 // CHECK7: cond.false: 6917 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6918 // CHECK7-NEXT: br label [[COND_END]] 6919 // CHECK7: cond.end: 6920 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 6921 // CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6922 // CHECK7-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6923 // CHECK7-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 6924 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6925 // CHECK7: omp.inner.for.cond: 6926 // CHECK7-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39:![0-9]+]] 6927 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP39]] 6928 // CHECK7-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 6929 // CHECK7-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6930 // CHECK7: omp.inner.for.body: 6931 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6932 // CHECK7-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 6933 // CHECK7-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 6934 // CHECK7-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP39]] 6935 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP39]] 6936 // CHECK7-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double 6937 // CHECK7-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 6938 // CHECK7-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6939 // CHECK7-NEXT: store double [[ADD]], double* [[A]], align 4, !nontemporal !40, !llvm.access.group [[ACC_GRP39]] 6940 // CHECK7-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6941 // CHECK7-NEXT: [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !40, !llvm.access.group [[ACC_GRP39]] 6942 // CHECK7-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 6943 // CHECK7-NEXT: store double [[INC]], double* [[A5]], align 4, !nontemporal !40, !llvm.access.group [[ACC_GRP39]] 6944 // CHECK7-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 6945 // CHECK7-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 6946 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]] 6947 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 6948 // CHECK7-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP39]] 6949 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6950 // CHECK7: omp.body.continue: 6951 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6952 // CHECK7: omp.inner.for.inc: 6953 // CHECK7-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6954 // CHECK7-NEXT: [[ADD8:%.*]] = add i64 [[TMP16]], 1 6955 // CHECK7-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP39]] 6956 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP41:![0-9]+]] 6957 // CHECK7: omp.inner.for.end: 6958 // CHECK7-NEXT: br label [[OMP_IF_END:%.*]] 6959 // CHECK7: omp_if.else: 6960 // CHECK7-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 6961 // CHECK7-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 6962 // CHECK7-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 6963 // CHECK7-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6964 // CHECK7-NEXT: [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3 6965 // CHECK7-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] 6966 // CHECK7: cond.true10: 6967 // CHECK7-NEXT: br label [[COND_END12:%.*]] 6968 // CHECK7: cond.false11: 6969 // CHECK7-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6970 // CHECK7-NEXT: br label [[COND_END12]] 6971 // CHECK7: cond.end12: 6972 // CHECK7-NEXT: [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ] 6973 // CHECK7-NEXT: store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8 6974 // CHECK7-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6975 // CHECK7-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 6976 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND14:%.*]] 6977 // CHECK7: omp.inner.for.cond14: 6978 // CHECK7-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6979 // CHECK7-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6980 // CHECK7-NEXT: [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 6981 // CHECK7-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]] 6982 // CHECK7: omp.inner.for.body16: 6983 // CHECK7-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6984 // CHECK7-NEXT: [[MUL17:%.*]] = mul i64 [[TMP24]], 400 6985 // CHECK7-NEXT: [[SUB18:%.*]] = sub i64 2000, [[MUL17]] 6986 // CHECK7-NEXT: store i64 [[SUB18]], i64* [[IT]], align 8 6987 // CHECK7-NEXT: [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4 6988 // CHECK7-NEXT: [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double 6989 // CHECK7-NEXT: [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00 6990 // CHECK7-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6991 // CHECK7-NEXT: store double [[ADD20]], double* [[A21]], align 4 6992 // CHECK7-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6993 // CHECK7-NEXT: [[TMP26:%.*]] = load double, double* [[A22]], align 4 6994 // CHECK7-NEXT: [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00 6995 // CHECK7-NEXT: store double [[INC23]], double* [[A22]], align 4 6996 // CHECK7-NEXT: [[CONV24:%.*]] = fptosi double [[INC23]] to i16 6997 // CHECK7-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 6998 // CHECK7-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]] 6999 // CHECK7-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1 7000 // CHECK7-NEXT: store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2 7001 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] 7002 // CHECK7: omp.body.continue27: 7003 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] 7004 // CHECK7: omp.inner.for.inc28: 7005 // CHECK7-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7006 // CHECK7-NEXT: [[ADD29:%.*]] = add i64 [[TMP28]], 1 7007 // CHECK7-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8 7008 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP43:![0-9]+]] 7009 // CHECK7: omp.inner.for.end30: 7010 // CHECK7-NEXT: br label [[OMP_IF_END]] 7011 // CHECK7: omp_if.end: 7012 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7013 // CHECK7: omp.loop.exit: 7014 // CHECK7-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7015 // CHECK7-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 7016 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 7017 // CHECK7-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7018 // CHECK7-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 7019 // CHECK7-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7020 // CHECK7: .omp.final.then: 7021 // CHECK7-NEXT: store i64 400, i64* [[IT]], align 8 7022 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 7023 // CHECK7: .omp.final.done: 7024 // CHECK7-NEXT: ret void 7025 // 7026 // 7027 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 7028 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 7029 // CHECK7-NEXT: entry: 7030 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7031 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7032 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 7033 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7034 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7035 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7036 // CHECK7-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 7037 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7038 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7039 // CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 7040 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7041 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7042 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 7043 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7044 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7045 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 7046 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 7047 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 7048 // CHECK7-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7049 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 7050 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7051 // CHECK7-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 7052 // CHECK7-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 7053 // CHECK7-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 7054 // CHECK7-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 7055 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 7056 // CHECK7-NEXT: ret void 7057 // 7058 // 7059 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..13 7060 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 7061 // CHECK7-NEXT: entry: 7062 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7063 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7064 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7065 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7066 // CHECK7-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 7067 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7068 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7069 // CHECK7-NEXT: [[TMP:%.*]] = alloca i32, align 4 7070 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7071 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7072 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7073 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7074 // CHECK7-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 7075 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7076 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7077 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 7078 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7079 // CHECK7-NEXT: ret void 7080 // 7081 // 7082 // CHECK7-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 7083 // CHECK7-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 7084 // CHECK7-NEXT: entry: 7085 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7086 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7087 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7088 // CHECK7-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7089 // CHECK7-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7090 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7091 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7092 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7093 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7094 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7095 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 7096 // CHECK7-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 7097 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 7098 // CHECK7-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 7099 // CHECK7-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7100 // CHECK7-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 7101 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7102 // CHECK7-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 7103 // CHECK7-NEXT: ret void 7104 // 7105 // 7106 // CHECK7-LABEL: define {{[^@]+}}@.omp_outlined..16 7107 // CHECK7-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 7108 // CHECK7-NEXT: entry: 7109 // CHECK7-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 7110 // CHECK7-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 7111 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 7112 // CHECK7-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 7113 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 7114 // CHECK7-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7115 // CHECK7-NEXT: [[TMP:%.*]] = alloca i64, align 4 7116 // CHECK7-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7117 // CHECK7-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7118 // CHECK7-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7119 // CHECK7-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7120 // CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 7121 // CHECK7-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 7122 // CHECK7-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 7123 // CHECK7-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 7124 // CHECK7-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 7125 // CHECK7-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 7126 // CHECK7-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 7127 // CHECK7-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 7128 // CHECK7-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7129 // CHECK7-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 7130 // CHECK7-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7131 // CHECK7-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7132 // CHECK7-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 7133 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 7134 // CHECK7-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7135 // CHECK7-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7136 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 7137 // CHECK7-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7138 // CHECK7: cond.true: 7139 // CHECK7-NEXT: br label [[COND_END:%.*]] 7140 // CHECK7: cond.false: 7141 // CHECK7-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7142 // CHECK7-NEXT: br label [[COND_END]] 7143 // CHECK7: cond.end: 7144 // CHECK7-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 7145 // CHECK7-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7146 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7147 // CHECK7-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 7148 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7149 // CHECK7: omp.inner.for.cond: 7150 // CHECK7-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45:![0-9]+]] 7151 // CHECK7-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP45]] 7152 // CHECK7-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 7153 // CHECK7-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7154 // CHECK7: omp.inner.for.body: 7155 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 7156 // CHECK7-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 7157 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7158 // CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP45]] 7159 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] 7160 // CHECK7-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 7161 // CHECK7-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP45]] 7162 // CHECK7-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP45]] 7163 // CHECK7-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 7164 // CHECK7-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 7165 // CHECK7-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 7166 // CHECK7-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP45]] 7167 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 7168 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] 7169 // CHECK7-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 7170 // CHECK7-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP45]] 7171 // CHECK7-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7172 // CHECK7: omp.body.continue: 7173 // CHECK7-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7174 // CHECK7: omp.inner.for.inc: 7175 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 7176 // CHECK7-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 7177 // CHECK7-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP45]] 7178 // CHECK7-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP46:![0-9]+]] 7179 // CHECK7: omp.inner.for.end: 7180 // CHECK7-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7181 // CHECK7: omp.loop.exit: 7182 // CHECK7-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 7183 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 7184 // CHECK7-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 7185 // CHECK7-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 7186 // CHECK7: .omp.final.then: 7187 // CHECK7-NEXT: store i64 11, i64* [[I]], align 8 7188 // CHECK7-NEXT: br label [[DOTOMP_FINAL_DONE]] 7189 // CHECK7: .omp.final.done: 7190 // CHECK7-NEXT: ret void 7191 // 7192 // 7193 // CHECK7-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 7194 // CHECK7-SAME: () #[[ATTR8:[0-9]+]] { 7195 // CHECK7-NEXT: entry: 7196 // CHECK7-NEXT: call void @__tgt_register_requires(i64 1) 7197 // CHECK7-NEXT: ret void 7198 // 7199 // 7200 // CHECK9-LABEL: define {{[^@]+}}@_Z7get_valv 7201 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 7202 // CHECK9-NEXT: entry: 7203 // CHECK9-NEXT: ret i64 0 7204 // 7205 // 7206 // CHECK9-LABEL: define {{[^@]+}}@_Z3fooi 7207 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7208 // CHECK9-NEXT: entry: 7209 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7210 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7211 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7212 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7213 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7214 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7215 // CHECK9-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7216 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7217 // CHECK9-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7218 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7219 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7220 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7221 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7222 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7223 // CHECK9-NEXT: [[K:%.*]] = alloca i64, align 8 7224 // CHECK9-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7225 // CHECK9-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7226 // CHECK9-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7227 // CHECK9-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7228 // CHECK9-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7229 // CHECK9-NEXT: [[I7:%.*]] = alloca i32, align 4 7230 // CHECK9-NEXT: [[K8:%.*]] = alloca i64, align 8 7231 // CHECK9-NEXT: [[LIN:%.*]] = alloca i32, align 4 7232 // CHECK9-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 7233 // CHECK9-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7234 // CHECK9-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7235 // CHECK9-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7236 // CHECK9-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7237 // CHECK9-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7238 // CHECK9-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7239 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7240 // CHECK9-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7241 // CHECK9-NEXT: [[A28:%.*]] = alloca i32, align 4 7242 // CHECK9-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7243 // CHECK9-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7244 // CHECK9-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7245 // CHECK9-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7246 // CHECK9-NEXT: [[IT53:%.*]] = alloca i16, align 2 7247 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7248 // CHECK9-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7249 // CHECK9-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7250 // CHECK9-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7251 // CHECK9-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7252 // CHECK9-NEXT: [[IT72:%.*]] = alloca i8, align 1 7253 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7254 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7255 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 7256 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7257 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 7258 // CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 7259 // CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 7260 // CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 7261 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 7262 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 7263 // CHECK9-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 7264 // CHECK9-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 7265 // CHECK9-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 7266 // CHECK9-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 7267 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7268 // CHECK9-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 7269 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7270 // CHECK9-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 7271 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7272 // CHECK9: omp.inner.for.cond: 7273 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 7274 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 7275 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 7276 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7277 // CHECK9: omp.inner.for.body: 7278 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7279 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 7280 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7281 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 7282 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7283 // CHECK9: omp.body.continue: 7284 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7285 // CHECK9: omp.inner.for.inc: 7286 // CHECK9-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7287 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 7288 // CHECK9-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 7289 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 7290 // CHECK9: omp.inner.for.end: 7291 // CHECK9-NEXT: store i32 33, i32* [[I]], align 4 7292 // CHECK9-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7293 // CHECK9-NEXT: store i64 [[CALL]], i64* [[K]], align 8 7294 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 7295 // CHECK9-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 7296 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 7297 // CHECK9-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4 7298 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8 7299 // CHECK9-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8 7300 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7301 // CHECK9: omp.inner.for.cond9: 7302 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 7303 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] 7304 // CHECK9-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 7305 // CHECK9-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7306 // CHECK9: omp.inner.for.body11: 7307 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7308 // CHECK9-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 7309 // CHECK9-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7310 // CHECK9-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] 7311 // CHECK9-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]] 7312 // CHECK9-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7313 // CHECK9-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 7314 // CHECK9-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7315 // CHECK9-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 7316 // CHECK9-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group [[ACC_GRP6]] 7317 // CHECK9-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 7318 // CHECK9-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 7319 // CHECK9-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 7320 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7321 // CHECK9: omp.body.continue16: 7322 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7323 // CHECK9: omp.inner.for.inc17: 7324 // CHECK9-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7325 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 7326 // CHECK9-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 7327 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 7328 // CHECK9: omp.inner.for.end19: 7329 // CHECK9-NEXT: store i32 1, i32* [[I7]], align 4 7330 // CHECK9-NEXT: [[TMP20:%.*]] = load i64, i64* [[K8]], align 8 7331 // CHECK9-NEXT: store i64 [[TMP20]], i64* [[K]], align 8 7332 // CHECK9-NEXT: store i32 12, i32* [[LIN]], align 4 7333 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 7334 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 7335 // CHECK9-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 7336 // CHECK9-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV23]], align 8 7337 // CHECK9-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4 7338 // CHECK9-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START24]], align 4 7339 // CHECK9-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 7340 // CHECK9-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START25]], align 4 7341 // CHECK9-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7342 // CHECK9-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 7343 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7344 // CHECK9: omp.inner.for.cond29: 7345 // CHECK9-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]] 7346 // CHECK9-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]] 7347 // CHECK9-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 7348 // CHECK9-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7349 // CHECK9: omp.inner.for.body31: 7350 // CHECK9-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7351 // CHECK9-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 7352 // CHECK9-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7353 // CHECK9-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP9]] 7354 // CHECK9-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]] 7355 // CHECK9-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 7356 // CHECK9-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7357 // CHECK9-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 7358 // CHECK9-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 7359 // CHECK9-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7360 // CHECK9-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7361 // CHECK9-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]] 7362 // CHECK9-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]] 7363 // CHECK9-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 7364 // CHECK9-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7365 // CHECK9-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 7366 // CHECK9-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 7367 // CHECK9-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7368 // CHECK9-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7369 // CHECK9-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group [[ACC_GRP9]] 7370 // CHECK9-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 7371 // CHECK9-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 7372 // CHECK9-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7373 // CHECK9-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7374 // CHECK9-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 7375 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7376 // CHECK9: omp.body.continue45: 7377 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7378 // CHECK9: omp.inner.for.inc46: 7379 // CHECK9-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7380 // CHECK9-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 7381 // CHECK9-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 7382 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 7383 // CHECK9: omp.inner.for.end48: 7384 // CHECK9-NEXT: store i64 400, i64* [[IT]], align 8 7385 // CHECK9-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN27]], align 4 7386 // CHECK9-NEXT: store i32 [[TMP35]], i32* [[LIN]], align 4 7387 // CHECK9-NEXT: [[TMP36:%.*]] = load i32, i32* [[A28]], align 4 7388 // CHECK9-NEXT: store i32 [[TMP36]], i32* [[A]], align 4 7389 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 7390 // CHECK9-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 7391 // CHECK9-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 7392 // CHECK9-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV52]], align 4 7393 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7394 // CHECK9: omp.inner.for.cond54: 7395 // CHECK9-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 7396 // CHECK9-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]] 7397 // CHECK9-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 7398 // CHECK9-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7399 // CHECK9: omp.inner.for.body56: 7400 // CHECK9-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7401 // CHECK9-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 7402 // CHECK9-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7403 // CHECK9-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7404 // CHECK9-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]] 7405 // CHECK9-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7406 // CHECK9-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 7407 // CHECK9-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 7408 // CHECK9-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7409 // CHECK9-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 7410 // CHECK9-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7411 // CHECK9-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7412 // CHECK9-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 7413 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7414 // CHECK9: omp.body.continue64: 7415 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7416 // CHECK9: omp.inner.for.inc65: 7417 // CHECK9-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7418 // CHECK9-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 7419 // CHECK9-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 7420 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 7421 // CHECK9: omp.inner.for.end67: 7422 // CHECK9-NEXT: store i16 22, i16* [[IT53]], align 2 7423 // CHECK9-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 7424 // CHECK9-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 7425 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 7426 // CHECK9-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 7427 // CHECK9-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 7428 // CHECK9-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV71]], align 4 7429 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7430 // CHECK9: omp.inner.for.cond73: 7431 // CHECK9-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 7432 // CHECK9-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]] 7433 // CHECK9-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 7434 // CHECK9-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7435 // CHECK9: omp.inner.for.body75: 7436 // CHECK9-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7437 // CHECK9-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 7438 // CHECK9-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7439 // CHECK9-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7440 // CHECK9-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]] 7441 // CHECK9-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7442 // CHECK9-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 7443 // CHECK9-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 7444 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 7445 // CHECK9-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 7446 // CHECK9-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 7447 // CHECK9-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7448 // CHECK9-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7449 // CHECK9-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 7450 // CHECK9-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 7451 // CHECK9-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 7452 // CHECK9-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 7453 // CHECK9-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7454 // CHECK9-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7455 // CHECK9-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 7456 // CHECK9-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 7457 // CHECK9-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i64 0, i64 2 7458 // CHECK9-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 7459 // CHECK9-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 7460 // CHECK9-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 7461 // CHECK9-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 7462 // CHECK9-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP53]] 7463 // CHECK9-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i64 3 7464 // CHECK9-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 7465 // CHECK9-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 7466 // CHECK9-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 7467 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 7468 // CHECK9-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 7469 // CHECK9-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 7470 // CHECK9-NEXT: store i64 [[ADD93]], i64* [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 7471 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 7472 // CHECK9-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 7473 // CHECK9-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 7474 // CHECK9-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7475 // CHECK9-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7476 // CHECK9-NEXT: store i8 [[CONV96]], i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 7477 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7478 // CHECK9: omp.body.continue97: 7479 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7480 // CHECK9: omp.inner.for.inc98: 7481 // CHECK9-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7482 // CHECK9-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 7483 // CHECK9-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 7484 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 7485 // CHECK9: omp.inner.for.end100: 7486 // CHECK9-NEXT: store i8 96, i8* [[IT72]], align 1 7487 // CHECK9-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4 7488 // CHECK9-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7489 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP59]]) 7490 // CHECK9-NEXT: ret i32 [[TMP58]] 7491 // 7492 // 7493 // CHECK9-LABEL: define {{[^@]+}}@_Z3bari 7494 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7495 // CHECK9-NEXT: entry: 7496 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7497 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7498 // CHECK9-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 7499 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7500 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7501 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7502 // CHECK9-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 7503 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 7504 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7505 // CHECK9-NEXT: store i32 [[ADD]], i32* [[A]], align 4 7506 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7507 // CHECK9-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 7508 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 7509 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7510 // CHECK9-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 7511 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7512 // CHECK9-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 7513 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 7514 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7515 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 7516 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7517 // CHECK9-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 7518 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7519 // CHECK9-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7520 // CHECK9-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 7521 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7522 // CHECK9-NEXT: ret i32 [[TMP8]] 7523 // 7524 // 7525 // CHECK9-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7526 // CHECK9-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7527 // CHECK9-NEXT: entry: 7528 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7529 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7530 // CHECK9-NEXT: [[B:%.*]] = alloca i32, align 4 7531 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7532 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7533 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7534 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7535 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7536 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7537 // CHECK9-NEXT: [[IT:%.*]] = alloca i64, align 8 7538 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7539 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7540 // CHECK9-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7541 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7542 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7543 // CHECK9-NEXT: store i32 [[ADD]], i32* [[B]], align 4 7544 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7545 // CHECK9-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7546 // CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 7547 // CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 7548 // CHECK9-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 7549 // CHECK9-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 7550 // CHECK9-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 7551 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7552 // CHECK9-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 7553 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7554 // CHECK9-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 7555 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7556 // CHECK9: omp.inner.for.cond: 7557 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 7558 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 7559 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP6]], [[TMP7]] 7560 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7561 // CHECK9: omp.inner.for.body: 7562 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7563 // CHECK9-NEXT: [[MUL:%.*]] = mul i64 [[TMP8]], 400 7564 // CHECK9-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 7565 // CHECK9-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 7566 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group [[ACC_GRP18]] 7567 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP9]] to double 7568 // CHECK9-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 7569 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 7570 // CHECK9-NEXT: store double [[ADD2]], double* [[A]], align 8, !llvm.access.group [[ACC_GRP18]] 7571 // CHECK9-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 7572 // CHECK9-NEXT: [[TMP10:%.*]] = load double, double* [[A3]], align 8, !llvm.access.group [[ACC_GRP18]] 7573 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP10]], 1.000000e+00 7574 // CHECK9-NEXT: store double [[INC]], double* [[A3]], align 8, !llvm.access.group [[ACC_GRP18]] 7575 // CHECK9-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 7576 // CHECK9-NEXT: [[TMP11:%.*]] = mul nsw i64 1, [[TMP2]] 7577 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP11]] 7578 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7579 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP18]] 7580 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7581 // CHECK9: omp.body.continue: 7582 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7583 // CHECK9: omp.inner.for.inc: 7584 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7585 // CHECK9-NEXT: [[ADD6:%.*]] = add i64 [[TMP12]], 1 7586 // CHECK9-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 7587 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 7588 // CHECK9: omp.inner.for.end: 7589 // CHECK9-NEXT: store i64 400, i64* [[IT]], align 8 7590 // CHECK9-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 7591 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] 7592 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i64 1 7593 // CHECK9-NEXT: [[TMP14:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 7594 // CHECK9-NEXT: [[CONV9:%.*]] = sext i16 [[TMP14]] to i32 7595 // CHECK9-NEXT: [[TMP15:%.*]] = load i32, i32* [[B]], align 4 7596 // CHECK9-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP15]] 7597 // CHECK9-NEXT: [[TMP16:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7598 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP16]]) 7599 // CHECK9-NEXT: ret i32 [[ADD10]] 7600 // 7601 // 7602 // CHECK9-LABEL: define {{[^@]+}}@_ZL7fstatici 7603 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7604 // CHECK9-NEXT: entry: 7605 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7606 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7607 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7608 // CHECK9-NEXT: [[AAA:%.*]] = alloca i8, align 1 7609 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7610 // CHECK9-NEXT: [[TMP:%.*]] = alloca i32, align 4 7611 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7612 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7613 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7614 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7615 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 7616 // CHECK9-NEXT: store i8 0, i8* [[AAA]], align 1 7617 // CHECK9-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7618 // CHECK9-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 7619 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7620 // CHECK9-NEXT: ret i32 [[TMP0]] 7621 // 7622 // 7623 // CHECK9-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7624 // CHECK9-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 7625 // CHECK9-NEXT: entry: 7626 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7627 // CHECK9-NEXT: [[A:%.*]] = alloca i32, align 4 7628 // CHECK9-NEXT: [[AA:%.*]] = alloca i16, align 2 7629 // CHECK9-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7630 // CHECK9-NEXT: [[TMP:%.*]] = alloca i64, align 8 7631 // CHECK9-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7632 // CHECK9-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7633 // CHECK9-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7634 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7635 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7636 // CHECK9-NEXT: store i32 0, i32* [[A]], align 4 7637 // CHECK9-NEXT: store i16 0, i16* [[AA]], align 2 7638 // CHECK9-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7639 // CHECK9-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 7640 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7641 // CHECK9-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 7642 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7643 // CHECK9: omp.inner.for.cond: 7644 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21:![0-9]+]] 7645 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP21]] 7646 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 7647 // CHECK9-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7648 // CHECK9: omp.inner.for.body: 7649 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7650 // CHECK9-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 7651 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 7652 // CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP21]] 7653 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP21]] 7654 // CHECK9-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 7655 // CHECK9-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP21]] 7656 // CHECK9-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP21]] 7657 // CHECK9-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 7658 // CHECK9-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 7659 // CHECK9-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 7660 // CHECK9-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP21]] 7661 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 7662 // CHECK9-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] 7663 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 7664 // CHECK9-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP21]] 7665 // CHECK9-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7666 // CHECK9: omp.body.continue: 7667 // CHECK9-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7668 // CHECK9: omp.inner.for.inc: 7669 // CHECK9-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7670 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 7671 // CHECK9-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP21]] 7672 // CHECK9-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 7673 // CHECK9: omp.inner.for.end: 7674 // CHECK9-NEXT: store i64 11, i64* [[I]], align 8 7675 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7676 // CHECK9-NEXT: ret i32 [[TMP8]] 7677 // 7678 // 7679 // CHECK11-LABEL: define {{[^@]+}}@_Z7get_valv 7680 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 7681 // CHECK11-NEXT: entry: 7682 // CHECK11-NEXT: ret i64 0 7683 // 7684 // 7685 // CHECK11-LABEL: define {{[^@]+}}@_Z3fooi 7686 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7687 // CHECK11-NEXT: entry: 7688 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7689 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7690 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 7691 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7692 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 7693 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7694 // CHECK11-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7695 // CHECK11-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 7696 // CHECK11-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 7697 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7698 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7699 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7700 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7701 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7702 // CHECK11-NEXT: [[K:%.*]] = alloca i64, align 8 7703 // CHECK11-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 7704 // CHECK11-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 7705 // CHECK11-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 7706 // CHECK11-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 7707 // CHECK11-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 7708 // CHECK11-NEXT: [[I7:%.*]] = alloca i32, align 4 7709 // CHECK11-NEXT: [[K8:%.*]] = alloca i64, align 8 7710 // CHECK11-NEXT: [[LIN:%.*]] = alloca i32, align 4 7711 // CHECK11-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 7712 // CHECK11-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 7713 // CHECK11-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 7714 // CHECK11-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 7715 // CHECK11-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 7716 // CHECK11-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 7717 // CHECK11-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 7718 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 7719 // CHECK11-NEXT: [[LIN27:%.*]] = alloca i32, align 4 7720 // CHECK11-NEXT: [[A28:%.*]] = alloca i32, align 4 7721 // CHECK11-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 7722 // CHECK11-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 7723 // CHECK11-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 7724 // CHECK11-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 7725 // CHECK11-NEXT: [[IT53:%.*]] = alloca i16, align 2 7726 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 7727 // CHECK11-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 7728 // CHECK11-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 7729 // CHECK11-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 7730 // CHECK11-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 7731 // CHECK11-NEXT: [[IT72:%.*]] = alloca i8, align 1 7732 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7733 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 7734 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 7735 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7736 // CHECK11-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 7737 // CHECK11-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 7738 // CHECK11-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 7739 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 7740 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7741 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 7742 // CHECK11-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 7743 // CHECK11-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 7744 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7745 // CHECK11-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 7746 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7747 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 7748 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7749 // CHECK11: omp.inner.for.cond: 7750 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 7751 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 7752 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 7753 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7754 // CHECK11: omp.inner.for.body: 7755 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7756 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 7757 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 7758 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 7759 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7760 // CHECK11: omp.body.continue: 7761 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7762 // CHECK11: omp.inner.for.inc: 7763 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7764 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 7765 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 7766 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7767 // CHECK11: omp.inner.for.end: 7768 // CHECK11-NEXT: store i32 33, i32* [[I]], align 4 7769 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 7770 // CHECK11-NEXT: store i64 [[CALL]], i64* [[K]], align 8 7771 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 7772 // CHECK11-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 7773 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 7774 // CHECK11-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4 7775 // CHECK11-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8 7776 // CHECK11-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8 7777 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 7778 // CHECK11: omp.inner.for.cond9: 7779 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 7780 // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]] 7781 // CHECK11-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 7782 // CHECK11-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 7783 // CHECK11: omp.inner.for.body11: 7784 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7785 // CHECK11-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 7786 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 7787 // CHECK11-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] 7788 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]] 7789 // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7790 // CHECK11-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 7791 // CHECK11-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 7792 // CHECK11-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 7793 // CHECK11-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group [[ACC_GRP7]] 7794 // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 7795 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 7796 // CHECK11-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 7797 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 7798 // CHECK11: omp.body.continue16: 7799 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 7800 // CHECK11: omp.inner.for.inc17: 7801 // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7802 // CHECK11-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 7803 // CHECK11-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 7804 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 7805 // CHECK11: omp.inner.for.end19: 7806 // CHECK11-NEXT: store i32 1, i32* [[I7]], align 4 7807 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[K8]], align 8 7808 // CHECK11-NEXT: store i64 [[TMP18]], i64* [[K]], align 8 7809 // CHECK11-NEXT: store i32 12, i32* [[LIN]], align 4 7810 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 7811 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 7812 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 7813 // CHECK11-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV23]], align 8 7814 // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4 7815 // CHECK11-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START24]], align 4 7816 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 7817 // CHECK11-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START25]], align 4 7818 // CHECK11-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 7819 // CHECK11-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 7820 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 7821 // CHECK11: omp.inner.for.cond29: 7822 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]] 7823 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]] 7824 // CHECK11-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 7825 // CHECK11-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 7826 // CHECK11: omp.inner.for.body31: 7827 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7828 // CHECK11-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 7829 // CHECK11-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 7830 // CHECK11-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP10]] 7831 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]] 7832 // CHECK11-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 7833 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7834 // CHECK11-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 7835 // CHECK11-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 7836 // CHECK11-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 7837 // CHECK11-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 7838 // CHECK11-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]] 7839 // CHECK11-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]] 7840 // CHECK11-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 7841 // CHECK11-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7842 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 7843 // CHECK11-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 7844 // CHECK11-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 7845 // CHECK11-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 7846 // CHECK11-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group [[ACC_GRP10]] 7847 // CHECK11-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 7848 // CHECK11-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 7849 // CHECK11-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 7850 // CHECK11-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 7851 // CHECK11-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 7852 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 7853 // CHECK11: omp.body.continue45: 7854 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 7855 // CHECK11: omp.inner.for.inc46: 7856 // CHECK11-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7857 // CHECK11-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 7858 // CHECK11-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 7859 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 7860 // CHECK11: omp.inner.for.end48: 7861 // CHECK11-NEXT: store i64 400, i64* [[IT]], align 8 7862 // CHECK11-NEXT: [[TMP33:%.*]] = load i32, i32* [[LIN27]], align 4 7863 // CHECK11-NEXT: store i32 [[TMP33]], i32* [[LIN]], align 4 7864 // CHECK11-NEXT: [[TMP34:%.*]] = load i32, i32* [[A28]], align 4 7865 // CHECK11-NEXT: store i32 [[TMP34]], i32* [[A]], align 4 7866 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 7867 // CHECK11-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 7868 // CHECK11-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 7869 // CHECK11-NEXT: store i32 [[TMP35]], i32* [[DOTOMP_IV52]], align 4 7870 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 7871 // CHECK11: omp.inner.for.cond54: 7872 // CHECK11-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 7873 // CHECK11-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]] 7874 // CHECK11-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 7875 // CHECK11-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 7876 // CHECK11: omp.inner.for.body56: 7877 // CHECK11-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7878 // CHECK11-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 7879 // CHECK11-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 7880 // CHECK11-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 7881 // CHECK11-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]] 7882 // CHECK11-NEXT: [[TMP39:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 7883 // CHECK11-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 7884 // CHECK11-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 7885 // CHECK11-NEXT: [[TMP40:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 7886 // CHECK11-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 7887 // CHECK11-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 7888 // CHECK11-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 7889 // CHECK11-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 7890 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 7891 // CHECK11: omp.body.continue64: 7892 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 7893 // CHECK11: omp.inner.for.inc65: 7894 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7895 // CHECK11-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 7896 // CHECK11-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 7897 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 7898 // CHECK11: omp.inner.for.end67: 7899 // CHECK11-NEXT: store i16 22, i16* [[IT53]], align 2 7900 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, i32* [[A]], align 4 7901 // CHECK11-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 7902 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 7903 // CHECK11-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 7904 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 7905 // CHECK11-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV71]], align 4 7906 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 7907 // CHECK11: omp.inner.for.cond73: 7908 // CHECK11-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 7909 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]] 7910 // CHECK11-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 7911 // CHECK11-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 7912 // CHECK11: omp.inner.for.body75: 7913 // CHECK11-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7914 // CHECK11-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 7915 // CHECK11-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 7916 // CHECK11-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 7917 // CHECK11-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]] 7918 // CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 7919 // CHECK11-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 7920 // CHECK11-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 7921 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 7922 // CHECK11-NEXT: [[TMP48:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 7923 // CHECK11-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 7924 // CHECK11-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 7925 // CHECK11-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 7926 // CHECK11-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 7927 // CHECK11-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 7928 // CHECK11-NEXT: [[TMP49:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 7929 // CHECK11-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 7930 // CHECK11-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 7931 // CHECK11-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 7932 // CHECK11-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 7933 // CHECK11-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 7934 // CHECK11-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i32 0, i32 2 7935 // CHECK11-NEXT: [[TMP50:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 7936 // CHECK11-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 7937 // CHECK11-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 7938 // CHECK11-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 7939 // CHECK11-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP51]] 7940 // CHECK11-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i32 3 7941 // CHECK11-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 7942 // CHECK11-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 7943 // CHECK11-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 7944 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 7945 // CHECK11-NEXT: [[TMP53:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 7946 // CHECK11-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 7947 // CHECK11-NEXT: store i64 [[ADD93]], i64* [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 7948 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 7949 // CHECK11-NEXT: [[TMP54:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 7950 // CHECK11-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 7951 // CHECK11-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 7952 // CHECK11-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 7953 // CHECK11-NEXT: store i8 [[CONV96]], i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 7954 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 7955 // CHECK11: omp.body.continue97: 7956 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 7957 // CHECK11: omp.inner.for.inc98: 7958 // CHECK11-NEXT: [[TMP55:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7959 // CHECK11-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 7960 // CHECK11-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 7961 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 7962 // CHECK11: omp.inner.for.end100: 7963 // CHECK11-NEXT: store i8 96, i8* [[IT72]], align 1 7964 // CHECK11-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 7965 // CHECK11-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 7966 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) 7967 // CHECK11-NEXT: ret i32 [[TMP56]] 7968 // 7969 // 7970 // CHECK11-LABEL: define {{[^@]+}}@_Z3bari 7971 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 7972 // CHECK11-NEXT: entry: 7973 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7974 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 7975 // CHECK11-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 7976 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7977 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 7978 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7979 // CHECK11-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 7980 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 7981 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7982 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A]], align 4 7983 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7984 // CHECK11-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 7985 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 7986 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7987 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 7988 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7989 // CHECK11-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 7990 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 7991 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7992 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 7993 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7994 // CHECK11-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 7995 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7996 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7997 // CHECK11-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 7998 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7999 // CHECK11-NEXT: ret i32 [[TMP8]] 8000 // 8001 // 8002 // CHECK11-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8003 // CHECK11-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8004 // CHECK11-NEXT: entry: 8005 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8006 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8007 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 8008 // CHECK11-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8009 // CHECK11-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8010 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 8011 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8012 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8013 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8014 // CHECK11-NEXT: [[IT:%.*]] = alloca i64, align 8 8015 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8016 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8017 // CHECK11-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8018 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8019 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8020 // CHECK11-NEXT: store i32 [[ADD]], i32* [[B]], align 4 8021 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8022 // CHECK11-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8023 // CHECK11-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 8024 // CHECK11-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 8025 // CHECK11-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 8026 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 8027 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8028 // CHECK11-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8029 // CHECK11-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8030 // CHECK11-NEXT: store i64 [[TMP4]], i64* [[DOTOMP_IV]], align 8 8031 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8032 // CHECK11: omp.inner.for.cond: 8033 // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]] 8034 // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]] 8035 // CHECK11-NEXT: [[CMP:%.*]] = icmp ule i64 [[TMP5]], [[TMP6]] 8036 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8037 // CHECK11: omp.inner.for.body: 8038 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8039 // CHECK11-NEXT: [[MUL:%.*]] = mul i64 [[TMP7]], 400 8040 // CHECK11-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8041 // CHECK11-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP19]] 8042 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group [[ACC_GRP19]] 8043 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP8]] to double 8044 // CHECK11-NEXT: [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00 8045 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8046 // CHECK11-NEXT: store double [[ADD2]], double* [[A]], align 4, !llvm.access.group [[ACC_GRP19]] 8047 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8048 // CHECK11-NEXT: [[TMP9:%.*]] = load double, double* [[A3]], align 4, !llvm.access.group [[ACC_GRP19]] 8049 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP9]], 1.000000e+00 8050 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4, !llvm.access.group [[ACC_GRP19]] 8051 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 8052 // CHECK11-NEXT: [[TMP10:%.*]] = mul nsw i32 1, [[TMP1]] 8053 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP10]] 8054 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8055 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2, !llvm.access.group [[ACC_GRP19]] 8056 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8057 // CHECK11: omp.body.continue: 8058 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8059 // CHECK11: omp.inner.for.inc: 8060 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8061 // CHECK11-NEXT: [[ADD6:%.*]] = add i64 [[TMP11]], 1 8062 // CHECK11-NEXT: store i64 [[ADD6]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 8063 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 8064 // CHECK11: omp.inner.for.end: 8065 // CHECK11-NEXT: store i64 400, i64* [[IT]], align 8 8066 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 8067 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] 8068 // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX7]], i32 1 8069 // CHECK11-NEXT: [[TMP13:%.*]] = load i16, i16* [[ARRAYIDX8]], align 2 8070 // CHECK11-NEXT: [[CONV9:%.*]] = sext i16 [[TMP13]] to i32 8071 // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[B]], align 4 8072 // CHECK11-NEXT: [[ADD10:%.*]] = add nsw i32 [[CONV9]], [[TMP14]] 8073 // CHECK11-NEXT: [[TMP15:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8074 // CHECK11-NEXT: call void @llvm.stackrestore(i8* [[TMP15]]) 8075 // CHECK11-NEXT: ret i32 [[ADD10]] 8076 // 8077 // 8078 // CHECK11-LABEL: define {{[^@]+}}@_ZL7fstatici 8079 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8080 // CHECK11-NEXT: entry: 8081 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8082 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 8083 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 8084 // CHECK11-NEXT: [[AAA:%.*]] = alloca i8, align 1 8085 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8086 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8087 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8088 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8089 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8090 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 8091 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 8092 // CHECK11-NEXT: store i8 0, i8* [[AAA]], align 1 8093 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8094 // CHECK11-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 8095 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8096 // CHECK11-NEXT: ret i32 [[TMP0]] 8097 // 8098 // 8099 // CHECK11-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8100 // CHECK11-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 8101 // CHECK11-NEXT: entry: 8102 // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8103 // CHECK11-NEXT: [[A:%.*]] = alloca i32, align 4 8104 // CHECK11-NEXT: [[AA:%.*]] = alloca i16, align 2 8105 // CHECK11-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8106 // CHECK11-NEXT: [[TMP:%.*]] = alloca i64, align 4 8107 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8108 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8109 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8110 // CHECK11-NEXT: [[I:%.*]] = alloca i64, align 8 8111 // CHECK11-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8112 // CHECK11-NEXT: store i32 0, i32* [[A]], align 4 8113 // CHECK11-NEXT: store i16 0, i16* [[AA]], align 2 8114 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8115 // CHECK11-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 8116 // CHECK11-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8117 // CHECK11-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 8118 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8119 // CHECK11: omp.inner.for.cond: 8120 // CHECK11-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22:![0-9]+]] 8121 // CHECK11-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP22]] 8122 // CHECK11-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8123 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8124 // CHECK11: omp.inner.for.body: 8125 // CHECK11-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 8126 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8127 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8128 // CHECK11-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP22]] 8129 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP22]] 8130 // CHECK11-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8131 // CHECK11-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP22]] 8132 // CHECK11-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP22]] 8133 // CHECK11-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8134 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8135 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8136 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP22]] 8137 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 8138 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 8139 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8140 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP22]] 8141 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8142 // CHECK11: omp.body.continue: 8143 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8144 // CHECK11: omp.inner.for.inc: 8145 // CHECK11-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 8146 // CHECK11-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 8147 // CHECK11-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP22]] 8148 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP23:![0-9]+]] 8149 // CHECK11: omp.inner.for.end: 8150 // CHECK11-NEXT: store i64 11, i64* [[I]], align 8 8151 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8152 // CHECK11-NEXT: ret i32 [[TMP8]] 8153 // 8154 // 8155 // CHECK13-LABEL: define {{[^@]+}}@_Z7get_valv 8156 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { 8157 // CHECK13-NEXT: entry: 8158 // CHECK13-NEXT: ret i64 0 8159 // 8160 // 8161 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi 8162 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8163 // CHECK13-NEXT: entry: 8164 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8165 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8166 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8167 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8168 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 8169 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8170 // CHECK13-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8171 // CHECK13-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 8172 // CHECK13-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 8173 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8174 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8175 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8176 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8177 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 8178 // CHECK13-NEXT: [[K:%.*]] = alloca i64, align 8 8179 // CHECK13-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 8180 // CHECK13-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 8181 // CHECK13-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 8182 // CHECK13-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 8183 // CHECK13-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 8184 // CHECK13-NEXT: [[I7:%.*]] = alloca i32, align 4 8185 // CHECK13-NEXT: [[K8:%.*]] = alloca i64, align 8 8186 // CHECK13-NEXT: [[LIN:%.*]] = alloca i32, align 4 8187 // CHECK13-NEXT: [[_TMP20:%.*]] = alloca i64, align 8 8188 // CHECK13-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 8189 // CHECK13-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 8190 // CHECK13-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 8191 // CHECK13-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 8192 // CHECK13-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 8193 // CHECK13-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8194 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 8195 // CHECK13-NEXT: [[LIN27:%.*]] = alloca i32, align 4 8196 // CHECK13-NEXT: [[A28:%.*]] = alloca i32, align 4 8197 // CHECK13-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 8198 // CHECK13-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 8199 // CHECK13-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 8200 // CHECK13-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 8201 // CHECK13-NEXT: [[IT53:%.*]] = alloca i16, align 2 8202 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8203 // CHECK13-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 8204 // CHECK13-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 8205 // CHECK13-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 8206 // CHECK13-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 8207 // CHECK13-NEXT: [[IT72:%.*]] = alloca i8, align 1 8208 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8209 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8210 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 8211 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8212 // CHECK13-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 8213 // CHECK13-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8214 // CHECK13-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 8215 // CHECK13-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4 8216 // CHECK13-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 8217 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 8218 // CHECK13-NEXT: [[TMP4:%.*]] = zext i32 [[TMP3]] to i64 8219 // CHECK13-NEXT: [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]] 8220 // CHECK13-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8 8221 // CHECK13-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8 8222 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8223 // CHECK13-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 8224 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8225 // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_IV]], align 4 8226 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8227 // CHECK13: omp.inner.for.cond: 8228 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2:![0-9]+]] 8229 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP2]] 8230 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP7]], [[TMP8]] 8231 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8232 // CHECK13: omp.inner.for.body: 8233 // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 8234 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP9]], 5 8235 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8236 // CHECK13-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP2]] 8237 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8238 // CHECK13: omp.body.continue: 8239 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8240 // CHECK13: omp.inner.for.inc: 8241 // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 8242 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP10]], 1 8243 // CHECK13-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP2]] 8244 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP3:![0-9]+]] 8245 // CHECK13: omp.inner.for.end: 8246 // CHECK13-NEXT: store i32 33, i32* [[I]], align 4 8247 // CHECK13-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 8248 // CHECK13-NEXT: store i64 [[CALL]], i64* [[K]], align 8 8249 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 8250 // CHECK13-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 8251 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 8252 // CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV6]], align 4 8253 // CHECK13-NEXT: [[TMP12:%.*]] = load i64, i64* [[K]], align 8 8254 // CHECK13-NEXT: store i64 [[TMP12]], i64* [[DOTLINEAR_START]], align 8 8255 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 8256 // CHECK13: omp.inner.for.cond9: 8257 // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6:![0-9]+]] 8258 // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP6]] 8259 // CHECK13-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 8260 // CHECK13-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8261 // CHECK13: omp.inner.for.body11: 8262 // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8263 // CHECK13-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP15]], 1 8264 // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 8265 // CHECK13-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group [[ACC_GRP6]] 8266 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP6]] 8267 // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8268 // CHECK13-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP17]], 3 8269 // CHECK13-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 8270 // CHECK13-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP16]], [[CONV]] 8271 // CHECK13-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group [[ACC_GRP6]] 8272 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 8273 // CHECK13-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP18]], 1 8274 // CHECK13-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP6]] 8275 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8276 // CHECK13: omp.body.continue16: 8277 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8278 // CHECK13: omp.inner.for.inc17: 8279 // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8280 // CHECK13-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP19]], 1 8281 // CHECK13-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP6]] 8282 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP7:![0-9]+]] 8283 // CHECK13: omp.inner.for.end19: 8284 // CHECK13-NEXT: store i32 1, i32* [[I7]], align 4 8285 // CHECK13-NEXT: [[TMP20:%.*]] = load i64, i64* [[K8]], align 8 8286 // CHECK13-NEXT: store i64 [[TMP20]], i64* [[K]], align 8 8287 // CHECK13-NEXT: store i32 12, i32* [[LIN]], align 4 8288 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 8289 // CHECK13-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 8290 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 8291 // CHECK13-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV23]], align 8 8292 // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN]], align 4 8293 // CHECK13-NEXT: store i32 [[TMP22]], i32* [[DOTLINEAR_START24]], align 4 8294 // CHECK13-NEXT: [[TMP23:%.*]] = load i32, i32* [[A]], align 4 8295 // CHECK13-NEXT: store i32 [[TMP23]], i32* [[DOTLINEAR_START25]], align 4 8296 // CHECK13-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 8297 // CHECK13-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 8298 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 8299 // CHECK13: omp.inner.for.cond29: 8300 // CHECK13-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9:![0-9]+]] 8301 // CHECK13-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP9]] 8302 // CHECK13-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP24]], [[TMP25]] 8303 // CHECK13-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 8304 // CHECK13: omp.inner.for.body31: 8305 // CHECK13-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8306 // CHECK13-NEXT: [[MUL32:%.*]] = mul i64 [[TMP26]], 400 8307 // CHECK13-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 8308 // CHECK13-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP9]] 8309 // CHECK13-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP9]] 8310 // CHECK13-NEXT: [[CONV34:%.*]] = sext i32 [[TMP27]] to i64 8311 // CHECK13-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8312 // CHECK13-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 8313 // CHECK13-NEXT: [[MUL35:%.*]] = mul i64 [[TMP28]], [[TMP29]] 8314 // CHECK13-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 8315 // CHECK13-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 8316 // CHECK13-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group [[ACC_GRP9]] 8317 // CHECK13-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP9]] 8318 // CHECK13-NEXT: [[CONV38:%.*]] = sext i32 [[TMP30]] to i64 8319 // CHECK13-NEXT: [[TMP31:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8320 // CHECK13-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP9]] 8321 // CHECK13-NEXT: [[MUL39:%.*]] = mul i64 [[TMP31]], [[TMP32]] 8322 // CHECK13-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 8323 // CHECK13-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 8324 // CHECK13-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group [[ACC_GRP9]] 8325 // CHECK13-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 8326 // CHECK13-NEXT: [[CONV42:%.*]] = sext i16 [[TMP33]] to i32 8327 // CHECK13-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 8328 // CHECK13-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 8329 // CHECK13-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP9]] 8330 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 8331 // CHECK13: omp.body.continue45: 8332 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 8333 // CHECK13: omp.inner.for.inc46: 8334 // CHECK13-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8335 // CHECK13-NEXT: [[ADD47:%.*]] = add i64 [[TMP34]], 1 8336 // CHECK13-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP9]] 8337 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP10:![0-9]+]] 8338 // CHECK13: omp.inner.for.end48: 8339 // CHECK13-NEXT: store i64 400, i64* [[IT]], align 8 8340 // CHECK13-NEXT: [[TMP35:%.*]] = load i32, i32* [[LIN27]], align 4 8341 // CHECK13-NEXT: store i32 [[TMP35]], i32* [[LIN]], align 4 8342 // CHECK13-NEXT: [[TMP36:%.*]] = load i32, i32* [[A28]], align 4 8343 // CHECK13-NEXT: store i32 [[TMP36]], i32* [[A]], align 4 8344 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 8345 // CHECK13-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 8346 // CHECK13-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 8347 // CHECK13-NEXT: store i32 [[TMP37]], i32* [[DOTOMP_IV52]], align 4 8348 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 8349 // CHECK13: omp.inner.for.cond54: 8350 // CHECK13-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 8351 // CHECK13-NEXT: [[TMP39:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP12]] 8352 // CHECK13-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP38]], [[TMP39]] 8353 // CHECK13-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 8354 // CHECK13: omp.inner.for.body56: 8355 // CHECK13-NEXT: [[TMP40:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 8356 // CHECK13-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP40]], 4 8357 // CHECK13-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 8358 // CHECK13-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 8359 // CHECK13-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group [[ACC_GRP12]] 8360 // CHECK13-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 8361 // CHECK13-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP41]], 1 8362 // CHECK13-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP12]] 8363 // CHECK13-NEXT: [[TMP42:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 8364 // CHECK13-NEXT: [[CONV61:%.*]] = sext i16 [[TMP42]] to i32 8365 // CHECK13-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 8366 // CHECK13-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 8367 // CHECK13-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP12]] 8368 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 8369 // CHECK13: omp.body.continue64: 8370 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 8371 // CHECK13: omp.inner.for.inc65: 8372 // CHECK13-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 8373 // CHECK13-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP43]], 1 8374 // CHECK13-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP12]] 8375 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP13:![0-9]+]] 8376 // CHECK13: omp.inner.for.end67: 8377 // CHECK13-NEXT: store i16 22, i16* [[IT53]], align 2 8378 // CHECK13-NEXT: [[TMP44:%.*]] = load i32, i32* [[A]], align 4 8379 // CHECK13-NEXT: store i32 [[TMP44]], i32* [[DOTCAPTURE_EXPR_]], align 4 8380 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 8381 // CHECK13-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 8382 // CHECK13-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 8383 // CHECK13-NEXT: store i32 [[TMP45]], i32* [[DOTOMP_IV71]], align 4 8384 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 8385 // CHECK13: omp.inner.for.cond73: 8386 // CHECK13-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15:![0-9]+]] 8387 // CHECK13-NEXT: [[TMP47:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP15]] 8388 // CHECK13-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP46]], [[TMP47]] 8389 // CHECK13-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 8390 // CHECK13: omp.inner.for.body75: 8391 // CHECK13-NEXT: [[TMP48:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8392 // CHECK13-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP48]], 1 8393 // CHECK13-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 8394 // CHECK13-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 8395 // CHECK13-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group [[ACC_GRP15]] 8396 // CHECK13-NEXT: [[TMP49:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 8397 // CHECK13-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP49]], 1 8398 // CHECK13-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP15]] 8399 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2 8400 // CHECK13-NEXT: [[TMP50:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 8401 // CHECK13-NEXT: [[CONV80:%.*]] = fpext float [[TMP50]] to double 8402 // CHECK13-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 8403 // CHECK13-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 8404 // CHECK13-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP15]] 8405 // CHECK13-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3 8406 // CHECK13-NEXT: [[TMP51:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 8407 // CHECK13-NEXT: [[CONV84:%.*]] = fpext float [[TMP51]] to double 8408 // CHECK13-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 8409 // CHECK13-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 8410 // CHECK13-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP15]] 8411 // CHECK13-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1 8412 // CHECK13-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i64 0, i64 2 8413 // CHECK13-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 8414 // CHECK13-NEXT: [[ADD89:%.*]] = fadd double [[TMP52]], 1.000000e+00 8415 // CHECK13-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP15]] 8416 // CHECK13-NEXT: [[TMP53:%.*]] = mul nsw i64 1, [[TMP4]] 8417 // CHECK13-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP53]] 8418 // CHECK13-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i64 3 8419 // CHECK13-NEXT: [[TMP54:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 8420 // CHECK13-NEXT: [[ADD92:%.*]] = fadd double [[TMP54]], 1.000000e+00 8421 // CHECK13-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP15]] 8422 // CHECK13-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 8423 // CHECK13-NEXT: [[TMP55:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 8424 // CHECK13-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP55]], 1 8425 // CHECK13-NEXT: store i64 [[ADD93]], i64* [[X]], align 8, !llvm.access.group [[ACC_GRP15]] 8426 // CHECK13-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 8427 // CHECK13-NEXT: [[TMP56:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 8428 // CHECK13-NEXT: [[CONV94:%.*]] = sext i8 [[TMP56]] to i32 8429 // CHECK13-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 8430 // CHECK13-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 8431 // CHECK13-NEXT: store i8 [[CONV96]], i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP15]] 8432 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 8433 // CHECK13: omp.body.continue97: 8434 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 8435 // CHECK13: omp.inner.for.inc98: 8436 // CHECK13-NEXT: [[TMP57:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8437 // CHECK13-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP57]], 1 8438 // CHECK13-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP15]] 8439 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP16:![0-9]+]] 8440 // CHECK13: omp.inner.for.end100: 8441 // CHECK13-NEXT: store i8 96, i8* [[IT72]], align 1 8442 // CHECK13-NEXT: [[TMP58:%.*]] = load i32, i32* [[A]], align 4 8443 // CHECK13-NEXT: [[TMP59:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 8444 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP59]]) 8445 // CHECK13-NEXT: ret i32 [[TMP58]] 8446 // 8447 // 8448 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari 8449 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8450 // CHECK13-NEXT: entry: 8451 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8452 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8453 // CHECK13-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 8454 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8455 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8456 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8457 // CHECK13-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 8458 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 8459 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8460 // CHECK13-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8461 // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8462 // CHECK13-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 8463 // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 8464 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8465 // CHECK13-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 8466 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8467 // CHECK13-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 8468 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8469 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8470 // CHECK13-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 8471 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8472 // CHECK13-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 8473 // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8474 // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8475 // CHECK13-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 8476 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8477 // CHECK13-NEXT: ret i32 [[TMP8]] 8478 // 8479 // 8480 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8481 // CHECK13-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8482 // CHECK13-NEXT: entry: 8483 // CHECK13-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 8484 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8485 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 8486 // CHECK13-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 8487 // CHECK13-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 8488 // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 8489 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 8490 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8491 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8492 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8493 // CHECK13-NEXT: [[IT:%.*]] = alloca i64, align 8 8494 // CHECK13-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 8495 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8496 // CHECK13-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 8497 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8498 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8499 // CHECK13-NEXT: store i32 [[ADD]], i32* [[B]], align 4 8500 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8501 // CHECK13-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 8502 // CHECK13-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 8503 // CHECK13-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 8504 // CHECK13-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 8505 // CHECK13-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 8506 // CHECK13-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 8507 // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_ADDR]], align 4 8508 // CHECK13-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP5]], 60 8509 // CHECK13-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 8510 // CHECK13-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 8511 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8512 // CHECK13-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 8513 // CHECK13-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8514 // CHECK13-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 8515 // CHECK13-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 8516 // CHECK13-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 8517 // CHECK13-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8518 // CHECK13: omp_if.then: 8519 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8520 // CHECK13: omp.inner.for.cond: 8521 // CHECK13-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 8522 // CHECK13-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 8523 // CHECK13-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP8]], [[TMP9]] 8524 // CHECK13-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8525 // CHECK13: omp.inner.for.body: 8526 // CHECK13-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8527 // CHECK13-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 400 8528 // CHECK13-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 8529 // CHECK13-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 8530 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group [[ACC_GRP18]] 8531 // CHECK13-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP11]] to double 8532 // CHECK13-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 8533 // CHECK13-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8534 // CHECK13-NEXT: store double [[ADD3]], double* [[A]], align 8, !nontemporal !19, !llvm.access.group [[ACC_GRP18]] 8535 // CHECK13-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8536 // CHECK13-NEXT: [[TMP12:%.*]] = load double, double* [[A4]], align 8, !nontemporal !19, !llvm.access.group [[ACC_GRP18]] 8537 // CHECK13-NEXT: [[INC:%.*]] = fadd double [[TMP12]], 1.000000e+00 8538 // CHECK13-NEXT: store double [[INC]], double* [[A4]], align 8, !nontemporal !19, !llvm.access.group [[ACC_GRP18]] 8539 // CHECK13-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 8540 // CHECK13-NEXT: [[TMP13:%.*]] = mul nsw i64 1, [[TMP2]] 8541 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP13]] 8542 // CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 8543 // CHECK13-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP18]] 8544 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8545 // CHECK13: omp.body.continue: 8546 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8547 // CHECK13: omp.inner.for.inc: 8548 // CHECK13-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8549 // CHECK13-NEXT: [[ADD7:%.*]] = add i64 [[TMP14]], 1 8550 // CHECK13-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 8551 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP20:![0-9]+]] 8552 // CHECK13: omp.inner.for.end: 8553 // CHECK13-NEXT: br label [[OMP_IF_END:%.*]] 8554 // CHECK13: omp_if.else: 8555 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 8556 // CHECK13: omp.inner.for.cond8: 8557 // CHECK13-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8558 // CHECK13-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8559 // CHECK13-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP15]], [[TMP16]] 8560 // CHECK13-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 8561 // CHECK13: omp.inner.for.body10: 8562 // CHECK13-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8563 // CHECK13-NEXT: [[MUL11:%.*]] = mul i64 [[TMP17]], 400 8564 // CHECK13-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 8565 // CHECK13-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8 8566 // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[B]], align 4 8567 // CHECK13-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP18]] to double 8568 // CHECK13-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 8569 // CHECK13-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8570 // CHECK13-NEXT: store double [[ADD14]], double* [[A15]], align 8 8571 // CHECK13-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 8572 // CHECK13-NEXT: [[TMP19:%.*]] = load double, double* [[A16]], align 8 8573 // CHECK13-NEXT: [[INC17:%.*]] = fadd double [[TMP19]], 1.000000e+00 8574 // CHECK13-NEXT: store double [[INC17]], double* [[A16]], align 8 8575 // CHECK13-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 8576 // CHECK13-NEXT: [[TMP20:%.*]] = mul nsw i64 1, [[TMP2]] 8577 // CHECK13-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP20]] 8578 // CHECK13-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i64 1 8579 // CHECK13-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2 8580 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 8581 // CHECK13: omp.body.continue21: 8582 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 8583 // CHECK13: omp.inner.for.inc22: 8584 // CHECK13-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8585 // CHECK13-NEXT: [[ADD23:%.*]] = add i64 [[TMP21]], 1 8586 // CHECK13-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8 8587 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP22:![0-9]+]] 8588 // CHECK13: omp.inner.for.end24: 8589 // CHECK13-NEXT: br label [[OMP_IF_END]] 8590 // CHECK13: omp_if.end: 8591 // CHECK13-NEXT: store i64 400, i64* [[IT]], align 8 8592 // CHECK13-NEXT: [[TMP22:%.*]] = mul nsw i64 1, [[TMP2]] 8593 // CHECK13-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP22]] 8594 // CHECK13-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i64 1 8595 // CHECK13-NEXT: [[TMP23:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2 8596 // CHECK13-NEXT: [[CONV27:%.*]] = sext i16 [[TMP23]] to i32 8597 // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[B]], align 4 8598 // CHECK13-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP24]] 8599 // CHECK13-NEXT: [[TMP25:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 8600 // CHECK13-NEXT: call void @llvm.stackrestore(i8* [[TMP25]]) 8601 // CHECK13-NEXT: ret i32 [[ADD28]] 8602 // 8603 // 8604 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici 8605 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 8606 // CHECK13-NEXT: entry: 8607 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8608 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8609 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8610 // CHECK13-NEXT: [[AAA:%.*]] = alloca i8, align 1 8611 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8612 // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 8613 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8614 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8615 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8616 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8617 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 8618 // CHECK13-NEXT: store i8 0, i8* [[AAA]], align 1 8619 // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8620 // CHECK13-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 8621 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8622 // CHECK13-NEXT: ret i32 [[TMP0]] 8623 // 8624 // 8625 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8626 // CHECK13-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 8627 // CHECK13-NEXT: entry: 8628 // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8629 // CHECK13-NEXT: [[A:%.*]] = alloca i32, align 4 8630 // CHECK13-NEXT: [[AA:%.*]] = alloca i16, align 2 8631 // CHECK13-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8632 // CHECK13-NEXT: [[TMP:%.*]] = alloca i64, align 8 8633 // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8634 // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8635 // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8636 // CHECK13-NEXT: [[I:%.*]] = alloca i64, align 8 8637 // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8638 // CHECK13-NEXT: store i32 0, i32* [[A]], align 4 8639 // CHECK13-NEXT: store i16 0, i16* [[AA]], align 2 8640 // CHECK13-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8641 // CHECK13-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 8642 // CHECK13-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8643 // CHECK13-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 8644 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8645 // CHECK13: omp.inner.for.cond: 8646 // CHECK13-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24:![0-9]+]] 8647 // CHECK13-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP24]] 8648 // CHECK13-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 8649 // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8650 // CHECK13: omp.inner.for.body: 8651 // CHECK13-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8652 // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 8653 // CHECK13-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 8654 // CHECK13-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP24]] 8655 // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP24]] 8656 // CHECK13-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 8657 // CHECK13-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP24]] 8658 // CHECK13-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] 8659 // CHECK13-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 8660 // CHECK13-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 8661 // CHECK13-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8662 // CHECK13-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP24]] 8663 // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2 8664 // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 8665 // CHECK13-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 8666 // CHECK13-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 8667 // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8668 // CHECK13: omp.body.continue: 8669 // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8670 // CHECK13: omp.inner.for.inc: 8671 // CHECK13-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8672 // CHECK13-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 8673 // CHECK13-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP24]] 8674 // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 8675 // CHECK13: omp.inner.for.end: 8676 // CHECK13-NEXT: store i64 11, i64* [[I]], align 8 8677 // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8678 // CHECK13-NEXT: ret i32 [[TMP8]] 8679 // 8680 // 8681 // CHECK15-LABEL: define {{[^@]+}}@_Z7get_valv 8682 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] { 8683 // CHECK15-NEXT: entry: 8684 // CHECK15-NEXT: ret i64 0 8685 // 8686 // 8687 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi 8688 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8689 // CHECK15-NEXT: entry: 8690 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8691 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8692 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 8693 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8694 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8695 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8696 // CHECK15-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8697 // CHECK15-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 8698 // CHECK15-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 8699 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 8700 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8701 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8702 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8703 // CHECK15-NEXT: [[I:%.*]] = alloca i32, align 4 8704 // CHECK15-NEXT: [[K:%.*]] = alloca i64, align 8 8705 // CHECK15-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 8706 // CHECK15-NEXT: [[DOTOMP_LB4:%.*]] = alloca i32, align 4 8707 // CHECK15-NEXT: [[DOTOMP_UB5:%.*]] = alloca i32, align 4 8708 // CHECK15-NEXT: [[DOTOMP_IV6:%.*]] = alloca i32, align 4 8709 // CHECK15-NEXT: [[DOTLINEAR_START:%.*]] = alloca i64, align 8 8710 // CHECK15-NEXT: [[I7:%.*]] = alloca i32, align 4 8711 // CHECK15-NEXT: [[K8:%.*]] = alloca i64, align 8 8712 // CHECK15-NEXT: [[LIN:%.*]] = alloca i32, align 4 8713 // CHECK15-NEXT: [[_TMP20:%.*]] = alloca i64, align 4 8714 // CHECK15-NEXT: [[DOTOMP_LB21:%.*]] = alloca i64, align 8 8715 // CHECK15-NEXT: [[DOTOMP_UB22:%.*]] = alloca i64, align 8 8716 // CHECK15-NEXT: [[DOTOMP_IV23:%.*]] = alloca i64, align 8 8717 // CHECK15-NEXT: [[DOTLINEAR_START24:%.*]] = alloca i32, align 4 8718 // CHECK15-NEXT: [[DOTLINEAR_START25:%.*]] = alloca i32, align 4 8719 // CHECK15-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 8720 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 8721 // CHECK15-NEXT: [[LIN27:%.*]] = alloca i32, align 4 8722 // CHECK15-NEXT: [[A28:%.*]] = alloca i32, align 4 8723 // CHECK15-NEXT: [[_TMP49:%.*]] = alloca i16, align 2 8724 // CHECK15-NEXT: [[DOTOMP_LB50:%.*]] = alloca i32, align 4 8725 // CHECK15-NEXT: [[DOTOMP_UB51:%.*]] = alloca i32, align 4 8726 // CHECK15-NEXT: [[DOTOMP_IV52:%.*]] = alloca i32, align 4 8727 // CHECK15-NEXT: [[IT53:%.*]] = alloca i16, align 2 8728 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 8729 // CHECK15-NEXT: [[_TMP68:%.*]] = alloca i8, align 1 8730 // CHECK15-NEXT: [[DOTOMP_LB69:%.*]] = alloca i32, align 4 8731 // CHECK15-NEXT: [[DOTOMP_UB70:%.*]] = alloca i32, align 4 8732 // CHECK15-NEXT: [[DOTOMP_IV71:%.*]] = alloca i32, align 4 8733 // CHECK15-NEXT: [[IT72:%.*]] = alloca i8, align 1 8734 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8735 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 8736 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 8737 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8738 // CHECK15-NEXT: [[TMP1:%.*]] = call i8* @llvm.stacksave() 8739 // CHECK15-NEXT: store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4 8740 // CHECK15-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4 8741 // CHECK15-NEXT: store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4 8742 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8743 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]] 8744 // CHECK15-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8 8745 // CHECK15-NEXT: store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4 8746 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8747 // CHECK15-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 8748 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8749 // CHECK15-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 8750 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8751 // CHECK15: omp.inner.for.cond: 8752 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3:![0-9]+]] 8753 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP3]] 8754 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 8755 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8756 // CHECK15: omp.inner.for.body: 8757 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8758 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 8759 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 8760 // CHECK15-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP3]] 8761 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8762 // CHECK15: omp.body.continue: 8763 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8764 // CHECK15: omp.inner.for.inc: 8765 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8766 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 8767 // CHECK15-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP3]] 8768 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 8769 // CHECK15: omp.inner.for.end: 8770 // CHECK15-NEXT: store i32 33, i32* [[I]], align 4 8771 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() 8772 // CHECK15-NEXT: store i64 [[CALL]], i64* [[K]], align 8 8773 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB4]], align 4 8774 // CHECK15-NEXT: store i32 8, i32* [[DOTOMP_UB5]], align 4 8775 // CHECK15-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_LB4]], align 4 8776 // CHECK15-NEXT: store i32 [[TMP9]], i32* [[DOTOMP_IV6]], align 4 8777 // CHECK15-NEXT: [[TMP10:%.*]] = load i64, i64* [[K]], align 8 8778 // CHECK15-NEXT: store i64 [[TMP10]], i64* [[DOTLINEAR_START]], align 8 8779 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9:%.*]] 8780 // CHECK15: omp.inner.for.cond9: 8781 // CHECK15-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7:![0-9]+]] 8782 // CHECK15-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB5]], align 4, !llvm.access.group [[ACC_GRP7]] 8783 // CHECK15-NEXT: [[CMP10:%.*]] = icmp sle i32 [[TMP11]], [[TMP12]] 8784 // CHECK15-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY11:%.*]], label [[OMP_INNER_FOR_END19:%.*]] 8785 // CHECK15: omp.inner.for.body11: 8786 // CHECK15-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8787 // CHECK15-NEXT: [[MUL12:%.*]] = mul nsw i32 [[TMP13]], 1 8788 // CHECK15-NEXT: [[SUB:%.*]] = sub nsw i32 10, [[MUL12]] 8789 // CHECK15-NEXT: store i32 [[SUB]], i32* [[I7]], align 4, !llvm.access.group [[ACC_GRP7]] 8790 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTLINEAR_START]], align 8, !llvm.access.group [[ACC_GRP7]] 8791 // CHECK15-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8792 // CHECK15-NEXT: [[MUL13:%.*]] = mul nsw i32 [[TMP15]], 3 8793 // CHECK15-NEXT: [[CONV:%.*]] = sext i32 [[MUL13]] to i64 8794 // CHECK15-NEXT: [[ADD14:%.*]] = add nsw i64 [[TMP14]], [[CONV]] 8795 // CHECK15-NEXT: store i64 [[ADD14]], i64* [[K8]], align 8, !llvm.access.group [[ACC_GRP7]] 8796 // CHECK15-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 8797 // CHECK15-NEXT: [[ADD15:%.*]] = add nsw i32 [[TMP16]], 1 8798 // CHECK15-NEXT: store i32 [[ADD15]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP7]] 8799 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE16:%.*]] 8800 // CHECK15: omp.body.continue16: 8801 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC17:%.*]] 8802 // CHECK15: omp.inner.for.inc17: 8803 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8804 // CHECK15-NEXT: [[ADD18:%.*]] = add nsw i32 [[TMP17]], 1 8805 // CHECK15-NEXT: store i32 [[ADD18]], i32* [[DOTOMP_IV6]], align 4, !llvm.access.group [[ACC_GRP7]] 8806 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND9]], !llvm.loop [[LOOP8:![0-9]+]] 8807 // CHECK15: omp.inner.for.end19: 8808 // CHECK15-NEXT: store i32 1, i32* [[I7]], align 4 8809 // CHECK15-NEXT: [[TMP18:%.*]] = load i64, i64* [[K8]], align 8 8810 // CHECK15-NEXT: store i64 [[TMP18]], i64* [[K]], align 8 8811 // CHECK15-NEXT: store i32 12, i32* [[LIN]], align 4 8812 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB21]], align 8 8813 // CHECK15-NEXT: store i64 3, i64* [[DOTOMP_UB22]], align 8 8814 // CHECK15-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_LB21]], align 8 8815 // CHECK15-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_IV23]], align 8 8816 // CHECK15-NEXT: [[TMP20:%.*]] = load i32, i32* [[LIN]], align 4 8817 // CHECK15-NEXT: store i32 [[TMP20]], i32* [[DOTLINEAR_START24]], align 4 8818 // CHECK15-NEXT: [[TMP21:%.*]] = load i32, i32* [[A]], align 4 8819 // CHECK15-NEXT: store i32 [[TMP21]], i32* [[DOTLINEAR_START25]], align 4 8820 // CHECK15-NEXT: [[CALL26:%.*]] = call noundef i64 @_Z7get_valv() 8821 // CHECK15-NEXT: store i64 [[CALL26]], i64* [[DOTLINEAR_STEP]], align 8 8822 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29:%.*]] 8823 // CHECK15: omp.inner.for.cond29: 8824 // CHECK15-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10:![0-9]+]] 8825 // CHECK15-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB22]], align 8, !llvm.access.group [[ACC_GRP10]] 8826 // CHECK15-NEXT: [[CMP30:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 8827 // CHECK15-NEXT: br i1 [[CMP30]], label [[OMP_INNER_FOR_BODY31:%.*]], label [[OMP_INNER_FOR_END48:%.*]] 8828 // CHECK15: omp.inner.for.body31: 8829 // CHECK15-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8830 // CHECK15-NEXT: [[MUL32:%.*]] = mul i64 [[TMP24]], 400 8831 // CHECK15-NEXT: [[SUB33:%.*]] = sub i64 2000, [[MUL32]] 8832 // CHECK15-NEXT: store i64 [[SUB33]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP10]] 8833 // CHECK15-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTLINEAR_START24]], align 4, !llvm.access.group [[ACC_GRP10]] 8834 // CHECK15-NEXT: [[CONV34:%.*]] = sext i32 [[TMP25]] to i64 8835 // CHECK15-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8836 // CHECK15-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 8837 // CHECK15-NEXT: [[MUL35:%.*]] = mul i64 [[TMP26]], [[TMP27]] 8838 // CHECK15-NEXT: [[ADD36:%.*]] = add i64 [[CONV34]], [[MUL35]] 8839 // CHECK15-NEXT: [[CONV37:%.*]] = trunc i64 [[ADD36]] to i32 8840 // CHECK15-NEXT: store i32 [[CONV37]], i32* [[LIN27]], align 4, !llvm.access.group [[ACC_GRP10]] 8841 // CHECK15-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTLINEAR_START25]], align 4, !llvm.access.group [[ACC_GRP10]] 8842 // CHECK15-NEXT: [[CONV38:%.*]] = sext i32 [[TMP28]] to i64 8843 // CHECK15-NEXT: [[TMP29:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8844 // CHECK15-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP10]] 8845 // CHECK15-NEXT: [[MUL39:%.*]] = mul i64 [[TMP29]], [[TMP30]] 8846 // CHECK15-NEXT: [[ADD40:%.*]] = add i64 [[CONV38]], [[MUL39]] 8847 // CHECK15-NEXT: [[CONV41:%.*]] = trunc i64 [[ADD40]] to i32 8848 // CHECK15-NEXT: store i32 [[CONV41]], i32* [[A28]], align 4, !llvm.access.group [[ACC_GRP10]] 8849 // CHECK15-NEXT: [[TMP31:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 8850 // CHECK15-NEXT: [[CONV42:%.*]] = sext i16 [[TMP31]] to i32 8851 // CHECK15-NEXT: [[ADD43:%.*]] = add nsw i32 [[CONV42]], 1 8852 // CHECK15-NEXT: [[CONV44:%.*]] = trunc i32 [[ADD43]] to i16 8853 // CHECK15-NEXT: store i16 [[CONV44]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP10]] 8854 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE45:%.*]] 8855 // CHECK15: omp.body.continue45: 8856 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC46:%.*]] 8857 // CHECK15: omp.inner.for.inc46: 8858 // CHECK15-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8859 // CHECK15-NEXT: [[ADD47:%.*]] = add i64 [[TMP32]], 1 8860 // CHECK15-NEXT: store i64 [[ADD47]], i64* [[DOTOMP_IV23]], align 8, !llvm.access.group [[ACC_GRP10]] 8861 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND29]], !llvm.loop [[LOOP11:![0-9]+]] 8862 // CHECK15: omp.inner.for.end48: 8863 // CHECK15-NEXT: store i64 400, i64* [[IT]], align 8 8864 // CHECK15-NEXT: [[TMP33:%.*]] = load i32, i32* [[LIN27]], align 4 8865 // CHECK15-NEXT: store i32 [[TMP33]], i32* [[LIN]], align 4 8866 // CHECK15-NEXT: [[TMP34:%.*]] = load i32, i32* [[A28]], align 4 8867 // CHECK15-NEXT: store i32 [[TMP34]], i32* [[A]], align 4 8868 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB50]], align 4 8869 // CHECK15-NEXT: store i32 3, i32* [[DOTOMP_UB51]], align 4 8870 // CHECK15-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTOMP_LB50]], align 4 8871 // CHECK15-NEXT: store i32 [[TMP35]], i32* [[DOTOMP_IV52]], align 4 8872 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54:%.*]] 8873 // CHECK15: omp.inner.for.cond54: 8874 // CHECK15-NEXT: [[TMP36:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13:![0-9]+]] 8875 // CHECK15-NEXT: [[TMP37:%.*]] = load i32, i32* [[DOTOMP_UB51]], align 4, !llvm.access.group [[ACC_GRP13]] 8876 // CHECK15-NEXT: [[CMP55:%.*]] = icmp sle i32 [[TMP36]], [[TMP37]] 8877 // CHECK15-NEXT: br i1 [[CMP55]], label [[OMP_INNER_FOR_BODY56:%.*]], label [[OMP_INNER_FOR_END67:%.*]] 8878 // CHECK15: omp.inner.for.body56: 8879 // CHECK15-NEXT: [[TMP38:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8880 // CHECK15-NEXT: [[MUL57:%.*]] = mul nsw i32 [[TMP38]], 4 8881 // CHECK15-NEXT: [[ADD58:%.*]] = add nsw i32 6, [[MUL57]] 8882 // CHECK15-NEXT: [[CONV59:%.*]] = trunc i32 [[ADD58]] to i16 8883 // CHECK15-NEXT: store i16 [[CONV59]], i16* [[IT53]], align 2, !llvm.access.group [[ACC_GRP13]] 8884 // CHECK15-NEXT: [[TMP39:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 8885 // CHECK15-NEXT: [[ADD60:%.*]] = add nsw i32 [[TMP39]], 1 8886 // CHECK15-NEXT: store i32 [[ADD60]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP13]] 8887 // CHECK15-NEXT: [[TMP40:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 8888 // CHECK15-NEXT: [[CONV61:%.*]] = sext i16 [[TMP40]] to i32 8889 // CHECK15-NEXT: [[ADD62:%.*]] = add nsw i32 [[CONV61]], 1 8890 // CHECK15-NEXT: [[CONV63:%.*]] = trunc i32 [[ADD62]] to i16 8891 // CHECK15-NEXT: store i16 [[CONV63]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP13]] 8892 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE64:%.*]] 8893 // CHECK15: omp.body.continue64: 8894 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC65:%.*]] 8895 // CHECK15: omp.inner.for.inc65: 8896 // CHECK15-NEXT: [[TMP41:%.*]] = load i32, i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8897 // CHECK15-NEXT: [[ADD66:%.*]] = add nsw i32 [[TMP41]], 1 8898 // CHECK15-NEXT: store i32 [[ADD66]], i32* [[DOTOMP_IV52]], align 4, !llvm.access.group [[ACC_GRP13]] 8899 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND54]], !llvm.loop [[LOOP14:![0-9]+]] 8900 // CHECK15: omp.inner.for.end67: 8901 // CHECK15-NEXT: store i16 22, i16* [[IT53]], align 2 8902 // CHECK15-NEXT: [[TMP42:%.*]] = load i32, i32* [[A]], align 4 8903 // CHECK15-NEXT: store i32 [[TMP42]], i32* [[DOTCAPTURE_EXPR_]], align 4 8904 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB69]], align 4 8905 // CHECK15-NEXT: store i32 25, i32* [[DOTOMP_UB70]], align 4 8906 // CHECK15-NEXT: [[TMP43:%.*]] = load i32, i32* [[DOTOMP_LB69]], align 4 8907 // CHECK15-NEXT: store i32 [[TMP43]], i32* [[DOTOMP_IV71]], align 4 8908 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73:%.*]] 8909 // CHECK15: omp.inner.for.cond73: 8910 // CHECK15-NEXT: [[TMP44:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16:![0-9]+]] 8911 // CHECK15-NEXT: [[TMP45:%.*]] = load i32, i32* [[DOTOMP_UB70]], align 4, !llvm.access.group [[ACC_GRP16]] 8912 // CHECK15-NEXT: [[CMP74:%.*]] = icmp sle i32 [[TMP44]], [[TMP45]] 8913 // CHECK15-NEXT: br i1 [[CMP74]], label [[OMP_INNER_FOR_BODY75:%.*]], label [[OMP_INNER_FOR_END100:%.*]] 8914 // CHECK15: omp.inner.for.body75: 8915 // CHECK15-NEXT: [[TMP46:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8916 // CHECK15-NEXT: [[MUL76:%.*]] = mul nsw i32 [[TMP46]], 1 8917 // CHECK15-NEXT: [[SUB77:%.*]] = sub nsw i32 122, [[MUL76]] 8918 // CHECK15-NEXT: [[CONV78:%.*]] = trunc i32 [[SUB77]] to i8 8919 // CHECK15-NEXT: store i8 [[CONV78]], i8* [[IT72]], align 1, !llvm.access.group [[ACC_GRP16]] 8920 // CHECK15-NEXT: [[TMP47:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 8921 // CHECK15-NEXT: [[ADD79:%.*]] = add nsw i32 [[TMP47]], 1 8922 // CHECK15-NEXT: store i32 [[ADD79]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP16]] 8923 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2 8924 // CHECK15-NEXT: [[TMP48:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 8925 // CHECK15-NEXT: [[CONV80:%.*]] = fpext float [[TMP48]] to double 8926 // CHECK15-NEXT: [[ADD81:%.*]] = fadd double [[CONV80]], 1.000000e+00 8927 // CHECK15-NEXT: [[CONV82:%.*]] = fptrunc double [[ADD81]] to float 8928 // CHECK15-NEXT: store float [[CONV82]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP16]] 8929 // CHECK15-NEXT: [[ARRAYIDX83:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3 8930 // CHECK15-NEXT: [[TMP49:%.*]] = load float, float* [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 8931 // CHECK15-NEXT: [[CONV84:%.*]] = fpext float [[TMP49]] to double 8932 // CHECK15-NEXT: [[ADD85:%.*]] = fadd double [[CONV84]], 1.000000e+00 8933 // CHECK15-NEXT: [[CONV86:%.*]] = fptrunc double [[ADD85]] to float 8934 // CHECK15-NEXT: store float [[CONV86]], float* [[ARRAYIDX83]], align 4, !llvm.access.group [[ACC_GRP16]] 8935 // CHECK15-NEXT: [[ARRAYIDX87:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1 8936 // CHECK15-NEXT: [[ARRAYIDX88:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX87]], i32 0, i32 2 8937 // CHECK15-NEXT: [[TMP50:%.*]] = load double, double* [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 8938 // CHECK15-NEXT: [[ADD89:%.*]] = fadd double [[TMP50]], 1.000000e+00 8939 // CHECK15-NEXT: store double [[ADD89]], double* [[ARRAYIDX88]], align 8, !llvm.access.group [[ACC_GRP16]] 8940 // CHECK15-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP2]] 8941 // CHECK15-NEXT: [[ARRAYIDX90:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP51]] 8942 // CHECK15-NEXT: [[ARRAYIDX91:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX90]], i32 3 8943 // CHECK15-NEXT: [[TMP52:%.*]] = load double, double* [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 8944 // CHECK15-NEXT: [[ADD92:%.*]] = fadd double [[TMP52]], 1.000000e+00 8945 // CHECK15-NEXT: store double [[ADD92]], double* [[ARRAYIDX91]], align 8, !llvm.access.group [[ACC_GRP16]] 8946 // CHECK15-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0 8947 // CHECK15-NEXT: [[TMP53:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 8948 // CHECK15-NEXT: [[ADD93:%.*]] = add nsw i64 [[TMP53]], 1 8949 // CHECK15-NEXT: store i64 [[ADD93]], i64* [[X]], align 4, !llvm.access.group [[ACC_GRP16]] 8950 // CHECK15-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1 8951 // CHECK15-NEXT: [[TMP54:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 8952 // CHECK15-NEXT: [[CONV94:%.*]] = sext i8 [[TMP54]] to i32 8953 // CHECK15-NEXT: [[ADD95:%.*]] = add nsw i32 [[CONV94]], 1 8954 // CHECK15-NEXT: [[CONV96:%.*]] = trunc i32 [[ADD95]] to i8 8955 // CHECK15-NEXT: store i8 [[CONV96]], i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP16]] 8956 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE97:%.*]] 8957 // CHECK15: omp.body.continue97: 8958 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC98:%.*]] 8959 // CHECK15: omp.inner.for.inc98: 8960 // CHECK15-NEXT: [[TMP55:%.*]] = load i32, i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8961 // CHECK15-NEXT: [[ADD99:%.*]] = add nsw i32 [[TMP55]], 1 8962 // CHECK15-NEXT: store i32 [[ADD99]], i32* [[DOTOMP_IV71]], align 4, !llvm.access.group [[ACC_GRP16]] 8963 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND73]], !llvm.loop [[LOOP17:![0-9]+]] 8964 // CHECK15: omp.inner.for.end100: 8965 // CHECK15-NEXT: store i8 96, i8* [[IT72]], align 1 8966 // CHECK15-NEXT: [[TMP56:%.*]] = load i32, i32* [[A]], align 4 8967 // CHECK15-NEXT: [[TMP57:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8968 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP57]]) 8969 // CHECK15-NEXT: ret i32 [[TMP56]] 8970 // 8971 // 8972 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari 8973 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8974 // CHECK15-NEXT: entry: 8975 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8976 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 8977 // CHECK15-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 8978 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8979 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 8980 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8981 // CHECK15-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 8982 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 8983 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8984 // CHECK15-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8985 // CHECK15-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8986 // CHECK15-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 8987 // CHECK15-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 8988 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8989 // CHECK15-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 8990 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8991 // CHECK15-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 8992 // CHECK15-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8993 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8994 // CHECK15-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 8995 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8996 // CHECK15-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 8997 // CHECK15-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8998 // CHECK15-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8999 // CHECK15-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 9000 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9001 // CHECK15-NEXT: ret i32 [[TMP8]] 9002 // 9003 // 9004 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 9005 // CHECK15-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 9006 // CHECK15-NEXT: entry: 9007 // CHECK15-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9008 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9009 // CHECK15-NEXT: [[B:%.*]] = alloca i32, align 4 9010 // CHECK15-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 9011 // CHECK15-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 9012 // CHECK15-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 9013 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 9014 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9015 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9016 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9017 // CHECK15-NEXT: [[IT:%.*]] = alloca i64, align 8 9018 // CHECK15-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9019 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9020 // CHECK15-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9021 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9022 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9023 // CHECK15-NEXT: store i32 [[ADD]], i32* [[B]], align 4 9024 // CHECK15-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9025 // CHECK15-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 9026 // CHECK15-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 9027 // CHECK15-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 9028 // CHECK15-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 9029 // CHECK15-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 9030 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9031 // CHECK15-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 60 9032 // CHECK15-NEXT: [[FROMBOOL:%.*]] = zext i1 [[CMP]] to i8 9033 // CHECK15-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR_]], align 1 9034 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9035 // CHECK15-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9036 // CHECK15-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9037 // CHECK15-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 9038 // CHECK15-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 9039 // CHECK15-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP6]] to i1 9040 // CHECK15-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9041 // CHECK15: omp_if.then: 9042 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9043 // CHECK15: omp.inner.for.cond: 9044 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19:![0-9]+]] 9045 // CHECK15-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP19]] 9046 // CHECK15-NEXT: [[CMP2:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9047 // CHECK15-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9048 // CHECK15: omp.inner.for.body: 9049 // CHECK15-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 9050 // CHECK15-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9051 // CHECK15-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9052 // CHECK15-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP19]] 9053 // CHECK15-NEXT: [[TMP10:%.*]] = load i32, i32* [[B]], align 4, !llvm.access.group [[ACC_GRP19]] 9054 // CHECK15-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP10]] to double 9055 // CHECK15-NEXT: [[ADD3:%.*]] = fadd double [[CONV]], 1.500000e+00 9056 // CHECK15-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 9057 // CHECK15-NEXT: store double [[ADD3]], double* [[A]], align 4, !nontemporal !20, !llvm.access.group [[ACC_GRP19]] 9058 // CHECK15-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 9059 // CHECK15-NEXT: [[TMP11:%.*]] = load double, double* [[A4]], align 4, !nontemporal !20, !llvm.access.group [[ACC_GRP19]] 9060 // CHECK15-NEXT: [[INC:%.*]] = fadd double [[TMP11]], 1.000000e+00 9061 // CHECK15-NEXT: store double [[INC]], double* [[A4]], align 4, !nontemporal !20, !llvm.access.group [[ACC_GRP19]] 9062 // CHECK15-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 9063 // CHECK15-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP1]] 9064 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP12]] 9065 // CHECK15-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9066 // CHECK15-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP19]] 9067 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9068 // CHECK15: omp.body.continue: 9069 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9070 // CHECK15: omp.inner.for.inc: 9071 // CHECK15-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 9072 // CHECK15-NEXT: [[ADD7:%.*]] = add i64 [[TMP13]], 1 9073 // CHECK15-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP19]] 9074 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 9075 // CHECK15: omp.inner.for.end: 9076 // CHECK15-NEXT: br label [[OMP_IF_END:%.*]] 9077 // CHECK15: omp_if.else: 9078 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8:%.*]] 9079 // CHECK15: omp.inner.for.cond8: 9080 // CHECK15-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9081 // CHECK15-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9082 // CHECK15-NEXT: [[CMP9:%.*]] = icmp ule i64 [[TMP14]], [[TMP15]] 9083 // CHECK15-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY10:%.*]], label [[OMP_INNER_FOR_END24:%.*]] 9084 // CHECK15: omp.inner.for.body10: 9085 // CHECK15-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9086 // CHECK15-NEXT: [[MUL11:%.*]] = mul i64 [[TMP16]], 400 9087 // CHECK15-NEXT: [[SUB12:%.*]] = sub i64 2000, [[MUL11]] 9088 // CHECK15-NEXT: store i64 [[SUB12]], i64* [[IT]], align 8 9089 // CHECK15-NEXT: [[TMP17:%.*]] = load i32, i32* [[B]], align 4 9090 // CHECK15-NEXT: [[CONV13:%.*]] = sitofp i32 [[TMP17]] to double 9091 // CHECK15-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.500000e+00 9092 // CHECK15-NEXT: [[A15:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 9093 // CHECK15-NEXT: store double [[ADD14]], double* [[A15]], align 4 9094 // CHECK15-NEXT: [[A16:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0 9095 // CHECK15-NEXT: [[TMP18:%.*]] = load double, double* [[A16]], align 4 9096 // CHECK15-NEXT: [[INC17:%.*]] = fadd double [[TMP18]], 1.000000e+00 9097 // CHECK15-NEXT: store double [[INC17]], double* [[A16]], align 4 9098 // CHECK15-NEXT: [[CONV18:%.*]] = fptosi double [[INC17]] to i16 9099 // CHECK15-NEXT: [[TMP19:%.*]] = mul nsw i32 1, [[TMP1]] 9100 // CHECK15-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP19]] 9101 // CHECK15-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX19]], i32 1 9102 // CHECK15-NEXT: store i16 [[CONV18]], i16* [[ARRAYIDX20]], align 2 9103 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE21:%.*]] 9104 // CHECK15: omp.body.continue21: 9105 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC22:%.*]] 9106 // CHECK15: omp.inner.for.inc22: 9107 // CHECK15-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9108 // CHECK15-NEXT: [[ADD23:%.*]] = add i64 [[TMP20]], 1 9109 // CHECK15-NEXT: store i64 [[ADD23]], i64* [[DOTOMP_IV]], align 8 9110 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND8]], !llvm.loop [[LOOP23:![0-9]+]] 9111 // CHECK15: omp.inner.for.end24: 9112 // CHECK15-NEXT: br label [[OMP_IF_END]] 9113 // CHECK15: omp_if.end: 9114 // CHECK15-NEXT: store i64 400, i64* [[IT]], align 8 9115 // CHECK15-NEXT: [[TMP21:%.*]] = mul nsw i32 1, [[TMP1]] 9116 // CHECK15-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP21]] 9117 // CHECK15-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1 9118 // CHECK15-NEXT: [[TMP22:%.*]] = load i16, i16* [[ARRAYIDX26]], align 2 9119 // CHECK15-NEXT: [[CONV27:%.*]] = sext i16 [[TMP22]] to i32 9120 // CHECK15-NEXT: [[TMP23:%.*]] = load i32, i32* [[B]], align 4 9121 // CHECK15-NEXT: [[ADD28:%.*]] = add nsw i32 [[CONV27]], [[TMP23]] 9122 // CHECK15-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9123 // CHECK15-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 9124 // CHECK15-NEXT: ret i32 [[ADD28]] 9125 // 9126 // 9127 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici 9128 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 9129 // CHECK15-NEXT: entry: 9130 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9131 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 9132 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 9133 // CHECK15-NEXT: [[AAA:%.*]] = alloca i8, align 1 9134 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9135 // CHECK15-NEXT: [[TMP:%.*]] = alloca i32, align 4 9136 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9137 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9138 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9139 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 9140 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 9141 // CHECK15-NEXT: store i8 0, i8* [[AAA]], align 1 9142 // CHECK15-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9143 // CHECK15-NEXT: store i32 429496720, i32* [[DOTOMP_UB]], align 4 9144 // CHECK15-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9145 // CHECK15-NEXT: ret i32 [[TMP0]] 9146 // 9147 // 9148 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 9149 // CHECK15-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 9150 // CHECK15-NEXT: entry: 9151 // CHECK15-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9152 // CHECK15-NEXT: [[A:%.*]] = alloca i32, align 4 9153 // CHECK15-NEXT: [[AA:%.*]] = alloca i16, align 2 9154 // CHECK15-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9155 // CHECK15-NEXT: [[TMP:%.*]] = alloca i64, align 4 9156 // CHECK15-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9157 // CHECK15-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9158 // CHECK15-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9159 // CHECK15-NEXT: [[I:%.*]] = alloca i64, align 8 9160 // CHECK15-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9161 // CHECK15-NEXT: store i32 0, i32* [[A]], align 4 9162 // CHECK15-NEXT: store i16 0, i16* [[AA]], align 2 9163 // CHECK15-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9164 // CHECK15-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 9165 // CHECK15-NEXT: [[TMP0:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9166 // CHECK15-NEXT: store i64 [[TMP0]], i64* [[DOTOMP_IV]], align 8 9167 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9168 // CHECK15: omp.inner.for.cond: 9169 // CHECK15-NEXT: [[TMP1:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25:![0-9]+]] 9170 // CHECK15-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP25]] 9171 // CHECK15-NEXT: [[CMP:%.*]] = icmp sle i64 [[TMP1]], [[TMP2]] 9172 // CHECK15-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9173 // CHECK15: omp.inner.for.body: 9174 // CHECK15-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 9175 // CHECK15-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP3]], 3 9176 // CHECK15-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9177 // CHECK15-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP25]] 9178 // CHECK15-NEXT: [[TMP4:%.*]] = load i32, i32* [[A]], align 4, !llvm.access.group [[ACC_GRP25]] 9179 // CHECK15-NEXT: [[ADD1:%.*]] = add nsw i32 [[TMP4]], 1 9180 // CHECK15-NEXT: store i32 [[ADD1]], i32* [[A]], align 4, !llvm.access.group [[ACC_GRP25]] 9181 // CHECK15-NEXT: [[TMP5:%.*]] = load i16, i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] 9182 // CHECK15-NEXT: [[CONV:%.*]] = sext i16 [[TMP5]] to i32 9183 // CHECK15-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV]], 1 9184 // CHECK15-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 9185 // CHECK15-NEXT: store i16 [[CONV3]], i16* [[AA]], align 2, !llvm.access.group [[ACC_GRP25]] 9186 // CHECK15-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2 9187 // CHECK15-NEXT: [[TMP6:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] 9188 // CHECK15-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1 9189 // CHECK15-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP25]] 9190 // CHECK15-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9191 // CHECK15: omp.body.continue: 9192 // CHECK15-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9193 // CHECK15: omp.inner.for.inc: 9194 // CHECK15-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 9195 // CHECK15-NEXT: [[ADD5:%.*]] = add nsw i64 [[TMP7]], 1 9196 // CHECK15-NEXT: store i64 [[ADD5]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP25]] 9197 // CHECK15-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP26:![0-9]+]] 9198 // CHECK15: omp.inner.for.end: 9199 // CHECK15-NEXT: store i64 11, i64* [[I]], align 8 9200 // CHECK15-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9201 // CHECK15-NEXT: ret i32 [[TMP8]] 9202 // 9203 // 9204 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 9205 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] { 9206 // CHECK17-NEXT: entry: 9207 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 9208 // CHECK17-NEXT: ret void 9209 // 9210 // 9211 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 9212 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 9213 // CHECK17-NEXT: entry: 9214 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9215 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9216 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9217 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9218 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9219 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9220 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9221 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9222 // CHECK17-NEXT: [[I:%.*]] = alloca i32, align 4 9223 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9224 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9225 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9226 // CHECK17-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 9227 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9228 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9229 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9230 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9231 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9232 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9233 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 9234 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9235 // CHECK17: cond.true: 9236 // CHECK17-NEXT: br label [[COND_END:%.*]] 9237 // CHECK17: cond.false: 9238 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9239 // CHECK17-NEXT: br label [[COND_END]] 9240 // CHECK17: cond.end: 9241 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9242 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9243 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9244 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9245 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9246 // CHECK17: omp.inner.for.cond: 9247 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 9248 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 9249 // CHECK17-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9250 // CHECK17-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9251 // CHECK17: omp.inner.for.body: 9252 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 9253 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 9254 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 9255 // CHECK17-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 9256 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9257 // CHECK17: omp.body.continue: 9258 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9259 // CHECK17: omp.inner.for.inc: 9260 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 9261 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 9262 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 9263 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 9264 // CHECK17: omp.inner.for.end: 9265 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9266 // CHECK17: omp.loop.exit: 9267 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9268 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9269 // CHECK17-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 9270 // CHECK17-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9271 // CHECK17: .omp.final.then: 9272 // CHECK17-NEXT: store i32 33, i32* [[I]], align 4 9273 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9274 // CHECK17: .omp.final.done: 9275 // CHECK17-NEXT: ret void 9276 // 9277 // 9278 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 9279 // CHECK17-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 9280 // CHECK17-NEXT: entry: 9281 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9282 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 9283 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9284 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9285 // CHECK17-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 9286 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9287 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9288 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 9289 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9290 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9291 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 9292 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9293 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9294 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9295 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 9296 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9297 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 9298 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 9299 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 9300 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 9301 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 9302 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9303 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 9304 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 9305 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 9306 // CHECK17-NEXT: ret void 9307 // 9308 // 9309 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..1 9310 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 9311 // CHECK17-NEXT: entry: 9312 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9313 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9314 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9315 // CHECK17-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 9316 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9317 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9318 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9319 // CHECK17-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 9320 // CHECK17-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 9321 // CHECK17-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 9322 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9323 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9324 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9325 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9326 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 9327 // CHECK17-NEXT: [[LIN4:%.*]] = alloca i32, align 4 9328 // CHECK17-NEXT: [[A5:%.*]] = alloca i32, align 4 9329 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9330 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9331 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9332 // CHECK17-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 9333 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9334 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9335 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 9336 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9337 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 9338 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 9339 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 9340 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 9341 // CHECK17-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 9342 // CHECK17-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 9343 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9344 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9345 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9346 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9347 // CHECK17-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9348 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 9349 // CHECK17-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 9350 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9351 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9352 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 9353 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9354 // CHECK17: cond.true: 9355 // CHECK17-NEXT: br label [[COND_END:%.*]] 9356 // CHECK17: cond.false: 9357 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9358 // CHECK17-NEXT: br label [[COND_END]] 9359 // CHECK17: cond.end: 9360 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 9361 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9362 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9363 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 9364 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9365 // CHECK17: omp.inner.for.cond: 9366 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]] 9367 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]] 9368 // CHECK17-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 9369 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9370 // CHECK17: omp.inner.for.body: 9371 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9372 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 9373 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9374 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP17]] 9375 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]] 9376 // CHECK17-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 9377 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9378 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 9379 // CHECK17-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 9380 // CHECK17-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 9381 // CHECK17-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 9382 // CHECK17-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group [[ACC_GRP17]] 9383 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group [[ACC_GRP17]] 9384 // CHECK17-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 9385 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9386 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 9387 // CHECK17-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 9388 // CHECK17-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 9389 // CHECK17-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 9390 // CHECK17-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group [[ACC_GRP17]] 9391 // CHECK17-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP17]] 9392 // CHECK17-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 9393 // CHECK17-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 9394 // CHECK17-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 9395 // CHECK17-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP17]] 9396 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9397 // CHECK17: omp.body.continue: 9398 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9399 // CHECK17: omp.inner.for.inc: 9400 // CHECK17-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9401 // CHECK17-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 9402 // CHECK17-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 9403 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 9404 // CHECK17: omp.inner.for.end: 9405 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9406 // CHECK17: omp.loop.exit: 9407 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 9408 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9409 // CHECK17-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 9410 // CHECK17-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9411 // CHECK17: .omp.final.then: 9412 // CHECK17-NEXT: store i64 400, i64* [[IT]], align 8 9413 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9414 // CHECK17: .omp.final.done: 9415 // CHECK17-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9416 // CHECK17-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 9417 // CHECK17-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 9418 // CHECK17: .omp.linear.pu: 9419 // CHECK17-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 9420 // CHECK17-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 9421 // CHECK17-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 9422 // CHECK17-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 9423 // CHECK17-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 9424 // CHECK17: .omp.linear.pu.done: 9425 // CHECK17-NEXT: ret void 9426 // 9427 // 9428 // CHECK17-LABEL: define {{[^@]+}}@_Z7get_valv 9429 // CHECK17-SAME: () #[[ATTR3:[0-9]+]] { 9430 // CHECK17-NEXT: entry: 9431 // CHECK17-NEXT: ret i64 0 9432 // 9433 // 9434 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 9435 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 9436 // CHECK17-NEXT: entry: 9437 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9438 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9439 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9440 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9441 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9442 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9443 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9444 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9445 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9446 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9447 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 9448 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 9449 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 9450 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9451 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 9452 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9453 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 9454 // CHECK17-NEXT: ret void 9455 // 9456 // 9457 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 9458 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 9459 // CHECK17-NEXT: entry: 9460 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9461 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9462 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9463 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9464 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9465 // CHECK17-NEXT: [[TMP:%.*]] = alloca i16, align 2 9466 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9467 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9468 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9469 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9470 // CHECK17-NEXT: [[IT:%.*]] = alloca i16, align 2 9471 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9472 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9473 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9474 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9475 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9476 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9477 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9478 // CHECK17-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 9479 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9480 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9481 // CHECK17-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9482 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 9483 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 9484 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9485 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 9486 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9487 // CHECK17: cond.true: 9488 // CHECK17-NEXT: br label [[COND_END:%.*]] 9489 // CHECK17: cond.false: 9490 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9491 // CHECK17-NEXT: br label [[COND_END]] 9492 // CHECK17: cond.end: 9493 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 9494 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9495 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9496 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 9497 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9498 // CHECK17: omp.inner.for.cond: 9499 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 9500 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 9501 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 9502 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9503 // CHECK17: omp.inner.for.body: 9504 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9505 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 9506 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 9507 // CHECK17-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 9508 // CHECK17-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group [[ACC_GRP20]] 9509 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP20]] 9510 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 9511 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP20]] 9512 // CHECK17-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP20]] 9513 // CHECK17-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 9514 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 9515 // CHECK17-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 9516 // CHECK17-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP20]] 9517 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9518 // CHECK17: omp.body.continue: 9519 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9520 // CHECK17: omp.inner.for.inc: 9521 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9522 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 9523 // CHECK17-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 9524 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 9525 // CHECK17: omp.inner.for.end: 9526 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9527 // CHECK17: omp.loop.exit: 9528 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 9529 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9530 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 9531 // CHECK17-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9532 // CHECK17: .omp.final.then: 9533 // CHECK17-NEXT: store i16 22, i16* [[IT]], align 2 9534 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9535 // CHECK17: .omp.final.done: 9536 // CHECK17-NEXT: ret void 9537 // 9538 // 9539 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 9540 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 9541 // CHECK17-NEXT: entry: 9542 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9543 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 9544 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9545 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 9546 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 9547 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9548 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9549 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 9550 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 9551 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9552 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9553 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 9554 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9555 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 9556 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9557 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 9558 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 9559 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9560 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 9561 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 9562 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 9563 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 9564 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9565 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 9566 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9567 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 9568 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 9569 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9570 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 9571 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 9572 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 9573 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 9574 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 9575 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9576 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 9577 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 9578 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 9579 // CHECK17-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 9580 // CHECK17-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 9581 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 9582 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 9583 // CHECK17-NEXT: ret void 9584 // 9585 // 9586 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 9587 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 9588 // CHECK17-NEXT: entry: 9589 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9590 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9591 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9592 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 9593 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9594 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 9595 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 9596 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9597 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 9598 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 9599 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 9600 // CHECK17-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 9601 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9602 // CHECK17-NEXT: [[TMP:%.*]] = alloca i8, align 1 9603 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 9604 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 9605 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 9606 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9607 // CHECK17-NEXT: [[IT:%.*]] = alloca i8, align 1 9608 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9609 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9610 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9611 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 9612 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9613 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 9614 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 9615 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9616 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 9617 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 9618 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 9619 // CHECK17-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 9620 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9621 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 9622 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9623 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 9624 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 9625 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9626 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 9627 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 9628 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 9629 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 9630 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 9631 // CHECK17-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 9632 // CHECK17-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 9633 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9634 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 9635 // CHECK17-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9636 // CHECK17-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 9637 // CHECK17-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 9638 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 9639 // CHECK17: omp.dispatch.cond: 9640 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9641 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 9642 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9643 // CHECK17: cond.true: 9644 // CHECK17-NEXT: br label [[COND_END:%.*]] 9645 // CHECK17: cond.false: 9646 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9647 // CHECK17-NEXT: br label [[COND_END]] 9648 // CHECK17: cond.end: 9649 // CHECK17-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 9650 // CHECK17-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 9651 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9652 // CHECK17-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 9653 // CHECK17-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 9654 // CHECK17-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9655 // CHECK17-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 9656 // CHECK17-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 9657 // CHECK17: omp.dispatch.body: 9658 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9659 // CHECK17: omp.inner.for.cond: 9660 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 9661 // CHECK17-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 9662 // CHECK17-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 9663 // CHECK17-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9664 // CHECK17: omp.inner.for.body: 9665 // CHECK17-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9666 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 9667 // CHECK17-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 9668 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 9669 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group [[ACC_GRP23]] 9670 // CHECK17-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP23]] 9671 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 9672 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP23]] 9673 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 9674 // CHECK17-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 9675 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 9676 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 9677 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 9678 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 9679 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 9680 // CHECK17-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP23]] 9681 // CHECK17-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 9682 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 9683 // CHECK17-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 9684 // CHECK17-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP23]] 9685 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 9686 // CHECK17-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 9687 // CHECK17-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP23]] 9688 // CHECK17-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 9689 // CHECK17-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP23]] 9690 // CHECK17-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 9691 // CHECK17-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 9692 // CHECK17-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 9693 // CHECK17-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group [[ACC_GRP23]] 9694 // CHECK17-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 9695 // CHECK17-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group [[ACC_GRP23]] 9696 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 9697 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 9698 // CHECK17-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 9699 // CHECK17-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 9700 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 9701 // CHECK17-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 9702 // CHECK17-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 9703 // CHECK17-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 9704 // CHECK17-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 9705 // CHECK17-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 9706 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9707 // CHECK17: omp.body.continue: 9708 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9709 // CHECK17: omp.inner.for.inc: 9710 // CHECK17-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9711 // CHECK17-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 9712 // CHECK17-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 9713 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 9714 // CHECK17: omp.inner.for.end: 9715 // CHECK17-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 9716 // CHECK17: omp.dispatch.inc: 9717 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 9718 // CHECK17-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9719 // CHECK17-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 9720 // CHECK17-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 9721 // CHECK17-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 9722 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 9723 // CHECK17-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 9724 // CHECK17-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 9725 // CHECK17-NEXT: br label [[OMP_DISPATCH_COND]] 9726 // CHECK17: omp.dispatch.end: 9727 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 9728 // CHECK17-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9729 // CHECK17-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 9730 // CHECK17-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9731 // CHECK17: .omp.final.then: 9732 // CHECK17-NEXT: store i8 96, i8* [[IT]], align 1 9733 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9734 // CHECK17: .omp.final.done: 9735 // CHECK17-NEXT: ret void 9736 // 9737 // 9738 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 9739 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9740 // CHECK17-NEXT: entry: 9741 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9742 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9743 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9744 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9745 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9746 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9747 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 9748 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9749 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9750 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 9751 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9752 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9753 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9754 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 9755 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9756 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9757 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9758 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 9759 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 9760 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 9761 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9762 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 9763 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9764 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 9765 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 9766 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 9767 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 9768 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 9769 // CHECK17-NEXT: ret void 9770 // 9771 // 9772 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 9773 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9774 // CHECK17-NEXT: entry: 9775 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9776 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9777 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9778 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9779 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 9780 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9781 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 9782 // CHECK17-NEXT: [[TMP:%.*]] = alloca i32, align 4 9783 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9784 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9785 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9786 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9787 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 9788 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9789 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9790 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9791 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 9792 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9793 // CHECK17-NEXT: ret void 9794 // 9795 // 9796 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 9797 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 9798 // CHECK17-NEXT: entry: 9799 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 9800 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9801 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9802 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9803 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 9804 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 9805 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 9806 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 9807 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9808 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9809 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 9810 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 9811 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 9812 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9813 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9814 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 9815 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 9816 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 9817 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 9818 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 9819 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 9820 // CHECK17-NEXT: ret void 9821 // 9822 // 9823 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..5 9824 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 9825 // CHECK17-NEXT: entry: 9826 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9827 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9828 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 9829 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 9830 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 9831 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 9832 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 9833 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9834 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9835 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9836 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9837 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9838 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9839 // CHECK17-NEXT: [[IT:%.*]] = alloca i64, align 8 9840 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9841 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9842 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 9843 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 9844 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 9845 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 9846 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 9847 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 9848 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 9849 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 9850 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 9851 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 9852 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9853 // CHECK17-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 9854 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9855 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9856 // CHECK17-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9857 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 9858 // CHECK17-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9859 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9860 // CHECK17-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 9861 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9862 // CHECK17: cond.true: 9863 // CHECK17-NEXT: br label [[COND_END:%.*]] 9864 // CHECK17: cond.false: 9865 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9866 // CHECK17-NEXT: br label [[COND_END]] 9867 // CHECK17: cond.end: 9868 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 9869 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9870 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9871 // CHECK17-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 9872 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9873 // CHECK17: omp.inner.for.cond: 9874 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]] 9875 // CHECK17-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]] 9876 // CHECK17-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 9877 // CHECK17-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9878 // CHECK17: omp.inner.for.body: 9879 // CHECK17-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9880 // CHECK17-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 9881 // CHECK17-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 9882 // CHECK17-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP26]] 9883 // CHECK17-NEXT: [[TMP12:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP26]] 9884 // CHECK17-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP12]] to double 9885 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 9886 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 9887 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8, !llvm.access.group [[ACC_GRP26]] 9888 // CHECK17-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 9889 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[A5]], align 8, !llvm.access.group [[ACC_GRP26]] 9890 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 9891 // CHECK17-NEXT: store double [[INC]], double* [[A5]], align 8, !llvm.access.group [[ACC_GRP26]] 9892 // CHECK17-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 9893 // CHECK17-NEXT: [[TMP14:%.*]] = mul nsw i64 1, [[TMP2]] 9894 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP14]] 9895 // CHECK17-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 9896 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP26]] 9897 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9898 // CHECK17: omp.body.continue: 9899 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9900 // CHECK17: omp.inner.for.inc: 9901 // CHECK17-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9902 // CHECK17-NEXT: [[ADD8:%.*]] = add i64 [[TMP15]], 1 9903 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 9904 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP27:![0-9]+]] 9905 // CHECK17: omp.inner.for.end: 9906 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9907 // CHECK17: omp.loop.exit: 9908 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 9909 // CHECK17-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 9910 // CHECK17-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 9911 // CHECK17-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 9912 // CHECK17: .omp.final.then: 9913 // CHECK17-NEXT: store i64 400, i64* [[IT]], align 8 9914 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 9915 // CHECK17: .omp.final.done: 9916 // CHECK17-NEXT: ret void 9917 // 9918 // 9919 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 9920 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 9921 // CHECK17-NEXT: entry: 9922 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9923 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9924 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9925 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9926 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9927 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9928 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9929 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9930 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9931 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9932 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9933 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 9934 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9935 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 9936 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 9937 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 9938 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9939 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 9940 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9941 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 9942 // CHECK17-NEXT: ret void 9943 // 9944 // 9945 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..6 9946 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 9947 // CHECK17-NEXT: entry: 9948 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9949 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9950 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9951 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9952 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 9953 // CHECK17-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 9954 // CHECK17-NEXT: [[TMP:%.*]] = alloca i64, align 8 9955 // CHECK17-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 9956 // CHECK17-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 9957 // CHECK17-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 9958 // CHECK17-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 9959 // CHECK17-NEXT: [[I:%.*]] = alloca i64, align 8 9960 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9961 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9962 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9963 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9964 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 9965 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9966 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9967 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 9968 // CHECK17-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9969 // CHECK17-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 9970 // CHECK17-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9971 // CHECK17-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9972 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9973 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 9974 // CHECK17-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9975 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9976 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 9977 // CHECK17-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9978 // CHECK17: cond.true: 9979 // CHECK17-NEXT: br label [[COND_END:%.*]] 9980 // CHECK17: cond.false: 9981 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9982 // CHECK17-NEXT: br label [[COND_END]] 9983 // CHECK17: cond.end: 9984 // CHECK17-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 9985 // CHECK17-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9986 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9987 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 9988 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9989 // CHECK17: omp.inner.for.cond: 9990 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29:![0-9]+]] 9991 // CHECK17-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP29]] 9992 // CHECK17-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 9993 // CHECK17-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9994 // CHECK17: omp.inner.for.body: 9995 // CHECK17-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 9996 // CHECK17-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 9997 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 9998 // CHECK17-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP29]] 9999 // CHECK17-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP29]] 10000 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 10001 // CHECK17-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP29]] 10002 // CHECK17-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP29]] 10003 // CHECK17-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 10004 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 10005 // CHECK17-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 10006 // CHECK17-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP29]] 10007 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10008 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] 10009 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 10010 // CHECK17-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP29]] 10011 // CHECK17-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10012 // CHECK17: omp.body.continue: 10013 // CHECK17-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10014 // CHECK17: omp.inner.for.inc: 10015 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 10016 // CHECK17-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 10017 // CHECK17-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP29]] 10018 // CHECK17-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP30:![0-9]+]] 10019 // CHECK17: omp.inner.for.end: 10020 // CHECK17-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10021 // CHECK17: omp.loop.exit: 10022 // CHECK17-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 10023 // CHECK17-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10024 // CHECK17-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 10025 // CHECK17-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10026 // CHECK17: .omp.final.then: 10027 // CHECK17-NEXT: store i64 11, i64* [[I]], align 8 10028 // CHECK17-NEXT: br label [[DOTOMP_FINAL_DONE]] 10029 // CHECK17: .omp.final.done: 10030 // CHECK17-NEXT: ret void 10031 // 10032 // 10033 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 10034 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] { 10035 // CHECK19-NEXT: entry: 10036 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10037 // CHECK19-NEXT: ret void 10038 // 10039 // 10040 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 10041 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10042 // CHECK19-NEXT: entry: 10043 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10044 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10045 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10046 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10047 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10048 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10049 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10050 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10051 // CHECK19-NEXT: [[I:%.*]] = alloca i32, align 4 10052 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10053 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10054 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10055 // CHECK19-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 10056 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10057 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10058 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10059 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10060 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10061 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10062 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 10063 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10064 // CHECK19: cond.true: 10065 // CHECK19-NEXT: br label [[COND_END:%.*]] 10066 // CHECK19: cond.false: 10067 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10068 // CHECK19-NEXT: br label [[COND_END]] 10069 // CHECK19: cond.end: 10070 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10071 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10072 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10073 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10074 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10075 // CHECK19: omp.inner.for.cond: 10076 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 10077 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 10078 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10079 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10080 // CHECK19: omp.inner.for.body: 10081 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 10082 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 10083 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 10084 // CHECK19-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 10085 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10086 // CHECK19: omp.body.continue: 10087 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10088 // CHECK19: omp.inner.for.inc: 10089 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 10090 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10091 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 10092 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 10093 // CHECK19: omp.inner.for.end: 10094 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10095 // CHECK19: omp.loop.exit: 10096 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10097 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10098 // CHECK19-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 10099 // CHECK19-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10100 // CHECK19: .omp.final.then: 10101 // CHECK19-NEXT: store i32 33, i32* [[I]], align 4 10102 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10103 // CHECK19: .omp.final.done: 10104 // CHECK19-NEXT: ret void 10105 // 10106 // 10107 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 10108 // CHECK19-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 10109 // CHECK19-NEXT: entry: 10110 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10111 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 10112 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10113 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10114 // CHECK19-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 10115 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10116 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10117 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 10118 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10119 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10120 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10121 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10122 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 10123 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10124 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 10125 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 10126 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 10127 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 10128 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 10129 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 10130 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 10131 // CHECK19-NEXT: ret void 10132 // 10133 // 10134 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..1 10135 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 10136 // CHECK19-NEXT: entry: 10137 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10138 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10139 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10140 // CHECK19-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 10141 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10142 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10143 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10144 // CHECK19-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 10145 // CHECK19-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 10146 // CHECK19-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 10147 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10148 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10149 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10150 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10151 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 10152 // CHECK19-NEXT: [[LIN2:%.*]] = alloca i32, align 4 10153 // CHECK19-NEXT: [[A3:%.*]] = alloca i32, align 4 10154 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10155 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10156 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10157 // CHECK19-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 10158 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10159 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10160 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 10161 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 10162 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10163 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 10164 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 10165 // CHECK19-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 10166 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10167 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 10168 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10169 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10170 // CHECK19-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10171 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 10172 // CHECK19-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 10173 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10174 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10175 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 10176 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10177 // CHECK19: cond.true: 10178 // CHECK19-NEXT: br label [[COND_END:%.*]] 10179 // CHECK19: cond.false: 10180 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10181 // CHECK19-NEXT: br label [[COND_END]] 10182 // CHECK19: cond.end: 10183 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 10184 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 10185 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 10186 // CHECK19-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 10187 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10188 // CHECK19: omp.inner.for.cond: 10189 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 10190 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 10191 // CHECK19-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 10192 // CHECK19-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10193 // CHECK19: omp.inner.for.body: 10194 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 10195 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 10196 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10197 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 10198 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]] 10199 // CHECK19-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 10200 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 10201 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 10202 // CHECK19-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 10203 // CHECK19-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 10204 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 10205 // CHECK19-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]] 10206 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]] 10207 // CHECK19-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 10208 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 10209 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 10210 // CHECK19-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 10211 // CHECK19-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 10212 // CHECK19-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 10213 // CHECK19-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group [[ACC_GRP18]] 10214 // CHECK19-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP18]] 10215 // CHECK19-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 10216 // CHECK19-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 10217 // CHECK19-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 10218 // CHECK19-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP18]] 10219 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10220 // CHECK19: omp.body.continue: 10221 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10222 // CHECK19: omp.inner.for.inc: 10223 // CHECK19-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 10224 // CHECK19-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 10225 // CHECK19-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 10226 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 10227 // CHECK19: omp.inner.for.end: 10228 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10229 // CHECK19: omp.loop.exit: 10230 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 10231 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10232 // CHECK19-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 10233 // CHECK19-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10234 // CHECK19: .omp.final.then: 10235 // CHECK19-NEXT: store i64 400, i64* [[IT]], align 8 10236 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10237 // CHECK19: .omp.final.done: 10238 // CHECK19-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10239 // CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 10240 // CHECK19-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 10241 // CHECK19: .omp.linear.pu: 10242 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 10243 // CHECK19-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 10244 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 10245 // CHECK19-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 10246 // CHECK19-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 10247 // CHECK19: .omp.linear.pu.done: 10248 // CHECK19-NEXT: ret void 10249 // 10250 // 10251 // CHECK19-LABEL: define {{[^@]+}}@_Z7get_valv 10252 // CHECK19-SAME: () #[[ATTR3:[0-9]+]] { 10253 // CHECK19-NEXT: entry: 10254 // CHECK19-NEXT: ret i64 0 10255 // 10256 // 10257 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 10258 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 10259 // CHECK19-NEXT: entry: 10260 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10261 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10262 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10263 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10264 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10265 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10266 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10267 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 10268 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 10269 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 10270 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 10271 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10272 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 10273 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10274 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 10275 // CHECK19-NEXT: ret void 10276 // 10277 // 10278 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 10279 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 10280 // CHECK19-NEXT: entry: 10281 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10282 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10283 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10284 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10285 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10286 // CHECK19-NEXT: [[TMP:%.*]] = alloca i16, align 2 10287 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10288 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10289 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10290 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10291 // CHECK19-NEXT: [[IT:%.*]] = alloca i16, align 2 10292 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10293 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10294 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10295 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10296 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10297 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10298 // CHECK19-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 10299 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10300 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10301 // CHECK19-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10302 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10303 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10304 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10305 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 10306 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10307 // CHECK19: cond.true: 10308 // CHECK19-NEXT: br label [[COND_END:%.*]] 10309 // CHECK19: cond.false: 10310 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10311 // CHECK19-NEXT: br label [[COND_END]] 10312 // CHECK19: cond.end: 10313 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10314 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10315 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10316 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10317 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10318 // CHECK19: omp.inner.for.cond: 10319 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 10320 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 10321 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10322 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10323 // CHECK19: omp.inner.for.body: 10324 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 10325 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 10326 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 10327 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 10328 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group [[ACC_GRP21]] 10329 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 10330 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 10331 // CHECK19-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 10332 // CHECK19-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP21]] 10333 // CHECK19-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 10334 // CHECK19-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 10335 // CHECK19-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 10336 // CHECK19-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP21]] 10337 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10338 // CHECK19: omp.body.continue: 10339 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10340 // CHECK19: omp.inner.for.inc: 10341 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 10342 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 10343 // CHECK19-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 10344 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 10345 // CHECK19: omp.inner.for.end: 10346 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10347 // CHECK19: omp.loop.exit: 10348 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10349 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10350 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 10351 // CHECK19-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10352 // CHECK19: .omp.final.then: 10353 // CHECK19-NEXT: store i16 22, i16* [[IT]], align 2 10354 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10355 // CHECK19: .omp.final.done: 10356 // CHECK19-NEXT: ret void 10357 // 10358 // 10359 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 10360 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 10361 // CHECK19-NEXT: entry: 10362 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10363 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 10364 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10365 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 10366 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 10367 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10368 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10369 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 10370 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 10371 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 10372 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10373 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 10374 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10375 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 10376 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10377 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 10378 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 10379 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10380 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 10381 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 10382 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 10383 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 10384 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 10385 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10386 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 10387 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 10388 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10389 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 10390 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 10391 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 10392 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 10393 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 10394 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 10395 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 10396 // CHECK19-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 10397 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 10398 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 10399 // CHECK19-NEXT: ret void 10400 // 10401 // 10402 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 10403 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 10404 // CHECK19-NEXT: entry: 10405 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10406 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10407 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10408 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 10409 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10410 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 10411 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 10412 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10413 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10414 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 10415 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 10416 // CHECK19-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 10417 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10418 // CHECK19-NEXT: [[TMP:%.*]] = alloca i8, align 1 10419 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10420 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10421 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10422 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10423 // CHECK19-NEXT: [[IT:%.*]] = alloca i8, align 1 10424 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10425 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10426 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10427 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 10428 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10429 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 10430 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 10431 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10432 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 10433 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 10434 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 10435 // CHECK19-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 10436 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 10437 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10438 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 10439 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 10440 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10441 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 10442 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 10443 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 10444 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10445 // CHECK19-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 10446 // CHECK19-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10447 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10448 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 10449 // CHECK19-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10450 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 10451 // CHECK19-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 10452 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 10453 // CHECK19: omp.dispatch.cond: 10454 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10455 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 10456 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10457 // CHECK19: cond.true: 10458 // CHECK19-NEXT: br label [[COND_END:%.*]] 10459 // CHECK19: cond.false: 10460 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10461 // CHECK19-NEXT: br label [[COND_END]] 10462 // CHECK19: cond.end: 10463 // CHECK19-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 10464 // CHECK19-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10465 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10466 // CHECK19-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 10467 // CHECK19-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 10468 // CHECK19-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10469 // CHECK19-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 10470 // CHECK19-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 10471 // CHECK19: omp.dispatch.body: 10472 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10473 // CHECK19: omp.inner.for.cond: 10474 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 10475 // CHECK19-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 10476 // CHECK19-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 10477 // CHECK19-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10478 // CHECK19: omp.inner.for.body: 10479 // CHECK19-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10480 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 10481 // CHECK19-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 10482 // CHECK19-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 10483 // CHECK19-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group [[ACC_GRP24]] 10484 // CHECK19-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 10485 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 10486 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 10487 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 10488 // CHECK19-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 10489 // CHECK19-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 10490 // CHECK19-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 10491 // CHECK19-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 10492 // CHECK19-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 10493 // CHECK19-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 10494 // CHECK19-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 10495 // CHECK19-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 10496 // CHECK19-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 10497 // CHECK19-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 10498 // CHECK19-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 10499 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 10500 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 10501 // CHECK19-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 10502 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 10503 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 10504 // CHECK19-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 10505 // CHECK19-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 10506 // CHECK19-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 10507 // CHECK19-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 10508 // CHECK19-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 10509 // CHECK19-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 10510 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10511 // CHECK19-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 10512 // CHECK19-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 10513 // CHECK19-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 10514 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10515 // CHECK19-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 10516 // CHECK19-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 10517 // CHECK19-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 10518 // CHECK19-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 10519 // CHECK19-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 10520 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10521 // CHECK19: omp.body.continue: 10522 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10523 // CHECK19: omp.inner.for.inc: 10524 // CHECK19-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10525 // CHECK19-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 10526 // CHECK19-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 10527 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 10528 // CHECK19: omp.inner.for.end: 10529 // CHECK19-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 10530 // CHECK19: omp.dispatch.inc: 10531 // CHECK19-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10532 // CHECK19-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10533 // CHECK19-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 10534 // CHECK19-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 10535 // CHECK19-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10536 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 10537 // CHECK19-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 10538 // CHECK19-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 10539 // CHECK19-NEXT: br label [[OMP_DISPATCH_COND]] 10540 // CHECK19: omp.dispatch.end: 10541 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 10542 // CHECK19-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10543 // CHECK19-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 10544 // CHECK19-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10545 // CHECK19: .omp.final.then: 10546 // CHECK19-NEXT: store i8 96, i8* [[IT]], align 1 10547 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10548 // CHECK19: .omp.final.done: 10549 // CHECK19-NEXT: ret void 10550 // 10551 // 10552 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 10553 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10554 // CHECK19-NEXT: entry: 10555 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10556 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10557 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10558 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10559 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10560 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10561 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 10562 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10563 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10564 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 10565 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10566 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10567 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 10568 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10569 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10570 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 10571 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 10572 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 10573 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10574 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 10575 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10576 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 10577 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 10578 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 10579 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 10580 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 10581 // CHECK19-NEXT: ret void 10582 // 10583 // 10584 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 10585 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10586 // CHECK19-NEXT: entry: 10587 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10588 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10589 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10590 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10591 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10592 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10593 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10594 // CHECK19-NEXT: [[TMP:%.*]] = alloca i32, align 4 10595 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10596 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10597 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10598 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10599 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 10600 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10601 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10602 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 10603 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10604 // CHECK19-NEXT: ret void 10605 // 10606 // 10607 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 10608 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10609 // CHECK19-NEXT: entry: 10610 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 10611 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10612 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10613 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10614 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 10615 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 10616 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 10617 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 10618 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10619 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10620 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 10621 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 10622 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10623 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10624 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 10625 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 10626 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 10627 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 10628 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 10629 // CHECK19-NEXT: ret void 10630 // 10631 // 10632 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..5 10633 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10634 // CHECK19-NEXT: entry: 10635 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10636 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10637 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 10638 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 10639 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10640 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10641 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 10642 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10643 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10644 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10645 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10646 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10647 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10648 // CHECK19-NEXT: [[IT:%.*]] = alloca i64, align 8 10649 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10650 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10651 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 10652 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 10653 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10654 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10655 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 10656 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 10657 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10658 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10659 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 10660 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10661 // CHECK19-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 10662 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10663 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10664 // CHECK19-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10665 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 10666 // CHECK19-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10667 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10668 // CHECK19-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP6]], 3 10669 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10670 // CHECK19: cond.true: 10671 // CHECK19-NEXT: br label [[COND_END:%.*]] 10672 // CHECK19: cond.false: 10673 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10674 // CHECK19-NEXT: br label [[COND_END]] 10675 // CHECK19: cond.end: 10676 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 10677 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 10678 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 10679 // CHECK19-NEXT: store i64 [[TMP8]], i64* [[DOTOMP_IV]], align 8 10680 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10681 // CHECK19: omp.inner.for.cond: 10682 // CHECK19-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]] 10683 // CHECK19-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]] 10684 // CHECK19-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP9]], [[TMP10]] 10685 // CHECK19-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10686 // CHECK19: omp.inner.for.body: 10687 // CHECK19-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10688 // CHECK19-NEXT: [[MUL:%.*]] = mul i64 [[TMP11]], 400 10689 // CHECK19-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 10690 // CHECK19-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP27]] 10691 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 10692 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP12]] to double 10693 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 10694 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 10695 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4, !llvm.access.group [[ACC_GRP27]] 10696 // CHECK19-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 10697 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[A4]], align 4, !llvm.access.group [[ACC_GRP27]] 10698 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP13]], 1.000000e+00 10699 // CHECK19-NEXT: store double [[INC]], double* [[A4]], align 4, !llvm.access.group [[ACC_GRP27]] 10700 // CHECK19-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10701 // CHECK19-NEXT: [[TMP14:%.*]] = mul nsw i32 1, [[TMP2]] 10702 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP14]] 10703 // CHECK19-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 10704 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2, !llvm.access.group [[ACC_GRP27]] 10705 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10706 // CHECK19: omp.body.continue: 10707 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10708 // CHECK19: omp.inner.for.inc: 10709 // CHECK19-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10710 // CHECK19-NEXT: [[ADD7:%.*]] = add i64 [[TMP15]], 1 10711 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 10712 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 10713 // CHECK19: omp.inner.for.end: 10714 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10715 // CHECK19: omp.loop.exit: 10716 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 10717 // CHECK19-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10718 // CHECK19-NEXT: [[TMP17:%.*]] = icmp ne i32 [[TMP16]], 0 10719 // CHECK19-NEXT: br i1 [[TMP17]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10720 // CHECK19: .omp.final.then: 10721 // CHECK19-NEXT: store i64 400, i64* [[IT]], align 8 10722 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10723 // CHECK19: .omp.final.done: 10724 // CHECK19-NEXT: ret void 10725 // 10726 // 10727 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 10728 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10729 // CHECK19-NEXT: entry: 10730 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10731 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10732 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10733 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10734 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10735 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10736 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10737 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10738 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10739 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10740 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10741 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 10742 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 10743 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 10744 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10745 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 10746 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10747 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 10748 // CHECK19-NEXT: ret void 10749 // 10750 // 10751 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..6 10752 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10753 // CHECK19-NEXT: entry: 10754 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10755 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10756 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10757 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10758 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10759 // CHECK19-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10760 // CHECK19-NEXT: [[TMP:%.*]] = alloca i64, align 4 10761 // CHECK19-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10762 // CHECK19-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10763 // CHECK19-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10764 // CHECK19-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10765 // CHECK19-NEXT: [[I:%.*]] = alloca i64, align 8 10766 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10767 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10768 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10769 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10770 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10771 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10772 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10773 // CHECK19-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10774 // CHECK19-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 10775 // CHECK19-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10776 // CHECK19-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10777 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10778 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10779 // CHECK19-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10780 // CHECK19-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10781 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 10782 // CHECK19-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10783 // CHECK19: cond.true: 10784 // CHECK19-NEXT: br label [[COND_END:%.*]] 10785 // CHECK19: cond.false: 10786 // CHECK19-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10787 // CHECK19-NEXT: br label [[COND_END]] 10788 // CHECK19: cond.end: 10789 // CHECK19-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 10790 // CHECK19-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 10791 // CHECK19-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 10792 // CHECK19-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 10793 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10794 // CHECK19: omp.inner.for.cond: 10795 // CHECK19-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30:![0-9]+]] 10796 // CHECK19-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP30]] 10797 // CHECK19-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 10798 // CHECK19-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10799 // CHECK19: omp.inner.for.body: 10800 // CHECK19-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10801 // CHECK19-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 10802 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 10803 // CHECK19-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP30]] 10804 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] 10805 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 10806 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP30]] 10807 // CHECK19-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP30]] 10808 // CHECK19-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 10809 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10810 // CHECK19-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10811 // CHECK19-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP30]] 10812 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 10813 // CHECK19-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] 10814 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 10815 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP30]] 10816 // CHECK19-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10817 // CHECK19: omp.body.continue: 10818 // CHECK19-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10819 // CHECK19: omp.inner.for.inc: 10820 // CHECK19-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10821 // CHECK19-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 10822 // CHECK19-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP30]] 10823 // CHECK19-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP31:![0-9]+]] 10824 // CHECK19: omp.inner.for.end: 10825 // CHECK19-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10826 // CHECK19: omp.loop.exit: 10827 // CHECK19-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 10828 // CHECK19-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10829 // CHECK19-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 10830 // CHECK19-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10831 // CHECK19: .omp.final.then: 10832 // CHECK19-NEXT: store i64 11, i64* [[I]], align 8 10833 // CHECK19-NEXT: br label [[DOTOMP_FINAL_DONE]] 10834 // CHECK19: .omp.final.done: 10835 // CHECK19-NEXT: ret void 10836 // 10837 // 10838 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 10839 // CHECK21-SAME: () #[[ATTR0:[0-9]+]] { 10840 // CHECK21-NEXT: entry: 10841 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10842 // CHECK21-NEXT: ret void 10843 // 10844 // 10845 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined. 10846 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10847 // CHECK21-NEXT: entry: 10848 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10849 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10850 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 10851 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 10852 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 10853 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 10854 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 10855 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10856 // CHECK21-NEXT: [[I:%.*]] = alloca i32, align 4 10857 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10858 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10859 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 10860 // CHECK21-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 10861 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 10862 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10863 // CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10864 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 10865 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 10866 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10867 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 10868 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10869 // CHECK21: cond.true: 10870 // CHECK21-NEXT: br label [[COND_END:%.*]] 10871 // CHECK21: cond.false: 10872 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 10873 // CHECK21-NEXT: br label [[COND_END]] 10874 // CHECK21: cond.end: 10875 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 10876 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 10877 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 10878 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 10879 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10880 // CHECK21: omp.inner.for.cond: 10881 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11:![0-9]+]] 10882 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP11]] 10883 // CHECK21-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 10884 // CHECK21-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 10885 // CHECK21: omp.inner.for.body: 10886 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10887 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 10888 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 10889 // CHECK21-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP11]] 10890 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 10891 // CHECK21: omp.body.continue: 10892 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 10893 // CHECK21: omp.inner.for.inc: 10894 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10895 // CHECK21-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 10896 // CHECK21-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP11]] 10897 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 10898 // CHECK21: omp.inner.for.end: 10899 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 10900 // CHECK21: omp.loop.exit: 10901 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 10902 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 10903 // CHECK21-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 10904 // CHECK21-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 10905 // CHECK21: .omp.final.then: 10906 // CHECK21-NEXT: store i32 33, i32* [[I]], align 4 10907 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 10908 // CHECK21: .omp.final.done: 10909 // CHECK21-NEXT: ret void 10910 // 10911 // 10912 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 10913 // CHECK21-SAME: (i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR0]] { 10914 // CHECK21-NEXT: entry: 10915 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10916 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10917 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10918 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10919 // CHECK21-NEXT: [[LIN_CASTED:%.*]] = alloca i64, align 8 10920 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10921 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10922 // CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 10923 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10924 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10925 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 10926 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10927 // CHECK21-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10928 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10929 // CHECK21-NEXT: store i16 [[TMP0]], i16* [[CONV3]], align 2 10930 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10931 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV1]], align 4 10932 // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[LIN_CASTED]] to i32* 10933 // CHECK21-NEXT: store i32 [[TMP2]], i32* [[CONV4]], align 4 10934 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[LIN_CASTED]], align 8 10935 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV2]], align 4 10936 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10937 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 10938 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[A_CASTED]], align 8 10939 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]]) 10940 // CHECK21-NEXT: ret void 10941 // 10942 // 10943 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..1 10944 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[LIN:%.*]], i64 noundef [[A:%.*]]) #[[ATTR1]] { 10945 // CHECK21-NEXT: entry: 10946 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10947 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10948 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10949 // CHECK21-NEXT: [[LIN_ADDR:%.*]] = alloca i64, align 8 10950 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10951 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 10952 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 10953 // CHECK21-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 10954 // CHECK21-NEXT: [[DOTLINEAR_START3:%.*]] = alloca i32, align 4 10955 // CHECK21-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 10956 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 10957 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 10958 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 10959 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 10960 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 10961 // CHECK21-NEXT: [[LIN4:%.*]] = alloca i32, align 4 10962 // CHECK21-NEXT: [[A5:%.*]] = alloca i32, align 4 10963 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10964 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10965 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10966 // CHECK21-NEXT: store i64 [[LIN]], i64* [[LIN_ADDR]], align 8 10967 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10968 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10969 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[LIN_ADDR]] to i32* 10970 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10971 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV1]], align 4 10972 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 10973 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV2]], align 4 10974 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START3]], align 4 10975 // CHECK21-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 10976 // CHECK21-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 10977 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 10978 // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 10979 // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 10980 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 10981 // CHECK21-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10982 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 10983 // CHECK21-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 10984 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 10985 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10986 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 10987 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 10988 // CHECK21: cond.true: 10989 // CHECK21-NEXT: br label [[COND_END:%.*]] 10990 // CHECK21: cond.false: 10991 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 10992 // CHECK21-NEXT: br label [[COND_END]] 10993 // CHECK21: cond.end: 10994 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 10995 // CHECK21-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 10996 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 10997 // CHECK21-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 10998 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 10999 // CHECK21: omp.inner.for.cond: 11000 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17:![0-9]+]] 11001 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP17]] 11002 // CHECK21-NEXT: [[CMP6:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 11003 // CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11004 // CHECK21: omp.inner.for.body: 11005 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 11006 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 11007 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11008 // CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP17]] 11009 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP17]] 11010 // CHECK21-NEXT: [[CONV7:%.*]] = sext i32 [[TMP10]] to i64 11011 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 11012 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 11013 // CHECK21-NEXT: [[MUL8:%.*]] = mul i64 [[TMP11]], [[TMP12]] 11014 // CHECK21-NEXT: [[ADD:%.*]] = add i64 [[CONV7]], [[MUL8]] 11015 // CHECK21-NEXT: [[CONV9:%.*]] = trunc i64 [[ADD]] to i32 11016 // CHECK21-NEXT: store i32 [[CONV9]], i32* [[LIN4]], align 4, !llvm.access.group [[ACC_GRP17]] 11017 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START3]], align 4, !llvm.access.group [[ACC_GRP17]] 11018 // CHECK21-NEXT: [[CONV10:%.*]] = sext i32 [[TMP13]] to i64 11019 // CHECK21-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 11020 // CHECK21-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP17]] 11021 // CHECK21-NEXT: [[MUL11:%.*]] = mul i64 [[TMP14]], [[TMP15]] 11022 // CHECK21-NEXT: [[ADD12:%.*]] = add i64 [[CONV10]], [[MUL11]] 11023 // CHECK21-NEXT: [[CONV13:%.*]] = trunc i64 [[ADD12]] to i32 11024 // CHECK21-NEXT: store i32 [[CONV13]], i32* [[A5]], align 4, !llvm.access.group [[ACC_GRP17]] 11025 // CHECK21-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP17]] 11026 // CHECK21-NEXT: [[CONV14:%.*]] = sext i16 [[TMP16]] to i32 11027 // CHECK21-NEXT: [[ADD15:%.*]] = add nsw i32 [[CONV14]], 1 11028 // CHECK21-NEXT: [[CONV16:%.*]] = trunc i32 [[ADD15]] to i16 11029 // CHECK21-NEXT: store i16 [[CONV16]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP17]] 11030 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11031 // CHECK21: omp.body.continue: 11032 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11033 // CHECK21: omp.inner.for.inc: 11034 // CHECK21-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 11035 // CHECK21-NEXT: [[ADD17:%.*]] = add i64 [[TMP17]], 1 11036 // CHECK21-NEXT: store i64 [[ADD17]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP17]] 11037 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP18:![0-9]+]] 11038 // CHECK21: omp.inner.for.end: 11039 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11040 // CHECK21: omp.loop.exit: 11041 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 11042 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11043 // CHECK21-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 11044 // CHECK21-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11045 // CHECK21: .omp.final.then: 11046 // CHECK21-NEXT: store i64 400, i64* [[IT]], align 8 11047 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11048 // CHECK21: .omp.final.done: 11049 // CHECK21-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11050 // CHECK21-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 11051 // CHECK21-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 11052 // CHECK21: .omp.linear.pu: 11053 // CHECK21-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN4]], align 4 11054 // CHECK21-NEXT: store i32 [[TMP22]], i32* [[CONV1]], align 4 11055 // CHECK21-NEXT: [[TMP23:%.*]] = load i32, i32* [[A5]], align 4 11056 // CHECK21-NEXT: store i32 [[TMP23]], i32* [[CONV2]], align 4 11057 // CHECK21-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 11058 // CHECK21: .omp.linear.pu.done: 11059 // CHECK21-NEXT: ret void 11060 // 11061 // 11062 // CHECK21-LABEL: define {{[^@]+}}@_Z7get_valv 11063 // CHECK21-SAME: () #[[ATTR3:[0-9]+]] { 11064 // CHECK21-NEXT: entry: 11065 // CHECK21-NEXT: ret i64 0 11066 // 11067 // 11068 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 11069 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 11070 // CHECK21-NEXT: entry: 11071 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11072 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11073 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11074 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11075 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11076 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11077 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11078 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11079 // CHECK21-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 11080 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11081 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 11082 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 11083 // CHECK21-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 11084 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11085 // CHECK21-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 11086 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11087 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 11088 // CHECK21-NEXT: ret void 11089 // 11090 // 11091 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..2 11092 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 11093 // CHECK21-NEXT: entry: 11094 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11095 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11096 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11097 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11098 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11099 // CHECK21-NEXT: [[TMP:%.*]] = alloca i16, align 2 11100 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11101 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11102 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11103 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11104 // CHECK21-NEXT: [[IT:%.*]] = alloca i16, align 2 11105 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11106 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11107 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11108 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11109 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11110 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11111 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11112 // CHECK21-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 11113 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11114 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11115 // CHECK21-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11116 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 11117 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11118 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11119 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 11120 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11121 // CHECK21: cond.true: 11122 // CHECK21-NEXT: br label [[COND_END:%.*]] 11123 // CHECK21: cond.false: 11124 // CHECK21-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11125 // CHECK21-NEXT: br label [[COND_END]] 11126 // CHECK21: cond.end: 11127 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11128 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11129 // CHECK21-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11130 // CHECK21-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11131 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11132 // CHECK21: omp.inner.for.cond: 11133 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20:![0-9]+]] 11134 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP20]] 11135 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11136 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11137 // CHECK21: omp.inner.for.body: 11138 // CHECK21-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 11139 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 11140 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 11141 // CHECK21-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD]] to i16 11142 // CHECK21-NEXT: store i16 [[CONV3]], i16* [[IT]], align 2, !llvm.access.group [[ACC_GRP20]] 11143 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP20]] 11144 // CHECK21-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1 11145 // CHECK21-NEXT: store i32 [[ADD4]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP20]] 11146 // CHECK21-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP20]] 11147 // CHECK21-NEXT: [[CONV5:%.*]] = sext i16 [[TMP9]] to i32 11148 // CHECK21-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 11149 // CHECK21-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16 11150 // CHECK21-NEXT: store i16 [[CONV7]], i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP20]] 11151 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11152 // CHECK21: omp.body.continue: 11153 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11154 // CHECK21: omp.inner.for.inc: 11155 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 11156 // CHECK21-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1 11157 // CHECK21-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP20]] 11158 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP21:![0-9]+]] 11159 // CHECK21: omp.inner.for.end: 11160 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11161 // CHECK21: omp.loop.exit: 11162 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11163 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11164 // CHECK21-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 11165 // CHECK21-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11166 // CHECK21: .omp.final.then: 11167 // CHECK21-NEXT: store i16 22, i16* [[IT]], align 2 11168 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11169 // CHECK21: .omp.final.done: 11170 // CHECK21-NEXT: ret void 11171 // 11172 // 11173 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 11174 // CHECK21-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11175 // CHECK21-NEXT: entry: 11176 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11177 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 11178 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11179 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 11180 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 11181 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11182 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 11183 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 11184 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 11185 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11186 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11187 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 11188 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11189 // CHECK21-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 11190 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11191 // CHECK21-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 11192 // CHECK21-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 11193 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11194 // CHECK21-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 11195 // CHECK21-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 11196 // CHECK21-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 11197 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 11198 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11199 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 11200 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11201 // CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 11202 // CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 11203 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11204 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 11205 // CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 11206 // CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 11207 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 11208 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 11209 // CHECK21-NEXT: [[CONV6:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11210 // CHECK21-NEXT: store i32 [[TMP8]], i32* [[CONV6]], align 4 11211 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 11212 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[CONV5]], align 4 11213 // CHECK21-NEXT: [[CONV7:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* 11214 // CHECK21-NEXT: store i32 [[TMP10]], i32* [[CONV7]], align 4 11215 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 11216 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i64 [[TMP11]]) 11217 // CHECK21-NEXT: ret void 11218 // 11219 // 11220 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..3 11221 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 11222 // CHECK21-NEXT: entry: 11223 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11224 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11225 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11226 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 11227 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11228 // CHECK21-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 11229 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 11230 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11231 // CHECK21-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 11232 // CHECK21-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 11233 // CHECK21-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 11234 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11235 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11236 // CHECK21-NEXT: [[TMP:%.*]] = alloca i8, align 1 11237 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11238 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11239 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11240 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11241 // CHECK21-NEXT: [[IT:%.*]] = alloca i8, align 1 11242 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11243 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11244 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11245 // CHECK21-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 11246 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11247 // CHECK21-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 11248 // CHECK21-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 11249 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11250 // CHECK21-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 11251 // CHECK21-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 11252 // CHECK21-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 11253 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 11254 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11255 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 11256 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11257 // CHECK21-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 11258 // CHECK21-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 11259 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11260 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 11261 // CHECK21-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 11262 // CHECK21-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 11263 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* 11264 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11265 // CHECK21-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 11266 // CHECK21-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11267 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11268 // CHECK21-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV5]], align 4 11269 // CHECK21-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11270 // CHECK21-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 11271 // CHECK21-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 11272 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 11273 // CHECK21: omp.dispatch.cond: 11274 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11275 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 11276 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11277 // CHECK21: cond.true: 11278 // CHECK21-NEXT: br label [[COND_END:%.*]] 11279 // CHECK21: cond.false: 11280 // CHECK21-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11281 // CHECK21-NEXT: br label [[COND_END]] 11282 // CHECK21: cond.end: 11283 // CHECK21-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 11284 // CHECK21-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11285 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11286 // CHECK21-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 11287 // CHECK21-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 11288 // CHECK21-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11289 // CHECK21-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 11290 // CHECK21-NEXT: br i1 [[CMP6]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 11291 // CHECK21: omp.dispatch.body: 11292 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11293 // CHECK21: omp.inner.for.cond: 11294 // CHECK21-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23:![0-9]+]] 11295 // CHECK21-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP23]] 11296 // CHECK21-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 11297 // CHECK21-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11298 // CHECK21: omp.inner.for.body: 11299 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 11300 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 11301 // CHECK21-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 11302 // CHECK21-NEXT: [[CONV8:%.*]] = trunc i32 [[SUB]] to i8 11303 // CHECK21-NEXT: store i8 [[CONV8]], i8* [[IT]], align 1, !llvm.access.group [[ACC_GRP23]] 11304 // CHECK21-NEXT: [[TMP19:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP23]] 11305 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 11306 // CHECK21-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP23]] 11307 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 11308 // CHECK21-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 11309 // CHECK21-NEXT: [[CONV9:%.*]] = fpext float [[TMP20]] to double 11310 // CHECK21-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 11311 // CHECK21-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 11312 // CHECK21-NEXT: store float [[CONV11]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP23]] 11313 // CHECK21-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 11314 // CHECK21-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP23]] 11315 // CHECK21-NEXT: [[CONV13:%.*]] = fpext float [[TMP21]] to double 11316 // CHECK21-NEXT: [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00 11317 // CHECK21-NEXT: [[CONV15:%.*]] = fptrunc double [[ADD14]] to float 11318 // CHECK21-NEXT: store float [[CONV15]], float* [[ARRAYIDX12]], align 4, !llvm.access.group [[ACC_GRP23]] 11319 // CHECK21-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 11320 // CHECK21-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2 11321 // CHECK21-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP23]] 11322 // CHECK21-NEXT: [[ADD18:%.*]] = fadd double [[TMP22]], 1.000000e+00 11323 // CHECK21-NEXT: store double [[ADD18]], double* [[ARRAYIDX17]], align 8, !llvm.access.group [[ACC_GRP23]] 11324 // CHECK21-NEXT: [[TMP23:%.*]] = mul nsw i64 1, [[TMP5]] 11325 // CHECK21-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP23]] 11326 // CHECK21-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3 11327 // CHECK21-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX20]], align 8, !llvm.access.group [[ACC_GRP23]] 11328 // CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[TMP24]], 1.000000e+00 11329 // CHECK21-NEXT: store double [[ADD21]], double* [[ARRAYIDX20]], align 8, !llvm.access.group [[ACC_GRP23]] 11330 // CHECK21-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 11331 // CHECK21-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 11332 // CHECK21-NEXT: [[ADD22:%.*]] = add nsw i64 [[TMP25]], 1 11333 // CHECK21-NEXT: store i64 [[ADD22]], i64* [[X]], align 8, !llvm.access.group [[ACC_GRP23]] 11334 // CHECK21-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 11335 // CHECK21-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 11336 // CHECK21-NEXT: [[CONV23:%.*]] = sext i8 [[TMP26]] to i32 11337 // CHECK21-NEXT: [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1 11338 // CHECK21-NEXT: [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8 11339 // CHECK21-NEXT: store i8 [[CONV25]], i8* [[Y]], align 8, !llvm.access.group [[ACC_GRP23]] 11340 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11341 // CHECK21: omp.body.continue: 11342 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11343 // CHECK21: omp.inner.for.inc: 11344 // CHECK21-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 11345 // CHECK21-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP27]], 1 11346 // CHECK21-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP23]] 11347 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP24:![0-9]+]] 11348 // CHECK21: omp.inner.for.end: 11349 // CHECK21-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 11350 // CHECK21: omp.dispatch.inc: 11351 // CHECK21-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11352 // CHECK21-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 11353 // CHECK21-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 11354 // CHECK21-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_LB]], align 4 11355 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11356 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 11357 // CHECK21-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 11358 // CHECK21-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_UB]], align 4 11359 // CHECK21-NEXT: br label [[OMP_DISPATCH_COND]] 11360 // CHECK21: omp.dispatch.end: 11361 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 11362 // CHECK21-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11363 // CHECK21-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 11364 // CHECK21-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11365 // CHECK21: .omp.final.then: 11366 // CHECK21-NEXT: store i8 96, i8* [[IT]], align 1 11367 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11368 // CHECK21: .omp.final.done: 11369 // CHECK21-NEXT: ret void 11370 // 11371 // 11372 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 11373 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11374 // CHECK21-NEXT: entry: 11375 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11376 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11377 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11378 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11379 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11380 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11381 // CHECK21-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 11382 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11383 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11384 // CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11385 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11386 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11387 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11388 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11389 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11390 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11391 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11392 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 11393 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11394 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 11395 // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11396 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 11397 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11398 // CHECK21-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 11399 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 11400 // CHECK21-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 11401 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 11402 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 11403 // CHECK21-NEXT: ret void 11404 // 11405 // 11406 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..4 11407 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11408 // CHECK21-NEXT: entry: 11409 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11410 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11411 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11412 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11413 // CHECK21-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 11414 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11415 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11416 // CHECK21-NEXT: [[TMP:%.*]] = alloca i32, align 4 11417 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11418 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11419 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11420 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11421 // CHECK21-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 11422 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11423 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11424 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11425 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 11426 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11427 // CHECK21-NEXT: ret void 11428 // 11429 // 11430 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 11431 // CHECK21-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 11432 // CHECK21-NEXT: entry: 11433 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11434 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11435 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11436 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11437 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 11438 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11439 // CHECK21-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 11440 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 11441 // CHECK21-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 11442 // CHECK21-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 11443 // CHECK21-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 11444 // CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11445 // CHECK21-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 11446 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11447 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11448 // CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 11449 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 11450 // CHECK21-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11451 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 11452 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11453 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11454 // CHECK21-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 8 11455 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 11456 // CHECK21-NEXT: [[TMP5:%.*]] = load i32, i32* [[CONV]], align 4 11457 // CHECK21-NEXT: [[CONV4:%.*]] = bitcast i64* [[B_CASTED]] to i32* 11458 // CHECK21-NEXT: store i32 [[TMP5]], i32* [[CONV4]], align 4 11459 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 11460 // CHECK21-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV3]], align 1 11461 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 11462 // CHECK21-NEXT: [[CONV5:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 11463 // CHECK21-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 11464 // CHECK21-NEXT: store i8 [[FROMBOOL]], i8* [[CONV5]], align 1 11465 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 11466 // CHECK21-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV3]], align 1 11467 // CHECK21-NEXT: [[TOBOOL6:%.*]] = trunc i8 [[TMP9]] to i1 11468 // CHECK21-NEXT: br i1 [[TOBOOL6]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11469 // CHECK21: omp_if.then: 11470 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*, i64)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) 11471 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 11472 // CHECK21: omp_if.else: 11473 // CHECK21-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 11474 // CHECK21-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 11475 // CHECK21-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 11476 // CHECK21-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i64 [[TMP6]], i64 [[TMP2]], i64 [[TMP3]], i16* [[TMP4]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] 11477 // CHECK21-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 11478 // CHECK21-NEXT: br label [[OMP_IF_END]] 11479 // CHECK21: omp_if.end: 11480 // CHECK21-NEXT: ret void 11481 // 11482 // 11483 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..5 11484 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i64 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 11485 // CHECK21-NEXT: entry: 11486 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11487 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11488 // CHECK21-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 11489 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 11490 // CHECK21-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 11491 // CHECK21-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 11492 // CHECK21-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 11493 // CHECK21-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 11494 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11495 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 11496 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11497 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11498 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11499 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11500 // CHECK21-NEXT: [[IT:%.*]] = alloca i64, align 8 11501 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11502 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11503 // CHECK21-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 11504 // CHECK21-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 11505 // CHECK21-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 11506 // CHECK21-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 11507 // CHECK21-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 11508 // CHECK21-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 11509 // CHECK21-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 11510 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 11511 // CHECK21-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 11512 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 11513 // CHECK21-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 11514 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 11515 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11516 // CHECK21-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 11517 // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11518 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11519 // CHECK21-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV3]], align 1 11520 // CHECK21-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 11521 // CHECK21-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 11522 // CHECK21: omp_if.then: 11523 // CHECK21-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11524 // CHECK21-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 11525 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11526 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11527 // CHECK21-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 11528 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11529 // CHECK21: cond.true: 11530 // CHECK21-NEXT: br label [[COND_END:%.*]] 11531 // CHECK21: cond.false: 11532 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11533 // CHECK21-NEXT: br label [[COND_END]] 11534 // CHECK21: cond.end: 11535 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 11536 // CHECK21-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11537 // CHECK21-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11538 // CHECK21-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 11539 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11540 // CHECK21: omp.inner.for.cond: 11541 // CHECK21-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26:![0-9]+]] 11542 // CHECK21-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP26]] 11543 // CHECK21-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 11544 // CHECK21-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11545 // CHECK21: omp.inner.for.body: 11546 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11547 // CHECK21-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 11548 // CHECK21-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11549 // CHECK21-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP26]] 11550 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP26]] 11551 // CHECK21-NEXT: [[CONV5:%.*]] = sitofp i32 [[TMP13]] to double 11552 // CHECK21-NEXT: [[ADD:%.*]] = fadd double [[CONV5]], 1.500000e+00 11553 // CHECK21-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11554 // CHECK21-NEXT: store double [[ADD]], double* [[A]], align 8, !nontemporal !27, !llvm.access.group [[ACC_GRP26]] 11555 // CHECK21-NEXT: [[A6:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11556 // CHECK21-NEXT: [[TMP14:%.*]] = load double, double* [[A6]], align 8, !nontemporal !27, !llvm.access.group [[ACC_GRP26]] 11557 // CHECK21-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 11558 // CHECK21-NEXT: store double [[INC]], double* [[A6]], align 8, !nontemporal !27, !llvm.access.group [[ACC_GRP26]] 11559 // CHECK21-NEXT: [[CONV7:%.*]] = fptosi double [[INC]] to i16 11560 // CHECK21-NEXT: [[TMP15:%.*]] = mul nsw i64 1, [[TMP2]] 11561 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP15]] 11562 // CHECK21-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 11563 // CHECK21-NEXT: store i16 [[CONV7]], i16* [[ARRAYIDX8]], align 2, !llvm.access.group [[ACC_GRP26]] 11564 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11565 // CHECK21: omp.body.continue: 11566 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11567 // CHECK21: omp.inner.for.inc: 11568 // CHECK21-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11569 // CHECK21-NEXT: [[ADD9:%.*]] = add i64 [[TMP16]], 1 11570 // CHECK21-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP26]] 11571 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP28:![0-9]+]] 11572 // CHECK21: omp.inner.for.end: 11573 // CHECK21-NEXT: br label [[OMP_IF_END:%.*]] 11574 // CHECK21: omp_if.else: 11575 // CHECK21-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11576 // CHECK21-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 11577 // CHECK21-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11578 // CHECK21-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11579 // CHECK21-NEXT: [[CMP10:%.*]] = icmp ugt i64 [[TMP19]], 3 11580 // CHECK21-NEXT: br i1 [[CMP10]], label [[COND_TRUE11:%.*]], label [[COND_FALSE12:%.*]] 11581 // CHECK21: cond.true11: 11582 // CHECK21-NEXT: br label [[COND_END13:%.*]] 11583 // CHECK21: cond.false12: 11584 // CHECK21-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11585 // CHECK21-NEXT: br label [[COND_END13]] 11586 // CHECK21: cond.end13: 11587 // CHECK21-NEXT: [[COND14:%.*]] = phi i64 [ 3, [[COND_TRUE11]] ], [ [[TMP20]], [[COND_FALSE12]] ] 11588 // CHECK21-NEXT: store i64 [[COND14]], i64* [[DOTOMP_UB]], align 8 11589 // CHECK21-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11590 // CHECK21-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 11591 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND15:%.*]] 11592 // CHECK21: omp.inner.for.cond15: 11593 // CHECK21-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11594 // CHECK21-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11595 // CHECK21-NEXT: [[CMP16:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 11596 // CHECK21-NEXT: br i1 [[CMP16]], label [[OMP_INNER_FOR_BODY17:%.*]], label [[OMP_INNER_FOR_END31:%.*]] 11597 // CHECK21: omp.inner.for.body17: 11598 // CHECK21-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11599 // CHECK21-NEXT: [[MUL18:%.*]] = mul i64 [[TMP24]], 400 11600 // CHECK21-NEXT: [[SUB19:%.*]] = sub i64 2000, [[MUL18]] 11601 // CHECK21-NEXT: store i64 [[SUB19]], i64* [[IT]], align 8 11602 // CHECK21-NEXT: [[TMP25:%.*]] = load i32, i32* [[CONV]], align 4 11603 // CHECK21-NEXT: [[CONV20:%.*]] = sitofp i32 [[TMP25]] to double 11604 // CHECK21-NEXT: [[ADD21:%.*]] = fadd double [[CONV20]], 1.500000e+00 11605 // CHECK21-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11606 // CHECK21-NEXT: store double [[ADD21]], double* [[A22]], align 8 11607 // CHECK21-NEXT: [[A23:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11608 // CHECK21-NEXT: [[TMP26:%.*]] = load double, double* [[A23]], align 8 11609 // CHECK21-NEXT: [[INC24:%.*]] = fadd double [[TMP26]], 1.000000e+00 11610 // CHECK21-NEXT: store double [[INC24]], double* [[A23]], align 8 11611 // CHECK21-NEXT: [[CONV25:%.*]] = fptosi double [[INC24]] to i16 11612 // CHECK21-NEXT: [[TMP27:%.*]] = mul nsw i64 1, [[TMP2]] 11613 // CHECK21-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP27]] 11614 // CHECK21-NEXT: [[ARRAYIDX27:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX26]], i64 1 11615 // CHECK21-NEXT: store i16 [[CONV25]], i16* [[ARRAYIDX27]], align 2 11616 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE28:%.*]] 11617 // CHECK21: omp.body.continue28: 11618 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC29:%.*]] 11619 // CHECK21: omp.inner.for.inc29: 11620 // CHECK21-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 11621 // CHECK21-NEXT: [[ADD30:%.*]] = add i64 [[TMP28]], 1 11622 // CHECK21-NEXT: store i64 [[ADD30]], i64* [[DOTOMP_IV]], align 8 11623 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND15]], !llvm.loop [[LOOP30:![0-9]+]] 11624 // CHECK21: omp.inner.for.end31: 11625 // CHECK21-NEXT: br label [[OMP_IF_END]] 11626 // CHECK21: omp_if.end: 11627 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11628 // CHECK21: omp.loop.exit: 11629 // CHECK21-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11630 // CHECK21-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 11631 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 11632 // CHECK21-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11633 // CHECK21-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 11634 // CHECK21-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11635 // CHECK21: .omp.final.then: 11636 // CHECK21-NEXT: store i64 400, i64* [[IT]], align 8 11637 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11638 // CHECK21: .omp.final.done: 11639 // CHECK21-NEXT: ret void 11640 // 11641 // 11642 // CHECK21-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 11643 // CHECK21-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11644 // CHECK21-NEXT: entry: 11645 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11646 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11647 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11648 // CHECK21-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 11649 // CHECK21-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 11650 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11651 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11652 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11653 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11654 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11655 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11656 // CHECK21-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 11657 // CHECK21-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 11658 // CHECK21-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 11659 // CHECK21-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 11660 // CHECK21-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 11661 // CHECK21-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 11662 // CHECK21-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 11663 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 11664 // CHECK21-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 11665 // CHECK21-NEXT: ret void 11666 // 11667 // 11668 // CHECK21-LABEL: define {{[^@]+}}@.omp_outlined..6 11669 // CHECK21-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11670 // CHECK21-NEXT: entry: 11671 // CHECK21-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 11672 // CHECK21-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 11673 // CHECK21-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 11674 // CHECK21-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 11675 // CHECK21-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 11676 // CHECK21-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11677 // CHECK21-NEXT: [[TMP:%.*]] = alloca i64, align 8 11678 // CHECK21-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11679 // CHECK21-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11680 // CHECK21-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11681 // CHECK21-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11682 // CHECK21-NEXT: [[I:%.*]] = alloca i64, align 8 11683 // CHECK21-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 11684 // CHECK21-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 11685 // CHECK21-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 11686 // CHECK21-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 11687 // CHECK21-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 11688 // CHECK21-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 11689 // CHECK21-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 11690 // CHECK21-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 11691 // CHECK21-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11692 // CHECK21-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 11693 // CHECK21-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11694 // CHECK21-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11695 // CHECK21-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 11696 // CHECK21-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 11697 // CHECK21-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11698 // CHECK21-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11699 // CHECK21-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 11700 // CHECK21-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11701 // CHECK21: cond.true: 11702 // CHECK21-NEXT: br label [[COND_END:%.*]] 11703 // CHECK21: cond.false: 11704 // CHECK21-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11705 // CHECK21-NEXT: br label [[COND_END]] 11706 // CHECK21: cond.end: 11707 // CHECK21-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 11708 // CHECK21-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11709 // CHECK21-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11710 // CHECK21-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 11711 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11712 // CHECK21: omp.inner.for.cond: 11713 // CHECK21-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32:![0-9]+]] 11714 // CHECK21-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP32]] 11715 // CHECK21-NEXT: [[CMP2:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 11716 // CHECK21-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11717 // CHECK21: omp.inner.for.body: 11718 // CHECK21-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11719 // CHECK21-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 11720 // CHECK21-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 11721 // CHECK21-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP32]] 11722 // CHECK21-NEXT: [[TMP9:%.*]] = load i32, i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP32]] 11723 // CHECK21-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP9]], 1 11724 // CHECK21-NEXT: store i32 [[ADD3]], i32* [[CONV]], align 4, !llvm.access.group [[ACC_GRP32]] 11725 // CHECK21-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP32]] 11726 // CHECK21-NEXT: [[CONV4:%.*]] = sext i16 [[TMP10]] to i32 11727 // CHECK21-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 11728 // CHECK21-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 11729 // CHECK21-NEXT: store i16 [[CONV6]], i16* [[CONV1]], align 2, !llvm.access.group [[ACC_GRP32]] 11730 // CHECK21-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 11731 // CHECK21-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] 11732 // CHECK21-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP11]], 1 11733 // CHECK21-NEXT: store i32 [[ADD7]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP32]] 11734 // CHECK21-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11735 // CHECK21: omp.body.continue: 11736 // CHECK21-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11737 // CHECK21: omp.inner.for.inc: 11738 // CHECK21-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11739 // CHECK21-NEXT: [[ADD8:%.*]] = add nsw i64 [[TMP12]], 1 11740 // CHECK21-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP32]] 11741 // CHECK21-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP33:![0-9]+]] 11742 // CHECK21: omp.inner.for.end: 11743 // CHECK21-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11744 // CHECK21: omp.loop.exit: 11745 // CHECK21-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 11746 // CHECK21-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11747 // CHECK21-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 11748 // CHECK21-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11749 // CHECK21: .omp.final.then: 11750 // CHECK21-NEXT: store i64 11, i64* [[I]], align 8 11751 // CHECK21-NEXT: br label [[DOTOMP_FINAL_DONE]] 11752 // CHECK21: .omp.final.done: 11753 // CHECK21-NEXT: ret void 11754 // 11755 // 11756 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l96 11757 // CHECK23-SAME: () #[[ATTR0:[0-9]+]] { 11758 // CHECK23-NEXT: entry: 11759 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 11760 // CHECK23-NEXT: ret void 11761 // 11762 // 11763 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined. 11764 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 11765 // CHECK23-NEXT: entry: 11766 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11767 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11768 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 11769 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 11770 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 11771 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 11772 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 11773 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11774 // CHECK23-NEXT: [[I:%.*]] = alloca i32, align 4 11775 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11776 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11777 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 11778 // CHECK23-NEXT: store i32 5, i32* [[DOTOMP_UB]], align 4 11779 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 11780 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11781 // CHECK23-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11782 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 11783 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 11784 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11785 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 5 11786 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11787 // CHECK23: cond.true: 11788 // CHECK23-NEXT: br label [[COND_END:%.*]] 11789 // CHECK23: cond.false: 11790 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 11791 // CHECK23-NEXT: br label [[COND_END]] 11792 // CHECK23: cond.end: 11793 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 5, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 11794 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 11795 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 11796 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 11797 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11798 // CHECK23: omp.inner.for.cond: 11799 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12:![0-9]+]] 11800 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP12]] 11801 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 11802 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11803 // CHECK23: omp.inner.for.body: 11804 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11805 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 5 11806 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 3, [[MUL]] 11807 // CHECK23-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !llvm.access.group [[ACC_GRP12]] 11808 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11809 // CHECK23: omp.body.continue: 11810 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11811 // CHECK23: omp.inner.for.inc: 11812 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11813 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP8]], 1 11814 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP12]] 11815 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 11816 // CHECK23: omp.inner.for.end: 11817 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11818 // CHECK23: omp.loop.exit: 11819 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 11820 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11821 // CHECK23-NEXT: [[TMP10:%.*]] = icmp ne i32 [[TMP9]], 0 11822 // CHECK23-NEXT: br i1 [[TMP10]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11823 // CHECK23: .omp.final.then: 11824 // CHECK23-NEXT: store i32 33, i32* [[I]], align 4 11825 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11826 // CHECK23: .omp.final.done: 11827 // CHECK23-NEXT: ret void 11828 // 11829 // 11830 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l108 11831 // CHECK23-SAME: (i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR0]] { 11832 // CHECK23-NEXT: entry: 11833 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11834 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11835 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11836 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11837 // CHECK23-NEXT: [[LIN_CASTED:%.*]] = alloca i32, align 4 11838 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11839 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11840 // CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 11841 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11842 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11843 // CHECK23-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 11844 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11845 // CHECK23-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 11846 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11847 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 11848 // CHECK23-NEXT: store i32 [[TMP2]], i32* [[LIN_CASTED]], align 4 11849 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[LIN_CASTED]], align 4 11850 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[A_ADDR]], align 4 11851 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[A_CASTED]], align 4 11852 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[A_CASTED]], align 4 11853 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]]) 11854 // CHECK23-NEXT: ret void 11855 // 11856 // 11857 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..1 11858 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[LIN:%.*]], i32 noundef [[A:%.*]]) #[[ATTR1]] { 11859 // CHECK23-NEXT: entry: 11860 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11861 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11862 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11863 // CHECK23-NEXT: [[LIN_ADDR:%.*]] = alloca i32, align 4 11864 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11865 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 11866 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 11867 // CHECK23-NEXT: [[DOTLINEAR_START:%.*]] = alloca i32, align 4 11868 // CHECK23-NEXT: [[DOTLINEAR_START1:%.*]] = alloca i32, align 4 11869 // CHECK23-NEXT: [[DOTLINEAR_STEP:%.*]] = alloca i64, align 8 11870 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 11871 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 11872 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 11873 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 11874 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 11875 // CHECK23-NEXT: [[LIN2:%.*]] = alloca i32, align 4 11876 // CHECK23-NEXT: [[A3:%.*]] = alloca i32, align 4 11877 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11878 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11879 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11880 // CHECK23-NEXT: store i32 [[LIN]], i32* [[LIN_ADDR]], align 4 11881 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11882 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11883 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[LIN_ADDR]], align 4 11884 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTLINEAR_START]], align 4 11885 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11886 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[DOTLINEAR_START1]], align 4 11887 // CHECK23-NEXT: [[CALL:%.*]] = call noundef i64 @_Z7get_valv() #[[ATTR5:[0-9]+]] 11888 // CHECK23-NEXT: store i64 [[CALL]], i64* [[DOTLINEAR_STEP]], align 8 11889 // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 11890 // CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 11891 // CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 11892 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 11893 // CHECK23-NEXT: [[TMP2:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11894 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[TMP2]], align 4 11895 // CHECK23-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP3]]) 11896 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 11897 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11898 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP4]], 3 11899 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 11900 // CHECK23: cond.true: 11901 // CHECK23-NEXT: br label [[COND_END:%.*]] 11902 // CHECK23: cond.false: 11903 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 11904 // CHECK23-NEXT: br label [[COND_END]] 11905 // CHECK23: cond.end: 11906 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP5]], [[COND_FALSE]] ] 11907 // CHECK23-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 11908 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 11909 // CHECK23-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_IV]], align 8 11910 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 11911 // CHECK23: omp.inner.for.cond: 11912 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18:![0-9]+]] 11913 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP18]] 11914 // CHECK23-NEXT: [[CMP4:%.*]] = icmp ule i64 [[TMP7]], [[TMP8]] 11915 // CHECK23-NEXT: br i1 [[CMP4]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 11916 // CHECK23: omp.inner.for.body: 11917 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11918 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP9]], 400 11919 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 11920 // CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP18]] 11921 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTLINEAR_START]], align 4, !llvm.access.group [[ACC_GRP18]] 11922 // CHECK23-NEXT: [[CONV5:%.*]] = sext i32 [[TMP10]] to i64 11923 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11924 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 11925 // CHECK23-NEXT: [[MUL6:%.*]] = mul i64 [[TMP11]], [[TMP12]] 11926 // CHECK23-NEXT: [[ADD:%.*]] = add i64 [[CONV5]], [[MUL6]] 11927 // CHECK23-NEXT: [[CONV7:%.*]] = trunc i64 [[ADD]] to i32 11928 // CHECK23-NEXT: store i32 [[CONV7]], i32* [[LIN2]], align 4, !llvm.access.group [[ACC_GRP18]] 11929 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTLINEAR_START1]], align 4, !llvm.access.group [[ACC_GRP18]] 11930 // CHECK23-NEXT: [[CONV8:%.*]] = sext i32 [[TMP13]] to i64 11931 // CHECK23-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11932 // CHECK23-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTLINEAR_STEP]], align 8, !llvm.access.group [[ACC_GRP18]] 11933 // CHECK23-NEXT: [[MUL9:%.*]] = mul i64 [[TMP14]], [[TMP15]] 11934 // CHECK23-NEXT: [[ADD10:%.*]] = add i64 [[CONV8]], [[MUL9]] 11935 // CHECK23-NEXT: [[CONV11:%.*]] = trunc i64 [[ADD10]] to i32 11936 // CHECK23-NEXT: store i32 [[CONV11]], i32* [[A3]], align 4, !llvm.access.group [[ACC_GRP18]] 11937 // CHECK23-NEXT: [[TMP16:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP18]] 11938 // CHECK23-NEXT: [[CONV12:%.*]] = sext i16 [[TMP16]] to i32 11939 // CHECK23-NEXT: [[ADD13:%.*]] = add nsw i32 [[CONV12]], 1 11940 // CHECK23-NEXT: [[CONV14:%.*]] = trunc i32 [[ADD13]] to i16 11941 // CHECK23-NEXT: store i16 [[CONV14]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP18]] 11942 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 11943 // CHECK23: omp.body.continue: 11944 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 11945 // CHECK23: omp.inner.for.inc: 11946 // CHECK23-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11947 // CHECK23-NEXT: [[ADD15:%.*]] = add i64 [[TMP17]], 1 11948 // CHECK23-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP18]] 11949 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP19:![0-9]+]] 11950 // CHECK23: omp.inner.for.end: 11951 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 11952 // CHECK23: omp.loop.exit: 11953 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP3]]) 11954 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11955 // CHECK23-NEXT: [[TMP19:%.*]] = icmp ne i32 [[TMP18]], 0 11956 // CHECK23-NEXT: br i1 [[TMP19]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 11957 // CHECK23: .omp.final.then: 11958 // CHECK23-NEXT: store i64 400, i64* [[IT]], align 8 11959 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 11960 // CHECK23: .omp.final.done: 11961 // CHECK23-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 11962 // CHECK23-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 11963 // CHECK23-NEXT: br i1 [[TMP21]], label [[DOTOMP_LINEAR_PU:%.*]], label [[DOTOMP_LINEAR_PU_DONE:%.*]] 11964 // CHECK23: .omp.linear.pu: 11965 // CHECK23-NEXT: [[TMP22:%.*]] = load i32, i32* [[LIN2]], align 4 11966 // CHECK23-NEXT: store i32 [[TMP22]], i32* [[LIN_ADDR]], align 4 11967 // CHECK23-NEXT: [[TMP23:%.*]] = load i32, i32* [[A3]], align 4 11968 // CHECK23-NEXT: store i32 [[TMP23]], i32* [[A_ADDR]], align 4 11969 // CHECK23-NEXT: br label [[DOTOMP_LINEAR_PU_DONE]] 11970 // CHECK23: .omp.linear.pu.done: 11971 // CHECK23-NEXT: ret void 11972 // 11973 // 11974 // CHECK23-LABEL: define {{[^@]+}}@_Z7get_valv 11975 // CHECK23-SAME: () #[[ATTR3:[0-9]+]] { 11976 // CHECK23-NEXT: entry: 11977 // CHECK23-NEXT: ret i64 0 11978 // 11979 // 11980 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l116 11981 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 11982 // CHECK23-NEXT: entry: 11983 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11984 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11985 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11986 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11987 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11988 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11989 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11990 // CHECK23-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11991 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 11992 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 11993 // CHECK23-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11994 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11995 // CHECK23-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 11996 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11997 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 11998 // CHECK23-NEXT: ret void 11999 // 12000 // 12001 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..2 12002 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 12003 // CHECK23-NEXT: entry: 12004 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12005 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12006 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12007 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12008 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12009 // CHECK23-NEXT: [[TMP:%.*]] = alloca i16, align 2 12010 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12011 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12012 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12013 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12014 // CHECK23-NEXT: [[IT:%.*]] = alloca i16, align 2 12015 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12016 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12017 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12018 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12019 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12020 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12021 // CHECK23-NEXT: store i32 3, i32* [[DOTOMP_UB]], align 4 12022 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12023 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12024 // CHECK23-NEXT: [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12025 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4 12026 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 12027 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12028 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP2]], 3 12029 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12030 // CHECK23: cond.true: 12031 // CHECK23-NEXT: br label [[COND_END:%.*]] 12032 // CHECK23: cond.false: 12033 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12034 // CHECK23-NEXT: br label [[COND_END]] 12035 // CHECK23: cond.end: 12036 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 3, [[COND_TRUE]] ], [ [[TMP3]], [[COND_FALSE]] ] 12037 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12038 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12039 // CHECK23-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_IV]], align 4 12040 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12041 // CHECK23: omp.inner.for.cond: 12042 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21:![0-9]+]] 12043 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP21]] 12044 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP5]], [[TMP6]] 12045 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12046 // CHECK23: omp.inner.for.body: 12047 // CHECK23-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 12048 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP7]], 4 12049 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 6, [[MUL]] 12050 // CHECK23-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 12051 // CHECK23-NEXT: store i16 [[CONV2]], i16* [[IT]], align 2, !llvm.access.group [[ACC_GRP21]] 12052 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 12053 // CHECK23-NEXT: [[ADD3:%.*]] = add nsw i32 [[TMP8]], 1 12054 // CHECK23-NEXT: store i32 [[ADD3]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP21]] 12055 // CHECK23-NEXT: [[TMP9:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP21]] 12056 // CHECK23-NEXT: [[CONV4:%.*]] = sext i16 [[TMP9]] to i32 12057 // CHECK23-NEXT: [[ADD5:%.*]] = add nsw i32 [[CONV4]], 1 12058 // CHECK23-NEXT: [[CONV6:%.*]] = trunc i32 [[ADD5]] to i16 12059 // CHECK23-NEXT: store i16 [[CONV6]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP21]] 12060 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12061 // CHECK23: omp.body.continue: 12062 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12063 // CHECK23: omp.inner.for.inc: 12064 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 12065 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP10]], 1 12066 // CHECK23-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP21]] 12067 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP22:![0-9]+]] 12068 // CHECK23: omp.inner.for.end: 12069 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12070 // CHECK23: omp.loop.exit: 12071 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]]) 12072 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12073 // CHECK23-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 12074 // CHECK23-NEXT: br i1 [[TMP12]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12075 // CHECK23: .omp.final.then: 12076 // CHECK23-NEXT: store i16 22, i16* [[IT]], align 2 12077 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12078 // CHECK23: .omp.final.done: 12079 // CHECK23-NEXT: ret void 12080 // 12081 // 12082 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l140 12083 // CHECK23-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 12084 // CHECK23-NEXT: entry: 12085 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12086 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 12087 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12088 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 12089 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 12090 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12091 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 12092 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 12093 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 12094 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12095 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12096 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 12097 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12098 // CHECK23-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 12099 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12100 // CHECK23-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 12101 // CHECK23-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 12102 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12103 // CHECK23-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 12104 // CHECK23-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 12105 // CHECK23-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 12106 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12107 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 12108 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12109 // CHECK23-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 12110 // CHECK23-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 12111 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12112 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 12113 // CHECK23-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 12114 // CHECK23-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 12115 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 12116 // CHECK23-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 12117 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 12118 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12119 // CHECK23-NEXT: store i32 [[TMP10]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 12120 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 12121 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 10, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]], i32 [[TMP11]]) 12122 // CHECK23-NEXT: ret void 12123 // 12124 // 12125 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..3 12126 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 12127 // CHECK23-NEXT: entry: 12128 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12129 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12130 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12131 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 12132 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12133 // CHECK23-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 12134 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 12135 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12136 // CHECK23-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 12137 // CHECK23-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 12138 // CHECK23-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 12139 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12140 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12141 // CHECK23-NEXT: [[TMP:%.*]] = alloca i8, align 1 12142 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 12143 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 12144 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 12145 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12146 // CHECK23-NEXT: [[IT:%.*]] = alloca i8, align 1 12147 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12148 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12149 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12150 // CHECK23-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 12151 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12152 // CHECK23-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 12153 // CHECK23-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 12154 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12155 // CHECK23-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 12156 // CHECK23-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 12157 // CHECK23-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 12158 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12159 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 12160 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12161 // CHECK23-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 12162 // CHECK23-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 12163 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12164 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 12165 // CHECK23-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 12166 // CHECK23-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 12167 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 12168 // CHECK23-NEXT: store i32 25, i32* [[DOTOMP_UB]], align 4 12169 // CHECK23-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 12170 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12171 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12172 // CHECK23-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12173 // CHECK23-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 12174 // CHECK23-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 [[TMP8]]) 12175 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 12176 // CHECK23: omp.dispatch.cond: 12177 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12178 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 25 12179 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12180 // CHECK23: cond.true: 12181 // CHECK23-NEXT: br label [[COND_END:%.*]] 12182 // CHECK23: cond.false: 12183 // CHECK23-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12184 // CHECK23-NEXT: br label [[COND_END]] 12185 // CHECK23: cond.end: 12186 // CHECK23-NEXT: [[COND:%.*]] = phi i32 [ 25, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 12187 // CHECK23-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 12188 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12189 // CHECK23-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 12190 // CHECK23-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 12191 // CHECK23-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12192 // CHECK23-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 12193 // CHECK23-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 12194 // CHECK23: omp.dispatch.body: 12195 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12196 // CHECK23: omp.inner.for.cond: 12197 // CHECK23-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24:![0-9]+]] 12198 // CHECK23-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group [[ACC_GRP24]] 12199 // CHECK23-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]] 12200 // CHECK23-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12201 // CHECK23: omp.inner.for.body: 12202 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 12203 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1 12204 // CHECK23-NEXT: [[SUB:%.*]] = sub nsw i32 122, [[MUL]] 12205 // CHECK23-NEXT: [[CONV:%.*]] = trunc i32 [[SUB]] to i8 12206 // CHECK23-NEXT: store i8 [[CONV]], i8* [[IT]], align 1, !llvm.access.group [[ACC_GRP24]] 12207 // CHECK23-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 12208 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], 1 12209 // CHECK23-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP24]] 12210 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 12211 // CHECK23-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 12212 // CHECK23-NEXT: [[CONV7:%.*]] = fpext float [[TMP20]] to double 12213 // CHECK23-NEXT: [[ADD8:%.*]] = fadd double [[CONV7]], 1.000000e+00 12214 // CHECK23-NEXT: [[CONV9:%.*]] = fptrunc double [[ADD8]] to float 12215 // CHECK23-NEXT: store float [[CONV9]], float* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP24]] 12216 // CHECK23-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 12217 // CHECK23-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 12218 // CHECK23-NEXT: [[CONV11:%.*]] = fpext float [[TMP21]] to double 12219 // CHECK23-NEXT: [[ADD12:%.*]] = fadd double [[CONV11]], 1.000000e+00 12220 // CHECK23-NEXT: [[CONV13:%.*]] = fptrunc double [[ADD12]] to float 12221 // CHECK23-NEXT: store float [[CONV13]], float* [[ARRAYIDX10]], align 4, !llvm.access.group [[ACC_GRP24]] 12222 // CHECK23-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 12223 // CHECK23-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX14]], i32 0, i32 2 12224 // CHECK23-NEXT: [[TMP22:%.*]] = load double, double* [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 12225 // CHECK23-NEXT: [[ADD16:%.*]] = fadd double [[TMP22]], 1.000000e+00 12226 // CHECK23-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8, !llvm.access.group [[ACC_GRP24]] 12227 // CHECK23-NEXT: [[TMP23:%.*]] = mul nsw i32 1, [[TMP5]] 12228 // CHECK23-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP23]] 12229 // CHECK23-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX17]], i32 3 12230 // CHECK23-NEXT: [[TMP24:%.*]] = load double, double* [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 12231 // CHECK23-NEXT: [[ADD19:%.*]] = fadd double [[TMP24]], 1.000000e+00 12232 // CHECK23-NEXT: store double [[ADD19]], double* [[ARRAYIDX18]], align 8, !llvm.access.group [[ACC_GRP24]] 12233 // CHECK23-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 12234 // CHECK23-NEXT: [[TMP25:%.*]] = load i64, i64* [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 12235 // CHECK23-NEXT: [[ADD20:%.*]] = add nsw i64 [[TMP25]], 1 12236 // CHECK23-NEXT: store i64 [[ADD20]], i64* [[X]], align 4, !llvm.access.group [[ACC_GRP24]] 12237 // CHECK23-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 12238 // CHECK23-NEXT: [[TMP26:%.*]] = load i8, i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 12239 // CHECK23-NEXT: [[CONV21:%.*]] = sext i8 [[TMP26]] to i32 12240 // CHECK23-NEXT: [[ADD22:%.*]] = add nsw i32 [[CONV21]], 1 12241 // CHECK23-NEXT: [[CONV23:%.*]] = trunc i32 [[ADD22]] to i8 12242 // CHECK23-NEXT: store i8 [[CONV23]], i8* [[Y]], align 4, !llvm.access.group [[ACC_GRP24]] 12243 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12244 // CHECK23: omp.body.continue: 12245 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12246 // CHECK23: omp.inner.for.inc: 12247 // CHECK23-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 12248 // CHECK23-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP27]], 1 12249 // CHECK23-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group [[ACC_GRP24]] 12250 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP25:![0-9]+]] 12251 // CHECK23: omp.inner.for.end: 12252 // CHECK23-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 12253 // CHECK23: omp.dispatch.inc: 12254 // CHECK23-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 12255 // CHECK23-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 12256 // CHECK23-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]] 12257 // CHECK23-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_LB]], align 4 12258 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 12259 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 12260 // CHECK23-NEXT: [[ADD26:%.*]] = add nsw i32 [[TMP30]], [[TMP31]] 12261 // CHECK23-NEXT: store i32 [[ADD26]], i32* [[DOTOMP_UB]], align 4 12262 // CHECK23-NEXT: br label [[OMP_DISPATCH_COND]] 12263 // CHECK23: omp.dispatch.end: 12264 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 12265 // CHECK23-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12266 // CHECK23-NEXT: [[TMP33:%.*]] = icmp ne i32 [[TMP32]], 0 12267 // CHECK23-NEXT: br i1 [[TMP33]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12268 // CHECK23: .omp.final.then: 12269 // CHECK23-NEXT: store i8 96, i8* [[IT]], align 1 12270 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12271 // CHECK23: .omp.final.done: 12272 // CHECK23-NEXT: ret void 12273 // 12274 // 12275 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l195 12276 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12277 // CHECK23-NEXT: entry: 12278 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12279 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12280 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 12281 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12282 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12283 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12284 // CHECK23-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 12285 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12286 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12287 // CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 12288 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12289 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12290 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 12291 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12292 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 12293 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 12294 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 12295 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 12296 // CHECK23-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12297 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 12298 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12299 // CHECK23-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 12300 // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 12301 // CHECK23-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 12302 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 12303 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 12304 // CHECK23-NEXT: ret void 12305 // 12306 // 12307 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..4 12308 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 12309 // CHECK23-NEXT: entry: 12310 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12311 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12312 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12313 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12314 // CHECK23-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 12315 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12316 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 12317 // CHECK23-NEXT: [[TMP:%.*]] = alloca i32, align 4 12318 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12319 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12320 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12321 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12322 // CHECK23-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 12323 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12324 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12325 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 12326 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12327 // CHECK23-NEXT: ret void 12328 // 12329 // 12330 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l214 12331 // CHECK23-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] { 12332 // CHECK23-NEXT: entry: 12333 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 12334 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 12335 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12336 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12337 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 12338 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12339 // CHECK23-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 12340 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 12341 // CHECK23-NEXT: [[DOTTHREADID_TEMP_:%.*]] = alloca i32, align 4 12342 // CHECK23-NEXT: [[DOTBOUND_ZERO_ADDR:%.*]] = alloca i32, align 4 12343 // CHECK23-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 12344 // CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 12345 // CHECK23-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 12346 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12347 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12348 // CHECK23-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 12349 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12350 // CHECK23-NEXT: [[TMP1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 12351 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12352 // CHECK23-NEXT: [[TMP3:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12353 // CHECK23-NEXT: [[TMP4:%.*]] = load i16*, i16** [[C_ADDR]], align 4 12354 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 12355 // CHECK23-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_ADDR]], align 4 12356 // CHECK23-NEXT: store i32 [[TMP5]], i32* [[B_CASTED]], align 4 12357 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[B_CASTED]], align 4 12358 // CHECK23-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV]], align 1 12359 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1 12360 // CHECK23-NEXT: [[CONV3:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__CASTED]] to i8* 12361 // CHECK23-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8 12362 // CHECK23-NEXT: store i8 [[FROMBOOL]], i8* [[CONV3]], align 1 12363 // CHECK23-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 12364 // CHECK23-NEXT: [[TMP9:%.*]] = load i8, i8* [[CONV]], align 1 12365 // CHECK23-NEXT: [[TOBOOL4:%.*]] = trunc i8 [[TMP9]] to i1 12366 // CHECK23-NEXT: br i1 [[TOBOOL4]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12367 // CHECK23: omp_if.then: 12368 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 6, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*, i32)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) 12369 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 12370 // CHECK23: omp_if.else: 12371 // CHECK23-NEXT: call void @__kmpc_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 12372 // CHECK23-NEXT: store i32 [[TMP0]], i32* [[DOTTHREADID_TEMP_]], align 4 12373 // CHECK23-NEXT: store i32 0, i32* [[DOTBOUND_ZERO_ADDR]], align 4 12374 // CHECK23-NEXT: call void @.omp_outlined..5(i32* [[DOTTHREADID_TEMP_]], i32* [[DOTBOUND_ZERO_ADDR]], %struct.S1* [[TMP1]], i32 [[TMP6]], i32 [[TMP2]], i32 [[TMP3]], i16* [[TMP4]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]] 12375 // CHECK23-NEXT: call void @__kmpc_end_serialized_parallel(%struct.ident_t* @[[GLOB2]], i32 [[TMP0]]) 12376 // CHECK23-NEXT: br label [[OMP_IF_END]] 12377 // CHECK23: omp_if.end: 12378 // CHECK23-NEXT: ret void 12379 // 12380 // 12381 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..5 12382 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]], i32 noundef [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1]] { 12383 // CHECK23-NEXT: entry: 12384 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12385 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12386 // CHECK23-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 12387 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 12388 // CHECK23-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 12389 // CHECK23-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 12390 // CHECK23-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 12391 // CHECK23-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 12392 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12393 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 12394 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12395 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12396 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12397 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12398 // CHECK23-NEXT: [[IT:%.*]] = alloca i64, align 8 12399 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12400 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12401 // CHECK23-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 12402 // CHECK23-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 12403 // CHECK23-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 12404 // CHECK23-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 12405 // CHECK23-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 12406 // CHECK23-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 12407 // CHECK23-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 12408 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 12409 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 12410 // CHECK23-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 12411 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[DOTCAPTURE_EXPR__ADDR]] to i8* 12412 // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 12413 // CHECK23-NEXT: store i64 3, i64* [[DOTOMP_UB]], align 8 12414 // CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 12415 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12416 // CHECK23-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 1 12417 // CHECK23-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP4]] to i1 12418 // CHECK23-NEXT: br i1 [[TOBOOL]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 12419 // CHECK23: omp_if.then: 12420 // CHECK23-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12421 // CHECK23-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 12422 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 12423 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12424 // CHECK23-NEXT: [[CMP:%.*]] = icmp ugt i64 [[TMP7]], 3 12425 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12426 // CHECK23: cond.true: 12427 // CHECK23-NEXT: br label [[COND_END:%.*]] 12428 // CHECK23: cond.false: 12429 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12430 // CHECK23-NEXT: br label [[COND_END]] 12431 // CHECK23: cond.end: 12432 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 3, [[COND_TRUE]] ], [ [[TMP8]], [[COND_FALSE]] ] 12433 // CHECK23-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 12434 // CHECK23-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 12435 // CHECK23-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_IV]], align 8 12436 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12437 // CHECK23: omp.inner.for.cond: 12438 // CHECK23-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27:![0-9]+]] 12439 // CHECK23-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP27]] 12440 // CHECK23-NEXT: [[CMP3:%.*]] = icmp ule i64 [[TMP10]], [[TMP11]] 12441 // CHECK23-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12442 // CHECK23: omp.inner.for.body: 12443 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 12444 // CHECK23-NEXT: [[MUL:%.*]] = mul i64 [[TMP12]], 400 12445 // CHECK23-NEXT: [[SUB:%.*]] = sub i64 2000, [[MUL]] 12446 // CHECK23-NEXT: store i64 [[SUB]], i64* [[IT]], align 8, !llvm.access.group [[ACC_GRP27]] 12447 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[B_ADDR]], align 4, !llvm.access.group [[ACC_GRP27]] 12448 // CHECK23-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP13]] to double 12449 // CHECK23-NEXT: [[ADD:%.*]] = fadd double [[CONV4]], 1.500000e+00 12450 // CHECK23-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 12451 // CHECK23-NEXT: store double [[ADD]], double* [[A]], align 4, !nontemporal !28, !llvm.access.group [[ACC_GRP27]] 12452 // CHECK23-NEXT: [[A5:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 12453 // CHECK23-NEXT: [[TMP14:%.*]] = load double, double* [[A5]], align 4, !nontemporal !28, !llvm.access.group [[ACC_GRP27]] 12454 // CHECK23-NEXT: [[INC:%.*]] = fadd double [[TMP14]], 1.000000e+00 12455 // CHECK23-NEXT: store double [[INC]], double* [[A5]], align 4, !nontemporal !28, !llvm.access.group [[ACC_GRP27]] 12456 // CHECK23-NEXT: [[CONV6:%.*]] = fptosi double [[INC]] to i16 12457 // CHECK23-NEXT: [[TMP15:%.*]] = mul nsw i32 1, [[TMP2]] 12458 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP15]] 12459 // CHECK23-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 12460 // CHECK23-NEXT: store i16 [[CONV6]], i16* [[ARRAYIDX7]], align 2, !llvm.access.group [[ACC_GRP27]] 12461 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12462 // CHECK23: omp.body.continue: 12463 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12464 // CHECK23: omp.inner.for.inc: 12465 // CHECK23-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 12466 // CHECK23-NEXT: [[ADD8:%.*]] = add i64 [[TMP16]], 1 12467 // CHECK23-NEXT: store i64 [[ADD8]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP27]] 12468 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP29:![0-9]+]] 12469 // CHECK23: omp.inner.for.end: 12470 // CHECK23-NEXT: br label [[OMP_IF_END:%.*]] 12471 // CHECK23: omp_if.else: 12472 // CHECK23-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12473 // CHECK23-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 12474 // CHECK23-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1]], i32 [[TMP18]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 12475 // CHECK23-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12476 // CHECK23-NEXT: [[CMP9:%.*]] = icmp ugt i64 [[TMP19]], 3 12477 // CHECK23-NEXT: br i1 [[CMP9]], label [[COND_TRUE10:%.*]], label [[COND_FALSE11:%.*]] 12478 // CHECK23: cond.true10: 12479 // CHECK23-NEXT: br label [[COND_END12:%.*]] 12480 // CHECK23: cond.false11: 12481 // CHECK23-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12482 // CHECK23-NEXT: br label [[COND_END12]] 12483 // CHECK23: cond.end12: 12484 // CHECK23-NEXT: [[COND13:%.*]] = phi i64 [ 3, [[COND_TRUE10]] ], [ [[TMP20]], [[COND_FALSE11]] ] 12485 // CHECK23-NEXT: store i64 [[COND13]], i64* [[DOTOMP_UB]], align 8 12486 // CHECK23-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 12487 // CHECK23-NEXT: store i64 [[TMP21]], i64* [[DOTOMP_IV]], align 8 12488 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND14:%.*]] 12489 // CHECK23: omp.inner.for.cond14: 12490 // CHECK23-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12491 // CHECK23-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12492 // CHECK23-NEXT: [[CMP15:%.*]] = icmp ule i64 [[TMP22]], [[TMP23]] 12493 // CHECK23-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY16:%.*]], label [[OMP_INNER_FOR_END30:%.*]] 12494 // CHECK23: omp.inner.for.body16: 12495 // CHECK23-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12496 // CHECK23-NEXT: [[MUL17:%.*]] = mul i64 [[TMP24]], 400 12497 // CHECK23-NEXT: [[SUB18:%.*]] = sub i64 2000, [[MUL17]] 12498 // CHECK23-NEXT: store i64 [[SUB18]], i64* [[IT]], align 8 12499 // CHECK23-NEXT: [[TMP25:%.*]] = load i32, i32* [[B_ADDR]], align 4 12500 // CHECK23-NEXT: [[CONV19:%.*]] = sitofp i32 [[TMP25]] to double 12501 // CHECK23-NEXT: [[ADD20:%.*]] = fadd double [[CONV19]], 1.500000e+00 12502 // CHECK23-NEXT: [[A21:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 12503 // CHECK23-NEXT: store double [[ADD20]], double* [[A21]], align 4 12504 // CHECK23-NEXT: [[A22:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 12505 // CHECK23-NEXT: [[TMP26:%.*]] = load double, double* [[A22]], align 4 12506 // CHECK23-NEXT: [[INC23:%.*]] = fadd double [[TMP26]], 1.000000e+00 12507 // CHECK23-NEXT: store double [[INC23]], double* [[A22]], align 4 12508 // CHECK23-NEXT: [[CONV24:%.*]] = fptosi double [[INC23]] to i16 12509 // CHECK23-NEXT: [[TMP27:%.*]] = mul nsw i32 1, [[TMP2]] 12510 // CHECK23-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP27]] 12511 // CHECK23-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX25]], i32 1 12512 // CHECK23-NEXT: store i16 [[CONV24]], i16* [[ARRAYIDX26]], align 2 12513 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE27:%.*]] 12514 // CHECK23: omp.body.continue27: 12515 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC28:%.*]] 12516 // CHECK23: omp.inner.for.inc28: 12517 // CHECK23-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 12518 // CHECK23-NEXT: [[ADD29:%.*]] = add i64 [[TMP28]], 1 12519 // CHECK23-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8 12520 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND14]], !llvm.loop [[LOOP31:![0-9]+]] 12521 // CHECK23: omp.inner.for.end30: 12522 // CHECK23-NEXT: br label [[OMP_IF_END]] 12523 // CHECK23: omp_if.end: 12524 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12525 // CHECK23: omp.loop.exit: 12526 // CHECK23-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12527 // CHECK23-NEXT: [[TMP30:%.*]] = load i32, i32* [[TMP29]], align 4 12528 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP30]]) 12529 // CHECK23-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12530 // CHECK23-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 12531 // CHECK23-NEXT: br i1 [[TMP32]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12532 // CHECK23: .omp.final.then: 12533 // CHECK23-NEXT: store i64 400, i64* [[IT]], align 8 12534 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12535 // CHECK23: .omp.final.done: 12536 // CHECK23-NEXT: ret void 12537 // 12538 // 12539 // CHECK23-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l178 12540 // CHECK23-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 12541 // CHECK23-NEXT: entry: 12542 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12543 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12544 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12545 // CHECK23-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 12546 // CHECK23-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 12547 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12548 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12549 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12550 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12551 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12552 // CHECK23-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 12553 // CHECK23-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 12554 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 12555 // CHECK23-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 12556 // CHECK23-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 12557 // CHECK23-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 12558 // CHECK23-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 12559 // CHECK23-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 12560 // CHECK23-NEXT: ret void 12561 // 12562 // 12563 // CHECK23-LABEL: define {{[^@]+}}@.omp_outlined..6 12564 // CHECK23-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 12565 // CHECK23-NEXT: entry: 12566 // CHECK23-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 12567 // CHECK23-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 12568 // CHECK23-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 12569 // CHECK23-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 12570 // CHECK23-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 12571 // CHECK23-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 12572 // CHECK23-NEXT: [[TMP:%.*]] = alloca i64, align 4 12573 // CHECK23-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 12574 // CHECK23-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 12575 // CHECK23-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 12576 // CHECK23-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 12577 // CHECK23-NEXT: [[I:%.*]] = alloca i64, align 8 12578 // CHECK23-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 12579 // CHECK23-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 12580 // CHECK23-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 12581 // CHECK23-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 12582 // CHECK23-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 12583 // CHECK23-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 12584 // CHECK23-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 12585 // CHECK23-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 12586 // CHECK23-NEXT: store i64 6, i64* [[DOTOMP_UB]], align 8 12587 // CHECK23-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 12588 // CHECK23-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 12589 // CHECK23-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 12590 // CHECK23-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 12591 // CHECK23-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 12592 // CHECK23-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12593 // CHECK23-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP3]], 6 12594 // CHECK23-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 12595 // CHECK23: cond.true: 12596 // CHECK23-NEXT: br label [[COND_END:%.*]] 12597 // CHECK23: cond.false: 12598 // CHECK23-NEXT: [[TMP4:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 12599 // CHECK23-NEXT: br label [[COND_END]] 12600 // CHECK23: cond.end: 12601 // CHECK23-NEXT: [[COND:%.*]] = phi i64 [ 6, [[COND_TRUE]] ], [ [[TMP4]], [[COND_FALSE]] ] 12602 // CHECK23-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 12603 // CHECK23-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 12604 // CHECK23-NEXT: store i64 [[TMP5]], i64* [[DOTOMP_IV]], align 8 12605 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 12606 // CHECK23: omp.inner.for.cond: 12607 // CHECK23-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33:![0-9]+]] 12608 // CHECK23-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group [[ACC_GRP33]] 12609 // CHECK23-NEXT: [[CMP1:%.*]] = icmp sle i64 [[TMP6]], [[TMP7]] 12610 // CHECK23-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 12611 // CHECK23: omp.inner.for.body: 12612 // CHECK23-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12613 // CHECK23-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP8]], 3 12614 // CHECK23-NEXT: [[ADD:%.*]] = add nsw i64 -10, [[MUL]] 12615 // CHECK23-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !llvm.access.group [[ACC_GRP33]] 12616 // CHECK23-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 12617 // CHECK23-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP9]], 1 12618 // CHECK23-NEXT: store i32 [[ADD2]], i32* [[A_ADDR]], align 4, !llvm.access.group [[ACC_GRP33]] 12619 // CHECK23-NEXT: [[TMP10:%.*]] = load i16, i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP33]] 12620 // CHECK23-NEXT: [[CONV3:%.*]] = sext i16 [[TMP10]] to i32 12621 // CHECK23-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 12622 // CHECK23-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 12623 // CHECK23-NEXT: store i16 [[CONV5]], i16* [[CONV]], align 2, !llvm.access.group [[ACC_GRP33]] 12624 // CHECK23-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 12625 // CHECK23-NEXT: [[TMP11:%.*]] = load i32, i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] 12626 // CHECK23-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP11]], 1 12627 // CHECK23-NEXT: store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4, !llvm.access.group [[ACC_GRP33]] 12628 // CHECK23-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 12629 // CHECK23: omp.body.continue: 12630 // CHECK23-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 12631 // CHECK23: omp.inner.for.inc: 12632 // CHECK23-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12633 // CHECK23-NEXT: [[ADD7:%.*]] = add nsw i64 [[TMP12]], 1 12634 // CHECK23-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group [[ACC_GRP33]] 12635 // CHECK23-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP34:![0-9]+]] 12636 // CHECK23: omp.inner.for.end: 12637 // CHECK23-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 12638 // CHECK23: omp.loop.exit: 12639 // CHECK23-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]]) 12640 // CHECK23-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IS_LAST]], align 4 12641 // CHECK23-NEXT: [[TMP14:%.*]] = icmp ne i32 [[TMP13]], 0 12642 // CHECK23-NEXT: br i1 [[TMP14]], label [[DOTOMP_FINAL_THEN:%.*]], label [[DOTOMP_FINAL_DONE:%.*]] 12643 // CHECK23: .omp.final.then: 12644 // CHECK23-NEXT: store i64 11, i64* [[I]], align 8 12645 // CHECK23-NEXT: br label [[DOTOMP_FINAL_DONE]] 12646 // CHECK23: .omp.final.done: 12647 // CHECK23-NEXT: ret void 12648 // 12649