1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-function-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -fopenmp-cuda-mode -emit-llvm-bc %s -o %t-ppc-host.bc 3 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -fopenmp-cuda-mode -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -debug-info-kind=limited | FileCheck %s 4 // expected-no-diagnostics 5 6 int main() { 7 /* int(*b)[a]; */ 8 /* int *(**c)[a]; */ 9 bool bb; 10 int a; 11 int b[10][10]; 12 int c[10][10][10]; 13 #pragma omp target parallel for firstprivate(a, b) map(tofrom \ 14 : c) map(tofrom \ 15 : bb) if (a) 16 for (int i = 0; i < 10; ++i) { 17 int &f = c[1][1][1]; 18 int &g = a; 19 int &h = b[1][1]; 20 int d = 15; 21 a = 5; 22 b[0][a] = 10; 23 c[0][0][a] = 11; 24 b[0][a] = c[0][0][a]; 25 bb |= b[0][a]; 26 } 27 #pragma omp target parallel for firstprivate(a) map(tofrom \ 28 : c, b) map(to \ 29 : bb) 30 for (int i = 0; i < 10; ++i) { 31 int &f = c[1][1][1]; 32 int &g = a; 33 int &h = b[1][1]; 34 int d = 15; 35 a = 5; 36 b[0][a] = 10; 37 c[0][0][a] = 11; 38 b[0][a] = c[0][0][a]; 39 d = bb; 40 } 41 #pragma omp target parallel for map(tofrom \ 42 : a, c, b) map(from \ 43 : bb) 44 for (int i = 0; i < 10; ++i) { 45 int &f = c[1][1][1]; 46 int &g = a; 47 int &h = b[1][1]; 48 int d = 15; 49 a = 5; 50 b[0][a] = 10; 51 c[0][0][a] = 11; 52 b[0][a] = c[0][0][a]; 53 bb = b[0][a]; 54 } 55 return 0; 56 } 57 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__ 58 // CHECK-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]], i1 zeroext [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG12:![0-9]+]] { 59 // CHECK-NEXT: entry: 60 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 61 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 62 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 63 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8 addrspace(1)*, align 8 64 // CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i8, align 1 65 // CHECK-NEXT: [[TMP:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 66 // CHECK-NEXT: [[_TMP1:%.*]] = alloca [10 x [10 x i32]]*, align 8 67 // CHECK-NEXT: [[_TMP2:%.*]] = alloca i8*, align 8 68 // CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 69 // CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8 70 // CHECK-NEXT: store [10 x [10 x [10 x i32]]] addrspace(1)* [[C]], [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8 71 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], metadata [[META29:![0-9]+]], metadata !DIExpression()), !dbg [[DBG30:![0-9]+]] 72 // CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 73 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META31:![0-9]+]], metadata !DIExpression()), !dbg [[DBG32:![0-9]+]] 74 // CHECK-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 75 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META33:![0-9]+]], metadata !DIExpression()), !dbg [[DBG34:![0-9]+]] 76 // CHECK-NEXT: store i8 addrspace(1)* [[BB]], i8 addrspace(1)** [[BB_ADDR]], align 8 77 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8 addrspace(1)** [[BB_ADDR]], metadata [[META35:![0-9]+]], metadata !DIExpression()), !dbg [[DBG36:![0-9]+]] 78 // CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[DOTCAPTURE_EXPR_]] to i8 79 // CHECK-NEXT: store i8 [[FROMBOOL]], i8* [[DOTCAPTURE_EXPR__ADDR]], align 1 80 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8* [[DOTCAPTURE_EXPR__ADDR]], metadata [[META37:![0-9]+]], metadata !DIExpression()), !dbg [[DBG38:![0-9]+]] 81 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]] addrspace(1)*, [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8, !dbg [[DBG39:![0-9]+]] 82 // CHECK-NEXT: [[TMP1:%.*]] = addrspacecast [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP0]] to [10 x [10 x [10 x i32]]]*, !dbg [[DBG39]] 83 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP1]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG39]] 84 // CHECK-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG39]] 85 // CHECK-NEXT: [[TMP3:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG39]] 86 // CHECK-NEXT: store [10 x [10 x i32]]* [[TMP3]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG39]] 87 // CHECK-NEXT: [[TMP4:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG39]] 88 // CHECK-NEXT: [[TMP5:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG39]] 89 // CHECK-NEXT: [[TMP6:%.*]] = addrspacecast i8 addrspace(1)* [[TMP5]] to i8*, !dbg [[DBG39]] 90 // CHECK-NEXT: store i8* [[TMP6]], i8** [[_TMP2]], align 8, !dbg [[DBG39]] 91 // CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[_TMP2]], align 8, !dbg [[DBG39]] 92 // CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !dbg [[DBG39]] 93 // CHECK-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 0), !dbg [[DBG39]] 94 // CHECK-NEXT: br label [[DOTEXECUTE:%.*]], !dbg [[DBG39]] 95 // CHECK: .execute: 96 // CHECK-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB4:[0-9]+]]) 97 // CHECK-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG40:![0-9]+]] 98 // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*, !dbg [[DBG40]] 99 // CHECK-NEXT: store i32 [[TMP9]], i32* [[CONV]], align 4, !dbg [[DBG40]] 100 // CHECK-NEXT: [[TMP10:%.*]] = load i64, i64* [[A_CASTED]], align 8, !dbg [[DBG40]] 101 // CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG40]] 102 // CHECK-NEXT: [[TMP12:%.*]] = bitcast [10 x [10 x [10 x i32]]]* [[TMP2]] to i8*, !dbg [[DBG40]] 103 // CHECK-NEXT: store i8* [[TMP12]], i8** [[TMP11]], align 8, !dbg [[DBG40]] 104 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG40]] 105 // CHECK-NEXT: [[TMP14:%.*]] = inttoptr i64 [[TMP10]] to i8*, !dbg [[DBG40]] 106 // CHECK-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8, !dbg [[DBG40]] 107 // CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG40]] 108 // CHECK-NEXT: [[TMP16:%.*]] = bitcast [10 x [10 x i32]]* [[TMP4]] to i8*, !dbg [[DBG40]] 109 // CHECK-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8, !dbg [[DBG40]] 110 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG40]] 111 // CHECK-NEXT: store i8* [[TMP7]], i8** [[TMP17]], align 8, !dbg [[DBG40]] 112 // CHECK-NEXT: [[TMP18:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR__ADDR]], align 1, !dbg [[DBG41:![0-9]+]] 113 // CHECK-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP18]] to i1, !dbg [[DBG41]] 114 // CHECK-NEXT: [[TMP19:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG40]] 115 // CHECK-NEXT: [[TMP20:%.*]] = bitcast [4 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG40]] 116 // CHECK-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB4]], i32 [[TMP8]], i32 [[TMP19]], i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, [10 x [10 x [10 x i32]]]*, i64, [10 x [10 x i32]]*, i8*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP20]], i64 4), !dbg [[DBG40]] 117 // CHECK-NEXT: br label [[DOTOMP_DEINIT:%.*]], !dbg [[DBG43:![0-9]+]] 118 // CHECK: .omp.deinit: 119 // CHECK-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 0), !dbg [[DBG43]] 120 // CHECK-NEXT: br label [[DOTEXIT:%.*]], !dbg [[DBG43]] 121 // CHECK: .exit: 122 // CHECK-NEXT: ret void, !dbg [[DBG44:![0-9]+]] 123 // 124 // 125 // CHECK-LABEL: define {{[^@]+}}@__omp_outlined___debug__ 126 // CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG45:![0-9]+]] { 127 // CHECK-NEXT: entry: 128 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 129 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 130 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 131 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 132 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 133 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8 addrspace(1)*, align 8 134 // CHECK-NEXT: [[TMP:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 135 // CHECK-NEXT: [[_TMP1:%.*]] = alloca [10 x [10 x i32]]*, align 8 136 // CHECK-NEXT: [[_TMP2:%.*]] = alloca i8*, align 8 137 // CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 138 // CHECK-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 139 // CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 140 // CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 141 // CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 142 // CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 143 // CHECK-NEXT: [[B4:%.*]] = alloca [10 x [10 x i32]], align 4 144 // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 145 // CHECK-NEXT: [[F:%.*]] = alloca i32*, align 8 146 // CHECK-NEXT: [[G:%.*]] = alloca i32*, align 8 147 // CHECK-NEXT: [[H:%.*]] = alloca i32*, align 8 148 // CHECK-NEXT: [[D:%.*]] = alloca i32, align 4 149 // CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 150 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META52:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53:![0-9]+]] 151 // CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 152 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META54:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53]] 153 // CHECK-NEXT: store [10 x [10 x [10 x i32]]] addrspace(1)* [[C]], [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8 154 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], metadata [[META55:![0-9]+]], metadata !DIExpression()), !dbg [[DBG56:![0-9]+]] 155 // CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 156 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META57:![0-9]+]], metadata !DIExpression()), !dbg [[DBG58:![0-9]+]] 157 // CHECK-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 158 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META59:![0-9]+]], metadata !DIExpression()), !dbg [[DBG60:![0-9]+]] 159 // CHECK-NEXT: store i8 addrspace(1)* [[BB]], i8 addrspace(1)** [[BB_ADDR]], align 8 160 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8 addrspace(1)** [[BB_ADDR]], metadata [[META61:![0-9]+]], metadata !DIExpression()), !dbg [[DBG62:![0-9]+]] 161 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]] addrspace(1)*, [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8, !dbg [[DBG63:![0-9]+]] 162 // CHECK-NEXT: [[TMP1:%.*]] = addrspacecast [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP0]] to [10 x [10 x [10 x i32]]]*, !dbg [[DBG63]] 163 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP1]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG63]] 164 // CHECK-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG63]] 165 // CHECK-NEXT: [[TMP3:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG63]] 166 // CHECK-NEXT: store [10 x [10 x i32]]* [[TMP3]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG63]] 167 // CHECK-NEXT: [[TMP4:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG63]] 168 // CHECK-NEXT: [[TMP5:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG63]] 169 // CHECK-NEXT: [[TMP6:%.*]] = addrspacecast i8 addrspace(1)* [[TMP5]] to i8*, !dbg [[DBG63]] 170 // CHECK-NEXT: store i8* [[TMP6]], i8** [[_TMP2]], align 8, !dbg [[DBG63]] 171 // CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[_TMP2]], align 8, !dbg [[DBG63]] 172 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IV]], metadata [[META64:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53]] 173 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_LB]], metadata [[META65:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53]] 174 // CHECK-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG66:![0-9]+]] 175 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_UB]], metadata [[META67:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53]] 176 // CHECK-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG66]] 177 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_STRIDE]], metadata [[META68:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53]] 178 // CHECK-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG66]] 179 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IS_LAST]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53]] 180 // CHECK-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG66]] 181 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]* [[B4]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53]] 182 // CHECK-NEXT: [[TMP8:%.*]] = bitcast [10 x [10 x i32]]* [[B4]] to i8*, !dbg [[DBG63]] 183 // CHECK-NEXT: [[TMP9:%.*]] = bitcast [10 x [10 x i32]]* [[TMP4]] to i8*, !dbg [[DBG63]] 184 // CHECK-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP8]], i8* align 4 [[TMP9]], i64 400, i1 false), !dbg [[DBG63]] 185 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[I]], metadata [[META71:![0-9]+]], metadata !DIExpression()), !dbg [[DBG53]] 186 // CHECK-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG63]] 187 // CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4, !dbg [[DBG63]] 188 // CHECK-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP11]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG72:![0-9]+]] 189 // CHECK-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG63]] 190 // CHECK: omp.dispatch.cond: 191 // CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG66]] 192 // CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP12]], 9, !dbg [[DBG66]] 193 // CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG66]] 194 // CHECK: cond.true: 195 // CHECK-NEXT: br label [[COND_END:%.*]], !dbg [[DBG66]] 196 // CHECK: cond.false: 197 // CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG66]] 198 // CHECK-NEXT: br label [[COND_END]], !dbg [[DBG66]] 199 // CHECK: cond.end: 200 // CHECK-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ], !dbg [[DBG66]] 201 // CHECK-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG66]] 202 // CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG66]] 203 // CHECK-NEXT: store i32 [[TMP14]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG66]] 204 // CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG66]] 205 // CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG66]] 206 // CHECK-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP15]], [[TMP16]], !dbg [[DBG63]] 207 // CHECK-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG63]] 208 // CHECK: omp.dispatch.body: 209 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG63]] 210 // CHECK: omp.inner.for.cond: 211 // CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG66]] 212 // CHECK-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG66]] 213 // CHECK-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG63]] 214 // CHECK-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG63]] 215 // CHECK: omp.inner.for.body: 216 // CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG66]] 217 // CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP19]], 1, !dbg [[DBG73:![0-9]+]] 218 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG73]] 219 // CHECK-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG73]] 220 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[F]], metadata [[META74:![0-9]+]], metadata !DIExpression()), !dbg [[DBG77:![0-9]+]] 221 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 1, !dbg [[DBG78:![0-9]+]] 222 // CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG78]] 223 // CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG78]] 224 // CHECK-NEXT: store i32* [[ARRAYIDX8]], i32** [[F]], align 8, !dbg [[DBG77]] 225 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[G]], metadata [[META79:![0-9]+]], metadata !DIExpression()), !dbg [[DBG80:![0-9]+]] 226 // CHECK-NEXT: store i32* [[A_ADDR]], i32** [[G]], align 8, !dbg [[DBG80]] 227 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[H]], metadata [[META81:![0-9]+]], metadata !DIExpression()), !dbg [[DBG82:![0-9]+]] 228 // CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[B4]], i64 0, i64 1, !dbg [[DBG83:![0-9]+]] 229 // CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG83]] 230 // CHECK-NEXT: store i32* [[ARRAYIDX10]], i32** [[H]], align 8, !dbg [[DBG82]] 231 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[D]], metadata [[META84:![0-9]+]], metadata !DIExpression()), !dbg [[DBG85:![0-9]+]] 232 // CHECK-NEXT: store i32 15, i32* [[D]], align 4, !dbg [[DBG85]] 233 // CHECK-NEXT: store i32 5, i32* [[A_ADDR]], align 4, !dbg [[DBG86:![0-9]+]] 234 // CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[B4]], i64 0, i64 0, !dbg [[DBG87:![0-9]+]] 235 // CHECK-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG88:![0-9]+]] 236 // CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG87]] 237 // CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG87]] 238 // CHECK-NEXT: store i32 10, i32* [[ARRAYIDX12]], align 4, !dbg [[DBG89:![0-9]+]] 239 // CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG90:![0-9]+]] 240 // CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG90]] 241 // CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG91:![0-9]+]] 242 // CHECK-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG90]] 243 // CHECK-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG90]] 244 // CHECK-NEXT: store i32 11, i32* [[ARRAYIDX16]], align 4, !dbg [[DBG92:![0-9]+]] 245 // CHECK-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG93:![0-9]+]] 246 // CHECK-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG93]] 247 // CHECK-NEXT: [[TMP22:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG94:![0-9]+]] 248 // CHECK-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG93]] 249 // CHECK-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG93]] 250 // CHECK-NEXT: [[TMP23:%.*]] = load i32, i32* [[ARRAYIDX20]], align 4, !dbg [[DBG93]] 251 // CHECK-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[B4]], i64 0, i64 0, !dbg [[DBG95:![0-9]+]] 252 // CHECK-NEXT: [[TMP24:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG96:![0-9]+]] 253 // CHECK-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG95]] 254 // CHECK-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG95]] 255 // CHECK-NEXT: store i32 [[TMP23]], i32* [[ARRAYIDX23]], align 4, !dbg [[DBG97:![0-9]+]] 256 // CHECK-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[B4]], i64 0, i64 0, !dbg [[DBG98:![0-9]+]] 257 // CHECK-NEXT: [[TMP25:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG99:![0-9]+]] 258 // CHECK-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP25]] to i64, !dbg [[DBG98]] 259 // CHECK-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG98]] 260 // CHECK-NEXT: [[TMP26:%.*]] = load i32, i32* [[ARRAYIDX26]], align 4, !dbg [[DBG98]] 261 // CHECK-NEXT: [[TMP27:%.*]] = load i8, i8* [[TMP7]], align 1, !dbg [[DBG100:![0-9]+]] 262 // CHECK-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP27]] to i1, !dbg [[DBG100]] 263 // CHECK-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG100]] 264 // CHECK-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP26]], !dbg [[DBG100]] 265 // CHECK-NEXT: [[TOBOOL27:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG100]] 266 // CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL27]] to i8, !dbg [[DBG100]] 267 // CHECK-NEXT: store i8 [[FROMBOOL]], i8* [[TMP7]], align 1, !dbg [[DBG100]] 268 // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG101:![0-9]+]] 269 // CHECK: omp.body.continue: 270 // CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG72]] 271 // CHECK: omp.inner.for.inc: 272 // CHECK-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG66]] 273 // CHECK-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP28]], 1, !dbg [[DBG63]] 274 // CHECK-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG63]] 275 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG72]], !llvm.loop [[LOOP102:![0-9]+]] 276 // CHECK: omp.inner.for.end: 277 // CHECK-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG72]] 278 // CHECK: omp.dispatch.inc: 279 // CHECK-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG66]] 280 // CHECK-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG66]] 281 // CHECK-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP29]], [[TMP30]], !dbg [[DBG63]] 282 // CHECK-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG63]] 283 // CHECK-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG66]] 284 // CHECK-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG66]] 285 // CHECK-NEXT: [[ADD30:%.*]] = add nsw i32 [[TMP31]], [[TMP32]], !dbg [[DBG63]] 286 // CHECK-NEXT: store i32 [[ADD30]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG63]] 287 // CHECK-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG72]], !llvm.loop [[LOOP104:![0-9]+]] 288 // CHECK: omp.dispatch.end: 289 // CHECK-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP11]]), !dbg [[DBG103:![0-9]+]] 290 // CHECK-NEXT: ret void, !dbg [[DBG105:![0-9]+]] 291 // 292 // 293 // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__ 294 // CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG106:![0-9]+]] { 295 // CHECK-NEXT: entry: 296 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 297 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 298 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 299 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 300 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 301 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8*, align 8 302 // CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 303 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META113:![0-9]+]], metadata !DIExpression()), !dbg [[DBG114:![0-9]+]] 304 // CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 305 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META115:![0-9]+]], metadata !DIExpression()), !dbg [[DBG114]] 306 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[C]], [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8 307 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]]** [[C_ADDR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG114]] 308 // CHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 309 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i64* [[A_ADDR]], metadata [[META117:![0-9]+]], metadata !DIExpression()), !dbg [[DBG114]] 310 // CHECK-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 311 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG114]] 312 // CHECK-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 313 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META119:![0-9]+]], metadata !DIExpression()), !dbg [[DBG114]] 314 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG120:![0-9]+]] 315 // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG120]] 316 // CHECK-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG120]] 317 // CHECK-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG120]] 318 // CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG120]] 319 // CHECK-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG120]] 320 // CHECK-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG120]] 321 // CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG120]] 322 // CHECK-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG120]] 323 // CHECK-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG120]] 324 // CHECK-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG120]] 325 // CHECK-NEXT: [[TMP10:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG120]] 326 // CHECK-NEXT: call void @__omp_outlined___debug__(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]]* [[TMP7]], i8 addrspace(1)* [[TMP10]]) #[[ATTR4:[0-9]+]], !dbg [[DBG120]] 327 // CHECK-NEXT: ret void, !dbg [[DBG120]] 328 // 329 // 330 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13 331 // CHECK-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR0]] !dbg [[DBG121:![0-9]+]] { 332 // CHECK-NEXT: entry: 333 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 334 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 335 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 336 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8*, align 8 337 // CHECK-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 338 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[C]], [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8 339 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]]** [[C_ADDR]], metadata [[META124:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125:![0-9]+]] 340 // CHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 341 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i64* [[A_ADDR]], metadata [[META126:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] 342 // CHECK-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 343 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META127:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] 344 // CHECK-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 345 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META128:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] 346 // CHECK-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 347 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i64* [[DOTCAPTURE_EXPR__ADDR]], metadata [[META129:![0-9]+]], metadata !DIExpression()), !dbg [[DBG125]] 348 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG130:![0-9]+]] 349 // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG130]] 350 // CHECK-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG130]] 351 // CHECK-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG130]] 352 // CHECK-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*, !dbg [[DBG130]] 353 // CHECK-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG130]] 354 // CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG130]] 355 // CHECK-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG130]] 356 // CHECK-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG130]] 357 // CHECK-NEXT: [[TMP7:%.*]] = load i8, i8* [[CONV1]], align 8, !dbg [[DBG130]] 358 // CHECK-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP7]] to i1, !dbg [[DBG130]] 359 // CHECK-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG130]] 360 // CHECK-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG130]] 361 // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l13_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP8]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP5]], i8 addrspace(1)* [[TMP9]], i1 [[TOBOOL]]) #[[ATTR4]], !dbg [[DBG130]] 362 // CHECK-NEXT: ret void, !dbg [[DBG130]] 363 // 364 // 365 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__ 366 // CHECK-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG131:![0-9]+]] { 367 // CHECK-NEXT: entry: 368 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 369 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 370 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]] addrspace(1)*, align 8 371 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8 addrspace(1)*, align 8 372 // CHECK-NEXT: [[TMP:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 373 // CHECK-NEXT: [[_TMP1:%.*]] = alloca [10 x [10 x i32]]*, align 8 374 // CHECK-NEXT: [[_TMP2:%.*]] = alloca i8*, align 8 375 // CHECK-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 376 // CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8 377 // CHECK-NEXT: store [10 x [10 x [10 x i32]]] addrspace(1)* [[C]], [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8 378 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], metadata [[META136:![0-9]+]], metadata !DIExpression()), !dbg [[DBG137:![0-9]+]] 379 // CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 380 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META138:![0-9]+]], metadata !DIExpression()), !dbg [[DBG139:![0-9]+]] 381 // CHECK-NEXT: store [10 x [10 x i32]] addrspace(1)* [[B]], [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8 382 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG141:![0-9]+]] 383 // CHECK-NEXT: store i8 addrspace(1)* [[BB]], i8 addrspace(1)** [[BB_ADDR]], align 8 384 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8 addrspace(1)** [[BB_ADDR]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG143:![0-9]+]] 385 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]] addrspace(1)*, [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8, !dbg [[DBG144:![0-9]+]] 386 // CHECK-NEXT: [[TMP1:%.*]] = addrspacecast [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP0]] to [10 x [10 x [10 x i32]]]*, !dbg [[DBG144]] 387 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP1]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG144]] 388 // CHECK-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG144]] 389 // CHECK-NEXT: [[TMP3:%.*]] = load [10 x [10 x i32]] addrspace(1)*, [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG144]] 390 // CHECK-NEXT: [[TMP4:%.*]] = addrspacecast [10 x [10 x i32]] addrspace(1)* [[TMP3]] to [10 x [10 x i32]]*, !dbg [[DBG144]] 391 // CHECK-NEXT: store [10 x [10 x i32]]* [[TMP4]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG144]] 392 // CHECK-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG144]] 393 // CHECK-NEXT: [[TMP6:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG144]] 394 // CHECK-NEXT: [[TMP7:%.*]] = addrspacecast i8 addrspace(1)* [[TMP6]] to i8*, !dbg [[DBG144]] 395 // CHECK-NEXT: store i8* [[TMP7]], i8** [[_TMP2]], align 8, !dbg [[DBG144]] 396 // CHECK-NEXT: [[TMP8:%.*]] = load i8*, i8** [[_TMP2]], align 8, !dbg [[DBG144]] 397 // CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !dbg [[DBG144]] 398 // CHECK-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 0), !dbg [[DBG144]] 399 // CHECK-NEXT: br label [[DOTEXECUTE:%.*]], !dbg [[DBG144]] 400 // CHECK: .execute: 401 // CHECK-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB9:[0-9]+]]) 402 // CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG145:![0-9]+]] 403 // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*, !dbg [[DBG145]] 404 // CHECK-NEXT: store i32 [[TMP10]], i32* [[CONV]], align 4, !dbg [[DBG145]] 405 // CHECK-NEXT: [[TMP11:%.*]] = load i64, i64* [[A_CASTED]], align 8, !dbg [[DBG145]] 406 // CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG145]] 407 // CHECK-NEXT: [[TMP13:%.*]] = bitcast [10 x [10 x [10 x i32]]]* [[TMP2]] to i8*, !dbg [[DBG145]] 408 // CHECK-NEXT: store i8* [[TMP13]], i8** [[TMP12]], align 8, !dbg [[DBG145]] 409 // CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG145]] 410 // CHECK-NEXT: [[TMP15:%.*]] = inttoptr i64 [[TMP11]] to i8*, !dbg [[DBG145]] 411 // CHECK-NEXT: store i8* [[TMP15]], i8** [[TMP14]], align 8, !dbg [[DBG145]] 412 // CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG145]] 413 // CHECK-NEXT: [[TMP17:%.*]] = bitcast [10 x [10 x i32]]* [[TMP5]] to i8*, !dbg [[DBG145]] 414 // CHECK-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG145]] 415 // CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG145]] 416 // CHECK-NEXT: store i8* [[TMP8]], i8** [[TMP18]], align 8, !dbg [[DBG145]] 417 // CHECK-NEXT: [[TMP19:%.*]] = bitcast [4 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG145]] 418 // CHECK-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB9]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, [10 x [10 x [10 x i32]]]*, i64, [10 x [10 x i32]]*, i8*)* @__omp_outlined__2 to i8*), i8* null, i8** [[TMP19]], i64 4), !dbg [[DBG145]] 419 // CHECK-NEXT: br label [[DOTOMP_DEINIT:%.*]], !dbg [[DBG146:![0-9]+]] 420 // CHECK: .omp.deinit: 421 // CHECK-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 0), !dbg [[DBG146]] 422 // CHECK-NEXT: br label [[DOTEXIT:%.*]], !dbg [[DBG146]] 423 // CHECK: .exit: 424 // CHECK-NEXT: ret void, !dbg [[DBG148:![0-9]+]] 425 // 426 // 427 // CHECK-LABEL: define {{[^@]+}}@__omp_outlined___debug__1 428 // CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG149:![0-9]+]] { 429 // CHECK-NEXT: entry: 430 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 431 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 432 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 433 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 434 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]] addrspace(1)*, align 8 435 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8 addrspace(1)*, align 8 436 // CHECK-NEXT: [[TMP:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 437 // CHECK-NEXT: [[_TMP1:%.*]] = alloca [10 x [10 x i32]]*, align 8 438 // CHECK-NEXT: [[_TMP2:%.*]] = alloca i8*, align 8 439 // CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 440 // CHECK-NEXT: [[_TMP3:%.*]] = alloca i32, align 4 441 // CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 442 // CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 443 // CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 444 // CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 445 // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 446 // CHECK-NEXT: [[F:%.*]] = alloca i32*, align 8 447 // CHECK-NEXT: [[G:%.*]] = alloca i32*, align 8 448 // CHECK-NEXT: [[H:%.*]] = alloca i32*, align 8 449 // CHECK-NEXT: [[D:%.*]] = alloca i32, align 4 450 // CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 451 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META152:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153:![0-9]+]] 452 // CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 453 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META154:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153]] 454 // CHECK-NEXT: store [10 x [10 x [10 x i32]]] addrspace(1)* [[C]], [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8 455 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], metadata [[META155:![0-9]+]], metadata !DIExpression()), !dbg [[DBG156:![0-9]+]] 456 // CHECK-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 457 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META157:![0-9]+]], metadata !DIExpression()), !dbg [[DBG158:![0-9]+]] 458 // CHECK-NEXT: store [10 x [10 x i32]] addrspace(1)* [[B]], [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8 459 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], metadata [[META159:![0-9]+]], metadata !DIExpression()), !dbg [[DBG160:![0-9]+]] 460 // CHECK-NEXT: store i8 addrspace(1)* [[BB]], i8 addrspace(1)** [[BB_ADDR]], align 8 461 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8 addrspace(1)** [[BB_ADDR]], metadata [[META161:![0-9]+]], metadata !DIExpression()), !dbg [[DBG162:![0-9]+]] 462 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]] addrspace(1)*, [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8, !dbg [[DBG163:![0-9]+]] 463 // CHECK-NEXT: [[TMP1:%.*]] = addrspacecast [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP0]] to [10 x [10 x [10 x i32]]]*, !dbg [[DBG163]] 464 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP1]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG163]] 465 // CHECK-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG163]] 466 // CHECK-NEXT: [[TMP3:%.*]] = load [10 x [10 x i32]] addrspace(1)*, [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG163]] 467 // CHECK-NEXT: [[TMP4:%.*]] = addrspacecast [10 x [10 x i32]] addrspace(1)* [[TMP3]] to [10 x [10 x i32]]*, !dbg [[DBG163]] 468 // CHECK-NEXT: store [10 x [10 x i32]]* [[TMP4]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG163]] 469 // CHECK-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG163]] 470 // CHECK-NEXT: [[TMP6:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG163]] 471 // CHECK-NEXT: [[TMP7:%.*]] = addrspacecast i8 addrspace(1)* [[TMP6]] to i8*, !dbg [[DBG163]] 472 // CHECK-NEXT: store i8* [[TMP7]], i8** [[_TMP2]], align 8, !dbg [[DBG163]] 473 // CHECK-NEXT: [[TMP8:%.*]] = load i8*, i8** [[_TMP2]], align 8, !dbg [[DBG163]] 474 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IV]], metadata [[META164:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153]] 475 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_LB]], metadata [[META165:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153]] 476 // CHECK-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG166:![0-9]+]] 477 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_UB]], metadata [[META167:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153]] 478 // CHECK-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG166]] 479 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_STRIDE]], metadata [[META168:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153]] 480 // CHECK-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG166]] 481 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IS_LAST]], metadata [[META169:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153]] 482 // CHECK-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG166]] 483 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[I]], metadata [[META170:![0-9]+]], metadata !DIExpression()), !dbg [[DBG153]] 484 // CHECK-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG163]] 485 // CHECK-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4, !dbg [[DBG163]] 486 // CHECK-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG171:![0-9]+]] 487 // CHECK-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG163]] 488 // CHECK: omp.dispatch.cond: 489 // CHECK-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG166]] 490 // CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 9, !dbg [[DBG166]] 491 // CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG166]] 492 // CHECK: cond.true: 493 // CHECK-NEXT: br label [[COND_END:%.*]], !dbg [[DBG166]] 494 // CHECK: cond.false: 495 // CHECK-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG166]] 496 // CHECK-NEXT: br label [[COND_END]], !dbg [[DBG166]] 497 // CHECK: cond.end: 498 // CHECK-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG166]] 499 // CHECK-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG166]] 500 // CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG166]] 501 // CHECK-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG166]] 502 // CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG166]] 503 // CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG166]] 504 // CHECK-NEXT: [[CMP4:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG163]] 505 // CHECK-NEXT: br i1 [[CMP4]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG163]] 506 // CHECK: omp.dispatch.body: 507 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG163]] 508 // CHECK: omp.inner.for.cond: 509 // CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG166]] 510 // CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG166]] 511 // CHECK-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP16]], [[TMP17]], !dbg [[DBG163]] 512 // CHECK-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG163]] 513 // CHECK: omp.inner.for.body: 514 // CHECK-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG166]] 515 // CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP18]], 1, !dbg [[DBG172:![0-9]+]] 516 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG172]] 517 // CHECK-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG172]] 518 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[F]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG175:![0-9]+]] 519 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 1, !dbg [[DBG176:![0-9]+]] 520 // CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG176]] 521 // CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX6]], i64 0, i64 1, !dbg [[DBG176]] 522 // CHECK-NEXT: store i32* [[ARRAYIDX7]], i32** [[F]], align 8, !dbg [[DBG175]] 523 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[G]], metadata [[META177:![0-9]+]], metadata !DIExpression()), !dbg [[DBG178:![0-9]+]] 524 // CHECK-NEXT: store i32* [[A_ADDR]], i32** [[G]], align 8, !dbg [[DBG178]] 525 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[H]], metadata [[META179:![0-9]+]], metadata !DIExpression()), !dbg [[DBG180:![0-9]+]] 526 // CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP5]], i64 0, i64 1, !dbg [[DBG181:![0-9]+]] 527 // CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX8]], i64 0, i64 1, !dbg [[DBG181]] 528 // CHECK-NEXT: store i32* [[ARRAYIDX9]], i32** [[H]], align 8, !dbg [[DBG180]] 529 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[D]], metadata [[META182:![0-9]+]], metadata !DIExpression()), !dbg [[DBG183:![0-9]+]] 530 // CHECK-NEXT: store i32 15, i32* [[D]], align 4, !dbg [[DBG183]] 531 // CHECK-NEXT: store i32 5, i32* [[A_ADDR]], align 4, !dbg [[DBG184:![0-9]+]] 532 // CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP5]], i64 0, i64 0, !dbg [[DBG185:![0-9]+]] 533 // CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG186:![0-9]+]] 534 // CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG185]] 535 // CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX10]], i64 0, i64 [[IDXPROM]], !dbg [[DBG185]] 536 // CHECK-NEXT: store i32 10, i32* [[ARRAYIDX11]], align 4, !dbg [[DBG187:![0-9]+]] 537 // CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG188:![0-9]+]] 538 // CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX12]], i64 0, i64 0, !dbg [[DBG188]] 539 // CHECK-NEXT: [[TMP20:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG189:![0-9]+]] 540 // CHECK-NEXT: [[IDXPROM14:%.*]] = sext i32 [[TMP20]] to i64, !dbg [[DBG188]] 541 // CHECK-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX13]], i64 0, i64 [[IDXPROM14]], !dbg [[DBG188]] 542 // CHECK-NEXT: store i32 11, i32* [[ARRAYIDX15]], align 4, !dbg [[DBG190:![0-9]+]] 543 // CHECK-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG191:![0-9]+]] 544 // CHECK-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX16]], i64 0, i64 0, !dbg [[DBG191]] 545 // CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG192:![0-9]+]] 546 // CHECK-NEXT: [[IDXPROM18:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG191]] 547 // CHECK-NEXT: [[ARRAYIDX19:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX17]], i64 0, i64 [[IDXPROM18]], !dbg [[DBG191]] 548 // CHECK-NEXT: [[TMP22:%.*]] = load i32, i32* [[ARRAYIDX19]], align 4, !dbg [[DBG191]] 549 // CHECK-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP5]], i64 0, i64 0, !dbg [[DBG193:![0-9]+]] 550 // CHECK-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG194:![0-9]+]] 551 // CHECK-NEXT: [[IDXPROM21:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG193]] 552 // CHECK-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX20]], i64 0, i64 [[IDXPROM21]], !dbg [[DBG193]] 553 // CHECK-NEXT: store i32 [[TMP22]], i32* [[ARRAYIDX22]], align 4, !dbg [[DBG195:![0-9]+]] 554 // CHECK-NEXT: [[TMP24:%.*]] = load i8, i8* [[TMP8]], align 1, !dbg [[DBG196:![0-9]+]] 555 // CHECK-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP24]] to i1, !dbg [[DBG196]] 556 // CHECK-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG196]] 557 // CHECK-NEXT: store i32 [[CONV]], i32* [[D]], align 4, !dbg [[DBG197:![0-9]+]] 558 // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG198:![0-9]+]] 559 // CHECK: omp.body.continue: 560 // CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG171]] 561 // CHECK: omp.inner.for.inc: 562 // CHECK-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG166]] 563 // CHECK-NEXT: [[ADD23:%.*]] = add nsw i32 [[TMP25]], 1, !dbg [[DBG163]] 564 // CHECK-NEXT: store i32 [[ADD23]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG163]] 565 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG171]], !llvm.loop [[LOOP199:![0-9]+]] 566 // CHECK: omp.inner.for.end: 567 // CHECK-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG171]] 568 // CHECK: omp.dispatch.inc: 569 // CHECK-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG166]] 570 // CHECK-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG166]] 571 // CHECK-NEXT: [[ADD24:%.*]] = add nsw i32 [[TMP26]], [[TMP27]], !dbg [[DBG163]] 572 // CHECK-NEXT: store i32 [[ADD24]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG163]] 573 // CHECK-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG166]] 574 // CHECK-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG166]] 575 // CHECK-NEXT: [[ADD25:%.*]] = add nsw i32 [[TMP28]], [[TMP29]], !dbg [[DBG163]] 576 // CHECK-NEXT: store i32 [[ADD25]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG163]] 577 // CHECK-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG171]], !llvm.loop [[LOOP201:![0-9]+]] 578 // CHECK: omp.dispatch.end: 579 // CHECK-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB8:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG200:![0-9]+]] 580 // CHECK-NEXT: ret void, !dbg [[DBG202:![0-9]+]] 581 // 582 // 583 // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__2 584 // CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG203:![0-9]+]] { 585 // CHECK-NEXT: entry: 586 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 587 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 588 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 589 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 590 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 591 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8*, align 8 592 // CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 593 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META204:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205:![0-9]+]] 594 // CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 595 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META206:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205]] 596 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[C]], [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8 597 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]]** [[C_ADDR]], metadata [[META207:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205]] 598 // CHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 599 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i64* [[A_ADDR]], metadata [[META208:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205]] 600 // CHECK-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 601 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205]] 602 // CHECK-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 603 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META210:![0-9]+]], metadata !DIExpression()), !dbg [[DBG205]] 604 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG211:![0-9]+]] 605 // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG211]] 606 // CHECK-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG211]] 607 // CHECK-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG211]] 608 // CHECK-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG211]] 609 // CHECK-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG211]] 610 // CHECK-NEXT: [[TMP5:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG211]] 611 // CHECK-NEXT: [[TMP6:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG211]] 612 // CHECK-NEXT: [[TMP7:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG211]] 613 // CHECK-NEXT: [[TMP8:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG211]] 614 // CHECK-NEXT: [[TMP9:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP5]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG211]] 615 // CHECK-NEXT: [[TMP10:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP7]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG211]] 616 // CHECK-NEXT: [[TMP11:%.*]] = addrspacecast i8* [[TMP8]] to i8 addrspace(1)*, !dbg [[DBG211]] 617 // CHECK-NEXT: call void @__omp_outlined___debug__1(i32* [[TMP3]], i32* [[TMP4]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP9]], i32 [[TMP6]], [10 x [10 x i32]] addrspace(1)* [[TMP10]], i8 addrspace(1)* [[TMP11]]) #[[ATTR4]], !dbg [[DBG211]] 618 // CHECK-NEXT: ret void, !dbg [[DBG211]] 619 // 620 // 621 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27 622 // CHECK-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG212:![0-9]+]] { 623 // CHECK-NEXT: entry: 624 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 625 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 626 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 627 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8*, align 8 628 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[C]], [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8 629 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]]** [[C_ADDR]], metadata [[META215:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216:![0-9]+]] 630 // CHECK-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 631 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i64* [[A_ADDR]], metadata [[META217:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] 632 // CHECK-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 633 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META218:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] 634 // CHECK-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 635 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META219:![0-9]+]], metadata !DIExpression()), !dbg [[DBG216]] 636 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG220:![0-9]+]] 637 // CHECK-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG220]] 638 // CHECK-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG220]] 639 // CHECK-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG220]] 640 // CHECK-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG220]] 641 // CHECK-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG220]] 642 // CHECK-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG220]] 643 // CHECK-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG220]] 644 // CHECK-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG220]] 645 // CHECK-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP5]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG220]] 646 // CHECK-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG220]] 647 // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l27_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP7]], i32 [[TMP4]], [10 x [10 x i32]] addrspace(1)* [[TMP8]], i8 addrspace(1)* [[TMP9]]) #[[ATTR4]], !dbg [[DBG220]] 648 // CHECK-NEXT: ret void, !dbg [[DBG220]] 649 // 650 // 651 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__ 652 // CHECK-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG221:![0-9]+]] { 653 // CHECK-NEXT: entry: 654 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 655 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32 addrspace(1)*, align 8 656 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]] addrspace(1)*, align 8 657 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8 addrspace(1)*, align 8 658 // CHECK-NEXT: [[TMP:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 659 // CHECK-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 660 // CHECK-NEXT: [[_TMP2:%.*]] = alloca [10 x [10 x i32]]*, align 8 661 // CHECK-NEXT: [[_TMP3:%.*]] = alloca i8*, align 8 662 // CHECK-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [4 x i8*], align 8 663 // CHECK-NEXT: store [10 x [10 x [10 x i32]]] addrspace(1)* [[C]], [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8 664 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], metadata [[META226:![0-9]+]], metadata !DIExpression()), !dbg [[DBG227:![0-9]+]] 665 // CHECK-NEXT: store i32 addrspace(1)* [[A]], i32 addrspace(1)** [[A_ADDR]], align 8 666 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32 addrspace(1)** [[A_ADDR]], metadata [[META228:![0-9]+]], metadata !DIExpression()), !dbg [[DBG229:![0-9]+]] 667 // CHECK-NEXT: store [10 x [10 x i32]] addrspace(1)* [[B]], [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8 668 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], metadata [[META230:![0-9]+]], metadata !DIExpression()), !dbg [[DBG231:![0-9]+]] 669 // CHECK-NEXT: store i8 addrspace(1)* [[BB]], i8 addrspace(1)** [[BB_ADDR]], align 8 670 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8 addrspace(1)** [[BB_ADDR]], metadata [[META232:![0-9]+]], metadata !DIExpression()), !dbg [[DBG233:![0-9]+]] 671 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]] addrspace(1)*, [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8, !dbg [[DBG234:![0-9]+]] 672 // CHECK-NEXT: [[TMP1:%.*]] = addrspacecast [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP0]] to [10 x [10 x [10 x i32]]]*, !dbg [[DBG234]] 673 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP1]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG234]] 674 // CHECK-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG234]] 675 // CHECK-NEXT: [[TMP3:%.*]] = load i32 addrspace(1)*, i32 addrspace(1)** [[A_ADDR]], align 8, !dbg [[DBG234]] 676 // CHECK-NEXT: [[TMP4:%.*]] = addrspacecast i32 addrspace(1)* [[TMP3]] to i32*, !dbg [[DBG234]] 677 // CHECK-NEXT: store i32* [[TMP4]], i32** [[_TMP1]], align 8, !dbg [[DBG234]] 678 // CHECK-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP1]], align 8, !dbg [[DBG234]] 679 // CHECK-NEXT: [[TMP6:%.*]] = load [10 x [10 x i32]] addrspace(1)*, [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG234]] 680 // CHECK-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x i32]] addrspace(1)* [[TMP6]] to [10 x [10 x i32]]*, !dbg [[DBG234]] 681 // CHECK-NEXT: store [10 x [10 x i32]]* [[TMP7]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG234]] 682 // CHECK-NEXT: [[TMP8:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG234]] 683 // CHECK-NEXT: [[TMP9:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG234]] 684 // CHECK-NEXT: [[TMP10:%.*]] = addrspacecast i8 addrspace(1)* [[TMP9]] to i8*, !dbg [[DBG234]] 685 // CHECK-NEXT: store i8* [[TMP10]], i8** [[_TMP3]], align 8, !dbg [[DBG234]] 686 // CHECK-NEXT: [[TMP11:%.*]] = load i8*, i8** [[_TMP3]], align 8, !dbg [[DBG234]] 687 // CHECK-NEXT: [[NVPTX_NUM_THREADS:%.*]] = call i32 @llvm.nvvm.read.ptx.sreg.ntid.x(), !dbg [[DBG234]] 688 // CHECK-NEXT: call void @__kmpc_spmd_kernel_init(i32 [[NVPTX_NUM_THREADS]], i16 0), !dbg [[DBG234]] 689 // CHECK-NEXT: br label [[DOTEXECUTE:%.*]], !dbg [[DBG234]] 690 // CHECK: .execute: 691 // CHECK-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB14:[0-9]+]]) 692 // CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG235:![0-9]+]] 693 // CHECK-NEXT: [[TMP14:%.*]] = bitcast [10 x [10 x [10 x i32]]]* [[TMP2]] to i8*, !dbg [[DBG235]] 694 // CHECK-NEXT: store i8* [[TMP14]], i8** [[TMP13]], align 8, !dbg [[DBG235]] 695 // CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 1, !dbg [[DBG235]] 696 // CHECK-NEXT: [[TMP16:%.*]] = bitcast i32* [[TMP5]] to i8*, !dbg [[DBG235]] 697 // CHECK-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8, !dbg [[DBG235]] 698 // CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 2, !dbg [[DBG235]] 699 // CHECK-NEXT: [[TMP18:%.*]] = bitcast [10 x [10 x i32]]* [[TMP8]] to i8*, !dbg [[DBG235]] 700 // CHECK-NEXT: store i8* [[TMP18]], i8** [[TMP17]], align 8, !dbg [[DBG235]] 701 // CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 3, !dbg [[DBG235]] 702 // CHECK-NEXT: store i8* [[TMP11]], i8** [[TMP19]], align 8, !dbg [[DBG235]] 703 // CHECK-NEXT: [[TMP20:%.*]] = bitcast [4 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG235]] 704 // CHECK-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB14]], i32 [[TMP12]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, [10 x [10 x [10 x i32]]]*, i32*, [10 x [10 x i32]]*, i8*)* @__omp_outlined__4 to i8*), i8* null, i8** [[TMP20]], i64 4), !dbg [[DBG235]] 705 // CHECK-NEXT: br label [[DOTOMP_DEINIT:%.*]], !dbg [[DBG236:![0-9]+]] 706 // CHECK: .omp.deinit: 707 // CHECK-NEXT: call void @__kmpc_spmd_kernel_deinit_v2(i16 0), !dbg [[DBG236]] 708 // CHECK-NEXT: br label [[DOTEXIT:%.*]], !dbg [[DBG236]] 709 // CHECK: .exit: 710 // CHECK-NEXT: ret void, !dbg [[DBG238:![0-9]+]] 711 // 712 // 713 // CHECK-LABEL: define {{[^@]+}}@__omp_outlined___debug__3 714 // CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG239:![0-9]+]] { 715 // CHECK-NEXT: entry: 716 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 717 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 718 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 719 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32 addrspace(1)*, align 8 720 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]] addrspace(1)*, align 8 721 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8 addrspace(1)*, align 8 722 // CHECK-NEXT: [[TMP:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 723 // CHECK-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 724 // CHECK-NEXT: [[_TMP2:%.*]] = alloca [10 x [10 x i32]]*, align 8 725 // CHECK-NEXT: [[_TMP3:%.*]] = alloca i8*, align 8 726 // CHECK-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 727 // CHECK-NEXT: [[_TMP4:%.*]] = alloca i32, align 4 728 // CHECK-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 729 // CHECK-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 730 // CHECK-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 731 // CHECK-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 732 // CHECK-NEXT: [[I:%.*]] = alloca i32, align 4 733 // CHECK-NEXT: [[F:%.*]] = alloca i32*, align 8 734 // CHECK-NEXT: [[G:%.*]] = alloca i32*, align 8 735 // CHECK-NEXT: [[H:%.*]] = alloca i32*, align 8 736 // CHECK-NEXT: [[D:%.*]] = alloca i32, align 4 737 // CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 738 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META242:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243:![0-9]+]] 739 // CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 740 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META244:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243]] 741 // CHECK-NEXT: store [10 x [10 x [10 x i32]]] addrspace(1)* [[C]], [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8 742 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], metadata [[META245:![0-9]+]], metadata !DIExpression()), !dbg [[DBG246:![0-9]+]] 743 // CHECK-NEXT: store i32 addrspace(1)* [[A]], i32 addrspace(1)** [[A_ADDR]], align 8 744 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32 addrspace(1)** [[A_ADDR]], metadata [[META247:![0-9]+]], metadata !DIExpression()), !dbg [[DBG248:![0-9]+]] 745 // CHECK-NEXT: store [10 x [10 x i32]] addrspace(1)* [[B]], [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8 746 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], metadata [[META249:![0-9]+]], metadata !DIExpression()), !dbg [[DBG250:![0-9]+]] 747 // CHECK-NEXT: store i8 addrspace(1)* [[BB]], i8 addrspace(1)** [[BB_ADDR]], align 8 748 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8 addrspace(1)** [[BB_ADDR]], metadata [[META251:![0-9]+]], metadata !DIExpression()), !dbg [[DBG252:![0-9]+]] 749 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]] addrspace(1)*, [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8, !dbg [[DBG253:![0-9]+]] 750 // CHECK-NEXT: [[TMP1:%.*]] = addrspacecast [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP0]] to [10 x [10 x [10 x i32]]]*, !dbg [[DBG253]] 751 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP1]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG253]] 752 // CHECK-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG253]] 753 // CHECK-NEXT: [[TMP3:%.*]] = load i32 addrspace(1)*, i32 addrspace(1)** [[A_ADDR]], align 8, !dbg [[DBG253]] 754 // CHECK-NEXT: [[TMP4:%.*]] = addrspacecast i32 addrspace(1)* [[TMP3]] to i32*, !dbg [[DBG253]] 755 // CHECK-NEXT: store i32* [[TMP4]], i32** [[_TMP1]], align 8, !dbg [[DBG253]] 756 // CHECK-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP1]], align 8, !dbg [[DBG253]] 757 // CHECK-NEXT: [[TMP6:%.*]] = load [10 x [10 x i32]] addrspace(1)*, [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG253]] 758 // CHECK-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x i32]] addrspace(1)* [[TMP6]] to [10 x [10 x i32]]*, !dbg [[DBG253]] 759 // CHECK-NEXT: store [10 x [10 x i32]]* [[TMP7]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG253]] 760 // CHECK-NEXT: [[TMP8:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG253]] 761 // CHECK-NEXT: [[TMP9:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG253]] 762 // CHECK-NEXT: [[TMP10:%.*]] = addrspacecast i8 addrspace(1)* [[TMP9]] to i8*, !dbg [[DBG253]] 763 // CHECK-NEXT: store i8* [[TMP10]], i8** [[_TMP3]], align 8, !dbg [[DBG253]] 764 // CHECK-NEXT: [[TMP11:%.*]] = load i8*, i8** [[_TMP3]], align 8, !dbg [[DBG253]] 765 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IV]], metadata [[META254:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243]] 766 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_LB]], metadata [[META255:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243]] 767 // CHECK-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG256:![0-9]+]] 768 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_UB]], metadata [[META257:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243]] 769 // CHECK-NEXT: store i32 9, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG256]] 770 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_STRIDE]], metadata [[META258:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243]] 771 // CHECK-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG256]] 772 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[DOTOMP_IS_LAST]], metadata [[META259:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243]] 773 // CHECK-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG256]] 774 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[I]], metadata [[META260:![0-9]+]], metadata !DIExpression()), !dbg [[DBG243]] 775 // CHECK-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG253]] 776 // CHECK-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4, !dbg [[DBG253]] 777 // CHECK-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB11:[0-9]+]], i32 [[TMP13]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG261:![0-9]+]] 778 // CHECK-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG253]] 779 // CHECK: omp.dispatch.cond: 780 // CHECK-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG256]] 781 // CHECK-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP14]], 9, !dbg [[DBG256]] 782 // CHECK-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG256]] 783 // CHECK: cond.true: 784 // CHECK-NEXT: br label [[COND_END:%.*]], !dbg [[DBG256]] 785 // CHECK: cond.false: 786 // CHECK-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG256]] 787 // CHECK-NEXT: br label [[COND_END]], !dbg [[DBG256]] 788 // CHECK: cond.end: 789 // CHECK-NEXT: [[COND:%.*]] = phi i32 [ 9, [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ], !dbg [[DBG256]] 790 // CHECK-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG256]] 791 // CHECK-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG256]] 792 // CHECK-NEXT: store i32 [[TMP16]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG256]] 793 // CHECK-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG256]] 794 // CHECK-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG256]] 795 // CHECK-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP17]], [[TMP18]], !dbg [[DBG253]] 796 // CHECK-NEXT: br i1 [[CMP5]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG253]] 797 // CHECK: omp.dispatch.body: 798 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG253]] 799 // CHECK: omp.inner.for.cond: 800 // CHECK-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG256]] 801 // CHECK-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG256]] 802 // CHECK-NEXT: [[CMP6:%.*]] = icmp sle i32 [[TMP19]], [[TMP20]], !dbg [[DBG253]] 803 // CHECK-NEXT: br i1 [[CMP6]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG253]] 804 // CHECK: omp.inner.for.body: 805 // CHECK-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG256]] 806 // CHECK-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP21]], 1, !dbg [[DBG262:![0-9]+]] 807 // CHECK-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]], !dbg [[DBG262]] 808 // CHECK-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG262]] 809 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[F]], metadata [[META263:![0-9]+]], metadata !DIExpression()), !dbg [[DBG265:![0-9]+]] 810 // CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 1, !dbg [[DBG266:![0-9]+]] 811 // CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG266]] 812 // CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX7]], i64 0, i64 1, !dbg [[DBG266]] 813 // CHECK-NEXT: store i32* [[ARRAYIDX8]], i32** [[F]], align 8, !dbg [[DBG265]] 814 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[G]], metadata [[META267:![0-9]+]], metadata !DIExpression()), !dbg [[DBG268:![0-9]+]] 815 // CHECK-NEXT: store i32* [[TMP5]], i32** [[G]], align 8, !dbg [[DBG268]] 816 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[H]], metadata [[META269:![0-9]+]], metadata !DIExpression()), !dbg [[DBG270:![0-9]+]] 817 // CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP8]], i64 0, i64 1, !dbg [[DBG271:![0-9]+]] 818 // CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX9]], i64 0, i64 1, !dbg [[DBG271]] 819 // CHECK-NEXT: store i32* [[ARRAYIDX10]], i32** [[H]], align 8, !dbg [[DBG270]] 820 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32* [[D]], metadata [[META272:![0-9]+]], metadata !DIExpression()), !dbg [[DBG273:![0-9]+]] 821 // CHECK-NEXT: store i32 15, i32* [[D]], align 4, !dbg [[DBG273]] 822 // CHECK-NEXT: store i32 5, i32* [[TMP5]], align 4, !dbg [[DBG274:![0-9]+]] 823 // CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP8]], i64 0, i64 0, !dbg [[DBG275:![0-9]+]] 824 // CHECK-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG276:![0-9]+]] 825 // CHECK-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG275]] 826 // CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX11]], i64 0, i64 [[IDXPROM]], !dbg [[DBG275]] 827 // CHECK-NEXT: store i32 10, i32* [[ARRAYIDX12]], align 4, !dbg [[DBG277:![0-9]+]] 828 // CHECK-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG278:![0-9]+]] 829 // CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX13]], i64 0, i64 0, !dbg [[DBG278]] 830 // CHECK-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG279:![0-9]+]] 831 // CHECK-NEXT: [[IDXPROM15:%.*]] = sext i32 [[TMP23]] to i64, !dbg [[DBG278]] 832 // CHECK-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX14]], i64 0, i64 [[IDXPROM15]], !dbg [[DBG278]] 833 // CHECK-NEXT: store i32 11, i32* [[ARRAYIDX16]], align 4, !dbg [[DBG280:![0-9]+]] 834 // CHECK-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG281:![0-9]+]] 835 // CHECK-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX17]], i64 0, i64 0, !dbg [[DBG281]] 836 // CHECK-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG282:![0-9]+]] 837 // CHECK-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG281]] 838 // CHECK-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG281]] 839 // CHECK-NEXT: [[TMP25:%.*]] = load i32, i32* [[ARRAYIDX20]], align 4, !dbg [[DBG281]] 840 // CHECK-NEXT: [[ARRAYIDX21:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP8]], i64 0, i64 0, !dbg [[DBG283:![0-9]+]] 841 // CHECK-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG284:![0-9]+]] 842 // CHECK-NEXT: [[IDXPROM22:%.*]] = sext i32 [[TMP26]] to i64, !dbg [[DBG283]] 843 // CHECK-NEXT: [[ARRAYIDX23:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX21]], i64 0, i64 [[IDXPROM22]], !dbg [[DBG283]] 844 // CHECK-NEXT: store i32 [[TMP25]], i32* [[ARRAYIDX23]], align 4, !dbg [[DBG285:![0-9]+]] 845 // CHECK-NEXT: [[ARRAYIDX24:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP8]], i64 0, i64 0, !dbg [[DBG286:![0-9]+]] 846 // CHECK-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG287:![0-9]+]] 847 // CHECK-NEXT: [[IDXPROM25:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG286]] 848 // CHECK-NEXT: [[ARRAYIDX26:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX24]], i64 0, i64 [[IDXPROM25]], !dbg [[DBG286]] 849 // CHECK-NEXT: [[TMP28:%.*]] = load i32, i32* [[ARRAYIDX26]], align 4, !dbg [[DBG286]] 850 // CHECK-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP28]], 0, !dbg [[DBG286]] 851 // CHECK-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG288:![0-9]+]] 852 // CHECK-NEXT: store i8 [[FROMBOOL]], i8* [[TMP11]], align 1, !dbg [[DBG288]] 853 // CHECK-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG289:![0-9]+]] 854 // CHECK: omp.body.continue: 855 // CHECK-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG261]] 856 // CHECK: omp.inner.for.inc: 857 // CHECK-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG256]] 858 // CHECK-NEXT: [[ADD27:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG253]] 859 // CHECK-NEXT: store i32 [[ADD27]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG253]] 860 // CHECK-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG261]], !llvm.loop [[LOOP290:![0-9]+]] 861 // CHECK: omp.inner.for.end: 862 // CHECK-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG261]] 863 // CHECK: omp.dispatch.inc: 864 // CHECK-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG256]] 865 // CHECK-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG256]] 866 // CHECK-NEXT: [[ADD28:%.*]] = add nsw i32 [[TMP30]], [[TMP31]], !dbg [[DBG253]] 867 // CHECK-NEXT: store i32 [[ADD28]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG253]] 868 // CHECK-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG256]] 869 // CHECK-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG256]] 870 // CHECK-NEXT: [[ADD29:%.*]] = add nsw i32 [[TMP32]], [[TMP33]], !dbg [[DBG253]] 871 // CHECK-NEXT: store i32 [[ADD29]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG253]] 872 // CHECK-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG261]], !llvm.loop [[LOOP292:![0-9]+]] 873 // CHECK: omp.dispatch.end: 874 // CHECK-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB13:[0-9]+]], i32 [[TMP13]]), !dbg [[DBG291:![0-9]+]] 875 // CHECK-NEXT: ret void, !dbg [[DBG293:![0-9]+]] 876 // 877 // 878 // CHECK-LABEL: define {{[^@]+}}@__omp_outlined__4 879 // CHECK-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG294:![0-9]+]] { 880 // CHECK-NEXT: entry: 881 // CHECK-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 882 // CHECK-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 883 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 884 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 885 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 886 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8*, align 8 887 // CHECK-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 888 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META297:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298:![0-9]+]] 889 // CHECK-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 890 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META299:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298]] 891 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[C]], [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8 892 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]]** [[C_ADDR]], metadata [[META300:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298]] 893 // CHECK-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 894 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META301:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298]] 895 // CHECK-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 896 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META302:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298]] 897 // CHECK-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 898 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META303:![0-9]+]], metadata !DIExpression()), !dbg [[DBG298]] 899 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG304:![0-9]+]] 900 // CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8, !dbg [[DBG304]] 901 // CHECK-NEXT: [[TMP2:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG304]] 902 // CHECK-NEXT: [[TMP3:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG304]] 903 // CHECK-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG304]] 904 // CHECK-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTBOUND_TID__ADDR]], align 8, !dbg [[DBG304]] 905 // CHECK-NEXT: [[TMP6:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG304]] 906 // CHECK-NEXT: [[TMP7:%.*]] = load i32*, i32** [[A_ADDR]], align 8, !dbg [[DBG304]] 907 // CHECK-NEXT: [[TMP8:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG304]] 908 // CHECK-NEXT: [[TMP9:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG304]] 909 // CHECK-NEXT: [[TMP10:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP6]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG304]] 910 // CHECK-NEXT: [[TMP11:%.*]] = addrspacecast i32* [[TMP7]] to i32 addrspace(1)*, !dbg [[DBG304]] 911 // CHECK-NEXT: [[TMP12:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP8]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG304]] 912 // CHECK-NEXT: [[TMP13:%.*]] = addrspacecast i8* [[TMP9]] to i8 addrspace(1)*, !dbg [[DBG304]] 913 // CHECK-NEXT: call void @__omp_outlined___debug__3(i32* [[TMP4]], i32* [[TMP5]], [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP10]], i32 addrspace(1)* [[TMP11]], [10 x [10 x i32]] addrspace(1)* [[TMP12]], i8 addrspace(1)* [[TMP13]]) #[[ATTR4]], !dbg [[DBG304]] 914 // CHECK-NEXT: ret void, !dbg [[DBG304]] 915 // 916 // 917 // CHECK-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41 918 // CHECK-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG305:![0-9]+]] { 919 // CHECK-NEXT: entry: 920 // CHECK-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 921 // CHECK-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 922 // CHECK-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 923 // CHECK-NEXT: [[BB_ADDR:%.*]] = alloca i8*, align 8 924 // CHECK-NEXT: store [10 x [10 x [10 x i32]]]* [[C]], [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8 925 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]]** [[C_ADDR]], metadata [[META308:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309:![0-9]+]] 926 // CHECK-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 927 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META310:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] 928 // CHECK-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 929 // CHECK-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META311:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] 930 // CHECK-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 931 // CHECK-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META312:![0-9]+]], metadata !DIExpression()), !dbg [[DBG309]] 932 // CHECK-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG313:![0-9]+]] 933 // CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8, !dbg [[DBG313]] 934 // CHECK-NEXT: [[TMP2:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG313]] 935 // CHECK-NEXT: [[TMP3:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG313]] 936 // CHECK-NEXT: [[TMP4:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG313]] 937 // CHECK-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A_ADDR]], align 8, !dbg [[DBG313]] 938 // CHECK-NEXT: [[TMP6:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG313]] 939 // CHECK-NEXT: [[TMP7:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG313]] 940 // CHECK-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP4]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG313]] 941 // CHECK-NEXT: [[TMP9:%.*]] = addrspacecast i32* [[TMP5]] to i32 addrspace(1)*, !dbg [[DBG313]] 942 // CHECK-NEXT: [[TMP10:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP6]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG313]] 943 // CHECK-NEXT: [[TMP11:%.*]] = addrspacecast i8* [[TMP7]] to i8 addrspace(1)*, !dbg [[DBG313]] 944 // CHECK-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l41_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP8]], i32 addrspace(1)* [[TMP9]], [10 x [10 x i32]] addrspace(1)* [[TMP10]], i8 addrspace(1)* [[TMP11]]) #[[ATTR4]], !dbg [[DBG313]] 945 // CHECK-NEXT: ret void, !dbg [[DBG313]] 946 // 947