1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -fopenmp-cuda-mode -emit-llvm-bc %s -o %t-ppc-host.bc -fopenmp-version=45 3 // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple nvptx64-unknown-unknown -fopenmp-targets=nvptx64-nvidia-cuda -fopenmp-cuda-mode -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - -debug-info-kind=limited -fopenmp-version=45 | FileCheck %s --check-prefix=CHECK1 4 // expected-no-diagnostics 5 6 template <unsigned *ddd> 7 struct S { 8 static int a; 9 }; 10 11 extern unsigned aaa; 12 template<> int S<&aaa>::a; 13 14 template struct S<&aaa>; 15 16 int main() { 17 /* int(*b)[a]; */ 18 /* int *(**c)[a]; */ 19 bool bb; 20 int a; 21 int b[10][10]; 22 int c[10][10][10]; 23 #pragma omp target parallel firstprivate(a, b) map(tofrom \ 24 : c) map(tofrom \ 25 : bb) if (target:a) 26 { 27 int &f = c[1][1][1]; 28 int &g = a; 29 int &h = b[1][1]; 30 int d = 15; 31 a = 5; 32 b[0][a] = 10; 33 c[0][0][a] = 11; 34 b[0][a] = c[0][0][a]; 35 bb |= b[0][a]; 36 } 37 #pragma omp target parallel firstprivate(a) map(tofrom \ 38 : c, b) map(to \ 39 : bb) 40 { 41 int &f = c[1][1][1]; 42 int &g = a; 43 int &h = b[1][1]; 44 int d = 15; 45 a = 5; 46 b[0][a] = 10; 47 c[0][0][a] = 11; 48 b[0][a] = c[0][0][a]; 49 d = bb; 50 } 51 #pragma omp target parallel map(tofrom \ 52 : a, c, b) map(from \ 53 : bb) 54 { 55 int &f = c[1][1][1]; 56 int &g = a; 57 int &h = b[1][1]; 58 int d = 15; 59 a = 5; 60 b[0][a] = 10; 61 c[0][0][a] = 11; 62 b[0][a] = c[0][0][a]; 63 bb = b[0][a]; 64 } 65 return 0; 66 } 67 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug__ 68 // CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]]* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0:[0-9]+]] !dbg [[DBG24:![0-9]+]] { 69 // CHECK1-NEXT: entry: 70 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 71 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 72 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 73 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca i8 addrspace(1)*, align 8 74 // CHECK1-NEXT: [[TMP:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 75 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca [10 x [10 x i32]]*, align 8 76 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i8*, align 8 77 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 78 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 79 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]] addrspace(1)* [[C]], [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8 80 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], metadata [[META39:![0-9]+]], metadata !DIExpression()), !dbg [[DBG40:![0-9]+]] 81 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 82 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META41:![0-9]+]], metadata !DIExpression()), !dbg [[DBG42:![0-9]+]] 83 // CHECK1-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 84 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META43:![0-9]+]], metadata !DIExpression()), !dbg [[DBG44:![0-9]+]] 85 // CHECK1-NEXT: store i8 addrspace(1)* [[BB]], i8 addrspace(1)** [[BB_ADDR]], align 8 86 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8 addrspace(1)** [[BB_ADDR]], metadata [[META45:![0-9]+]], metadata !DIExpression()), !dbg [[DBG46:![0-9]+]] 87 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]] addrspace(1)*, [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8, !dbg [[DBG47:![0-9]+]] 88 // CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP0]] to [10 x [10 x [10 x i32]]]*, !dbg [[DBG47]] 89 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP1]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG47]] 90 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG47]] 91 // CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG47]] 92 // CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP3]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG47]] 93 // CHECK1-NEXT: [[TMP4:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG47]] 94 // CHECK1-NEXT: [[TMP5:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG47]] 95 // CHECK1-NEXT: [[TMP6:%.*]] = addrspacecast i8 addrspace(1)* [[TMP5]] to i8*, !dbg [[DBG47]] 96 // CHECK1-NEXT: store i8* [[TMP6]], i8** [[_TMP2]], align 8, !dbg [[DBG47]] 97 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[_TMP2]], align 8, !dbg [[DBG47]] 98 // CHECK1-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB1:[0-9]+]], i1 true, i1 false, i1 true), !dbg [[DBG47]] 99 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP8]], -1, !dbg [[DBG47]] 100 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG47]] 101 // CHECK1: user_code.entry: 102 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) 103 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG48:![0-9]+]] 104 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP2]], [10 x [10 x [10 x i32]]]** [[TMP10]], align 8, !dbg [[DBG48]] 105 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG48]] 106 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG49:![0-9]+]] 107 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[TMP11]], align 8, !dbg [[DBG48]] 108 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG48]] 109 // CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP4]], [10 x [10 x i32]]** [[TMP13]], align 8, !dbg [[DBG48]] 110 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG48]] 111 // CHECK1-NEXT: store i8* [[TMP7]], i8** [[TMP14]], align 8, !dbg [[DBG48]] 112 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG48]] 113 // CHECK1-NEXT: [[TMP16:%.*]] = call i8* @__kmpc_alloc_shared(i64 32), !dbg [[DBG48]] 114 // CHECK1-NEXT: [[TMP17:%.*]] = load [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], align 8, !dbg [[DBG48]] 115 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8* [[TMP16]] to %struct.anon*, !dbg [[DBG48]] 116 // CHECK1-NEXT: store [[STRUCT_ANON]] [[TMP17]], %struct.anon* [[TMP18]], align 8, !dbg [[DBG48]] 117 // CHECK1-NEXT: store i8* [[TMP16]], i8** [[TMP15]], align 8, !dbg [[DBG48]] 118 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG48]] 119 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB3]], i32 [[TMP9]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, %struct.anon*)* @__omp_outlined__ to i8*), i8* null, i8** [[TMP19]], i64 1), !dbg [[DBG48]] 120 // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[TMP16]]), !dbg [[DBG48]] 121 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB5:[0-9]+]], i1 true, i1 true), !dbg [[DBG51:![0-9]+]] 122 // CHECK1-NEXT: ret void, !dbg [[DBG52:![0-9]+]] 123 // CHECK1: worker.exit: 124 // CHECK1-NEXT: ret void, !dbg [[DBG47]] 125 // 126 // 127 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__ 128 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR0]] !dbg [[DBG53:![0-9]+]] { 129 // CHECK1-NEXT: entry: 130 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 131 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 132 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 133 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 134 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x [10 x i32]], align 4 135 // CHECK1-NEXT: [[F:%.*]] = alloca i32*, align 8 136 // CHECK1-NEXT: [[G:%.*]] = alloca i32*, align 8 137 // CHECK1-NEXT: [[H:%.*]] = alloca i32*, align 8 138 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 139 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 140 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META64:![0-9]+]], metadata !DIExpression()), !dbg [[DBG65:![0-9]+]] 141 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 142 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META66:![0-9]+]], metadata !DIExpression()), !dbg [[DBG65]] 143 // CHECK1-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 144 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata %struct.anon** [[__CONTEXT_ADDR]], metadata [[META67:![0-9]+]], metadata !DIExpression()), !dbg [[DBG65]] 145 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG68:![0-9]+]] 146 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0, !dbg [[DBG68]] 147 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP1]], align 8, !dbg [[DBG68]] 148 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 1, !dbg [[DBG68]] 149 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 8, !dbg [[DBG68]] 150 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[A]], align 4, !dbg [[DBG68]] 151 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 2, !dbg [[DBG68]] 152 // CHECK1-NEXT: [[TMP6:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[TMP5]], align 8, !dbg [[DBG68]] 153 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[TMP0]], i32 0, i32 3, !dbg [[DBG68]] 154 // CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[TMP7]], align 8, !dbg [[DBG68]] 155 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]* [[B]], metadata [[META69:![0-9]+]], metadata !DIExpression()), !dbg [[DBG65]] 156 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast [10 x [10 x i32]]* [[B]] to i8*, !dbg [[DBG68]] 157 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [10 x [10 x i32]]* [[TMP6]] to i8*, !dbg [[DBG68]] 158 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 [[TMP10]], i64 400, i1 false), !dbg [[DBG68]] 159 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[F]], metadata [[META70:![0-9]+]], metadata !DIExpression()), !dbg [[DBG73:![0-9]+]] 160 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 1, !dbg [[DBG74:![0-9]+]] 161 // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG74]] 162 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX1]], i64 0, i64 1, !dbg [[DBG74]] 163 // CHECK1-NEXT: store i32* [[ARRAYIDX2]], i32** [[F]], align 8, !dbg [[DBG73]] 164 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[G]], metadata [[META75:![0-9]+]], metadata !DIExpression()), !dbg [[DBG76:![0-9]+]] 165 // CHECK1-NEXT: store i32* [[A]], i32** [[G]], align 8, !dbg [[DBG76]] 166 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[H]], metadata [[META77:![0-9]+]], metadata !DIExpression()), !dbg [[DBG78:![0-9]+]] 167 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[B]], i64 0, i64 1, !dbg [[DBG79:![0-9]+]] 168 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX3]], i64 0, i64 1, !dbg [[DBG79]] 169 // CHECK1-NEXT: store i32* [[ARRAYIDX4]], i32** [[H]], align 8, !dbg [[DBG78]] 170 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[D]], metadata [[META80:![0-9]+]], metadata !DIExpression()), !dbg [[DBG81:![0-9]+]] 171 // CHECK1-NEXT: store i32 15, i32* [[D]], align 4, !dbg [[DBG81]] 172 // CHECK1-NEXT: store i32 5, i32* [[A]], align 4, !dbg [[DBG82:![0-9]+]] 173 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[B]], i64 0, i64 0, !dbg [[DBG83:![0-9]+]] 174 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG84:![0-9]+]] 175 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG83]] 176 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX5]], i64 0, i64 [[IDXPROM]], !dbg [[DBG83]] 177 // CHECK1-NEXT: store i32 10, i32* [[ARRAYIDX6]], align 4, !dbg [[DBG85:![0-9]+]] 178 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG86:![0-9]+]] 179 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX7]], i64 0, i64 0, !dbg [[DBG86]] 180 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG87:![0-9]+]] 181 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP12]] to i64, !dbg [[DBG86]] 182 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX8]], i64 0, i64 [[IDXPROM9]], !dbg [[DBG86]] 183 // CHECK1-NEXT: store i32 11, i32* [[ARRAYIDX10]], align 4, !dbg [[DBG88:![0-9]+]] 184 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG89:![0-9]+]] 185 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX11]], i64 0, i64 0, !dbg [[DBG89]] 186 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG90:![0-9]+]] 187 // CHECK1-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG89]] 188 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX12]], i64 0, i64 [[IDXPROM13]], !dbg [[DBG89]] 189 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[ARRAYIDX14]], align 4, !dbg [[DBG89]] 190 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[B]], i64 0, i64 0, !dbg [[DBG91:![0-9]+]] 191 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG92:![0-9]+]] 192 // CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP15]] to i64, !dbg [[DBG91]] 193 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG91]] 194 // CHECK1-NEXT: store i32 [[TMP14]], i32* [[ARRAYIDX17]], align 4, !dbg [[DBG93:![0-9]+]] 195 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[B]], i64 0, i64 0, !dbg [[DBG94:![0-9]+]] 196 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG95:![0-9]+]] 197 // CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG94]] 198 // CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG94]] 199 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[ARRAYIDX20]], align 4, !dbg [[DBG94]] 200 // CHECK1-NEXT: [[TMP18:%.*]] = load i8, i8* [[TMP8]], align 1, !dbg [[DBG96:![0-9]+]] 201 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP18]] to i1, !dbg [[DBG96]] 202 // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG96]] 203 // CHECK1-NEXT: [[OR:%.*]] = or i32 [[CONV]], [[TMP17]], !dbg [[DBG96]] 204 // CHECK1-NEXT: [[TOBOOL21:%.*]] = icmp ne i32 [[OR]], 0, !dbg [[DBG96]] 205 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL21]] to i8, !dbg [[DBG96]] 206 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[TMP8]], align 1, !dbg [[DBG96]] 207 // CHECK1-NEXT: ret void, !dbg [[DBG97:![0-9]+]] 208 // 209 // 210 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23 211 // CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG98:![0-9]+]] { 212 // CHECK1-NEXT: entry: 213 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 214 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 215 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 216 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca i8*, align 8 217 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]]* [[C]], [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8 218 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]]** [[C_ADDR]], metadata [[META105:![0-9]+]], metadata !DIExpression()), !dbg [[DBG106:![0-9]+]] 219 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 220 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i64* [[A_ADDR]], metadata [[META107:![0-9]+]], metadata !DIExpression()), !dbg [[DBG106]] 221 // CHECK1-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 222 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META108:![0-9]+]], metadata !DIExpression()), !dbg [[DBG106]] 223 // CHECK1-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 224 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META109:![0-9]+]], metadata !DIExpression()), !dbg [[DBG106]] 225 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG110:![0-9]+]] 226 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG110]] 227 // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG110]] 228 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG110]] 229 // CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG110]] 230 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG110]] 231 // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG110]] 232 // CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG110]] 233 // CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG110]] 234 // CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG110]] 235 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l23_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP7]], i32 [[TMP4]], [10 x [10 x i32]]* [[TMP5]], i8 addrspace(1)* [[TMP8]]) #[[ATTR3:[0-9]+]], !dbg [[DBG110]] 236 // CHECK1-NEXT: ret void, !dbg [[DBG110]] 237 // 238 // 239 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__ 240 // CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG111:![0-9]+]] { 241 // CHECK1-NEXT: entry: 242 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 243 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 244 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]] addrspace(1)*, align 8 245 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca i8 addrspace(1)*, align 8 246 // CHECK1-NEXT: [[TMP:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 247 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca [10 x [10 x i32]]*, align 8 248 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca i8*, align 8 249 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 250 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 251 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]] addrspace(1)* [[C]], [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8 252 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], metadata [[META116:![0-9]+]], metadata !DIExpression()), !dbg [[DBG117:![0-9]+]] 253 // CHECK1-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 254 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[A_ADDR]], metadata [[META118:![0-9]+]], metadata !DIExpression()), !dbg [[DBG119:![0-9]+]] 255 // CHECK1-NEXT: store [10 x [10 x i32]] addrspace(1)* [[B]], [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8 256 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], metadata [[META120:![0-9]+]], metadata !DIExpression()), !dbg [[DBG121:![0-9]+]] 257 // CHECK1-NEXT: store i8 addrspace(1)* [[BB]], i8 addrspace(1)** [[BB_ADDR]], align 8 258 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8 addrspace(1)** [[BB_ADDR]], metadata [[META122:![0-9]+]], metadata !DIExpression()), !dbg [[DBG123:![0-9]+]] 259 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]] addrspace(1)*, [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8, !dbg [[DBG124:![0-9]+]] 260 // CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP0]] to [10 x [10 x [10 x i32]]]*, !dbg [[DBG124]] 261 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP1]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG124]] 262 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG124]] 263 // CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x i32]] addrspace(1)*, [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG124]] 264 // CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast [10 x [10 x i32]] addrspace(1)* [[TMP3]] to [10 x [10 x i32]]*, !dbg [[DBG124]] 265 // CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP4]], [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG124]] 266 // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[_TMP1]], align 8, !dbg [[DBG124]] 267 // CHECK1-NEXT: [[TMP6:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG124]] 268 // CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast i8 addrspace(1)* [[TMP6]] to i8*, !dbg [[DBG124]] 269 // CHECK1-NEXT: store i8* [[TMP7]], i8** [[_TMP2]], align 8, !dbg [[DBG124]] 270 // CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[_TMP2]], align 8, !dbg [[DBG124]] 271 // CHECK1-NEXT: [[TMP9:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB7:[0-9]+]], i1 true, i1 false, i1 true), !dbg [[DBG124]] 272 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP9]], -1, !dbg [[DBG124]] 273 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG124]] 274 // CHECK1: user_code.entry: 275 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB9:[0-9]+]]) 276 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG125:![0-9]+]] 277 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP2]], [10 x [10 x [10 x i32]]]** [[TMP11]], align 8, !dbg [[DBG125]] 278 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG125]] 279 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[A_ADDR]], align 4, !dbg [[DBG126:![0-9]+]] 280 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[TMP12]], align 8, !dbg [[DBG125]] 281 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG125]] 282 // CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP5]], [10 x [10 x i32]]** [[TMP14]], align 8, !dbg [[DBG125]] 283 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG125]] 284 // CHECK1-NEXT: store i8* [[TMP8]], i8** [[TMP15]], align 8, !dbg [[DBG125]] 285 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG125]] 286 // CHECK1-NEXT: [[TMP17:%.*]] = call i8* @__kmpc_alloc_shared(i64 32), !dbg [[DBG125]] 287 // CHECK1-NEXT: [[TMP18:%.*]] = load [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], align 8, !dbg [[DBG125]] 288 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8* [[TMP17]] to %struct.anon.0*, !dbg [[DBG125]] 289 // CHECK1-NEXT: store [[STRUCT_ANON_0]] [[TMP18]], %struct.anon.0* [[TMP19]], align 8, !dbg [[DBG125]] 290 // CHECK1-NEXT: store i8* [[TMP17]], i8** [[TMP16]], align 8, !dbg [[DBG125]] 291 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG125]] 292 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB9]], i32 [[TMP10]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, %struct.anon.0*)* @__omp_outlined__1 to i8*), i8* null, i8** [[TMP20]], i64 1), !dbg [[DBG125]] 293 // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[TMP17]]), !dbg [[DBG125]] 294 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB11:[0-9]+]], i1 true, i1 true), !dbg [[DBG128:![0-9]+]] 295 // CHECK1-NEXT: ret void, !dbg [[DBG129:![0-9]+]] 296 // CHECK1: worker.exit: 297 // CHECK1-NEXT: ret void, !dbg [[DBG124]] 298 // 299 // 300 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__1 301 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR0]] !dbg [[DBG130:![0-9]+]] { 302 // CHECK1-NEXT: entry: 303 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 304 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 305 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.0*, align 8 306 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 307 // CHECK1-NEXT: [[F:%.*]] = alloca i32*, align 8 308 // CHECK1-NEXT: [[G:%.*]] = alloca i32*, align 8 309 // CHECK1-NEXT: [[H:%.*]] = alloca i32*, align 8 310 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 311 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 312 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META137:![0-9]+]], metadata !DIExpression()), !dbg [[DBG138:![0-9]+]] 313 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 314 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META139:![0-9]+]], metadata !DIExpression()), !dbg [[DBG138]] 315 // CHECK1-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 316 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata %struct.anon.0** [[__CONTEXT_ADDR]], metadata [[META140:![0-9]+]], metadata !DIExpression()), !dbg [[DBG138]] 317 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG141:![0-9]+]] 318 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0, !dbg [[DBG141]] 319 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP1]], align 8, !dbg [[DBG141]] 320 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1, !dbg [[DBG141]] 321 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 8, !dbg [[DBG141]] 322 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[A]], align 4, !dbg [[DBG141]] 323 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2, !dbg [[DBG141]] 324 // CHECK1-NEXT: [[TMP6:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[TMP5]], align 8, !dbg [[DBG141]] 325 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 3, !dbg [[DBG141]] 326 // CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[TMP7]], align 8, !dbg [[DBG141]] 327 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[F]], metadata [[META142:![0-9]+]], metadata !DIExpression()), !dbg [[DBG144:![0-9]+]] 328 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 1, !dbg [[DBG145:![0-9]+]] 329 // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG145]] 330 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX1]], i64 0, i64 1, !dbg [[DBG145]] 331 // CHECK1-NEXT: store i32* [[ARRAYIDX2]], i32** [[F]], align 8, !dbg [[DBG144]] 332 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[G]], metadata [[META146:![0-9]+]], metadata !DIExpression()), !dbg [[DBG147:![0-9]+]] 333 // CHECK1-NEXT: store i32* [[A]], i32** [[G]], align 8, !dbg [[DBG147]] 334 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[H]], metadata [[META148:![0-9]+]], metadata !DIExpression()), !dbg [[DBG149:![0-9]+]] 335 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP6]], i64 0, i64 1, !dbg [[DBG150:![0-9]+]] 336 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX3]], i64 0, i64 1, !dbg [[DBG150]] 337 // CHECK1-NEXT: store i32* [[ARRAYIDX4]], i32** [[H]], align 8, !dbg [[DBG149]] 338 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[D]], metadata [[META151:![0-9]+]], metadata !DIExpression()), !dbg [[DBG152:![0-9]+]] 339 // CHECK1-NEXT: store i32 15, i32* [[D]], align 4, !dbg [[DBG152]] 340 // CHECK1-NEXT: store i32 5, i32* [[A]], align 4, !dbg [[DBG153:![0-9]+]] 341 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP6]], i64 0, i64 0, !dbg [[DBG154:![0-9]+]] 342 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG155:![0-9]+]] 343 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG154]] 344 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX5]], i64 0, i64 [[IDXPROM]], !dbg [[DBG154]] 345 // CHECK1-NEXT: store i32 10, i32* [[ARRAYIDX6]], align 4, !dbg [[DBG156:![0-9]+]] 346 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG157:![0-9]+]] 347 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX7]], i64 0, i64 0, !dbg [[DBG157]] 348 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG158:![0-9]+]] 349 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG157]] 350 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX8]], i64 0, i64 [[IDXPROM9]], !dbg [[DBG157]] 351 // CHECK1-NEXT: store i32 11, i32* [[ARRAYIDX10]], align 4, !dbg [[DBG159:![0-9]+]] 352 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG160:![0-9]+]] 353 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX11]], i64 0, i64 0, !dbg [[DBG160]] 354 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG161:![0-9]+]] 355 // CHECK1-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG160]] 356 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX12]], i64 0, i64 [[IDXPROM13]], !dbg [[DBG160]] 357 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARRAYIDX14]], align 4, !dbg [[DBG160]] 358 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP6]], i64 0, i64 0, !dbg [[DBG162:![0-9]+]] 359 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[A]], align 4, !dbg [[DBG163:![0-9]+]] 360 // CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG162]] 361 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG162]] 362 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX17]], align 4, !dbg [[DBG164:![0-9]+]] 363 // CHECK1-NEXT: [[TMP14:%.*]] = load i8, i8* [[TMP8]], align 1, !dbg [[DBG165:![0-9]+]] 364 // CHECK1-NEXT: [[TOBOOL:%.*]] = trunc i8 [[TMP14]] to i1, !dbg [[DBG165]] 365 // CHECK1-NEXT: [[CONV:%.*]] = zext i1 [[TOBOOL]] to i32, !dbg [[DBG165]] 366 // CHECK1-NEXT: store i32 [[CONV]], i32* [[D]], align 4, !dbg [[DBG166:![0-9]+]] 367 // CHECK1-NEXT: ret void, !dbg [[DBG167:![0-9]+]] 368 // 369 // 370 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37 371 // CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i64 [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG168:![0-9]+]] { 372 // CHECK1-NEXT: entry: 373 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 374 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 375 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 376 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca i8*, align 8 377 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]]* [[C]], [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8 378 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]]** [[C_ADDR]], metadata [[META169:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170:![0-9]+]] 379 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 380 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i64* [[A_ADDR]], metadata [[META171:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170]] 381 // CHECK1-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 382 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META172:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170]] 383 // CHECK1-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 384 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META173:![0-9]+]], metadata !DIExpression()), !dbg [[DBG170]] 385 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG174:![0-9]+]] 386 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*, !dbg [[DBG174]] 387 // CHECK1-NEXT: [[TMP1:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG174]] 388 // CHECK1-NEXT: [[TMP2:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG174]] 389 // CHECK1-NEXT: [[TMP3:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG174]] 390 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG174]] 391 // CHECK1-NEXT: [[TMP5:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG174]] 392 // CHECK1-NEXT: [[TMP6:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG174]] 393 // CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP3]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG174]] 394 // CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP5]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG174]] 395 // CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast i8* [[TMP6]] to i8 addrspace(1)*, !dbg [[DBG174]] 396 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l37_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP7]], i32 [[TMP4]], [10 x [10 x i32]] addrspace(1)* [[TMP8]], i8 addrspace(1)* [[TMP9]]) #[[ATTR3]], !dbg [[DBG174]] 397 // CHECK1-NEXT: ret void, !dbg [[DBG174]] 398 // 399 // 400 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__ 401 // CHECK1-SAME: ([10 x [10 x [10 x i32]]] addrspace(1)* noalias [[C:%.*]], i32 addrspace(1)* noalias [[A:%.*]], [10 x [10 x i32]] addrspace(1)* noalias [[B:%.*]], i8 addrspace(1)* noalias [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG175:![0-9]+]] { 402 // CHECK1-NEXT: entry: 403 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]] addrspace(1)*, align 8 404 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32 addrspace(1)*, align 8 405 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]] addrspace(1)*, align 8 406 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca i8 addrspace(1)*, align 8 407 // CHECK1-NEXT: [[TMP:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 408 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 409 // CHECK1-NEXT: [[_TMP2:%.*]] = alloca [10 x [10 x i32]]*, align 8 410 // CHECK1-NEXT: [[_TMP3:%.*]] = alloca i8*, align 8 411 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 412 // CHECK1-NEXT: [[CAPTURED_VARS_ADDRS:%.*]] = alloca [1 x i8*], align 8 413 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]] addrspace(1)* [[C]], [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8 414 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], metadata [[META180:![0-9]+]], metadata !DIExpression()), !dbg [[DBG181:![0-9]+]] 415 // CHECK1-NEXT: store i32 addrspace(1)* [[A]], i32 addrspace(1)** [[A_ADDR]], align 8 416 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32 addrspace(1)** [[A_ADDR]], metadata [[META182:![0-9]+]], metadata !DIExpression()), !dbg [[DBG183:![0-9]+]] 417 // CHECK1-NEXT: store [10 x [10 x i32]] addrspace(1)* [[B]], [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8 418 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], metadata [[META184:![0-9]+]], metadata !DIExpression()), !dbg [[DBG185:![0-9]+]] 419 // CHECK1-NEXT: store i8 addrspace(1)* [[BB]], i8 addrspace(1)** [[BB_ADDR]], align 8 420 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8 addrspace(1)** [[BB_ADDR]], metadata [[META186:![0-9]+]], metadata !DIExpression()), !dbg [[DBG187:![0-9]+]] 421 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]] addrspace(1)*, [10 x [10 x [10 x i32]]] addrspace(1)** [[C_ADDR]], align 8, !dbg [[DBG188:![0-9]+]] 422 // CHECK1-NEXT: [[TMP1:%.*]] = addrspacecast [10 x [10 x [10 x i32]]] addrspace(1)* [[TMP0]] to [10 x [10 x [10 x i32]]]*, !dbg [[DBG188]] 423 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP1]], [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG188]] 424 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP]], align 8, !dbg [[DBG188]] 425 // CHECK1-NEXT: [[TMP3:%.*]] = load i32 addrspace(1)*, i32 addrspace(1)** [[A_ADDR]], align 8, !dbg [[DBG188]] 426 // CHECK1-NEXT: [[TMP4:%.*]] = addrspacecast i32 addrspace(1)* [[TMP3]] to i32*, !dbg [[DBG188]] 427 // CHECK1-NEXT: store i32* [[TMP4]], i32** [[_TMP1]], align 8, !dbg [[DBG188]] 428 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[_TMP1]], align 8, !dbg [[DBG188]] 429 // CHECK1-NEXT: [[TMP6:%.*]] = load [10 x [10 x i32]] addrspace(1)*, [10 x [10 x i32]] addrspace(1)** [[B_ADDR]], align 8, !dbg [[DBG188]] 430 // CHECK1-NEXT: [[TMP7:%.*]] = addrspacecast [10 x [10 x i32]] addrspace(1)* [[TMP6]] to [10 x [10 x i32]]*, !dbg [[DBG188]] 431 // CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP7]], [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG188]] 432 // CHECK1-NEXT: [[TMP8:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[_TMP2]], align 8, !dbg [[DBG188]] 433 // CHECK1-NEXT: [[TMP9:%.*]] = load i8 addrspace(1)*, i8 addrspace(1)** [[BB_ADDR]], align 8, !dbg [[DBG188]] 434 // CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast i8 addrspace(1)* [[TMP9]] to i8*, !dbg [[DBG188]] 435 // CHECK1-NEXT: store i8* [[TMP10]], i8** [[_TMP3]], align 8, !dbg [[DBG188]] 436 // CHECK1-NEXT: [[TMP11:%.*]] = load i8*, i8** [[_TMP3]], align 8, !dbg [[DBG188]] 437 // CHECK1-NEXT: [[TMP12:%.*]] = call i32 @__kmpc_target_init(%struct.ident_t* @[[GLOB13:[0-9]+]], i1 true, i1 false, i1 true), !dbg [[DBG188]] 438 // CHECK1-NEXT: [[EXEC_USER_CODE:%.*]] = icmp eq i32 [[TMP12]], -1, !dbg [[DBG188]] 439 // CHECK1-NEXT: br i1 [[EXEC_USER_CODE]], label [[USER_CODE_ENTRY:%.*]], label [[WORKER_EXIT:%.*]], !dbg [[DBG188]] 440 // CHECK1: user_code.entry: 441 // CHECK1-NEXT: [[TMP13:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB15:[0-9]+]]) 442 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG189:![0-9]+]] 443 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]]* [[TMP2]], [10 x [10 x [10 x i32]]]** [[TMP14]], align 8, !dbg [[DBG189]] 444 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG189]] 445 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[TMP15]], align 8, !dbg [[DBG189]] 446 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG189]] 447 // CHECK1-NEXT: store [10 x [10 x i32]]* [[TMP8]], [10 x [10 x i32]]** [[TMP16]], align 8, !dbg [[DBG189]] 448 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG189]] 449 // CHECK1-NEXT: store i8* [[TMP11]], i8** [[TMP17]], align 8, !dbg [[DBG189]] 450 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[CAPTURED_VARS_ADDRS]], i64 0, i64 0, !dbg [[DBG189]] 451 // CHECK1-NEXT: [[TMP19:%.*]] = call i8* @__kmpc_alloc_shared(i64 32), !dbg [[DBG189]] 452 // CHECK1-NEXT: [[TMP20:%.*]] = load [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], align 8, !dbg [[DBG189]] 453 // CHECK1-NEXT: [[TMP21:%.*]] = bitcast i8* [[TMP19]] to %struct.anon.1*, !dbg [[DBG189]] 454 // CHECK1-NEXT: store [[STRUCT_ANON_1]] [[TMP20]], %struct.anon.1* [[TMP21]], align 8, !dbg [[DBG189]] 455 // CHECK1-NEXT: store i8* [[TMP19]], i8** [[TMP18]], align 8, !dbg [[DBG189]] 456 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast [1 x i8*]* [[CAPTURED_VARS_ADDRS]] to i8**, !dbg [[DBG189]] 457 // CHECK1-NEXT: call void @__kmpc_parallel_51(%struct.ident_t* @[[GLOB15]], i32 [[TMP13]], i32 1, i32 -1, i32 -1, i8* bitcast (void (i32*, i32*, %struct.anon.1*)* @__omp_outlined__2 to i8*), i8* null, i8** [[TMP22]], i64 1), !dbg [[DBG189]] 458 // CHECK1-NEXT: call void @__kmpc_free_shared(i8* [[TMP19]]), !dbg [[DBG189]] 459 // CHECK1-NEXT: call void @__kmpc_target_deinit(%struct.ident_t* @[[GLOB17:[0-9]+]], i1 true, i1 true), !dbg [[DBG190:![0-9]+]] 460 // CHECK1-NEXT: ret void, !dbg [[DBG192:![0-9]+]] 461 // CHECK1: worker.exit: 462 // CHECK1-NEXT: ret void, !dbg [[DBG188]] 463 // 464 // 465 // CHECK1-LABEL: define {{[^@]+}}@__omp_outlined__2 466 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR0]] !dbg [[DBG193:![0-9]+]] { 467 // CHECK1-NEXT: entry: 468 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 469 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 470 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.1*, align 8 471 // CHECK1-NEXT: [[F:%.*]] = alloca i32*, align 8 472 // CHECK1-NEXT: [[G:%.*]] = alloca i32*, align 8 473 // CHECK1-NEXT: [[H:%.*]] = alloca i32*, align 8 474 // CHECK1-NEXT: [[D:%.*]] = alloca i32, align 4 475 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 476 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTGLOBAL_TID__ADDR]], metadata [[META200:![0-9]+]], metadata !DIExpression()), !dbg [[DBG201:![0-9]+]] 477 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 478 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[DOTBOUND_TID__ADDR]], metadata [[META202:![0-9]+]], metadata !DIExpression()), !dbg [[DBG201]] 479 // CHECK1-NEXT: store %struct.anon.1* [[__CONTEXT]], %struct.anon.1** [[__CONTEXT_ADDR]], align 8 480 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata %struct.anon.1** [[__CONTEXT_ADDR]], metadata [[META203:![0-9]+]], metadata !DIExpression()), !dbg [[DBG201]] 481 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG204:![0-9]+]] 482 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP0]], i32 0, i32 0, !dbg [[DBG204]] 483 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[TMP1]], align 8, !dbg [[DBG204]] 484 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 1, !dbg [[DBG204]] 485 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[TMP3]], align 8, !dbg [[DBG204]] 486 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 2, !dbg [[DBG204]] 487 // CHECK1-NEXT: [[TMP6:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[TMP5]], align 8, !dbg [[DBG204]] 488 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 3, !dbg [[DBG204]] 489 // CHECK1-NEXT: [[TMP8:%.*]] = load i8*, i8** [[TMP7]], align 8, !dbg [[DBG204]] 490 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[F]], metadata [[META205:![0-9]+]], metadata !DIExpression()), !dbg [[DBG207:![0-9]+]] 491 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 1, !dbg [[DBG208:![0-9]+]] 492 // CHECK1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX]], i64 0, i64 1, !dbg [[DBG208]] 493 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX1]], i64 0, i64 1, !dbg [[DBG208]] 494 // CHECK1-NEXT: store i32* [[ARRAYIDX2]], i32** [[F]], align 8, !dbg [[DBG207]] 495 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[G]], metadata [[META209:![0-9]+]], metadata !DIExpression()), !dbg [[DBG210:![0-9]+]] 496 // CHECK1-NEXT: store i32* [[TMP4]], i32** [[G]], align 8, !dbg [[DBG210]] 497 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[H]], metadata [[META211:![0-9]+]], metadata !DIExpression()), !dbg [[DBG212:![0-9]+]] 498 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP6]], i64 0, i64 1, !dbg [[DBG213:![0-9]+]] 499 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX3]], i64 0, i64 1, !dbg [[DBG213]] 500 // CHECK1-NEXT: store i32* [[ARRAYIDX4]], i32** [[H]], align 8, !dbg [[DBG212]] 501 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32* [[D]], metadata [[META214:![0-9]+]], metadata !DIExpression()), !dbg [[DBG215:![0-9]+]] 502 // CHECK1-NEXT: store i32 15, i32* [[D]], align 4, !dbg [[DBG215]] 503 // CHECK1-NEXT: store i32 5, i32* [[TMP4]], align 4, !dbg [[DBG216:![0-9]+]] 504 // CHECK1-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP6]], i64 0, i64 0, !dbg [[DBG217:![0-9]+]] 505 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG218:![0-9]+]] 506 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP9]] to i64, !dbg [[DBG217]] 507 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX5]], i64 0, i64 [[IDXPROM]], !dbg [[DBG217]] 508 // CHECK1-NEXT: store i32 10, i32* [[ARRAYIDX6]], align 4, !dbg [[DBG219:![0-9]+]] 509 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG220:![0-9]+]] 510 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX7]], i64 0, i64 0, !dbg [[DBG220]] 511 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG221:![0-9]+]] 512 // CHECK1-NEXT: [[IDXPROM9:%.*]] = sext i32 [[TMP10]] to i64, !dbg [[DBG220]] 513 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX8]], i64 0, i64 [[IDXPROM9]], !dbg [[DBG220]] 514 // CHECK1-NEXT: store i32 11, i32* [[ARRAYIDX10]], align 4, !dbg [[DBG222:![0-9]+]] 515 // CHECK1-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [10 x [10 x [10 x i32]]], [10 x [10 x [10 x i32]]]* [[TMP2]], i64 0, i64 0, !dbg [[DBG223:![0-9]+]] 516 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[ARRAYIDX11]], i64 0, i64 0, !dbg [[DBG223]] 517 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG224:![0-9]+]] 518 // CHECK1-NEXT: [[IDXPROM13:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG223]] 519 // CHECK1-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX12]], i64 0, i64 [[IDXPROM13]], !dbg [[DBG223]] 520 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARRAYIDX14]], align 4, !dbg [[DBG223]] 521 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP6]], i64 0, i64 0, !dbg [[DBG225:![0-9]+]] 522 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG226:![0-9]+]] 523 // CHECK1-NEXT: [[IDXPROM16:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG225]] 524 // CHECK1-NEXT: [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX15]], i64 0, i64 [[IDXPROM16]], !dbg [[DBG225]] 525 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[ARRAYIDX17]], align 4, !dbg [[DBG227:![0-9]+]] 526 // CHECK1-NEXT: [[ARRAYIDX18:%.*]] = getelementptr inbounds [10 x [10 x i32]], [10 x [10 x i32]]* [[TMP6]], i64 0, i64 0, !dbg [[DBG228:![0-9]+]] 527 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG229:![0-9]+]] 528 // CHECK1-NEXT: [[IDXPROM19:%.*]] = sext i32 [[TMP14]] to i64, !dbg [[DBG228]] 529 // CHECK1-NEXT: [[ARRAYIDX20:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[ARRAYIDX18]], i64 0, i64 [[IDXPROM19]], !dbg [[DBG228]] 530 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[ARRAYIDX20]], align 4, !dbg [[DBG228]] 531 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0, !dbg [[DBG228]] 532 // CHECK1-NEXT: [[FROMBOOL:%.*]] = zext i1 [[TOBOOL]] to i8, !dbg [[DBG230:![0-9]+]] 533 // CHECK1-NEXT: store i8 [[FROMBOOL]], i8* [[TMP8]], align 1, !dbg [[DBG230]] 534 // CHECK1-NEXT: ret void, !dbg [[DBG231:![0-9]+]] 535 // 536 // 537 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51 538 // CHECK1-SAME: ([10 x [10 x [10 x i32]]]* nonnull align 4 dereferenceable(4000) [[C:%.*]], i32* nonnull align 4 dereferenceable(4) [[A:%.*]], [10 x [10 x i32]]* nonnull align 4 dereferenceable(400) [[B:%.*]], i8* nonnull align 1 dereferenceable(1) [[BB:%.*]]) #[[ATTR0]] !dbg [[DBG232:![0-9]+]] { 539 // CHECK1-NEXT: entry: 540 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [10 x [10 x [10 x i32]]]*, align 8 541 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i32*, align 8 542 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x [10 x i32]]*, align 8 543 // CHECK1-NEXT: [[BB_ADDR:%.*]] = alloca i8*, align 8 544 // CHECK1-NEXT: store [10 x [10 x [10 x i32]]]* [[C]], [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8 545 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x [10 x i32]]]** [[C_ADDR]], metadata [[META235:![0-9]+]], metadata !DIExpression()), !dbg [[DBG236:![0-9]+]] 546 // CHECK1-NEXT: store i32* [[A]], i32** [[A_ADDR]], align 8 547 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i32** [[A_ADDR]], metadata [[META237:![0-9]+]], metadata !DIExpression()), !dbg [[DBG236]] 548 // CHECK1-NEXT: store [10 x [10 x i32]]* [[B]], [10 x [10 x i32]]** [[B_ADDR]], align 8 549 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata [10 x [10 x i32]]** [[B_ADDR]], metadata [[META238:![0-9]+]], metadata !DIExpression()), !dbg [[DBG236]] 550 // CHECK1-NEXT: store i8* [[BB]], i8** [[BB_ADDR]], align 8 551 // CHECK1-NEXT: call void @llvm.dbg.declare(metadata i8** [[BB_ADDR]], metadata [[META239:![0-9]+]], metadata !DIExpression()), !dbg [[DBG236]] 552 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG240:![0-9]+]] 553 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[A_ADDR]], align 8, !dbg [[DBG240]] 554 // CHECK1-NEXT: [[TMP2:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG240]] 555 // CHECK1-NEXT: [[TMP3:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG240]] 556 // CHECK1-NEXT: [[TMP4:%.*]] = load [10 x [10 x [10 x i32]]]*, [10 x [10 x [10 x i32]]]** [[C_ADDR]], align 8, !dbg [[DBG240]] 557 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[A_ADDR]], align 8, !dbg [[DBG240]] 558 // CHECK1-NEXT: [[TMP6:%.*]] = load [10 x [10 x i32]]*, [10 x [10 x i32]]** [[B_ADDR]], align 8, !dbg [[DBG240]] 559 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[BB_ADDR]], align 8, !dbg [[DBG240]] 560 // CHECK1-NEXT: [[TMP8:%.*]] = addrspacecast [10 x [10 x [10 x i32]]]* [[TMP4]] to [10 x [10 x [10 x i32]]] addrspace(1)*, !dbg [[DBG240]] 561 // CHECK1-NEXT: [[TMP9:%.*]] = addrspacecast i32* [[TMP5]] to i32 addrspace(1)*, !dbg [[DBG240]] 562 // CHECK1-NEXT: [[TMP10:%.*]] = addrspacecast [10 x [10 x i32]]* [[TMP6]] to [10 x [10 x i32]] addrspace(1)*, !dbg [[DBG240]] 563 // CHECK1-NEXT: [[TMP11:%.*]] = addrspacecast i8* [[TMP7]] to i8 addrspace(1)*, !dbg [[DBG240]] 564 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}_main_l51_debug__([10 x [10 x [10 x i32]]] addrspace(1)* [[TMP8]], i32 addrspace(1)* [[TMP9]], [10 x [10 x i32]] addrspace(1)* [[TMP10]], i8 addrspace(1)* [[TMP11]]) #[[ATTR3]], !dbg [[DBG240]] 565 // CHECK1-NEXT: ret void, !dbg [[DBG240]] 566 // 567