1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 26 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 40 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 43 44 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 60 61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 8 target regions, but only 6 that actually will generate offloading 78 // code and have mapped arguments, and only 4 have all-constant map sizes. 79 80 81 82 // Check target registration is registered as a Ctor. 83 84 85 template<typename tx, typename ty> 86 struct TT{ 87 tx X; 88 ty Y; 89 }; 90 91 int foo(int n) { 92 int a = 0; 93 short aa = 0; 94 float b[10]; 95 float bn[n]; 96 double c[5][10]; 97 double cn[5][n]; 98 TT<long long, char> d; 99 100 #pragma omp target parallel nowait 101 { 102 } 103 104 #pragma omp target parallel if(target: 0) 105 { 106 a += 1; 107 } 108 109 110 #pragma omp target parallel if(target: 1) 111 { 112 aa += 1; 113 #pragma omp cancel parallel 114 } 115 116 117 118 119 #pragma omp target parallel if(target: n>10) 120 { 121 a += 1; 122 aa += 1; 123 } 124 125 // We capture 3 VLA sizes in this target region 126 127 128 129 130 131 // The names below are not necessarily consistent with the names used for the 132 // addresses above as some are repeated. 133 134 135 136 137 138 139 140 141 142 143 144 #pragma omp target parallel if(target: n>20) 145 { 146 a += 1; 147 b[2] += 1.0; 148 bn[3] += 1.0; 149 c[1][2] += 1.0; 150 cn[1][3] += 1.0; 151 d.X += 1; 152 d.Y += 1; 153 } 154 155 return a; 156 } 157 158 // Check that the offloading functions are emitted and that the arguments are 159 // correct and loaded correctly for the target regions in foo(). 160 161 162 163 // Create stack storage and store argument in there. 164 165 // Create stack storage and store argument in there. 166 167 // Create stack storage and store argument in there. 168 169 // Create local storage for each capture. 170 171 172 173 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 174 175 template<typename tx> 176 tx ftemplate(int n) { 177 tx a = 0; 178 short aa = 0; 179 tx b[10]; 180 181 #pragma omp target parallel if(target: n>40) 182 { 183 a += 1; 184 aa += 1; 185 b[2] += 1; 186 } 187 188 return a; 189 } 190 191 static 192 int fstatic(int n) { 193 int a = 0; 194 short aa = 0; 195 char aaa = 0; 196 int b[10]; 197 198 #pragma omp target parallel if(target: n>50) 199 { 200 a += 1; 201 aa += 1; 202 aaa += 1; 203 b[2] += 1; 204 } 205 206 return a; 207 } 208 209 struct S1 { 210 double a; 211 212 int r1(int n){ 213 int b = n+1; 214 short int c[2][n]; 215 216 #pragma omp target parallel if(target: n>60) 217 { 218 this->a = (double)b + 1.5; 219 c[1][1] = ++a; 220 } 221 222 return c[1][1] + (int)b; 223 } 224 }; 225 226 int bar(int n){ 227 int a = 0; 228 229 a += foo(n); 230 231 S1 S; 232 a += S.r1(n); 233 234 a += fstatic(n); 235 236 a += ftemplate<int>(n); 237 238 return a; 239 } 240 241 242 243 // We capture 2 VLA sizes in this target region 244 245 246 // The names below are not necessarily consistent with the names used for the 247 // addresses above as some are repeated. 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 // Check that the offloading functions are emitted and that the arguments are 268 // correct and loaded correctly for the target regions of the callees of bar(). 269 270 // Create local storage for each capture. 271 // Store captures in the context. 272 273 274 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 275 276 277 // Create local storage for each capture. 278 // Store captures in the context. 279 280 281 282 283 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 284 285 // Create local storage for each capture. 286 // Store captures in the context. 287 288 289 290 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 291 292 293 #endif 294 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 295 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 296 // CHECK1-NEXT: entry: 297 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 300 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 301 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 302 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 303 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 304 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 305 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 306 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 307 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 308 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 309 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 310 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 311 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 312 // CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 315 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 316 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 317 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 319 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 321 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 322 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 323 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 324 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 325 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 326 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 327 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 328 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 329 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 330 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 331 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 332 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 333 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 334 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 335 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 336 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 337 // CHECK1-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 338 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 339 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 340 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 341 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 342 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 343 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 344 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 345 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 346 // CHECK1-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 347 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 348 // CHECK1-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 349 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 350 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 351 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 352 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 353 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 354 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 355 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 356 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 357 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 358 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 359 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 360 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 361 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 362 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 363 // CHECK1: omp_offload.failed: 364 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 365 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 366 // CHECK1: omp_offload.cont: 367 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 368 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 369 // CHECK1-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 370 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 371 // CHECK1-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 372 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 373 // CHECK1-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 374 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 375 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 376 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 377 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 378 // CHECK1: omp_if.then: 379 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 380 // CHECK1-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 381 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 382 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 383 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 384 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 385 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 386 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 387 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 388 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* 389 // CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 390 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 391 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 392 // CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 393 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 394 // CHECK1-NEXT: store i8* null, i8** [[TMP38]], align 8 395 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 396 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 398 // CHECK1-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 399 // CHECK1-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 400 // CHECK1: omp_offload.failed10: 401 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 402 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT11]] 403 // CHECK1: omp_offload.cont11: 404 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 405 // CHECK1: omp_if.else: 406 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 407 // CHECK1-NEXT: br label [[OMP_IF_END]] 408 // CHECK1: omp_if.end: 409 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 410 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 411 // CHECK1-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 412 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 413 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 414 // CHECK1-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 415 // CHECK1-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] 416 // CHECK1: omp_if.then15: 417 // CHECK1-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 418 // CHECK1-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] 419 // CHECK1-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 420 // CHECK1-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 421 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP49]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i64 72, i1 false) 422 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 423 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 424 // CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8 425 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 426 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 427 // CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8 428 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 429 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8 430 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 431 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 432 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 433 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 434 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 435 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 436 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 437 // CHECK1-NEXT: store i8* null, i8** [[TMP59]], align 8 438 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 439 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64* 440 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP61]], align 8 441 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 442 // CHECK1-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64* 443 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP63]], align 8 444 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 445 // CHECK1-NEXT: store i8* null, i8** [[TMP64]], align 8 446 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 447 // CHECK1-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 448 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP66]], align 8 449 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 450 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 451 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 452 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 453 // CHECK1-NEXT: store i64 [[TMP46]], i64* [[TMP69]], align 8 454 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 455 // CHECK1-NEXT: store i8* null, i8** [[TMP70]], align 8 456 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 457 // CHECK1-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 458 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 8 459 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 460 // CHECK1-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 461 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 462 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 463 // CHECK1-NEXT: store i8* null, i8** [[TMP75]], align 8 464 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 465 // CHECK1-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* 466 // CHECK1-NEXT: store i64 5, i64* [[TMP77]], align 8 467 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 468 // CHECK1-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 469 // CHECK1-NEXT: store i64 5, i64* [[TMP79]], align 8 470 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 471 // CHECK1-NEXT: store i8* null, i8** [[TMP80]], align 8 472 // CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 473 // CHECK1-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 474 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP82]], align 8 475 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 476 // CHECK1-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i64* 477 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP84]], align 8 478 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 479 // CHECK1-NEXT: store i8* null, i8** [[TMP85]], align 8 480 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 481 // CHECK1-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 482 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP87]], align 8 483 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 484 // CHECK1-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 485 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP89]], align 8 486 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 487 // CHECK1-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 8 488 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 489 // CHECK1-NEXT: store i8* null, i8** [[TMP91]], align 8 490 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 491 // CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 492 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 8 493 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 494 // CHECK1-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 495 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 8 496 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 497 // CHECK1-NEXT: store i8* null, i8** [[TMP96]], align 8 498 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 499 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 500 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 501 // CHECK1-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 502 // CHECK1-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 503 // CHECK1-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 504 // CHECK1: omp_offload.failed19: 505 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 506 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT20]] 507 // CHECK1: omp_offload.cont20: 508 // CHECK1-NEXT: br label [[OMP_IF_END22:%.*]] 509 // CHECK1: omp_if.else21: 510 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 511 // CHECK1-NEXT: br label [[OMP_IF_END22]] 512 // CHECK1: omp_if.end22: 513 // CHECK1-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 514 // CHECK1-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 515 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 516 // CHECK1-NEXT: ret i32 [[TMP102]] 517 // 518 // 519 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 520 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 521 // CHECK1-NEXT: entry: 522 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 523 // CHECK1-NEXT: ret void 524 // 525 // 526 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 527 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 528 // CHECK1-NEXT: entry: 529 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 530 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 531 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 532 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 533 // CHECK1-NEXT: ret void 534 // 535 // 536 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 537 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 538 // CHECK1-NEXT: entry: 539 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 540 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 541 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 542 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 543 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 544 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 545 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 546 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 547 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 548 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 549 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 550 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 551 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 552 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 553 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 554 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 555 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 556 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 557 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 558 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 559 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 560 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 561 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 562 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 563 // CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 564 // CHECK1-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 565 // CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 566 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 567 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 568 // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 569 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 570 // CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 571 // CHECK1: omp_offload.failed.i: 572 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 573 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 574 // CHECK1: .omp_outlined..1.exit: 575 // CHECK1-NEXT: ret i32 0 576 // 577 // 578 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 579 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 580 // CHECK1-NEXT: entry: 581 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 582 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 583 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 584 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 585 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 586 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 587 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 588 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 589 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 590 // CHECK1-NEXT: ret void 591 // 592 // 593 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 594 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 595 // CHECK1-NEXT: entry: 596 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 597 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 598 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 599 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 600 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 601 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 602 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 603 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 604 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 605 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 606 // CHECK1-NEXT: ret void 607 // 608 // 609 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 610 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 611 // CHECK1-NEXT: entry: 612 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 613 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 614 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 615 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 616 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 617 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 618 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 619 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 620 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 621 // CHECK1-NEXT: ret void 622 // 623 // 624 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 625 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 626 // CHECK1-NEXT: entry: 627 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 628 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 629 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 630 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 631 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 632 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 633 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 634 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 635 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 636 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 637 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 638 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 639 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 640 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 641 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 642 // CHECK1-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 643 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 644 // CHECK1: .cancel.exit: 645 // CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 646 // CHECK1-NEXT: br label [[DOTCANCEL_CONTINUE]] 647 // CHECK1: .cancel.continue: 648 // CHECK1-NEXT: ret void 649 // 650 // 651 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 652 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 653 // CHECK1-NEXT: entry: 654 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 655 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 656 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 657 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 658 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 659 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 660 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 661 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 662 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 663 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 664 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 665 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 666 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 667 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 668 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 669 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 670 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 671 // CHECK1-NEXT: ret void 672 // 673 // 674 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 675 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 676 // CHECK1-NEXT: entry: 677 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 678 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 679 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 680 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 681 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 682 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 683 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 684 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 685 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 686 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 687 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 688 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 689 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 690 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 691 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 692 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 693 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 694 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 695 // CHECK1-NEXT: ret void 696 // 697 // 698 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 699 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 700 // CHECK1-NEXT: entry: 701 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 702 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 703 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 704 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 705 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 706 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 707 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 708 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 709 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 710 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 711 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 712 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 713 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 714 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 715 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 716 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 717 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 718 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 719 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 720 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 721 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 722 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 723 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 724 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 725 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 726 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 727 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 728 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 729 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 730 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 731 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 732 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 733 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 734 // CHECK1-NEXT: ret void 735 // 736 // 737 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 738 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 739 // CHECK1-NEXT: entry: 740 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 741 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 742 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 743 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 744 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 745 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 746 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 747 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 748 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 749 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 750 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 751 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 752 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 753 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 754 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 755 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 756 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 757 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 758 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 759 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 760 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 761 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 762 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 763 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 764 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 765 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 766 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 767 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 768 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 769 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 770 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 771 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 772 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 773 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 774 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 775 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 776 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 777 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 778 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 779 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 780 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 781 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 782 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 783 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 784 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 785 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 786 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 787 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 788 // CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 789 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 790 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 791 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 792 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 793 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 794 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 795 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 796 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 797 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 798 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 799 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 800 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 801 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 802 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 803 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 804 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 805 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 806 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 807 // CHECK1-NEXT: ret void 808 // 809 // 810 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 811 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 812 // CHECK1-NEXT: entry: 813 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 814 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 815 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 816 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 817 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 818 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 819 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 820 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 821 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 822 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 823 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 824 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 825 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 826 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 827 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 828 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 829 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 830 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 831 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 832 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 833 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 834 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 835 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 836 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 837 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 838 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 839 // CHECK1-NEXT: ret i32 [[TMP8]] 840 // 841 // 842 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 843 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 844 // CHECK1-NEXT: entry: 845 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 846 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 847 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 848 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 849 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 850 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 851 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 852 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 853 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 854 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 855 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 856 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 857 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 858 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 859 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 860 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 861 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 862 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 863 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 864 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 865 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 866 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 867 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 868 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 869 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 870 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 871 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 872 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 873 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 874 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 875 // CHECK1: omp_if.then: 876 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 877 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 878 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 879 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 880 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 881 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 882 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 883 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 884 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 885 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 886 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 887 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 888 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 889 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 890 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 891 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 892 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 893 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 894 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 895 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 896 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 897 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 898 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 899 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 900 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 901 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 902 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 903 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 904 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 905 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 906 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 907 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 908 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 909 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 910 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 911 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 912 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 913 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 914 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 915 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 916 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 917 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 918 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 919 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 920 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 921 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 922 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 923 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 924 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 925 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 926 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 927 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 928 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 929 // CHECK1: omp_offload.failed: 930 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 931 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 932 // CHECK1: omp_offload.cont: 933 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 934 // CHECK1: omp_if.else: 935 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 936 // CHECK1-NEXT: br label [[OMP_IF_END]] 937 // CHECK1: omp_if.end: 938 // CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 939 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 940 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 941 // CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 942 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 943 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 944 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 945 // CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 946 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 947 // CHECK1-NEXT: ret i32 [[ADD4]] 948 // 949 // 950 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 951 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 952 // CHECK1-NEXT: entry: 953 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 954 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 955 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 956 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 957 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 958 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 959 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 960 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 961 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 962 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 963 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 964 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 965 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 966 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 967 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 968 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 969 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 970 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 971 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 972 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 973 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 974 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 975 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 976 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 977 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 978 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 979 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 980 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 981 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 982 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 983 // CHECK1: omp_if.then: 984 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 985 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 986 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 987 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 988 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 989 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 990 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 991 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 992 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 993 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 994 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 995 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 996 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 997 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 998 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 999 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1000 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1001 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1002 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1003 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1004 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1005 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1006 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1007 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1008 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1009 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1010 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1011 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1012 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1013 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1014 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1015 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1016 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1017 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1018 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1019 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1020 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1021 // CHECK1: omp_offload.failed: 1022 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1023 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1024 // CHECK1: omp_offload.cont: 1025 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1026 // CHECK1: omp_if.else: 1027 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1028 // CHECK1-NEXT: br label [[OMP_IF_END]] 1029 // CHECK1: omp_if.end: 1030 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1031 // CHECK1-NEXT: ret i32 [[TMP31]] 1032 // 1033 // 1034 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1035 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1036 // CHECK1-NEXT: entry: 1037 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1038 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1039 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1040 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1041 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1042 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1043 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1044 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1045 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1046 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1047 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1048 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1049 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1050 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1051 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1052 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1053 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1054 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1055 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1056 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1057 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1058 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1059 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1060 // CHECK1: omp_if.then: 1061 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1062 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1063 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1064 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1065 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1066 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1067 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1068 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1069 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1070 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1071 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1072 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1073 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1074 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1075 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1076 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1077 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1078 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1079 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1080 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1081 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1082 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1083 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1084 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1085 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1086 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1087 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1088 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1089 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1090 // CHECK1: omp_offload.failed: 1091 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1092 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1093 // CHECK1: omp_offload.cont: 1094 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1095 // CHECK1: omp_if.else: 1096 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1097 // CHECK1-NEXT: br label [[OMP_IF_END]] 1098 // CHECK1: omp_if.end: 1099 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1100 // CHECK1-NEXT: ret i32 [[TMP24]] 1101 // 1102 // 1103 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 1104 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1105 // CHECK1-NEXT: entry: 1106 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1107 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1108 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1109 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1110 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1111 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1112 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1113 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1114 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1115 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1116 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1117 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1118 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1119 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1120 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1121 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1122 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1123 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1124 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1125 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1126 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1127 // CHECK1-NEXT: ret void 1128 // 1129 // 1130 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 1131 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1132 // CHECK1-NEXT: entry: 1133 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1134 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1135 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1136 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1137 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1138 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1139 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1140 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1141 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1142 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1143 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1144 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1145 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1146 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1147 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1148 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1149 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1150 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1151 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1152 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1153 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 1154 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 1155 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1156 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1157 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1158 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 1159 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 1160 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 1161 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1162 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 1163 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 1164 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1165 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 1166 // CHECK1-NEXT: ret void 1167 // 1168 // 1169 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 1170 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1171 // CHECK1-NEXT: entry: 1172 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1173 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1174 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1175 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1176 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1177 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1178 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1179 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1180 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1181 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1182 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1183 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1184 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1185 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1186 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1187 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1188 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1189 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1190 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1191 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1192 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1193 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1194 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1195 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1196 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1197 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1198 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1199 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1200 // CHECK1-NEXT: ret void 1201 // 1202 // 1203 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1204 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1205 // CHECK1-NEXT: entry: 1206 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1207 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1209 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1210 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1211 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1212 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1213 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1214 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1215 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1216 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1217 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1218 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1219 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1220 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1221 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1222 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1223 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1224 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1225 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1226 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 1227 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1228 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1229 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 1230 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 1231 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 1232 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 1233 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 1234 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 1235 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1236 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1237 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 1238 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 1239 // CHECK1-NEXT: ret void 1240 // 1241 // 1242 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 1243 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1244 // CHECK1-NEXT: entry: 1245 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1246 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1247 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1248 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1249 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1250 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1251 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1252 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1253 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1254 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1255 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1256 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1257 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1258 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1259 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1260 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1261 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1262 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1263 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1264 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1265 // CHECK1-NEXT: ret void 1266 // 1267 // 1268 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1269 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1270 // CHECK1-NEXT: entry: 1271 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1272 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1273 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1274 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1275 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1276 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1277 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1278 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1279 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1280 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1281 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1282 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1283 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1284 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1285 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1286 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1287 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1288 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1289 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1290 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1291 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1292 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1293 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1294 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 1295 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 1296 // CHECK1-NEXT: ret void 1297 // 1298 // 1299 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1300 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { 1301 // CHECK1-NEXT: entry: 1302 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1303 // CHECK1-NEXT: ret void 1304 // 1305 // 1306 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi 1307 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1308 // CHECK2-NEXT: entry: 1309 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1310 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 1311 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 1312 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1313 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1314 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1315 // CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1316 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1317 // CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 1318 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 1319 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1320 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1321 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1322 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1323 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1324 // CHECK2-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 1325 // CHECK2-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 1326 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 1327 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 1328 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 1329 // CHECK2-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 1330 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 1331 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 1332 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 1333 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 1334 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1335 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1336 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1337 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 1338 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1339 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1340 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1341 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1342 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 1343 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1344 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1345 // CHECK2-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 1346 // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 1347 // CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 1348 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 1349 // CHECK2-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 1350 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 1351 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 1352 // CHECK2-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 1353 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 1354 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1355 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 1356 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 1357 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 1358 // CHECK2-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 1359 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1360 // CHECK2-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 1361 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1362 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1363 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 1364 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 1365 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1366 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1367 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 1368 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1369 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 1370 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1371 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1372 // CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1373 // CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1374 // CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1375 // CHECK2: omp_offload.failed: 1376 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 1377 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1378 // CHECK2: omp_offload.cont: 1379 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1380 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 1381 // CHECK2-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 1382 // CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 1383 // CHECK2-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 1384 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 1385 // CHECK2-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 1386 // CHECK2-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 1387 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 1388 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 1389 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1390 // CHECK2: omp_if.then: 1391 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 1392 // CHECK2-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 1393 // CHECK2-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 1394 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 1395 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 1396 // CHECK2-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 1397 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 1398 // CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8 1399 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 1400 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* 1401 // CHECK2-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 1402 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 1403 // CHECK2-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 1404 // CHECK2-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 1405 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 1406 // CHECK2-NEXT: store i8* null, i8** [[TMP38]], align 8 1407 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 1408 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 1409 // CHECK2-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1410 // CHECK2-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 1411 // CHECK2-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 1412 // CHECK2: omp_offload.failed10: 1413 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 1414 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT11]] 1415 // CHECK2: omp_offload.cont11: 1416 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 1417 // CHECK2: omp_if.else: 1418 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 1419 // CHECK2-NEXT: br label [[OMP_IF_END]] 1420 // CHECK2: omp_if.end: 1421 // CHECK2-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 1422 // CHECK2-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 1423 // CHECK2-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 1424 // CHECK2-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 1425 // CHECK2-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 1426 // CHECK2-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 1427 // CHECK2-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] 1428 // CHECK2: omp_if.then15: 1429 // CHECK2-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 1430 // CHECK2-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] 1431 // CHECK2-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 1432 // CHECK2-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1433 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP49]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i64 72, i1 false) 1434 // CHECK2-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 1435 // CHECK2-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 1436 // CHECK2-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8 1437 // CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 1438 // CHECK2-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 1439 // CHECK2-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8 1440 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 1441 // CHECK2-NEXT: store i8* null, i8** [[TMP54]], align 8 1442 // CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 1443 // CHECK2-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 1444 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 1445 // CHECK2-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 1446 // CHECK2-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 1447 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 1448 // CHECK2-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 1449 // CHECK2-NEXT: store i8* null, i8** [[TMP59]], align 8 1450 // CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 1451 // CHECK2-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64* 1452 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP61]], align 8 1453 // CHECK2-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 1454 // CHECK2-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64* 1455 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP63]], align 8 1456 // CHECK2-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 1457 // CHECK2-NEXT: store i8* null, i8** [[TMP64]], align 8 1458 // CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 1459 // CHECK2-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 1460 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP66]], align 8 1461 // CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 1462 // CHECK2-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 1463 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 1464 // CHECK2-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1465 // CHECK2-NEXT: store i64 [[TMP46]], i64* [[TMP69]], align 8 1466 // CHECK2-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 1467 // CHECK2-NEXT: store i8* null, i8** [[TMP70]], align 8 1468 // CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 1469 // CHECK2-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 1470 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 8 1471 // CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 1472 // CHECK2-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 1473 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 1474 // CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 1475 // CHECK2-NEXT: store i8* null, i8** [[TMP75]], align 8 1476 // CHECK2-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 1477 // CHECK2-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* 1478 // CHECK2-NEXT: store i64 5, i64* [[TMP77]], align 8 1479 // CHECK2-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 1480 // CHECK2-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 1481 // CHECK2-NEXT: store i64 5, i64* [[TMP79]], align 8 1482 // CHECK2-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 1483 // CHECK2-NEXT: store i8* null, i8** [[TMP80]], align 8 1484 // CHECK2-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 1485 // CHECK2-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 1486 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP82]], align 8 1487 // CHECK2-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 1488 // CHECK2-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i64* 1489 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP84]], align 8 1490 // CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 1491 // CHECK2-NEXT: store i8* null, i8** [[TMP85]], align 8 1492 // CHECK2-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 1493 // CHECK2-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 1494 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP87]], align 8 1495 // CHECK2-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 1496 // CHECK2-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 1497 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP89]], align 8 1498 // CHECK2-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 1499 // CHECK2-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 8 1500 // CHECK2-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 1501 // CHECK2-NEXT: store i8* null, i8** [[TMP91]], align 8 1502 // CHECK2-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 1503 // CHECK2-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 1504 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 8 1505 // CHECK2-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 1506 // CHECK2-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 1507 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 8 1508 // CHECK2-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 1509 // CHECK2-NEXT: store i8* null, i8** [[TMP96]], align 8 1510 // CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 1511 // CHECK2-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 1512 // CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1513 // CHECK2-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1514 // CHECK2-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 1515 // CHECK2-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 1516 // CHECK2: omp_offload.failed19: 1517 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 1518 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT20]] 1519 // CHECK2: omp_offload.cont20: 1520 // CHECK2-NEXT: br label [[OMP_IF_END22:%.*]] 1521 // CHECK2: omp_if.else21: 1522 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 1523 // CHECK2-NEXT: br label [[OMP_IF_END22]] 1524 // CHECK2: omp_if.end22: 1525 // CHECK2-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 1526 // CHECK2-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1527 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 1528 // CHECK2-NEXT: ret i32 [[TMP102]] 1529 // 1530 // 1531 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 1532 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] { 1533 // CHECK2-NEXT: entry: 1534 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1535 // CHECK2-NEXT: ret void 1536 // 1537 // 1538 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1539 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 1540 // CHECK2-NEXT: entry: 1541 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1542 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1543 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1544 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1545 // CHECK2-NEXT: ret void 1546 // 1547 // 1548 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. 1549 // CHECK2-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 1550 // CHECK2-NEXT: entry: 1551 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 1552 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 1553 // CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 1554 // CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 1555 // CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 1556 // CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 1557 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 1558 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 1559 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 1560 // CHECK2-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1561 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 1562 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1563 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 1564 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 1565 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 1566 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1567 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 1568 // CHECK2-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 1569 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 1570 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 1571 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 1572 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 1573 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 1574 // CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 1575 // CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 1576 // CHECK2-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 1577 // CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 1578 // CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 1579 // CHECK2-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 1580 // CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 1581 // CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1582 // CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 1583 // CHECK2: omp_offload.failed.i: 1584 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 1585 // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 1586 // CHECK2: .omp_outlined..1.exit: 1587 // CHECK2-NEXT: ret i32 0 1588 // 1589 // 1590 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 1591 // CHECK2-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 1592 // CHECK2-NEXT: entry: 1593 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1594 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1595 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1596 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1597 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1598 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1599 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1600 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1601 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1602 // CHECK2-NEXT: ret void 1603 // 1604 // 1605 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 1606 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 1607 // CHECK2-NEXT: entry: 1608 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1609 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1610 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1611 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1612 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1613 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1614 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1615 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1616 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1617 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1618 // CHECK2-NEXT: ret void 1619 // 1620 // 1621 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 1622 // CHECK2-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1623 // CHECK2-NEXT: entry: 1624 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1625 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1626 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1627 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1628 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 1629 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1630 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 1631 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1632 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1633 // CHECK2-NEXT: ret void 1634 // 1635 // 1636 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1637 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 1638 // CHECK2-NEXT: entry: 1639 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1640 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1641 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1642 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1643 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1644 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1645 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1646 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 1647 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 1648 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 1649 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 1650 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 1651 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1652 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1653 // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 1654 // CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 1655 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 1656 // CHECK2: .cancel.exit: 1657 // CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 1658 // CHECK2-NEXT: br label [[DOTCANCEL_CONTINUE]] 1659 // CHECK2: .cancel.continue: 1660 // CHECK2-NEXT: ret void 1661 // 1662 // 1663 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 1664 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 1665 // CHECK2-NEXT: entry: 1666 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1667 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1668 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1669 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1670 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1671 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1672 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1673 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1674 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1675 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1676 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 1677 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1678 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1679 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1680 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 1681 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1682 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 1683 // CHECK2-NEXT: ret void 1684 // 1685 // 1686 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1687 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 1688 // CHECK2-NEXT: entry: 1689 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1690 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1691 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1692 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1693 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1694 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1695 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1696 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1697 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1698 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1699 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1700 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1701 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1702 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 1703 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 1704 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1705 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1706 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1707 // CHECK2-NEXT: ret void 1708 // 1709 // 1710 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 1711 // CHECK2-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 1712 // CHECK2-NEXT: entry: 1713 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1714 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1715 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1716 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1717 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1718 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1719 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1720 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1721 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1722 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1723 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1724 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1725 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1726 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1727 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1728 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1729 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1730 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1731 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1732 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1733 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1734 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1735 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1736 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1737 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1738 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1739 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1740 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1741 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1742 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1743 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 1744 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1745 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 1746 // CHECK2-NEXT: ret void 1747 // 1748 // 1749 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 1750 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 1751 // CHECK2-NEXT: entry: 1752 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1753 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1754 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1755 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1756 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1757 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1758 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1759 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1760 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1761 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1762 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1763 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1764 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1765 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1766 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1767 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1768 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1769 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1770 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1771 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1772 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1773 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1774 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1775 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1776 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1777 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1778 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1779 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1780 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1781 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1782 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1783 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1784 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 1785 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1786 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1787 // CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 1788 // CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 1789 // CHECK2-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 1790 // CHECK2-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 1791 // CHECK2-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 1792 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1793 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1794 // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 1795 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1796 // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1797 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 1798 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1799 // CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 1800 // CHECK2-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 1801 // CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 1802 // CHECK2-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 1803 // CHECK2-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 1804 // CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 1805 // CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 1806 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 1807 // CHECK2-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 1808 // CHECK2-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 1809 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1810 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 1811 // CHECK2-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 1812 // CHECK2-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 1813 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1814 // CHECK2-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 1815 // CHECK2-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 1816 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 1817 // CHECK2-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 1818 // CHECK2-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 1819 // CHECK2-NEXT: ret void 1820 // 1821 // 1822 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari 1823 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1824 // CHECK2-NEXT: entry: 1825 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1826 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 1827 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1828 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1829 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1830 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1831 // CHECK2-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 1832 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1833 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1834 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1835 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1836 // CHECK2-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 1837 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1838 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1839 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1840 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1841 // CHECK2-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 1842 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1843 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1844 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1845 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1846 // CHECK2-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 1847 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1848 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1849 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1850 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1851 // CHECK2-NEXT: ret i32 [[TMP8]] 1852 // 1853 // 1854 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1855 // CHECK2-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1856 // CHECK2-NEXT: entry: 1857 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1858 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1859 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 1860 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1861 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1862 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1863 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1864 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1865 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1866 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1867 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1868 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1869 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1870 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1871 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1872 // CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1873 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1874 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1875 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1876 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1877 // CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1878 // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1879 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1880 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1881 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1882 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1883 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1884 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1885 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1886 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1887 // CHECK2: omp_if.then: 1888 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1889 // CHECK2-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1890 // CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1891 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1892 // CHECK2-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 1893 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1894 // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1895 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 1896 // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1897 // CHECK2-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1898 // CHECK2-NEXT: store double* [[A]], double** [[TMP14]], align 8 1899 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1900 // CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8 1901 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1902 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1903 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1904 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1905 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1906 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1907 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1908 // CHECK2-NEXT: store i8* null, i8** [[TMP20]], align 8 1909 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1910 // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 1911 // CHECK2-NEXT: store i64 2, i64* [[TMP22]], align 8 1912 // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1913 // CHECK2-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 1914 // CHECK2-NEXT: store i64 2, i64* [[TMP24]], align 8 1915 // CHECK2-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1916 // CHECK2-NEXT: store i8* null, i8** [[TMP25]], align 8 1917 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1918 // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 1919 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 1920 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1921 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1922 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1923 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1924 // CHECK2-NEXT: store i8* null, i8** [[TMP30]], align 8 1925 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1926 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1927 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 1928 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1929 // CHECK2-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1930 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 1931 // CHECK2-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1932 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 1933 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1934 // CHECK2-NEXT: store i8* null, i8** [[TMP36]], align 8 1935 // CHECK2-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1936 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1937 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1938 // CHECK2-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1939 // CHECK2-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1940 // CHECK2-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1941 // CHECK2: omp_offload.failed: 1942 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1943 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1944 // CHECK2: omp_offload.cont: 1945 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 1946 // CHECK2: omp_if.else: 1947 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1948 // CHECK2-NEXT: br label [[OMP_IF_END]] 1949 // CHECK2: omp_if.end: 1950 // CHECK2-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 1951 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 1952 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1953 // CHECK2-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1954 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 1955 // CHECK2-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 1956 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 1957 // CHECK2-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1958 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 1959 // CHECK2-NEXT: ret i32 [[ADD4]] 1960 // 1961 // 1962 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici 1963 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1964 // CHECK2-NEXT: entry: 1965 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1966 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 1967 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 1968 // CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1 1969 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1970 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1971 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1972 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1973 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1974 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1975 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1976 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1977 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1978 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 1979 // CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1 1980 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1981 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1982 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1983 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1984 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1985 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1986 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1987 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1988 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1989 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1990 // CHECK2-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1991 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1992 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1993 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1994 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1995 // CHECK2: omp_if.then: 1996 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1997 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1998 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1999 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2000 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 2001 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 2002 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2003 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8 2004 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2005 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2006 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 2007 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2008 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 2009 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 2010 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2011 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8 2012 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2013 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 2014 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 2015 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2016 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 2017 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 2018 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2019 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 2020 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2021 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 2022 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 2023 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2024 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 2025 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 2026 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2027 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8 2028 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2029 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2030 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2031 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2032 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2033 // CHECK2: omp_offload.failed: 2034 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 2035 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2036 // CHECK2: omp_offload.cont: 2037 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2038 // CHECK2: omp_if.else: 2039 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 2040 // CHECK2-NEXT: br label [[OMP_IF_END]] 2041 // CHECK2: omp_if.end: 2042 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 2043 // CHECK2-NEXT: ret i32 [[TMP31]] 2044 // 2045 // 2046 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2047 // CHECK2-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 2048 // CHECK2-NEXT: entry: 2049 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2050 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2051 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 2052 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2053 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2054 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2055 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 2056 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 2057 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 2058 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2059 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2060 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 2061 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2062 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2063 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 2064 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2065 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2066 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2067 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2068 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2069 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2070 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 2071 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2072 // CHECK2: omp_if.then: 2073 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2074 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 2075 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 2076 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2077 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 2078 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 2079 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2080 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8 2081 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2082 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 2083 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 2084 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2085 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2086 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 2087 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2088 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8 2089 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2090 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 2091 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 2092 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2093 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 2094 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 2095 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2096 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 2097 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2098 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2099 // CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2100 // CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2101 // CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2102 // CHECK2: omp_offload.failed: 2103 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 2104 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2105 // CHECK2: omp_offload.cont: 2106 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2107 // CHECK2: omp_if.else: 2108 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 2109 // CHECK2-NEXT: br label [[OMP_IF_END]] 2110 // CHECK2: omp_if.end: 2111 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 2112 // CHECK2-NEXT: ret i32 [[TMP24]] 2113 // 2114 // 2115 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 2116 // CHECK2-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2117 // CHECK2-NEXT: entry: 2118 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2119 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2120 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2121 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2122 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2123 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2124 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2125 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2126 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2127 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2128 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2129 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2130 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2131 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2132 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2133 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2134 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2135 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2136 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 2137 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 2138 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 2139 // CHECK2-NEXT: ret void 2140 // 2141 // 2142 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10 2143 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 2144 // CHECK2-NEXT: entry: 2145 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2146 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2147 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2148 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2149 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2150 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2151 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2152 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2153 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2154 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2155 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2156 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2157 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2158 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2159 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2160 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2161 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2162 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2163 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2164 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2165 // CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 2166 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 2167 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2168 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 2169 // CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2170 // CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 2171 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 2172 // CHECK2-NEXT: store double [[INC]], double* [[A4]], align 8 2173 // CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 2174 // CHECK2-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 2175 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 2176 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 2177 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 2178 // CHECK2-NEXT: ret void 2179 // 2180 // 2181 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 2182 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2183 // CHECK2-NEXT: entry: 2184 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2185 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2186 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2187 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2188 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2189 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2190 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2191 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2192 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2193 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2194 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2195 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2196 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2197 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2198 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2199 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2200 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2201 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 2202 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2203 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2204 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2205 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 2206 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2207 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 2208 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 2209 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 2210 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 2211 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 2212 // CHECK2-NEXT: ret void 2213 // 2214 // 2215 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..13 2216 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 2217 // CHECK2-NEXT: entry: 2218 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2219 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2220 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2221 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2222 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2223 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2224 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2225 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2226 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2227 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2228 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2229 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2230 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2231 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2232 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2233 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2234 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2235 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2236 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2237 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2238 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 2239 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2240 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2241 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 2242 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 2243 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 2244 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 2245 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 2246 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 2247 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 2248 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2249 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 2250 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 2251 // CHECK2-NEXT: ret void 2252 // 2253 // 2254 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 2255 // CHECK2-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2256 // CHECK2-NEXT: entry: 2257 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2258 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2259 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2260 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2261 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2262 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2263 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2264 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2265 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2266 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2267 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2268 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2269 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2270 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 2271 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2272 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2273 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2274 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 2275 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2276 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 2277 // CHECK2-NEXT: ret void 2278 // 2279 // 2280 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..16 2281 // CHECK2-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 2282 // CHECK2-NEXT: entry: 2283 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2284 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2285 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2286 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2287 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2288 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2289 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2290 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2291 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2292 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2293 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2294 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2295 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2296 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2297 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2298 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2299 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2300 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 2301 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2302 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2303 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 2304 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 2305 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2306 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 2307 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 2308 // CHECK2-NEXT: ret void 2309 // 2310 // 2311 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2312 // CHECK2-SAME: () #[[ATTR8:[0-9]+]] { 2313 // CHECK2-NEXT: entry: 2314 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 2315 // CHECK2-NEXT: ret void 2316 // 2317 // 2318 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 2319 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2320 // CHECK3-NEXT: entry: 2321 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2322 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2323 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2324 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 2325 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2326 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2327 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 2328 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2329 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 2330 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 2331 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2332 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2333 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2334 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2335 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2336 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 2337 // CHECK3-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 2338 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 2339 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 2340 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 2341 // CHECK3-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 2342 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 2343 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 2344 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 2345 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 2346 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2347 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2348 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2349 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2350 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2351 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2352 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2353 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 2354 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2355 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2356 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 2357 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 2358 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 2359 // CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 2360 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 2361 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 2362 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 2363 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 2364 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 2365 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 2366 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 2367 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 2368 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2369 // CHECK3-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 2370 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2371 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2372 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 2373 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 2374 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2375 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 2376 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 2377 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2378 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 2379 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2380 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2381 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2382 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2383 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2384 // CHECK3: omp_offload.failed: 2385 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 2386 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2387 // CHECK3: omp_offload.cont: 2388 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 2389 // CHECK3-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 2390 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 2391 // CHECK3-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 2392 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 2393 // CHECK3-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 2394 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 2395 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 2396 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 2397 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2398 // CHECK3: omp_if.then: 2399 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2400 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 2401 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 2402 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2403 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 2404 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 2405 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 2406 // CHECK3-NEXT: store i8* null, i8** [[TMP31]], align 4 2407 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 2408 // CHECK3-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* 2409 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 2410 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 2411 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 2412 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 2413 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 2414 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 2415 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2416 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2417 // CHECK3-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2418 // CHECK3-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 2419 // CHECK3-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 2420 // CHECK3: omp_offload.failed8: 2421 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 2422 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT9]] 2423 // CHECK3: omp_offload.cont9: 2424 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2425 // CHECK3: omp_if.else: 2426 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 2427 // CHECK3-NEXT: br label [[OMP_IF_END]] 2428 // CHECK3: omp_if.end: 2429 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 2430 // CHECK3-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 2431 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 2432 // CHECK3-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 2433 // CHECK3-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 2434 // CHECK3-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] 2435 // CHECK3: omp_if.then12: 2436 // CHECK3-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 2437 // CHECK3-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 2438 // CHECK3-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] 2439 // CHECK3-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 2440 // CHECK3-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 2441 // CHECK3-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2442 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i32 72, i1 false) 2443 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 2444 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 2445 // CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP51]], align 4 2446 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 2447 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 2448 // CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP53]], align 4 2449 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 2450 // CHECK3-NEXT: store i8* null, i8** [[TMP54]], align 4 2451 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 2452 // CHECK3-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 2453 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 2454 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 2455 // CHECK3-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 2456 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 2457 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 2458 // CHECK3-NEXT: store i8* null, i8** [[TMP59]], align 4 2459 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 2460 // CHECK3-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32* 2461 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP61]], align 4 2462 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 2463 // CHECK3-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 2464 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP63]], align 4 2465 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 2466 // CHECK3-NEXT: store i8* null, i8** [[TMP64]], align 4 2467 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 2468 // CHECK3-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 2469 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP66]], align 4 2470 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 2471 // CHECK3-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 2472 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 2473 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2474 // CHECK3-NEXT: store i64 [[TMP45]], i64* [[TMP69]], align 4 2475 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 2476 // CHECK3-NEXT: store i8* null, i8** [[TMP70]], align 4 2477 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 2478 // CHECK3-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 2479 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 4 2480 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 2481 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 2482 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 2483 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 2484 // CHECK3-NEXT: store i8* null, i8** [[TMP75]], align 4 2485 // CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 2486 // CHECK3-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* 2487 // CHECK3-NEXT: store i32 5, i32* [[TMP77]], align 4 2488 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 2489 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 2490 // CHECK3-NEXT: store i32 5, i32* [[TMP79]], align 4 2491 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 2492 // CHECK3-NEXT: store i8* null, i8** [[TMP80]], align 4 2493 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 2494 // CHECK3-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* 2495 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP82]], align 4 2496 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 2497 // CHECK3-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32* 2498 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP84]], align 4 2499 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 2500 // CHECK3-NEXT: store i8* null, i8** [[TMP85]], align 4 2501 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 2502 // CHECK3-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 2503 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP87]], align 4 2504 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 2505 // CHECK3-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 2506 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP89]], align 4 2507 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2508 // CHECK3-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 4 2509 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 2510 // CHECK3-NEXT: store i8* null, i8** [[TMP91]], align 4 2511 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 2512 // CHECK3-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 2513 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 4 2514 // CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 2515 // CHECK3-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 2516 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 4 2517 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 2518 // CHECK3-NEXT: store i8* null, i8** [[TMP96]], align 4 2519 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 2520 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 2521 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2522 // CHECK3-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2523 // CHECK3-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 2524 // CHECK3-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 2525 // CHECK3: omp_offload.failed16: 2526 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 2527 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] 2528 // CHECK3: omp_offload.cont17: 2529 // CHECK3-NEXT: br label [[OMP_IF_END19:%.*]] 2530 // CHECK3: omp_if.else18: 2531 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 2532 // CHECK3-NEXT: br label [[OMP_IF_END19]] 2533 // CHECK3: omp_if.end19: 2534 // CHECK3-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 2535 // CHECK3-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2536 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 2537 // CHECK3-NEXT: ret i32 [[TMP102]] 2538 // 2539 // 2540 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 2541 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 2542 // CHECK3-NEXT: entry: 2543 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2544 // CHECK3-NEXT: ret void 2545 // 2546 // 2547 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2548 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 2549 // CHECK3-NEXT: entry: 2550 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2551 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2552 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2553 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2554 // CHECK3-NEXT: ret void 2555 // 2556 // 2557 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2558 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2559 // CHECK3-NEXT: entry: 2560 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2561 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 2562 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 2563 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 2564 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 2565 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 2566 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2567 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 2568 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2569 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2570 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2571 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2572 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2573 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2574 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2575 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 2576 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2577 // CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2578 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 2579 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 2580 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 2581 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2582 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 2583 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 2584 // CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 2585 // CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 2586 // CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 2587 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 2588 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 2589 // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 2590 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2591 // CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2592 // CHECK3: omp_offload.failed.i: 2593 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 2594 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2595 // CHECK3: .omp_outlined..1.exit: 2596 // CHECK3-NEXT: ret i32 0 2597 // 2598 // 2599 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 2600 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { 2601 // CHECK3-NEXT: entry: 2602 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2603 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2604 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2605 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2606 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2607 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2608 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2609 // CHECK3-NEXT: ret void 2610 // 2611 // 2612 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2613 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 2614 // CHECK3-NEXT: entry: 2615 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2616 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2617 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2618 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2619 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2620 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2621 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2622 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2623 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2624 // CHECK3-NEXT: ret void 2625 // 2626 // 2627 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 2628 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2629 // CHECK3-NEXT: entry: 2630 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2631 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2632 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2633 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2634 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2635 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2636 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2637 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2638 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2639 // CHECK3-NEXT: ret void 2640 // 2641 // 2642 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2643 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 2644 // CHECK3-NEXT: entry: 2645 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2646 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2647 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2648 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2649 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2650 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2651 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2652 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2653 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2654 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 2655 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2656 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 2657 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2658 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2659 // CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 2660 // CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 2661 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 2662 // CHECK3: .cancel.exit: 2663 // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 2664 // CHECK3-NEXT: br label [[DOTCANCEL_CONTINUE]] 2665 // CHECK3: .cancel.continue: 2666 // CHECK3-NEXT: ret void 2667 // 2668 // 2669 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 2670 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 2671 // CHECK3-NEXT: entry: 2672 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2673 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2674 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2675 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2676 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2677 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2678 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2679 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2680 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2681 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2682 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2683 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2684 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2685 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2686 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2687 // CHECK3-NEXT: ret void 2688 // 2689 // 2690 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 2691 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 2692 // CHECK3-NEXT: entry: 2693 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2694 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2695 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2696 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2697 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2698 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2699 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2700 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2701 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2702 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2703 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2704 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2705 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 2706 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 2707 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 2708 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 2709 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 2710 // CHECK3-NEXT: ret void 2711 // 2712 // 2713 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 2714 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 2715 // CHECK3-NEXT: entry: 2716 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2717 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2718 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2719 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2720 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2721 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2722 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2723 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2724 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2725 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2726 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2727 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2728 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2729 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2730 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2731 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2732 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2733 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2734 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2735 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2736 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2737 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2738 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2739 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2740 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2741 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2742 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2743 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2744 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2745 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2746 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2747 // CHECK3-NEXT: ret void 2748 // 2749 // 2750 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 2751 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 2752 // CHECK3-NEXT: entry: 2753 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2754 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2755 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2756 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2757 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2758 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2759 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2760 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2761 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2762 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2763 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2764 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2765 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2766 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2767 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2768 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2769 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2770 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2771 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2772 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2773 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2774 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2775 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2776 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2777 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2778 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2779 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2780 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2781 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2782 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2783 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2784 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 2785 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2786 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2787 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2788 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 2789 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 2790 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 2791 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 2792 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2793 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2794 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 2795 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 2796 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 2797 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 2798 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2799 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 2800 // CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 2801 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 2802 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 2803 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 2804 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 2805 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 2806 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 2807 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 2808 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 2809 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2810 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 2811 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 2812 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 2813 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2814 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 2815 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 2816 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 2817 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 2818 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 2819 // CHECK3-NEXT: ret void 2820 // 2821 // 2822 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2823 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2824 // CHECK3-NEXT: entry: 2825 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2826 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2827 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2828 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2829 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2830 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2831 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2832 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2833 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2834 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2835 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2836 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2837 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2838 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2839 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2840 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2841 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2842 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2843 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2844 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2845 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2846 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2847 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2848 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2849 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2850 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2851 // CHECK3-NEXT: ret i32 [[TMP8]] 2852 // 2853 // 2854 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2855 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2856 // CHECK3-NEXT: entry: 2857 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2858 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2859 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2860 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2861 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2862 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2863 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2864 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2865 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2866 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2867 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2868 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2869 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2870 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2871 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2872 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 2873 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2874 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2875 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2876 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2877 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2878 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2879 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 2880 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 2881 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 2882 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2883 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 2884 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2885 // CHECK3: omp_if.then: 2886 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2887 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 2888 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 2889 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 2890 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2891 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 2892 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2893 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 2894 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 2895 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2896 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 2897 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 2898 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2899 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 2900 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2901 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 2902 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 2903 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2904 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 2905 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 2906 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2907 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 2908 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2909 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 2910 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 2911 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2912 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 2913 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 2914 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2915 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 2916 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2917 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2918 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 2919 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2920 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 2921 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 2922 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2923 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 2924 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2925 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 2926 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 2927 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2928 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 2929 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 2930 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2931 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 2932 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2933 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 2934 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2935 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2936 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2937 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2938 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 2939 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2940 // CHECK3: omp_offload.failed: 2941 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 2942 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2943 // CHECK3: omp_offload.cont: 2944 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2945 // CHECK3: omp_if.else: 2946 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 2947 // CHECK3-NEXT: br label [[OMP_IF_END]] 2948 // CHECK3: omp_if.end: 2949 // CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 2950 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 2951 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 2952 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 2953 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 2954 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 2955 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 2956 // CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2957 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 2958 // CHECK3-NEXT: ret i32 [[ADD3]] 2959 // 2960 // 2961 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 2962 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2963 // CHECK3-NEXT: entry: 2964 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2965 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2966 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2967 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 2968 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2969 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2970 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2971 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 2972 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2973 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2974 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2975 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2976 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2977 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2978 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 2979 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2980 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2981 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2982 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2983 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2984 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 2985 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2986 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 2987 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 2988 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 2989 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 2990 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2991 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 2992 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2993 // CHECK3: omp_if.then: 2994 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2995 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2996 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 2997 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2998 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 2999 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3000 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3001 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 3002 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3003 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3004 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3005 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3006 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 3007 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 3008 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3009 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 3010 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3011 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 3012 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 3013 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3014 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 3015 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 3016 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3017 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 3018 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3019 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 3020 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 3021 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3022 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 3023 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 3024 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3025 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 3026 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3027 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3028 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3029 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3030 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3031 // CHECK3: omp_offload.failed: 3032 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3033 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3034 // CHECK3: omp_offload.cont: 3035 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3036 // CHECK3: omp_if.else: 3037 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3038 // CHECK3-NEXT: br label [[OMP_IF_END]] 3039 // CHECK3: omp_if.end: 3040 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 3041 // CHECK3-NEXT: ret i32 [[TMP31]] 3042 // 3043 // 3044 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3045 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 3046 // CHECK3-NEXT: entry: 3047 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3048 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3049 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3050 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3051 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3052 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3053 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3054 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3055 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3056 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3057 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3058 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3059 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3060 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3061 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3062 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3063 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3064 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3065 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3066 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3067 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3068 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3069 // CHECK3: omp_if.then: 3070 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3071 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 3072 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 3073 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3074 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3075 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3076 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3077 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 3078 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3079 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 3080 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 3081 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3082 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3083 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3084 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3085 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 3086 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3087 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3088 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 3089 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3090 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3091 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 3092 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3093 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3094 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3095 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3096 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3097 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3098 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3099 // CHECK3: omp_offload.failed: 3100 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3101 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3102 // CHECK3: omp_offload.cont: 3103 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3104 // CHECK3: omp_if.else: 3105 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3106 // CHECK3-NEXT: br label [[OMP_IF_END]] 3107 // CHECK3: omp_if.end: 3108 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 3109 // CHECK3-NEXT: ret i32 [[TMP24]] 3110 // 3111 // 3112 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 3113 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3114 // CHECK3-NEXT: entry: 3115 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3116 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3117 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3118 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3119 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3120 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3121 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3122 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3123 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3124 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3125 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3126 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3127 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3128 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3129 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3130 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3131 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3132 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3133 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3134 // CHECK3-NEXT: ret void 3135 // 3136 // 3137 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 3138 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3139 // CHECK3-NEXT: entry: 3140 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3141 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3142 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3143 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3144 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3145 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3146 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3147 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3148 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3149 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3150 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3151 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3152 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3153 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3154 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3155 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3156 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3157 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3158 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3159 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 3160 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3161 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3162 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 3163 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3164 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 3165 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 3166 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 4 3167 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 3168 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 3169 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 3170 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3171 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 3172 // CHECK3-NEXT: ret void 3173 // 3174 // 3175 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 3176 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3177 // CHECK3-NEXT: entry: 3178 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3179 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3180 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3181 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3182 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3183 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3184 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3185 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3186 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3187 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3188 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3189 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3190 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3191 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3192 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3193 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3194 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3195 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3196 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3197 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 3198 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3199 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 3200 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3201 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 3202 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3203 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 3204 // CHECK3-NEXT: ret void 3205 // 3206 // 3207 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 3208 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3209 // CHECK3-NEXT: entry: 3210 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3211 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3212 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3213 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3214 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3215 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3216 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3217 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3218 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3219 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3220 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3221 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3222 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3223 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3224 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3225 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3226 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3227 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3228 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3229 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 3230 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3231 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3232 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 3233 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 3234 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 3235 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 3236 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 3237 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 3238 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3239 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3240 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 3241 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 3242 // CHECK3-NEXT: ret void 3243 // 3244 // 3245 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 3246 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3247 // CHECK3-NEXT: entry: 3248 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3249 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3250 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3251 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3252 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3253 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3254 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3255 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3256 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3257 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3258 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3259 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3260 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3261 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3262 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3263 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3264 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3265 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3266 // CHECK3-NEXT: ret void 3267 // 3268 // 3269 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 3270 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3271 // CHECK3-NEXT: entry: 3272 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3273 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3274 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3275 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3276 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3277 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3278 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3279 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3280 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3281 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3282 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3283 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3284 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3285 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3286 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3287 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3288 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 3289 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3290 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3291 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3292 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3293 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3294 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 3295 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 3296 // CHECK3-NEXT: ret void 3297 // 3298 // 3299 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3300 // CHECK3-SAME: () #[[ATTR8:[0-9]+]] { 3301 // CHECK3-NEXT: entry: 3302 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3303 // CHECK3-NEXT: ret void 3304 // 3305 // 3306 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi 3307 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3308 // CHECK4-NEXT: entry: 3309 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3310 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 3311 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 3312 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3313 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3314 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3315 // CHECK4-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3316 // CHECK4-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3317 // CHECK4-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 3318 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 3319 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3320 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3321 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 3322 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 3323 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 3324 // CHECK4-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 3325 // CHECK4-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 3326 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 3327 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 3328 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 3329 // CHECK4-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 3330 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 3331 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 3332 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 3333 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 3334 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 3335 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3336 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 3337 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 3338 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3339 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3340 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3341 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 3342 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3343 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 3344 // CHECK4-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 3345 // CHECK4-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 3346 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 3347 // CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 3348 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 3349 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 3350 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 3351 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 3352 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 3353 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 3354 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 3355 // CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 3356 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3357 // CHECK4-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 3358 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3359 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3360 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 3361 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 3362 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3363 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 3364 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 3365 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3366 // CHECK4-NEXT: store i8* null, i8** [[TMP17]], align 4 3367 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3368 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3369 // CHECK4-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3370 // CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 3371 // CHECK4-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3372 // CHECK4: omp_offload.failed: 3373 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 3374 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 3375 // CHECK4: omp_offload.cont: 3376 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 3377 // CHECK4-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 3378 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 3379 // CHECK4-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 3380 // CHECK4-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 3381 // CHECK4-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 3382 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 3383 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 3384 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 3385 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3386 // CHECK4: omp_if.then: 3387 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3388 // CHECK4-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 3389 // CHECK4-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 3390 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3391 // CHECK4-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 3392 // CHECK4-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 3393 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 3394 // CHECK4-NEXT: store i8* null, i8** [[TMP31]], align 4 3395 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 3396 // CHECK4-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* 3397 // CHECK4-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 3398 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 3399 // CHECK4-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 3400 // CHECK4-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 3401 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 3402 // CHECK4-NEXT: store i8* null, i8** [[TMP36]], align 4 3403 // CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3404 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3405 // CHECK4-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3406 // CHECK4-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 3407 // CHECK4-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 3408 // CHECK4: omp_offload.failed8: 3409 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 3410 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT9]] 3411 // CHECK4: omp_offload.cont9: 3412 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 3413 // CHECK4: omp_if.else: 3414 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 3415 // CHECK4-NEXT: br label [[OMP_IF_END]] 3416 // CHECK4: omp_if.end: 3417 // CHECK4-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 3418 // CHECK4-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 3419 // CHECK4-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 3420 // CHECK4-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 3421 // CHECK4-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 3422 // CHECK4-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] 3423 // CHECK4: omp_if.then12: 3424 // CHECK4-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 3425 // CHECK4-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 3426 // CHECK4-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] 3427 // CHECK4-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 3428 // CHECK4-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 3429 // CHECK4-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3430 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i32 72, i1 false) 3431 // CHECK4-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 3432 // CHECK4-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 3433 // CHECK4-NEXT: store i32 [[TMP42]], i32* [[TMP51]], align 4 3434 // CHECK4-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 3435 // CHECK4-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 3436 // CHECK4-NEXT: store i32 [[TMP42]], i32* [[TMP53]], align 4 3437 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 3438 // CHECK4-NEXT: store i8* null, i8** [[TMP54]], align 4 3439 // CHECK4-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 3440 // CHECK4-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 3441 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 3442 // CHECK4-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 3443 // CHECK4-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 3444 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 3445 // CHECK4-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 3446 // CHECK4-NEXT: store i8* null, i8** [[TMP59]], align 4 3447 // CHECK4-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 3448 // CHECK4-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32* 3449 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP61]], align 4 3450 // CHECK4-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 3451 // CHECK4-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 3452 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP63]], align 4 3453 // CHECK4-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 3454 // CHECK4-NEXT: store i8* null, i8** [[TMP64]], align 4 3455 // CHECK4-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 3456 // CHECK4-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 3457 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP66]], align 4 3458 // CHECK4-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 3459 // CHECK4-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 3460 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 3461 // CHECK4-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3462 // CHECK4-NEXT: store i64 [[TMP45]], i64* [[TMP69]], align 4 3463 // CHECK4-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 3464 // CHECK4-NEXT: store i8* null, i8** [[TMP70]], align 4 3465 // CHECK4-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 3466 // CHECK4-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 3467 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 4 3468 // CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 3469 // CHECK4-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 3470 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 3471 // CHECK4-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 3472 // CHECK4-NEXT: store i8* null, i8** [[TMP75]], align 4 3473 // CHECK4-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 3474 // CHECK4-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* 3475 // CHECK4-NEXT: store i32 5, i32* [[TMP77]], align 4 3476 // CHECK4-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 3477 // CHECK4-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 3478 // CHECK4-NEXT: store i32 5, i32* [[TMP79]], align 4 3479 // CHECK4-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 3480 // CHECK4-NEXT: store i8* null, i8** [[TMP80]], align 4 3481 // CHECK4-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 3482 // CHECK4-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* 3483 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP82]], align 4 3484 // CHECK4-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 3485 // CHECK4-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32* 3486 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP84]], align 4 3487 // CHECK4-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 3488 // CHECK4-NEXT: store i8* null, i8** [[TMP85]], align 4 3489 // CHECK4-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 3490 // CHECK4-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 3491 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP87]], align 4 3492 // CHECK4-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 3493 // CHECK4-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 3494 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP89]], align 4 3495 // CHECK4-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3496 // CHECK4-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 4 3497 // CHECK4-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 3498 // CHECK4-NEXT: store i8* null, i8** [[TMP91]], align 4 3499 // CHECK4-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 3500 // CHECK4-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 3501 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 4 3502 // CHECK4-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 3503 // CHECK4-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 3504 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 4 3505 // CHECK4-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 3506 // CHECK4-NEXT: store i8* null, i8** [[TMP96]], align 4 3507 // CHECK4-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 3508 // CHECK4-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 3509 // CHECK4-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3510 // CHECK4-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3511 // CHECK4-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 3512 // CHECK4-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 3513 // CHECK4: omp_offload.failed16: 3514 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 3515 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT17]] 3516 // CHECK4: omp_offload.cont17: 3517 // CHECK4-NEXT: br label [[OMP_IF_END19:%.*]] 3518 // CHECK4: omp_if.else18: 3519 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 3520 // CHECK4-NEXT: br label [[OMP_IF_END19]] 3521 // CHECK4: omp_if.end19: 3522 // CHECK4-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 3523 // CHECK4-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3524 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 3525 // CHECK4-NEXT: ret i32 [[TMP102]] 3526 // 3527 // 3528 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 3529 // CHECK4-SAME: () #[[ATTR2:[0-9]+]] { 3530 // CHECK4-NEXT: entry: 3531 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 3532 // CHECK4-NEXT: ret void 3533 // 3534 // 3535 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 3536 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 3537 // CHECK4-NEXT: entry: 3538 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3539 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3540 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3541 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3542 // CHECK4-NEXT: ret void 3543 // 3544 // 3545 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. 3546 // CHECK4-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 3547 // CHECK4-NEXT: entry: 3548 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 3549 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 3550 // CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 3551 // CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 3552 // CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 3553 // CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 3554 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 3555 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 3556 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 3557 // CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 3558 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 3559 // CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 3560 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 3561 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 3562 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 3563 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 3564 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 3565 // CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 3566 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 3567 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 3568 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 3569 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 3570 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 3571 // CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 3572 // CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 3573 // CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 3574 // CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 3575 // CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 3576 // CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 3577 // CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 3578 // CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 3579 // CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 3580 // CHECK4: omp_offload.failed.i: 3581 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 3582 // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 3583 // CHECK4: .omp_outlined..1.exit: 3584 // CHECK4-NEXT: ret i32 0 3585 // 3586 // 3587 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 3588 // CHECK4-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { 3589 // CHECK4-NEXT: entry: 3590 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3591 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3592 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3593 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3594 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3595 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3596 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3597 // CHECK4-NEXT: ret void 3598 // 3599 // 3600 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 3601 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 3602 // CHECK4-NEXT: entry: 3603 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3604 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3605 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3606 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3607 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3608 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3609 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3610 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3611 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3612 // CHECK4-NEXT: ret void 3613 // 3614 // 3615 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 3616 // CHECK4-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3617 // CHECK4-NEXT: entry: 3618 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3619 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3620 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3621 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3622 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3623 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3624 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3625 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3626 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3627 // CHECK4-NEXT: ret void 3628 // 3629 // 3630 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 3631 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 3632 // CHECK4-NEXT: entry: 3633 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3634 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3635 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3636 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3637 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3638 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3639 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3640 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3641 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3642 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 3643 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 3644 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 3645 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3646 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3647 // CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 3648 // CHECK4-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 3649 // CHECK4-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 3650 // CHECK4: .cancel.exit: 3651 // CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 3652 // CHECK4-NEXT: br label [[DOTCANCEL_CONTINUE]] 3653 // CHECK4: .cancel.continue: 3654 // CHECK4-NEXT: ret void 3655 // 3656 // 3657 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 3658 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 3659 // CHECK4-NEXT: entry: 3660 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3661 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3662 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3663 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3664 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3665 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3666 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3667 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3668 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3669 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3670 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3671 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3672 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3673 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3674 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 3675 // CHECK4-NEXT: ret void 3676 // 3677 // 3678 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 3679 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 3680 // CHECK4-NEXT: entry: 3681 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3682 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3683 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3684 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3685 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3686 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3687 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3688 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3689 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3690 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3691 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3692 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3693 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 3694 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 3695 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3696 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3697 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3698 // CHECK4-NEXT: ret void 3699 // 3700 // 3701 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 3702 // CHECK4-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 3703 // CHECK4-NEXT: entry: 3704 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3705 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3706 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3707 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3708 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3709 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3710 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3711 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3712 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3713 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3714 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3715 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3716 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3717 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3718 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3719 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3720 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3721 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3722 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3723 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3724 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3725 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3726 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3727 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3728 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3729 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3730 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3731 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3732 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 3733 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 3734 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 3735 // CHECK4-NEXT: ret void 3736 // 3737 // 3738 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 3739 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 3740 // CHECK4-NEXT: entry: 3741 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3742 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3743 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3744 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3745 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3746 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3747 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3748 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3749 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3750 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3751 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3752 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3753 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3754 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3755 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3756 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3757 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3758 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3759 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3760 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3761 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3762 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3763 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3764 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3765 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3766 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3767 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3768 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3769 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3770 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3771 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3772 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 3773 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3774 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 3775 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 3776 // CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 3777 // CHECK4-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 3778 // CHECK4-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 3779 // CHECK4-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 3780 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 3781 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3782 // CHECK4-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 3783 // CHECK4-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 3784 // CHECK4-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 3785 // CHECK4-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 3786 // CHECK4-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 3787 // CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 3788 // CHECK4-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 3789 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 3790 // CHECK4-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 3791 // CHECK4-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 3792 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 3793 // CHECK4-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 3794 // CHECK4-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 3795 // CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 3796 // CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 3797 // CHECK4-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 3798 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 3799 // CHECK4-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 3800 // CHECK4-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 3801 // CHECK4-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 3802 // CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 3803 // CHECK4-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 3804 // CHECK4-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 3805 // CHECK4-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 3806 // CHECK4-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 3807 // CHECK4-NEXT: ret void 3808 // 3809 // 3810 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari 3811 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3812 // CHECK4-NEXT: entry: 3813 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3814 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 3815 // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3816 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3817 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 3818 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3819 // CHECK4-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 3820 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3821 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3822 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3823 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3824 // CHECK4-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 3825 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3826 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3827 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3828 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3829 // CHECK4-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 3830 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3831 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3832 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3833 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3834 // CHECK4-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 3835 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3836 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 3837 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 3838 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 3839 // CHECK4-NEXT: ret i32 [[TMP8]] 3840 // 3841 // 3842 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3843 // CHECK4-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3844 // CHECK4-NEXT: entry: 3845 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3846 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3847 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 3848 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3849 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3850 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3851 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 3852 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 3853 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 3854 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 3855 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3856 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3857 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3858 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3859 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3860 // CHECK4-NEXT: store i32 [[ADD]], i32* [[B]], align 4 3861 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3862 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3863 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3864 // CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 3865 // CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 3866 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3867 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 3868 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3869 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3870 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3871 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3872 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3873 // CHECK4: omp_if.then: 3874 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3875 // CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3876 // CHECK4-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3877 // CHECK4-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3878 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 3879 // CHECK4-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 3880 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3881 // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 3882 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 3883 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3884 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 3885 // CHECK4-NEXT: store double* [[A]], double** [[TMP14]], align 4 3886 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3887 // CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4 3888 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3889 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 3890 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 3891 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3892 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 3893 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 3894 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3895 // CHECK4-NEXT: store i8* null, i8** [[TMP20]], align 4 3896 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3897 // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 3898 // CHECK4-NEXT: store i32 2, i32* [[TMP22]], align 4 3899 // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3900 // CHECK4-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 3901 // CHECK4-NEXT: store i32 2, i32* [[TMP24]], align 4 3902 // CHECK4-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3903 // CHECK4-NEXT: store i8* null, i8** [[TMP25]], align 4 3904 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3905 // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 3906 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 3907 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3908 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 3909 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 3910 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3911 // CHECK4-NEXT: store i8* null, i8** [[TMP30]], align 4 3912 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3913 // CHECK4-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 3914 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 3915 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3916 // CHECK4-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 3917 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 3918 // CHECK4-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3919 // CHECK4-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 3920 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3921 // CHECK4-NEXT: store i8* null, i8** [[TMP36]], align 4 3922 // CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3923 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3924 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3925 // CHECK4-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3926 // CHECK4-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 3927 // CHECK4-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3928 // CHECK4: omp_offload.failed: 3929 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 3930 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 3931 // CHECK4: omp_offload.cont: 3932 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 3933 // CHECK4: omp_if.else: 3934 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 3935 // CHECK4-NEXT: br label [[OMP_IF_END]] 3936 // CHECK4: omp_if.end: 3937 // CHECK4-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 3938 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 3939 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3940 // CHECK4-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 3941 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 3942 // CHECK4-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 3943 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 3944 // CHECK4-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3945 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 3946 // CHECK4-NEXT: ret i32 [[ADD3]] 3947 // 3948 // 3949 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici 3950 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 3951 // CHECK4-NEXT: entry: 3952 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3953 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 3954 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 3955 // CHECK4-NEXT: [[AAA:%.*]] = alloca i8, align 1 3956 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3957 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3958 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3959 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3960 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 3961 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 3962 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 3963 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3964 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 3965 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 3966 // CHECK4-NEXT: store i8 0, i8* [[AAA]], align 1 3967 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3968 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3969 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3970 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3971 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3972 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3973 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3974 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 3975 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3976 // CHECK4-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 3977 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3978 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3979 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3980 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3981 // CHECK4: omp_if.then: 3982 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3983 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3984 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3985 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3986 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3987 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3988 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3989 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4 3990 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3991 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3992 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3993 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3994 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 3995 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 3996 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3997 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4 3998 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3999 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 4000 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 4001 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4002 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 4003 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 4004 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4005 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 4006 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4007 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 4008 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 4009 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4010 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 4011 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 4012 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4013 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4 4014 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4015 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4016 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4017 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 4018 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4019 // CHECK4: omp_offload.failed: 4020 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4021 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 4022 // CHECK4: omp_offload.cont: 4023 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 4024 // CHECK4: omp_if.else: 4025 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4026 // CHECK4-NEXT: br label [[OMP_IF_END]] 4027 // CHECK4: omp_if.end: 4028 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 4029 // CHECK4-NEXT: ret i32 [[TMP31]] 4030 // 4031 // 4032 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4033 // CHECK4-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 4034 // CHECK4-NEXT: entry: 4035 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4036 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 4037 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 4038 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4039 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4040 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4041 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4042 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4043 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4044 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4045 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 4046 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 4047 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4048 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4049 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4050 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4051 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4052 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4053 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4054 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4055 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4056 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4057 // CHECK4: omp_if.then: 4058 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4059 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4060 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 4061 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4062 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4063 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4064 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4065 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4 4066 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4067 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 4068 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 4069 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4070 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4071 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4072 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4073 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4 4074 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4075 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 4076 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 4077 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4078 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 4079 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 4080 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4081 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 4082 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4083 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4084 // CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4085 // CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4086 // CHECK4-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4087 // CHECK4: omp_offload.failed: 4088 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4089 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 4090 // CHECK4: omp_offload.cont: 4091 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 4092 // CHECK4: omp_if.else: 4093 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4094 // CHECK4-NEXT: br label [[OMP_IF_END]] 4095 // CHECK4: omp_if.end: 4096 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 4097 // CHECK4-NEXT: ret i32 [[TMP24]] 4098 // 4099 // 4100 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 4101 // CHECK4-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 4102 // CHECK4-NEXT: entry: 4103 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4104 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4105 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4106 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4107 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4108 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4109 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4110 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4111 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4112 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4113 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4114 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4115 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4116 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4117 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4118 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4119 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4120 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4121 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 4122 // CHECK4-NEXT: ret void 4123 // 4124 // 4125 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..10 4126 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 4127 // CHECK4-NEXT: entry: 4128 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4129 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4130 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4131 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4132 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4133 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4134 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4135 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4136 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4137 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4138 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4139 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4140 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4141 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4142 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4143 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4144 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4145 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4146 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4147 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 4148 // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4149 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4150 // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4 4151 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4152 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 4153 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 4154 // CHECK4-NEXT: store double [[INC]], double* [[A3]], align 4 4155 // CHECK4-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 4156 // CHECK4-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 4157 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 4158 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4159 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 4160 // CHECK4-NEXT: ret void 4161 // 4162 // 4163 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 4164 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4165 // CHECK4-NEXT: entry: 4166 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4167 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4168 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4169 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4170 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4171 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4172 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4173 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4174 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4175 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4176 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4177 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4178 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4179 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4180 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4181 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4182 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4183 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4184 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4185 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 4186 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4187 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 4188 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4189 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 4190 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4191 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 4192 // CHECK4-NEXT: ret void 4193 // 4194 // 4195 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..13 4196 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 4197 // CHECK4-NEXT: entry: 4198 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4199 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4200 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4201 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4202 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4203 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4204 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4205 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4206 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4207 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4208 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4209 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4210 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4211 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4212 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4213 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4214 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4215 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4216 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4217 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 4218 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4219 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4220 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 4221 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 4222 // CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 4223 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 4224 // CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 4225 // CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 4226 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4227 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4228 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 4229 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 4230 // CHECK4-NEXT: ret void 4231 // 4232 // 4233 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 4234 // CHECK4-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4235 // CHECK4-NEXT: entry: 4236 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4237 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4238 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4239 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4240 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4241 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4242 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4243 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4244 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4245 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4246 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4247 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4248 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4249 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4250 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4251 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 4252 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4253 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 4254 // CHECK4-NEXT: ret void 4255 // 4256 // 4257 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..16 4258 // CHECK4-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 4259 // CHECK4-NEXT: entry: 4260 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4261 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4262 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4263 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4264 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4265 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4266 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4267 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4268 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4269 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4270 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4271 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4272 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4273 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4274 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4275 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4276 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 4277 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 4278 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 4279 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 4280 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4281 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4282 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 4283 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 4284 // CHECK4-NEXT: ret void 4285 // 4286 // 4287 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4288 // CHECK4-SAME: () #[[ATTR8:[0-9]+]] { 4289 // CHECK4-NEXT: entry: 4290 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 4291 // CHECK4-NEXT: ret void 4292 // 4293 // 4294 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 4295 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 4296 // CHECK9-NEXT: entry: 4297 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4298 // CHECK9-NEXT: ret void 4299 // 4300 // 4301 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 4302 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 4303 // CHECK9-NEXT: entry: 4304 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4305 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4306 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4307 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4308 // CHECK9-NEXT: ret void 4309 // 4310 // 4311 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 4312 // CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4313 // CHECK9-NEXT: entry: 4314 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4315 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4316 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4317 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4318 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4319 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4320 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4321 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4322 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 4323 // CHECK9-NEXT: ret void 4324 // 4325 // 4326 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 4327 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 4328 // CHECK9-NEXT: entry: 4329 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4330 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4331 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4332 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4333 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4334 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4335 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4336 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4337 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 4338 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 4339 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 4340 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 4341 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4342 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4343 // CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 4344 // CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 4345 // CHECK9-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 4346 // CHECK9: .cancel.exit: 4347 // CHECK9-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 4348 // CHECK9-NEXT: br label [[DOTCANCEL_CONTINUE]] 4349 // CHECK9: .cancel.continue: 4350 // CHECK9-NEXT: ret void 4351 // 4352 // 4353 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 4354 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4355 // CHECK9-NEXT: entry: 4356 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4357 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4358 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4359 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4360 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4361 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4362 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4363 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4364 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4365 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4366 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 4367 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4368 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4369 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4370 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 4371 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4372 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 4373 // CHECK9-NEXT: ret void 4374 // 4375 // 4376 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 4377 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 4378 // CHECK9-NEXT: entry: 4379 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4380 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4381 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4382 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4383 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4384 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4385 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4386 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4387 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4388 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4389 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4390 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4391 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4392 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 4393 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 4394 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4395 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4396 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 4397 // CHECK9-NEXT: ret void 4398 // 4399 // 4400 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 4401 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 4402 // CHECK9-NEXT: entry: 4403 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4404 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4405 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4406 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4407 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4408 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4409 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4410 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4411 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4412 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4413 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4414 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4415 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4416 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4417 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4418 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4419 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4420 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4421 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4422 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4423 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4424 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4425 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4426 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4427 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4428 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4429 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4430 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4431 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4432 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4433 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 4434 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 4435 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 4436 // CHECK9-NEXT: ret void 4437 // 4438 // 4439 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 4440 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 4441 // CHECK9-NEXT: entry: 4442 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4443 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4444 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4445 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4446 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4447 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4448 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4449 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4450 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4451 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4452 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4453 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4454 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4455 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4456 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4457 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4458 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4459 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4460 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4461 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4462 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4463 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4464 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4465 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4466 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4467 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4468 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4469 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4470 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4471 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4472 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4473 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4474 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 4475 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4476 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 4477 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 4478 // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 4479 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 4480 // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 4481 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 4482 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 4483 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 4484 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 4485 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 4486 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 4487 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 4488 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 4489 // CHECK9-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 4490 // CHECK9-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 4491 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 4492 // CHECK9-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 4493 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 4494 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 4495 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 4496 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 4497 // CHECK9-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 4498 // CHECK9-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 4499 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4500 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 4501 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 4502 // CHECK9-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 4503 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4504 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 4505 // CHECK9-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 4506 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 4507 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 4508 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 4509 // CHECK9-NEXT: ret void 4510 // 4511 // 4512 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 4513 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4514 // CHECK9-NEXT: entry: 4515 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4516 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4517 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4518 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4519 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4520 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4521 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4522 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4523 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4524 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4525 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4526 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4527 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4528 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4529 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4530 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4531 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4532 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 4533 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4534 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4535 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4536 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 4537 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4538 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 4539 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 4540 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 4541 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 4542 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 4543 // CHECK9-NEXT: ret void 4544 // 4545 // 4546 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 4547 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 4548 // CHECK9-NEXT: entry: 4549 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4550 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4551 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4552 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4553 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4554 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4555 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4556 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4557 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4558 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4559 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4560 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4561 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4562 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4563 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4564 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4565 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4566 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4567 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4568 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4569 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 4570 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 4571 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 4572 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 4573 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 4574 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 4575 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 4576 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 4577 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 4578 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 4579 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4580 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 4581 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 4582 // CHECK9-NEXT: ret void 4583 // 4584 // 4585 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 4586 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4587 // CHECK9-NEXT: entry: 4588 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4589 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4590 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4591 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4592 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4593 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4594 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4595 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4596 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4597 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4598 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4599 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4600 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4601 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4602 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4603 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4604 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 4605 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4606 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 4607 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 4608 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 4609 // CHECK9-NEXT: ret void 4610 // 4611 // 4612 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 4613 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 4614 // CHECK9-NEXT: entry: 4615 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4616 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4617 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4618 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4619 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4620 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4621 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4622 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4623 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4624 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4625 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4626 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4627 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4628 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4629 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4630 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4631 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4632 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4633 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4634 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 4635 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 4636 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 4637 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4638 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 4639 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4640 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 4641 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 4642 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 4643 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 4644 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 4645 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 4646 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 4647 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 4648 // CHECK9-NEXT: ret void 4649 // 4650 // 4651 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 4652 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4653 // CHECK9-NEXT: entry: 4654 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4655 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4656 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4657 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4658 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4659 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4660 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4661 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4662 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4663 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4664 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4665 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4666 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4667 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 4668 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4669 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4670 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4671 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 4672 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4673 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 4674 // CHECK9-NEXT: ret void 4675 // 4676 // 4677 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 4678 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 4679 // CHECK9-NEXT: entry: 4680 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4681 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4682 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4683 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4684 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4685 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4686 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4687 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4688 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4689 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4690 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4691 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4692 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4693 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4694 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4695 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4696 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4697 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 4698 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4699 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4700 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 4701 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 4702 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4703 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 4704 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 4705 // CHECK9-NEXT: ret void 4706 // 4707 // 4708 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 4709 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 4710 // CHECK10-NEXT: entry: 4711 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4712 // CHECK10-NEXT: ret void 4713 // 4714 // 4715 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 4716 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 4717 // CHECK10-NEXT: entry: 4718 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4719 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4720 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4721 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4722 // CHECK10-NEXT: ret void 4723 // 4724 // 4725 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 4726 // CHECK10-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4727 // CHECK10-NEXT: entry: 4728 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4729 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4730 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4731 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4732 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4733 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4734 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4735 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4736 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 4737 // CHECK10-NEXT: ret void 4738 // 4739 // 4740 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 4741 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 4742 // CHECK10-NEXT: entry: 4743 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4744 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4745 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4746 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4747 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4748 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4749 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4750 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4751 // CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 4752 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 4753 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 4754 // CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 4755 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4756 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4757 // CHECK10-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 4758 // CHECK10-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 4759 // CHECK10-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 4760 // CHECK10: .cancel.exit: 4761 // CHECK10-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 4762 // CHECK10-NEXT: br label [[DOTCANCEL_CONTINUE]] 4763 // CHECK10: .cancel.continue: 4764 // CHECK10-NEXT: ret void 4765 // 4766 // 4767 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 4768 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 4769 // CHECK10-NEXT: entry: 4770 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4771 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4772 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4773 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4774 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4775 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4776 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4777 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4778 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4779 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4780 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 4781 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4782 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4783 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4784 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 4785 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4786 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 4787 // CHECK10-NEXT: ret void 4788 // 4789 // 4790 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 4791 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 4792 // CHECK10-NEXT: entry: 4793 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4794 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4795 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4796 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4797 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4798 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4799 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4800 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4801 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4802 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4803 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4804 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4805 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4806 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 4807 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 4808 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4809 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4810 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 4811 // CHECK10-NEXT: ret void 4812 // 4813 // 4814 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 4815 // CHECK10-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 4816 // CHECK10-NEXT: entry: 4817 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4818 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4819 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4820 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4821 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4822 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4823 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4824 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4825 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4826 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4827 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4828 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4829 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4830 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4831 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4832 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4833 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4834 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4835 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4836 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4837 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4838 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4839 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4840 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4841 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4842 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4843 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4844 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4845 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4846 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4847 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 4848 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 4849 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 4850 // CHECK10-NEXT: ret void 4851 // 4852 // 4853 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 4854 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 4855 // CHECK10-NEXT: entry: 4856 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4857 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4858 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4859 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4860 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4861 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4862 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4863 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4864 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4865 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4866 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4867 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4868 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4869 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4870 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4871 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4872 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4873 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4874 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4875 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4876 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4877 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4878 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4879 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4880 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4881 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4882 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4883 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4884 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4885 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4886 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4887 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4888 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 4889 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4890 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 4891 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 4892 // CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 4893 // CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 4894 // CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 4895 // CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 4896 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 4897 // CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 4898 // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 4899 // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 4900 // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 4901 // CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 4902 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 4903 // CHECK10-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 4904 // CHECK10-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 4905 // CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 4906 // CHECK10-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 4907 // CHECK10-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 4908 // CHECK10-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 4909 // CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 4910 // CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 4911 // CHECK10-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 4912 // CHECK10-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 4913 // CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4914 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 4915 // CHECK10-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 4916 // CHECK10-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 4917 // CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4918 // CHECK10-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 4919 // CHECK10-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 4920 // CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 4921 // CHECK10-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 4922 // CHECK10-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 4923 // CHECK10-NEXT: ret void 4924 // 4925 // 4926 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 4927 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4928 // CHECK10-NEXT: entry: 4929 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4930 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4931 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4932 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4933 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4934 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4935 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4936 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4937 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4938 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4939 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4940 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4941 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4942 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4943 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4944 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4945 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4946 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 4947 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4948 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4949 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4950 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 4951 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4952 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 4953 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 4954 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 4955 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 4956 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 4957 // CHECK10-NEXT: ret void 4958 // 4959 // 4960 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 4961 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 4962 // CHECK10-NEXT: entry: 4963 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4964 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4965 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4966 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4967 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4968 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4969 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4970 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4971 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4972 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4973 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4974 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4975 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4976 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4977 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4978 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4979 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4980 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4981 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4982 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4983 // CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 4984 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 4985 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 4986 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 4987 // CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 4988 // CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 4989 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 4990 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 4991 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 4992 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 4993 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4994 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 4995 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 4996 // CHECK10-NEXT: ret void 4997 // 4998 // 4999 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 5000 // CHECK10-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5001 // CHECK10-NEXT: entry: 5002 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5003 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5004 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5005 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5006 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 5007 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5008 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5009 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5010 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5011 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5012 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 5013 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5014 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5015 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5016 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5017 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 5018 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 5019 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 5020 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 5021 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 5022 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 5023 // CHECK10-NEXT: ret void 5024 // 5025 // 5026 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 5027 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 5028 // CHECK10-NEXT: entry: 5029 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5030 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5031 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5032 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5033 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5034 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5035 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 5036 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5037 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5038 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5039 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5040 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5041 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5042 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 5043 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5044 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5045 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5046 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5047 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 5048 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 5049 // CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 5050 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 5051 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5052 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 5053 // CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5054 // CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 5055 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 5056 // CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8 5057 // CHECK10-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 5058 // CHECK10-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 5059 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 5060 // CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 5061 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 5062 // CHECK10-NEXT: ret void 5063 // 5064 // 5065 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 5066 // CHECK10-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5067 // CHECK10-NEXT: entry: 5068 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5069 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5070 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5071 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5072 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5073 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5074 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5075 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5076 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5077 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5078 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5079 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5080 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5081 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 5082 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 5083 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 5084 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5085 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 5086 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5087 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 5088 // CHECK10-NEXT: ret void 5089 // 5090 // 5091 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 5092 // CHECK10-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5093 // CHECK10-NEXT: entry: 5094 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5095 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5096 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5097 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5098 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5099 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5100 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5101 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5102 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5103 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5104 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5105 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5106 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5107 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5108 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5109 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 5110 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 5111 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 5112 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 5113 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5114 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 5115 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 5116 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5117 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 5118 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 5119 // CHECK10-NEXT: ret void 5120 // 5121 // 5122 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 5123 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 5124 // CHECK11-NEXT: entry: 5125 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5126 // CHECK11-NEXT: ret void 5127 // 5128 // 5129 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 5130 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 5131 // CHECK11-NEXT: entry: 5132 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5133 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5134 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5135 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5136 // CHECK11-NEXT: ret void 5137 // 5138 // 5139 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 5140 // CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 5141 // CHECK11-NEXT: entry: 5142 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5143 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5144 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5145 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5146 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5147 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5148 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 5149 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5150 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5151 // CHECK11-NEXT: ret void 5152 // 5153 // 5154 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 5155 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 5156 // CHECK11-NEXT: entry: 5157 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5158 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5159 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5160 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5161 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5162 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5163 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5164 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5165 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 5166 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 5167 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 5168 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 5169 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5170 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5171 // CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 5172 // CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 5173 // CHECK11-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 5174 // CHECK11: .cancel.exit: 5175 // CHECK11-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 5176 // CHECK11-NEXT: br label [[DOTCANCEL_CONTINUE]] 5177 // CHECK11: .cancel.continue: 5178 // CHECK11-NEXT: ret void 5179 // 5180 // 5181 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 5182 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 5183 // CHECK11-NEXT: entry: 5184 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5185 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5186 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5187 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5188 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5189 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5190 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5191 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5192 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5193 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5194 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5195 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5196 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 5197 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5198 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 5199 // CHECK11-NEXT: ret void 5200 // 5201 // 5202 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 5203 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 5204 // CHECK11-NEXT: entry: 5205 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5206 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5207 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5208 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5209 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5210 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5211 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5212 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5213 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5214 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5215 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5216 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5217 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 5218 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 5219 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5220 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5221 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 5222 // CHECK11-NEXT: ret void 5223 // 5224 // 5225 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 5226 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 5227 // CHECK11-NEXT: entry: 5228 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5229 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5230 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5231 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5232 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5233 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5234 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5235 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5236 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5237 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5238 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5239 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5240 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5241 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5242 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5243 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5244 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5245 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5246 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5247 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5248 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5249 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5250 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5251 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5252 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5253 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5254 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5255 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5256 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 5257 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 5258 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 5259 // CHECK11-NEXT: ret void 5260 // 5261 // 5262 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 5263 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 5264 // CHECK11-NEXT: entry: 5265 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5266 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5267 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5268 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5269 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5270 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5271 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5272 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5273 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5274 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5275 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5276 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5277 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5278 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5279 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5280 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5281 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5282 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5283 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5284 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5285 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5286 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5287 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5288 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5289 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5290 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5291 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5292 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5293 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5294 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5295 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5296 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 5297 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5298 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 5299 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 5300 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 5301 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 5302 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 5303 // CHECK11-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 5304 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 5305 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 5306 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 5307 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 5308 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 5309 // CHECK11-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 5310 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 5311 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 5312 // CHECK11-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 5313 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 5314 // CHECK11-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 5315 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 5316 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 5317 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 5318 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 5319 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 5320 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 5321 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 5322 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 5323 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 5324 // CHECK11-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 5325 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 5326 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 5327 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 5328 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 5329 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 5330 // CHECK11-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 5331 // CHECK11-NEXT: ret void 5332 // 5333 // 5334 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 5335 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5336 // CHECK11-NEXT: entry: 5337 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5338 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5339 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5340 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5341 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5342 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5343 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5344 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5345 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5346 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5347 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5348 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5349 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5350 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5351 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5352 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5353 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5354 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5355 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5356 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 5357 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5358 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 5359 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 5360 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 5361 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 5362 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 5363 // CHECK11-NEXT: ret void 5364 // 5365 // 5366 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 5367 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5368 // CHECK11-NEXT: entry: 5369 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5370 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5371 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5372 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5373 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5374 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5375 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5376 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5377 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5378 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5379 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5380 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5381 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5382 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5383 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5384 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5385 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5386 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5387 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5388 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 5389 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 5390 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5391 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 5392 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 5393 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 5394 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 5395 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 5396 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 5397 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5398 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5399 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 5400 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 5401 // CHECK11-NEXT: ret void 5402 // 5403 // 5404 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 5405 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5406 // CHECK11-NEXT: entry: 5407 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5408 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5409 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5410 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5411 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5412 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5413 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5414 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5415 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5416 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5417 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5418 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5419 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5420 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5421 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5422 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5423 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 5424 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 5425 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 5426 // CHECK11-NEXT: ret void 5427 // 5428 // 5429 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 5430 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 5431 // CHECK11-NEXT: entry: 5432 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5433 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5434 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5435 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5436 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5437 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5438 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5439 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5440 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5441 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5442 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5443 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5444 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5445 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5446 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5447 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5448 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5449 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5450 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5451 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 5452 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5453 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5454 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 5455 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5456 // CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 5457 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 5458 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 5459 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 5460 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 5461 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 5462 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5463 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 5464 // CHECK11-NEXT: ret void 5465 // 5466 // 5467 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 5468 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5469 // CHECK11-NEXT: entry: 5470 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5471 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5472 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5473 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5474 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5475 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5476 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5477 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5478 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5479 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5480 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5481 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5482 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5483 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5484 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5485 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5486 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5487 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5488 // CHECK11-NEXT: ret void 5489 // 5490 // 5491 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 5492 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5493 // CHECK11-NEXT: entry: 5494 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5495 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5496 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5497 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5498 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5499 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5500 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5501 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5502 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5503 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5504 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5505 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5506 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5507 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5508 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5509 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5510 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 5511 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5512 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5513 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 5514 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5515 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5516 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 5517 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 5518 // CHECK11-NEXT: ret void 5519 // 5520 // 5521 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 5522 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 5523 // CHECK12-NEXT: entry: 5524 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5525 // CHECK12-NEXT: ret void 5526 // 5527 // 5528 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 5529 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 5530 // CHECK12-NEXT: entry: 5531 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5532 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5533 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5534 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5535 // CHECK12-NEXT: ret void 5536 // 5537 // 5538 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 5539 // CHECK12-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 5540 // CHECK12-NEXT: entry: 5541 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5542 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5543 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5544 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5545 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5546 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5547 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 5548 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5549 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5550 // CHECK12-NEXT: ret void 5551 // 5552 // 5553 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 5554 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 5555 // CHECK12-NEXT: entry: 5556 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5557 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5558 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5559 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5560 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5561 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5562 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5563 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5564 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 5565 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 5566 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 5567 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 5568 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5569 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5570 // CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 5571 // CHECK12-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 5572 // CHECK12-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 5573 // CHECK12: .cancel.exit: 5574 // CHECK12-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 5575 // CHECK12-NEXT: br label [[DOTCANCEL_CONTINUE]] 5576 // CHECK12: .cancel.continue: 5577 // CHECK12-NEXT: ret void 5578 // 5579 // 5580 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 5581 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 5582 // CHECK12-NEXT: entry: 5583 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5584 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5585 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5586 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5587 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5588 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5589 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5590 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5591 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5592 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5593 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5594 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5595 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 5596 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5597 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 5598 // CHECK12-NEXT: ret void 5599 // 5600 // 5601 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 5602 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 5603 // CHECK12-NEXT: entry: 5604 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5605 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5606 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5607 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5608 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5609 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5610 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5611 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5612 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5613 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5614 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5615 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5616 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 5617 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 5618 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5619 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5620 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 5621 // CHECK12-NEXT: ret void 5622 // 5623 // 5624 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 5625 // CHECK12-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 5626 // CHECK12-NEXT: entry: 5627 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5628 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5629 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5630 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5631 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5632 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5633 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5634 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5635 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5636 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5637 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5638 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5639 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5640 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5641 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5642 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5643 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5644 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5645 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5646 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5647 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5648 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5649 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5650 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5651 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5652 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5653 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5654 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5655 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 5656 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 5657 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 5658 // CHECK12-NEXT: ret void 5659 // 5660 // 5661 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 5662 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 5663 // CHECK12-NEXT: entry: 5664 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5665 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5666 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5667 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5668 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5669 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5670 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5671 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5672 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5673 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5674 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5675 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5676 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5677 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5678 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5679 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5680 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5681 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5682 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5683 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5684 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5685 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5686 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5687 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5688 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5689 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5690 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5691 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5692 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5693 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5694 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5695 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 5696 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5697 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 5698 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 5699 // CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 5700 // CHECK12-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 5701 // CHECK12-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 5702 // CHECK12-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 5703 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 5704 // CHECK12-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 5705 // CHECK12-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 5706 // CHECK12-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 5707 // CHECK12-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 5708 // CHECK12-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 5709 // CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 5710 // CHECK12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 5711 // CHECK12-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 5712 // CHECK12-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 5713 // CHECK12-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 5714 // CHECK12-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 5715 // CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 5716 // CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 5717 // CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 5718 // CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 5719 // CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 5720 // CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 5721 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 5722 // CHECK12-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 5723 // CHECK12-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 5724 // CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 5725 // CHECK12-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 5726 // CHECK12-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 5727 // CHECK12-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 5728 // CHECK12-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 5729 // CHECK12-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 5730 // CHECK12-NEXT: ret void 5731 // 5732 // 5733 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 5734 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5735 // CHECK12-NEXT: entry: 5736 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5737 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5738 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5739 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5740 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5741 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5742 // CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5743 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5744 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5745 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5746 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5747 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5748 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5749 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5750 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5751 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5752 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5753 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5754 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5755 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 5756 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5757 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 5758 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 5759 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 5760 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 5761 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 5762 // CHECK12-NEXT: ret void 5763 // 5764 // 5765 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 5766 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5767 // CHECK12-NEXT: entry: 5768 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5769 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5770 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5771 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5772 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5773 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5774 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5775 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5776 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5777 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5778 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5779 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5780 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5781 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5782 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5783 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5784 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5785 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5786 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5787 // CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 5788 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 5789 // CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5790 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 5791 // CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 5792 // CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 5793 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 5794 // CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 5795 // CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 5796 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5797 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5798 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 5799 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 5800 // CHECK12-NEXT: ret void 5801 // 5802 // 5803 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 5804 // CHECK12-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5805 // CHECK12-NEXT: entry: 5806 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5807 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5808 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5809 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5810 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5811 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5812 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5813 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5814 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5815 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5816 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5817 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5818 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5819 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5820 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5821 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5822 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 5823 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 5824 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 5825 // CHECK12-NEXT: ret void 5826 // 5827 // 5828 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 5829 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 5830 // CHECK12-NEXT: entry: 5831 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5832 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5833 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5834 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5835 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5836 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5837 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5838 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5839 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5840 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5841 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5842 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5843 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5844 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5845 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5846 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5847 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5848 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5849 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5850 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 5851 // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5852 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5853 // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 5854 // CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5855 // CHECK12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 5856 // CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 5857 // CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4 5858 // CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 5859 // CHECK12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 5860 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 5861 // CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5862 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 5863 // CHECK12-NEXT: ret void 5864 // 5865 // 5866 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 5867 // CHECK12-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5868 // CHECK12-NEXT: entry: 5869 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5870 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5871 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5872 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5873 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5874 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5875 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5876 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5877 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5878 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5879 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5880 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5881 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5882 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5883 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5884 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5885 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5886 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5887 // CHECK12-NEXT: ret void 5888 // 5889 // 5890 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 5891 // CHECK12-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5892 // CHECK12-NEXT: entry: 5893 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5894 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5895 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5896 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5897 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5898 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5899 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5900 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5901 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5902 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5903 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5904 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5905 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5906 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5907 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5908 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5909 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 5910 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5911 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5912 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 5913 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5914 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5915 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 5916 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 5917 // CHECK12-NEXT: ret void 5918 // 5919 // 5920 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi 5921 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5922 // CHECK17-NEXT: entry: 5923 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5924 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 5925 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 5926 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5927 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 5928 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 5929 // CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 5930 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 5931 // CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 5932 // CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 5933 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5934 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5935 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 5936 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 5937 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 5938 // CHECK17-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 5939 // CHECK17-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 5940 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 5941 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 5942 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 5943 // CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 5944 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 5945 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 5946 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 5947 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 5948 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 5949 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5950 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 5951 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 5952 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 5953 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 5954 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 5955 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 5956 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 5957 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 5958 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 5959 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 5960 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 5961 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 5962 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 5963 // CHECK17-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 5964 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 5965 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 5966 // CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 5967 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 5968 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5969 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 5970 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 5971 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 5972 // CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 5973 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5974 // CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 5975 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5976 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5977 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 5978 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 5979 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5980 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 5981 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 5982 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 5983 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 5984 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 5985 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 5986 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 5987 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 5988 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 5989 // CHECK17: omp_offload.failed: 5990 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 5991 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 5992 // CHECK17: omp_offload.cont: 5993 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 5994 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 5995 // CHECK17-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 5996 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 5997 // CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 5998 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 5999 // CHECK17-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 6000 // CHECK17-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 6001 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 6002 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 6003 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6004 // CHECK17: omp_if.then: 6005 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 6006 // CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 6007 // CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 6008 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 6009 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 6010 // CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 6011 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 6012 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 6013 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 6014 // CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* 6015 // CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 6016 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 6017 // CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 6018 // CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 6019 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 6020 // CHECK17-NEXT: store i8* null, i8** [[TMP38]], align 8 6021 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 6022 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 6023 // CHECK17-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6024 // CHECK17-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 6025 // CHECK17-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 6026 // CHECK17: omp_offload.failed10: 6027 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 6028 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT11]] 6029 // CHECK17: omp_offload.cont11: 6030 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6031 // CHECK17: omp_if.else: 6032 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 6033 // CHECK17-NEXT: br label [[OMP_IF_END]] 6034 // CHECK17: omp_if.end: 6035 // CHECK17-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 6036 // CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 6037 // CHECK17-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 6038 // CHECK17-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 6039 // CHECK17-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 6040 // CHECK17-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 6041 // CHECK17-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] 6042 // CHECK17: omp_if.then15: 6043 // CHECK17-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 6044 // CHECK17-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] 6045 // CHECK17-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 6046 // CHECK17-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 6047 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP49]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i64 72, i1 false) 6048 // CHECK17-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 6049 // CHECK17-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 6050 // CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8 6051 // CHECK17-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 6052 // CHECK17-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 6053 // CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8 6054 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 6055 // CHECK17-NEXT: store i8* null, i8** [[TMP54]], align 8 6056 // CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 6057 // CHECK17-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 6058 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 6059 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 6060 // CHECK17-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 6061 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 6062 // CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 6063 // CHECK17-NEXT: store i8* null, i8** [[TMP59]], align 8 6064 // CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 6065 // CHECK17-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64* 6066 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP61]], align 8 6067 // CHECK17-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 6068 // CHECK17-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64* 6069 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP63]], align 8 6070 // CHECK17-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 6071 // CHECK17-NEXT: store i8* null, i8** [[TMP64]], align 8 6072 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 6073 // CHECK17-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 6074 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP66]], align 8 6075 // CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 6076 // CHECK17-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 6077 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 6078 // CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 6079 // CHECK17-NEXT: store i64 [[TMP46]], i64* [[TMP69]], align 8 6080 // CHECK17-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 6081 // CHECK17-NEXT: store i8* null, i8** [[TMP70]], align 8 6082 // CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 6083 // CHECK17-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 6084 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 8 6085 // CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 6086 // CHECK17-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 6087 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 6088 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 6089 // CHECK17-NEXT: store i8* null, i8** [[TMP75]], align 8 6090 // CHECK17-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 6091 // CHECK17-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* 6092 // CHECK17-NEXT: store i64 5, i64* [[TMP77]], align 8 6093 // CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 6094 // CHECK17-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 6095 // CHECK17-NEXT: store i64 5, i64* [[TMP79]], align 8 6096 // CHECK17-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 6097 // CHECK17-NEXT: store i8* null, i8** [[TMP80]], align 8 6098 // CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 6099 // CHECK17-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 6100 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP82]], align 8 6101 // CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 6102 // CHECK17-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i64* 6103 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP84]], align 8 6104 // CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 6105 // CHECK17-NEXT: store i8* null, i8** [[TMP85]], align 8 6106 // CHECK17-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 6107 // CHECK17-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 6108 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP87]], align 8 6109 // CHECK17-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 6110 // CHECK17-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 6111 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP89]], align 8 6112 // CHECK17-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 6113 // CHECK17-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 8 6114 // CHECK17-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 6115 // CHECK17-NEXT: store i8* null, i8** [[TMP91]], align 8 6116 // CHECK17-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 6117 // CHECK17-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 6118 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 8 6119 // CHECK17-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 6120 // CHECK17-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 6121 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 8 6122 // CHECK17-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 6123 // CHECK17-NEXT: store i8* null, i8** [[TMP96]], align 8 6124 // CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 6125 // CHECK17-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 6126 // CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6127 // CHECK17-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6128 // CHECK17-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 6129 // CHECK17-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 6130 // CHECK17: omp_offload.failed19: 6131 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 6132 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT20]] 6133 // CHECK17: omp_offload.cont20: 6134 // CHECK17-NEXT: br label [[OMP_IF_END22:%.*]] 6135 // CHECK17: omp_if.else21: 6136 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 6137 // CHECK17-NEXT: br label [[OMP_IF_END22]] 6138 // CHECK17: omp_if.end22: 6139 // CHECK17-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 6140 // CHECK17-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6141 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 6142 // CHECK17-NEXT: ret i32 [[TMP102]] 6143 // 6144 // 6145 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 6146 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] { 6147 // CHECK17-NEXT: entry: 6148 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 6149 // CHECK17-NEXT: ret void 6150 // 6151 // 6152 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 6153 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 6154 // CHECK17-NEXT: entry: 6155 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6156 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6157 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6158 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6159 // CHECK17-NEXT: ret void 6160 // 6161 // 6162 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. 6163 // CHECK17-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 6164 // CHECK17-NEXT: entry: 6165 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 6166 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 6167 // CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 6168 // CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 6169 // CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 6170 // CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 6171 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 6172 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 6173 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 6174 // CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 6175 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 6176 // CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 6177 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 6178 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 6179 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 6180 // CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 6181 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 6182 // CHECK17-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 6183 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 6184 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 6185 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 6186 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 6187 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 6188 // CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 6189 // CHECK17-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 6190 // CHECK17-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 6191 // CHECK17-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 6192 // CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 6193 // CHECK17-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 6194 // CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 6195 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 6196 // CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 6197 // CHECK17: omp_offload.failed.i: 6198 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 6199 // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 6200 // CHECK17: .omp_outlined..1.exit: 6201 // CHECK17-NEXT: ret i32 0 6202 // 6203 // 6204 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 6205 // CHECK17-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 6206 // CHECK17-NEXT: entry: 6207 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6208 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6209 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6210 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6211 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6212 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6213 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 6214 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6215 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6216 // CHECK17-NEXT: ret void 6217 // 6218 // 6219 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 6220 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 6221 // CHECK17-NEXT: entry: 6222 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6223 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6224 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6225 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6226 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6227 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6228 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6229 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6230 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6231 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6232 // CHECK17-NEXT: ret void 6233 // 6234 // 6235 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 6236 // CHECK17-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 6237 // CHECK17-NEXT: entry: 6238 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6239 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6240 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6241 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6242 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6243 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6244 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 6245 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6246 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6247 // CHECK17-NEXT: ret void 6248 // 6249 // 6250 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 6251 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 6252 // CHECK17-NEXT: entry: 6253 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6254 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6255 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6256 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6257 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6258 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6259 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6260 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6261 // CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 6262 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 6263 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 6264 // CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 6265 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6266 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 6267 // CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 6268 // CHECK17-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 6269 // CHECK17-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 6270 // CHECK17: .cancel.exit: 6271 // CHECK17-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 6272 // CHECK17-NEXT: br label [[DOTCANCEL_CONTINUE]] 6273 // CHECK17: .cancel.continue: 6274 // CHECK17-NEXT: ret void 6275 // 6276 // 6277 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 6278 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 6279 // CHECK17-NEXT: entry: 6280 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6281 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6282 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6283 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6284 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6285 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6286 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6287 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6288 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6289 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6290 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 6291 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6292 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6293 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6294 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 6295 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6296 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 6297 // CHECK17-NEXT: ret void 6298 // 6299 // 6300 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 6301 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 6302 // CHECK17-NEXT: entry: 6303 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6304 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6305 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6306 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6307 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6308 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6309 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6310 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6311 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6312 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6313 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6314 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6315 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6316 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 6317 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 6318 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 6319 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6320 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 6321 // CHECK17-NEXT: ret void 6322 // 6323 // 6324 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 6325 // CHECK17-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 6326 // CHECK17-NEXT: entry: 6327 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6328 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 6329 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6330 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 6331 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 6332 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6333 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 6334 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 6335 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 6336 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6337 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6338 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 6339 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6340 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 6341 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 6342 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6343 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 6344 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 6345 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 6346 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6347 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 6348 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6349 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 6350 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 6351 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6352 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 6353 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 6354 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 6355 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 6356 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6357 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 6358 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 6359 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 6360 // CHECK17-NEXT: ret void 6361 // 6362 // 6363 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 6364 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 6365 // CHECK17-NEXT: entry: 6366 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6367 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6368 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6369 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 6370 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6371 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 6372 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 6373 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6374 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 6375 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 6376 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 6377 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6378 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6379 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6380 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 6381 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6382 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 6383 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 6384 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6385 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 6386 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 6387 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 6388 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6389 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 6390 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6391 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 6392 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 6393 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6394 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 6395 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 6396 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 6397 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 6398 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 6399 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6400 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 6401 // CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 6402 // CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 6403 // CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 6404 // CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 6405 // CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 6406 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 6407 // CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 6408 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 6409 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 6410 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 6411 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 6412 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 6413 // CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 6414 // CHECK17-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 6415 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 6416 // CHECK17-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 6417 // CHECK17-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 6418 // CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 6419 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 6420 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 6421 // CHECK17-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 6422 // CHECK17-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 6423 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6424 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 6425 // CHECK17-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 6426 // CHECK17-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 6427 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6428 // CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 6429 // CHECK17-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 6430 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 6431 // CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 6432 // CHECK17-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 6433 // CHECK17-NEXT: ret void 6434 // 6435 // 6436 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari 6437 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 6438 // CHECK17-NEXT: entry: 6439 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6440 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 6441 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 6442 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6443 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6444 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6445 // CHECK17-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 6446 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6447 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6448 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6449 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6450 // CHECK17-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 6451 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6452 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6453 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6454 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6455 // CHECK17-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 6456 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6457 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6458 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6459 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6460 // CHECK17-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 6461 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6462 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6463 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6464 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6465 // CHECK17-NEXT: ret i32 [[TMP8]] 6466 // 6467 // 6468 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6469 // CHECK17-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6470 // CHECK17-NEXT: entry: 6471 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6472 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6473 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 6474 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6475 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6476 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 6477 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 6478 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 6479 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 6480 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 6481 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6482 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6483 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6484 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6485 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6486 // CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6487 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6488 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 6489 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6490 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 6491 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 6492 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 6493 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 6494 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 6495 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 6496 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 6497 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 6498 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 6499 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 6500 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6501 // CHECK17: omp_if.then: 6502 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6503 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 6504 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 6505 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 6506 // CHECK17-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 6507 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6508 // CHECK17-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 6509 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 6510 // CHECK17-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6511 // CHECK17-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 6512 // CHECK17-NEXT: store double* [[A]], double** [[TMP14]], align 8 6513 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6514 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 6515 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6516 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 6517 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 6518 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6519 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 6520 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 6521 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 6522 // CHECK17-NEXT: store i8* null, i8** [[TMP20]], align 8 6523 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6524 // CHECK17-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 6525 // CHECK17-NEXT: store i64 2, i64* [[TMP22]], align 8 6526 // CHECK17-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6527 // CHECK17-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 6528 // CHECK17-NEXT: store i64 2, i64* [[TMP24]], align 8 6529 // CHECK17-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 6530 // CHECK17-NEXT: store i8* null, i8** [[TMP25]], align 8 6531 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6532 // CHECK17-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 6533 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 6534 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6535 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 6536 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 6537 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 6538 // CHECK17-NEXT: store i8* null, i8** [[TMP30]], align 8 6539 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6540 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 6541 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 6542 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6543 // CHECK17-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 6544 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 6545 // CHECK17-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6546 // CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 6547 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 6548 // CHECK17-NEXT: store i8* null, i8** [[TMP36]], align 8 6549 // CHECK17-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6550 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6551 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6552 // CHECK17-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6553 // CHECK17-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 6554 // CHECK17-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6555 // CHECK17: omp_offload.failed: 6556 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 6557 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6558 // CHECK17: omp_offload.cont: 6559 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6560 // CHECK17: omp_if.else: 6561 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 6562 // CHECK17-NEXT: br label [[OMP_IF_END]] 6563 // CHECK17: omp_if.end: 6564 // CHECK17-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 6565 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 6566 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 6567 // CHECK17-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 6568 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 6569 // CHECK17-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 6570 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 6571 // CHECK17-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6572 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 6573 // CHECK17-NEXT: ret i32 [[ADD4]] 6574 // 6575 // 6576 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici 6577 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 6578 // CHECK17-NEXT: entry: 6579 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6580 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 6581 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 6582 // CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 6583 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6584 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6585 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6586 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 6587 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 6588 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 6589 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 6590 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6591 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6592 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 6593 // CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 6594 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6595 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6596 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 6597 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6598 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6599 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6600 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 6601 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6602 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 6603 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 6604 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 6605 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 6606 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6607 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6608 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6609 // CHECK17: omp_if.then: 6610 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6611 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 6612 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 6613 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6614 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 6615 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 6616 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6617 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 6618 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6619 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 6620 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 6621 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6622 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 6623 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 6624 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 6625 // CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 6626 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6627 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 6628 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 6629 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6630 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 6631 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 6632 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 6633 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 6634 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6635 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 6636 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 6637 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6638 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 6639 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 6640 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 6641 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 6642 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6643 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6644 // CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6645 // CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 6646 // CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6647 // CHECK17: omp_offload.failed: 6648 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6649 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6650 // CHECK17: omp_offload.cont: 6651 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6652 // CHECK17: omp_if.else: 6653 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6654 // CHECK17-NEXT: br label [[OMP_IF_END]] 6655 // CHECK17: omp_if.end: 6656 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 6657 // CHECK17-NEXT: ret i32 [[TMP31]] 6658 // 6659 // 6660 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6661 // CHECK17-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 6662 // CHECK17-NEXT: entry: 6663 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6664 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 6665 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 6666 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6667 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6668 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6669 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 6670 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 6671 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 6672 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6673 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6674 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 6675 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6676 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6677 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 6678 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6679 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6680 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6681 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 6682 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6683 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6684 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6685 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6686 // CHECK17: omp_if.then: 6687 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6688 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 6689 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 6690 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6691 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 6692 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 6693 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6694 // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 6695 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6696 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 6697 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 6698 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6699 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 6700 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 6701 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 6702 // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 6703 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6704 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 6705 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 6706 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6707 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 6708 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 6709 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 6710 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 6711 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6712 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6713 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6714 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 6715 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6716 // CHECK17: omp_offload.failed: 6717 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6718 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6719 // CHECK17: omp_offload.cont: 6720 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6721 // CHECK17: omp_if.else: 6722 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6723 // CHECK17-NEXT: br label [[OMP_IF_END]] 6724 // CHECK17: omp_if.end: 6725 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 6726 // CHECK17-NEXT: ret i32 [[TMP24]] 6727 // 6728 // 6729 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 6730 // CHECK17-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 6731 // CHECK17-NEXT: entry: 6732 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6733 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6734 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6735 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6736 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6737 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 6738 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6739 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6740 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6741 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6742 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6743 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6744 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6745 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6746 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6747 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6748 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 6749 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 6750 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 6751 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 6752 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 6753 // CHECK17-NEXT: ret void 6754 // 6755 // 6756 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..10 6757 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 6758 // CHECK17-NEXT: entry: 6759 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6760 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6761 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6762 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6763 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6764 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6765 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6766 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6767 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6768 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6769 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6770 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6771 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6772 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6773 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6774 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6775 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6776 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6777 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6778 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 6779 // CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 6780 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 6781 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6782 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 6783 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6784 // CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 6785 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 6786 // CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 6787 // CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 6788 // CHECK17-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 6789 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 6790 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 6791 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 6792 // CHECK17-NEXT: ret void 6793 // 6794 // 6795 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 6796 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6797 // CHECK17-NEXT: entry: 6798 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6799 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6800 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6801 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6802 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6803 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6804 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 6805 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6806 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6807 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6808 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6809 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6810 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6811 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6812 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6813 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6814 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6815 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 6816 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6817 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6818 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6819 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 6820 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6821 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 6822 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 6823 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 6824 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 6825 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 6826 // CHECK17-NEXT: ret void 6827 // 6828 // 6829 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..13 6830 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6831 // CHECK17-NEXT: entry: 6832 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6833 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6834 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6835 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6836 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6837 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6838 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6839 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6840 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6841 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6842 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6843 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6844 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6845 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6846 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6847 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6848 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6849 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 6850 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6851 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6852 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 6853 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6854 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6855 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 6856 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 6857 // CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 6858 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 6859 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 6860 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 6861 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 6862 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6863 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 6864 // CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 6865 // CHECK17-NEXT: ret void 6866 // 6867 // 6868 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 6869 // CHECK17-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6870 // CHECK17-NEXT: entry: 6871 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6872 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6873 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6874 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6875 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6876 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6877 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6878 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6879 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6880 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6881 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6882 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6883 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6884 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 6885 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6886 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6887 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6888 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 6889 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6890 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 6891 // CHECK17-NEXT: ret void 6892 // 6893 // 6894 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..16 6895 // CHECK17-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6896 // CHECK17-NEXT: entry: 6897 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6898 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6899 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6900 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6901 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6902 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6903 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6904 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6905 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6906 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6907 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6908 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6909 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6910 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6911 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 6912 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6913 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6914 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 6915 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 6916 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6917 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 6918 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 6919 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6920 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 6921 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 6922 // CHECK17-NEXT: ret void 6923 // 6924 // 6925 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 6926 // CHECK17-SAME: () #[[ATTR8:[0-9]+]] { 6927 // CHECK17-NEXT: entry: 6928 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 6929 // CHECK17-NEXT: ret void 6930 // 6931 // 6932 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi 6933 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 6934 // CHECK18-NEXT: entry: 6935 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6936 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 6937 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 6938 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 6939 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6940 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6941 // CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 6942 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6943 // CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 6944 // CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 6945 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6946 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6947 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 6948 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 6949 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 6950 // CHECK18-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 6951 // CHECK18-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 6952 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 6953 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 6954 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 6955 // CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 6956 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 6957 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 6958 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 6959 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 6960 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 6961 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6962 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 6963 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 6964 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6965 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 6966 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6967 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 6968 // CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 6969 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 6970 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6971 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 6972 // CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 6973 // CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 6974 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 6975 // CHECK18-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 6976 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 6977 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 6978 // CHECK18-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 6979 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 6980 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6981 // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 6982 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 6983 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 6984 // CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 6985 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6986 // CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 6987 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6988 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6989 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 6990 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 6991 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6992 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 6993 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 6994 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6995 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 6996 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6997 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6998 // CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6999 // CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 7000 // CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7001 // CHECK18: omp_offload.failed: 7002 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 7003 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 7004 // CHECK18: omp_offload.cont: 7005 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 7006 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 7007 // CHECK18-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 7008 // CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 7009 // CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 7010 // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 7011 // CHECK18-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 7012 // CHECK18-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 7013 // CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 7014 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 7015 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7016 // CHECK18: omp_if.then: 7017 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 7018 // CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 7019 // CHECK18-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 7020 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 7021 // CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 7022 // CHECK18-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 7023 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 7024 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 7025 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 7026 // CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* 7027 // CHECK18-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 7028 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 7029 // CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 7030 // CHECK18-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 7031 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 7032 // CHECK18-NEXT: store i8* null, i8** [[TMP38]], align 8 7033 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 7034 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 7035 // CHECK18-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7036 // CHECK18-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 7037 // CHECK18-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 7038 // CHECK18: omp_offload.failed10: 7039 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 7040 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT11]] 7041 // CHECK18: omp_offload.cont11: 7042 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 7043 // CHECK18: omp_if.else: 7044 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 7045 // CHECK18-NEXT: br label [[OMP_IF_END]] 7046 // CHECK18: omp_if.end: 7047 // CHECK18-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 7048 // CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 7049 // CHECK18-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 7050 // CHECK18-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 7051 // CHECK18-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 7052 // CHECK18-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 7053 // CHECK18-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] 7054 // CHECK18: omp_if.then15: 7055 // CHECK18-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 7056 // CHECK18-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] 7057 // CHECK18-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 7058 // CHECK18-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 7059 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP49]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i64 72, i1 false) 7060 // CHECK18-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 7061 // CHECK18-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 7062 // CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8 7063 // CHECK18-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 7064 // CHECK18-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 7065 // CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8 7066 // CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 7067 // CHECK18-NEXT: store i8* null, i8** [[TMP54]], align 8 7068 // CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 7069 // CHECK18-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 7070 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 7071 // CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 7072 // CHECK18-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 7073 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 7074 // CHECK18-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 7075 // CHECK18-NEXT: store i8* null, i8** [[TMP59]], align 8 7076 // CHECK18-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 7077 // CHECK18-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64* 7078 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP61]], align 8 7079 // CHECK18-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 7080 // CHECK18-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64* 7081 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP63]], align 8 7082 // CHECK18-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 7083 // CHECK18-NEXT: store i8* null, i8** [[TMP64]], align 8 7084 // CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 7085 // CHECK18-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 7086 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP66]], align 8 7087 // CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 7088 // CHECK18-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 7089 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 7090 // CHECK18-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 7091 // CHECK18-NEXT: store i64 [[TMP46]], i64* [[TMP69]], align 8 7092 // CHECK18-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 7093 // CHECK18-NEXT: store i8* null, i8** [[TMP70]], align 8 7094 // CHECK18-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 7095 // CHECK18-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 7096 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 8 7097 // CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 7098 // CHECK18-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 7099 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 7100 // CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 7101 // CHECK18-NEXT: store i8* null, i8** [[TMP75]], align 8 7102 // CHECK18-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 7103 // CHECK18-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* 7104 // CHECK18-NEXT: store i64 5, i64* [[TMP77]], align 8 7105 // CHECK18-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 7106 // CHECK18-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 7107 // CHECK18-NEXT: store i64 5, i64* [[TMP79]], align 8 7108 // CHECK18-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 7109 // CHECK18-NEXT: store i8* null, i8** [[TMP80]], align 8 7110 // CHECK18-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 7111 // CHECK18-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 7112 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP82]], align 8 7113 // CHECK18-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 7114 // CHECK18-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i64* 7115 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP84]], align 8 7116 // CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 7117 // CHECK18-NEXT: store i8* null, i8** [[TMP85]], align 8 7118 // CHECK18-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 7119 // CHECK18-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 7120 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP87]], align 8 7121 // CHECK18-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 7122 // CHECK18-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 7123 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP89]], align 8 7124 // CHECK18-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 7125 // CHECK18-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 8 7126 // CHECK18-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 7127 // CHECK18-NEXT: store i8* null, i8** [[TMP91]], align 8 7128 // CHECK18-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 7129 // CHECK18-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 7130 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 8 7131 // CHECK18-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 7132 // CHECK18-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 7133 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 8 7134 // CHECK18-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 7135 // CHECK18-NEXT: store i8* null, i8** [[TMP96]], align 8 7136 // CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 7137 // CHECK18-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 7138 // CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 7139 // CHECK18-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7140 // CHECK18-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 7141 // CHECK18-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 7142 // CHECK18: omp_offload.failed19: 7143 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 7144 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT20]] 7145 // CHECK18: omp_offload.cont20: 7146 // CHECK18-NEXT: br label [[OMP_IF_END22:%.*]] 7147 // CHECK18: omp_if.else21: 7148 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 7149 // CHECK18-NEXT: br label [[OMP_IF_END22]] 7150 // CHECK18: omp_if.end22: 7151 // CHECK18-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 7152 // CHECK18-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7153 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 7154 // CHECK18-NEXT: ret i32 [[TMP102]] 7155 // 7156 // 7157 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 7158 // CHECK18-SAME: () #[[ATTR2:[0-9]+]] { 7159 // CHECK18-NEXT: entry: 7160 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 7161 // CHECK18-NEXT: ret void 7162 // 7163 // 7164 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 7165 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 7166 // CHECK18-NEXT: entry: 7167 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7168 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7169 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7170 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7171 // CHECK18-NEXT: ret void 7172 // 7173 // 7174 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. 7175 // CHECK18-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 7176 // CHECK18-NEXT: entry: 7177 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 7178 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 7179 // CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 7180 // CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 7181 // CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 7182 // CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 7183 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 7184 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 7185 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 7186 // CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 7187 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 7188 // CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 7189 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 7190 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 7191 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 7192 // CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 7193 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 7194 // CHECK18-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 7195 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 7196 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 7197 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 7198 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 7199 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 7200 // CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 7201 // CHECK18-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 7202 // CHECK18-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 7203 // CHECK18-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 7204 // CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 7205 // CHECK18-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 7206 // CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 7207 // CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 7208 // CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 7209 // CHECK18: omp_offload.failed.i: 7210 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 7211 // CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 7212 // CHECK18: .omp_outlined..1.exit: 7213 // CHECK18-NEXT: ret i32 0 7214 // 7215 // 7216 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 7217 // CHECK18-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 7218 // CHECK18-NEXT: entry: 7219 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7220 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7221 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7222 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7223 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7224 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7225 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 7226 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7227 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 7228 // CHECK18-NEXT: ret void 7229 // 7230 // 7231 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 7232 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 7233 // CHECK18-NEXT: entry: 7234 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7235 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7236 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7237 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7238 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7239 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7240 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7241 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7242 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7243 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7244 // CHECK18-NEXT: ret void 7245 // 7246 // 7247 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 7248 // CHECK18-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 7249 // CHECK18-NEXT: entry: 7250 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7251 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7252 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7253 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7254 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 7255 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7256 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 7257 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7258 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 7259 // CHECK18-NEXT: ret void 7260 // 7261 // 7262 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 7263 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 7264 // CHECK18-NEXT: entry: 7265 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7266 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7267 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7268 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7269 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7270 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7271 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7272 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 7273 // CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 7274 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 7275 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 7276 // CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 7277 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7278 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 7279 // CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 7280 // CHECK18-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 7281 // CHECK18-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 7282 // CHECK18: .cancel.exit: 7283 // CHECK18-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 7284 // CHECK18-NEXT: br label [[DOTCANCEL_CONTINUE]] 7285 // CHECK18: .cancel.continue: 7286 // CHECK18-NEXT: ret void 7287 // 7288 // 7289 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 7290 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 7291 // CHECK18-NEXT: entry: 7292 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7293 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7294 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7295 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7296 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7297 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7298 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7299 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7300 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7301 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7302 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 7303 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7304 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 7305 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7306 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 7307 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7308 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 7309 // CHECK18-NEXT: ret void 7310 // 7311 // 7312 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 7313 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 7314 // CHECK18-NEXT: entry: 7315 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7316 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7317 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7318 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7319 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7320 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7321 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7322 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7323 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7324 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7325 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7326 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7327 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7328 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 7329 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 7330 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 7331 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 7332 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 7333 // CHECK18-NEXT: ret void 7334 // 7335 // 7336 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 7337 // CHECK18-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 7338 // CHECK18-NEXT: entry: 7339 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7340 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7341 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7342 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7343 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7344 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7345 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7346 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7347 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7348 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7349 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7350 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7351 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7352 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7353 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7354 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7355 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7356 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7357 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7358 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7359 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7360 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7361 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7362 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7363 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7364 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7365 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7366 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7367 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7368 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7369 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 7370 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 7371 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 7372 // CHECK18-NEXT: ret void 7373 // 7374 // 7375 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 7376 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 7377 // CHECK18-NEXT: entry: 7378 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7379 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7380 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7381 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7382 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7383 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7384 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7385 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7386 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7387 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7388 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7389 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7390 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7391 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7392 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7393 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7394 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7395 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7396 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7397 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7398 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7399 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7400 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7401 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7402 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7403 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7404 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7405 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7406 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7407 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7408 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7409 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7410 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 7411 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7412 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 7413 // CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 7414 // CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 7415 // CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 7416 // CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 7417 // CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 7418 // CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 7419 // CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 7420 // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 7421 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 7422 // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 7423 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 7424 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 7425 // CHECK18-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 7426 // CHECK18-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 7427 // CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 7428 // CHECK18-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 7429 // CHECK18-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 7430 // CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 7431 // CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 7432 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 7433 // CHECK18-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 7434 // CHECK18-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 7435 // CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 7436 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 7437 // CHECK18-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 7438 // CHECK18-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 7439 // CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 7440 // CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 7441 // CHECK18-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 7442 // CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 7443 // CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 7444 // CHECK18-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 7445 // CHECK18-NEXT: ret void 7446 // 7447 // 7448 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari 7449 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7450 // CHECK18-NEXT: entry: 7451 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7452 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 7453 // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 7454 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7455 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 7456 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7457 // CHECK18-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 7458 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 7459 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7460 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 7461 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7462 // CHECK18-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 7463 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 7464 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7465 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 7466 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7467 // CHECK18-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 7468 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 7469 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7470 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 7471 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7472 // CHECK18-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 7473 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7474 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7475 // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 7476 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7477 // CHECK18-NEXT: ret i32 [[TMP8]] 7478 // 7479 // 7480 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7481 // CHECK18-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7482 // CHECK18-NEXT: entry: 7483 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7484 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7485 // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 7486 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7487 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7488 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 7489 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 7490 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 7491 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 7492 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 7493 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7494 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7495 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7496 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7497 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7498 // CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 7499 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7500 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7501 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 7502 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 7503 // CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 7504 // CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 7505 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 7506 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 7507 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 7508 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 7509 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 7510 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 7511 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 7512 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7513 // CHECK18: omp_if.then: 7514 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 7515 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 7516 // CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 7517 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 7518 // CHECK18-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 7519 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7520 // CHECK18-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 7521 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 7522 // CHECK18-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7523 // CHECK18-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 7524 // CHECK18-NEXT: store double* [[A]], double** [[TMP14]], align 8 7525 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 7526 // CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 7527 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7528 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 7529 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 7530 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7531 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 7532 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 7533 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 7534 // CHECK18-NEXT: store i8* null, i8** [[TMP20]], align 8 7535 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7536 // CHECK18-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 7537 // CHECK18-NEXT: store i64 2, i64* [[TMP22]], align 8 7538 // CHECK18-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7539 // CHECK18-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 7540 // CHECK18-NEXT: store i64 2, i64* [[TMP24]], align 8 7541 // CHECK18-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 7542 // CHECK18-NEXT: store i8* null, i8** [[TMP25]], align 8 7543 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 7544 // CHECK18-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 7545 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 7546 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 7547 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 7548 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 7549 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 7550 // CHECK18-NEXT: store i8* null, i8** [[TMP30]], align 8 7551 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 7552 // CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 7553 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 7554 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 7555 // CHECK18-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 7556 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 7557 // CHECK18-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 7558 // CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 7559 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 7560 // CHECK18-NEXT: store i8* null, i8** [[TMP36]], align 8 7561 // CHECK18-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7562 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7563 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 7564 // CHECK18-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7565 // CHECK18-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 7566 // CHECK18-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7567 // CHECK18: omp_offload.failed: 7568 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 7569 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 7570 // CHECK18: omp_offload.cont: 7571 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 7572 // CHECK18: omp_if.else: 7573 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 7574 // CHECK18-NEXT: br label [[OMP_IF_END]] 7575 // CHECK18: omp_if.end: 7576 // CHECK18-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 7577 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 7578 // CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7579 // CHECK18-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 7580 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 7581 // CHECK18-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 7582 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 7583 // CHECK18-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7584 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 7585 // CHECK18-NEXT: ret i32 [[ADD4]] 7586 // 7587 // 7588 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici 7589 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 7590 // CHECK18-NEXT: entry: 7591 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7592 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 7593 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 7594 // CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 7595 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7596 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7597 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7598 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 7599 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 7600 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 7601 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 7602 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7603 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 7604 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 7605 // CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 7606 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7607 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7608 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 7609 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7610 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 7611 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7612 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 7613 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7614 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 7615 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 7616 // CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 7617 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 7618 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7619 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 7620 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7621 // CHECK18: omp_if.then: 7622 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7623 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 7624 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 7625 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7626 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 7627 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 7628 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 7629 // CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 7630 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7631 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 7632 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 7633 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7634 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 7635 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 7636 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 7637 // CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 7638 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7639 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 7640 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 7641 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7642 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 7643 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 7644 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 7645 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 7646 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 7647 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 7648 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 7649 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 7650 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 7651 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 7652 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 7653 // CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 7654 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7655 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7656 // CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7657 // CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 7658 // CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7659 // CHECK18: omp_offload.failed: 7660 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 7661 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 7662 // CHECK18: omp_offload.cont: 7663 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 7664 // CHECK18: omp_if.else: 7665 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 7666 // CHECK18-NEXT: br label [[OMP_IF_END]] 7667 // CHECK18: omp_if.end: 7668 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 7669 // CHECK18-NEXT: ret i32 [[TMP31]] 7670 // 7671 // 7672 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7673 // CHECK18-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 7674 // CHECK18-NEXT: entry: 7675 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7676 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 7677 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 7678 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7679 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7680 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7681 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 7682 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 7683 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 7684 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7685 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 7686 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 7687 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7688 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7689 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 7690 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7691 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 7692 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7693 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 7694 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7695 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7696 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 7697 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7698 // CHECK18: omp_if.then: 7699 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7700 // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 7701 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 7702 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7703 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 7704 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 7705 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 7706 // CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 7707 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7708 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 7709 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 7710 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7711 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 7712 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 7713 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 7714 // CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 7715 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7716 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 7717 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 7718 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7719 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 7720 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 7721 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 7722 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 7723 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7724 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7725 // CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7726 // CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 7727 // CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7728 // CHECK18: omp_offload.failed: 7729 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 7730 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 7731 // CHECK18: omp_offload.cont: 7732 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 7733 // CHECK18: omp_if.else: 7734 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 7735 // CHECK18-NEXT: br label [[OMP_IF_END]] 7736 // CHECK18: omp_if.end: 7737 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 7738 // CHECK18-NEXT: ret i32 [[TMP24]] 7739 // 7740 // 7741 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 7742 // CHECK18-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 7743 // CHECK18-NEXT: entry: 7744 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7745 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7746 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7747 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7748 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7749 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 7750 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7751 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7752 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7753 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7754 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7755 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7756 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7757 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7758 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7759 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7760 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 7761 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 7762 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 7763 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 7764 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 7765 // CHECK18-NEXT: ret void 7766 // 7767 // 7768 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..10 7769 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 7770 // CHECK18-NEXT: entry: 7771 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7772 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7773 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7774 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7775 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7776 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7777 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7778 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7779 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7780 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7781 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7782 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7783 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7784 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7785 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7786 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7787 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7788 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7789 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7790 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 7791 // CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 7792 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 7793 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 7794 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 7795 // CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 7796 // CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 7797 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 7798 // CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 7799 // CHECK18-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 7800 // CHECK18-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 7801 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 7802 // CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7803 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 7804 // CHECK18-NEXT: ret void 7805 // 7806 // 7807 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 7808 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 7809 // CHECK18-NEXT: entry: 7810 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7811 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7812 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7813 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7814 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7815 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7816 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 7817 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7818 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7819 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7820 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7821 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7822 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7823 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7824 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7825 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7826 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7827 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 7828 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7829 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 7830 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7831 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 7832 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7833 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 7834 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 7835 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 7836 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 7837 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 7838 // CHECK18-NEXT: ret void 7839 // 7840 // 7841 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..13 7842 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 7843 // CHECK18-NEXT: entry: 7844 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7845 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7846 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7847 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7848 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7849 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7850 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7851 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7852 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7853 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7854 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7855 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7856 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7857 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7858 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7859 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7860 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7861 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7862 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7863 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 7864 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 7865 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 7866 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 7867 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 7868 // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 7869 // CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 7870 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 7871 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 7872 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 7873 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7874 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7875 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 7876 // CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 7877 // CHECK18-NEXT: ret void 7878 // 7879 // 7880 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 7881 // CHECK18-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 7882 // CHECK18-NEXT: entry: 7883 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7884 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7885 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7886 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7887 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7888 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7889 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7890 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7891 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7892 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7893 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7894 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7895 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7896 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 7897 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7898 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 7899 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7900 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 7901 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7902 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 7903 // CHECK18-NEXT: ret void 7904 // 7905 // 7906 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..16 7907 // CHECK18-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 7908 // CHECK18-NEXT: entry: 7909 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7910 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7911 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7912 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7913 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7914 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7915 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7916 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7917 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7918 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7919 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7920 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7921 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7922 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7923 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7924 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7925 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 7926 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 7927 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 7928 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 7929 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 7930 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7931 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7932 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 7933 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 7934 // CHECK18-NEXT: ret void 7935 // 7936 // 7937 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 7938 // CHECK18-SAME: () #[[ATTR8:[0-9]+]] { 7939 // CHECK18-NEXT: entry: 7940 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 7941 // CHECK18-NEXT: ret void 7942 // 7943 // 7944 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi 7945 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 7946 // CHECK19-NEXT: entry: 7947 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7948 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 7949 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 7950 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7951 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 7952 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 7953 // CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7954 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 7955 // CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 7956 // CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 7957 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 7958 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 7959 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 7960 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 7961 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 7962 // CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 7963 // CHECK19-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 7964 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 7965 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 7966 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 7967 // CHECK19-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 7968 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 7969 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 7970 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 7971 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 7972 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 7973 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7974 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 7975 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 7976 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7977 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 7978 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 7979 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 7980 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 7981 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 7982 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 7983 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 7984 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 7985 // CHECK19-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 7986 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 7987 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 7988 // CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 7989 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 7990 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 7991 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 7992 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 7993 // CHECK19-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 7994 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 7995 // CHECK19-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 7996 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 7997 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7998 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 7999 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 8000 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8001 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 8002 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 8003 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 8004 // CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 8005 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8006 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8007 // CHECK19-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8008 // CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 8009 // CHECK19-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8010 // CHECK19: omp_offload.failed: 8011 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 8012 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 8013 // CHECK19: omp_offload.cont: 8014 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 8015 // CHECK19-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 8016 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 8017 // CHECK19-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 8018 // CHECK19-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 8019 // CHECK19-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 8020 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 8021 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 8022 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 8023 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8024 // CHECK19: omp_if.then: 8025 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 8026 // CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 8027 // CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 8028 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 8029 // CHECK19-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 8030 // CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 8031 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 8032 // CHECK19-NEXT: store i8* null, i8** [[TMP31]], align 4 8033 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 8034 // CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* 8035 // CHECK19-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 8036 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 8037 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 8038 // CHECK19-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 8039 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 8040 // CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 8041 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 8042 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 8043 // CHECK19-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8044 // CHECK19-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 8045 // CHECK19-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 8046 // CHECK19: omp_offload.failed8: 8047 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 8048 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT9]] 8049 // CHECK19: omp_offload.cont9: 8050 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 8051 // CHECK19: omp_if.else: 8052 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 8053 // CHECK19-NEXT: br label [[OMP_IF_END]] 8054 // CHECK19: omp_if.end: 8055 // CHECK19-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 8056 // CHECK19-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 8057 // CHECK19-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 8058 // CHECK19-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 8059 // CHECK19-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 8060 // CHECK19-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] 8061 // CHECK19: omp_if.then12: 8062 // CHECK19-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 8063 // CHECK19-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 8064 // CHECK19-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] 8065 // CHECK19-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 8066 // CHECK19-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 8067 // CHECK19-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 8068 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i32 72, i1 false) 8069 // CHECK19-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 8070 // CHECK19-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 8071 // CHECK19-NEXT: store i32 [[TMP42]], i32* [[TMP51]], align 4 8072 // CHECK19-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 8073 // CHECK19-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 8074 // CHECK19-NEXT: store i32 [[TMP42]], i32* [[TMP53]], align 4 8075 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 8076 // CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 8077 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 8078 // CHECK19-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 8079 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 8080 // CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 8081 // CHECK19-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 8082 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 8083 // CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 8084 // CHECK19-NEXT: store i8* null, i8** [[TMP59]], align 4 8085 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 8086 // CHECK19-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32* 8087 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP61]], align 4 8088 // CHECK19-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 8089 // CHECK19-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 8090 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP63]], align 4 8091 // CHECK19-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 8092 // CHECK19-NEXT: store i8* null, i8** [[TMP64]], align 4 8093 // CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 8094 // CHECK19-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 8095 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP66]], align 4 8096 // CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 8097 // CHECK19-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 8098 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 8099 // CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 8100 // CHECK19-NEXT: store i64 [[TMP45]], i64* [[TMP69]], align 4 8101 // CHECK19-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 8102 // CHECK19-NEXT: store i8* null, i8** [[TMP70]], align 4 8103 // CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 8104 // CHECK19-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 8105 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 4 8106 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 8107 // CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 8108 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 8109 // CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 8110 // CHECK19-NEXT: store i8* null, i8** [[TMP75]], align 4 8111 // CHECK19-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 8112 // CHECK19-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* 8113 // CHECK19-NEXT: store i32 5, i32* [[TMP77]], align 4 8114 // CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 8115 // CHECK19-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 8116 // CHECK19-NEXT: store i32 5, i32* [[TMP79]], align 4 8117 // CHECK19-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 8118 // CHECK19-NEXT: store i8* null, i8** [[TMP80]], align 4 8119 // CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 8120 // CHECK19-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* 8121 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP82]], align 4 8122 // CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 8123 // CHECK19-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32* 8124 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP84]], align 4 8125 // CHECK19-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 8126 // CHECK19-NEXT: store i8* null, i8** [[TMP85]], align 4 8127 // CHECK19-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 8128 // CHECK19-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 8129 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP87]], align 4 8130 // CHECK19-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 8131 // CHECK19-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 8132 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP89]], align 4 8133 // CHECK19-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 8134 // CHECK19-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 4 8135 // CHECK19-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 8136 // CHECK19-NEXT: store i8* null, i8** [[TMP91]], align 4 8137 // CHECK19-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 8138 // CHECK19-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 8139 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 4 8140 // CHECK19-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 8141 // CHECK19-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 8142 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 4 8143 // CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 8144 // CHECK19-NEXT: store i8* null, i8** [[TMP96]], align 4 8145 // CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 8146 // CHECK19-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 8147 // CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 8148 // CHECK19-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8149 // CHECK19-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 8150 // CHECK19-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 8151 // CHECK19: omp_offload.failed16: 8152 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 8153 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT17]] 8154 // CHECK19: omp_offload.cont17: 8155 // CHECK19-NEXT: br label [[OMP_IF_END19:%.*]] 8156 // CHECK19: omp_if.else18: 8157 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 8158 // CHECK19-NEXT: br label [[OMP_IF_END19]] 8159 // CHECK19: omp_if.end19: 8160 // CHECK19-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 8161 // CHECK19-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8162 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 8163 // CHECK19-NEXT: ret i32 [[TMP102]] 8164 // 8165 // 8166 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 8167 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] { 8168 // CHECK19-NEXT: entry: 8169 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 8170 // CHECK19-NEXT: ret void 8171 // 8172 // 8173 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 8174 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 8175 // CHECK19-NEXT: entry: 8176 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8177 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8178 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8179 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8180 // CHECK19-NEXT: ret void 8181 // 8182 // 8183 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. 8184 // CHECK19-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 8185 // CHECK19-NEXT: entry: 8186 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 8187 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 8188 // CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 8189 // CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 8190 // CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 8191 // CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 8192 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 8193 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 8194 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 8195 // CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 8196 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 8197 // CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 8198 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 8199 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 8200 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 8201 // CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 8202 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 8203 // CHECK19-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 8204 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 8205 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 8206 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 8207 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 8208 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 8209 // CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 8210 // CHECK19-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 8211 // CHECK19-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 8212 // CHECK19-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 8213 // CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 8214 // CHECK19-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 8215 // CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 8216 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 8217 // CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 8218 // CHECK19: omp_offload.failed.i: 8219 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 8220 // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 8221 // CHECK19: .omp_outlined..1.exit: 8222 // CHECK19-NEXT: ret i32 0 8223 // 8224 // 8225 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 8226 // CHECK19-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { 8227 // CHECK19-NEXT: entry: 8228 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8229 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8230 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8231 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8232 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8233 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8234 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8235 // CHECK19-NEXT: ret void 8236 // 8237 // 8238 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 8239 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 8240 // CHECK19-NEXT: entry: 8241 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8242 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8243 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8244 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8245 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8246 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8247 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8248 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8249 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8250 // CHECK19-NEXT: ret void 8251 // 8252 // 8253 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 8254 // CHECK19-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 8255 // CHECK19-NEXT: entry: 8256 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8257 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8258 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8259 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8260 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 8261 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8262 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 8263 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8264 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8265 // CHECK19-NEXT: ret void 8266 // 8267 // 8268 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 8269 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 8270 // CHECK19-NEXT: entry: 8271 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8272 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8273 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8274 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8275 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8276 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8277 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8278 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 8279 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 8280 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 8281 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 8282 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 8283 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8284 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 8285 // CHECK19-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 8286 // CHECK19-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 8287 // CHECK19-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 8288 // CHECK19: .cancel.exit: 8289 // CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 8290 // CHECK19-NEXT: br label [[DOTCANCEL_CONTINUE]] 8291 // CHECK19: .cancel.continue: 8292 // CHECK19-NEXT: ret void 8293 // 8294 // 8295 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 8296 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 8297 // CHECK19-NEXT: entry: 8298 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8299 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8300 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8301 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8302 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8303 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8304 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8305 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8306 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8307 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8308 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 8309 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8310 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 8311 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8312 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 8313 // CHECK19-NEXT: ret void 8314 // 8315 // 8316 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 8317 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 8318 // CHECK19-NEXT: entry: 8319 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8320 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8321 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8322 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8323 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8324 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8325 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8326 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8327 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8328 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8329 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8330 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8331 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 8332 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 8333 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 8334 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8335 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 8336 // CHECK19-NEXT: ret void 8337 // 8338 // 8339 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 8340 // CHECK19-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 8341 // CHECK19-NEXT: entry: 8342 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8343 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8344 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8345 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8346 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8347 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8348 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8349 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8350 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8351 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8352 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8353 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8354 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8355 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8356 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8357 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8358 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8359 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8360 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8361 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8362 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8363 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8364 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8365 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8366 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8367 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8368 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8369 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8370 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 8371 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 8372 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 8373 // CHECK19-NEXT: ret void 8374 // 8375 // 8376 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 8377 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 8378 // CHECK19-NEXT: entry: 8379 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8380 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8381 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8382 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8383 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8384 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8385 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8386 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8387 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8388 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8389 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8390 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8391 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8392 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8393 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8394 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8395 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8396 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8397 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8398 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8399 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8400 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8401 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8402 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8403 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8404 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8405 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8406 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8407 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8408 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8409 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8410 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 8411 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8412 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 8413 // CHECK19-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 8414 // CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 8415 // CHECK19-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 8416 // CHECK19-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 8417 // CHECK19-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 8418 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 8419 // CHECK19-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 8420 // CHECK19-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 8421 // CHECK19-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 8422 // CHECK19-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 8423 // CHECK19-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 8424 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 8425 // CHECK19-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 8426 // CHECK19-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 8427 // CHECK19-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 8428 // CHECK19-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 8429 // CHECK19-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 8430 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 8431 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 8432 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 8433 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 8434 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 8435 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 8436 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 8437 // CHECK19-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 8438 // CHECK19-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 8439 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 8440 // CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 8441 // CHECK19-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 8442 // CHECK19-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 8443 // CHECK19-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 8444 // CHECK19-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 8445 // CHECK19-NEXT: ret void 8446 // 8447 // 8448 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari 8449 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8450 // CHECK19-NEXT: entry: 8451 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8452 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 8453 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 8454 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8455 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 8456 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8457 // CHECK19-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 8458 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 8459 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8460 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8461 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8462 // CHECK19-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 8463 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 8464 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8465 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 8466 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8467 // CHECK19-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 8468 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8469 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8470 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 8471 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8472 // CHECK19-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 8473 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8474 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8475 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 8476 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8477 // CHECK19-NEXT: ret i32 [[TMP8]] 8478 // 8479 // 8480 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8481 // CHECK19-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8482 // CHECK19-NEXT: entry: 8483 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8484 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8485 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 8486 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8487 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8488 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 8489 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 8490 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 8491 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 8492 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 8493 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8494 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8495 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8496 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8497 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8498 // CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 8499 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8500 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8501 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 8502 // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 8503 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 8504 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 8505 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 8506 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 8507 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 8508 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8509 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 8510 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8511 // CHECK19: omp_if.then: 8512 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8513 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 8514 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 8515 // CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 8516 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 8517 // CHECK19-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 8518 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8519 // CHECK19-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 8520 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 8521 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8522 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 8523 // CHECK19-NEXT: store double* [[A]], double** [[TMP14]], align 4 8524 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 8525 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 8526 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 8527 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 8528 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 8529 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 8530 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 8531 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 8532 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 8533 // CHECK19-NEXT: store i8* null, i8** [[TMP20]], align 4 8534 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 8535 // CHECK19-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 8536 // CHECK19-NEXT: store i32 2, i32* [[TMP22]], align 4 8537 // CHECK19-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 8538 // CHECK19-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 8539 // CHECK19-NEXT: store i32 2, i32* [[TMP24]], align 4 8540 // CHECK19-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 8541 // CHECK19-NEXT: store i8* null, i8** [[TMP25]], align 4 8542 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 8543 // CHECK19-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 8544 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 8545 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 8546 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 8547 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 8548 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 8549 // CHECK19-NEXT: store i8* null, i8** [[TMP30]], align 4 8550 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 8551 // CHECK19-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 8552 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 8553 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 8554 // CHECK19-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 8555 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 8556 // CHECK19-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 8557 // CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 8558 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 8559 // CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 8560 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8561 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8562 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 8563 // CHECK19-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8564 // CHECK19-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 8565 // CHECK19-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8566 // CHECK19: omp_offload.failed: 8567 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 8568 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 8569 // CHECK19: omp_offload.cont: 8570 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 8571 // CHECK19: omp_if.else: 8572 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 8573 // CHECK19-NEXT: br label [[OMP_IF_END]] 8574 // CHECK19: omp_if.end: 8575 // CHECK19-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 8576 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 8577 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8578 // CHECK19-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 8579 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 8580 // CHECK19-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 8581 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 8582 // CHECK19-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8583 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 8584 // CHECK19-NEXT: ret i32 [[ADD3]] 8585 // 8586 // 8587 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici 8588 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 8589 // CHECK19-NEXT: entry: 8590 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8591 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 8592 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 8593 // CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 8594 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8595 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8596 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8597 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 8598 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 8599 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 8600 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 8601 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8602 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 8603 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 8604 // CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 8605 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8606 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8607 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8608 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 8609 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8610 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 8611 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8612 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 8613 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 8614 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 8615 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 8616 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8617 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 8618 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8619 // CHECK19: omp_if.then: 8620 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8621 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 8622 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 8623 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8624 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 8625 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 8626 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 8627 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 8628 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 8629 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 8630 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 8631 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 8632 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 8633 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 8634 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 8635 // CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 8636 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 8637 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 8638 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 8639 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 8640 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 8641 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 8642 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 8643 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 8644 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 8645 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 8646 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 8647 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 8648 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 8649 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 8650 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 8651 // CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 8652 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8653 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8654 // CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8655 // CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 8656 // CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8657 // CHECK19: omp_offload.failed: 8658 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 8659 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 8660 // CHECK19: omp_offload.cont: 8661 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 8662 // CHECK19: omp_if.else: 8663 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 8664 // CHECK19-NEXT: br label [[OMP_IF_END]] 8665 // CHECK19: omp_if.end: 8666 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 8667 // CHECK19-NEXT: ret i32 [[TMP31]] 8668 // 8669 // 8670 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8671 // CHECK19-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 8672 // CHECK19-NEXT: entry: 8673 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8674 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 8675 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 8676 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8677 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8678 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8679 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 8680 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 8681 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 8682 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8683 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 8684 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 8685 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8686 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8687 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8688 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 8689 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8690 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 8691 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8692 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8693 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 8694 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8695 // CHECK19: omp_if.then: 8696 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8697 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 8698 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 8699 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8700 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 8701 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 8702 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 8703 // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 8704 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 8705 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 8706 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 8707 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 8708 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 8709 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 8710 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 8711 // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 8712 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 8713 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 8714 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 8715 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 8716 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 8717 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 8718 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 8719 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 8720 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8721 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8722 // CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8723 // CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 8724 // CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8725 // CHECK19: omp_offload.failed: 8726 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 8727 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 8728 // CHECK19: omp_offload.cont: 8729 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 8730 // CHECK19: omp_if.else: 8731 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 8732 // CHECK19-NEXT: br label [[OMP_IF_END]] 8733 // CHECK19: omp_if.end: 8734 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 8735 // CHECK19-NEXT: ret i32 [[TMP24]] 8736 // 8737 // 8738 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 8739 // CHECK19-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 8740 // CHECK19-NEXT: entry: 8741 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8742 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8743 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8744 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8745 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8746 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 8747 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8748 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8749 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8750 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8751 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8752 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8753 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8754 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8755 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8756 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8757 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 8758 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 8759 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 8760 // CHECK19-NEXT: ret void 8761 // 8762 // 8763 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..10 8764 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 8765 // CHECK19-NEXT: entry: 8766 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8767 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8768 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8769 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8770 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8771 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8772 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8773 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8774 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8775 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8776 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8777 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8778 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8779 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8780 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8781 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8782 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8783 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8784 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8785 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 8786 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 8787 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 8788 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 8789 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 8790 // CHECK19-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 8791 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 8792 // CHECK19-NEXT: store double [[INC]], double* [[A3]], align 4 8793 // CHECK19-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 8794 // CHECK19-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 8795 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 8796 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8797 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 8798 // CHECK19-NEXT: ret void 8799 // 8800 // 8801 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 8802 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 8803 // CHECK19-NEXT: entry: 8804 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8805 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8806 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8807 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8808 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8809 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8810 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 8811 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8812 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8813 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8814 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8815 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8816 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8817 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8818 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8819 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8820 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8821 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 8822 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8823 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 8824 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8825 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 8826 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 8827 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 8828 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 8829 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 8830 // CHECK19-NEXT: ret void 8831 // 8832 // 8833 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..13 8834 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 8835 // CHECK19-NEXT: entry: 8836 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8837 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8838 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8839 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8840 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8841 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8842 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8843 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8844 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8845 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8846 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8847 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8848 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8849 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8850 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8851 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8852 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 8853 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8854 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 8855 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 8856 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 8857 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 8858 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 8859 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 8860 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 8861 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 8862 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 8863 // CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 8864 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 8865 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8866 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 8867 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 8868 // CHECK19-NEXT: ret void 8869 // 8870 // 8871 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 8872 // CHECK19-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 8873 // CHECK19-NEXT: entry: 8874 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8875 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8876 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8877 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8878 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8879 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8880 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8881 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8882 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8883 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8884 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8885 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8886 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8887 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 8888 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8889 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 8890 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8891 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 8892 // CHECK19-NEXT: ret void 8893 // 8894 // 8895 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..16 8896 // CHECK19-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 8897 // CHECK19-NEXT: entry: 8898 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8899 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8900 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8901 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8902 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8903 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8904 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8905 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8906 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8907 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8908 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8909 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8910 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8911 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 8912 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8913 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 8914 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 8915 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 8916 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8917 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 8918 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 8919 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8920 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 8921 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 8922 // CHECK19-NEXT: ret void 8923 // 8924 // 8925 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 8926 // CHECK19-SAME: () #[[ATTR8:[0-9]+]] { 8927 // CHECK19-NEXT: entry: 8928 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 8929 // CHECK19-NEXT: ret void 8930 // 8931 // 8932 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi 8933 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 8934 // CHECK20-NEXT: entry: 8935 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8936 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 8937 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 8938 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8939 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8940 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8941 // CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8942 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 8943 // CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 8944 // CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 8945 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8946 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8947 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 8948 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 8949 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 8950 // CHECK20-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 8951 // CHECK20-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 8952 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 8953 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 8954 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 8955 // CHECK20-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 8956 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 8957 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 8958 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 8959 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 8960 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 8961 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8962 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 8963 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 8964 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8965 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8966 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 8967 // CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 8968 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 8969 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 8970 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 8971 // CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 8972 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 8973 // CHECK20-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 8974 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 8975 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 8976 // CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 8977 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 8978 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 8979 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 8980 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 8981 // CHECK20-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 8982 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8983 // CHECK20-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 8984 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8985 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8986 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 8987 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 8988 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8989 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 8990 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 8991 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 8992 // CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 8993 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8994 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8995 // CHECK20-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8996 // CHECK20-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 8997 // CHECK20-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8998 // CHECK20: omp_offload.failed: 8999 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 9000 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 9001 // CHECK20: omp_offload.cont: 9002 // CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 9003 // CHECK20-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 9004 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 9005 // CHECK20-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 9006 // CHECK20-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 9007 // CHECK20-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 9008 // CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 9009 // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 9010 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 9011 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9012 // CHECK20: omp_if.then: 9013 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 9014 // CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 9015 // CHECK20-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 9016 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 9017 // CHECK20-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 9018 // CHECK20-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 9019 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 9020 // CHECK20-NEXT: store i8* null, i8** [[TMP31]], align 4 9021 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 9022 // CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* 9023 // CHECK20-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 9024 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 9025 // CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 9026 // CHECK20-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 9027 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 9028 // CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 9029 // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 9030 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 9031 // CHECK20-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9032 // CHECK20-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 9033 // CHECK20-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 9034 // CHECK20: omp_offload.failed8: 9035 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 9036 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT9]] 9037 // CHECK20: omp_offload.cont9: 9038 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 9039 // CHECK20: omp_if.else: 9040 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 9041 // CHECK20-NEXT: br label [[OMP_IF_END]] 9042 // CHECK20: omp_if.end: 9043 // CHECK20-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 9044 // CHECK20-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 9045 // CHECK20-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 9046 // CHECK20-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 9047 // CHECK20-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 9048 // CHECK20-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] 9049 // CHECK20: omp_if.then12: 9050 // CHECK20-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 9051 // CHECK20-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 9052 // CHECK20-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] 9053 // CHECK20-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 9054 // CHECK20-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 9055 // CHECK20-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 9056 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i32 72, i1 false) 9057 // CHECK20-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 9058 // CHECK20-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 9059 // CHECK20-NEXT: store i32 [[TMP42]], i32* [[TMP51]], align 4 9060 // CHECK20-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 9061 // CHECK20-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 9062 // CHECK20-NEXT: store i32 [[TMP42]], i32* [[TMP53]], align 4 9063 // CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 9064 // CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 9065 // CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 9066 // CHECK20-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 9067 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 9068 // CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 9069 // CHECK20-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 9070 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 9071 // CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 9072 // CHECK20-NEXT: store i8* null, i8** [[TMP59]], align 4 9073 // CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 9074 // CHECK20-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32* 9075 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP61]], align 4 9076 // CHECK20-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 9077 // CHECK20-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 9078 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP63]], align 4 9079 // CHECK20-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 9080 // CHECK20-NEXT: store i8* null, i8** [[TMP64]], align 4 9081 // CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 9082 // CHECK20-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 9083 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP66]], align 4 9084 // CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 9085 // CHECK20-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 9086 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 9087 // CHECK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 9088 // CHECK20-NEXT: store i64 [[TMP45]], i64* [[TMP69]], align 4 9089 // CHECK20-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 9090 // CHECK20-NEXT: store i8* null, i8** [[TMP70]], align 4 9091 // CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 9092 // CHECK20-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 9093 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 4 9094 // CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 9095 // CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 9096 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 9097 // CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 9098 // CHECK20-NEXT: store i8* null, i8** [[TMP75]], align 4 9099 // CHECK20-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 9100 // CHECK20-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* 9101 // CHECK20-NEXT: store i32 5, i32* [[TMP77]], align 4 9102 // CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 9103 // CHECK20-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 9104 // CHECK20-NEXT: store i32 5, i32* [[TMP79]], align 4 9105 // CHECK20-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 9106 // CHECK20-NEXT: store i8* null, i8** [[TMP80]], align 4 9107 // CHECK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 9108 // CHECK20-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* 9109 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP82]], align 4 9110 // CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 9111 // CHECK20-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32* 9112 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP84]], align 4 9113 // CHECK20-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 9114 // CHECK20-NEXT: store i8* null, i8** [[TMP85]], align 4 9115 // CHECK20-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 9116 // CHECK20-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 9117 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP87]], align 4 9118 // CHECK20-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 9119 // CHECK20-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 9120 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP89]], align 4 9121 // CHECK20-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 9122 // CHECK20-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 4 9123 // CHECK20-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 9124 // CHECK20-NEXT: store i8* null, i8** [[TMP91]], align 4 9125 // CHECK20-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 9126 // CHECK20-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 9127 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 4 9128 // CHECK20-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 9129 // CHECK20-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 9130 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 4 9131 // CHECK20-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 9132 // CHECK20-NEXT: store i8* null, i8** [[TMP96]], align 4 9133 // CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 9134 // CHECK20-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 9135 // CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 9136 // CHECK20-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9137 // CHECK20-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 9138 // CHECK20-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 9139 // CHECK20: omp_offload.failed16: 9140 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 9141 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT17]] 9142 // CHECK20: omp_offload.cont17: 9143 // CHECK20-NEXT: br label [[OMP_IF_END19:%.*]] 9144 // CHECK20: omp_if.else18: 9145 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 9146 // CHECK20-NEXT: br label [[OMP_IF_END19]] 9147 // CHECK20: omp_if.end19: 9148 // CHECK20-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 9149 // CHECK20-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9150 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 9151 // CHECK20-NEXT: ret i32 [[TMP102]] 9152 // 9153 // 9154 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 9155 // CHECK20-SAME: () #[[ATTR2:[0-9]+]] { 9156 // CHECK20-NEXT: entry: 9157 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 9158 // CHECK20-NEXT: ret void 9159 // 9160 // 9161 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 9162 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 9163 // CHECK20-NEXT: entry: 9164 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9165 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9166 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9167 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9168 // CHECK20-NEXT: ret void 9169 // 9170 // 9171 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. 9172 // CHECK20-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 9173 // CHECK20-NEXT: entry: 9174 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 9175 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 9176 // CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 9177 // CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 9178 // CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 9179 // CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 9180 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 9181 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 9182 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 9183 // CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 9184 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 9185 // CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 9186 // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 9187 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 9188 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 9189 // CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 9190 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 9191 // CHECK20-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 9192 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 9193 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 9194 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 9195 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 9196 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 9197 // CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 9198 // CHECK20-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 9199 // CHECK20-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 9200 // CHECK20-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 9201 // CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 9202 // CHECK20-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 9203 // CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 9204 // CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 9205 // CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 9206 // CHECK20: omp_offload.failed.i: 9207 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 9208 // CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 9209 // CHECK20: .omp_outlined..1.exit: 9210 // CHECK20-NEXT: ret i32 0 9211 // 9212 // 9213 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 9214 // CHECK20-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { 9215 // CHECK20-NEXT: entry: 9216 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9217 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9218 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9219 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9220 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9221 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9222 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 9223 // CHECK20-NEXT: ret void 9224 // 9225 // 9226 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 9227 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 9228 // CHECK20-NEXT: entry: 9229 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9230 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9231 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9232 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9233 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9234 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9235 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9236 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9237 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9238 // CHECK20-NEXT: ret void 9239 // 9240 // 9241 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 9242 // CHECK20-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 9243 // CHECK20-NEXT: entry: 9244 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9245 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9246 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9247 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9248 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9249 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9250 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 9251 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9252 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 9253 // CHECK20-NEXT: ret void 9254 // 9255 // 9256 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 9257 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 9258 // CHECK20-NEXT: entry: 9259 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9260 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9261 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9262 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9263 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9264 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9265 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9266 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9267 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 9268 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 9269 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 9270 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 9271 // CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9272 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 9273 // CHECK20-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 9274 // CHECK20-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 9275 // CHECK20-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 9276 // CHECK20: .cancel.exit: 9277 // CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 9278 // CHECK20-NEXT: br label [[DOTCANCEL_CONTINUE]] 9279 // CHECK20: .cancel.continue: 9280 // CHECK20-NEXT: ret void 9281 // 9282 // 9283 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 9284 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 9285 // CHECK20-NEXT: entry: 9286 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9287 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9288 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9289 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9290 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9291 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9292 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9293 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9294 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9295 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9296 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 9297 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9298 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 9299 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9300 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 9301 // CHECK20-NEXT: ret void 9302 // 9303 // 9304 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 9305 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 9306 // CHECK20-NEXT: entry: 9307 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9308 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9309 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9310 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9311 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9312 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9313 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9314 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9315 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9316 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9317 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9318 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9319 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 9320 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 9321 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 9322 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 9323 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 9324 // CHECK20-NEXT: ret void 9325 // 9326 // 9327 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 9328 // CHECK20-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 9329 // CHECK20-NEXT: entry: 9330 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9331 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9332 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9333 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9334 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9335 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9336 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9337 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9338 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9339 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9340 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9341 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9342 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9343 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9344 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9345 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9346 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9347 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9348 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9349 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9350 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9351 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9352 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9353 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9354 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9355 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9356 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9357 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 9358 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 9359 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 9360 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 9361 // CHECK20-NEXT: ret void 9362 // 9363 // 9364 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 9365 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 9366 // CHECK20-NEXT: entry: 9367 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9368 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9369 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9370 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9371 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9372 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9373 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9374 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9375 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9376 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9377 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9378 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9379 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9380 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9381 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9382 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9383 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9384 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9385 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9386 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9387 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9388 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9389 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9390 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9391 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9392 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9393 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9394 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9395 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9396 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9397 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 9398 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 9399 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9400 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 9401 // CHECK20-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 9402 // CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 9403 // CHECK20-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 9404 // CHECK20-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 9405 // CHECK20-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 9406 // CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 9407 // CHECK20-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 9408 // CHECK20-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 9409 // CHECK20-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 9410 // CHECK20-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 9411 // CHECK20-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 9412 // CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 9413 // CHECK20-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 9414 // CHECK20-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 9415 // CHECK20-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 9416 // CHECK20-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 9417 // CHECK20-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 9418 // CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 9419 // CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 9420 // CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 9421 // CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 9422 // CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 9423 // CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 9424 // CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 9425 // CHECK20-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 9426 // CHECK20-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 9427 // CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 9428 // CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 9429 // CHECK20-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 9430 // CHECK20-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 9431 // CHECK20-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 9432 // CHECK20-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 9433 // CHECK20-NEXT: ret void 9434 // 9435 // 9436 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari 9437 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 9438 // CHECK20-NEXT: entry: 9439 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9440 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 9441 // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 9442 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9443 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 9444 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9445 // CHECK20-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 9446 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 9447 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 9448 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9449 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 9450 // CHECK20-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 9451 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9452 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 9453 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 9454 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9455 // CHECK20-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 9456 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 9457 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 9458 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 9459 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9460 // CHECK20-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 9461 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 9462 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 9463 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 9464 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9465 // CHECK20-NEXT: ret i32 [[TMP8]] 9466 // 9467 // 9468 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 9469 // CHECK20-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 9470 // CHECK20-NEXT: entry: 9471 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9472 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9473 // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 9474 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 9475 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 9476 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 9477 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 9478 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 9479 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 9480 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 9481 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9482 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9483 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9484 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9485 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9486 // CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 9487 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9488 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 9489 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 9490 // CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 9491 // CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 9492 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 9493 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 9494 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 9495 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 9496 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9497 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 9498 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9499 // CHECK20: omp_if.then: 9500 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 9501 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 9502 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 9503 // CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 9504 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 9505 // CHECK20-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 9506 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9507 // CHECK20-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 9508 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 9509 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9510 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 9511 // CHECK20-NEXT: store double* [[A]], double** [[TMP14]], align 4 9512 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 9513 // CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 9514 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 9515 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 9516 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 9517 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 9518 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 9519 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 9520 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 9521 // CHECK20-NEXT: store i8* null, i8** [[TMP20]], align 4 9522 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 9523 // CHECK20-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 9524 // CHECK20-NEXT: store i32 2, i32* [[TMP22]], align 4 9525 // CHECK20-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 9526 // CHECK20-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 9527 // CHECK20-NEXT: store i32 2, i32* [[TMP24]], align 4 9528 // CHECK20-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 9529 // CHECK20-NEXT: store i8* null, i8** [[TMP25]], align 4 9530 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 9531 // CHECK20-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 9532 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 9533 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 9534 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 9535 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 9536 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 9537 // CHECK20-NEXT: store i8* null, i8** [[TMP30]], align 4 9538 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 9539 // CHECK20-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 9540 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 9541 // CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 9542 // CHECK20-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 9543 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 9544 // CHECK20-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 9545 // CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 9546 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 9547 // CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 9548 // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9549 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9550 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 9551 // CHECK20-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9552 // CHECK20-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 9553 // CHECK20-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9554 // CHECK20: omp_offload.failed: 9555 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 9556 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 9557 // CHECK20: omp_offload.cont: 9558 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 9559 // CHECK20: omp_if.else: 9560 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 9561 // CHECK20-NEXT: br label [[OMP_IF_END]] 9562 // CHECK20: omp_if.end: 9563 // CHECK20-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 9564 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 9565 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9566 // CHECK20-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 9567 // CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 9568 // CHECK20-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 9569 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 9570 // CHECK20-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9571 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 9572 // CHECK20-NEXT: ret i32 [[ADD3]] 9573 // 9574 // 9575 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici 9576 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 9577 // CHECK20-NEXT: entry: 9578 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9579 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 9580 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 9581 // CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 9582 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9583 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9584 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9585 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 9586 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 9587 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 9588 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 9589 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9590 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 9591 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 9592 // CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 9593 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9594 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9595 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9596 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 9597 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9598 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 9599 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9600 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 9601 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 9602 // CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 9603 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 9604 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9605 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 9606 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9607 // CHECK20: omp_if.then: 9608 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9609 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 9610 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 9611 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9612 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 9613 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 9614 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 9615 // CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 9616 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 9617 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 9618 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 9619 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 9620 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 9621 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 9622 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 9623 // CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 9624 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 9625 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 9626 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 9627 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 9628 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 9629 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 9630 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 9631 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 9632 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 9633 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 9634 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 9635 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 9636 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 9637 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 9638 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 9639 // CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 9640 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9641 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9642 // CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9643 // CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 9644 // CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9645 // CHECK20: omp_offload.failed: 9646 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 9647 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 9648 // CHECK20: omp_offload.cont: 9649 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 9650 // CHECK20: omp_if.else: 9651 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 9652 // CHECK20-NEXT: br label [[OMP_IF_END]] 9653 // CHECK20: omp_if.end: 9654 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 9655 // CHECK20-NEXT: ret i32 [[TMP31]] 9656 // 9657 // 9658 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 9659 // CHECK20-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 9660 // CHECK20-NEXT: entry: 9661 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9662 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 9663 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 9664 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9665 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9666 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9667 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 9668 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 9669 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 9670 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9671 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 9672 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 9673 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9674 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9675 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9676 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 9677 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9678 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 9679 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9680 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9681 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 9682 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9683 // CHECK20: omp_if.then: 9684 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9685 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 9686 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 9687 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9688 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 9689 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 9690 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 9691 // CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 9692 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 9693 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 9694 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 9695 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 9696 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 9697 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 9698 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 9699 // CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 9700 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 9701 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 9702 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 9703 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 9704 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 9705 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 9706 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 9707 // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 9708 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9709 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9710 // CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9711 // CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 9712 // CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9713 // CHECK20: omp_offload.failed: 9714 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 9715 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 9716 // CHECK20: omp_offload.cont: 9717 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 9718 // CHECK20: omp_if.else: 9719 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 9720 // CHECK20-NEXT: br label [[OMP_IF_END]] 9721 // CHECK20: omp_if.end: 9722 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 9723 // CHECK20-NEXT: ret i32 [[TMP24]] 9724 // 9725 // 9726 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 9727 // CHECK20-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 9728 // CHECK20-NEXT: entry: 9729 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9730 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 9731 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9732 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9733 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 9734 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 9735 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9736 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 9737 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9738 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9739 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 9740 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9741 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9742 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9743 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 9744 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 9745 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 9746 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 9747 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 9748 // CHECK20-NEXT: ret void 9749 // 9750 // 9751 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..10 9752 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 9753 // CHECK20-NEXT: entry: 9754 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9755 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9756 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9757 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 9758 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9759 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9760 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 9761 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9762 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9763 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9764 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 9765 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9766 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9767 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 9768 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9769 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9770 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9771 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 9772 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 9773 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 9774 // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 9775 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 9776 // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 9777 // CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 9778 // CHECK20-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 9779 // CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 9780 // CHECK20-NEXT: store double [[INC]], double* [[A3]], align 4 9781 // CHECK20-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 9782 // CHECK20-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 9783 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 9784 // CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9785 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 9786 // CHECK20-NEXT: ret void 9787 // 9788 // 9789 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 9790 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 9791 // CHECK20-NEXT: entry: 9792 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9793 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9794 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 9795 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9796 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9797 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9798 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 9799 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9800 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9801 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 9802 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9803 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9804 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 9805 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9806 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9807 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9808 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9809 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9810 // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9811 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 9812 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9813 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 9814 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 9815 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 9816 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 9817 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 9818 // CHECK20-NEXT: ret void 9819 // 9820 // 9821 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..13 9822 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 9823 // CHECK20-NEXT: entry: 9824 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9825 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9826 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9827 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9828 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 9829 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9830 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9831 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9832 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9833 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9834 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 9835 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9836 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9837 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 9838 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9839 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9840 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 9841 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9842 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 9843 // CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 9844 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 9845 // CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9846 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 9847 // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 9848 // CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 9849 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 9850 // CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 9851 // CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 9852 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 9853 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9854 // CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 9855 // CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 9856 // CHECK20-NEXT: ret void 9857 // 9858 // 9859 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 9860 // CHECK20-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 9861 // CHECK20-NEXT: entry: 9862 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9863 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9864 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9865 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9866 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9867 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9868 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9869 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9870 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9871 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9872 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9873 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9874 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9875 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9876 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9877 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 9878 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9879 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 9880 // CHECK20-NEXT: ret void 9881 // 9882 // 9883 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..16 9884 // CHECK20-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 9885 // CHECK20-NEXT: entry: 9886 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9887 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9888 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9889 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9890 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9891 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9892 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9893 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9894 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9895 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9896 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9897 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9898 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9899 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 9900 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9901 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 9902 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 9903 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 9904 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 9905 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 9906 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 9907 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9908 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 9909 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 9910 // CHECK20-NEXT: ret void 9911 // 9912 // 9913 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 9914 // CHECK20-SAME: () #[[ATTR8:[0-9]+]] { 9915 // CHECK20-NEXT: entry: 9916 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 9917 // CHECK20-NEXT: ret void 9918 // 9919 // 9920 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 9921 // CHECK25-SAME: () #[[ATTR0:[0-9]+]] { 9922 // CHECK25-NEXT: entry: 9923 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 9924 // CHECK25-NEXT: ret void 9925 // 9926 // 9927 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. 9928 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 9929 // CHECK25-NEXT: entry: 9930 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9931 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9932 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9933 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9934 // CHECK25-NEXT: ret void 9935 // 9936 // 9937 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 9938 // CHECK25-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 9939 // CHECK25-NEXT: entry: 9940 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9941 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9942 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9943 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9944 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9945 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9946 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 9947 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9948 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 9949 // CHECK25-NEXT: ret void 9950 // 9951 // 9952 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 9953 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 9954 // CHECK25-NEXT: entry: 9955 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 9956 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 9957 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9958 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 9959 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 9960 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9961 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9962 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9963 // CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 9964 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 9965 // CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 9966 // CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 9967 // CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9968 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 9969 // CHECK25-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 9970 // CHECK25-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 9971 // CHECK25-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 9972 // CHECK25: .cancel.exit: 9973 // CHECK25-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 9974 // CHECK25-NEXT: br label [[DOTCANCEL_CONTINUE]] 9975 // CHECK25: .cancel.continue: 9976 // CHECK25-NEXT: ret void 9977 // 9978 // 9979 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 9980 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 9981 // CHECK25-NEXT: entry: 9982 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 9983 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 9984 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 9985 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 9986 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 9987 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 9988 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 9989 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 9990 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 9991 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 9992 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 9993 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 9994 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 9995 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 9996 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 9997 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 9998 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 9999 // CHECK25-NEXT: ret void 10000 // 10001 // 10002 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 10003 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 10004 // CHECK25-NEXT: entry: 10005 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10006 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10007 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10008 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10009 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10010 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10011 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10012 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10013 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10014 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10015 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10016 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10017 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10018 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 10019 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 10020 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10021 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10022 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 10023 // CHECK25-NEXT: ret void 10024 // 10025 // 10026 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 10027 // CHECK25-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 10028 // CHECK25-NEXT: entry: 10029 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10030 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10031 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10032 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10033 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10034 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10035 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10036 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10037 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10038 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10039 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10040 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10041 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10042 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10043 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10044 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10045 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10046 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10047 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10048 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10049 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10050 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10051 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10052 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10053 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10054 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10055 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10056 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10057 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10058 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10059 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 10060 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 10061 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 10062 // CHECK25-NEXT: ret void 10063 // 10064 // 10065 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 10066 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 10067 // CHECK25-NEXT: entry: 10068 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10069 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10070 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10071 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10072 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10073 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10074 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10075 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10076 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10077 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10078 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10079 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10080 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10081 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10082 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10083 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10084 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10085 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10086 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10087 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10088 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10089 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10090 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10091 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10092 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10093 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10094 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10095 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10096 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10097 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10098 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10099 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10100 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 10101 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10102 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 10103 // CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 10104 // CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 10105 // CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 10106 // CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 10107 // CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 10108 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 10109 // CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 10110 // CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 10111 // CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 10112 // CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 10113 // CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 10114 // CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 10115 // CHECK25-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 10116 // CHECK25-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 10117 // CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 10118 // CHECK25-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 10119 // CHECK25-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 10120 // CHECK25-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 10121 // CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 10122 // CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 10123 // CHECK25-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 10124 // CHECK25-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 10125 // CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10126 // CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 10127 // CHECK25-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 10128 // CHECK25-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 10129 // CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10130 // CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 10131 // CHECK25-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 10132 // CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 10133 // CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 10134 // CHECK25-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 10135 // CHECK25-NEXT: ret void 10136 // 10137 // 10138 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 10139 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10140 // CHECK25-NEXT: entry: 10141 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10142 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10143 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10144 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10145 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10146 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10147 // CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 10148 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10149 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10150 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10151 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10152 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10153 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10154 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10155 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10156 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10157 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10158 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 10159 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10160 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10161 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10162 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 10163 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10164 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 10165 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 10166 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 10167 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 10168 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 10169 // CHECK25-NEXT: ret void 10170 // 10171 // 10172 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 10173 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10174 // CHECK25-NEXT: entry: 10175 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10176 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10177 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10178 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10179 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10180 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10181 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10182 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10183 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10184 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10185 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10186 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10187 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10188 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10189 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10190 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10191 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10192 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10193 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10194 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10195 // CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 10196 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10197 // CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10198 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 10199 // CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 10200 // CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 10201 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 10202 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 10203 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 10204 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10205 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10206 // CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 10207 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 10208 // CHECK25-NEXT: ret void 10209 // 10210 // 10211 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 10212 // CHECK25-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10213 // CHECK25-NEXT: entry: 10214 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10215 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10216 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10217 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10218 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10219 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10220 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10221 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10222 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10223 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10224 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10225 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10226 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10227 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10228 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10229 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10230 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10231 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10232 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 10233 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 10234 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 10235 // CHECK25-NEXT: ret void 10236 // 10237 // 10238 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 10239 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10240 // CHECK25-NEXT: entry: 10241 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10242 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10243 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10244 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10245 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10246 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10247 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10248 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10249 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10250 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10251 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10252 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10253 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10254 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10255 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10256 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10257 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10258 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10259 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10260 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10261 // CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 10262 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 10263 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 10264 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 10265 // CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 10266 // CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 10267 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 10268 // CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 10269 // CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10270 // CHECK25-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 10271 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 10272 // CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 10273 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 10274 // CHECK25-NEXT: ret void 10275 // 10276 // 10277 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 10278 // CHECK25-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10279 // CHECK25-NEXT: entry: 10280 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10281 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10282 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10283 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10284 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10285 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10286 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10287 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10288 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10289 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10290 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10291 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10292 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10293 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 10294 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10295 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10296 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10297 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 10298 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10299 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 10300 // CHECK25-NEXT: ret void 10301 // 10302 // 10303 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 10304 // CHECK25-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10305 // CHECK25-NEXT: entry: 10306 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10307 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10308 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10309 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10310 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10311 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10312 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10313 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10314 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10315 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10316 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10317 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10318 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10319 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10320 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10321 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10322 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10323 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 10324 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10325 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10326 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 10327 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10328 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10329 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 10330 // CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 10331 // CHECK25-NEXT: ret void 10332 // 10333 // 10334 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 10335 // CHECK26-SAME: () #[[ATTR0:[0-9]+]] { 10336 // CHECK26-NEXT: entry: 10337 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10338 // CHECK26-NEXT: ret void 10339 // 10340 // 10341 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. 10342 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10343 // CHECK26-NEXT: entry: 10344 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10345 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10346 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10347 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10348 // CHECK26-NEXT: ret void 10349 // 10350 // 10351 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 10352 // CHECK26-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 10353 // CHECK26-NEXT: entry: 10354 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10355 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10356 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10357 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10358 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10359 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10360 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 10361 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10362 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 10363 // CHECK26-NEXT: ret void 10364 // 10365 // 10366 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 10367 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 10368 // CHECK26-NEXT: entry: 10369 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10370 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10371 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10372 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10373 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10374 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10375 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10376 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10377 // CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 10378 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 10379 // CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 10380 // CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 10381 // CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10382 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10383 // CHECK26-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 10384 // CHECK26-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 10385 // CHECK26-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 10386 // CHECK26: .cancel.exit: 10387 // CHECK26-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 10388 // CHECK26-NEXT: br label [[DOTCANCEL_CONTINUE]] 10389 // CHECK26: .cancel.continue: 10390 // CHECK26-NEXT: ret void 10391 // 10392 // 10393 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 10394 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 10395 // CHECK26-NEXT: entry: 10396 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10397 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10398 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10399 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10400 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10401 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10402 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10403 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10404 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10405 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10406 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 10407 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10408 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10409 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10410 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 10411 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10412 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 10413 // CHECK26-NEXT: ret void 10414 // 10415 // 10416 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 10417 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 10418 // CHECK26-NEXT: entry: 10419 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10420 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10421 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10422 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10423 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10424 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10425 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10426 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10427 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10428 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10429 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10430 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10431 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10432 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 10433 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 10434 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10435 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10436 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 10437 // CHECK26-NEXT: ret void 10438 // 10439 // 10440 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 10441 // CHECK26-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 10442 // CHECK26-NEXT: entry: 10443 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10444 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10445 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10446 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10447 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10448 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10449 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10450 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10451 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10452 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10453 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10454 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10455 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10456 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10457 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10458 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10459 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10460 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10461 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10462 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10463 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10464 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10465 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10466 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10467 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10468 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10469 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10470 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10471 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10472 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10473 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 10474 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 10475 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 10476 // CHECK26-NEXT: ret void 10477 // 10478 // 10479 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 10480 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 10481 // CHECK26-NEXT: entry: 10482 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10483 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10484 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10485 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10486 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10487 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10488 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10489 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10490 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10491 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10492 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10493 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10494 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10495 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10496 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10497 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10498 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10499 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10500 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10501 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10502 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10503 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10504 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10505 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10506 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10507 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10508 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10509 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10510 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10511 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10512 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10513 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10514 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 10515 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10516 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 10517 // CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 10518 // CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 10519 // CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 10520 // CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 10521 // CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 10522 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 10523 // CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 10524 // CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 10525 // CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 10526 // CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 10527 // CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 10528 // CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 10529 // CHECK26-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 10530 // CHECK26-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 10531 // CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 10532 // CHECK26-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 10533 // CHECK26-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 10534 // CHECK26-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 10535 // CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 10536 // CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 10537 // CHECK26-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 10538 // CHECK26-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 10539 // CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10540 // CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 10541 // CHECK26-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 10542 // CHECK26-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 10543 // CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10544 // CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 10545 // CHECK26-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 10546 // CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 10547 // CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 10548 // CHECK26-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 10549 // CHECK26-NEXT: ret void 10550 // 10551 // 10552 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 10553 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10554 // CHECK26-NEXT: entry: 10555 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10556 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10557 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10558 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10559 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10560 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10561 // CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 10562 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10563 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10564 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10565 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10566 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10567 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10568 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10569 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10570 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10571 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10572 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 10573 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10574 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10575 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10576 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 10577 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10578 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 10579 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 10580 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 10581 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 10582 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 10583 // CHECK26-NEXT: ret void 10584 // 10585 // 10586 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 10587 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10588 // CHECK26-NEXT: entry: 10589 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10590 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10591 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10592 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10593 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10594 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10595 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10596 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10597 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10598 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10599 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10600 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10601 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10602 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10603 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10604 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10605 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10606 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10607 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10608 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10609 // CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 10610 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10611 // CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10612 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 10613 // CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 10614 // CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 10615 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 10616 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 10617 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 10618 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10619 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10620 // CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 10621 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 10622 // CHECK26-NEXT: ret void 10623 // 10624 // 10625 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 10626 // CHECK26-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10627 // CHECK26-NEXT: entry: 10628 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10629 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10630 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10631 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10632 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10633 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10634 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10635 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10636 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10637 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10638 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10639 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10640 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10641 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10642 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10643 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10644 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10645 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10646 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 10647 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 10648 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 10649 // CHECK26-NEXT: ret void 10650 // 10651 // 10652 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 10653 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10654 // CHECK26-NEXT: entry: 10655 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10656 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10657 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10658 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10659 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10660 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10661 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10662 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10663 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10664 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10665 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10666 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10667 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10668 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10669 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10670 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10671 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10672 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10673 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10674 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10675 // CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 10676 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 10677 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 10678 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 10679 // CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 10680 // CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 10681 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 10682 // CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 10683 // CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10684 // CHECK26-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 10685 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 10686 // CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 10687 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 10688 // CHECK26-NEXT: ret void 10689 // 10690 // 10691 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 10692 // CHECK26-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10693 // CHECK26-NEXT: entry: 10694 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10695 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10696 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10697 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10698 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10699 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10700 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10701 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10702 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10703 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10704 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10705 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10706 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10707 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 10708 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10709 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10710 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10711 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 10712 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10713 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 10714 // CHECK26-NEXT: ret void 10715 // 10716 // 10717 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 10718 // CHECK26-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10719 // CHECK26-NEXT: entry: 10720 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10721 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10722 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10723 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10724 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10725 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10726 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10727 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10728 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10729 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10730 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10731 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10732 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10733 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10734 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10735 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10736 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10737 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 10738 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10739 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10740 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 10741 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10742 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10743 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 10744 // CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 10745 // CHECK26-NEXT: ret void 10746 // 10747 // 10748 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 10749 // CHECK27-SAME: () #[[ATTR0:[0-9]+]] { 10750 // CHECK27-NEXT: entry: 10751 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10752 // CHECK27-NEXT: ret void 10753 // 10754 // 10755 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. 10756 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10757 // CHECK27-NEXT: entry: 10758 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10759 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10760 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10761 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10762 // CHECK27-NEXT: ret void 10763 // 10764 // 10765 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 10766 // CHECK27-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 10767 // CHECK27-NEXT: entry: 10768 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10769 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10770 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10771 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10772 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10773 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10774 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 10775 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10776 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 10777 // CHECK27-NEXT: ret void 10778 // 10779 // 10780 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 10781 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 10782 // CHECK27-NEXT: entry: 10783 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10784 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10785 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10786 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10787 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10788 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10789 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10790 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10791 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 10792 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 10793 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 10794 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 10795 // CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10796 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10797 // CHECK27-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 10798 // CHECK27-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 10799 // CHECK27-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 10800 // CHECK27: .cancel.exit: 10801 // CHECK27-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 10802 // CHECK27-NEXT: br label [[DOTCANCEL_CONTINUE]] 10803 // CHECK27: .cancel.continue: 10804 // CHECK27-NEXT: ret void 10805 // 10806 // 10807 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 10808 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 10809 // CHECK27-NEXT: entry: 10810 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10811 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10812 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10813 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10814 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10815 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10816 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10817 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 10818 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 10819 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 10820 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 10821 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10822 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 10823 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10824 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 10825 // CHECK27-NEXT: ret void 10826 // 10827 // 10828 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 10829 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 10830 // CHECK27-NEXT: entry: 10831 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10832 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10833 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10834 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10835 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10836 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10837 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10838 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10839 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10840 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 10841 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10842 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 10843 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 10844 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 10845 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 10846 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 10847 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 10848 // CHECK27-NEXT: ret void 10849 // 10850 // 10851 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 10852 // CHECK27-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 10853 // CHECK27-NEXT: entry: 10854 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10855 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 10856 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10857 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 10858 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 10859 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10860 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10861 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 10862 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 10863 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10864 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10865 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 10866 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10867 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 10868 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 10869 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10870 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 10871 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 10872 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 10873 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 10874 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10875 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 10876 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 10877 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10878 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 10879 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 10880 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 10881 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 10882 // CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 10883 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 10884 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 10885 // CHECK27-NEXT: ret void 10886 // 10887 // 10888 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 10889 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 10890 // CHECK27-NEXT: entry: 10891 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10892 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10893 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10894 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 10895 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 10896 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 10897 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 10898 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 10899 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 10900 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 10901 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 10902 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10903 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10904 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10905 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 10906 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 10907 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 10908 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 10909 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 10910 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 10911 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 10912 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 10913 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 10914 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 10915 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 10916 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 10917 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 10918 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 10919 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 10920 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 10921 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 10922 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 10923 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 10924 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 10925 // CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 10926 // CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 10927 // CHECK27-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 10928 // CHECK27-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 10929 // CHECK27-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 10930 // CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 10931 // CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 10932 // CHECK27-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 10933 // CHECK27-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 10934 // CHECK27-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 10935 // CHECK27-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 10936 // CHECK27-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 10937 // CHECK27-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 10938 // CHECK27-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 10939 // CHECK27-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 10940 // CHECK27-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 10941 // CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 10942 // CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 10943 // CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 10944 // CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 10945 // CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 10946 // CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 10947 // CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10948 // CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 10949 // CHECK27-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 10950 // CHECK27-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 10951 // CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10952 // CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 10953 // CHECK27-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 10954 // CHECK27-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 10955 // CHECK27-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 10956 // CHECK27-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 10957 // CHECK27-NEXT: ret void 10958 // 10959 // 10960 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 10961 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10962 // CHECK27-NEXT: entry: 10963 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10964 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10965 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 10966 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10967 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10968 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10969 // CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 10970 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10971 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10972 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 10973 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10974 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10975 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 10976 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10977 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10978 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 10979 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 10980 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 10981 // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10982 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 10983 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10984 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 10985 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 10986 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 10987 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 10988 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 10989 // CHECK27-NEXT: ret void 10990 // 10991 // 10992 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 10993 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10994 // CHECK27-NEXT: entry: 10995 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10996 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10997 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10998 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10999 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11000 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11001 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11002 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11003 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11004 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11005 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11006 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11007 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11008 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11009 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11010 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11011 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11012 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11013 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11014 // CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 11015 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 11016 // CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11017 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 11018 // CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 11019 // CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 11020 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 11021 // CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 11022 // CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 11023 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11024 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11025 // CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 11026 // CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 11027 // CHECK27-NEXT: ret void 11028 // 11029 // 11030 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 11031 // CHECK27-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 11032 // CHECK27-NEXT: entry: 11033 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11034 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11035 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11036 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11037 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11038 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 11039 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11040 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11041 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11042 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11043 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11044 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11045 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11046 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11047 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11048 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11049 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 11050 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 11051 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 11052 // CHECK27-NEXT: ret void 11053 // 11054 // 11055 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 11056 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 11057 // CHECK27-NEXT: entry: 11058 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11059 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11060 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11061 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11062 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11063 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11064 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11065 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11066 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11067 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11068 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11069 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11070 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11071 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11072 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11073 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11074 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11075 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11076 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11077 // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 11078 // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 11079 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11080 // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 11081 // CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11082 // CHECK27-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 11083 // CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 11084 // CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4 11085 // CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 11086 // CHECK27-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 11087 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 11088 // CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 11089 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 11090 // CHECK27-NEXT: ret void 11091 // 11092 // 11093 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 11094 // CHECK27-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11095 // CHECK27-NEXT: entry: 11096 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11097 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11098 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11099 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11100 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11101 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11102 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11103 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11104 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11105 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11106 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11107 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11108 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11109 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11110 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11111 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 11112 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11113 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 11114 // CHECK27-NEXT: ret void 11115 // 11116 // 11117 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 11118 // CHECK27-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11119 // CHECK27-NEXT: entry: 11120 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11121 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11122 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11123 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11124 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11125 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11126 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11127 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11128 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11129 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11130 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11131 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11132 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11133 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11134 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11135 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11136 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 11137 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 11138 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 11139 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 11140 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11141 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11142 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 11143 // CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 11144 // CHECK27-NEXT: ret void 11145 // 11146 // 11147 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 11148 // CHECK28-SAME: () #[[ATTR0:[0-9]+]] { 11149 // CHECK28-NEXT: entry: 11150 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 11151 // CHECK28-NEXT: ret void 11152 // 11153 // 11154 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. 11155 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 11156 // CHECK28-NEXT: entry: 11157 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11158 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11159 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11160 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11161 // CHECK28-NEXT: ret void 11162 // 11163 // 11164 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 11165 // CHECK28-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 11166 // CHECK28-NEXT: entry: 11167 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11168 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11169 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11170 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11171 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 11172 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11173 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 11174 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11175 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 11176 // CHECK28-NEXT: ret void 11177 // 11178 // 11179 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 11180 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 11181 // CHECK28-NEXT: entry: 11182 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11183 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11184 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11185 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11186 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11187 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11188 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11189 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 11190 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 11191 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 11192 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 11193 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 11194 // CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11195 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 11196 // CHECK28-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 11197 // CHECK28-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 11198 // CHECK28-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 11199 // CHECK28: .cancel.exit: 11200 // CHECK28-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 11201 // CHECK28-NEXT: br label [[DOTCANCEL_CONTINUE]] 11202 // CHECK28: .cancel.continue: 11203 // CHECK28-NEXT: ret void 11204 // 11205 // 11206 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 11207 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 11208 // CHECK28-NEXT: entry: 11209 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11210 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11211 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11212 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11213 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11214 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11215 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11216 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11217 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 11218 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 11219 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11220 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11221 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 11222 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11223 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 11224 // CHECK28-NEXT: ret void 11225 // 11226 // 11227 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 11228 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 11229 // CHECK28-NEXT: entry: 11230 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11231 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11232 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11233 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11234 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11235 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11236 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11237 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11238 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11239 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11240 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 11241 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11242 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 11243 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 11244 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 11245 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 11246 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 11247 // CHECK28-NEXT: ret void 11248 // 11249 // 11250 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 11251 // CHECK28-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 11252 // CHECK28-NEXT: entry: 11253 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11254 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11255 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11256 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11257 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11258 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11259 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11260 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11261 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11262 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11263 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11264 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11265 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11266 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11267 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11268 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11269 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11270 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11271 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11272 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11273 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11274 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11275 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11276 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11277 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11278 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11279 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11280 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 11281 // CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 11282 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 11283 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 11284 // CHECK28-NEXT: ret void 11285 // 11286 // 11287 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 11288 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 11289 // CHECK28-NEXT: entry: 11290 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11291 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11292 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11293 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11294 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11295 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11296 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11297 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11298 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11299 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11300 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11301 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11302 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11303 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11304 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11305 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11306 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11307 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11308 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11309 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11310 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11311 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11312 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11313 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11314 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11315 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11316 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11317 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11318 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11319 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11320 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 11321 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 11322 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11323 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 11324 // CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 11325 // CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 11326 // CHECK28-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 11327 // CHECK28-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 11328 // CHECK28-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 11329 // CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 11330 // CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 11331 // CHECK28-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 11332 // CHECK28-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 11333 // CHECK28-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 11334 // CHECK28-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 11335 // CHECK28-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 11336 // CHECK28-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 11337 // CHECK28-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 11338 // CHECK28-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 11339 // CHECK28-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 11340 // CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 11341 // CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 11342 // CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 11343 // CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 11344 // CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 11345 // CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 11346 // CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 11347 // CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 11348 // CHECK28-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 11349 // CHECK28-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 11350 // CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 11351 // CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 11352 // CHECK28-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 11353 // CHECK28-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 11354 // CHECK28-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 11355 // CHECK28-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 11356 // CHECK28-NEXT: ret void 11357 // 11358 // 11359 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 11360 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11361 // CHECK28-NEXT: entry: 11362 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11363 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11364 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11365 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11366 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11367 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11368 // CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 11369 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11370 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11371 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11372 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11373 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11374 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11375 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11376 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11377 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11378 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11379 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11380 // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11381 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 11382 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11383 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 11384 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 11385 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 11386 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 11387 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 11388 // CHECK28-NEXT: ret void 11389 // 11390 // 11391 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 11392 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11393 // CHECK28-NEXT: entry: 11394 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11395 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11396 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11397 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11398 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11399 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11400 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11401 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11402 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11403 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11404 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11405 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11406 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11407 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11408 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11409 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11410 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11411 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11412 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11413 // CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 11414 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 11415 // CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11416 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 11417 // CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 11418 // CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 11419 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 11420 // CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 11421 // CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 11422 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11423 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11424 // CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 11425 // CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 11426 // CHECK28-NEXT: ret void 11427 // 11428 // 11429 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 11430 // CHECK28-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 11431 // CHECK28-NEXT: entry: 11432 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11433 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11434 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11435 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11436 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11437 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 11438 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11439 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11440 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11441 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11442 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11443 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11444 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11445 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11446 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11447 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11448 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 11449 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 11450 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 11451 // CHECK28-NEXT: ret void 11452 // 11453 // 11454 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 11455 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 11456 // CHECK28-NEXT: entry: 11457 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11458 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11459 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11460 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11461 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11462 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11463 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11464 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11465 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11466 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11467 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11468 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11469 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11470 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11471 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11472 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11473 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11474 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11475 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11476 // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 11477 // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 11478 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11479 // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 11480 // CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11481 // CHECK28-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 11482 // CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 11483 // CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4 11484 // CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 11485 // CHECK28-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 11486 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 11487 // CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 11488 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 11489 // CHECK28-NEXT: ret void 11490 // 11491 // 11492 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 11493 // CHECK28-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11494 // CHECK28-NEXT: entry: 11495 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11496 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11497 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11498 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11499 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11500 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11501 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11502 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11503 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11504 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11505 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11506 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11507 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11508 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11509 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11510 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 11511 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11512 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 11513 // CHECK28-NEXT: ret void 11514 // 11515 // 11516 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 11517 // CHECK28-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11518 // CHECK28-NEXT: entry: 11519 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11520 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11521 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11522 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11523 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11524 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11525 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11526 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11527 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11528 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11529 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11530 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11531 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11532 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11533 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11534 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11535 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 11536 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 11537 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 11538 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 11539 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11540 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11541 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 11542 // CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 11543 // CHECK28-NEXT: ret void 11544 // 11545