1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2 6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 9 10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10 22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 26 27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17 38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18 40 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19 41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20 43 44 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25 54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26 56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27 58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28 60 61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 8 target regions, but only 6 that actually will generate offloading 78 // code and have mapped arguments, and only 4 have all-constant map sizes. 79 80 81 82 // Check target registration is registered as a Ctor. 83 84 85 template<typename tx, typename ty> 86 struct TT{ 87 tx X; 88 ty Y; 89 }; 90 91 int foo(int n) { 92 int a = 0; 93 short aa = 0; 94 float b[10]; 95 float bn[n]; 96 double c[5][10]; 97 double cn[5][n]; 98 TT<long long, char> d; 99 100 #pragma omp target parallel nowait 101 { 102 } 103 104 #pragma omp target parallel if(target: 0) 105 { 106 a += 1; 107 } 108 109 110 #pragma omp target parallel if(target: 1) 111 { 112 aa += 1; 113 #pragma omp cancel parallel 114 } 115 116 117 118 119 #pragma omp target parallel if(target: n>10) 120 { 121 a += 1; 122 aa += 1; 123 } 124 125 // We capture 3 VLA sizes in this target region 126 127 128 129 130 131 // The names below are not necessarily consistent with the names used for the 132 // addresses above as some are repeated. 133 134 135 136 137 138 139 140 141 142 143 144 #pragma omp target parallel if(target: n>20) 145 { 146 a += 1; 147 b[2] += 1.0; 148 bn[3] += 1.0; 149 c[1][2] += 1.0; 150 cn[1][3] += 1.0; 151 d.X += 1; 152 d.Y += 1; 153 } 154 155 return a; 156 } 157 158 // Check that the offloading functions are emitted and that the arguments are 159 // correct and loaded correctly for the target regions in foo(). 160 161 162 163 // Create stack storage and store argument in there. 164 165 // Create stack storage and store argument in there. 166 167 // Create stack storage and store argument in there. 168 169 // Create local storage for each capture. 170 171 172 173 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 174 175 template<typename tx> 176 tx ftemplate(int n) { 177 tx a = 0; 178 short aa = 0; 179 tx b[10]; 180 181 #pragma omp target parallel if(target: n>40) 182 { 183 a += 1; 184 aa += 1; 185 b[2] += 1; 186 } 187 188 return a; 189 } 190 191 static 192 int fstatic(int n) { 193 int a = 0; 194 short aa = 0; 195 char aaa = 0; 196 int b[10]; 197 198 #pragma omp target parallel if(target: n>50) 199 { 200 a += 1; 201 aa += 1; 202 aaa += 1; 203 b[2] += 1; 204 } 205 206 return a; 207 } 208 209 struct S1 { 210 double a; 211 212 int r1(int n){ 213 int b = n+1; 214 short int c[2][n]; 215 216 #pragma omp target parallel if(target: n>60) 217 { 218 this->a = (double)b + 1.5; 219 c[1][1] = ++a; 220 } 221 222 return c[1][1] + (int)b; 223 } 224 }; 225 226 int bar(int n){ 227 int a = 0; 228 229 a += foo(n); 230 231 S1 S; 232 a += S.r1(n); 233 234 a += fstatic(n); 235 236 a += ftemplate<int>(n); 237 238 return a; 239 } 240 241 242 243 // We capture 2 VLA sizes in this target region 244 245 246 // The names below are not necessarily consistent with the names used for the 247 // addresses above as some are repeated. 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 // Check that the offloading functions are emitted and that the arguments are 268 // correct and loaded correctly for the target regions of the callees of bar(). 269 270 // Create local storage for each capture. 271 // Store captures in the context. 272 273 274 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 275 276 277 // Create local storage for each capture. 278 // Store captures in the context. 279 280 281 282 283 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 284 285 // Create local storage for each capture. 286 // Store captures in the context. 287 288 289 290 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 291 292 293 #endif 294 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 295 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 296 // CHECK1-NEXT: entry: 297 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 300 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 301 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 302 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 303 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 304 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 305 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 306 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 307 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 308 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 309 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 310 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 311 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 312 // CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 315 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 316 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 317 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 319 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 321 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 322 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 323 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 324 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 325 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 326 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 327 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 328 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 329 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 330 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 331 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 332 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 333 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 334 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 335 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 336 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 337 // CHECK1-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 338 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 339 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 340 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 341 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 342 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 343 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 344 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 345 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 346 // CHECK1-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 347 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 348 // CHECK1-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 349 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 350 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 351 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 352 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 353 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 354 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 355 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 356 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 357 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 358 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 359 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 360 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 361 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 362 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 363 // CHECK1: omp_offload.failed: 364 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 365 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 366 // CHECK1: omp_offload.cont: 367 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 368 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 369 // CHECK1-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 370 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 371 // CHECK1-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 372 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 373 // CHECK1-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 374 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 375 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 376 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 377 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 378 // CHECK1: omp_if.then: 379 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 380 // CHECK1-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 381 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 382 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 383 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 384 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 385 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 386 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 387 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 388 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* 389 // CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 390 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 391 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 392 // CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 393 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 394 // CHECK1-NEXT: store i8* null, i8** [[TMP38]], align 8 395 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 396 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 398 // CHECK1-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 399 // CHECK1-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 400 // CHECK1: omp_offload.failed10: 401 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 402 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT11]] 403 // CHECK1: omp_offload.cont11: 404 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 405 // CHECK1: omp_if.else: 406 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 407 // CHECK1-NEXT: br label [[OMP_IF_END]] 408 // CHECK1: omp_if.end: 409 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 410 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 411 // CHECK1-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 412 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 413 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 414 // CHECK1-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 415 // CHECK1-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] 416 // CHECK1: omp_if.then15: 417 // CHECK1-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 418 // CHECK1-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] 419 // CHECK1-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 420 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 421 // CHECK1-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64* 422 // CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP50]], align 8 423 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 424 // CHECK1-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* 425 // CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP52]], align 8 426 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 427 // CHECK1-NEXT: store i64 4, i64* [[TMP53]], align 8 428 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 429 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8 430 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 431 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 432 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 433 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 434 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 435 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 436 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 437 // CHECK1-NEXT: store i64 40, i64* [[TMP59]], align 8 438 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 439 // CHECK1-NEXT: store i8* null, i8** [[TMP60]], align 8 440 // CHECK1-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 441 // CHECK1-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 442 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP62]], align 8 443 // CHECK1-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 444 // CHECK1-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 445 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP64]], align 8 446 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 447 // CHECK1-NEXT: store i64 8, i64* [[TMP65]], align 8 448 // CHECK1-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 449 // CHECK1-NEXT: store i8* null, i8** [[TMP66]], align 8 450 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 451 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 452 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 453 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 454 // CHECK1-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** 455 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP70]], align 8 456 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 457 // CHECK1-NEXT: store i64 [[TMP46]], i64* [[TMP71]], align 8 458 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 459 // CHECK1-NEXT: store i8* null, i8** [[TMP72]], align 8 460 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 461 // CHECK1-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 462 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 463 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 464 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** 465 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8 466 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 467 // CHECK1-NEXT: store i64 400, i64* [[TMP77]], align 8 468 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 469 // CHECK1-NEXT: store i8* null, i8** [[TMP78]], align 8 470 // CHECK1-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 471 // CHECK1-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* 472 // CHECK1-NEXT: store i64 5, i64* [[TMP80]], align 8 473 // CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 474 // CHECK1-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 475 // CHECK1-NEXT: store i64 5, i64* [[TMP82]], align 8 476 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 477 // CHECK1-NEXT: store i64 8, i64* [[TMP83]], align 8 478 // CHECK1-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 479 // CHECK1-NEXT: store i8* null, i8** [[TMP84]], align 8 480 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 481 // CHECK1-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* 482 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP86]], align 8 483 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 484 // CHECK1-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* 485 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP88]], align 8 486 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 487 // CHECK1-NEXT: store i64 8, i64* [[TMP89]], align 8 488 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 489 // CHECK1-NEXT: store i8* null, i8** [[TMP90]], align 8 490 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 491 // CHECK1-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** 492 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP92]], align 8 493 // CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 494 // CHECK1-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** 495 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP94]], align 8 496 // CHECK1-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 497 // CHECK1-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 8 498 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 499 // CHECK1-NEXT: store i8* null, i8** [[TMP96]], align 8 500 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 501 // CHECK1-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** 502 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8 503 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 504 // CHECK1-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** 505 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8 506 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 507 // CHECK1-NEXT: store i64 16, i64* [[TMP101]], align 8 508 // CHECK1-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 509 // CHECK1-NEXT: store i8* null, i8** [[TMP102]], align 8 510 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 511 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 512 // CHECK1-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 513 // CHECK1-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 514 // CHECK1-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 515 // CHECK1-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 516 // CHECK1: omp_offload.failed19: 517 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 518 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT20]] 519 // CHECK1: omp_offload.cont20: 520 // CHECK1-NEXT: br label [[OMP_IF_END22:%.*]] 521 // CHECK1: omp_if.else21: 522 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 523 // CHECK1-NEXT: br label [[OMP_IF_END22]] 524 // CHECK1: omp_if.end22: 525 // CHECK1-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 526 // CHECK1-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 527 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) 528 // CHECK1-NEXT: ret i32 [[TMP108]] 529 // 530 // 531 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 532 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 533 // CHECK1-NEXT: entry: 534 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 535 // CHECK1-NEXT: ret void 536 // 537 // 538 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 539 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 540 // CHECK1-NEXT: entry: 541 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 542 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 543 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 544 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 545 // CHECK1-NEXT: ret void 546 // 547 // 548 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 549 // CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 550 // CHECK1-NEXT: entry: 551 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 552 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 553 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 554 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 555 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 556 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 557 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 558 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 559 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 560 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 561 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 562 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 563 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 564 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 565 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 566 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 567 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 568 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 569 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 570 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 571 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 572 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 573 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 574 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 575 // CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 576 // CHECK1-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 577 // CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 578 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 579 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 580 // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 581 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 582 // CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 583 // CHECK1: omp_offload.failed.i: 584 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 585 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 586 // CHECK1: .omp_outlined..1.exit: 587 // CHECK1-NEXT: ret i32 0 588 // 589 // 590 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 591 // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { 592 // CHECK1-NEXT: entry: 593 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 594 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 595 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 596 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 597 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 598 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 599 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 600 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 601 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 602 // CHECK1-NEXT: ret void 603 // 604 // 605 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 606 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { 607 // CHECK1-NEXT: entry: 608 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 609 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 610 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 611 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 612 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 613 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 614 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 615 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 616 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 617 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 618 // CHECK1-NEXT: ret void 619 // 620 // 621 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 622 // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { 623 // CHECK1-NEXT: entry: 624 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 625 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 626 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 627 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 628 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 629 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 630 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 631 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 632 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 633 // CHECK1-NEXT: ret void 634 // 635 // 636 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 637 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { 638 // CHECK1-NEXT: entry: 639 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 640 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 641 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 642 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 643 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 644 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 645 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 646 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 647 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 648 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 649 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 650 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 651 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 652 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 653 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 654 // CHECK1-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 655 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 656 // CHECK1: .cancel.exit: 657 // CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 658 // CHECK1-NEXT: br label [[DOTCANCEL_CONTINUE]] 659 // CHECK1: .cancel.continue: 660 // CHECK1-NEXT: ret void 661 // 662 // 663 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 664 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 665 // CHECK1-NEXT: entry: 666 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 667 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 668 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 669 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 670 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 671 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 672 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 673 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 674 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 675 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 676 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 677 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 678 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 679 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 680 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 681 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 682 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 683 // CHECK1-NEXT: ret void 684 // 685 // 686 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 687 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { 688 // CHECK1-NEXT: entry: 689 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 690 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 691 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 692 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 693 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 694 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 695 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 696 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 697 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 698 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 699 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 700 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 701 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 702 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 703 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 704 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 705 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 706 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 707 // CHECK1-NEXT: ret void 708 // 709 // 710 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 711 // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 712 // CHECK1-NEXT: entry: 713 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 714 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 715 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 716 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 717 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 718 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 719 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 720 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 721 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 722 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 723 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 724 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 725 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 726 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 727 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 728 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 729 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 730 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 731 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 732 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 733 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 734 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 735 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 736 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 737 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 738 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 739 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 740 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 741 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 742 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 743 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 744 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 745 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 746 // CHECK1-NEXT: ret void 747 // 748 // 749 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 750 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 751 // CHECK1-NEXT: entry: 752 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 753 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 754 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 755 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 756 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 757 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 758 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 759 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 760 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 761 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 762 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 763 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 764 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 765 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 766 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 767 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 768 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 769 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 770 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 771 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 772 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 773 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 774 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 775 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 776 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 777 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 778 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 779 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 780 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 781 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 782 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 783 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 784 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 785 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 786 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 787 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 788 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 789 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 790 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 791 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 792 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 793 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 794 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 795 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 796 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 797 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 798 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 799 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 800 // CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 801 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 802 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 803 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 804 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 805 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 806 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 807 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 808 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 809 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 810 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 811 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 812 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 813 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 814 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 815 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 816 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 817 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 818 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 819 // CHECK1-NEXT: ret void 820 // 821 // 822 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 823 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 824 // CHECK1-NEXT: entry: 825 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 826 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 827 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 828 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 829 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 830 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 831 // CHECK1-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 832 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 833 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 834 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 835 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 836 // CHECK1-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 837 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 838 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 839 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 840 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 841 // CHECK1-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 842 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 843 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 844 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 845 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 846 // CHECK1-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 847 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 848 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 849 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 850 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 851 // CHECK1-NEXT: ret i32 [[TMP8]] 852 // 853 // 854 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 855 // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 856 // CHECK1-NEXT: entry: 857 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 858 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 859 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 860 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 861 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 862 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 863 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 864 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 865 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 866 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 867 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 868 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 869 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 870 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 871 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 872 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 873 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 874 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 875 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 876 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 877 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 878 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 879 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 880 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 881 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 882 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 883 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 884 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 885 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 886 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 887 // CHECK1: omp_if.then: 888 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 889 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 890 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 891 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 892 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 893 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 894 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 895 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 896 // CHECK1-NEXT: store double* [[A]], double** [[TMP13]], align 8 897 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 898 // CHECK1-NEXT: store i64 8, i64* [[TMP14]], align 8 899 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 900 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 901 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 902 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 903 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 904 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 905 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 906 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 907 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 908 // CHECK1-NEXT: store i64 4, i64* [[TMP20]], align 8 909 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 910 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 911 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 912 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 913 // CHECK1-NEXT: store i64 2, i64* [[TMP23]], align 8 914 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 915 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 916 // CHECK1-NEXT: store i64 2, i64* [[TMP25]], align 8 917 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 918 // CHECK1-NEXT: store i64 8, i64* [[TMP26]], align 8 919 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 920 // CHECK1-NEXT: store i8* null, i8** [[TMP27]], align 8 921 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 922 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 923 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 924 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 925 // CHECK1-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 926 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 927 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 928 // CHECK1-NEXT: store i64 8, i64* [[TMP32]], align 8 929 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 930 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 931 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 932 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 933 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 934 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 935 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 936 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 937 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 938 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 939 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 940 // CHECK1-NEXT: store i8* null, i8** [[TMP39]], align 8 941 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 942 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 943 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 944 // CHECK1-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 945 // CHECK1-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 946 // CHECK1-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 947 // CHECK1: omp_offload.failed: 948 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 949 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 950 // CHECK1: omp_offload.cont: 951 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 952 // CHECK1: omp_if.else: 953 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 954 // CHECK1-NEXT: br label [[OMP_IF_END]] 955 // CHECK1: omp_if.end: 956 // CHECK1-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 957 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 958 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 959 // CHECK1-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 960 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 961 // CHECK1-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 962 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 963 // CHECK1-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 964 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 965 // CHECK1-NEXT: ret i32 [[ADD4]] 966 // 967 // 968 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 969 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 970 // CHECK1-NEXT: entry: 971 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 972 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 973 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 974 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 975 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 976 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 977 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 978 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 979 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 980 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 981 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 982 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 983 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 984 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 985 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 986 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 987 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 988 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 989 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 990 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 991 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 992 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 993 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 994 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 995 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 996 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 997 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 998 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 999 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1000 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1001 // CHECK1: omp_if.then: 1002 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1003 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1004 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1005 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1006 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1007 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1008 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1009 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1010 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1011 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1012 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1013 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1014 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1015 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1016 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1017 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1018 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1019 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1020 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1021 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1022 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1023 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1024 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1025 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1026 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1027 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1028 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1029 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1030 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1031 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1032 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1033 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1034 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1035 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1036 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1037 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1038 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1039 // CHECK1: omp_offload.failed: 1040 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1041 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1042 // CHECK1: omp_offload.cont: 1043 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1044 // CHECK1: omp_if.else: 1045 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1046 // CHECK1-NEXT: br label [[OMP_IF_END]] 1047 // CHECK1: omp_if.end: 1048 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1049 // CHECK1-NEXT: ret i32 [[TMP31]] 1050 // 1051 // 1052 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1053 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 1054 // CHECK1-NEXT: entry: 1055 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1056 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1057 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1058 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1059 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1060 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1061 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1062 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1063 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1064 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1065 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1066 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1067 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1068 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1069 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1070 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1071 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1072 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1073 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1074 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1075 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1076 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1077 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1078 // CHECK1: omp_if.then: 1079 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1080 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1081 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1082 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1083 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1084 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1085 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1086 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1087 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1088 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1089 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1090 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1091 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1092 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1093 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1094 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1095 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1096 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1097 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1098 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1099 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1100 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1101 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1102 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1103 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1104 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1105 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1106 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1107 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1108 // CHECK1: omp_offload.failed: 1109 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1110 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1111 // CHECK1: omp_offload.cont: 1112 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1113 // CHECK1: omp_if.else: 1114 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1115 // CHECK1-NEXT: br label [[OMP_IF_END]] 1116 // CHECK1: omp_if.end: 1117 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1118 // CHECK1-NEXT: ret i32 [[TMP24]] 1119 // 1120 // 1121 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 1122 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1123 // CHECK1-NEXT: entry: 1124 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1125 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1126 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1127 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1128 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1129 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1130 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1131 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1132 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1133 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1134 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1135 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1136 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1137 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1138 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1139 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1140 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1141 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1142 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1143 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1144 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1145 // CHECK1-NEXT: ret void 1146 // 1147 // 1148 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9 1149 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1150 // CHECK1-NEXT: entry: 1151 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1152 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1153 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1154 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1155 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1156 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1157 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1158 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1159 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1160 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1161 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1162 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1163 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1164 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1165 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1166 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1167 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1168 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1169 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1170 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1171 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 1172 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 1173 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1174 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1175 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1176 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 1177 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 1178 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 1179 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1180 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 1181 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 1182 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1183 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 1184 // CHECK1-NEXT: ret void 1185 // 1186 // 1187 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 1188 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1189 // CHECK1-NEXT: entry: 1190 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1191 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1192 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1193 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1194 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1195 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1196 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1197 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1198 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1199 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1200 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1201 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1202 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1203 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1204 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1205 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1206 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1207 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1208 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1209 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1210 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1211 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1212 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1213 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1214 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1215 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1216 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1217 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1218 // CHECK1-NEXT: ret void 1219 // 1220 // 1221 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11 1222 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1223 // CHECK1-NEXT: entry: 1224 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1225 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1226 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1227 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1228 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1229 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1230 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1231 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1232 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1233 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1234 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1235 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1236 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1237 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1238 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1239 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1240 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1241 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1242 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1243 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1244 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 1245 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1246 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1247 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 1248 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 1249 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 1250 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 1251 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 1252 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 1253 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1254 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1255 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 1256 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 1257 // CHECK1-NEXT: ret void 1258 // 1259 // 1260 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 1261 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1262 // CHECK1-NEXT: entry: 1263 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1264 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1265 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1266 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1267 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1268 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1269 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1270 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1271 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1272 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1273 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1274 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1275 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1276 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1277 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1278 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1279 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1280 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1281 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1282 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1283 // CHECK1-NEXT: ret void 1284 // 1285 // 1286 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14 1287 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1288 // CHECK1-NEXT: entry: 1289 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1290 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1291 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1292 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1293 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1294 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1295 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1296 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1297 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1298 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1299 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1300 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1301 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1302 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1303 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1304 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1305 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1306 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1307 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1308 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1309 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1310 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1311 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1312 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 1313 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 1314 // CHECK1-NEXT: ret void 1315 // 1316 // 1317 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1318 // CHECK1-SAME: () #[[ATTR7:[0-9]+]] { 1319 // CHECK1-NEXT: entry: 1320 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1321 // CHECK1-NEXT: ret void 1322 // 1323 // 1324 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi 1325 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1326 // CHECK2-NEXT: entry: 1327 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1328 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 1329 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 1330 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1331 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1332 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1333 // CHECK2-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1334 // CHECK2-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 1335 // CHECK2-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 1336 // CHECK2-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 1337 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1338 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1339 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 1340 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 1341 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 1342 // CHECK2-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 1343 // CHECK2-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 1344 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 1345 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 1346 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 1347 // CHECK2-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 1348 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 1349 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 1350 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 1351 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 1352 // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1353 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1354 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1355 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 1356 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1357 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1358 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1359 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1360 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 1361 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1362 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1363 // CHECK2-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 1364 // CHECK2-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 1365 // CHECK2-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 1366 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 1367 // CHECK2-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 1368 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 1369 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 1370 // CHECK2-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 1371 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 1372 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1373 // CHECK2-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 1374 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 1375 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 1376 // CHECK2-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 1377 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1378 // CHECK2-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 1379 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1380 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1381 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 1382 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 1383 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1384 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1385 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 1386 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1387 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 1388 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1389 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1390 // CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1391 // CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1392 // CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1393 // CHECK2: omp_offload.failed: 1394 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 1395 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1396 // CHECK2: omp_offload.cont: 1397 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1398 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 1399 // CHECK2-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 1400 // CHECK2-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 1401 // CHECK2-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 1402 // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 1403 // CHECK2-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 1404 // CHECK2-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 1405 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 1406 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 1407 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1408 // CHECK2: omp_if.then: 1409 // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 1410 // CHECK2-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 1411 // CHECK2-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 1412 // CHECK2-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 1413 // CHECK2-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 1414 // CHECK2-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 1415 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 1416 // CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8 1417 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 1418 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* 1419 // CHECK2-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 1420 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 1421 // CHECK2-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 1422 // CHECK2-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 1423 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 1424 // CHECK2-NEXT: store i8* null, i8** [[TMP38]], align 8 1425 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 1426 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 1427 // CHECK2-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1428 // CHECK2-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 1429 // CHECK2-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 1430 // CHECK2: omp_offload.failed10: 1431 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 1432 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT11]] 1433 // CHECK2: omp_offload.cont11: 1434 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 1435 // CHECK2: omp_if.else: 1436 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 1437 // CHECK2-NEXT: br label [[OMP_IF_END]] 1438 // CHECK2: omp_if.end: 1439 // CHECK2-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 1440 // CHECK2-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 1441 // CHECK2-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 1442 // CHECK2-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 1443 // CHECK2-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 1444 // CHECK2-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 1445 // CHECK2-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] 1446 // CHECK2: omp_if.then15: 1447 // CHECK2-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 1448 // CHECK2-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] 1449 // CHECK2-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 1450 // CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 1451 // CHECK2-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64* 1452 // CHECK2-NEXT: store i64 [[TMP44]], i64* [[TMP50]], align 8 1453 // CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 1454 // CHECK2-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* 1455 // CHECK2-NEXT: store i64 [[TMP44]], i64* [[TMP52]], align 8 1456 // CHECK2-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1457 // CHECK2-NEXT: store i64 4, i64* [[TMP53]], align 8 1458 // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 1459 // CHECK2-NEXT: store i8* null, i8** [[TMP54]], align 8 1460 // CHECK2-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 1461 // CHECK2-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 1462 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 1463 // CHECK2-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 1464 // CHECK2-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 1465 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 1466 // CHECK2-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 1467 // CHECK2-NEXT: store i64 40, i64* [[TMP59]], align 8 1468 // CHECK2-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 1469 // CHECK2-NEXT: store i8* null, i8** [[TMP60]], align 8 1470 // CHECK2-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 1471 // CHECK2-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 1472 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP62]], align 8 1473 // CHECK2-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 1474 // CHECK2-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 1475 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP64]], align 8 1476 // CHECK2-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 1477 // CHECK2-NEXT: store i64 8, i64* [[TMP65]], align 8 1478 // CHECK2-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 1479 // CHECK2-NEXT: store i8* null, i8** [[TMP66]], align 8 1480 // CHECK2-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 1481 // CHECK2-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 1482 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 1483 // CHECK2-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 1484 // CHECK2-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** 1485 // CHECK2-NEXT: store float* [[VLA]], float** [[TMP70]], align 8 1486 // CHECK2-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1487 // CHECK2-NEXT: store i64 [[TMP46]], i64* [[TMP71]], align 8 1488 // CHECK2-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 1489 // CHECK2-NEXT: store i8* null, i8** [[TMP72]], align 8 1490 // CHECK2-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 1491 // CHECK2-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 1492 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 1493 // CHECK2-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 1494 // CHECK2-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** 1495 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8 1496 // CHECK2-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1497 // CHECK2-NEXT: store i64 400, i64* [[TMP77]], align 8 1498 // CHECK2-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 1499 // CHECK2-NEXT: store i8* null, i8** [[TMP78]], align 8 1500 // CHECK2-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 1501 // CHECK2-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* 1502 // CHECK2-NEXT: store i64 5, i64* [[TMP80]], align 8 1503 // CHECK2-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 1504 // CHECK2-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 1505 // CHECK2-NEXT: store i64 5, i64* [[TMP82]], align 8 1506 // CHECK2-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 1507 // CHECK2-NEXT: store i64 8, i64* [[TMP83]], align 8 1508 // CHECK2-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 1509 // CHECK2-NEXT: store i8* null, i8** [[TMP84]], align 8 1510 // CHECK2-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 1511 // CHECK2-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* 1512 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP86]], align 8 1513 // CHECK2-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 1514 // CHECK2-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* 1515 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP88]], align 8 1516 // CHECK2-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 1517 // CHECK2-NEXT: store i64 8, i64* [[TMP89]], align 8 1518 // CHECK2-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 1519 // CHECK2-NEXT: store i8* null, i8** [[TMP90]], align 8 1520 // CHECK2-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 1521 // CHECK2-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** 1522 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP92]], align 8 1523 // CHECK2-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 1524 // CHECK2-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** 1525 // CHECK2-NEXT: store double* [[VLA1]], double** [[TMP94]], align 8 1526 // CHECK2-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 1527 // CHECK2-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 8 1528 // CHECK2-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 1529 // CHECK2-NEXT: store i8* null, i8** [[TMP96]], align 8 1530 // CHECK2-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 1531 // CHECK2-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** 1532 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8 1533 // CHECK2-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 1534 // CHECK2-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** 1535 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8 1536 // CHECK2-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 1537 // CHECK2-NEXT: store i64 16, i64* [[TMP101]], align 8 1538 // CHECK2-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 1539 // CHECK2-NEXT: store i8* null, i8** [[TMP102]], align 8 1540 // CHECK2-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 1541 // CHECK2-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 1542 // CHECK2-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1543 // CHECK2-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1544 // CHECK2-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 1545 // CHECK2-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 1546 // CHECK2: omp_offload.failed19: 1547 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 1548 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT20]] 1549 // CHECK2: omp_offload.cont20: 1550 // CHECK2-NEXT: br label [[OMP_IF_END22:%.*]] 1551 // CHECK2: omp_if.else21: 1552 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 1553 // CHECK2-NEXT: br label [[OMP_IF_END22]] 1554 // CHECK2: omp_if.end22: 1555 // CHECK2-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 1556 // CHECK2-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1557 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) 1558 // CHECK2-NEXT: ret i32 [[TMP108]] 1559 // 1560 // 1561 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 1562 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] { 1563 // CHECK2-NEXT: entry: 1564 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1565 // CHECK2-NEXT: ret void 1566 // 1567 // 1568 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1569 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 1570 // CHECK2-NEXT: entry: 1571 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1572 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1573 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1574 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1575 // CHECK2-NEXT: ret void 1576 // 1577 // 1578 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry. 1579 // CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 1580 // CHECK2-NEXT: entry: 1581 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 1582 // CHECK2-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 1583 // CHECK2-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 1584 // CHECK2-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 1585 // CHECK2-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 1586 // CHECK2-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 1587 // CHECK2-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 1588 // CHECK2-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 1589 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 1590 // CHECK2-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1591 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 1592 // CHECK2-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 1593 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 1594 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 1595 // CHECK2-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 1596 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 1597 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 1598 // CHECK2-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 1599 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 1600 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 1601 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 1602 // CHECK2-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 1603 // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 1604 // CHECK2-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 1605 // CHECK2-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 1606 // CHECK2-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 1607 // CHECK2-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 1608 // CHECK2-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 1609 // CHECK2-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 1610 // CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 1611 // CHECK2-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1612 // CHECK2-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 1613 // CHECK2: omp_offload.failed.i: 1614 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 1615 // CHECK2-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 1616 // CHECK2: .omp_outlined..1.exit: 1617 // CHECK2-NEXT: ret i32 0 1618 // 1619 // 1620 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 1621 // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { 1622 // CHECK2-NEXT: entry: 1623 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1624 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1625 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1626 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1627 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1628 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1629 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 1630 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1631 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1632 // CHECK2-NEXT: ret void 1633 // 1634 // 1635 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 1636 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { 1637 // CHECK2-NEXT: entry: 1638 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1639 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1640 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1641 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1642 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1643 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1644 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1645 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1646 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1647 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1648 // CHECK2-NEXT: ret void 1649 // 1650 // 1651 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 1652 // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { 1653 // CHECK2-NEXT: entry: 1654 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1655 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1656 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1657 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1658 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 1659 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1660 // CHECK2-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 1661 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1662 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 1663 // CHECK2-NEXT: ret void 1664 // 1665 // 1666 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1667 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { 1668 // CHECK2-NEXT: entry: 1669 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1670 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1671 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1672 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1673 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1674 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1675 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1676 // CHECK2-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 1677 // CHECK2-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 1678 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 1679 // CHECK2-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 1680 // CHECK2-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 1681 // CHECK2-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1682 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1683 // CHECK2-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 1684 // CHECK2-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 1685 // CHECK2-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 1686 // CHECK2: .cancel.exit: 1687 // CHECK2-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 1688 // CHECK2-NEXT: br label [[DOTCANCEL_CONTINUE]] 1689 // CHECK2: .cancel.continue: 1690 // CHECK2-NEXT: ret void 1691 // 1692 // 1693 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 1694 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 1695 // CHECK2-NEXT: entry: 1696 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1697 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1698 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1699 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1700 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1701 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1702 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1703 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1704 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1705 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1706 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 1707 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1708 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1709 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1710 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 1711 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1712 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 1713 // CHECK2-NEXT: ret void 1714 // 1715 // 1716 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1717 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { 1718 // CHECK2-NEXT: entry: 1719 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1720 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1721 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1722 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1723 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1724 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1725 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1726 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1727 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1728 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1729 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 1730 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1731 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1732 // CHECK2-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 1733 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 1734 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1735 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1736 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1737 // CHECK2-NEXT: ret void 1738 // 1739 // 1740 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 1741 // CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 1742 // CHECK2-NEXT: entry: 1743 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1744 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1745 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1746 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1747 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1748 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1749 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1750 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1751 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1752 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1753 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1754 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1755 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1756 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1757 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1758 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1759 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1760 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1761 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1762 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1763 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1764 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1765 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1766 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1767 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1768 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1769 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1770 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1771 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1772 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1773 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 1774 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 1775 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 1776 // CHECK2-NEXT: ret void 1777 // 1778 // 1779 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 1780 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 1781 // CHECK2-NEXT: entry: 1782 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1783 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1784 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1785 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 1786 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1787 // CHECK2-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 1788 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 1789 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1790 // CHECK2-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 1791 // CHECK2-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 1792 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 1793 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1794 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1795 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1796 // CHECK2-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 1797 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1798 // CHECK2-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 1799 // CHECK2-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 1800 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1801 // CHECK2-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 1802 // CHECK2-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 1803 // CHECK2-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 1804 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1805 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 1806 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1807 // CHECK2-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 1808 // CHECK2-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 1809 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1810 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 1811 // CHECK2-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 1812 // CHECK2-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 1813 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 1814 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 1815 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1816 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 1817 // CHECK2-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 1818 // CHECK2-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 1819 // CHECK2-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 1820 // CHECK2-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 1821 // CHECK2-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 1822 // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 1823 // CHECK2-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 1824 // CHECK2-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 1825 // CHECK2-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 1826 // CHECK2-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 1827 // CHECK2-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 1828 // CHECK2-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 1829 // CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 1830 // CHECK2-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 1831 // CHECK2-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 1832 // CHECK2-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 1833 // CHECK2-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 1834 // CHECK2-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 1835 // CHECK2-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 1836 // CHECK2-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 1837 // CHECK2-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 1838 // CHECK2-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 1839 // CHECK2-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1840 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 1841 // CHECK2-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 1842 // CHECK2-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 1843 // CHECK2-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1844 // CHECK2-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 1845 // CHECK2-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 1846 // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 1847 // CHECK2-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 1848 // CHECK2-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 1849 // CHECK2-NEXT: ret void 1850 // 1851 // 1852 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari 1853 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 1854 // CHECK2-NEXT: entry: 1855 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1856 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 1857 // CHECK2-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 1858 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1859 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 1860 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1861 // CHECK2-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 1862 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1863 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1864 // CHECK2-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1865 // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1866 // CHECK2-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 1867 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1868 // CHECK2-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1869 // CHECK2-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1870 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1871 // CHECK2-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 1872 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1873 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1874 // CHECK2-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1875 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1876 // CHECK2-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 1877 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1878 // CHECK2-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1879 // CHECK2-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1880 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1881 // CHECK2-NEXT: ret i32 [[TMP8]] 1882 // 1883 // 1884 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1885 // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1886 // CHECK2-NEXT: entry: 1887 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1888 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1889 // CHECK2-NEXT: [[B:%.*]] = alloca i32, align 4 1890 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1891 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1892 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1893 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 1894 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 1895 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 1896 // CHECK2-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 1897 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1898 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1899 // CHECK2-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1900 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1901 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1902 // CHECK2-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1903 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1904 // CHECK2-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 1905 // CHECK2-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 1906 // CHECK2-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 1907 // CHECK2-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 1908 // CHECK2-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 1909 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 1910 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 1911 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1912 // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 1913 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 1914 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 1915 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 1916 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1917 // CHECK2: omp_if.then: 1918 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1919 // CHECK2-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 1920 // CHECK2-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 1921 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1922 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 1923 // CHECK2-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 1924 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1925 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 1926 // CHECK2-NEXT: store double* [[A]], double** [[TMP13]], align 8 1927 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1928 // CHECK2-NEXT: store i64 8, i64* [[TMP14]], align 8 1929 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1930 // CHECK2-NEXT: store i8* null, i8** [[TMP15]], align 8 1931 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1932 // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 1933 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 1934 // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1935 // CHECK2-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 1936 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 1937 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 1938 // CHECK2-NEXT: store i64 4, i64* [[TMP20]], align 8 1939 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1940 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 1941 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1942 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 1943 // CHECK2-NEXT: store i64 2, i64* [[TMP23]], align 8 1944 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1945 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 1946 // CHECK2-NEXT: store i64 2, i64* [[TMP25]], align 8 1947 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 1948 // CHECK2-NEXT: store i64 8, i64* [[TMP26]], align 8 1949 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1950 // CHECK2-NEXT: store i8* null, i8** [[TMP27]], align 8 1951 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1952 // CHECK2-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 1953 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 1954 // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1955 // CHECK2-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 1956 // CHECK2-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 1957 // CHECK2-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1958 // CHECK2-NEXT: store i64 8, i64* [[TMP32]], align 8 1959 // CHECK2-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1960 // CHECK2-NEXT: store i8* null, i8** [[TMP33]], align 8 1961 // CHECK2-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1962 // CHECK2-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 1963 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 1964 // CHECK2-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1965 // CHECK2-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 1966 // CHECK2-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 1967 // CHECK2-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1968 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 1969 // CHECK2-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 1970 // CHECK2-NEXT: store i8* null, i8** [[TMP39]], align 8 1971 // CHECK2-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1972 // CHECK2-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1973 // CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1974 // CHECK2-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1975 // CHECK2-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 1976 // CHECK2-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1977 // CHECK2: omp_offload.failed: 1978 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1979 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 1980 // CHECK2: omp_offload.cont: 1981 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 1982 // CHECK2: omp_if.else: 1983 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1984 // CHECK2-NEXT: br label [[OMP_IF_END]] 1985 // CHECK2: omp_if.end: 1986 // CHECK2-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 1987 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 1988 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1989 // CHECK2-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1990 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 1991 // CHECK2-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 1992 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 1993 // CHECK2-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1994 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 1995 // CHECK2-NEXT: ret i32 [[ADD4]] 1996 // 1997 // 1998 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici 1999 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 2000 // CHECK2-NEXT: entry: 2001 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2002 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2003 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 2004 // CHECK2-NEXT: [[AAA:%.*]] = alloca i8, align 1 2005 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2006 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2007 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2008 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2009 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 2010 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 2011 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 2012 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2013 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2014 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 2015 // CHECK2-NEXT: store i8 0, i8* [[AAA]], align 1 2016 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2017 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2018 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 2019 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2020 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2021 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2022 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2023 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2024 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 2025 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 2026 // CHECK2-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 2027 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 2028 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2029 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 2030 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2031 // CHECK2: omp_if.then: 2032 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2033 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 2034 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 2035 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2036 // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 2037 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 2038 // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2039 // CHECK2-NEXT: store i8* null, i8** [[TMP11]], align 8 2040 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2041 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2042 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 2043 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2044 // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 2045 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 2046 // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2047 // CHECK2-NEXT: store i8* null, i8** [[TMP16]], align 8 2048 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2049 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 2050 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 2051 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2052 // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 2053 // CHECK2-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 2054 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2055 // CHECK2-NEXT: store i8* null, i8** [[TMP21]], align 8 2056 // CHECK2-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2057 // CHECK2-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 2058 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 2059 // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2060 // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 2061 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 2062 // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 2063 // CHECK2-NEXT: store i8* null, i8** [[TMP26]], align 8 2064 // CHECK2-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2065 // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2066 // CHECK2-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2067 // CHECK2-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2068 // CHECK2-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2069 // CHECK2: omp_offload.failed: 2070 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 2071 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2072 // CHECK2: omp_offload.cont: 2073 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2074 // CHECK2: omp_if.else: 2075 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 2076 // CHECK2-NEXT: br label [[OMP_IF_END]] 2077 // CHECK2: omp_if.end: 2078 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 2079 // CHECK2-NEXT: ret i32 [[TMP31]] 2080 // 2081 // 2082 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2083 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 2084 // CHECK2-NEXT: entry: 2085 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2086 // CHECK2-NEXT: [[A:%.*]] = alloca i32, align 4 2087 // CHECK2-NEXT: [[AA:%.*]] = alloca i16, align 2 2088 // CHECK2-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2089 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2090 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2091 // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 2092 // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 2093 // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 2094 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2095 // CHECK2-NEXT: store i32 0, i32* [[A]], align 4 2096 // CHECK2-NEXT: store i16 0, i16* [[AA]], align 2 2097 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2098 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2099 // CHECK2-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 2100 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2101 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2102 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2103 // CHECK2-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2104 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2105 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2106 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 2107 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2108 // CHECK2: omp_if.then: 2109 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2110 // CHECK2-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 2111 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 2112 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2113 // CHECK2-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 2114 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 2115 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 2116 // CHECK2-NEXT: store i8* null, i8** [[TMP9]], align 8 2117 // CHECK2-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2118 // CHECK2-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 2119 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 2120 // CHECK2-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2121 // CHECK2-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 2122 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 2123 // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 2124 // CHECK2-NEXT: store i8* null, i8** [[TMP14]], align 8 2125 // CHECK2-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2126 // CHECK2-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 2127 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 2128 // CHECK2-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2129 // CHECK2-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 2130 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 2131 // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 2132 // CHECK2-NEXT: store i8* null, i8** [[TMP19]], align 8 2133 // CHECK2-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2134 // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2135 // CHECK2-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2136 // CHECK2-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2137 // CHECK2-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2138 // CHECK2: omp_offload.failed: 2139 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 2140 // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] 2141 // CHECK2: omp_offload.cont: 2142 // CHECK2-NEXT: br label [[OMP_IF_END:%.*]] 2143 // CHECK2: omp_if.else: 2144 // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 2145 // CHECK2-NEXT: br label [[OMP_IF_END]] 2146 // CHECK2: omp_if.end: 2147 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 2148 // CHECK2-NEXT: ret i32 [[TMP24]] 2149 // 2150 // 2151 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 2152 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2153 // CHECK2-NEXT: entry: 2154 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2155 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2156 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2157 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2158 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2159 // CHECK2-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2160 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2161 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2162 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2163 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2164 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2165 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2166 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2167 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2168 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2169 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2170 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2171 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2172 // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 2173 // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 2174 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 2175 // CHECK2-NEXT: ret void 2176 // 2177 // 2178 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9 2179 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 2180 // CHECK2-NEXT: entry: 2181 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2182 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2183 // CHECK2-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2184 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2185 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2186 // CHECK2-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2187 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2188 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2189 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2190 // CHECK2-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2191 // CHECK2-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2192 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2193 // CHECK2-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2194 // CHECK2-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2195 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2196 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2197 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2198 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2199 // CHECK2-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2200 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2201 // CHECK2-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 2202 // CHECK2-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 2203 // CHECK2-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2204 // CHECK2-NEXT: store double [[ADD]], double* [[A]], align 8 2205 // CHECK2-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2206 // CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 2207 // CHECK2-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 2208 // CHECK2-NEXT: store double [[INC]], double* [[A4]], align 8 2209 // CHECK2-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 2210 // CHECK2-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 2211 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 2212 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 2213 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 2214 // CHECK2-NEXT: ret void 2215 // 2216 // 2217 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 2218 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2219 // CHECK2-NEXT: entry: 2220 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2221 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2222 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2223 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2224 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2225 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2226 // CHECK2-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2227 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2228 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2229 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2230 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2231 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2232 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2233 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2234 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2235 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2236 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2237 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 2238 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2239 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2240 // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2241 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 2242 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2243 // CHECK2-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 2244 // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 2245 // CHECK2-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 2246 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 2247 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 2248 // CHECK2-NEXT: ret void 2249 // 2250 // 2251 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11 2252 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 2253 // CHECK2-NEXT: entry: 2254 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2255 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2256 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2257 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2258 // CHECK2-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2259 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2260 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2261 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2262 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2263 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2264 // CHECK2-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2265 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2266 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2267 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2268 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2269 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2270 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2271 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2272 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2273 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2274 // CHECK2-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 2275 // CHECK2-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2276 // CHECK2-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2277 // CHECK2-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 2278 // CHECK2-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 2279 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 2280 // CHECK2-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 2281 // CHECK2-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 2282 // CHECK2-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 2283 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 2284 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2285 // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 2286 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 2287 // CHECK2-NEXT: ret void 2288 // 2289 // 2290 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 2291 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2292 // CHECK2-NEXT: entry: 2293 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2294 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2295 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2296 // CHECK2-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2297 // CHECK2-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2298 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2299 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2300 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2301 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2302 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2303 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2304 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2305 // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2306 // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 2307 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2308 // CHECK2-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2309 // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2310 // CHECK2-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 2311 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2312 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 2313 // CHECK2-NEXT: ret void 2314 // 2315 // 2316 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14 2317 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 2318 // CHECK2-NEXT: entry: 2319 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2320 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2321 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2322 // CHECK2-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2323 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2324 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2325 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2326 // CHECK2-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2327 // CHECK2-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2328 // CHECK2-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2329 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2330 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2331 // CHECK2-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2332 // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2333 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2334 // CHECK2-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2335 // CHECK2-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2336 // CHECK2-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 2337 // CHECK2-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2338 // CHECK2-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2339 // CHECK2-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 2340 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 2341 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2342 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 2343 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 2344 // CHECK2-NEXT: ret void 2345 // 2346 // 2347 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2348 // CHECK2-SAME: () #[[ATTR7:[0-9]+]] { 2349 // CHECK2-NEXT: entry: 2350 // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) 2351 // CHECK2-NEXT: ret void 2352 // 2353 // 2354 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 2355 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 2356 // CHECK3-NEXT: entry: 2357 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2358 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2359 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2360 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 2361 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2362 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2363 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 2364 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 2365 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 2366 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 2367 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2368 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2369 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 2370 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 2371 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 2372 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 2373 // CHECK3-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 2374 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 2375 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 2376 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 2377 // CHECK3-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 2378 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 2379 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 2380 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 2381 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 2382 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 2383 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2384 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2385 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2386 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2387 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2388 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2389 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 2390 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2391 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2392 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 2393 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 2394 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 2395 // CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 2396 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 2397 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 2398 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 2399 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 2400 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 2401 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 2402 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 2403 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 2404 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2405 // CHECK3-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 2406 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2407 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2408 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 2409 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 2410 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2411 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 2412 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 2413 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2414 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 2415 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2416 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2417 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2418 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 2419 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2420 // CHECK3: omp_offload.failed: 2421 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 2422 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2423 // CHECK3: omp_offload.cont: 2424 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 2425 // CHECK3-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 2426 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 2427 // CHECK3-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 2428 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 2429 // CHECK3-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 2430 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 2431 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 2432 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 2433 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2434 // CHECK3: omp_if.then: 2435 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2436 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 2437 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 2438 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2439 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 2440 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 2441 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 2442 // CHECK3-NEXT: store i8* null, i8** [[TMP31]], align 4 2443 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 2444 // CHECK3-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* 2445 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 2446 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 2447 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 2448 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 2449 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 2450 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 2451 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 2452 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 2453 // CHECK3-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2454 // CHECK3-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 2455 // CHECK3-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 2456 // CHECK3: omp_offload.failed8: 2457 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 2458 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT9]] 2459 // CHECK3: omp_offload.cont9: 2460 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2461 // CHECK3: omp_if.else: 2462 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 2463 // CHECK3-NEXT: br label [[OMP_IF_END]] 2464 // CHECK3: omp_if.end: 2465 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 2466 // CHECK3-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 2467 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 2468 // CHECK3-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 2469 // CHECK3-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 2470 // CHECK3-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] 2471 // CHECK3: omp_if.then12: 2472 // CHECK3-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 2473 // CHECK3-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 2474 // CHECK3-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] 2475 // CHECK3-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 2476 // CHECK3-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 2477 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 2478 // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* 2479 // CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP50]], align 4 2480 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 2481 // CHECK3-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* 2482 // CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP52]], align 4 2483 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2484 // CHECK3-NEXT: store i64 4, i64* [[TMP53]], align 4 2485 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 2486 // CHECK3-NEXT: store i8* null, i8** [[TMP54]], align 4 2487 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 2488 // CHECK3-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 2489 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 2490 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 2491 // CHECK3-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 2492 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 2493 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 2494 // CHECK3-NEXT: store i64 40, i64* [[TMP59]], align 4 2495 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 2496 // CHECK3-NEXT: store i8* null, i8** [[TMP60]], align 4 2497 // CHECK3-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 2498 // CHECK3-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 2499 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP62]], align 4 2500 // CHECK3-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 2501 // CHECK3-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* 2502 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP64]], align 4 2503 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 2504 // CHECK3-NEXT: store i64 4, i64* [[TMP65]], align 4 2505 // CHECK3-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 2506 // CHECK3-NEXT: store i8* null, i8** [[TMP66]], align 4 2507 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 2508 // CHECK3-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 2509 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 2510 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 2511 // CHECK3-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** 2512 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP70]], align 4 2513 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2514 // CHECK3-NEXT: store i64 [[TMP45]], i64* [[TMP71]], align 4 2515 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 2516 // CHECK3-NEXT: store i8* null, i8** [[TMP72]], align 4 2517 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 2518 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 2519 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 2520 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 2521 // CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** 2522 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4 2523 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2524 // CHECK3-NEXT: store i64 400, i64* [[TMP77]], align 4 2525 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 2526 // CHECK3-NEXT: store i8* null, i8** [[TMP78]], align 4 2527 // CHECK3-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 2528 // CHECK3-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* 2529 // CHECK3-NEXT: store i32 5, i32* [[TMP80]], align 4 2530 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 2531 // CHECK3-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* 2532 // CHECK3-NEXT: store i32 5, i32* [[TMP82]], align 4 2533 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 2534 // CHECK3-NEXT: store i64 4, i64* [[TMP83]], align 4 2535 // CHECK3-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 2536 // CHECK3-NEXT: store i8* null, i8** [[TMP84]], align 4 2537 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 2538 // CHECK3-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* 2539 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP86]], align 4 2540 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 2541 // CHECK3-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 2542 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP88]], align 4 2543 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 2544 // CHECK3-NEXT: store i64 4, i64* [[TMP89]], align 4 2545 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 2546 // CHECK3-NEXT: store i8* null, i8** [[TMP90]], align 4 2547 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 2548 // CHECK3-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** 2549 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP92]], align 4 2550 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 2551 // CHECK3-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** 2552 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP94]], align 4 2553 // CHECK3-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 2554 // CHECK3-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 4 2555 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 2556 // CHECK3-NEXT: store i8* null, i8** [[TMP96]], align 4 2557 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 2558 // CHECK3-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** 2559 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4 2560 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 2561 // CHECK3-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** 2562 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4 2563 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 2564 // CHECK3-NEXT: store i64 12, i64* [[TMP101]], align 4 2565 // CHECK3-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 2566 // CHECK3-NEXT: store i8* null, i8** [[TMP102]], align 4 2567 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 2568 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 2569 // CHECK3-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2570 // CHECK3-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2571 // CHECK3-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 2572 // CHECK3-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 2573 // CHECK3: omp_offload.failed16: 2574 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 2575 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] 2576 // CHECK3: omp_offload.cont17: 2577 // CHECK3-NEXT: br label [[OMP_IF_END19:%.*]] 2578 // CHECK3: omp_if.else18: 2579 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 2580 // CHECK3-NEXT: br label [[OMP_IF_END19]] 2581 // CHECK3: omp_if.end19: 2582 // CHECK3-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 2583 // CHECK3-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2584 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) 2585 // CHECK3-NEXT: ret i32 [[TMP108]] 2586 // 2587 // 2588 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 2589 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 2590 // CHECK3-NEXT: entry: 2591 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2592 // CHECK3-NEXT: ret void 2593 // 2594 // 2595 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2596 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 2597 // CHECK3-NEXT: entry: 2598 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2599 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2600 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2601 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2602 // CHECK3-NEXT: ret void 2603 // 2604 // 2605 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 2606 // CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 2607 // CHECK3-NEXT: entry: 2608 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 2609 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 2610 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 2611 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 2612 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 2613 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 2614 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 2615 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 2616 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 2617 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2618 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 2619 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 2620 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 2621 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 2622 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 2623 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 2624 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 2625 // CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 2626 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 2627 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 2628 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 2629 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 2630 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 2631 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 2632 // CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 2633 // CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 2634 // CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 2635 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 2636 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 2637 // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 2638 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 2639 // CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 2640 // CHECK3: omp_offload.failed.i: 2641 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 2642 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 2643 // CHECK3: .omp_outlined..1.exit: 2644 // CHECK3-NEXT: ret i32 0 2645 // 2646 // 2647 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 2648 // CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { 2649 // CHECK3-NEXT: entry: 2650 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2651 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2652 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2653 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2654 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2655 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2656 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2657 // CHECK3-NEXT: ret void 2658 // 2659 // 2660 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2661 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { 2662 // CHECK3-NEXT: entry: 2663 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2664 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2665 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2666 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2667 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2668 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2669 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2670 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2671 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2672 // CHECK3-NEXT: ret void 2673 // 2674 // 2675 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 2676 // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { 2677 // CHECK3-NEXT: entry: 2678 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2679 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2680 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2681 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2682 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2683 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2684 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2685 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2686 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2687 // CHECK3-NEXT: ret void 2688 // 2689 // 2690 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2691 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { 2692 // CHECK3-NEXT: entry: 2693 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2694 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2695 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2696 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2697 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2698 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2699 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2700 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2701 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2702 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 2703 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2704 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 2705 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2706 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2707 // CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 2708 // CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 2709 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 2710 // CHECK3: .cancel.exit: 2711 // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 2712 // CHECK3-NEXT: br label [[DOTCANCEL_CONTINUE]] 2713 // CHECK3: .cancel.continue: 2714 // CHECK3-NEXT: ret void 2715 // 2716 // 2717 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 2718 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 2719 // CHECK3-NEXT: entry: 2720 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2721 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2722 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2723 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2724 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2725 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2726 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2727 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2728 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2729 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2730 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2731 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2732 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2733 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2734 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2735 // CHECK3-NEXT: ret void 2736 // 2737 // 2738 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 2739 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { 2740 // CHECK3-NEXT: entry: 2741 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2742 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2743 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2744 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2745 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2746 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2747 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2748 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2749 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2750 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2751 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2752 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2753 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 2754 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 2755 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 2756 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 2757 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 2758 // CHECK3-NEXT: ret void 2759 // 2760 // 2761 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 2762 // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 2763 // CHECK3-NEXT: entry: 2764 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2765 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2766 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2767 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2768 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2769 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2770 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2771 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2772 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2773 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2774 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2775 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2776 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2777 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2778 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2779 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2780 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2781 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2782 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2783 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2784 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2785 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2786 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2787 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2788 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2789 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2790 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2791 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2792 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2793 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2794 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2795 // CHECK3-NEXT: ret void 2796 // 2797 // 2798 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 2799 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 2800 // CHECK3-NEXT: entry: 2801 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2802 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2803 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2804 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2805 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2806 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2807 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2808 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2809 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2810 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2811 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2812 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2813 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2814 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2815 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2816 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2817 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2818 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2819 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2820 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2821 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2822 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2823 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2824 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2825 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2826 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2827 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2828 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2829 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2830 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2831 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2832 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 2833 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2834 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2835 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2836 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 2837 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 2838 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 2839 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 2840 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2841 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2842 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 2843 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 2844 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 2845 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 2846 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2847 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 2848 // CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 2849 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 2850 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 2851 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 2852 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 2853 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 2854 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 2855 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 2856 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 2857 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2858 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 2859 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 2860 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 2861 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2862 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 2863 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 2864 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 2865 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 2866 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 2867 // CHECK3-NEXT: ret void 2868 // 2869 // 2870 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2871 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 2872 // CHECK3-NEXT: entry: 2873 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2874 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2875 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2876 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2877 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2878 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2879 // CHECK3-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 2880 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2881 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2882 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2883 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2884 // CHECK3-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 2885 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2886 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2887 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2888 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2889 // CHECK3-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 2890 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2891 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2892 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2893 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2894 // CHECK3-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 2895 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2896 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2897 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2898 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2899 // CHECK3-NEXT: ret i32 [[TMP8]] 2900 // 2901 // 2902 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2903 // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2904 // CHECK3-NEXT: entry: 2905 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2906 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2907 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2908 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2909 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2910 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2911 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2912 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2913 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2914 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2915 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2916 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2917 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2918 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2919 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2920 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 2921 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2922 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2923 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2924 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2925 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2926 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2927 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 2928 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 2929 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 2930 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2931 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 2932 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2933 // CHECK3: omp_if.then: 2934 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2935 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 2936 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 2937 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 2938 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2939 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 2940 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 2941 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2942 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 2943 // CHECK3-NEXT: store double* [[A]], double** [[TMP13]], align 4 2944 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2945 // CHECK3-NEXT: store i64 8, i64* [[TMP14]], align 4 2946 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2947 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 2948 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2949 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 2950 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 2951 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2952 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 2953 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 2954 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 2955 // CHECK3-NEXT: store i64 4, i64* [[TMP20]], align 4 2956 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2957 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 2958 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2959 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 2960 // CHECK3-NEXT: store i32 2, i32* [[TMP23]], align 4 2961 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2962 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 2963 // CHECK3-NEXT: store i32 2, i32* [[TMP25]], align 4 2964 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 2965 // CHECK3-NEXT: store i64 4, i64* [[TMP26]], align 4 2966 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2967 // CHECK3-NEXT: store i8* null, i8** [[TMP27]], align 4 2968 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2969 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 2970 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 2971 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2972 // CHECK3-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 2973 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 2974 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 2975 // CHECK3-NEXT: store i64 4, i64* [[TMP32]], align 4 2976 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2977 // CHECK3-NEXT: store i8* null, i8** [[TMP33]], align 4 2978 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2979 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 2980 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 2981 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2982 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 2983 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 2984 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2985 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 2986 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2987 // CHECK3-NEXT: store i8* null, i8** [[TMP39]], align 4 2988 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2989 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2990 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2991 // CHECK3-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2992 // CHECK3-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 2993 // CHECK3-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2994 // CHECK3: omp_offload.failed: 2995 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 2996 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2997 // CHECK3: omp_offload.cont: 2998 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2999 // CHECK3: omp_if.else: 3000 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 3001 // CHECK3-NEXT: br label [[OMP_IF_END]] 3002 // CHECK3: omp_if.end: 3003 // CHECK3-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 3004 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 3005 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3006 // CHECK3-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 3007 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 3008 // CHECK3-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 3009 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 3010 // CHECK3-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3011 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 3012 // CHECK3-NEXT: ret i32 [[ADD3]] 3013 // 3014 // 3015 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 3016 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 3017 // CHECK3-NEXT: entry: 3018 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3019 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3020 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3021 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 3022 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3023 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3024 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3025 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3026 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 3027 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 3028 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 3029 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3030 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3031 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3032 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 3033 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3034 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3035 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3036 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3037 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3038 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3039 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3040 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 3041 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3042 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 3043 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3044 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3045 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 3046 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3047 // CHECK3: omp_if.then: 3048 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3049 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3050 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3051 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3052 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 3053 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 3054 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3055 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 3056 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3057 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3058 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3059 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3060 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 3061 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 3062 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3063 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 3064 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3065 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 3066 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 3067 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3068 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 3069 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 3070 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3071 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 3072 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3073 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 3074 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 3075 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3076 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 3077 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 3078 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3079 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 3080 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3081 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3082 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3083 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 3084 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3085 // CHECK3: omp_offload.failed: 3086 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3087 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3088 // CHECK3: omp_offload.cont: 3089 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3090 // CHECK3: omp_if.else: 3091 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 3092 // CHECK3-NEXT: br label [[OMP_IF_END]] 3093 // CHECK3: omp_if.end: 3094 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 3095 // CHECK3-NEXT: ret i32 [[TMP31]] 3096 // 3097 // 3098 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 3099 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 3100 // CHECK3-NEXT: entry: 3101 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3102 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 3103 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 3104 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 3105 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3106 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3107 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 3108 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 3109 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 3110 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3111 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 3112 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 3113 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 3114 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3115 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3116 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 3117 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3118 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 3119 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3120 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3121 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 3122 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3123 // CHECK3: omp_if.then: 3124 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3125 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 3126 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 3127 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3128 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 3129 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 3130 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3131 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 3132 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3133 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 3134 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 3135 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3136 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 3137 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 3138 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3139 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 3140 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3141 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 3142 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 3143 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3144 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 3145 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 3146 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3147 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 3148 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3149 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3150 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3151 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 3152 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3153 // CHECK3: omp_offload.failed: 3154 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3155 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 3156 // CHECK3: omp_offload.cont: 3157 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 3158 // CHECK3: omp_if.else: 3159 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 3160 // CHECK3-NEXT: br label [[OMP_IF_END]] 3161 // CHECK3: omp_if.end: 3162 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 3163 // CHECK3-NEXT: ret i32 [[TMP24]] 3164 // 3165 // 3166 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 3167 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 3168 // CHECK3-NEXT: entry: 3169 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3170 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3171 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3172 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3173 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3174 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3175 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3176 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3177 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3178 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3179 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3180 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3181 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3182 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3183 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3184 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3185 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3186 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3187 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3188 // CHECK3-NEXT: ret void 3189 // 3190 // 3191 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9 3192 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 3193 // CHECK3-NEXT: entry: 3194 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3195 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3196 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3197 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3198 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3199 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3200 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3201 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3202 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3203 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3204 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3205 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3206 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3207 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3208 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3209 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3210 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3211 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3212 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3213 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 3214 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3215 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3216 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 3217 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3218 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 3219 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 3220 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 4 3221 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 3222 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 3223 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 3224 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3225 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 3226 // CHECK3-NEXT: ret void 3227 // 3228 // 3229 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 3230 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3231 // CHECK3-NEXT: entry: 3232 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3233 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3234 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3235 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3236 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3237 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3238 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3239 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3240 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3241 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3242 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3243 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3244 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3245 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3246 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3247 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3248 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3249 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3250 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3251 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 3252 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3253 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 3254 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3255 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 3256 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3257 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 3258 // CHECK3-NEXT: ret void 3259 // 3260 // 3261 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11 3262 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3263 // CHECK3-NEXT: entry: 3264 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3265 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3266 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3267 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3268 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3269 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3270 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3271 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3272 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3273 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3274 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3275 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3276 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3277 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3278 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3279 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3280 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3281 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3282 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3283 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 3284 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3285 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3286 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 3287 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 3288 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 3289 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 3290 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 3291 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 3292 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3293 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3294 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 3295 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 3296 // CHECK3-NEXT: ret void 3297 // 3298 // 3299 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 3300 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 3301 // CHECK3-NEXT: entry: 3302 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3303 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3304 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3305 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3306 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3307 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3308 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3309 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3310 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3311 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3312 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3313 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3314 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3315 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3316 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3317 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3318 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3319 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3320 // CHECK3-NEXT: ret void 3321 // 3322 // 3323 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14 3324 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 3325 // CHECK3-NEXT: entry: 3326 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3327 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3328 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3329 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3330 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3331 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3332 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3333 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3334 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3335 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3336 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3337 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3338 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3339 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3340 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3341 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3342 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 3343 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3344 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3345 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3346 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3347 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3348 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 3349 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 3350 // CHECK3-NEXT: ret void 3351 // 3352 // 3353 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 3354 // CHECK3-SAME: () #[[ATTR7:[0-9]+]] { 3355 // CHECK3-NEXT: entry: 3356 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 3357 // CHECK3-NEXT: ret void 3358 // 3359 // 3360 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi 3361 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 3362 // CHECK4-NEXT: entry: 3363 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3364 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 3365 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 3366 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x float], align 4 3367 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3368 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3369 // CHECK4-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 3370 // CHECK4-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 3371 // CHECK4-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 3372 // CHECK4-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 3373 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3374 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3375 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 3376 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 3377 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 3378 // CHECK4-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 3379 // CHECK4-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 3380 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 3381 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 3382 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 3383 // CHECK4-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 3384 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 3385 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 3386 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 3387 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 3388 // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 3389 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3390 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 3391 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 3392 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3393 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3394 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3395 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 3396 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3397 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 3398 // CHECK4-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 3399 // CHECK4-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 3400 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 3401 // CHECK4-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 3402 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 3403 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 3404 // CHECK4-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 3405 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 3406 // CHECK4-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 3407 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 3408 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 3409 // CHECK4-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 3410 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3411 // CHECK4-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 3412 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3413 // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3414 // CHECK4-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 3415 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 3416 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3417 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 3418 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 3419 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3420 // CHECK4-NEXT: store i8* null, i8** [[TMP17]], align 4 3421 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3422 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3423 // CHECK4-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3424 // CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 3425 // CHECK4-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 3426 // CHECK4: omp_offload.failed: 3427 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 3428 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 3429 // CHECK4: omp_offload.cont: 3430 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 3431 // CHECK4-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 3432 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 3433 // CHECK4-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 3434 // CHECK4-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 3435 // CHECK4-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 3436 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 3437 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 3438 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 3439 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3440 // CHECK4: omp_if.then: 3441 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3442 // CHECK4-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 3443 // CHECK4-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 3444 // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3445 // CHECK4-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 3446 // CHECK4-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 3447 // CHECK4-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 3448 // CHECK4-NEXT: store i8* null, i8** [[TMP31]], align 4 3449 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 3450 // CHECK4-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* 3451 // CHECK4-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 3452 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 3453 // CHECK4-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 3454 // CHECK4-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 3455 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 3456 // CHECK4-NEXT: store i8* null, i8** [[TMP36]], align 4 3457 // CHECK4-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 3458 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 3459 // CHECK4-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3460 // CHECK4-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 3461 // CHECK4-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 3462 // CHECK4: omp_offload.failed8: 3463 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 3464 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT9]] 3465 // CHECK4: omp_offload.cont9: 3466 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 3467 // CHECK4: omp_if.else: 3468 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 3469 // CHECK4-NEXT: br label [[OMP_IF_END]] 3470 // CHECK4: omp_if.end: 3471 // CHECK4-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 3472 // CHECK4-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 3473 // CHECK4-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 3474 // CHECK4-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 3475 // CHECK4-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 3476 // CHECK4-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] 3477 // CHECK4: omp_if.then12: 3478 // CHECK4-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 3479 // CHECK4-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 3480 // CHECK4-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] 3481 // CHECK4-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 3482 // CHECK4-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 3483 // CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 3484 // CHECK4-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* 3485 // CHECK4-NEXT: store i32 [[TMP42]], i32* [[TMP50]], align 4 3486 // CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 3487 // CHECK4-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* 3488 // CHECK4-NEXT: store i32 [[TMP42]], i32* [[TMP52]], align 4 3489 // CHECK4-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3490 // CHECK4-NEXT: store i64 4, i64* [[TMP53]], align 4 3491 // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 3492 // CHECK4-NEXT: store i8* null, i8** [[TMP54]], align 4 3493 // CHECK4-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 3494 // CHECK4-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 3495 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 3496 // CHECK4-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 3497 // CHECK4-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 3498 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 3499 // CHECK4-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 3500 // CHECK4-NEXT: store i64 40, i64* [[TMP59]], align 4 3501 // CHECK4-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 3502 // CHECK4-NEXT: store i8* null, i8** [[TMP60]], align 4 3503 // CHECK4-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 3504 // CHECK4-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 3505 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP62]], align 4 3506 // CHECK4-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 3507 // CHECK4-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* 3508 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP64]], align 4 3509 // CHECK4-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 3510 // CHECK4-NEXT: store i64 4, i64* [[TMP65]], align 4 3511 // CHECK4-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 3512 // CHECK4-NEXT: store i8* null, i8** [[TMP66]], align 4 3513 // CHECK4-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 3514 // CHECK4-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 3515 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 3516 // CHECK4-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 3517 // CHECK4-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** 3518 // CHECK4-NEXT: store float* [[VLA]], float** [[TMP70]], align 4 3519 // CHECK4-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3520 // CHECK4-NEXT: store i64 [[TMP45]], i64* [[TMP71]], align 4 3521 // CHECK4-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 3522 // CHECK4-NEXT: store i8* null, i8** [[TMP72]], align 4 3523 // CHECK4-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 3524 // CHECK4-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 3525 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 3526 // CHECK4-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 3527 // CHECK4-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** 3528 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4 3529 // CHECK4-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3530 // CHECK4-NEXT: store i64 400, i64* [[TMP77]], align 4 3531 // CHECK4-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 3532 // CHECK4-NEXT: store i8* null, i8** [[TMP78]], align 4 3533 // CHECK4-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 3534 // CHECK4-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* 3535 // CHECK4-NEXT: store i32 5, i32* [[TMP80]], align 4 3536 // CHECK4-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 3537 // CHECK4-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* 3538 // CHECK4-NEXT: store i32 5, i32* [[TMP82]], align 4 3539 // CHECK4-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 3540 // CHECK4-NEXT: store i64 4, i64* [[TMP83]], align 4 3541 // CHECK4-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 3542 // CHECK4-NEXT: store i8* null, i8** [[TMP84]], align 4 3543 // CHECK4-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 3544 // CHECK4-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* 3545 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP86]], align 4 3546 // CHECK4-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 3547 // CHECK4-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 3548 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP88]], align 4 3549 // CHECK4-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 3550 // CHECK4-NEXT: store i64 4, i64* [[TMP89]], align 4 3551 // CHECK4-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 3552 // CHECK4-NEXT: store i8* null, i8** [[TMP90]], align 4 3553 // CHECK4-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 3554 // CHECK4-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** 3555 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP92]], align 4 3556 // CHECK4-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 3557 // CHECK4-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** 3558 // CHECK4-NEXT: store double* [[VLA1]], double** [[TMP94]], align 4 3559 // CHECK4-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 3560 // CHECK4-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 4 3561 // CHECK4-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 3562 // CHECK4-NEXT: store i8* null, i8** [[TMP96]], align 4 3563 // CHECK4-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 3564 // CHECK4-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** 3565 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4 3566 // CHECK4-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 3567 // CHECK4-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** 3568 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4 3569 // CHECK4-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 3570 // CHECK4-NEXT: store i64 12, i64* [[TMP101]], align 4 3571 // CHECK4-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 3572 // CHECK4-NEXT: store i8* null, i8** [[TMP102]], align 4 3573 // CHECK4-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 3574 // CHECK4-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 3575 // CHECK4-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3576 // CHECK4-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3577 // CHECK4-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 3578 // CHECK4-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 3579 // CHECK4: omp_offload.failed16: 3580 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 3581 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT17]] 3582 // CHECK4: omp_offload.cont17: 3583 // CHECK4-NEXT: br label [[OMP_IF_END19:%.*]] 3584 // CHECK4: omp_if.else18: 3585 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 3586 // CHECK4-NEXT: br label [[OMP_IF_END19]] 3587 // CHECK4: omp_if.end19: 3588 // CHECK4-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 3589 // CHECK4-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 3590 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) 3591 // CHECK4-NEXT: ret i32 [[TMP108]] 3592 // 3593 // 3594 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 3595 // CHECK4-SAME: () #[[ATTR2:[0-9]+]] { 3596 // CHECK4-NEXT: entry: 3597 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 3598 // CHECK4-NEXT: ret void 3599 // 3600 // 3601 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 3602 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 3603 // CHECK4-NEXT: entry: 3604 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3605 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3606 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3607 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3608 // CHECK4-NEXT: ret void 3609 // 3610 // 3611 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry. 3612 // CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 3613 // CHECK4-NEXT: entry: 3614 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 3615 // CHECK4-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 3616 // CHECK4-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 3617 // CHECK4-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 3618 // CHECK4-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 3619 // CHECK4-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 3620 // CHECK4-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 3621 // CHECK4-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 3622 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 3623 // CHECK4-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 3624 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 3625 // CHECK4-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 3626 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 3627 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 3628 // CHECK4-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 3629 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 3630 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 3631 // CHECK4-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 3632 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 3633 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 3634 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 3635 // CHECK4-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 3636 // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 3637 // CHECK4-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 3638 // CHECK4-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 3639 // CHECK4-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 3640 // CHECK4-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 3641 // CHECK4-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 3642 // CHECK4-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 3643 // CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 3644 // CHECK4-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 3645 // CHECK4-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 3646 // CHECK4: omp_offload.failed.i: 3647 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 3648 // CHECK4-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 3649 // CHECK4: .omp_outlined..1.exit: 3650 // CHECK4-NEXT: ret i32 0 3651 // 3652 // 3653 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 3654 // CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { 3655 // CHECK4-NEXT: entry: 3656 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3657 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3658 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3659 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3660 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3661 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3662 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3663 // CHECK4-NEXT: ret void 3664 // 3665 // 3666 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 3667 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { 3668 // CHECK4-NEXT: entry: 3669 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3670 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3671 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3672 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3673 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3674 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3675 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3676 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3677 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3678 // CHECK4-NEXT: ret void 3679 // 3680 // 3681 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 3682 // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { 3683 // CHECK4-NEXT: entry: 3684 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3685 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3686 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3687 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3688 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3689 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3690 // CHECK4-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3691 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3692 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3693 // CHECK4-NEXT: ret void 3694 // 3695 // 3696 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 3697 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { 3698 // CHECK4-NEXT: entry: 3699 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3700 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3701 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3702 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3703 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3704 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3705 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3706 // CHECK4-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3707 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3708 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 3709 // CHECK4-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 3710 // CHECK4-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 3711 // CHECK4-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3712 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3713 // CHECK4-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 3714 // CHECK4-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 3715 // CHECK4-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 3716 // CHECK4: .cancel.exit: 3717 // CHECK4-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 3718 // CHECK4-NEXT: br label [[DOTCANCEL_CONTINUE]] 3719 // CHECK4: .cancel.continue: 3720 // CHECK4-NEXT: ret void 3721 // 3722 // 3723 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 3724 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 3725 // CHECK4-NEXT: entry: 3726 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3727 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3728 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3729 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3730 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3731 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3732 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3733 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3734 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3735 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3736 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3737 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3738 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3739 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3740 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 3741 // CHECK4-NEXT: ret void 3742 // 3743 // 3744 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 3745 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { 3746 // CHECK4-NEXT: entry: 3747 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3748 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3749 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3750 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3751 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3752 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3753 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3754 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3755 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3756 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3757 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3758 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3759 // CHECK4-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 3760 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 3761 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3762 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3763 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3764 // CHECK4-NEXT: ret void 3765 // 3766 // 3767 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 3768 // CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 3769 // CHECK4-NEXT: entry: 3770 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3771 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3772 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3773 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3774 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3775 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3776 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3777 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3778 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3779 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3780 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3781 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3782 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3783 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3784 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3785 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3786 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3787 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3788 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3789 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3790 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3791 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3792 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3793 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3794 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3795 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3796 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3797 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3798 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 3799 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 3800 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 3801 // CHECK4-NEXT: ret void 3802 // 3803 // 3804 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 3805 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 3806 // CHECK4-NEXT: entry: 3807 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3808 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3809 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3810 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3811 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3812 // CHECK4-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3813 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3814 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3815 // CHECK4-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3816 // CHECK4-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3817 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3818 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3819 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3820 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3821 // CHECK4-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3822 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3823 // CHECK4-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3824 // CHECK4-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3825 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3826 // CHECK4-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3827 // CHECK4-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3828 // CHECK4-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3829 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3830 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3831 // CHECK4-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3832 // CHECK4-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3833 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3834 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3835 // CHECK4-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3836 // CHECK4-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3837 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3838 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 3839 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3840 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 3841 // CHECK4-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 3842 // CHECK4-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 3843 // CHECK4-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 3844 // CHECK4-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 3845 // CHECK4-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 3846 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 3847 // CHECK4-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3848 // CHECK4-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 3849 // CHECK4-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 3850 // CHECK4-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 3851 // CHECK4-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 3852 // CHECK4-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 3853 // CHECK4-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 3854 // CHECK4-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 3855 // CHECK4-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 3856 // CHECK4-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 3857 // CHECK4-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 3858 // CHECK4-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 3859 // CHECK4-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 3860 // CHECK4-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 3861 // CHECK4-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 3862 // CHECK4-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 3863 // CHECK4-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 3864 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 3865 // CHECK4-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 3866 // CHECK4-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 3867 // CHECK4-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 3868 // CHECK4-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 3869 // CHECK4-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 3870 // CHECK4-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 3871 // CHECK4-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 3872 // CHECK4-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 3873 // CHECK4-NEXT: ret void 3874 // 3875 // 3876 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari 3877 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 3878 // CHECK4-NEXT: entry: 3879 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3880 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 3881 // CHECK4-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 3882 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3883 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 3884 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3885 // CHECK4-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 3886 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 3887 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 3888 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A]], align 4 3889 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 3890 // CHECK4-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 3891 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 3892 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 3893 // CHECK4-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 3894 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 3895 // CHECK4-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 3896 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 3897 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 3898 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 3899 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3900 // CHECK4-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 3901 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 3902 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 3903 // CHECK4-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 3904 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 3905 // CHECK4-NEXT: ret i32 [[TMP8]] 3906 // 3907 // 3908 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 3909 // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 3910 // CHECK4-NEXT: entry: 3911 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3912 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3913 // CHECK4-NEXT: [[B:%.*]] = alloca i32, align 4 3914 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 3915 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 3916 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3917 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 3918 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 3919 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 3920 // CHECK4-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 3921 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3922 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3923 // CHECK4-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3924 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3925 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3926 // CHECK4-NEXT: store i32 [[ADD]], i32* [[B]], align 4 3927 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 3928 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3929 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 3930 // CHECK4-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 3931 // CHECK4-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 3932 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 3933 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 3934 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3935 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3936 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3937 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 3938 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 3939 // CHECK4: omp_if.then: 3940 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 3941 // CHECK4-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 3942 // CHECK4-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 3943 // CHECK4-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 3944 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3945 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 3946 // CHECK4-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 3947 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3948 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 3949 // CHECK4-NEXT: store double* [[A]], double** [[TMP13]], align 4 3950 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3951 // CHECK4-NEXT: store i64 8, i64* [[TMP14]], align 4 3952 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 3953 // CHECK4-NEXT: store i8* null, i8** [[TMP15]], align 4 3954 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 3955 // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 3956 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 3957 // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 3958 // CHECK4-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 3959 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 3960 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 3961 // CHECK4-NEXT: store i64 4, i64* [[TMP20]], align 4 3962 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 3963 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 3964 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 3965 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 3966 // CHECK4-NEXT: store i32 2, i32* [[TMP23]], align 4 3967 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 3968 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 3969 // CHECK4-NEXT: store i32 2, i32* [[TMP25]], align 4 3970 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 3971 // CHECK4-NEXT: store i64 4, i64* [[TMP26]], align 4 3972 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 3973 // CHECK4-NEXT: store i8* null, i8** [[TMP27]], align 4 3974 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 3975 // CHECK4-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 3976 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 3977 // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 3978 // CHECK4-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 3979 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 3980 // CHECK4-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 3981 // CHECK4-NEXT: store i64 4, i64* [[TMP32]], align 4 3982 // CHECK4-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 3983 // CHECK4-NEXT: store i8* null, i8** [[TMP33]], align 4 3984 // CHECK4-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 3985 // CHECK4-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 3986 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 3987 // CHECK4-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 3988 // CHECK4-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 3989 // CHECK4-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 3990 // CHECK4-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 3991 // CHECK4-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 3992 // CHECK4-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 3993 // CHECK4-NEXT: store i8* null, i8** [[TMP39]], align 4 3994 // CHECK4-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 3995 // CHECK4-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 3996 // CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 3997 // CHECK4-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 3998 // CHECK4-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 3999 // CHECK4-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4000 // CHECK4: omp_offload.failed: 4001 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 4002 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 4003 // CHECK4: omp_offload.cont: 4004 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 4005 // CHECK4: omp_if.else: 4006 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 4007 // CHECK4-NEXT: br label [[OMP_IF_END]] 4008 // CHECK4: omp_if.end: 4009 // CHECK4-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 4010 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 4011 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4012 // CHECK4-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 4013 // CHECK4-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 4014 // CHECK4-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 4015 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 4016 // CHECK4-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 4017 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 4018 // CHECK4-NEXT: ret i32 [[ADD3]] 4019 // 4020 // 4021 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici 4022 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 4023 // CHECK4-NEXT: entry: 4024 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4025 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 4026 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 4027 // CHECK4-NEXT: [[AAA:%.*]] = alloca i8, align 1 4028 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4029 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4030 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4031 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4032 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 4033 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 4034 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 4035 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4036 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 4037 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 4038 // CHECK4-NEXT: store i8 0, i8* [[AAA]], align 1 4039 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4040 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4041 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4042 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4043 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4044 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4045 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4046 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 4047 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4048 // CHECK4-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 4049 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4050 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4051 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 4052 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4053 // CHECK4: omp_if.then: 4054 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4055 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4056 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4057 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4058 // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 4059 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 4060 // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4061 // CHECK4-NEXT: store i8* null, i8** [[TMP11]], align 4 4062 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4063 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4064 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4065 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4066 // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 4067 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 4068 // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4069 // CHECK4-NEXT: store i8* null, i8** [[TMP16]], align 4 4070 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4071 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 4072 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 4073 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4074 // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 4075 // CHECK4-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 4076 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4077 // CHECK4-NEXT: store i8* null, i8** [[TMP21]], align 4 4078 // CHECK4-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 4079 // CHECK4-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 4080 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 4081 // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 4082 // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 4083 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 4084 // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 4085 // CHECK4-NEXT: store i8* null, i8** [[TMP26]], align 4 4086 // CHECK4-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4087 // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4088 // CHECK4-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4089 // CHECK4-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 4090 // CHECK4-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4091 // CHECK4: omp_offload.failed: 4092 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4093 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 4094 // CHECK4: omp_offload.cont: 4095 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 4096 // CHECK4: omp_if.else: 4097 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 4098 // CHECK4-NEXT: br label [[OMP_IF_END]] 4099 // CHECK4: omp_if.end: 4100 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 4101 // CHECK4-NEXT: ret i32 [[TMP31]] 4102 // 4103 // 4104 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 4105 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 4106 // CHECK4-NEXT: entry: 4107 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4108 // CHECK4-NEXT: [[A:%.*]] = alloca i32, align 4 4109 // CHECK4-NEXT: [[AA:%.*]] = alloca i16, align 2 4110 // CHECK4-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 4111 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4112 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4113 // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 4114 // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 4115 // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 4116 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4117 // CHECK4-NEXT: store i32 0, i32* [[A]], align 4 4118 // CHECK4-NEXT: store i16 0, i16* [[AA]], align 2 4119 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 4120 // CHECK4-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 4121 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 4122 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 4123 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4124 // CHECK4-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 4125 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4126 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 4127 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 4128 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 4129 // CHECK4: omp_if.then: 4130 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4131 // CHECK4-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 4132 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 4133 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4134 // CHECK4-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 4135 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 4136 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 4137 // CHECK4-NEXT: store i8* null, i8** [[TMP9]], align 4 4138 // CHECK4-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 4139 // CHECK4-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 4140 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 4141 // CHECK4-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 4142 // CHECK4-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 4143 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 4144 // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 4145 // CHECK4-NEXT: store i8* null, i8** [[TMP14]], align 4 4146 // CHECK4-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 4147 // CHECK4-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 4148 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 4149 // CHECK4-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 4150 // CHECK4-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 4151 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 4152 // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 4153 // CHECK4-NEXT: store i8* null, i8** [[TMP19]], align 4 4154 // CHECK4-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 4155 // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 4156 // CHECK4-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 4157 // CHECK4-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 4158 // CHECK4-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 4159 // CHECK4: omp_offload.failed: 4160 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4161 // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] 4162 // CHECK4: omp_offload.cont: 4163 // CHECK4-NEXT: br label [[OMP_IF_END:%.*]] 4164 // CHECK4: omp_if.else: 4165 // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 4166 // CHECK4-NEXT: br label [[OMP_IF_END]] 4167 // CHECK4: omp_if.end: 4168 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 4169 // CHECK4-NEXT: ret i32 [[TMP24]] 4170 // 4171 // 4172 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 4173 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 4174 // CHECK4-NEXT: entry: 4175 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4176 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4177 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4178 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4179 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4180 // CHECK4-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 4181 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4182 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4183 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4184 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4185 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4186 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4187 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4188 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4189 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4190 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4191 // CHECK4-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 4192 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 4193 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 4194 // CHECK4-NEXT: ret void 4195 // 4196 // 4197 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9 4198 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 4199 // CHECK4-NEXT: entry: 4200 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4201 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4202 // CHECK4-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 4203 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 4204 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 4205 // CHECK4-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 4206 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 4207 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4208 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4209 // CHECK4-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 4210 // CHECK4-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 4211 // CHECK4-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 4212 // CHECK4-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 4213 // CHECK4-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 4214 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 4215 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 4216 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 4217 // CHECK4-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 4218 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 4219 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 4220 // CHECK4-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 4221 // CHECK4-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4222 // CHECK4-NEXT: store double [[ADD]], double* [[A]], align 4 4223 // CHECK4-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4224 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 4225 // CHECK4-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 4226 // CHECK4-NEXT: store double [[INC]], double* [[A3]], align 4 4227 // CHECK4-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 4228 // CHECK4-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 4229 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 4230 // CHECK4-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 4231 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 4232 // CHECK4-NEXT: ret void 4233 // 4234 // 4235 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 4236 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4237 // CHECK4-NEXT: entry: 4238 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4239 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4240 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4241 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4242 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4243 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4244 // CHECK4-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 4245 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4246 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4247 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4248 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4249 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4250 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4251 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4252 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4253 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4254 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4255 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4256 // CHECK4-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4257 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 4258 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4259 // CHECK4-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 4260 // CHECK4-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 4261 // CHECK4-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 4262 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 4263 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 4264 // CHECK4-NEXT: ret void 4265 // 4266 // 4267 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11 4268 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 4269 // CHECK4-NEXT: entry: 4270 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4271 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4272 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4273 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4274 // CHECK4-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 4275 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4276 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4277 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4278 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4279 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4280 // CHECK4-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 4281 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4282 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4283 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 4284 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4285 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4286 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4287 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4288 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4289 // CHECK4-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 4290 // CHECK4-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4291 // CHECK4-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4292 // CHECK4-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 4293 // CHECK4-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 4294 // CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 4295 // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 4296 // CHECK4-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 4297 // CHECK4-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 4298 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4299 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4300 // CHECK4-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 4301 // CHECK4-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 4302 // CHECK4-NEXT: ret void 4303 // 4304 // 4305 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 4306 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 4307 // CHECK4-NEXT: entry: 4308 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4309 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4310 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4311 // CHECK4-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 4312 // CHECK4-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 4313 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4314 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4315 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4316 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4317 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4318 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4319 // CHECK4-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 4320 // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 4321 // CHECK4-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 4322 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 4323 // CHECK4-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 4324 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 4325 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 4326 // CHECK4-NEXT: ret void 4327 // 4328 // 4329 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14 4330 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 4331 // CHECK4-NEXT: entry: 4332 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 4333 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 4334 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 4335 // CHECK4-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 4336 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 4337 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 4338 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 4339 // CHECK4-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 4340 // CHECK4-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 4341 // CHECK4-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 4342 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 4343 // CHECK4-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 4344 // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 4345 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4346 // CHECK4-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 4347 // CHECK4-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 4348 // CHECK4-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 4349 // CHECK4-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 4350 // CHECK4-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 4351 // CHECK4-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 4352 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 4353 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4354 // CHECK4-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 4355 // CHECK4-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 4356 // CHECK4-NEXT: ret void 4357 // 4358 // 4359 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 4360 // CHECK4-SAME: () #[[ATTR7:[0-9]+]] { 4361 // CHECK4-NEXT: entry: 4362 // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) 4363 // CHECK4-NEXT: ret void 4364 // 4365 // 4366 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 4367 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 4368 // CHECK9-NEXT: entry: 4369 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4370 // CHECK9-NEXT: ret void 4371 // 4372 // 4373 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 4374 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 4375 // CHECK9-NEXT: entry: 4376 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4377 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4378 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4379 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4380 // CHECK9-NEXT: ret void 4381 // 4382 // 4383 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 4384 // CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 4385 // CHECK9-NEXT: entry: 4386 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4387 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4388 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4389 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4390 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4391 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4392 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4393 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4394 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 4395 // CHECK9-NEXT: ret void 4396 // 4397 // 4398 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 4399 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { 4400 // CHECK9-NEXT: entry: 4401 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4402 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4403 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4404 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4405 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4406 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4407 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4408 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4409 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 4410 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 4411 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 4412 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 4413 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4414 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4415 // CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 4416 // CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 4417 // CHECK9-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 4418 // CHECK9: .cancel.exit: 4419 // CHECK9-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 4420 // CHECK9-NEXT: br label [[DOTCANCEL_CONTINUE]] 4421 // CHECK9: .cancel.continue: 4422 // CHECK9-NEXT: ret void 4423 // 4424 // 4425 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 4426 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 4427 // CHECK9-NEXT: entry: 4428 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4429 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4430 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4431 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4432 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4433 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4434 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4435 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4436 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4437 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4438 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 4439 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4440 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4441 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4442 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 4443 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4444 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 4445 // CHECK9-NEXT: ret void 4446 // 4447 // 4448 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 4449 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { 4450 // CHECK9-NEXT: entry: 4451 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4452 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4453 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4454 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4455 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4456 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4457 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4458 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4459 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4460 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4461 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4462 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4463 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4464 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 4465 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 4466 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4467 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4468 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 4469 // CHECK9-NEXT: ret void 4470 // 4471 // 4472 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 4473 // CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 4474 // CHECK9-NEXT: entry: 4475 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4476 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4477 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4478 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4479 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4480 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4481 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4482 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4483 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4484 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4485 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4486 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4487 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4488 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4489 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4490 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4491 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4492 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4493 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4494 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4495 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4496 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4497 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4498 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4499 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4500 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4501 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4502 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4503 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4504 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4505 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 4506 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 4507 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 4508 // CHECK9-NEXT: ret void 4509 // 4510 // 4511 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 4512 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 4513 // CHECK9-NEXT: entry: 4514 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4515 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4516 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4517 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4518 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4519 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4520 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4521 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4522 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4523 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4524 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4525 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4526 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4527 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4528 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4529 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4530 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4531 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4532 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4533 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4534 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4535 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4536 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4537 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4538 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4539 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4540 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4541 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4542 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4543 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4544 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4545 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4546 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 4547 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4548 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 4549 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 4550 // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 4551 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 4552 // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 4553 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 4554 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 4555 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 4556 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 4557 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 4558 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 4559 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 4560 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 4561 // CHECK9-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 4562 // CHECK9-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 4563 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 4564 // CHECK9-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 4565 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 4566 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 4567 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 4568 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 4569 // CHECK9-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 4570 // CHECK9-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 4571 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4572 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 4573 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 4574 // CHECK9-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 4575 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4576 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 4577 // CHECK9-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 4578 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 4579 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 4580 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 4581 // CHECK9-NEXT: ret void 4582 // 4583 // 4584 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 4585 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4586 // CHECK9-NEXT: entry: 4587 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4588 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4589 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4590 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4591 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4592 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4593 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 4594 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4595 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4596 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4597 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4598 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4599 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4600 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4601 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4602 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4603 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4604 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 4605 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4606 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4607 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4608 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 4609 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4610 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 4611 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 4612 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 4613 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 4614 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 4615 // CHECK9-NEXT: ret void 4616 // 4617 // 4618 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 4619 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 4620 // CHECK9-NEXT: entry: 4621 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4622 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4623 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4624 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4625 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 4626 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4627 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4628 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4629 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4630 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4631 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 4632 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4633 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4634 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4635 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 4636 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4637 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4638 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4639 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4640 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4641 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 4642 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 4643 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 4644 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 4645 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 4646 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 4647 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 4648 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 4649 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 4650 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 4651 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4652 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 4653 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 4654 // CHECK9-NEXT: ret void 4655 // 4656 // 4657 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 4658 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 4659 // CHECK9-NEXT: entry: 4660 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4661 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4662 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4663 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4664 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4665 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 4666 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4667 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4668 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4669 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4670 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4671 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4672 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4673 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4674 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4675 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4676 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 4677 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 4678 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 4679 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 4680 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 4681 // CHECK9-NEXT: ret void 4682 // 4683 // 4684 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 4685 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 4686 // CHECK9-NEXT: entry: 4687 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4688 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4689 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 4690 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 4691 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4692 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4693 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 4694 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4695 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4696 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 4697 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 4698 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4699 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4700 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 4701 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 4702 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 4703 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4704 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4705 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 4706 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 4707 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 4708 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 4709 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 4710 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 4711 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 4712 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 4713 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 4714 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 4715 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 4716 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 4717 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 4718 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 4719 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 4720 // CHECK9-NEXT: ret void 4721 // 4722 // 4723 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 4724 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 4725 // CHECK9-NEXT: entry: 4726 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4727 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4728 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4729 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4730 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4731 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4732 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4733 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4734 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4735 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4736 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4737 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4738 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4739 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 4740 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 4741 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 4742 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4743 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 4744 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4745 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 4746 // CHECK9-NEXT: ret void 4747 // 4748 // 4749 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 4750 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 4751 // CHECK9-NEXT: entry: 4752 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4753 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4754 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4755 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4756 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 4757 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4758 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4759 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4760 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4761 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 4762 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4763 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4764 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 4765 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 4766 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 4767 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4768 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4769 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 4770 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4771 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4772 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 4773 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 4774 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 4775 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 4776 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 4777 // CHECK9-NEXT: ret void 4778 // 4779 // 4780 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 4781 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] { 4782 // CHECK10-NEXT: entry: 4783 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 4784 // CHECK10-NEXT: ret void 4785 // 4786 // 4787 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. 4788 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 4789 // CHECK10-NEXT: entry: 4790 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4791 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4792 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4793 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4794 // CHECK10-NEXT: ret void 4795 // 4796 // 4797 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 4798 // CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 4799 // CHECK10-NEXT: entry: 4800 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4801 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4802 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4803 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4804 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4805 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4806 // CHECK10-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 4807 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4808 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 4809 // CHECK10-NEXT: ret void 4810 // 4811 // 4812 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 4813 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { 4814 // CHECK10-NEXT: entry: 4815 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4816 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4817 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4818 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4819 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4820 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4821 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4822 // CHECK10-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 4823 // CHECK10-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 4824 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 4825 // CHECK10-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 4826 // CHECK10-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 4827 // CHECK10-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4828 // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 4829 // CHECK10-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 4830 // CHECK10-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 4831 // CHECK10-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 4832 // CHECK10: .cancel.exit: 4833 // CHECK10-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 4834 // CHECK10-NEXT: br label [[DOTCANCEL_CONTINUE]] 4835 // CHECK10: .cancel.continue: 4836 // CHECK10-NEXT: ret void 4837 // 4838 // 4839 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 4840 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 4841 // CHECK10-NEXT: entry: 4842 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4843 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4844 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4845 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 4846 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4847 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4848 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4849 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4850 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4851 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4852 // CHECK10-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 4853 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 4854 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 4855 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 4856 // CHECK10-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 4857 // CHECK10-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 4858 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 4859 // CHECK10-NEXT: ret void 4860 // 4861 // 4862 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 4863 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { 4864 // CHECK10-NEXT: entry: 4865 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4866 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4867 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4868 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 4869 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4870 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4871 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4872 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 4873 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4874 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 4875 // CHECK10-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 4876 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 4877 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4878 // CHECK10-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 4879 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 4880 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 4881 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 4882 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 4883 // CHECK10-NEXT: ret void 4884 // 4885 // 4886 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 4887 // CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 4888 // CHECK10-NEXT: entry: 4889 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4890 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4891 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4892 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4893 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4894 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4895 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4896 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4897 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4898 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 4899 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4900 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4901 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4902 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4903 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4904 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4905 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4906 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4907 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4908 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4909 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4910 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4911 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4912 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4913 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4914 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4915 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4916 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4917 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4918 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 4919 // CHECK10-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 4920 // CHECK10-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 4921 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 4922 // CHECK10-NEXT: ret void 4923 // 4924 // 4925 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 4926 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 4927 // CHECK10-NEXT: entry: 4928 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4929 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4930 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 4931 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 4932 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4933 // CHECK10-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 4934 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 4935 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 4936 // CHECK10-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 4937 // CHECK10-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 4938 // CHECK10-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 4939 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4940 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4941 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 4942 // CHECK10-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 4943 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4944 // CHECK10-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 4945 // CHECK10-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 4946 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 4947 // CHECK10-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 4948 // CHECK10-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 4949 // CHECK10-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 4950 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 4951 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 4952 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4953 // CHECK10-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 4954 // CHECK10-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 4955 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 4956 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 4957 // CHECK10-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 4958 // CHECK10-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 4959 // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 4960 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 4961 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 4962 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 4963 // CHECK10-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 4964 // CHECK10-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 4965 // CHECK10-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 4966 // CHECK10-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 4967 // CHECK10-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 4968 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 4969 // CHECK10-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 4970 // CHECK10-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 4971 // CHECK10-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 4972 // CHECK10-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 4973 // CHECK10-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 4974 // CHECK10-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 4975 // CHECK10-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 4976 // CHECK10-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 4977 // CHECK10-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 4978 // CHECK10-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 4979 // CHECK10-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 4980 // CHECK10-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 4981 // CHECK10-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 4982 // CHECK10-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 4983 // CHECK10-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 4984 // CHECK10-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 4985 // CHECK10-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 4986 // CHECK10-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 4987 // CHECK10-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 4988 // CHECK10-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 4989 // CHECK10-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 4990 // CHECK10-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 4991 // CHECK10-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 4992 // CHECK10-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 4993 // CHECK10-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 4994 // CHECK10-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 4995 // CHECK10-NEXT: ret void 4996 // 4997 // 4998 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 4999 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5000 // CHECK10-NEXT: entry: 5001 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5002 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5003 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5004 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5005 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5006 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5007 // CHECK10-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 5008 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5009 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5010 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 5011 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5012 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5013 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5014 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 5015 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5016 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5017 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5018 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 5019 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 5020 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 5021 // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5022 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 5023 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5024 // CHECK10-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 5025 // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 5026 // CHECK10-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 5027 // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 5028 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 5029 // CHECK10-NEXT: ret void 5030 // 5031 // 5032 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4 5033 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5034 // CHECK10-NEXT: entry: 5035 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5036 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5037 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5038 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5039 // CHECK10-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 5040 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5041 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5042 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5043 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5044 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5045 // CHECK10-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 5046 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5047 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5048 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5049 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 5050 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5051 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5052 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5053 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 5054 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 5055 // CHECK10-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 5056 // CHECK10-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 5057 // CHECK10-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 5058 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 5059 // CHECK10-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 5060 // CHECK10-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 5061 // CHECK10-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 5062 // CHECK10-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 5063 // CHECK10-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 5064 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 5065 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5066 // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 5067 // CHECK10-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 5068 // CHECK10-NEXT: ret void 5069 // 5070 // 5071 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 5072 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5073 // CHECK10-NEXT: entry: 5074 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5075 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5076 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5077 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5078 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 5079 // CHECK10-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 5080 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5081 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5082 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5083 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5084 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 5085 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5086 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5087 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5088 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5089 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 5090 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 5091 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 5092 // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 5093 // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 5094 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 5095 // CHECK10-NEXT: ret void 5096 // 5097 // 5098 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5 5099 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 5100 // CHECK10-NEXT: entry: 5101 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5102 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5103 // CHECK10-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 5104 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 5105 // CHECK10-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5106 // CHECK10-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 5107 // CHECK10-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 5108 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5109 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5110 // CHECK10-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 5111 // CHECK10-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 5112 // CHECK10-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5113 // CHECK10-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 5114 // CHECK10-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 5115 // CHECK10-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 5116 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 5117 // CHECK10-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 5118 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 5119 // CHECK10-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 5120 // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 5121 // CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 5122 // CHECK10-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 5123 // CHECK10-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5124 // CHECK10-NEXT: store double [[ADD]], double* [[A]], align 8 5125 // CHECK10-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5126 // CHECK10-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 5127 // CHECK10-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 5128 // CHECK10-NEXT: store double [[INC]], double* [[A4]], align 8 5129 // CHECK10-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 5130 // CHECK10-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 5131 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 5132 // CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 5133 // CHECK10-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 5134 // CHECK10-NEXT: ret void 5135 // 5136 // 5137 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 5138 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5139 // CHECK10-NEXT: entry: 5140 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5141 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5142 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5143 // CHECK10-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 5144 // CHECK10-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 5145 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5146 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5147 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5148 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5149 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5150 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5151 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5152 // CHECK10-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 5153 // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 5154 // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 5155 // CHECK10-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 5156 // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 5157 // CHECK10-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 5158 // CHECK10-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 5159 // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 5160 // CHECK10-NEXT: ret void 5161 // 5162 // 5163 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6 5164 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5165 // CHECK10-NEXT: entry: 5166 // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5167 // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5168 // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 5169 // CHECK10-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 5170 // CHECK10-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 5171 // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5172 // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5173 // CHECK10-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 5174 // CHECK10-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 5175 // CHECK10-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 5176 // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 5177 // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 5178 // CHECK10-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 5179 // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 5180 // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5181 // CHECK10-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 5182 // CHECK10-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 5183 // CHECK10-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 5184 // CHECK10-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 5185 // CHECK10-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5186 // CHECK10-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 5187 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 5188 // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5189 // CHECK10-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 5190 // CHECK10-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 5191 // CHECK10-NEXT: ret void 5192 // 5193 // 5194 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 5195 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 5196 // CHECK11-NEXT: entry: 5197 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5198 // CHECK11-NEXT: ret void 5199 // 5200 // 5201 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 5202 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 5203 // CHECK11-NEXT: entry: 5204 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5205 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5206 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5207 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5208 // CHECK11-NEXT: ret void 5209 // 5210 // 5211 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 5212 // CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 5213 // CHECK11-NEXT: entry: 5214 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5215 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5216 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5217 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5218 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5219 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5220 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 5221 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5222 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5223 // CHECK11-NEXT: ret void 5224 // 5225 // 5226 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 5227 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { 5228 // CHECK11-NEXT: entry: 5229 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5230 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5231 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5232 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5233 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5234 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5235 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5236 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5237 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 5238 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 5239 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 5240 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 5241 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5242 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5243 // CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 5244 // CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 5245 // CHECK11-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 5246 // CHECK11: .cancel.exit: 5247 // CHECK11-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 5248 // CHECK11-NEXT: br label [[DOTCANCEL_CONTINUE]] 5249 // CHECK11: .cancel.continue: 5250 // CHECK11-NEXT: ret void 5251 // 5252 // 5253 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 5254 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 5255 // CHECK11-NEXT: entry: 5256 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5257 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5258 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5259 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5260 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5261 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5262 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5263 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5264 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5265 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5266 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5267 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5268 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 5269 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5270 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 5271 // CHECK11-NEXT: ret void 5272 // 5273 // 5274 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 5275 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { 5276 // CHECK11-NEXT: entry: 5277 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5278 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5279 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5280 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5281 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5282 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5283 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5284 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5285 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5286 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5287 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5288 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5289 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 5290 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 5291 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5292 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5293 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 5294 // CHECK11-NEXT: ret void 5295 // 5296 // 5297 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 5298 // CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 5299 // CHECK11-NEXT: entry: 5300 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5301 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5302 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5303 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5304 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5305 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5306 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5307 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5308 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5309 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5310 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5311 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5312 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5313 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5314 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5315 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5316 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5317 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5318 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5319 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5320 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5321 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5322 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5323 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5324 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5325 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5326 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5327 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5328 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 5329 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 5330 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 5331 // CHECK11-NEXT: ret void 5332 // 5333 // 5334 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 5335 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 5336 // CHECK11-NEXT: entry: 5337 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5338 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5339 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5340 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5341 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5342 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5343 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5344 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5345 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5346 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5347 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5348 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5349 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5350 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5351 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5352 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5353 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5354 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5355 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5356 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5357 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5358 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5359 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5360 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5361 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5362 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5363 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5364 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5365 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5366 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5367 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5368 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 5369 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5370 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 5371 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 5372 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 5373 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 5374 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 5375 // CHECK11-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 5376 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 5377 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 5378 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 5379 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 5380 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 5381 // CHECK11-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 5382 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 5383 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 5384 // CHECK11-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 5385 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 5386 // CHECK11-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 5387 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 5388 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 5389 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 5390 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 5391 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 5392 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 5393 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 5394 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 5395 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 5396 // CHECK11-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 5397 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 5398 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 5399 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 5400 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 5401 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 5402 // CHECK11-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 5403 // CHECK11-NEXT: ret void 5404 // 5405 // 5406 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 5407 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5408 // CHECK11-NEXT: entry: 5409 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5410 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5411 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5412 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5413 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5414 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5415 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5416 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5417 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5418 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5419 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5420 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5421 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5422 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5423 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5424 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5425 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5426 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5427 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5428 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 5429 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5430 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 5431 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 5432 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 5433 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 5434 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 5435 // CHECK11-NEXT: ret void 5436 // 5437 // 5438 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 5439 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5440 // CHECK11-NEXT: entry: 5441 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5442 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5443 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5444 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5445 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5446 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5447 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5448 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5449 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5450 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5451 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5452 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5453 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5454 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5455 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5456 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5457 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5458 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5459 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5460 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 5461 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 5462 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5463 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 5464 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 5465 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 5466 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 5467 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 5468 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 5469 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5470 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5471 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 5472 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 5473 // CHECK11-NEXT: ret void 5474 // 5475 // 5476 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 5477 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5478 // CHECK11-NEXT: entry: 5479 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5480 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5481 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5482 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5483 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5484 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5485 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5486 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5487 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5488 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5489 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5490 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5491 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5492 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5493 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5494 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5495 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 5496 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 5497 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 5498 // CHECK11-NEXT: ret void 5499 // 5500 // 5501 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 5502 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 5503 // CHECK11-NEXT: entry: 5504 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5505 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5506 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5507 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5508 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5509 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5510 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5511 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5512 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5513 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5514 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5515 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5516 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5517 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5518 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5519 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5520 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5521 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5522 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5523 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 5524 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5525 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5526 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 5527 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5528 // CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 5529 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 5530 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 5531 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 5532 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 5533 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 5534 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5535 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 5536 // CHECK11-NEXT: ret void 5537 // 5538 // 5539 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 5540 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5541 // CHECK11-NEXT: entry: 5542 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5543 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5544 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5545 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5546 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5547 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5548 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5549 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5550 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5551 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5552 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5553 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5554 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5555 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5556 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5557 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5558 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5559 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5560 // CHECK11-NEXT: ret void 5561 // 5562 // 5563 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 5564 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5565 // CHECK11-NEXT: entry: 5566 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5567 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5568 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5569 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5570 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5571 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5572 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5573 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5574 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5575 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5576 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5577 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5578 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5579 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5580 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5581 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5582 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 5583 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5584 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5585 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 5586 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5587 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5588 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 5589 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 5590 // CHECK11-NEXT: ret void 5591 // 5592 // 5593 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 5594 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 5595 // CHECK12-NEXT: entry: 5596 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 5597 // CHECK12-NEXT: ret void 5598 // 5599 // 5600 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 5601 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 5602 // CHECK12-NEXT: entry: 5603 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5604 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5605 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5606 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5607 // CHECK12-NEXT: ret void 5608 // 5609 // 5610 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 5611 // CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 5612 // CHECK12-NEXT: entry: 5613 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5614 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5615 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5616 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5617 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5618 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5619 // CHECK12-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 5620 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5621 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 5622 // CHECK12-NEXT: ret void 5623 // 5624 // 5625 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 5626 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { 5627 // CHECK12-NEXT: entry: 5628 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5629 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5630 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5631 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5632 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5633 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5634 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5635 // CHECK12-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 5636 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 5637 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 5638 // CHECK12-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 5639 // CHECK12-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 5640 // CHECK12-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 5641 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 5642 // CHECK12-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 5643 // CHECK12-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 5644 // CHECK12-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 5645 // CHECK12: .cancel.exit: 5646 // CHECK12-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 5647 // CHECK12-NEXT: br label [[DOTCANCEL_CONTINUE]] 5648 // CHECK12: .cancel.continue: 5649 // CHECK12-NEXT: ret void 5650 // 5651 // 5652 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 5653 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 5654 // CHECK12-NEXT: entry: 5655 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5656 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5657 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5658 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5659 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5660 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5661 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5662 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5663 // CHECK12-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 5664 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 5665 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5666 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5667 // CHECK12-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 5668 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5669 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 5670 // CHECK12-NEXT: ret void 5671 // 5672 // 5673 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 5674 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { 5675 // CHECK12-NEXT: entry: 5676 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5677 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5678 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5679 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5680 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5681 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5682 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5683 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5684 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5685 // CHECK12-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 5686 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 5687 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5688 // CHECK12-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 5689 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 5690 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5691 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5692 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 5693 // CHECK12-NEXT: ret void 5694 // 5695 // 5696 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 5697 // CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 5698 // CHECK12-NEXT: entry: 5699 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5700 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5701 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5702 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5703 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5704 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5705 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5706 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5707 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5708 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5709 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5710 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5711 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5712 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5713 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5714 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5715 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5716 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5717 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5718 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5719 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5720 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5721 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5722 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5723 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5724 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5725 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5726 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5727 // CHECK12-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 5728 // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 5729 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 5730 // CHECK12-NEXT: ret void 5731 // 5732 // 5733 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 5734 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 5735 // CHECK12-NEXT: entry: 5736 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5737 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5738 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5739 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 5740 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5741 // CHECK12-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 5742 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 5743 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5744 // CHECK12-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 5745 // CHECK12-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 5746 // CHECK12-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 5747 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5748 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5749 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5750 // CHECK12-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 5751 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5752 // CHECK12-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 5753 // CHECK12-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 5754 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5755 // CHECK12-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 5756 // CHECK12-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 5757 // CHECK12-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 5758 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 5759 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5760 // CHECK12-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 5761 // CHECK12-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 5762 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5763 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 5764 // CHECK12-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 5765 // CHECK12-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 5766 // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 5767 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 5768 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5769 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 5770 // CHECK12-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 5771 // CHECK12-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 5772 // CHECK12-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 5773 // CHECK12-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 5774 // CHECK12-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 5775 // CHECK12-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 5776 // CHECK12-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 5777 // CHECK12-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 5778 // CHECK12-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 5779 // CHECK12-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 5780 // CHECK12-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 5781 // CHECK12-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 5782 // CHECK12-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 5783 // CHECK12-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 5784 // CHECK12-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 5785 // CHECK12-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 5786 // CHECK12-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 5787 // CHECK12-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 5788 // CHECK12-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 5789 // CHECK12-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 5790 // CHECK12-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 5791 // CHECK12-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 5792 // CHECK12-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 5793 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 5794 // CHECK12-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 5795 // CHECK12-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 5796 // CHECK12-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 5797 // CHECK12-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 5798 // CHECK12-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 5799 // CHECK12-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 5800 // CHECK12-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 5801 // CHECK12-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 5802 // CHECK12-NEXT: ret void 5803 // 5804 // 5805 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 5806 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5807 // CHECK12-NEXT: entry: 5808 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5809 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5810 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5811 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5812 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5813 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5814 // CHECK12-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 5815 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5816 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5817 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5818 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5819 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5820 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5821 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5822 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5823 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5824 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5825 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5826 // CHECK12-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5827 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 5828 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5829 // CHECK12-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 5830 // CHECK12-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 5831 // CHECK12-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 5832 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 5833 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 5834 // CHECK12-NEXT: ret void 5835 // 5836 // 5837 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4 5838 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5839 // CHECK12-NEXT: entry: 5840 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5841 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5842 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5843 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5844 // CHECK12-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 5845 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5846 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5847 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5848 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5849 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5850 // CHECK12-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 5851 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5852 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5853 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 5854 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5855 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5856 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5857 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5858 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5859 // CHECK12-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 5860 // CHECK12-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 5861 // CHECK12-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 5862 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 5863 // CHECK12-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 5864 // CHECK12-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 5865 // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 5866 // CHECK12-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 5867 // CHECK12-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 5868 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5869 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5870 // CHECK12-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 5871 // CHECK12-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 5872 // CHECK12-NEXT: ret void 5873 // 5874 // 5875 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 5876 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 5877 // CHECK12-NEXT: entry: 5878 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5879 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5880 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5881 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5882 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5883 // CHECK12-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 5884 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5885 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5886 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5887 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5888 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5889 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5890 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5891 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5892 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5893 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5894 // CHECK12-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 5895 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 5896 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 5897 // CHECK12-NEXT: ret void 5898 // 5899 // 5900 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5 5901 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 5902 // CHECK12-NEXT: entry: 5903 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5904 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5905 // CHECK12-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 5906 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 5907 // CHECK12-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 5908 // CHECK12-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 5909 // CHECK12-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 5910 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5911 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5912 // CHECK12-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 5913 // CHECK12-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 5914 // CHECK12-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 5915 // CHECK12-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 5916 // CHECK12-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 5917 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 5918 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 5919 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 5920 // CHECK12-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 5921 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 5922 // CHECK12-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 5923 // CHECK12-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 5924 // CHECK12-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 5925 // CHECK12-NEXT: store double [[ADD]], double* [[A]], align 4 5926 // CHECK12-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 5927 // CHECK12-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 5928 // CHECK12-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 5929 // CHECK12-NEXT: store double [[INC]], double* [[A3]], align 4 5930 // CHECK12-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 5931 // CHECK12-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 5932 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 5933 // CHECK12-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 5934 // CHECK12-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 5935 // CHECK12-NEXT: ret void 5936 // 5937 // 5938 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 5939 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 5940 // CHECK12-NEXT: entry: 5941 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5942 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5943 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5944 // CHECK12-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 5945 // CHECK12-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 5946 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5947 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5948 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5949 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5950 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5951 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5952 // CHECK12-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 5953 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 5954 // CHECK12-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 5955 // CHECK12-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 5956 // CHECK12-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 5957 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 5958 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 5959 // CHECK12-NEXT: ret void 5960 // 5961 // 5962 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6 5963 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 5964 // CHECK12-NEXT: entry: 5965 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 5966 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 5967 // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 5968 // CHECK12-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 5969 // CHECK12-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 5970 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 5971 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 5972 // CHECK12-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 5973 // CHECK12-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 5974 // CHECK12-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 5975 // CHECK12-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 5976 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 5977 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 5978 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 5979 // CHECK12-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 5980 // CHECK12-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 5981 // CHECK12-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 5982 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 5983 // CHECK12-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 5984 // CHECK12-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 5985 // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 5986 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 5987 // CHECK12-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 5988 // CHECK12-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 5989 // CHECK12-NEXT: ret void 5990 // 5991 // 5992 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi 5993 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 5994 // CHECK17-NEXT: entry: 5995 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5996 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 5997 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 5998 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x float], align 4 5999 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6000 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6001 // CHECK17-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 6002 // CHECK17-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6003 // CHECK17-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 6004 // CHECK17-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 6005 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6006 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6007 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 6008 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 6009 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 6010 // CHECK17-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 6011 // CHECK17-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 6012 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 6013 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 6014 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 6015 // CHECK17-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 6016 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 6017 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 6018 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 6019 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 6020 // CHECK17-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 6021 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6022 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6023 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 6024 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6025 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 6026 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6027 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 6028 // CHECK17-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 6029 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 6030 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6031 // CHECK17-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 6032 // CHECK17-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 6033 // CHECK17-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 6034 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 6035 // CHECK17-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 6036 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 6037 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 6038 // CHECK17-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 6039 // CHECK17-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 6040 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6041 // CHECK17-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 6042 // CHECK17-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 6043 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 6044 // CHECK17-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 6045 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6046 // CHECK17-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 6047 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6048 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6049 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 6050 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 6051 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6052 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 6053 // CHECK17-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 6054 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6055 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 6056 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6057 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6058 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6059 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 6060 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6061 // CHECK17: omp_offload.failed: 6062 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 6063 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6064 // CHECK17: omp_offload.cont: 6065 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 6066 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 6067 // CHECK17-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 6068 // CHECK17-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 6069 // CHECK17-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 6070 // CHECK17-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 6071 // CHECK17-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 6072 // CHECK17-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 6073 // CHECK17-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 6074 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 6075 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6076 // CHECK17: omp_if.then: 6077 // CHECK17-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 6078 // CHECK17-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 6079 // CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 6080 // CHECK17-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 6081 // CHECK17-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 6082 // CHECK17-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 6083 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 6084 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 6085 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 6086 // CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* 6087 // CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 6088 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 6089 // CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 6090 // CHECK17-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 6091 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 6092 // CHECK17-NEXT: store i8* null, i8** [[TMP38]], align 8 6093 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 6094 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 6095 // CHECK17-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6096 // CHECK17-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 6097 // CHECK17-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 6098 // CHECK17: omp_offload.failed10: 6099 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 6100 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT11]] 6101 // CHECK17: omp_offload.cont11: 6102 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6103 // CHECK17: omp_if.else: 6104 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 6105 // CHECK17-NEXT: br label [[OMP_IF_END]] 6106 // CHECK17: omp_if.end: 6107 // CHECK17-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 6108 // CHECK17-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 6109 // CHECK17-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 6110 // CHECK17-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 6111 // CHECK17-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 6112 // CHECK17-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 6113 // CHECK17-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] 6114 // CHECK17: omp_if.then15: 6115 // CHECK17-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 6116 // CHECK17-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] 6117 // CHECK17-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 6118 // CHECK17-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 6119 // CHECK17-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64* 6120 // CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP50]], align 8 6121 // CHECK17-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 6122 // CHECK17-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* 6123 // CHECK17-NEXT: store i64 [[TMP44]], i64* [[TMP52]], align 8 6124 // CHECK17-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6125 // CHECK17-NEXT: store i64 4, i64* [[TMP53]], align 8 6126 // CHECK17-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 6127 // CHECK17-NEXT: store i8* null, i8** [[TMP54]], align 8 6128 // CHECK17-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 6129 // CHECK17-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 6130 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 6131 // CHECK17-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 6132 // CHECK17-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 6133 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 6134 // CHECK17-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 6135 // CHECK17-NEXT: store i64 40, i64* [[TMP59]], align 8 6136 // CHECK17-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 6137 // CHECK17-NEXT: store i8* null, i8** [[TMP60]], align 8 6138 // CHECK17-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 6139 // CHECK17-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 6140 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP62]], align 8 6141 // CHECK17-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 6142 // CHECK17-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 6143 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP64]], align 8 6144 // CHECK17-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 6145 // CHECK17-NEXT: store i64 8, i64* [[TMP65]], align 8 6146 // CHECK17-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 6147 // CHECK17-NEXT: store i8* null, i8** [[TMP66]], align 8 6148 // CHECK17-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 6149 // CHECK17-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 6150 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 6151 // CHECK17-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 6152 // CHECK17-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** 6153 // CHECK17-NEXT: store float* [[VLA]], float** [[TMP70]], align 8 6154 // CHECK17-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 6155 // CHECK17-NEXT: store i64 [[TMP46]], i64* [[TMP71]], align 8 6156 // CHECK17-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 6157 // CHECK17-NEXT: store i8* null, i8** [[TMP72]], align 8 6158 // CHECK17-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 6159 // CHECK17-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 6160 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 6161 // CHECK17-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 6162 // CHECK17-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** 6163 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8 6164 // CHECK17-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6165 // CHECK17-NEXT: store i64 400, i64* [[TMP77]], align 8 6166 // CHECK17-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 6167 // CHECK17-NEXT: store i8* null, i8** [[TMP78]], align 8 6168 // CHECK17-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 6169 // CHECK17-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* 6170 // CHECK17-NEXT: store i64 5, i64* [[TMP80]], align 8 6171 // CHECK17-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 6172 // CHECK17-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 6173 // CHECK17-NEXT: store i64 5, i64* [[TMP82]], align 8 6174 // CHECK17-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 6175 // CHECK17-NEXT: store i64 8, i64* [[TMP83]], align 8 6176 // CHECK17-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 6177 // CHECK17-NEXT: store i8* null, i8** [[TMP84]], align 8 6178 // CHECK17-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 6179 // CHECK17-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* 6180 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP86]], align 8 6181 // CHECK17-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 6182 // CHECK17-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* 6183 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP88]], align 8 6184 // CHECK17-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 6185 // CHECK17-NEXT: store i64 8, i64* [[TMP89]], align 8 6186 // CHECK17-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 6187 // CHECK17-NEXT: store i8* null, i8** [[TMP90]], align 8 6188 // CHECK17-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 6189 // CHECK17-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** 6190 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP92]], align 8 6191 // CHECK17-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 6192 // CHECK17-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** 6193 // CHECK17-NEXT: store double* [[VLA1]], double** [[TMP94]], align 8 6194 // CHECK17-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 6195 // CHECK17-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 8 6196 // CHECK17-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 6197 // CHECK17-NEXT: store i8* null, i8** [[TMP96]], align 8 6198 // CHECK17-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 6199 // CHECK17-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** 6200 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8 6201 // CHECK17-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 6202 // CHECK17-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** 6203 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8 6204 // CHECK17-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 6205 // CHECK17-NEXT: store i64 16, i64* [[TMP101]], align 8 6206 // CHECK17-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 6207 // CHECK17-NEXT: store i8* null, i8** [[TMP102]], align 8 6208 // CHECK17-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 6209 // CHECK17-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 6210 // CHECK17-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6211 // CHECK17-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6212 // CHECK17-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 6213 // CHECK17-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 6214 // CHECK17: omp_offload.failed19: 6215 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 6216 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT20]] 6217 // CHECK17: omp_offload.cont20: 6218 // CHECK17-NEXT: br label [[OMP_IF_END22:%.*]] 6219 // CHECK17: omp_if.else21: 6220 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 6221 // CHECK17-NEXT: br label [[OMP_IF_END22]] 6222 // CHECK17: omp_if.end22: 6223 // CHECK17-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 6224 // CHECK17-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6225 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) 6226 // CHECK17-NEXT: ret i32 [[TMP108]] 6227 // 6228 // 6229 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 6230 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] { 6231 // CHECK17-NEXT: entry: 6232 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 6233 // CHECK17-NEXT: ret void 6234 // 6235 // 6236 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined. 6237 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 6238 // CHECK17-NEXT: entry: 6239 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6240 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6241 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6242 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6243 // CHECK17-NEXT: ret void 6244 // 6245 // 6246 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry. 6247 // CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 6248 // CHECK17-NEXT: entry: 6249 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 6250 // CHECK17-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 6251 // CHECK17-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 6252 // CHECK17-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 6253 // CHECK17-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 6254 // CHECK17-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 6255 // CHECK17-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 6256 // CHECK17-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 6257 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 6258 // CHECK17-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 6259 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 6260 // CHECK17-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 6261 // CHECK17-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 6262 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 6263 // CHECK17-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 6264 // CHECK17-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 6265 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 6266 // CHECK17-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 6267 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 6268 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 6269 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 6270 // CHECK17-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 6271 // CHECK17-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 6272 // CHECK17-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 6273 // CHECK17-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 6274 // CHECK17-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 6275 // CHECK17-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 6276 // CHECK17-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 6277 // CHECK17-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 6278 // CHECK17-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 6279 // CHECK17-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 6280 // CHECK17-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 6281 // CHECK17: omp_offload.failed.i: 6282 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 6283 // CHECK17-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 6284 // CHECK17: .omp_outlined..1.exit: 6285 // CHECK17-NEXT: ret i32 0 6286 // 6287 // 6288 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 6289 // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { 6290 // CHECK17-NEXT: entry: 6291 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6292 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6293 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6294 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6295 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6296 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6297 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 6298 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6299 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6300 // CHECK17-NEXT: ret void 6301 // 6302 // 6303 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2 6304 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { 6305 // CHECK17-NEXT: entry: 6306 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6307 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6308 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6309 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6310 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6311 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6312 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6313 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6314 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6315 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6316 // CHECK17-NEXT: ret void 6317 // 6318 // 6319 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 6320 // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { 6321 // CHECK17-NEXT: entry: 6322 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6323 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6324 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6325 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6326 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6327 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6328 // CHECK17-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 6329 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6330 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 6331 // CHECK17-NEXT: ret void 6332 // 6333 // 6334 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3 6335 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { 6336 // CHECK17-NEXT: entry: 6337 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6338 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6339 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6340 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6341 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6342 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6343 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6344 // CHECK17-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 6345 // CHECK17-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 6346 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 6347 // CHECK17-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 6348 // CHECK17-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 6349 // CHECK17-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6350 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 6351 // CHECK17-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 6352 // CHECK17-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 6353 // CHECK17-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 6354 // CHECK17: .cancel.exit: 6355 // CHECK17-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 6356 // CHECK17-NEXT: br label [[DOTCANCEL_CONTINUE]] 6357 // CHECK17: .cancel.continue: 6358 // CHECK17-NEXT: ret void 6359 // 6360 // 6361 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 6362 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 6363 // CHECK17-NEXT: entry: 6364 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6365 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6366 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6367 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6368 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6369 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6370 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6371 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6372 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6373 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6374 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 6375 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6376 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6377 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6378 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 6379 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6380 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 6381 // CHECK17-NEXT: ret void 6382 // 6383 // 6384 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4 6385 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { 6386 // CHECK17-NEXT: entry: 6387 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6388 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6389 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6390 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6391 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6392 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6393 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6394 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6395 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6396 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6397 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 6398 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6399 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6400 // CHECK17-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 6401 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 6402 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 6403 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 6404 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 6405 // CHECK17-NEXT: ret void 6406 // 6407 // 6408 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 6409 // CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 6410 // CHECK17-NEXT: entry: 6411 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6412 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 6413 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6414 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 6415 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 6416 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6417 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 6418 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 6419 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 6420 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6421 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6422 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 6423 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6424 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 6425 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 6426 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6427 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 6428 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 6429 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 6430 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6431 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 6432 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6433 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 6434 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 6435 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6436 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 6437 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 6438 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 6439 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 6440 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6441 // CHECK17-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 6442 // CHECK17-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 6443 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 6444 // CHECK17-NEXT: ret void 6445 // 6446 // 6447 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7 6448 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 6449 // CHECK17-NEXT: entry: 6450 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6451 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6452 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6453 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 6454 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6455 // CHECK17-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 6456 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 6457 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6458 // CHECK17-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 6459 // CHECK17-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 6460 // CHECK17-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 6461 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6462 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6463 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6464 // CHECK17-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 6465 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6466 // CHECK17-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 6467 // CHECK17-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 6468 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6469 // CHECK17-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 6470 // CHECK17-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 6471 // CHECK17-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 6472 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6473 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 6474 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6475 // CHECK17-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 6476 // CHECK17-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 6477 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6478 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 6479 // CHECK17-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 6480 // CHECK17-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 6481 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 6482 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 6483 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6484 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 6485 // CHECK17-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 6486 // CHECK17-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 6487 // CHECK17-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 6488 // CHECK17-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 6489 // CHECK17-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 6490 // CHECK17-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 6491 // CHECK17-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 6492 // CHECK17-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 6493 // CHECK17-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 6494 // CHECK17-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 6495 // CHECK17-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 6496 // CHECK17-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 6497 // CHECK17-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 6498 // CHECK17-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 6499 // CHECK17-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 6500 // CHECK17-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 6501 // CHECK17-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 6502 // CHECK17-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 6503 // CHECK17-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 6504 // CHECK17-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 6505 // CHECK17-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 6506 // CHECK17-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 6507 // CHECK17-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 6508 // CHECK17-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 6509 // CHECK17-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 6510 // CHECK17-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 6511 // CHECK17-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 6512 // CHECK17-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 6513 // CHECK17-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 6514 // CHECK17-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 6515 // CHECK17-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 6516 // CHECK17-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 6517 // CHECK17-NEXT: ret void 6518 // 6519 // 6520 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari 6521 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 6522 // CHECK17-NEXT: entry: 6523 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6524 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 6525 // CHECK17-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 6526 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6527 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6528 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6529 // CHECK17-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 6530 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 6531 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 6532 // CHECK17-NEXT: store i32 [[ADD]], i32* [[A]], align 4 6533 // CHECK17-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 6534 // CHECK17-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 6535 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 6536 // CHECK17-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 6537 // CHECK17-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 6538 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6539 // CHECK17-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 6540 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 6541 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 6542 // CHECK17-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 6543 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6544 // CHECK17-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 6545 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 6546 // CHECK17-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 6547 // CHECK17-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 6548 // CHECK17-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 6549 // CHECK17-NEXT: ret i32 [[TMP8]] 6550 // 6551 // 6552 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 6553 // CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 6554 // CHECK17-NEXT: entry: 6555 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6556 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6557 // CHECK17-NEXT: [[B:%.*]] = alloca i32, align 4 6558 // CHECK17-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6559 // CHECK17-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6560 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 6561 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 6562 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 6563 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 6564 // CHECK17-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 6565 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6566 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6567 // CHECK17-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6568 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6569 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 6570 // CHECK17-NEXT: store i32 [[ADD]], i32* [[B]], align 4 6571 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 6572 // CHECK17-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 6573 // CHECK17-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6574 // CHECK17-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 6575 // CHECK17-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 6576 // CHECK17-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 6577 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 6578 // CHECK17-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 6579 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 6580 // CHECK17-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 6581 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 6582 // CHECK17-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 6583 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 6584 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6585 // CHECK17: omp_if.then: 6586 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 6587 // CHECK17-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 6588 // CHECK17-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 6589 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6590 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 6591 // CHECK17-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 6592 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6593 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 6594 // CHECK17-NEXT: store double* [[A]], double** [[TMP13]], align 8 6595 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6596 // CHECK17-NEXT: store i64 8, i64* [[TMP14]], align 8 6597 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6598 // CHECK17-NEXT: store i8* null, i8** [[TMP15]], align 8 6599 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6600 // CHECK17-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 6601 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 6602 // CHECK17-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6603 // CHECK17-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 6604 // CHECK17-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 6605 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 6606 // CHECK17-NEXT: store i64 4, i64* [[TMP20]], align 8 6607 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 6608 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 6609 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6610 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 6611 // CHECK17-NEXT: store i64 2, i64* [[TMP23]], align 8 6612 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6613 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 6614 // CHECK17-NEXT: store i64 2, i64* [[TMP25]], align 8 6615 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 6616 // CHECK17-NEXT: store i64 8, i64* [[TMP26]], align 8 6617 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 6618 // CHECK17-NEXT: store i8* null, i8** [[TMP27]], align 8 6619 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6620 // CHECK17-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 6621 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 6622 // CHECK17-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6623 // CHECK17-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 6624 // CHECK17-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 6625 // CHECK17-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 6626 // CHECK17-NEXT: store i64 8, i64* [[TMP32]], align 8 6627 // CHECK17-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 6628 // CHECK17-NEXT: store i8* null, i8** [[TMP33]], align 8 6629 // CHECK17-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 6630 // CHECK17-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 6631 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 6632 // CHECK17-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 6633 // CHECK17-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 6634 // CHECK17-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 6635 // CHECK17-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 6636 // CHECK17-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 6637 // CHECK17-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 6638 // CHECK17-NEXT: store i8* null, i8** [[TMP39]], align 8 6639 // CHECK17-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6640 // CHECK17-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6641 // CHECK17-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 6642 // CHECK17-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6643 // CHECK17-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 6644 // CHECK17-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6645 // CHECK17: omp_offload.failed: 6646 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 6647 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6648 // CHECK17: omp_offload.cont: 6649 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6650 // CHECK17: omp_if.else: 6651 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 6652 // CHECK17-NEXT: br label [[OMP_IF_END]] 6653 // CHECK17: omp_if.end: 6654 // CHECK17-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 6655 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 6656 // CHECK17-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 6657 // CHECK17-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 6658 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 6659 // CHECK17-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 6660 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 6661 // CHECK17-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6662 // CHECK17-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 6663 // CHECK17-NEXT: ret i32 [[ADD4]] 6664 // 6665 // 6666 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici 6667 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 6668 // CHECK17-NEXT: entry: 6669 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6670 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 6671 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 6672 // CHECK17-NEXT: [[AAA:%.*]] = alloca i8, align 1 6673 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6674 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6675 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6676 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 6677 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 6678 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 6679 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 6680 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6681 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6682 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 6683 // CHECK17-NEXT: store i8 0, i8* [[AAA]], align 1 6684 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6685 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6686 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 6687 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6688 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6689 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6690 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 6691 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6692 // CHECK17-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 6693 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 6694 // CHECK17-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 6695 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 6696 // CHECK17-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 6697 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 6698 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6699 // CHECK17: omp_if.then: 6700 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6701 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 6702 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 6703 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6704 // CHECK17-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 6705 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 6706 // CHECK17-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6707 // CHECK17-NEXT: store i8* null, i8** [[TMP11]], align 8 6708 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6709 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 6710 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 6711 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6712 // CHECK17-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 6713 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 6714 // CHECK17-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 6715 // CHECK17-NEXT: store i8* null, i8** [[TMP16]], align 8 6716 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6717 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 6718 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 6719 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6720 // CHECK17-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 6721 // CHECK17-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 6722 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 6723 // CHECK17-NEXT: store i8* null, i8** [[TMP21]], align 8 6724 // CHECK17-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 6725 // CHECK17-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 6726 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 6727 // CHECK17-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 6728 // CHECK17-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 6729 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 6730 // CHECK17-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 6731 // CHECK17-NEXT: store i8* null, i8** [[TMP26]], align 8 6732 // CHECK17-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6733 // CHECK17-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6734 // CHECK17-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6735 // CHECK17-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 6736 // CHECK17-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6737 // CHECK17: omp_offload.failed: 6738 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6739 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6740 // CHECK17: omp_offload.cont: 6741 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6742 // CHECK17: omp_if.else: 6743 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 6744 // CHECK17-NEXT: br label [[OMP_IF_END]] 6745 // CHECK17: omp_if.end: 6746 // CHECK17-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 6747 // CHECK17-NEXT: ret i32 [[TMP31]] 6748 // 6749 // 6750 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 6751 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 6752 // CHECK17-NEXT: entry: 6753 // CHECK17-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6754 // CHECK17-NEXT: [[A:%.*]] = alloca i32, align 4 6755 // CHECK17-NEXT: [[AA:%.*]] = alloca i16, align 2 6756 // CHECK17-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 6757 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6758 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6759 // CHECK17-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 6760 // CHECK17-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 6761 // CHECK17-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 6762 // CHECK17-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6763 // CHECK17-NEXT: store i32 0, i32* [[A]], align 4 6764 // CHECK17-NEXT: store i16 0, i16* [[AA]], align 2 6765 // CHECK17-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 6766 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6767 // CHECK17-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 6768 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 6769 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 6770 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6771 // CHECK17-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 6772 // CHECK17-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6773 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 6774 // CHECK17-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 6775 // CHECK17-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 6776 // CHECK17: omp_if.then: 6777 // CHECK17-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6778 // CHECK17-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 6779 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 6780 // CHECK17-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6781 // CHECK17-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 6782 // CHECK17-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 6783 // CHECK17-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 6784 // CHECK17-NEXT: store i8* null, i8** [[TMP9]], align 8 6785 // CHECK17-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 6786 // CHECK17-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 6787 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 6788 // CHECK17-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 6789 // CHECK17-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 6790 // CHECK17-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 6791 // CHECK17-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 6792 // CHECK17-NEXT: store i8* null, i8** [[TMP14]], align 8 6793 // CHECK17-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 6794 // CHECK17-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 6795 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 6796 // CHECK17-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 6797 // CHECK17-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 6798 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 6799 // CHECK17-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 6800 // CHECK17-NEXT: store i8* null, i8** [[TMP19]], align 8 6801 // CHECK17-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 6802 // CHECK17-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 6803 // CHECK17-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 6804 // CHECK17-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 6805 // CHECK17-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 6806 // CHECK17: omp_offload.failed: 6807 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6808 // CHECK17-NEXT: br label [[OMP_OFFLOAD_CONT]] 6809 // CHECK17: omp_offload.cont: 6810 // CHECK17-NEXT: br label [[OMP_IF_END:%.*]] 6811 // CHECK17: omp_if.else: 6812 // CHECK17-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 6813 // CHECK17-NEXT: br label [[OMP_IF_END]] 6814 // CHECK17: omp_if.end: 6815 // CHECK17-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 6816 // CHECK17-NEXT: ret i32 [[TMP24]] 6817 // 6818 // 6819 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 6820 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 6821 // CHECK17-NEXT: entry: 6822 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6823 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6824 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6825 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6826 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6827 // CHECK17-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 6828 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6829 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6830 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6831 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6832 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6833 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6834 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6835 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6836 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6837 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6838 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 6839 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 6840 // CHECK17-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 6841 // CHECK17-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 6842 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 6843 // CHECK17-NEXT: ret void 6844 // 6845 // 6846 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9 6847 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 6848 // CHECK17-NEXT: entry: 6849 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6850 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6851 // CHECK17-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 6852 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 6853 // CHECK17-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 6854 // CHECK17-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 6855 // CHECK17-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 6856 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6857 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6858 // CHECK17-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 6859 // CHECK17-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 6860 // CHECK17-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 6861 // CHECK17-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 6862 // CHECK17-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 6863 // CHECK17-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 6864 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 6865 // CHECK17-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 6866 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 6867 // CHECK17-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 6868 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 6869 // CHECK17-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 6870 // CHECK17-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 6871 // CHECK17-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 6872 // CHECK17-NEXT: store double [[ADD]], double* [[A]], align 8 6873 // CHECK17-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 6874 // CHECK17-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 6875 // CHECK17-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 6876 // CHECK17-NEXT: store double [[INC]], double* [[A4]], align 8 6877 // CHECK17-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 6878 // CHECK17-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 6879 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 6880 // CHECK17-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 6881 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 6882 // CHECK17-NEXT: ret void 6883 // 6884 // 6885 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 6886 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6887 // CHECK17-NEXT: entry: 6888 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6889 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6890 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6891 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6892 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6893 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6894 // CHECK17-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 6895 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6896 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6897 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6898 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6899 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6900 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6901 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6902 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6903 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6904 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6905 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 6906 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6907 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6908 // CHECK17-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6909 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 6910 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6911 // CHECK17-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 6912 // CHECK17-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 6913 // CHECK17-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 6914 // CHECK17-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 6915 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 6916 // CHECK17-NEXT: ret void 6917 // 6918 // 6919 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11 6920 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6921 // CHECK17-NEXT: entry: 6922 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6923 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6924 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6925 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6926 // CHECK17-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 6927 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6928 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6929 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6930 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6931 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6932 // CHECK17-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 6933 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6934 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6935 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6936 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 6937 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6938 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6939 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 6940 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 6941 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 6942 // CHECK17-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 6943 // CHECK17-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 6944 // CHECK17-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 6945 // CHECK17-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 6946 // CHECK17-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 6947 // CHECK17-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 6948 // CHECK17-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 6949 // CHECK17-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 6950 // CHECK17-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 6951 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 6952 // CHECK17-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 6953 // CHECK17-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 6954 // CHECK17-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 6955 // CHECK17-NEXT: ret void 6956 // 6957 // 6958 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 6959 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 6960 // CHECK17-NEXT: entry: 6961 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6962 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6963 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6964 // CHECK17-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 6965 // CHECK17-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 6966 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6967 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6968 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6969 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6970 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6971 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 6972 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 6973 // CHECK17-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 6974 // CHECK17-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 6975 // CHECK17-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 6976 // CHECK17-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 6977 // CHECK17-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 6978 // CHECK17-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 6979 // CHECK17-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 6980 // CHECK17-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 6981 // CHECK17-NEXT: ret void 6982 // 6983 // 6984 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14 6985 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 6986 // CHECK17-NEXT: entry: 6987 // CHECK17-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6988 // CHECK17-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6989 // CHECK17-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 6990 // CHECK17-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 6991 // CHECK17-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 6992 // CHECK17-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6993 // CHECK17-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6994 // CHECK17-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 6995 // CHECK17-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 6996 // CHECK17-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 6997 // CHECK17-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 6998 // CHECK17-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 6999 // CHECK17-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7000 // CHECK17-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7001 // CHECK17-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7002 // CHECK17-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7003 // CHECK17-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 7004 // CHECK17-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 7005 // CHECK17-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 7006 // CHECK17-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 7007 // CHECK17-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 7008 // CHECK17-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7009 // CHECK17-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7010 // CHECK17-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 7011 // CHECK17-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 7012 // CHECK17-NEXT: ret void 7013 // 7014 // 7015 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 7016 // CHECK17-SAME: () #[[ATTR7:[0-9]+]] { 7017 // CHECK17-NEXT: entry: 7018 // CHECK17-NEXT: call void @__tgt_register_requires(i64 1) 7019 // CHECK17-NEXT: ret void 7020 // 7021 // 7022 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi 7023 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 7024 // CHECK18-NEXT: entry: 7025 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7026 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 7027 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 7028 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x float], align 4 7029 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7030 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7031 // CHECK18-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 7032 // CHECK18-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7033 // CHECK18-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 7034 // CHECK18-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 7035 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7036 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7037 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 7038 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 7039 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 7040 // CHECK18-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 7041 // CHECK18-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 7042 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 7043 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 7044 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 7045 // CHECK18-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 7046 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 7047 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 7048 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 7049 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 7050 // CHECK18-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 7051 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7052 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 7053 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 7054 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7055 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7056 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 7057 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 7058 // CHECK18-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 7059 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 7060 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7061 // CHECK18-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 7062 // CHECK18-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 7063 // CHECK18-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 7064 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 7065 // CHECK18-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 7066 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 7067 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 7068 // CHECK18-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 7069 // CHECK18-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 7070 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7071 // CHECK18-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 7072 // CHECK18-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 7073 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 7074 // CHECK18-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 7075 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7076 // CHECK18-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 7077 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7078 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7079 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 7080 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 7081 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7082 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 7083 // CHECK18-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 7084 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 7085 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 7086 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7087 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7088 // CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7089 // CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 7090 // CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7091 // CHECK18: omp_offload.failed: 7092 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 7093 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 7094 // CHECK18: omp_offload.cont: 7095 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 7096 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 7097 // CHECK18-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 7098 // CHECK18-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 7099 // CHECK18-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 7100 // CHECK18-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 7101 // CHECK18-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 7102 // CHECK18-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 7103 // CHECK18-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 7104 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 7105 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7106 // CHECK18: omp_if.then: 7107 // CHECK18-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 7108 // CHECK18-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 7109 // CHECK18-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 7110 // CHECK18-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 7111 // CHECK18-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 7112 // CHECK18-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 7113 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 7114 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 7115 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 7116 // CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* 7117 // CHECK18-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 7118 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 7119 // CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 7120 // CHECK18-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 7121 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 7122 // CHECK18-NEXT: store i8* null, i8** [[TMP38]], align 8 7123 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 7124 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 7125 // CHECK18-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7126 // CHECK18-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 7127 // CHECK18-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 7128 // CHECK18: omp_offload.failed10: 7129 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 7130 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT11]] 7131 // CHECK18: omp_offload.cont11: 7132 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 7133 // CHECK18: omp_if.else: 7134 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 7135 // CHECK18-NEXT: br label [[OMP_IF_END]] 7136 // CHECK18: omp_if.end: 7137 // CHECK18-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 7138 // CHECK18-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 7139 // CHECK18-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 7140 // CHECK18-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 7141 // CHECK18-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 7142 // CHECK18-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 7143 // CHECK18-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] 7144 // CHECK18: omp_if.then15: 7145 // CHECK18-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 7146 // CHECK18-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] 7147 // CHECK18-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 7148 // CHECK18-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 7149 // CHECK18-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64* 7150 // CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP50]], align 8 7151 // CHECK18-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 7152 // CHECK18-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64* 7153 // CHECK18-NEXT: store i64 [[TMP44]], i64* [[TMP52]], align 8 7154 // CHECK18-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 7155 // CHECK18-NEXT: store i64 4, i64* [[TMP53]], align 8 7156 // CHECK18-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 7157 // CHECK18-NEXT: store i8* null, i8** [[TMP54]], align 8 7158 // CHECK18-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 7159 // CHECK18-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 7160 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 7161 // CHECK18-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 7162 // CHECK18-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 7163 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 7164 // CHECK18-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 7165 // CHECK18-NEXT: store i64 40, i64* [[TMP59]], align 8 7166 // CHECK18-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 7167 // CHECK18-NEXT: store i8* null, i8** [[TMP60]], align 8 7168 // CHECK18-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 7169 // CHECK18-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64* 7170 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP62]], align 8 7171 // CHECK18-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 7172 // CHECK18-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64* 7173 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP64]], align 8 7174 // CHECK18-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 7175 // CHECK18-NEXT: store i64 8, i64* [[TMP65]], align 8 7176 // CHECK18-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 7177 // CHECK18-NEXT: store i8* null, i8** [[TMP66]], align 8 7178 // CHECK18-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 7179 // CHECK18-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 7180 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 7181 // CHECK18-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 7182 // CHECK18-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** 7183 // CHECK18-NEXT: store float* [[VLA]], float** [[TMP70]], align 8 7184 // CHECK18-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 7185 // CHECK18-NEXT: store i64 [[TMP46]], i64* [[TMP71]], align 8 7186 // CHECK18-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 7187 // CHECK18-NEXT: store i8* null, i8** [[TMP72]], align 8 7188 // CHECK18-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 7189 // CHECK18-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 7190 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 7191 // CHECK18-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 7192 // CHECK18-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** 7193 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8 7194 // CHECK18-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 7195 // CHECK18-NEXT: store i64 400, i64* [[TMP77]], align 8 7196 // CHECK18-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 7197 // CHECK18-NEXT: store i8* null, i8** [[TMP78]], align 8 7198 // CHECK18-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 7199 // CHECK18-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64* 7200 // CHECK18-NEXT: store i64 5, i64* [[TMP80]], align 8 7201 // CHECK18-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 7202 // CHECK18-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 7203 // CHECK18-NEXT: store i64 5, i64* [[TMP82]], align 8 7204 // CHECK18-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 7205 // CHECK18-NEXT: store i64 8, i64* [[TMP83]], align 8 7206 // CHECK18-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 7207 // CHECK18-NEXT: store i8* null, i8** [[TMP84]], align 8 7208 // CHECK18-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 7209 // CHECK18-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64* 7210 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP86]], align 8 7211 // CHECK18-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 7212 // CHECK18-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64* 7213 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP88]], align 8 7214 // CHECK18-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 7215 // CHECK18-NEXT: store i64 8, i64* [[TMP89]], align 8 7216 // CHECK18-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 7217 // CHECK18-NEXT: store i8* null, i8** [[TMP90]], align 8 7218 // CHECK18-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 7219 // CHECK18-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** 7220 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP92]], align 8 7221 // CHECK18-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 7222 // CHECK18-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** 7223 // CHECK18-NEXT: store double* [[VLA1]], double** [[TMP94]], align 8 7224 // CHECK18-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 7225 // CHECK18-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 8 7226 // CHECK18-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 7227 // CHECK18-NEXT: store i8* null, i8** [[TMP96]], align 8 7228 // CHECK18-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 7229 // CHECK18-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** 7230 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8 7231 // CHECK18-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 7232 // CHECK18-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** 7233 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8 7234 // CHECK18-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 7235 // CHECK18-NEXT: store i64 16, i64* [[TMP101]], align 8 7236 // CHECK18-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 7237 // CHECK18-NEXT: store i8* null, i8** [[TMP102]], align 8 7238 // CHECK18-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 7239 // CHECK18-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 7240 // CHECK18-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 7241 // CHECK18-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7242 // CHECK18-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 7243 // CHECK18-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 7244 // CHECK18: omp_offload.failed19: 7245 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 7246 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT20]] 7247 // CHECK18: omp_offload.cont20: 7248 // CHECK18-NEXT: br label [[OMP_IF_END22:%.*]] 7249 // CHECK18: omp_if.else21: 7250 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 7251 // CHECK18-NEXT: br label [[OMP_IF_END22]] 7252 // CHECK18: omp_if.end22: 7253 // CHECK18-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 7254 // CHECK18-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7255 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) 7256 // CHECK18-NEXT: ret i32 [[TMP108]] 7257 // 7258 // 7259 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 7260 // CHECK18-SAME: () #[[ATTR2:[0-9]+]] { 7261 // CHECK18-NEXT: entry: 7262 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 7263 // CHECK18-NEXT: ret void 7264 // 7265 // 7266 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined. 7267 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 7268 // CHECK18-NEXT: entry: 7269 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7270 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7271 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7272 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7273 // CHECK18-NEXT: ret void 7274 // 7275 // 7276 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry. 7277 // CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 7278 // CHECK18-NEXT: entry: 7279 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 7280 // CHECK18-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 7281 // CHECK18-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 7282 // CHECK18-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 7283 // CHECK18-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 7284 // CHECK18-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 7285 // CHECK18-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 7286 // CHECK18-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 7287 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 7288 // CHECK18-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 7289 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 7290 // CHECK18-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 7291 // CHECK18-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 7292 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 7293 // CHECK18-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 7294 // CHECK18-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 7295 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 7296 // CHECK18-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 7297 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 7298 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 7299 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 7300 // CHECK18-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 7301 // CHECK18-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 7302 // CHECK18-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 7303 // CHECK18-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 7304 // CHECK18-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 7305 // CHECK18-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 7306 // CHECK18-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 7307 // CHECK18-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 7308 // CHECK18-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 7309 // CHECK18-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 7310 // CHECK18-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 7311 // CHECK18: omp_offload.failed.i: 7312 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 7313 // CHECK18-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 7314 // CHECK18: .omp_outlined..1.exit: 7315 // CHECK18-NEXT: ret i32 0 7316 // 7317 // 7318 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 7319 // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR3]] { 7320 // CHECK18-NEXT: entry: 7321 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7322 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7323 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7324 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7325 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7326 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7327 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 7328 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7329 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 7330 // CHECK18-NEXT: ret void 7331 // 7332 // 7333 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2 7334 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR3]] { 7335 // CHECK18-NEXT: entry: 7336 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7337 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7338 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7339 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7340 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7341 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7342 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7343 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7344 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7345 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7346 // CHECK18-NEXT: ret void 7347 // 7348 // 7349 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 7350 // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] { 7351 // CHECK18-NEXT: entry: 7352 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7353 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7354 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7355 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7356 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 7357 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7358 // CHECK18-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 7359 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7360 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 7361 // CHECK18-NEXT: ret void 7362 // 7363 // 7364 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3 7365 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { 7366 // CHECK18-NEXT: entry: 7367 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7368 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7369 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7370 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7371 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7372 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7373 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7374 // CHECK18-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 7375 // CHECK18-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 7376 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 7377 // CHECK18-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 7378 // CHECK18-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 7379 // CHECK18-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7380 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 7381 // CHECK18-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 7382 // CHECK18-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 7383 // CHECK18-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 7384 // CHECK18: .cancel.exit: 7385 // CHECK18-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 7386 // CHECK18-NEXT: br label [[DOTCANCEL_CONTINUE]] 7387 // CHECK18: .cancel.continue: 7388 // CHECK18-NEXT: ret void 7389 // 7390 // 7391 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 7392 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] { 7393 // CHECK18-NEXT: entry: 7394 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7395 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7396 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7397 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7398 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7399 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7400 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7401 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7402 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7403 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7404 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 7405 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7406 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 7407 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7408 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 7409 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7410 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 7411 // CHECK18-NEXT: ret void 7412 // 7413 // 7414 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4 7415 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR3]] { 7416 // CHECK18-NEXT: entry: 7417 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7418 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7419 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7420 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7421 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7422 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7423 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7424 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7425 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7426 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7427 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 7428 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7429 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7430 // CHECK18-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 7431 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 7432 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 7433 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 7434 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 7435 // CHECK18-NEXT: ret void 7436 // 7437 // 7438 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 7439 // CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 7440 // CHECK18-NEXT: entry: 7441 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7442 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7443 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7444 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7445 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7446 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7447 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7448 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7449 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7450 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7451 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7452 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7453 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7454 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7455 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7456 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7457 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7458 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7459 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7460 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7461 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7462 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7463 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7464 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7465 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7466 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7467 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7468 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7469 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7470 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7471 // CHECK18-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 7472 // CHECK18-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 7473 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 7474 // CHECK18-NEXT: ret void 7475 // 7476 // 7477 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7 7478 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 7479 // CHECK18-NEXT: entry: 7480 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7481 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7482 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7483 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 7484 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7485 // CHECK18-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 7486 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 7487 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7488 // CHECK18-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 7489 // CHECK18-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 7490 // CHECK18-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 7491 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7492 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7493 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7494 // CHECK18-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 7495 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7496 // CHECK18-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 7497 // CHECK18-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 7498 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7499 // CHECK18-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 7500 // CHECK18-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 7501 // CHECK18-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 7502 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7503 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 7504 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7505 // CHECK18-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 7506 // CHECK18-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 7507 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7508 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 7509 // CHECK18-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 7510 // CHECK18-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 7511 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 7512 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 7513 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7514 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 7515 // CHECK18-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 7516 // CHECK18-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 7517 // CHECK18-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 7518 // CHECK18-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 7519 // CHECK18-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 7520 // CHECK18-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 7521 // CHECK18-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 7522 // CHECK18-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 7523 // CHECK18-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 7524 // CHECK18-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 7525 // CHECK18-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 7526 // CHECK18-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 7527 // CHECK18-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 7528 // CHECK18-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 7529 // CHECK18-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 7530 // CHECK18-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 7531 // CHECK18-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 7532 // CHECK18-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 7533 // CHECK18-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 7534 // CHECK18-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 7535 // CHECK18-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 7536 // CHECK18-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 7537 // CHECK18-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 7538 // CHECK18-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 7539 // CHECK18-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 7540 // CHECK18-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 7541 // CHECK18-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 7542 // CHECK18-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 7543 // CHECK18-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 7544 // CHECK18-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 7545 // CHECK18-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 7546 // CHECK18-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 7547 // CHECK18-NEXT: ret void 7548 // 7549 // 7550 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari 7551 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 7552 // CHECK18-NEXT: entry: 7553 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7554 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 7555 // CHECK18-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 7556 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7557 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 7558 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7559 // CHECK18-NEXT: [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]]) 7560 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 7561 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 7562 // CHECK18-NEXT: store i32 [[ADD]], i32* [[A]], align 4 7563 // CHECK18-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 7564 // CHECK18-NEXT: [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]]) 7565 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 7566 // CHECK18-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 7567 // CHECK18-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 7568 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7569 // CHECK18-NEXT: [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]]) 7570 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 7571 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 7572 // CHECK18-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 7573 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7574 // CHECK18-NEXT: [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]]) 7575 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 7576 // CHECK18-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 7577 // CHECK18-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 7578 // CHECK18-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 7579 // CHECK18-NEXT: ret i32 [[TMP8]] 7580 // 7581 // 7582 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 7583 // CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 7584 // CHECK18-NEXT: entry: 7585 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7586 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7587 // CHECK18-NEXT: [[B:%.*]] = alloca i32, align 4 7588 // CHECK18-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7589 // CHECK18-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7590 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 7591 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 7592 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 7593 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 7594 // CHECK18-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 7595 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7596 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7597 // CHECK18-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7598 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7599 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 7600 // CHECK18-NEXT: store i32 [[ADD]], i32* [[B]], align 4 7601 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 7602 // CHECK18-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 7603 // CHECK18-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 7604 // CHECK18-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 7605 // CHECK18-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 7606 // CHECK18-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 7607 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 7608 // CHECK18-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 7609 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 7610 // CHECK18-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 7611 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 7612 // CHECK18-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 7613 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 7614 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7615 // CHECK18: omp_if.then: 7616 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 7617 // CHECK18-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 7618 // CHECK18-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 7619 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7620 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 7621 // CHECK18-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8 7622 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7623 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 7624 // CHECK18-NEXT: store double* [[A]], double** [[TMP13]], align 8 7625 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 7626 // CHECK18-NEXT: store i64 8, i64* [[TMP14]], align 8 7627 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 7628 // CHECK18-NEXT: store i8* null, i8** [[TMP15]], align 8 7629 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7630 // CHECK18-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 7631 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 7632 // CHECK18-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7633 // CHECK18-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 7634 // CHECK18-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 7635 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 7636 // CHECK18-NEXT: store i64 4, i64* [[TMP20]], align 8 7637 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 7638 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 7639 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7640 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64* 7641 // CHECK18-NEXT: store i64 2, i64* [[TMP23]], align 8 7642 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7643 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* 7644 // CHECK18-NEXT: store i64 2, i64* [[TMP25]], align 8 7645 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 7646 // CHECK18-NEXT: store i64 8, i64* [[TMP26]], align 8 7647 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 7648 // CHECK18-NEXT: store i8* null, i8** [[TMP27]], align 8 7649 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 7650 // CHECK18-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 7651 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 7652 // CHECK18-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 7653 // CHECK18-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64* 7654 // CHECK18-NEXT: store i64 [[TMP2]], i64* [[TMP31]], align 8 7655 // CHECK18-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 7656 // CHECK18-NEXT: store i64 8, i64* [[TMP32]], align 8 7657 // CHECK18-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 7658 // CHECK18-NEXT: store i8* null, i8** [[TMP33]], align 8 7659 // CHECK18-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 7660 // CHECK18-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 7661 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 8 7662 // CHECK18-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 7663 // CHECK18-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 7664 // CHECK18-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 8 7665 // CHECK18-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 7666 // CHECK18-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 8 7667 // CHECK18-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 7668 // CHECK18-NEXT: store i8* null, i8** [[TMP39]], align 8 7669 // CHECK18-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7670 // CHECK18-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7671 // CHECK18-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 7672 // CHECK18-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7673 // CHECK18-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 7674 // CHECK18-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7675 // CHECK18: omp_offload.failed: 7676 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 7677 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 7678 // CHECK18: omp_offload.cont: 7679 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 7680 // CHECK18: omp_if.else: 7681 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 7682 // CHECK18-NEXT: br label [[OMP_IF_END]] 7683 // CHECK18: omp_if.end: 7684 // CHECK18-NEXT: [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]] 7685 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]] 7686 // CHECK18-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7687 // CHECK18-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 7688 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP46]] to i32 7689 // CHECK18-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 7690 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]] 7691 // CHECK18-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7692 // CHECK18-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 7693 // CHECK18-NEXT: ret i32 [[ADD4]] 7694 // 7695 // 7696 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici 7697 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] { 7698 // CHECK18-NEXT: entry: 7699 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7700 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 7701 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 7702 // CHECK18-NEXT: [[AAA:%.*]] = alloca i8, align 1 7703 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7704 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7705 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7706 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 7707 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 7708 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 7709 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 7710 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7711 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 7712 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 7713 // CHECK18-NEXT: store i8 0, i8* [[AAA]], align 1 7714 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7715 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7716 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 7717 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7718 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 7719 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7720 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 7721 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7722 // CHECK18-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 7723 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 7724 // CHECK18-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 7725 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 7726 // CHECK18-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7727 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 7728 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7729 // CHECK18: omp_if.then: 7730 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7731 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 7732 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 7733 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7734 // CHECK18-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 7735 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 7736 // CHECK18-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 7737 // CHECK18-NEXT: store i8* null, i8** [[TMP11]], align 8 7738 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7739 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 7740 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 7741 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7742 // CHECK18-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 7743 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 7744 // CHECK18-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 7745 // CHECK18-NEXT: store i8* null, i8** [[TMP16]], align 8 7746 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7747 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 7748 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 7749 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7750 // CHECK18-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 7751 // CHECK18-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 7752 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 7753 // CHECK18-NEXT: store i8* null, i8** [[TMP21]], align 8 7754 // CHECK18-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 7755 // CHECK18-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 7756 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 7757 // CHECK18-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 7758 // CHECK18-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 7759 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 7760 // CHECK18-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 7761 // CHECK18-NEXT: store i8* null, i8** [[TMP26]], align 8 7762 // CHECK18-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7763 // CHECK18-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7764 // CHECK18-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7765 // CHECK18-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 7766 // CHECK18-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7767 // CHECK18: omp_offload.failed: 7768 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 7769 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 7770 // CHECK18: omp_offload.cont: 7771 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 7772 // CHECK18: omp_if.else: 7773 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 7774 // CHECK18-NEXT: br label [[OMP_IF_END]] 7775 // CHECK18: omp_if.end: 7776 // CHECK18-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 7777 // CHECK18-NEXT: ret i32 [[TMP31]] 7778 // 7779 // 7780 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 7781 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat { 7782 // CHECK18-NEXT: entry: 7783 // CHECK18-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7784 // CHECK18-NEXT: [[A:%.*]] = alloca i32, align 4 7785 // CHECK18-NEXT: [[AA:%.*]] = alloca i16, align 2 7786 // CHECK18-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 7787 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7788 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7789 // CHECK18-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 7790 // CHECK18-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 7791 // CHECK18-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 7792 // CHECK18-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7793 // CHECK18-NEXT: store i32 0, i32* [[A]], align 4 7794 // CHECK18-NEXT: store i16 0, i16* [[AA]], align 2 7795 // CHECK18-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 7796 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7797 // CHECK18-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 7798 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 7799 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 7800 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7801 // CHECK18-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 7802 // CHECK18-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7803 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 7804 // CHECK18-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 7805 // CHECK18-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 7806 // CHECK18: omp_if.then: 7807 // CHECK18-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7808 // CHECK18-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 7809 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 7810 // CHECK18-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7811 // CHECK18-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 7812 // CHECK18-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 7813 // CHECK18-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 7814 // CHECK18-NEXT: store i8* null, i8** [[TMP9]], align 8 7815 // CHECK18-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 7816 // CHECK18-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 7817 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 7818 // CHECK18-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 7819 // CHECK18-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 7820 // CHECK18-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 7821 // CHECK18-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 7822 // CHECK18-NEXT: store i8* null, i8** [[TMP14]], align 8 7823 // CHECK18-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 7824 // CHECK18-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 7825 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 7826 // CHECK18-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 7827 // CHECK18-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 7828 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 7829 // CHECK18-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 7830 // CHECK18-NEXT: store i8* null, i8** [[TMP19]], align 8 7831 // CHECK18-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 7832 // CHECK18-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 7833 // CHECK18-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 7834 // CHECK18-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 7835 // CHECK18-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 7836 // CHECK18: omp_offload.failed: 7837 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 7838 // CHECK18-NEXT: br label [[OMP_OFFLOAD_CONT]] 7839 // CHECK18: omp_offload.cont: 7840 // CHECK18-NEXT: br label [[OMP_IF_END:%.*]] 7841 // CHECK18: omp_if.else: 7842 // CHECK18-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 7843 // CHECK18-NEXT: br label [[OMP_IF_END]] 7844 // CHECK18: omp_if.end: 7845 // CHECK18-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 7846 // CHECK18-NEXT: ret i32 [[TMP24]] 7847 // 7848 // 7849 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 7850 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 7851 // CHECK18-NEXT: entry: 7852 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7853 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7854 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7855 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7856 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7857 // CHECK18-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 7858 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7859 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7860 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7861 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7862 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7863 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7864 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7865 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7866 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7867 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7868 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 7869 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 7870 // CHECK18-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 7871 // CHECK18-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 7872 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 7873 // CHECK18-NEXT: ret void 7874 // 7875 // 7876 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9 7877 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 7878 // CHECK18-NEXT: entry: 7879 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7880 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7881 // CHECK18-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 7882 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 7883 // CHECK18-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 7884 // CHECK18-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 7885 // CHECK18-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 7886 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7887 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7888 // CHECK18-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 7889 // CHECK18-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 7890 // CHECK18-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 7891 // CHECK18-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 7892 // CHECK18-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 7893 // CHECK18-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 7894 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 7895 // CHECK18-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 7896 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 7897 // CHECK18-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 7898 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 7899 // CHECK18-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 7900 // CHECK18-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 7901 // CHECK18-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 7902 // CHECK18-NEXT: store double [[ADD]], double* [[A]], align 8 7903 // CHECK18-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 7904 // CHECK18-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 7905 // CHECK18-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 7906 // CHECK18-NEXT: store double [[INC]], double* [[A4]], align 8 7907 // CHECK18-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 7908 // CHECK18-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 7909 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 7910 // CHECK18-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 7911 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 7912 // CHECK18-NEXT: ret void 7913 // 7914 // 7915 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 7916 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 7917 // CHECK18-NEXT: entry: 7918 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7919 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7920 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7921 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7922 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7923 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7924 // CHECK18-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 7925 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7926 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7927 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7928 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7929 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7930 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7931 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7932 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7933 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7934 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 7935 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 7936 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 7937 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 7938 // CHECK18-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 7939 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 7940 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 7941 // CHECK18-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 7942 // CHECK18-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 7943 // CHECK18-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 7944 // CHECK18-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 7945 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 7946 // CHECK18-NEXT: ret void 7947 // 7948 // 7949 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11 7950 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 7951 // CHECK18-NEXT: entry: 7952 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7953 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7954 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7955 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7956 // CHECK18-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 7957 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7958 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7959 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7960 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7961 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7962 // CHECK18-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 7963 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7964 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 7965 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 7966 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 7967 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 7968 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 7969 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 7970 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 7971 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 7972 // CHECK18-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 7973 // CHECK18-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 7974 // CHECK18-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 7975 // CHECK18-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 7976 // CHECK18-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 7977 // CHECK18-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 7978 // CHECK18-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 7979 // CHECK18-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 7980 // CHECK18-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 7981 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 7982 // CHECK18-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 7983 // CHECK18-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 7984 // CHECK18-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 7985 // CHECK18-NEXT: ret void 7986 // 7987 // 7988 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 7989 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 7990 // CHECK18-NEXT: entry: 7991 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 7992 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 7993 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 7994 // CHECK18-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 7995 // CHECK18-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 7996 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 7997 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 7998 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 7999 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8000 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8001 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8002 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 8003 // CHECK18-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 8004 // CHECK18-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 8005 // CHECK18-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 8006 // CHECK18-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 8007 // CHECK18-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 8008 // CHECK18-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 8009 // CHECK18-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 8010 // CHECK18-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 8011 // CHECK18-NEXT: ret void 8012 // 8013 // 8014 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14 8015 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 8016 // CHECK18-NEXT: entry: 8017 // CHECK18-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8018 // CHECK18-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8019 // CHECK18-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 8020 // CHECK18-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 8021 // CHECK18-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 8022 // CHECK18-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8023 // CHECK18-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8024 // CHECK18-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 8025 // CHECK18-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 8026 // CHECK18-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 8027 // CHECK18-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 8028 // CHECK18-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 8029 // CHECK18-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 8030 // CHECK18-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 8031 // CHECK18-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 8032 // CHECK18-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 8033 // CHECK18-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 8034 // CHECK18-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 8035 // CHECK18-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 8036 // CHECK18-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 8037 // CHECK18-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 8038 // CHECK18-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 8039 // CHECK18-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8040 // CHECK18-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 8041 // CHECK18-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 8042 // CHECK18-NEXT: ret void 8043 // 8044 // 8045 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 8046 // CHECK18-SAME: () #[[ATTR7:[0-9]+]] { 8047 // CHECK18-NEXT: entry: 8048 // CHECK18-NEXT: call void @__tgt_register_requires(i64 1) 8049 // CHECK18-NEXT: ret void 8050 // 8051 // 8052 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi 8053 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 8054 // CHECK19-NEXT: entry: 8055 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8056 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 8057 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 8058 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x float], align 4 8059 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8060 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8061 // CHECK19-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 8062 // CHECK19-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 8063 // CHECK19-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 8064 // CHECK19-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 8065 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8066 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8067 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 8068 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 8069 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 8070 // CHECK19-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 8071 // CHECK19-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 8072 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 8073 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 8074 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 8075 // CHECK19-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 8076 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 8077 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 8078 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 8079 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 8080 // CHECK19-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 8081 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8082 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 8083 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 8084 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8085 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8086 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 8087 // CHECK19-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 8088 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 8089 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 8090 // CHECK19-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 8091 // CHECK19-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 8092 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 8093 // CHECK19-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 8094 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 8095 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 8096 // CHECK19-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 8097 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 8098 // CHECK19-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 8099 // CHECK19-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 8100 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 8101 // CHECK19-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 8102 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8103 // CHECK19-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 8104 // CHECK19-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8105 // CHECK19-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8106 // CHECK19-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 8107 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 8108 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8109 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 8110 // CHECK19-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 8111 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 8112 // CHECK19-NEXT: store i8* null, i8** [[TMP17]], align 4 8113 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8114 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8115 // CHECK19-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8116 // CHECK19-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 8117 // CHECK19-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8118 // CHECK19: omp_offload.failed: 8119 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 8120 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 8121 // CHECK19: omp_offload.cont: 8122 // CHECK19-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 8123 // CHECK19-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 8124 // CHECK19-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 8125 // CHECK19-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 8126 // CHECK19-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 8127 // CHECK19-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 8128 // CHECK19-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 8129 // CHECK19-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 8130 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 8131 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8132 // CHECK19: omp_if.then: 8133 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 8134 // CHECK19-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 8135 // CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 8136 // CHECK19-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 8137 // CHECK19-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 8138 // CHECK19-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 8139 // CHECK19-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 8140 // CHECK19-NEXT: store i8* null, i8** [[TMP31]], align 4 8141 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 8142 // CHECK19-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* 8143 // CHECK19-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 8144 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 8145 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 8146 // CHECK19-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 8147 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 8148 // CHECK19-NEXT: store i8* null, i8** [[TMP36]], align 4 8149 // CHECK19-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 8150 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 8151 // CHECK19-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8152 // CHECK19-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 8153 // CHECK19-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 8154 // CHECK19: omp_offload.failed8: 8155 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 8156 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT9]] 8157 // CHECK19: omp_offload.cont9: 8158 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 8159 // CHECK19: omp_if.else: 8160 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 8161 // CHECK19-NEXT: br label [[OMP_IF_END]] 8162 // CHECK19: omp_if.end: 8163 // CHECK19-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 8164 // CHECK19-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 8165 // CHECK19-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 8166 // CHECK19-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 8167 // CHECK19-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 8168 // CHECK19-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] 8169 // CHECK19: omp_if.then12: 8170 // CHECK19-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 8171 // CHECK19-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 8172 // CHECK19-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] 8173 // CHECK19-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 8174 // CHECK19-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 8175 // CHECK19-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 8176 // CHECK19-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* 8177 // CHECK19-NEXT: store i32 [[TMP42]], i32* [[TMP50]], align 4 8178 // CHECK19-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 8179 // CHECK19-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* 8180 // CHECK19-NEXT: store i32 [[TMP42]], i32* [[TMP52]], align 4 8181 // CHECK19-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 8182 // CHECK19-NEXT: store i64 4, i64* [[TMP53]], align 4 8183 // CHECK19-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 8184 // CHECK19-NEXT: store i8* null, i8** [[TMP54]], align 4 8185 // CHECK19-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 8186 // CHECK19-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 8187 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 8188 // CHECK19-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 8189 // CHECK19-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 8190 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 8191 // CHECK19-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 8192 // CHECK19-NEXT: store i64 40, i64* [[TMP59]], align 4 8193 // CHECK19-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 8194 // CHECK19-NEXT: store i8* null, i8** [[TMP60]], align 4 8195 // CHECK19-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 8196 // CHECK19-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 8197 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP62]], align 4 8198 // CHECK19-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 8199 // CHECK19-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* 8200 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP64]], align 4 8201 // CHECK19-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 8202 // CHECK19-NEXT: store i64 4, i64* [[TMP65]], align 4 8203 // CHECK19-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 8204 // CHECK19-NEXT: store i8* null, i8** [[TMP66]], align 4 8205 // CHECK19-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 8206 // CHECK19-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 8207 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 8208 // CHECK19-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 8209 // CHECK19-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** 8210 // CHECK19-NEXT: store float* [[VLA]], float** [[TMP70]], align 4 8211 // CHECK19-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 8212 // CHECK19-NEXT: store i64 [[TMP45]], i64* [[TMP71]], align 4 8213 // CHECK19-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 8214 // CHECK19-NEXT: store i8* null, i8** [[TMP72]], align 4 8215 // CHECK19-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 8216 // CHECK19-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 8217 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 8218 // CHECK19-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 8219 // CHECK19-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** 8220 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4 8221 // CHECK19-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 8222 // CHECK19-NEXT: store i64 400, i64* [[TMP77]], align 4 8223 // CHECK19-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 8224 // CHECK19-NEXT: store i8* null, i8** [[TMP78]], align 4 8225 // CHECK19-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 8226 // CHECK19-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* 8227 // CHECK19-NEXT: store i32 5, i32* [[TMP80]], align 4 8228 // CHECK19-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 8229 // CHECK19-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* 8230 // CHECK19-NEXT: store i32 5, i32* [[TMP82]], align 4 8231 // CHECK19-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 8232 // CHECK19-NEXT: store i64 4, i64* [[TMP83]], align 4 8233 // CHECK19-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 8234 // CHECK19-NEXT: store i8* null, i8** [[TMP84]], align 4 8235 // CHECK19-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 8236 // CHECK19-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* 8237 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP86]], align 4 8238 // CHECK19-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 8239 // CHECK19-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 8240 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP88]], align 4 8241 // CHECK19-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 8242 // CHECK19-NEXT: store i64 4, i64* [[TMP89]], align 4 8243 // CHECK19-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 8244 // CHECK19-NEXT: store i8* null, i8** [[TMP90]], align 4 8245 // CHECK19-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 8246 // CHECK19-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** 8247 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP92]], align 4 8248 // CHECK19-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 8249 // CHECK19-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** 8250 // CHECK19-NEXT: store double* [[VLA1]], double** [[TMP94]], align 4 8251 // CHECK19-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 8252 // CHECK19-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 4 8253 // CHECK19-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 8254 // CHECK19-NEXT: store i8* null, i8** [[TMP96]], align 4 8255 // CHECK19-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 8256 // CHECK19-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** 8257 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4 8258 // CHECK19-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 8259 // CHECK19-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** 8260 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4 8261 // CHECK19-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 8262 // CHECK19-NEXT: store i64 12, i64* [[TMP101]], align 4 8263 // CHECK19-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 8264 // CHECK19-NEXT: store i8* null, i8** [[TMP102]], align 4 8265 // CHECK19-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 8266 // CHECK19-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 8267 // CHECK19-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 8268 // CHECK19-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8269 // CHECK19-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 8270 // CHECK19-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 8271 // CHECK19: omp_offload.failed16: 8272 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 8273 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT17]] 8274 // CHECK19: omp_offload.cont17: 8275 // CHECK19-NEXT: br label [[OMP_IF_END19:%.*]] 8276 // CHECK19: omp_if.else18: 8277 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 8278 // CHECK19-NEXT: br label [[OMP_IF_END19]] 8279 // CHECK19: omp_if.end19: 8280 // CHECK19-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 8281 // CHECK19-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8282 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) 8283 // CHECK19-NEXT: ret i32 [[TMP108]] 8284 // 8285 // 8286 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 8287 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] { 8288 // CHECK19-NEXT: entry: 8289 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 8290 // CHECK19-NEXT: ret void 8291 // 8292 // 8293 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined. 8294 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 8295 // CHECK19-NEXT: entry: 8296 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8297 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8298 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8299 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8300 // CHECK19-NEXT: ret void 8301 // 8302 // 8303 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry. 8304 // CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 8305 // CHECK19-NEXT: entry: 8306 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 8307 // CHECK19-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 8308 // CHECK19-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 8309 // CHECK19-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 8310 // CHECK19-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 8311 // CHECK19-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 8312 // CHECK19-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 8313 // CHECK19-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 8314 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 8315 // CHECK19-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 8316 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 8317 // CHECK19-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 8318 // CHECK19-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 8319 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 8320 // CHECK19-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 8321 // CHECK19-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 8322 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 8323 // CHECK19-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 8324 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 8325 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 8326 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 8327 // CHECK19-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 8328 // CHECK19-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 8329 // CHECK19-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 8330 // CHECK19-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 8331 // CHECK19-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 8332 // CHECK19-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 8333 // CHECK19-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 8334 // CHECK19-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 8335 // CHECK19-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 8336 // CHECK19-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 8337 // CHECK19-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 8338 // CHECK19: omp_offload.failed.i: 8339 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 8340 // CHECK19-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 8341 // CHECK19: .omp_outlined..1.exit: 8342 // CHECK19-NEXT: ret i32 0 8343 // 8344 // 8345 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 8346 // CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { 8347 // CHECK19-NEXT: entry: 8348 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8349 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8350 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8351 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8352 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8353 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8354 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8355 // CHECK19-NEXT: ret void 8356 // 8357 // 8358 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2 8359 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { 8360 // CHECK19-NEXT: entry: 8361 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8362 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8363 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8364 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8365 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8366 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8367 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8368 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8369 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8370 // CHECK19-NEXT: ret void 8371 // 8372 // 8373 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 8374 // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { 8375 // CHECK19-NEXT: entry: 8376 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8377 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8378 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8379 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8380 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 8381 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8382 // CHECK19-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 8383 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8384 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 8385 // CHECK19-NEXT: ret void 8386 // 8387 // 8388 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3 8389 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { 8390 // CHECK19-NEXT: entry: 8391 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8392 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8393 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8394 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8395 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8396 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8397 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8398 // CHECK19-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 8399 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 8400 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 8401 // CHECK19-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 8402 // CHECK19-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 8403 // CHECK19-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 8404 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 8405 // CHECK19-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 8406 // CHECK19-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 8407 // CHECK19-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 8408 // CHECK19: .cancel.exit: 8409 // CHECK19-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 8410 // CHECK19-NEXT: br label [[DOTCANCEL_CONTINUE]] 8411 // CHECK19: .cancel.continue: 8412 // CHECK19-NEXT: ret void 8413 // 8414 // 8415 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 8416 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 8417 // CHECK19-NEXT: entry: 8418 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8419 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8420 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8421 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8422 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8423 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8424 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8425 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8426 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8427 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8428 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 8429 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8430 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 8431 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8432 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 8433 // CHECK19-NEXT: ret void 8434 // 8435 // 8436 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4 8437 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { 8438 // CHECK19-NEXT: entry: 8439 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8440 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8441 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8442 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8443 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8444 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8445 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8446 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8447 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8448 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 8449 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8450 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8451 // CHECK19-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 8452 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 8453 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 8454 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 8455 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 8456 // CHECK19-NEXT: ret void 8457 // 8458 // 8459 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 8460 // CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 8461 // CHECK19-NEXT: entry: 8462 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8463 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8464 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8465 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8466 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8467 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8468 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8469 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8470 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8471 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8472 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8473 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8474 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8475 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8476 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8477 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8478 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8479 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8480 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8481 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8482 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8483 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8484 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8485 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8486 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8487 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8488 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8489 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8490 // CHECK19-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 8491 // CHECK19-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 8492 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 8493 // CHECK19-NEXT: ret void 8494 // 8495 // 8496 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7 8497 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 8498 // CHECK19-NEXT: entry: 8499 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8500 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8501 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8502 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 8503 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8504 // CHECK19-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 8505 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 8506 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8507 // CHECK19-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 8508 // CHECK19-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 8509 // CHECK19-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 8510 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8511 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8512 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8513 // CHECK19-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 8514 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8515 // CHECK19-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 8516 // CHECK19-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 8517 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8518 // CHECK19-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 8519 // CHECK19-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 8520 // CHECK19-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 8521 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 8522 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8523 // CHECK19-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 8524 // CHECK19-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 8525 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8526 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 8527 // CHECK19-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 8528 // CHECK19-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 8529 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 8530 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 8531 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8532 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 8533 // CHECK19-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 8534 // CHECK19-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 8535 // CHECK19-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 8536 // CHECK19-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 8537 // CHECK19-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 8538 // CHECK19-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 8539 // CHECK19-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 8540 // CHECK19-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 8541 // CHECK19-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 8542 // CHECK19-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 8543 // CHECK19-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 8544 // CHECK19-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 8545 // CHECK19-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 8546 // CHECK19-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 8547 // CHECK19-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 8548 // CHECK19-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 8549 // CHECK19-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 8550 // CHECK19-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 8551 // CHECK19-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 8552 // CHECK19-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 8553 // CHECK19-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 8554 // CHECK19-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 8555 // CHECK19-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 8556 // CHECK19-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 8557 // CHECK19-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 8558 // CHECK19-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 8559 // CHECK19-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 8560 // CHECK19-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 8561 // CHECK19-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 8562 // CHECK19-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 8563 // CHECK19-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 8564 // CHECK19-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 8565 // CHECK19-NEXT: ret void 8566 // 8567 // 8568 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari 8569 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 8570 // CHECK19-NEXT: entry: 8571 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8572 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 8573 // CHECK19-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 8574 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8575 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 8576 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8577 // CHECK19-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 8578 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 8579 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 8580 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A]], align 4 8581 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 8582 // CHECK19-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 8583 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 8584 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 8585 // CHECK19-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 8586 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8587 // CHECK19-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 8588 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 8589 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 8590 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 8591 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8592 // CHECK19-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 8593 // CHECK19-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 8594 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 8595 // CHECK19-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 8596 // CHECK19-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 8597 // CHECK19-NEXT: ret i32 [[TMP8]] 8598 // 8599 // 8600 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 8601 // CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 8602 // CHECK19-NEXT: entry: 8603 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8604 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8605 // CHECK19-NEXT: [[B:%.*]] = alloca i32, align 4 8606 // CHECK19-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 8607 // CHECK19-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 8608 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 8609 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 8610 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 8611 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 8612 // CHECK19-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 8613 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8614 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8615 // CHECK19-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8616 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 8617 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 8618 // CHECK19-NEXT: store i32 [[ADD]], i32* [[B]], align 4 8619 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 8620 // CHECK19-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 8621 // CHECK19-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 8622 // CHECK19-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 8623 // CHECK19-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 8624 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 8625 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 8626 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 8627 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 8628 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8629 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 8630 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8631 // CHECK19: omp_if.then: 8632 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 8633 // CHECK19-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 8634 // CHECK19-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 8635 // CHECK19-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 8636 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8637 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 8638 // CHECK19-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 8639 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8640 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 8641 // CHECK19-NEXT: store double* [[A]], double** [[TMP13]], align 4 8642 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 8643 // CHECK19-NEXT: store i64 8, i64* [[TMP14]], align 4 8644 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 8645 // CHECK19-NEXT: store i8* null, i8** [[TMP15]], align 4 8646 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 8647 // CHECK19-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 8648 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 8649 // CHECK19-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 8650 // CHECK19-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 8651 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 8652 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 8653 // CHECK19-NEXT: store i64 4, i64* [[TMP20]], align 4 8654 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 8655 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 8656 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 8657 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 8658 // CHECK19-NEXT: store i32 2, i32* [[TMP23]], align 4 8659 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 8660 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 8661 // CHECK19-NEXT: store i32 2, i32* [[TMP25]], align 4 8662 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 8663 // CHECK19-NEXT: store i64 4, i64* [[TMP26]], align 4 8664 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 8665 // CHECK19-NEXT: store i8* null, i8** [[TMP27]], align 4 8666 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 8667 // CHECK19-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 8668 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 8669 // CHECK19-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 8670 // CHECK19-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 8671 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 8672 // CHECK19-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 8673 // CHECK19-NEXT: store i64 4, i64* [[TMP32]], align 4 8674 // CHECK19-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 8675 // CHECK19-NEXT: store i8* null, i8** [[TMP33]], align 4 8676 // CHECK19-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 8677 // CHECK19-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 8678 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 8679 // CHECK19-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 8680 // CHECK19-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 8681 // CHECK19-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 8682 // CHECK19-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 8683 // CHECK19-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 8684 // CHECK19-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 8685 // CHECK19-NEXT: store i8* null, i8** [[TMP39]], align 4 8686 // CHECK19-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8687 // CHECK19-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8688 // CHECK19-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 8689 // CHECK19-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8690 // CHECK19-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 8691 // CHECK19-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8692 // CHECK19: omp_offload.failed: 8693 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 8694 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 8695 // CHECK19: omp_offload.cont: 8696 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 8697 // CHECK19: omp_if.else: 8698 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 8699 // CHECK19-NEXT: br label [[OMP_IF_END]] 8700 // CHECK19: omp_if.end: 8701 // CHECK19-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 8702 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 8703 // CHECK19-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8704 // CHECK19-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 8705 // CHECK19-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 8706 // CHECK19-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 8707 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 8708 // CHECK19-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 8709 // CHECK19-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 8710 // CHECK19-NEXT: ret i32 [[ADD3]] 8711 // 8712 // 8713 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici 8714 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 8715 // CHECK19-NEXT: entry: 8716 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8717 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 8718 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 8719 // CHECK19-NEXT: [[AAA:%.*]] = alloca i8, align 1 8720 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8721 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8722 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8723 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 8724 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 8725 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 8726 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 8727 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8728 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 8729 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 8730 // CHECK19-NEXT: store i8 0, i8* [[AAA]], align 1 8731 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8732 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8733 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8734 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 8735 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8736 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 8737 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8738 // CHECK19-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 8739 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 8740 // CHECK19-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 8741 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 8742 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 8743 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 8744 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8745 // CHECK19: omp_if.then: 8746 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8747 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 8748 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 8749 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8750 // CHECK19-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 8751 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 8752 // CHECK19-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 8753 // CHECK19-NEXT: store i8* null, i8** [[TMP11]], align 4 8754 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 8755 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 8756 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 8757 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 8758 // CHECK19-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 8759 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 8760 // CHECK19-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 8761 // CHECK19-NEXT: store i8* null, i8** [[TMP16]], align 4 8762 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 8763 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 8764 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 8765 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 8766 // CHECK19-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 8767 // CHECK19-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 8768 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 8769 // CHECK19-NEXT: store i8* null, i8** [[TMP21]], align 4 8770 // CHECK19-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 8771 // CHECK19-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 8772 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 8773 // CHECK19-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 8774 // CHECK19-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 8775 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 8776 // CHECK19-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 8777 // CHECK19-NEXT: store i8* null, i8** [[TMP26]], align 4 8778 // CHECK19-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8779 // CHECK19-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8780 // CHECK19-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8781 // CHECK19-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 8782 // CHECK19-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8783 // CHECK19: omp_offload.failed: 8784 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 8785 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 8786 // CHECK19: omp_offload.cont: 8787 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 8788 // CHECK19: omp_if.else: 8789 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 8790 // CHECK19-NEXT: br label [[OMP_IF_END]] 8791 // CHECK19: omp_if.end: 8792 // CHECK19-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 8793 // CHECK19-NEXT: ret i32 [[TMP31]] 8794 // 8795 // 8796 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 8797 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 8798 // CHECK19-NEXT: entry: 8799 // CHECK19-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 8800 // CHECK19-NEXT: [[A:%.*]] = alloca i32, align 4 8801 // CHECK19-NEXT: [[AA:%.*]] = alloca i16, align 2 8802 // CHECK19-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 8803 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8804 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8805 // CHECK19-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 8806 // CHECK19-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 8807 // CHECK19-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 8808 // CHECK19-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 8809 // CHECK19-NEXT: store i32 0, i32* [[A]], align 4 8810 // CHECK19-NEXT: store i16 0, i16* [[AA]], align 2 8811 // CHECK19-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 8812 // CHECK19-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 8813 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 8814 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 8815 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8816 // CHECK19-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 8817 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8818 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 8819 // CHECK19-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 8820 // CHECK19-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 8821 // CHECK19: omp_if.then: 8822 // CHECK19-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8823 // CHECK19-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 8824 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 8825 // CHECK19-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8826 // CHECK19-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 8827 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 8828 // CHECK19-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 8829 // CHECK19-NEXT: store i8* null, i8** [[TMP9]], align 4 8830 // CHECK19-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 8831 // CHECK19-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 8832 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 8833 // CHECK19-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 8834 // CHECK19-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 8835 // CHECK19-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 8836 // CHECK19-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 8837 // CHECK19-NEXT: store i8* null, i8** [[TMP14]], align 4 8838 // CHECK19-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 8839 // CHECK19-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 8840 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 8841 // CHECK19-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 8842 // CHECK19-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 8843 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 8844 // CHECK19-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 8845 // CHECK19-NEXT: store i8* null, i8** [[TMP19]], align 4 8846 // CHECK19-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 8847 // CHECK19-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 8848 // CHECK19-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 8849 // CHECK19-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 8850 // CHECK19-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 8851 // CHECK19: omp_offload.failed: 8852 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 8853 // CHECK19-NEXT: br label [[OMP_OFFLOAD_CONT]] 8854 // CHECK19: omp_offload.cont: 8855 // CHECK19-NEXT: br label [[OMP_IF_END:%.*]] 8856 // CHECK19: omp_if.else: 8857 // CHECK19-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 8858 // CHECK19-NEXT: br label [[OMP_IF_END]] 8859 // CHECK19: omp_if.end: 8860 // CHECK19-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 8861 // CHECK19-NEXT: ret i32 [[TMP24]] 8862 // 8863 // 8864 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 8865 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 8866 // CHECK19-NEXT: entry: 8867 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8868 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8869 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8870 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8871 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8872 // CHECK19-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 8873 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8874 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8875 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8876 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8877 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8878 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8879 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8880 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8881 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8882 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8883 // CHECK19-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 8884 // CHECK19-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 8885 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 8886 // CHECK19-NEXT: ret void 8887 // 8888 // 8889 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9 8890 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 8891 // CHECK19-NEXT: entry: 8892 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8893 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8894 // CHECK19-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 8895 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 8896 // CHECK19-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 8897 // CHECK19-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 8898 // CHECK19-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 8899 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8900 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8901 // CHECK19-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 8902 // CHECK19-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 8903 // CHECK19-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 8904 // CHECK19-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 8905 // CHECK19-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 8906 // CHECK19-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 8907 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 8908 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 8909 // CHECK19-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 8910 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 8911 // CHECK19-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 8912 // CHECK19-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 8913 // CHECK19-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 8914 // CHECK19-NEXT: store double [[ADD]], double* [[A]], align 4 8915 // CHECK19-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 8916 // CHECK19-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 8917 // CHECK19-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 8918 // CHECK19-NEXT: store double [[INC]], double* [[A3]], align 4 8919 // CHECK19-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 8920 // CHECK19-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 8921 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 8922 // CHECK19-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 8923 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 8924 // CHECK19-NEXT: ret void 8925 // 8926 // 8927 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 8928 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 8929 // CHECK19-NEXT: entry: 8930 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8931 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8932 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8933 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8934 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 8935 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 8936 // CHECK19-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 8937 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8938 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8939 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8940 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8941 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8942 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8943 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8944 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8945 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 8946 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 8947 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 8948 // CHECK19-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 8949 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 8950 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 8951 // CHECK19-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 8952 // CHECK19-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 8953 // CHECK19-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 8954 // CHECK19-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 8955 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 8956 // CHECK19-NEXT: ret void 8957 // 8958 // 8959 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11 8960 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 8961 // CHECK19-NEXT: entry: 8962 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 8963 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 8964 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 8965 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 8966 // CHECK19-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 8967 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 8968 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 8969 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 8970 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 8971 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 8972 // CHECK19-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 8973 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 8974 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 8975 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 8976 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 8977 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 8978 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 8979 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 8980 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 8981 // CHECK19-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 8982 // CHECK19-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 8983 // CHECK19-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 8984 // CHECK19-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 8985 // CHECK19-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 8986 // CHECK19-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 8987 // CHECK19-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 8988 // CHECK19-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 8989 // CHECK19-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 8990 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 8991 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 8992 // CHECK19-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 8993 // CHECK19-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 8994 // CHECK19-NEXT: ret void 8995 // 8996 // 8997 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 8998 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 8999 // CHECK19-NEXT: entry: 9000 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9001 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9002 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9003 // CHECK19-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9004 // CHECK19-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9005 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9006 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9007 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9008 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9009 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9010 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9011 // CHECK19-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9012 // CHECK19-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9013 // CHECK19-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9014 // CHECK19-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9015 // CHECK19-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 9016 // CHECK19-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9017 // CHECK19-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 9018 // CHECK19-NEXT: ret void 9019 // 9020 // 9021 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14 9022 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 9023 // CHECK19-NEXT: entry: 9024 // CHECK19-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9025 // CHECK19-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9026 // CHECK19-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9027 // CHECK19-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9028 // CHECK19-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9029 // CHECK19-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9030 // CHECK19-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9031 // CHECK19-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9032 // CHECK19-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9033 // CHECK19-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9034 // CHECK19-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9035 // CHECK19-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9036 // CHECK19-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9037 // CHECK19-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 9038 // CHECK19-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9039 // CHECK19-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 9040 // CHECK19-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 9041 // CHECK19-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 9042 // CHECK19-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 9043 // CHECK19-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 9044 // CHECK19-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 9045 // CHECK19-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9046 // CHECK19-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 9047 // CHECK19-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 9048 // CHECK19-NEXT: ret void 9049 // 9050 // 9051 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 9052 // CHECK19-SAME: () #[[ATTR7:[0-9]+]] { 9053 // CHECK19-NEXT: entry: 9054 // CHECK19-NEXT: call void @__tgt_register_requires(i64 1) 9055 // CHECK19-NEXT: ret void 9056 // 9057 // 9058 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi 9059 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] { 9060 // CHECK20-NEXT: entry: 9061 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9062 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 9063 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 9064 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x float], align 4 9065 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 9066 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 9067 // CHECK20-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 9068 // CHECK20-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 9069 // CHECK20-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 9070 // CHECK20-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 9071 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9072 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9073 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 9074 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 9075 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 9076 // CHECK20-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 9077 // CHECK20-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 9078 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 9079 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 9080 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 9081 // CHECK20-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 9082 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 9083 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 9084 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 9085 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 9086 // CHECK20-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 9087 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9088 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 9089 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 9090 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9091 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 9092 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 9093 // CHECK20-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 9094 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 9095 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 9096 // CHECK20-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 9097 // CHECK20-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 9098 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 9099 // CHECK20-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 9100 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 9101 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 9102 // CHECK20-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 9103 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 9104 // CHECK20-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 9105 // CHECK20-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 9106 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 9107 // CHECK20-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 9108 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9109 // CHECK20-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 9110 // CHECK20-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9111 // CHECK20-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9112 // CHECK20-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 9113 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 9114 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9115 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 9116 // CHECK20-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 9117 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 9118 // CHECK20-NEXT: store i8* null, i8** [[TMP17]], align 4 9119 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9120 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9121 // CHECK20-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9122 // CHECK20-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 9123 // CHECK20-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9124 // CHECK20: omp_offload.failed: 9125 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 9126 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 9127 // CHECK20: omp_offload.cont: 9128 // CHECK20-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 9129 // CHECK20-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 9130 // CHECK20-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 9131 // CHECK20-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 9132 // CHECK20-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 9133 // CHECK20-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 9134 // CHECK20-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 9135 // CHECK20-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 9136 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 9137 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9138 // CHECK20: omp_if.then: 9139 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 9140 // CHECK20-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 9141 // CHECK20-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 9142 // CHECK20-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 9143 // CHECK20-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 9144 // CHECK20-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 9145 // CHECK20-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 9146 // CHECK20-NEXT: store i8* null, i8** [[TMP31]], align 4 9147 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 9148 // CHECK20-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* 9149 // CHECK20-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 9150 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 9151 // CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 9152 // CHECK20-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 9153 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 9154 // CHECK20-NEXT: store i8* null, i8** [[TMP36]], align 4 9155 // CHECK20-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 9156 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 9157 // CHECK20-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9158 // CHECK20-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 9159 // CHECK20-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 9160 // CHECK20: omp_offload.failed8: 9161 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 9162 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT9]] 9163 // CHECK20: omp_offload.cont9: 9164 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 9165 // CHECK20: omp_if.else: 9166 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 9167 // CHECK20-NEXT: br label [[OMP_IF_END]] 9168 // CHECK20: omp_if.end: 9169 // CHECK20-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 9170 // CHECK20-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 9171 // CHECK20-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 9172 // CHECK20-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 9173 // CHECK20-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 9174 // CHECK20-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] 9175 // CHECK20: omp_if.then12: 9176 // CHECK20-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 9177 // CHECK20-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 9178 // CHECK20-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] 9179 // CHECK20-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 9180 // CHECK20-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 9181 // CHECK20-NEXT: [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 9182 // CHECK20-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32* 9183 // CHECK20-NEXT: store i32 [[TMP42]], i32* [[TMP50]], align 4 9184 // CHECK20-NEXT: [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 9185 // CHECK20-NEXT: [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32* 9186 // CHECK20-NEXT: store i32 [[TMP42]], i32* [[TMP52]], align 4 9187 // CHECK20-NEXT: [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 9188 // CHECK20-NEXT: store i64 4, i64* [[TMP53]], align 4 9189 // CHECK20-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 9190 // CHECK20-NEXT: store i8* null, i8** [[TMP54]], align 4 9191 // CHECK20-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 9192 // CHECK20-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 9193 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 9194 // CHECK20-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 9195 // CHECK20-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 9196 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 9197 // CHECK20-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 9198 // CHECK20-NEXT: store i64 40, i64* [[TMP59]], align 4 9199 // CHECK20-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 9200 // CHECK20-NEXT: store i8* null, i8** [[TMP60]], align 4 9201 // CHECK20-NEXT: [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 9202 // CHECK20-NEXT: [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32* 9203 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP62]], align 4 9204 // CHECK20-NEXT: [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 9205 // CHECK20-NEXT: [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32* 9206 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP64]], align 4 9207 // CHECK20-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 9208 // CHECK20-NEXT: store i64 4, i64* [[TMP65]], align 4 9209 // CHECK20-NEXT: [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 9210 // CHECK20-NEXT: store i8* null, i8** [[TMP66]], align 4 9211 // CHECK20-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 9212 // CHECK20-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 9213 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 9214 // CHECK20-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 9215 // CHECK20-NEXT: [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float** 9216 // CHECK20-NEXT: store float* [[VLA]], float** [[TMP70]], align 4 9217 // CHECK20-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 9218 // CHECK20-NEXT: store i64 [[TMP45]], i64* [[TMP71]], align 4 9219 // CHECK20-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 9220 // CHECK20-NEXT: store i8* null, i8** [[TMP72]], align 4 9221 // CHECK20-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 9222 // CHECK20-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 9223 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 9224 // CHECK20-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 9225 // CHECK20-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]** 9226 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4 9227 // CHECK20-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 9228 // CHECK20-NEXT: store i64 400, i64* [[TMP77]], align 4 9229 // CHECK20-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 9230 // CHECK20-NEXT: store i8* null, i8** [[TMP78]], align 4 9231 // CHECK20-NEXT: [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 9232 // CHECK20-NEXT: [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32* 9233 // CHECK20-NEXT: store i32 5, i32* [[TMP80]], align 4 9234 // CHECK20-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 9235 // CHECK20-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* 9236 // CHECK20-NEXT: store i32 5, i32* [[TMP82]], align 4 9237 // CHECK20-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5 9238 // CHECK20-NEXT: store i64 4, i64* [[TMP83]], align 4 9239 // CHECK20-NEXT: [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 9240 // CHECK20-NEXT: store i8* null, i8** [[TMP84]], align 4 9241 // CHECK20-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 9242 // CHECK20-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32* 9243 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP86]], align 4 9244 // CHECK20-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 9245 // CHECK20-NEXT: [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32* 9246 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP88]], align 4 9247 // CHECK20-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6 9248 // CHECK20-NEXT: store i64 4, i64* [[TMP89]], align 4 9249 // CHECK20-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 9250 // CHECK20-NEXT: store i8* null, i8** [[TMP90]], align 4 9251 // CHECK20-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 9252 // CHECK20-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double** 9253 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP92]], align 4 9254 // CHECK20-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 9255 // CHECK20-NEXT: [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double** 9256 // CHECK20-NEXT: store double* [[VLA1]], double** [[TMP94]], align 4 9257 // CHECK20-NEXT: [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 9258 // CHECK20-NEXT: store i64 [[TMP48]], i64* [[TMP95]], align 4 9259 // CHECK20-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 9260 // CHECK20-NEXT: store i8* null, i8** [[TMP96]], align 4 9261 // CHECK20-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 9262 // CHECK20-NEXT: [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT** 9263 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4 9264 // CHECK20-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 9265 // CHECK20-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT** 9266 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4 9267 // CHECK20-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8 9268 // CHECK20-NEXT: store i64 12, i64* [[TMP101]], align 4 9269 // CHECK20-NEXT: [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 9270 // CHECK20-NEXT: store i8* null, i8** [[TMP102]], align 4 9271 // CHECK20-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 9272 // CHECK20-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 9273 // CHECK20-NEXT: [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 9274 // CHECK20-NEXT: [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9275 // CHECK20-NEXT: [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0 9276 // CHECK20-NEXT: br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 9277 // CHECK20: omp_offload.failed16: 9278 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 9279 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT17]] 9280 // CHECK20: omp_offload.cont17: 9281 // CHECK20-NEXT: br label [[OMP_IF_END19:%.*]] 9282 // CHECK20: omp_if.else18: 9283 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 9284 // CHECK20-NEXT: br label [[OMP_IF_END19]] 9285 // CHECK20: omp_if.end19: 9286 // CHECK20-NEXT: [[TMP108:%.*]] = load i32, i32* [[A]], align 4 9287 // CHECK20-NEXT: [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9288 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP109]]) 9289 // CHECK20-NEXT: ret i32 [[TMP108]] 9290 // 9291 // 9292 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 9293 // CHECK20-SAME: () #[[ATTR2:[0-9]+]] { 9294 // CHECK20-NEXT: entry: 9295 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 9296 // CHECK20-NEXT: ret void 9297 // 9298 // 9299 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined. 9300 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 9301 // CHECK20-NEXT: entry: 9302 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9303 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9304 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9305 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9306 // CHECK20-NEXT: ret void 9307 // 9308 // 9309 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry. 9310 // CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 9311 // CHECK20-NEXT: entry: 9312 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 9313 // CHECK20-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 9314 // CHECK20-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 9315 // CHECK20-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 9316 // CHECK20-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 9317 // CHECK20-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 9318 // CHECK20-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 9319 // CHECK20-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 9320 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 9321 // CHECK20-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 9322 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 9323 // CHECK20-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 9324 // CHECK20-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 9325 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 9326 // CHECK20-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 9327 // CHECK20-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 9328 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 9329 // CHECK20-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 9330 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 9331 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 9332 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 9333 // CHECK20-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 9334 // CHECK20-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 9335 // CHECK20-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 9336 // CHECK20-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 9337 // CHECK20-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 9338 // CHECK20-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 9339 // CHECK20-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 9340 // CHECK20-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 9341 // CHECK20-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 9342 // CHECK20-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 9343 // CHECK20-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 9344 // CHECK20: omp_offload.failed.i: 9345 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 9346 // CHECK20-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 9347 // CHECK20: .omp_outlined..1.exit: 9348 // CHECK20-NEXT: ret i32 0 9349 // 9350 // 9351 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 9352 // CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR3]] { 9353 // CHECK20-NEXT: entry: 9354 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9355 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9356 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9357 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9358 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9359 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9360 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 9361 // CHECK20-NEXT: ret void 9362 // 9363 // 9364 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2 9365 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR3]] { 9366 // CHECK20-NEXT: entry: 9367 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9368 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9369 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9370 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9371 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9372 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9373 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9374 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9375 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9376 // CHECK20-NEXT: ret void 9377 // 9378 // 9379 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 9380 // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] { 9381 // CHECK20-NEXT: entry: 9382 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9383 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9384 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9385 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9386 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9387 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9388 // CHECK20-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 9389 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9390 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 9391 // CHECK20-NEXT: ret void 9392 // 9393 // 9394 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3 9395 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { 9396 // CHECK20-NEXT: entry: 9397 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9398 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9399 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9400 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9401 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9402 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9403 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9404 // CHECK20-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 9405 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 9406 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 9407 // CHECK20-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 9408 // CHECK20-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 9409 // CHECK20-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 9410 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 9411 // CHECK20-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 9412 // CHECK20-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 9413 // CHECK20-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 9414 // CHECK20: .cancel.exit: 9415 // CHECK20-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 9416 // CHECK20-NEXT: br label [[DOTCANCEL_CONTINUE]] 9417 // CHECK20: .cancel.continue: 9418 // CHECK20-NEXT: ret void 9419 // 9420 // 9421 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 9422 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] { 9423 // CHECK20-NEXT: entry: 9424 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9425 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9426 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9427 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9428 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9429 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9430 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9431 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9432 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9433 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9434 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 9435 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9436 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 9437 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9438 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 9439 // CHECK20-NEXT: ret void 9440 // 9441 // 9442 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4 9443 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR3]] { 9444 // CHECK20-NEXT: entry: 9445 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9446 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9447 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9448 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9449 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9450 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9451 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9452 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9453 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9454 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 9455 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9456 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9457 // CHECK20-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 9458 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 9459 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 9460 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 9461 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 9462 // CHECK20-NEXT: ret void 9463 // 9464 // 9465 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 9466 // CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 9467 // CHECK20-NEXT: entry: 9468 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9469 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9470 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9471 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9472 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9473 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9474 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9475 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9476 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9477 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9478 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9479 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9480 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9481 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9482 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9483 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9484 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9485 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9486 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9487 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9488 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9489 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9490 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9491 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9492 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9493 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9494 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9495 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 9496 // CHECK20-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 9497 // CHECK20-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 9498 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 9499 // CHECK20-NEXT: ret void 9500 // 9501 // 9502 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7 9503 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 9504 // CHECK20-NEXT: entry: 9505 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9506 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9507 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9508 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 9509 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9510 // CHECK20-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 9511 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 9512 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9513 // CHECK20-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 9514 // CHECK20-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 9515 // CHECK20-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 9516 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9517 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9518 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9519 // CHECK20-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 9520 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9521 // CHECK20-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 9522 // CHECK20-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 9523 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9524 // CHECK20-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 9525 // CHECK20-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 9526 // CHECK20-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 9527 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 9528 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9529 // CHECK20-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 9530 // CHECK20-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 9531 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9532 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 9533 // CHECK20-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 9534 // CHECK20-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 9535 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 9536 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 9537 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9538 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 9539 // CHECK20-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 9540 // CHECK20-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 9541 // CHECK20-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 9542 // CHECK20-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 9543 // CHECK20-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 9544 // CHECK20-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 9545 // CHECK20-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 9546 // CHECK20-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 9547 // CHECK20-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 9548 // CHECK20-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 9549 // CHECK20-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 9550 // CHECK20-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 9551 // CHECK20-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 9552 // CHECK20-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 9553 // CHECK20-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 9554 // CHECK20-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 9555 // CHECK20-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 9556 // CHECK20-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 9557 // CHECK20-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 9558 // CHECK20-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 9559 // CHECK20-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 9560 // CHECK20-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 9561 // CHECK20-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 9562 // CHECK20-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 9563 // CHECK20-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 9564 // CHECK20-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 9565 // CHECK20-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 9566 // CHECK20-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 9567 // CHECK20-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 9568 // CHECK20-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 9569 // CHECK20-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 9570 // CHECK20-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 9571 // CHECK20-NEXT: ret void 9572 // 9573 // 9574 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari 9575 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 9576 // CHECK20-NEXT: entry: 9577 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9578 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 9579 // CHECK20-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 9580 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9581 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 9582 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9583 // CHECK20-NEXT: [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]]) 9584 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 9585 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 9586 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A]], align 4 9587 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 9588 // CHECK20-NEXT: [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]]) 9589 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 9590 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 9591 // CHECK20-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 9592 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9593 // CHECK20-NEXT: [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]]) 9594 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 9595 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 9596 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 9597 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9598 // CHECK20-NEXT: [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]]) 9599 // CHECK20-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 9600 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 9601 // CHECK20-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 9602 // CHECK20-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 9603 // CHECK20-NEXT: ret i32 [[TMP8]] 9604 // 9605 // 9606 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 9607 // CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 { 9608 // CHECK20-NEXT: entry: 9609 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9610 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9611 // CHECK20-NEXT: [[B:%.*]] = alloca i32, align 4 9612 // CHECK20-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 9613 // CHECK20-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 9614 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 9615 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 9616 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 9617 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 9618 // CHECK20-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 9619 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9620 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9621 // CHECK20-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9622 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 9623 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 9624 // CHECK20-NEXT: store i32 [[ADD]], i32* [[B]], align 4 9625 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 9626 // CHECK20-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 9627 // CHECK20-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 9628 // CHECK20-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 9629 // CHECK20-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 9630 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 9631 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 9632 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 9633 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 9634 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9635 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 9636 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9637 // CHECK20: omp_if.then: 9638 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 9639 // CHECK20-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 9640 // CHECK20-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 9641 // CHECK20-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 9642 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9643 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1** 9644 // CHECK20-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4 9645 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9646 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double** 9647 // CHECK20-NEXT: store double* [[A]], double** [[TMP13]], align 4 9648 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 9649 // CHECK20-NEXT: store i64 8, i64* [[TMP14]], align 4 9650 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 9651 // CHECK20-NEXT: store i8* null, i8** [[TMP15]], align 4 9652 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 9653 // CHECK20-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 9654 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 9655 // CHECK20-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 9656 // CHECK20-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 9657 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 9658 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1 9659 // CHECK20-NEXT: store i64 4, i64* [[TMP20]], align 4 9660 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 9661 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 9662 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 9663 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32* 9664 // CHECK20-NEXT: store i32 2, i32* [[TMP23]], align 4 9665 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 9666 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* 9667 // CHECK20-NEXT: store i32 2, i32* [[TMP25]], align 4 9668 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2 9669 // CHECK20-NEXT: store i64 4, i64* [[TMP26]], align 4 9670 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 9671 // CHECK20-NEXT: store i8* null, i8** [[TMP27]], align 4 9672 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 9673 // CHECK20-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 9674 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 9675 // CHECK20-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 9676 // CHECK20-NEXT: [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32* 9677 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP31]], align 4 9678 // CHECK20-NEXT: [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 9679 // CHECK20-NEXT: store i64 4, i64* [[TMP32]], align 4 9680 // CHECK20-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 9681 // CHECK20-NEXT: store i8* null, i8** [[TMP33]], align 4 9682 // CHECK20-NEXT: [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 9683 // CHECK20-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16** 9684 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP35]], align 4 9685 // CHECK20-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 9686 // CHECK20-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16** 9687 // CHECK20-NEXT: store i16* [[VLA]], i16** [[TMP37]], align 4 9688 // CHECK20-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 9689 // CHECK20-NEXT: store i64 [[TMP9]], i64* [[TMP38]], align 4 9690 // CHECK20-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 9691 // CHECK20-NEXT: store i8* null, i8** [[TMP39]], align 4 9692 // CHECK20-NEXT: [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9693 // CHECK20-NEXT: [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9694 // CHECK20-NEXT: [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 9695 // CHECK20-NEXT: [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9696 // CHECK20-NEXT: [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0 9697 // CHECK20-NEXT: br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9698 // CHECK20: omp_offload.failed: 9699 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 9700 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 9701 // CHECK20: omp_offload.cont: 9702 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 9703 // CHECK20: omp_if.else: 9704 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 9705 // CHECK20-NEXT: br label [[OMP_IF_END]] 9706 // CHECK20: omp_if.end: 9707 // CHECK20-NEXT: [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]] 9708 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]] 9709 // CHECK20-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9710 // CHECK20-NEXT: [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 9711 // CHECK20-NEXT: [[CONV:%.*]] = sext i16 [[TMP46]] to i32 9712 // CHECK20-NEXT: [[TMP47:%.*]] = load i32, i32* [[B]], align 4 9713 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]] 9714 // CHECK20-NEXT: [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 9715 // CHECK20-NEXT: call void @llvm.stackrestore(i8* [[TMP48]]) 9716 // CHECK20-NEXT: ret i32 [[ADD3]] 9717 // 9718 // 9719 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici 9720 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] { 9721 // CHECK20-NEXT: entry: 9722 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9723 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 9724 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 9725 // CHECK20-NEXT: [[AAA:%.*]] = alloca i8, align 1 9726 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9727 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9728 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9729 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 9730 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 9731 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 9732 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 9733 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9734 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 9735 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 9736 // CHECK20-NEXT: store i8 0, i8* [[AAA]], align 1 9737 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9738 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9739 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9740 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 9741 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9742 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 9743 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9744 // CHECK20-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 9745 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 9746 // CHECK20-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 9747 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 9748 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 9749 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 9750 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9751 // CHECK20: omp_if.then: 9752 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9753 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 9754 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 9755 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9756 // CHECK20-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 9757 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 9758 // CHECK20-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 9759 // CHECK20-NEXT: store i8* null, i8** [[TMP11]], align 4 9760 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 9761 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 9762 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 9763 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 9764 // CHECK20-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 9765 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 9766 // CHECK20-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 9767 // CHECK20-NEXT: store i8* null, i8** [[TMP16]], align 4 9768 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 9769 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 9770 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 9771 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 9772 // CHECK20-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 9773 // CHECK20-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 9774 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 9775 // CHECK20-NEXT: store i8* null, i8** [[TMP21]], align 4 9776 // CHECK20-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 9777 // CHECK20-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 9778 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 9779 // CHECK20-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 9780 // CHECK20-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 9781 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 9782 // CHECK20-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 9783 // CHECK20-NEXT: store i8* null, i8** [[TMP26]], align 4 9784 // CHECK20-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9785 // CHECK20-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9786 // CHECK20-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9787 // CHECK20-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 9788 // CHECK20-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9789 // CHECK20: omp_offload.failed: 9790 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 9791 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 9792 // CHECK20: omp_offload.cont: 9793 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 9794 // CHECK20: omp_if.else: 9795 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 9796 // CHECK20-NEXT: br label [[OMP_IF_END]] 9797 // CHECK20: omp_if.end: 9798 // CHECK20-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 9799 // CHECK20-NEXT: ret i32 [[TMP31]] 9800 // 9801 // 9802 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 9803 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat { 9804 // CHECK20-NEXT: entry: 9805 // CHECK20-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 9806 // CHECK20-NEXT: [[A:%.*]] = alloca i32, align 4 9807 // CHECK20-NEXT: [[AA:%.*]] = alloca i16, align 2 9808 // CHECK20-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 9809 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9810 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9811 // CHECK20-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 9812 // CHECK20-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 9813 // CHECK20-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 9814 // CHECK20-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 9815 // CHECK20-NEXT: store i32 0, i32* [[A]], align 4 9816 // CHECK20-NEXT: store i16 0, i16* [[AA]], align 2 9817 // CHECK20-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 9818 // CHECK20-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 9819 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 9820 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 9821 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9822 // CHECK20-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 9823 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9824 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 9825 // CHECK20-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 9826 // CHECK20-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 9827 // CHECK20: omp_if.then: 9828 // CHECK20-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9829 // CHECK20-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 9830 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 9831 // CHECK20-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9832 // CHECK20-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 9833 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 9834 // CHECK20-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 9835 // CHECK20-NEXT: store i8* null, i8** [[TMP9]], align 4 9836 // CHECK20-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 9837 // CHECK20-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 9838 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 9839 // CHECK20-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 9840 // CHECK20-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 9841 // CHECK20-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 9842 // CHECK20-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 9843 // CHECK20-NEXT: store i8* null, i8** [[TMP14]], align 4 9844 // CHECK20-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 9845 // CHECK20-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 9846 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 9847 // CHECK20-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 9848 // CHECK20-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 9849 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 9850 // CHECK20-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 9851 // CHECK20-NEXT: store i8* null, i8** [[TMP19]], align 4 9852 // CHECK20-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 9853 // CHECK20-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 9854 // CHECK20-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 9855 // CHECK20-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 9856 // CHECK20-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 9857 // CHECK20: omp_offload.failed: 9858 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 9859 // CHECK20-NEXT: br label [[OMP_OFFLOAD_CONT]] 9860 // CHECK20: omp_offload.cont: 9861 // CHECK20-NEXT: br label [[OMP_IF_END:%.*]] 9862 // CHECK20: omp_if.else: 9863 // CHECK20-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 9864 // CHECK20-NEXT: br label [[OMP_IF_END]] 9865 // CHECK20: omp_if.end: 9866 // CHECK20-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 9867 // CHECK20-NEXT: ret i32 [[TMP24]] 9868 // 9869 // 9870 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 9871 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 9872 // CHECK20-NEXT: entry: 9873 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9874 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 9875 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9876 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9877 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 9878 // CHECK20-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 9879 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9880 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 9881 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9882 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9883 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 9884 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9885 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9886 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9887 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 9888 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 9889 // CHECK20-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 9890 // CHECK20-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 9891 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 9892 // CHECK20-NEXT: ret void 9893 // 9894 // 9895 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9 9896 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 9897 // CHECK20-NEXT: entry: 9898 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9899 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9900 // CHECK20-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 9901 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 9902 // CHECK20-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 9903 // CHECK20-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 9904 // CHECK20-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 9905 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9906 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9907 // CHECK20-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 9908 // CHECK20-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 9909 // CHECK20-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 9910 // CHECK20-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 9911 // CHECK20-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 9912 // CHECK20-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 9913 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 9914 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 9915 // CHECK20-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 9916 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 9917 // CHECK20-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 9918 // CHECK20-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 9919 // CHECK20-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 9920 // CHECK20-NEXT: store double [[ADD]], double* [[A]], align 4 9921 // CHECK20-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 9922 // CHECK20-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 9923 // CHECK20-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 9924 // CHECK20-NEXT: store double [[INC]], double* [[A3]], align 4 9925 // CHECK20-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 9926 // CHECK20-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 9927 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 9928 // CHECK20-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 9929 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 9930 // CHECK20-NEXT: ret void 9931 // 9932 // 9933 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 9934 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 9935 // CHECK20-NEXT: entry: 9936 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9937 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9938 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 9939 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9940 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 9941 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 9942 // CHECK20-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 9943 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9944 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9945 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 9946 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9947 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9948 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 9949 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9950 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9951 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 9952 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 9953 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 9954 // CHECK20-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 9955 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 9956 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 9957 // CHECK20-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 9958 // CHECK20-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 9959 // CHECK20-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 9960 // CHECK20-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 9961 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 9962 // CHECK20-NEXT: ret void 9963 // 9964 // 9965 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11 9966 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 9967 // CHECK20-NEXT: entry: 9968 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 9969 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 9970 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 9971 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 9972 // CHECK20-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 9973 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 9974 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 9975 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 9976 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 9977 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 9978 // CHECK20-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 9979 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 9980 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 9981 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 9982 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 9983 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 9984 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 9985 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 9986 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 9987 // CHECK20-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 9988 // CHECK20-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 9989 // CHECK20-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 9990 // CHECK20-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 9991 // CHECK20-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 9992 // CHECK20-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 9993 // CHECK20-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 9994 // CHECK20-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 9995 // CHECK20-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 9996 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 9997 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 9998 // CHECK20-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 9999 // CHECK20-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 10000 // CHECK20-NEXT: ret void 10001 // 10002 // 10003 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 10004 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 10005 // CHECK20-NEXT: entry: 10006 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10007 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10008 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10009 // CHECK20-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10010 // CHECK20-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10011 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10012 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10013 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10014 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10015 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10016 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10017 // CHECK20-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 10018 // CHECK20-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 10019 // CHECK20-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 10020 // CHECK20-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10021 // CHECK20-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 10022 // CHECK20-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10023 // CHECK20-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 10024 // CHECK20-NEXT: ret void 10025 // 10026 // 10027 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14 10028 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 10029 // CHECK20-NEXT: entry: 10030 // CHECK20-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10031 // CHECK20-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10032 // CHECK20-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10033 // CHECK20-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10034 // CHECK20-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 10035 // CHECK20-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10036 // CHECK20-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10037 // CHECK20-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10038 // CHECK20-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10039 // CHECK20-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 10040 // CHECK20-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10041 // CHECK20-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 10042 // CHECK20-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 10043 // CHECK20-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10044 // CHECK20-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 10045 // CHECK20-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 10046 // CHECK20-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 10047 // CHECK20-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 10048 // CHECK20-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 10049 // CHECK20-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 10050 // CHECK20-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 10051 // CHECK20-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10052 // CHECK20-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 10053 // CHECK20-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 10054 // CHECK20-NEXT: ret void 10055 // 10056 // 10057 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 10058 // CHECK20-SAME: () #[[ATTR7:[0-9]+]] { 10059 // CHECK20-NEXT: entry: 10060 // CHECK20-NEXT: call void @__tgt_register_requires(i64 1) 10061 // CHECK20-NEXT: ret void 10062 // 10063 // 10064 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 10065 // CHECK25-SAME: () #[[ATTR0:[0-9]+]] { 10066 // CHECK25-NEXT: entry: 10067 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10068 // CHECK25-NEXT: ret void 10069 // 10070 // 10071 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined. 10072 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10073 // CHECK25-NEXT: entry: 10074 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10075 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10076 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10077 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10078 // CHECK25-NEXT: ret void 10079 // 10080 // 10081 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 10082 // CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 10083 // CHECK25-NEXT: entry: 10084 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10085 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10086 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10087 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10088 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10089 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10090 // CHECK25-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 10091 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10092 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 10093 // CHECK25-NEXT: ret void 10094 // 10095 // 10096 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1 10097 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { 10098 // CHECK25-NEXT: entry: 10099 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10100 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10101 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10102 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10103 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10104 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10105 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10106 // CHECK25-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10107 // CHECK25-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 10108 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 10109 // CHECK25-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 10110 // CHECK25-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 10111 // CHECK25-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10112 // CHECK25-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10113 // CHECK25-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 10114 // CHECK25-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 10115 // CHECK25-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 10116 // CHECK25: .cancel.exit: 10117 // CHECK25-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 10118 // CHECK25-NEXT: br label [[DOTCANCEL_CONTINUE]] 10119 // CHECK25: .cancel.continue: 10120 // CHECK25-NEXT: ret void 10121 // 10122 // 10123 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 10124 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 10125 // CHECK25-NEXT: entry: 10126 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10127 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10128 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10129 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10130 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10131 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10132 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10133 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10134 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10135 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10136 // CHECK25-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 10137 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10138 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10139 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10140 // CHECK25-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 10141 // CHECK25-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10142 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 10143 // CHECK25-NEXT: ret void 10144 // 10145 // 10146 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2 10147 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { 10148 // CHECK25-NEXT: entry: 10149 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10150 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10151 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10152 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10153 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10154 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10155 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10156 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10157 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10158 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10159 // CHECK25-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10160 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10161 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10162 // CHECK25-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 10163 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 10164 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10165 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10166 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 10167 // CHECK25-NEXT: ret void 10168 // 10169 // 10170 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 10171 // CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 10172 // CHECK25-NEXT: entry: 10173 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10174 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10175 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10176 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10177 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10178 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10179 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10180 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10181 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10182 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10183 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10184 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10185 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10186 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10187 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10188 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10189 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10190 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10191 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10192 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10193 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10194 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10195 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10196 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10197 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10198 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10199 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10200 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10201 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10202 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10203 // CHECK25-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 10204 // CHECK25-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 10205 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 10206 // CHECK25-NEXT: ret void 10207 // 10208 // 10209 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3 10210 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 10211 // CHECK25-NEXT: entry: 10212 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10213 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10214 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10215 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10216 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10217 // CHECK25-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10218 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10219 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10220 // CHECK25-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10221 // CHECK25-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10222 // CHECK25-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10223 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10224 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10225 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10226 // CHECK25-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10227 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10228 // CHECK25-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10229 // CHECK25-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10230 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10231 // CHECK25-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10232 // CHECK25-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10233 // CHECK25-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10234 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10235 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10236 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10237 // CHECK25-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10238 // CHECK25-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10239 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10240 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10241 // CHECK25-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10242 // CHECK25-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10243 // CHECK25-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10244 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 10245 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10246 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 10247 // CHECK25-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 10248 // CHECK25-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 10249 // CHECK25-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 10250 // CHECK25-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 10251 // CHECK25-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 10252 // CHECK25-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 10253 // CHECK25-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 10254 // CHECK25-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 10255 // CHECK25-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 10256 // CHECK25-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 10257 // CHECK25-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 10258 // CHECK25-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 10259 // CHECK25-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 10260 // CHECK25-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 10261 // CHECK25-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 10262 // CHECK25-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 10263 // CHECK25-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 10264 // CHECK25-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 10265 // CHECK25-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 10266 // CHECK25-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 10267 // CHECK25-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 10268 // CHECK25-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 10269 // CHECK25-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10270 // CHECK25-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 10271 // CHECK25-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 10272 // CHECK25-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 10273 // CHECK25-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10274 // CHECK25-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 10275 // CHECK25-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 10276 // CHECK25-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 10277 // CHECK25-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 10278 // CHECK25-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 10279 // CHECK25-NEXT: ret void 10280 // 10281 // 10282 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 10283 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10284 // CHECK25-NEXT: entry: 10285 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10286 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10287 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10288 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10289 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10290 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10291 // CHECK25-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 10292 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10293 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10294 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10295 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10296 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10297 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10298 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10299 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10300 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10301 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10302 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 10303 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10304 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10305 // CHECK25-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10306 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 10307 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10308 // CHECK25-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 10309 // CHECK25-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 10310 // CHECK25-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 10311 // CHECK25-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 10312 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 10313 // CHECK25-NEXT: ret void 10314 // 10315 // 10316 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4 10317 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10318 // CHECK25-NEXT: entry: 10319 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10320 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10321 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10322 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10323 // CHECK25-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10324 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10325 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10326 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10327 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10328 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10329 // CHECK25-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10330 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10331 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10332 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10333 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10334 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10335 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10336 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10337 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10338 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10339 // CHECK25-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 10340 // CHECK25-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10341 // CHECK25-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10342 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 10343 // CHECK25-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 10344 // CHECK25-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 10345 // CHECK25-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 10346 // CHECK25-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 10347 // CHECK25-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 10348 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10349 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10350 // CHECK25-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 10351 // CHECK25-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 10352 // CHECK25-NEXT: ret void 10353 // 10354 // 10355 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 10356 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10357 // CHECK25-NEXT: entry: 10358 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10359 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10360 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10361 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10362 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10363 // CHECK25-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10364 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10365 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10366 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10367 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10368 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10369 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10370 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10371 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10372 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10373 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10374 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10375 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10376 // CHECK25-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 10377 // CHECK25-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 10378 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 10379 // CHECK25-NEXT: ret void 10380 // 10381 // 10382 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5 10383 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10384 // CHECK25-NEXT: entry: 10385 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10386 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10387 // CHECK25-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10388 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10389 // CHECK25-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10390 // CHECK25-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10391 // CHECK25-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10392 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10393 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10394 // CHECK25-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10395 // CHECK25-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10396 // CHECK25-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10397 // CHECK25-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10398 // CHECK25-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10399 // CHECK25-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10400 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10401 // CHECK25-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10402 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10403 // CHECK25-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10404 // CHECK25-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10405 // CHECK25-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 10406 // CHECK25-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 10407 // CHECK25-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 10408 // CHECK25-NEXT: store double [[ADD]], double* [[A]], align 8 10409 // CHECK25-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 10410 // CHECK25-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 10411 // CHECK25-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 10412 // CHECK25-NEXT: store double [[INC]], double* [[A4]], align 8 10413 // CHECK25-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10414 // CHECK25-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 10415 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 10416 // CHECK25-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 10417 // CHECK25-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 10418 // CHECK25-NEXT: ret void 10419 // 10420 // 10421 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 10422 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10423 // CHECK25-NEXT: entry: 10424 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10425 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10426 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10427 // CHECK25-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10428 // CHECK25-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10429 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10430 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10431 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10432 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10433 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10434 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10435 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10436 // CHECK25-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10437 // CHECK25-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 10438 // CHECK25-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10439 // CHECK25-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10440 // CHECK25-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10441 // CHECK25-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 10442 // CHECK25-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10443 // CHECK25-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 10444 // CHECK25-NEXT: ret void 10445 // 10446 // 10447 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6 10448 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10449 // CHECK25-NEXT: entry: 10450 // CHECK25-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10451 // CHECK25-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10452 // CHECK25-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10453 // CHECK25-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10454 // CHECK25-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10455 // CHECK25-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10456 // CHECK25-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10457 // CHECK25-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10458 // CHECK25-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10459 // CHECK25-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10460 // CHECK25-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10461 // CHECK25-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10462 // CHECK25-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10463 // CHECK25-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10464 // CHECK25-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10465 // CHECK25-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10466 // CHECK25-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10467 // CHECK25-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 10468 // CHECK25-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10469 // CHECK25-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10470 // CHECK25-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 10471 // CHECK25-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10472 // CHECK25-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10473 // CHECK25-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 10474 // CHECK25-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 10475 // CHECK25-NEXT: ret void 10476 // 10477 // 10478 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 10479 // CHECK26-SAME: () #[[ATTR0:[0-9]+]] { 10480 // CHECK26-NEXT: entry: 10481 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10482 // CHECK26-NEXT: ret void 10483 // 10484 // 10485 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined. 10486 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10487 // CHECK26-NEXT: entry: 10488 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10489 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10490 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10491 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10492 // CHECK26-NEXT: ret void 10493 // 10494 // 10495 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 10496 // CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] { 10497 // CHECK26-NEXT: entry: 10498 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10499 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10500 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10501 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10502 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10503 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10504 // CHECK26-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 10505 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10506 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 10507 // CHECK26-NEXT: ret void 10508 // 10509 // 10510 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1 10511 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { 10512 // CHECK26-NEXT: entry: 10513 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10514 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10515 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10516 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10517 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10518 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10519 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10520 // CHECK26-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10521 // CHECK26-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 10522 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 10523 // CHECK26-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 10524 // CHECK26-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 10525 // CHECK26-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 10526 // CHECK26-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10527 // CHECK26-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 10528 // CHECK26-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 10529 // CHECK26-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 10530 // CHECK26: .cancel.exit: 10531 // CHECK26-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 10532 // CHECK26-NEXT: br label [[DOTCANCEL_CONTINUE]] 10533 // CHECK26: .cancel.continue: 10534 // CHECK26-NEXT: ret void 10535 // 10536 // 10537 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 10538 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] { 10539 // CHECK26-NEXT: entry: 10540 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10541 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10542 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10543 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10544 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10545 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10546 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10547 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10548 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10549 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10550 // CHECK26-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 10551 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 10552 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10553 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10554 // CHECK26-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 10555 // CHECK26-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10556 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 10557 // CHECK26-NEXT: ret void 10558 // 10559 // 10560 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2 10561 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR1]] { 10562 // CHECK26-NEXT: entry: 10563 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10564 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10565 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10566 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10567 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10568 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10569 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10570 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10571 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10572 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10573 // CHECK26-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 10574 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10575 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10576 // CHECK26-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 10577 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 10578 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10579 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10580 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 10581 // CHECK26-NEXT: ret void 10582 // 10583 // 10584 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 10585 // CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 10586 // CHECK26-NEXT: entry: 10587 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10588 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10589 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10590 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10591 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10592 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10593 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10594 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10595 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10596 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10597 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10598 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10599 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10600 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10601 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10602 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10603 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10604 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10605 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10606 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10607 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10608 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10609 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10610 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10611 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10612 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10613 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10614 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10615 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10616 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10617 // CHECK26-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 10618 // CHECK26-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 10619 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 10620 // CHECK26-NEXT: ret void 10621 // 10622 // 10623 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3 10624 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 10625 // CHECK26-NEXT: entry: 10626 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10627 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10628 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10629 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 10630 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10631 // CHECK26-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 10632 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 10633 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10634 // CHECK26-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 10635 // CHECK26-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 10636 // CHECK26-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 10637 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10638 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10639 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10640 // CHECK26-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 10641 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10642 // CHECK26-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 10643 // CHECK26-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 10644 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10645 // CHECK26-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 10646 // CHECK26-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 10647 // CHECK26-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 10648 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10649 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 10650 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10651 // CHECK26-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 10652 // CHECK26-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 10653 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10654 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 10655 // CHECK26-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 10656 // CHECK26-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 10657 // CHECK26-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 10658 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 10659 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10660 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 10661 // CHECK26-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 10662 // CHECK26-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 10663 // CHECK26-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 10664 // CHECK26-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 10665 // CHECK26-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 10666 // CHECK26-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 10667 // CHECK26-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 10668 // CHECK26-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 10669 // CHECK26-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 10670 // CHECK26-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 10671 // CHECK26-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 10672 // CHECK26-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 10673 // CHECK26-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 10674 // CHECK26-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 10675 // CHECK26-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 10676 // CHECK26-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 10677 // CHECK26-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 10678 // CHECK26-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 10679 // CHECK26-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 10680 // CHECK26-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 10681 // CHECK26-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 10682 // CHECK26-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 10683 // CHECK26-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 10684 // CHECK26-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 10685 // CHECK26-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 10686 // CHECK26-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 10687 // CHECK26-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 10688 // CHECK26-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 10689 // CHECK26-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 10690 // CHECK26-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 10691 // CHECK26-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 10692 // CHECK26-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 10693 // CHECK26-NEXT: ret void 10694 // 10695 // 10696 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 10697 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10698 // CHECK26-NEXT: entry: 10699 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10700 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10701 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10702 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10703 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10704 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10705 // CHECK26-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 10706 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10707 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10708 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10709 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10710 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10711 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10712 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10713 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10714 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10715 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10716 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 10717 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10718 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10719 // CHECK26-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10720 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 10721 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10722 // CHECK26-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 10723 // CHECK26-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 10724 // CHECK26-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 10725 // CHECK26-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 10726 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 10727 // CHECK26-NEXT: ret void 10728 // 10729 // 10730 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4 10731 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10732 // CHECK26-NEXT: entry: 10733 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10734 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10735 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10736 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10737 // CHECK26-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 10738 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10739 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10740 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10741 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10742 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10743 // CHECK26-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 10744 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10745 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10746 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10747 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 10748 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10749 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10750 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10751 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10752 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10753 // CHECK26-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 10754 // CHECK26-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 10755 // CHECK26-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 10756 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 10757 // CHECK26-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 10758 // CHECK26-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 10759 // CHECK26-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 10760 // CHECK26-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 10761 // CHECK26-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 10762 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10763 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10764 // CHECK26-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 10765 // CHECK26-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 10766 // CHECK26-NEXT: ret void 10767 // 10768 // 10769 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 10770 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 10771 // CHECK26-NEXT: entry: 10772 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10773 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10774 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10775 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10776 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10777 // CHECK26-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 10778 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10779 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10780 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10781 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10782 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10783 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10784 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10785 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10786 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10787 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10788 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10789 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 10790 // CHECK26-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 10791 // CHECK26-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 10792 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 10793 // CHECK26-NEXT: ret void 10794 // 10795 // 10796 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5 10797 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 10798 // CHECK26-NEXT: entry: 10799 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10800 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10801 // CHECK26-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 10802 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 10803 // CHECK26-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 10804 // CHECK26-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 10805 // CHECK26-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 10806 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10807 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10808 // CHECK26-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 10809 // CHECK26-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 10810 // CHECK26-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 10811 // CHECK26-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 10812 // CHECK26-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 10813 // CHECK26-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 10814 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 10815 // CHECK26-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 10816 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 10817 // CHECK26-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 10818 // CHECK26-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 10819 // CHECK26-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 10820 // CHECK26-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 10821 // CHECK26-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 10822 // CHECK26-NEXT: store double [[ADD]], double* [[A]], align 8 10823 // CHECK26-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 10824 // CHECK26-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 10825 // CHECK26-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 10826 // CHECK26-NEXT: store double [[INC]], double* [[A4]], align 8 10827 // CHECK26-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 10828 // CHECK26-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 10829 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 10830 // CHECK26-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 10831 // CHECK26-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 10832 // CHECK26-NEXT: ret void 10833 // 10834 // 10835 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 10836 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 10837 // CHECK26-NEXT: entry: 10838 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10839 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10840 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10841 // CHECK26-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 10842 // CHECK26-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 10843 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10844 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10845 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10846 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10847 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10848 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10849 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10850 // CHECK26-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 10851 // CHECK26-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 10852 // CHECK26-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 10853 // CHECK26-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 10854 // CHECK26-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 10855 // CHECK26-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 10856 // CHECK26-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 10857 // CHECK26-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 10858 // CHECK26-NEXT: ret void 10859 // 10860 // 10861 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6 10862 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 10863 // CHECK26-NEXT: entry: 10864 // CHECK26-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 10865 // CHECK26-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 10866 // CHECK26-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 10867 // CHECK26-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 10868 // CHECK26-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 10869 // CHECK26-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 10870 // CHECK26-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 10871 // CHECK26-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 10872 // CHECK26-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 10873 // CHECK26-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 10874 // CHECK26-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 10875 // CHECK26-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 10876 // CHECK26-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 10877 // CHECK26-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 10878 // CHECK26-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 10879 // CHECK26-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 10880 // CHECK26-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 10881 // CHECK26-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 10882 // CHECK26-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 10883 // CHECK26-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 10884 // CHECK26-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 10885 // CHECK26-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 10886 // CHECK26-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 10887 // CHECK26-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 10888 // CHECK26-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 10889 // CHECK26-NEXT: ret void 10890 // 10891 // 10892 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 10893 // CHECK27-SAME: () #[[ATTR0:[0-9]+]] { 10894 // CHECK27-NEXT: entry: 10895 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 10896 // CHECK27-NEXT: ret void 10897 // 10898 // 10899 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined. 10900 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 10901 // CHECK27-NEXT: entry: 10902 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10903 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10904 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10905 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10906 // CHECK27-NEXT: ret void 10907 // 10908 // 10909 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 10910 // CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 10911 // CHECK27-NEXT: entry: 10912 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10913 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10914 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10915 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10916 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10917 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10918 // CHECK27-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 10919 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10920 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 10921 // CHECK27-NEXT: ret void 10922 // 10923 // 10924 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1 10925 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { 10926 // CHECK27-NEXT: entry: 10927 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10928 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10929 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10930 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10931 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10932 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10933 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10934 // CHECK27-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 10935 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 10936 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 10937 // CHECK27-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 10938 // CHECK27-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 10939 // CHECK27-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 10940 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 10941 // CHECK27-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 10942 // CHECK27-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 10943 // CHECK27-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 10944 // CHECK27: .cancel.exit: 10945 // CHECK27-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 10946 // CHECK27-NEXT: br label [[DOTCANCEL_CONTINUE]] 10947 // CHECK27: .cancel.continue: 10948 // CHECK27-NEXT: ret void 10949 // 10950 // 10951 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 10952 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 10953 // CHECK27-NEXT: entry: 10954 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10955 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10956 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 10957 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 10958 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10959 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10960 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10961 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 10962 // CHECK27-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 10963 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 10964 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 10965 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 10966 // CHECK27-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 10967 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 10968 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 10969 // CHECK27-NEXT: ret void 10970 // 10971 // 10972 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2 10973 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { 10974 // CHECK27-NEXT: entry: 10975 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 10976 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 10977 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10978 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 10979 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 10980 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 10981 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 10982 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 10983 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 10984 // CHECK27-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 10985 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 10986 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 10987 // CHECK27-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 10988 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 10989 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 10990 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 10991 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 10992 // CHECK27-NEXT: ret void 10993 // 10994 // 10995 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 10996 // CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 10997 // CHECK27-NEXT: entry: 10998 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 10999 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11000 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11001 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11002 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11003 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11004 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11005 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11006 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11007 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11008 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11009 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11010 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11011 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11012 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11013 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11014 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11015 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11016 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11017 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11018 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11019 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11020 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11021 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11022 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11023 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11024 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11025 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 11026 // CHECK27-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 11027 // CHECK27-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 11028 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 11029 // CHECK27-NEXT: ret void 11030 // 11031 // 11032 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3 11033 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 11034 // CHECK27-NEXT: entry: 11035 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11036 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11037 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11038 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11039 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11040 // CHECK27-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11041 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11042 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11043 // CHECK27-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11044 // CHECK27-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11045 // CHECK27-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11046 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11047 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11048 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11049 // CHECK27-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11050 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11051 // CHECK27-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11052 // CHECK27-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11053 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11054 // CHECK27-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11055 // CHECK27-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11056 // CHECK27-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11057 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11058 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11059 // CHECK27-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11060 // CHECK27-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11061 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11062 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11063 // CHECK27-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11064 // CHECK27-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11065 // CHECK27-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 11066 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 11067 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11068 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 11069 // CHECK27-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 11070 // CHECK27-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 11071 // CHECK27-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 11072 // CHECK27-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 11073 // CHECK27-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 11074 // CHECK27-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 11075 // CHECK27-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 11076 // CHECK27-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 11077 // CHECK27-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 11078 // CHECK27-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 11079 // CHECK27-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 11080 // CHECK27-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 11081 // CHECK27-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 11082 // CHECK27-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 11083 // CHECK27-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 11084 // CHECK27-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 11085 // CHECK27-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 11086 // CHECK27-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 11087 // CHECK27-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 11088 // CHECK27-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 11089 // CHECK27-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 11090 // CHECK27-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 11091 // CHECK27-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 11092 // CHECK27-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 11093 // CHECK27-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 11094 // CHECK27-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 11095 // CHECK27-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 11096 // CHECK27-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 11097 // CHECK27-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 11098 // CHECK27-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 11099 // CHECK27-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 11100 // CHECK27-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 11101 // CHECK27-NEXT: ret void 11102 // 11103 // 11104 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 11105 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11106 // CHECK27-NEXT: entry: 11107 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11108 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11109 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11110 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11111 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11112 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11113 // CHECK27-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 11114 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11115 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11116 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11117 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11118 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11119 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11120 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11121 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11122 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11123 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11124 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11125 // CHECK27-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11126 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 11127 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11128 // CHECK27-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 11129 // CHECK27-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 11130 // CHECK27-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 11131 // CHECK27-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 11132 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 11133 // CHECK27-NEXT: ret void 11134 // 11135 // 11136 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4 11137 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11138 // CHECK27-NEXT: entry: 11139 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11140 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11141 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11142 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11143 // CHECK27-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11144 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11145 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11146 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11147 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11148 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11149 // CHECK27-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11150 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11151 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11152 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11153 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11154 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11155 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11156 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11157 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11158 // CHECK27-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 11159 // CHECK27-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 11160 // CHECK27-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11161 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 11162 // CHECK27-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 11163 // CHECK27-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 11164 // CHECK27-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 11165 // CHECK27-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 11166 // CHECK27-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 11167 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11168 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11169 // CHECK27-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 11170 // CHECK27-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 11171 // CHECK27-NEXT: ret void 11172 // 11173 // 11174 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 11175 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 11176 // CHECK27-NEXT: entry: 11177 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11178 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11179 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11180 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11181 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11182 // CHECK27-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 11183 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11184 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11185 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11186 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11187 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11188 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11189 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11190 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11191 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11192 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11193 // CHECK27-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 11194 // CHECK27-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 11195 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 11196 // CHECK27-NEXT: ret void 11197 // 11198 // 11199 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5 11200 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 11201 // CHECK27-NEXT: entry: 11202 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11203 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11204 // CHECK27-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11205 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11206 // CHECK27-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11207 // CHECK27-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11208 // CHECK27-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11209 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11210 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11211 // CHECK27-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11212 // CHECK27-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11213 // CHECK27-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11214 // CHECK27-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11215 // CHECK27-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11216 // CHECK27-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11217 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11218 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11219 // CHECK27-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11220 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11221 // CHECK27-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 11222 // CHECK27-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 11223 // CHECK27-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11224 // CHECK27-NEXT: store double [[ADD]], double* [[A]], align 4 11225 // CHECK27-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11226 // CHECK27-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 11227 // CHECK27-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 11228 // CHECK27-NEXT: store double [[INC]], double* [[A3]], align 4 11229 // CHECK27-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 11230 // CHECK27-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 11231 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 11232 // CHECK27-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 11233 // CHECK27-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 11234 // CHECK27-NEXT: ret void 11235 // 11236 // 11237 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 11238 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11239 // CHECK27-NEXT: entry: 11240 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11241 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11242 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11243 // CHECK27-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11244 // CHECK27-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11245 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11246 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11247 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11248 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11249 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11250 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11251 // CHECK27-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11252 // CHECK27-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11253 // CHECK27-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11254 // CHECK27-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11255 // CHECK27-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 11256 // CHECK27-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11257 // CHECK27-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 11258 // CHECK27-NEXT: ret void 11259 // 11260 // 11261 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6 11262 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11263 // CHECK27-NEXT: entry: 11264 // CHECK27-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11265 // CHECK27-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11266 // CHECK27-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11267 // CHECK27-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11268 // CHECK27-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11269 // CHECK27-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11270 // CHECK27-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11271 // CHECK27-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11272 // CHECK27-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11273 // CHECK27-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11274 // CHECK27-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11275 // CHECK27-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11276 // CHECK27-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11277 // CHECK27-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11278 // CHECK27-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11279 // CHECK27-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11280 // CHECK27-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 11281 // CHECK27-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 11282 // CHECK27-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 11283 // CHECK27-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 11284 // CHECK27-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11285 // CHECK27-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11286 // CHECK27-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 11287 // CHECK27-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 11288 // CHECK27-NEXT: ret void 11289 // 11290 // 11291 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 11292 // CHECK28-SAME: () #[[ATTR0:[0-9]+]] { 11293 // CHECK28-NEXT: entry: 11294 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 11295 // CHECK28-NEXT: ret void 11296 // 11297 // 11298 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined. 11299 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 11300 // CHECK28-NEXT: entry: 11301 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11302 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11303 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11304 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11305 // CHECK28-NEXT: ret void 11306 // 11307 // 11308 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 11309 // CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] { 11310 // CHECK28-NEXT: entry: 11311 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11312 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11313 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11314 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11315 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 11316 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11317 // CHECK28-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 11318 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11319 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 11320 // CHECK28-NEXT: ret void 11321 // 11322 // 11323 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1 11324 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { 11325 // CHECK28-NEXT: entry: 11326 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11327 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11328 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11329 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11330 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11331 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11332 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11333 // CHECK28-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 11334 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 11335 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 11336 // CHECK28-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 11337 // CHECK28-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 11338 // CHECK28-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 11339 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 11340 // CHECK28-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 11341 // CHECK28-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 11342 // CHECK28-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 11343 // CHECK28: .cancel.exit: 11344 // CHECK28-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 11345 // CHECK28-NEXT: br label [[DOTCANCEL_CONTINUE]] 11346 // CHECK28: .cancel.continue: 11347 // CHECK28-NEXT: ret void 11348 // 11349 // 11350 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 11351 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] { 11352 // CHECK28-NEXT: entry: 11353 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11354 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11355 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11356 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11357 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11358 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11359 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11360 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11361 // CHECK28-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 11362 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 11363 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11364 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11365 // CHECK28-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 11366 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11367 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 11368 // CHECK28-NEXT: ret void 11369 // 11370 // 11371 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2 11372 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR1]] { 11373 // CHECK28-NEXT: entry: 11374 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11375 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11376 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11377 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11378 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11379 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11380 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11381 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11382 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11383 // CHECK28-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 11384 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 11385 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11386 // CHECK28-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 11387 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 11388 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 11389 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 11390 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 11391 // CHECK28-NEXT: ret void 11392 // 11393 // 11394 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 11395 // CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 11396 // CHECK28-NEXT: entry: 11397 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11398 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11399 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11400 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11401 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11402 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11403 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11404 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11405 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11406 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11407 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11408 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11409 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11410 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11411 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11412 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11413 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11414 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11415 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11416 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11417 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11418 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11419 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11420 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11421 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11422 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11423 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11424 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 11425 // CHECK28-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 11426 // CHECK28-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 11427 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 11428 // CHECK28-NEXT: ret void 11429 // 11430 // 11431 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3 11432 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 11433 // CHECK28-NEXT: entry: 11434 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11435 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11436 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11437 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 11438 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11439 // CHECK28-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 11440 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 11441 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11442 // CHECK28-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 11443 // CHECK28-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 11444 // CHECK28-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 11445 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11446 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11447 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11448 // CHECK28-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 11449 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11450 // CHECK28-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 11451 // CHECK28-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 11452 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11453 // CHECK28-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 11454 // CHECK28-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 11455 // CHECK28-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 11456 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 11457 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11458 // CHECK28-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 11459 // CHECK28-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 11460 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11461 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 11462 // CHECK28-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 11463 // CHECK28-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 11464 // CHECK28-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 11465 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 11466 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11467 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 11468 // CHECK28-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 11469 // CHECK28-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 11470 // CHECK28-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 11471 // CHECK28-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 11472 // CHECK28-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 11473 // CHECK28-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 11474 // CHECK28-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 11475 // CHECK28-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 11476 // CHECK28-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 11477 // CHECK28-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 11478 // CHECK28-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 11479 // CHECK28-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 11480 // CHECK28-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 11481 // CHECK28-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 11482 // CHECK28-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 11483 // CHECK28-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 11484 // CHECK28-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 11485 // CHECK28-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 11486 // CHECK28-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 11487 // CHECK28-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 11488 // CHECK28-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 11489 // CHECK28-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 11490 // CHECK28-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 11491 // CHECK28-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 11492 // CHECK28-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 11493 // CHECK28-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 11494 // CHECK28-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 11495 // CHECK28-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 11496 // CHECK28-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 11497 // CHECK28-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 11498 // CHECK28-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 11499 // CHECK28-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 11500 // CHECK28-NEXT: ret void 11501 // 11502 // 11503 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 11504 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11505 // CHECK28-NEXT: entry: 11506 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11507 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11508 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11509 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11510 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11511 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11512 // CHECK28-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 11513 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11514 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11515 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11516 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11517 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11518 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11519 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11520 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11521 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11522 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11523 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11524 // CHECK28-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11525 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 11526 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11527 // CHECK28-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 11528 // CHECK28-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 11529 // CHECK28-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 11530 // CHECK28-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 11531 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 11532 // CHECK28-NEXT: ret void 11533 // 11534 // 11535 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4 11536 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11537 // CHECK28-NEXT: entry: 11538 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11539 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11540 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11541 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11542 // CHECK28-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 11543 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11544 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11545 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11546 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11547 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11548 // CHECK28-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 11549 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11550 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11551 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 11552 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11553 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11554 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11555 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11556 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11557 // CHECK28-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 11558 // CHECK28-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 11559 // CHECK28-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 11560 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 11561 // CHECK28-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 11562 // CHECK28-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 11563 // CHECK28-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 11564 // CHECK28-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 11565 // CHECK28-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 11566 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11567 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11568 // CHECK28-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 11569 // CHECK28-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 11570 // CHECK28-NEXT: ret void 11571 // 11572 // 11573 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 11574 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 11575 // CHECK28-NEXT: entry: 11576 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11577 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11578 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11579 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11580 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11581 // CHECK28-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 11582 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11583 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11584 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11585 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11586 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11587 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11588 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11589 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11590 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11591 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11592 // CHECK28-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 11593 // CHECK28-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 11594 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 11595 // CHECK28-NEXT: ret void 11596 // 11597 // 11598 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5 11599 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 11600 // CHECK28-NEXT: entry: 11601 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11602 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11603 // CHECK28-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 11604 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 11605 // CHECK28-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 11606 // CHECK28-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 11607 // CHECK28-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 11608 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11609 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11610 // CHECK28-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 11611 // CHECK28-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 11612 // CHECK28-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 11613 // CHECK28-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 11614 // CHECK28-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 11615 // CHECK28-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 11616 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 11617 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 11618 // CHECK28-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 11619 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 11620 // CHECK28-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 11621 // CHECK28-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 11622 // CHECK28-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 11623 // CHECK28-NEXT: store double [[ADD]], double* [[A]], align 4 11624 // CHECK28-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 11625 // CHECK28-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 11626 // CHECK28-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 11627 // CHECK28-NEXT: store double [[INC]], double* [[A3]], align 4 11628 // CHECK28-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 11629 // CHECK28-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 11630 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 11631 // CHECK28-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 11632 // CHECK28-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 11633 // CHECK28-NEXT: ret void 11634 // 11635 // 11636 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 11637 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 11638 // CHECK28-NEXT: entry: 11639 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11640 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11641 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11642 // CHECK28-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 11643 // CHECK28-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 11644 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11645 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11646 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11647 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11648 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11649 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11650 // CHECK28-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 11651 // CHECK28-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 11652 // CHECK28-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 11653 // CHECK28-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 11654 // CHECK28-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 11655 // CHECK28-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 11656 // CHECK28-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 11657 // CHECK28-NEXT: ret void 11658 // 11659 // 11660 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6 11661 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 11662 // CHECK28-NEXT: entry: 11663 // CHECK28-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 11664 // CHECK28-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 11665 // CHECK28-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 11666 // CHECK28-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 11667 // CHECK28-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 11668 // CHECK28-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 11669 // CHECK28-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 11670 // CHECK28-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 11671 // CHECK28-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 11672 // CHECK28-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 11673 // CHECK28-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 11674 // CHECK28-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 11675 // CHECK28-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 11676 // CHECK28-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 11677 // CHECK28-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 11678 // CHECK28-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 11679 // CHECK28-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 11680 // CHECK28-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 11681 // CHECK28-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 11682 // CHECK28-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 11683 // CHECK28-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 11684 // CHECK28-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 11685 // CHECK28-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 11686 // CHECK28-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 11687 // CHECK28-NEXT: ret void 11688 // 11689