1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 26 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 40 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 43 44 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 60 61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 8 target regions, but only 6 that actually will generate offloading 78 // code and have mapped arguments, and only 4 have all-constant map sizes. 79 80 81 82 // Check target registration is registered as a Ctor. 83 84 85 template<typename tx, typename ty> 86 struct TT{ 87 tx X; 88 ty Y; 89 }; 90 91 int foo(int n) { 92 int a = 0; 93 short aa = 0; 94 float b[10]; 95 float bn[n]; 96 double c[5][10]; 97 double cn[5][n]; 98 TT<long long, char> d; 99 100 #pragma omp target parallel nowait 101 { 102 } 103 104 #pragma omp target parallel if(target: 0) 105 { 106 a += 1; 107 } 108 109 110 #pragma omp target parallel if(target: 1) 111 { 112 aa += 1; 113 #pragma omp cancel parallel 114 } 115 116 117 118 119 #pragma omp target parallel if(target: n>10) 120 { 121 a += 1; 122 aa += 1; 123 } 124 125 // We capture 3 VLA sizes in this target region 126 127 128 129 130 131 // The names below are not necessarily consistent with the names used for the 132 // addresses above as some are repeated. 133 134 135 136 137 138 139 140 141 142 143 144 #pragma omp target parallel if(target: n>20) 145 { 146 a += 1; 147 b[2] += 1.0; 148 bn[3] += 1.0; 149 c[1][2] += 1.0; 150 cn[1][3] += 1.0; 151 d.X += 1; 152 d.Y += 1; 153 } 154 155 return a; 156 } 157 158 // Check that the offloading functions are emitted and that the arguments are 159 // correct and loaded correctly for the target regions in foo(). 160 161 162 163 // Create stack storage and store argument in there. 164 165 // Create stack storage and store argument in there. 166 167 // Create stack storage and store argument in there. 168 169 // Create local storage for each capture. 170 171 172 173 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 174 175 template<typename tx> 176 tx ftemplate(int n) { 177 tx a = 0; 178 short aa = 0; 179 tx b[10]; 180 181 #pragma omp target parallel if(target: n>40) 182 { 183 a += 1; 184 aa += 1; 185 b[2] += 1; 186 } 187 188 return a; 189 } 190 191 static 192 int fstatic(int n) { 193 int a = 0; 194 short aa = 0; 195 char aaa = 0; 196 int b[10]; 197 198 #pragma omp target parallel if(target: n>50) 199 { 200 a += 1; 201 aa += 1; 202 aaa += 1; 203 b[2] += 1; 204 } 205 206 return a; 207 } 208 209 struct S1 { 210 double a; 211 212 int r1(int n){ 213 int b = n+1; 214 short int c[2][n]; 215 216 #pragma omp target parallel if(target: n>60) 217 { 218 this->a = (double)b + 1.5; 219 c[1][1] = ++a; 220 } 221 222 return c[1][1] + (int)b; 223 } 224 }; 225 226 int bar(int n){ 227 int a = 0; 228 229 a += foo(n); 230 231 S1 S; 232 a += S.r1(n); 233 234 a += fstatic(n); 235 236 a += ftemplate<int>(n); 237 238 return a; 239 } 240 241 242 243 // We capture 2 VLA sizes in this target region 244 245 246 // The names below are not necessarily consistent with the names used for the 247 // addresses above as some are repeated. 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 // Check that the offloading functions are emitted and that the arguments are 268 // correct and loaded correctly for the target regions of the callees of bar(). 269 270 // Create local storage for each capture. 271 // Store captures in the context. 272 273 274 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 275 276 277 // Create local storage for each capture. 278 // Store captures in the context. 279 280 281 282 283 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 284 285 // Create local storage for each capture. 286 // Store captures in the context. 287 288 289 290 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 291 292 293 #endif 294 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 295 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 296 // CHECK1-NEXT: entry: 297 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 300 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 301 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 302 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 303 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 304 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 305 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 306 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 307 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 308 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 309 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 310 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 311 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 312 // CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 315 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 316 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 317 // CHECK1-NEXT: [[A_CASTED13:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS17:%.*]] = alloca [9 x i8*], align 8 319 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS18:%.*]] = alloca [9 x i8*], align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS19:%.*]] = alloca [9 x i8*], align 8 321 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 322 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 323 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 324 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 325 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 326 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 327 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 328 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 329 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 330 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 331 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 332 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 333 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 334 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 335 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 336 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 337 // CHECK1-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 338 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 339 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 340 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 341 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 342 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 343 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 344 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 345 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 346 // CHECK1-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 347 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 348 // CHECK1-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 349 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 350 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 351 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 352 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 353 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 354 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 355 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 356 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 357 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 358 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 359 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 360 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 361 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 362 // CHECK1-NEXT: store i32 1, i32* [[TMP22]], align 4 363 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 364 // CHECK1-NEXT: store i32 1, i32* [[TMP23]], align 4 365 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 366 // CHECK1-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8 367 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 368 // CHECK1-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 8 369 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 370 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP26]], align 8 371 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 372 // CHECK1-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP27]], align 8 373 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 374 // CHECK1-NEXT: store i8** null, i8*** [[TMP28]], align 8 375 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 376 // CHECK1-NEXT: store i8** null, i8*** [[TMP29]], align 8 377 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 378 // CHECK1-NEXT: store i64 0, i64* [[TMP30]], align 8 379 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 380 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 381 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 382 // CHECK1: omp_offload.failed: 383 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 384 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 385 // CHECK1: omp_offload.cont: 386 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4 387 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 388 // CHECK1-NEXT: store i32 [[TMP33]], i32* [[CONV4]], align 4 389 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, i64* [[A_CASTED3]], align 8 390 // CHECK1-NEXT: [[TMP35:%.*]] = load i16, i16* [[AA]], align 2 391 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 392 // CHECK1-NEXT: store i16 [[TMP35]], i16* [[CONV6]], align 2 393 // CHECK1-NEXT: [[TMP36:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 394 // CHECK1-NEXT: [[TMP37:%.*]] = load i32, i32* [[N_ADDR]], align 4 395 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP37]], 10 396 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 397 // CHECK1: omp_if.then: 398 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 399 // CHECK1-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i64* 400 // CHECK1-NEXT: store i64 [[TMP34]], i64* [[TMP39]], align 8 401 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 402 // CHECK1-NEXT: [[TMP41:%.*]] = bitcast i8** [[TMP40]] to i64* 403 // CHECK1-NEXT: store i64 [[TMP34]], i64* [[TMP41]], align 8 404 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 405 // CHECK1-NEXT: store i8* null, i8** [[TMP42]], align 8 406 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 407 // CHECK1-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i64* 408 // CHECK1-NEXT: store i64 [[TMP36]], i64* [[TMP44]], align 8 409 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 410 // CHECK1-NEXT: [[TMP46:%.*]] = bitcast i8** [[TMP45]] to i64* 411 // CHECK1-NEXT: store i64 [[TMP36]], i64* [[TMP46]], align 8 412 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 413 // CHECK1-NEXT: store i8* null, i8** [[TMP47]], align 8 414 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 415 // CHECK1-NEXT: [[TMP49:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 416 // CHECK1-NEXT: [[KERNEL_ARGS10:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 417 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]], i32 0, i32 0 418 // CHECK1-NEXT: store i32 1, i32* [[TMP50]], align 4 419 // CHECK1-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]], i32 0, i32 1 420 // CHECK1-NEXT: store i32 2, i32* [[TMP51]], align 4 421 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]], i32 0, i32 2 422 // CHECK1-NEXT: store i8** [[TMP48]], i8*** [[TMP52]], align 8 423 // CHECK1-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]], i32 0, i32 3 424 // CHECK1-NEXT: store i8** [[TMP49]], i8*** [[TMP53]], align 8 425 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]], i32 0, i32 4 426 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP54]], align 8 427 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]], i32 0, i32 5 428 // CHECK1-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP55]], align 8 429 // CHECK1-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]], i32 0, i32 6 430 // CHECK1-NEXT: store i8** null, i8*** [[TMP56]], align 8 431 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]], i32 0, i32 7 432 // CHECK1-NEXT: store i8** null, i8*** [[TMP57]], align 8 433 // CHECK1-NEXT: [[TMP58:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]], i32 0, i32 8 434 // CHECK1-NEXT: store i64 0, i64* [[TMP58]], align 8 435 // CHECK1-NEXT: [[TMP59:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS10]]) 436 // CHECK1-NEXT: [[TMP60:%.*]] = icmp ne i32 [[TMP59]], 0 437 // CHECK1-NEXT: br i1 [[TMP60]], label [[OMP_OFFLOAD_FAILED11:%.*]], label [[OMP_OFFLOAD_CONT12:%.*]] 438 // CHECK1: omp_offload.failed11: 439 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP34]], i64 [[TMP36]]) #[[ATTR4]] 440 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT12]] 441 // CHECK1: omp_offload.cont12: 442 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 443 // CHECK1: omp_if.else: 444 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP34]], i64 [[TMP36]]) #[[ATTR4]] 445 // CHECK1-NEXT: br label [[OMP_IF_END]] 446 // CHECK1: omp_if.end: 447 // CHECK1-NEXT: [[TMP61:%.*]] = load i32, i32* [[A]], align 4 448 // CHECK1-NEXT: [[CONV14:%.*]] = bitcast i64* [[A_CASTED13]] to i32* 449 // CHECK1-NEXT: store i32 [[TMP61]], i32* [[CONV14]], align 4 450 // CHECK1-NEXT: [[TMP62:%.*]] = load i64, i64* [[A_CASTED13]], align 8 451 // CHECK1-NEXT: [[TMP63:%.*]] = load i32, i32* [[N_ADDR]], align 4 452 // CHECK1-NEXT: [[CMP15:%.*]] = icmp sgt i32 [[TMP63]], 20 453 // CHECK1-NEXT: br i1 [[CMP15]], label [[OMP_IF_THEN16:%.*]], label [[OMP_IF_ELSE23:%.*]] 454 // CHECK1: omp_if.then16: 455 // CHECK1-NEXT: [[TMP64:%.*]] = mul nuw i64 [[TMP2]], 4 456 // CHECK1-NEXT: [[TMP65:%.*]] = mul nuw i64 5, [[TMP5]] 457 // CHECK1-NEXT: [[TMP66:%.*]] = mul nuw i64 [[TMP65]], 8 458 // CHECK1-NEXT: [[TMP67:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 459 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP67]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i64 72, i1 false) 460 // CHECK1-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 461 // CHECK1-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i64* 462 // CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP69]], align 8 463 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 464 // CHECK1-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i64* 465 // CHECK1-NEXT: store i64 [[TMP62]], i64* [[TMP71]], align 8 466 // CHECK1-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i64 0, i64 0 467 // CHECK1-NEXT: store i8* null, i8** [[TMP72]], align 8 468 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 1 469 // CHECK1-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [10 x float]** 470 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP74]], align 8 471 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 1 472 // CHECK1-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [10 x float]** 473 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP76]], align 8 474 // CHECK1-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i64 0, i64 1 475 // CHECK1-NEXT: store i8* null, i8** [[TMP77]], align 8 476 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 2 477 // CHECK1-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 478 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP79]], align 8 479 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 2 480 // CHECK1-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i64* 481 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP81]], align 8 482 // CHECK1-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i64 0, i64 2 483 // CHECK1-NEXT: store i8* null, i8** [[TMP82]], align 8 484 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 3 485 // CHECK1-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to float** 486 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP84]], align 8 487 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 3 488 // CHECK1-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to float** 489 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP86]], align 8 490 // CHECK1-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 491 // CHECK1-NEXT: store i64 [[TMP64]], i64* [[TMP87]], align 8 492 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i64 0, i64 3 493 // CHECK1-NEXT: store i8* null, i8** [[TMP88]], align 8 494 // CHECK1-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 4 495 // CHECK1-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to [5 x [10 x double]]** 496 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP90]], align 8 497 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 4 498 // CHECK1-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to [5 x [10 x double]]** 499 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP92]], align 8 500 // CHECK1-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i64 0, i64 4 501 // CHECK1-NEXT: store i8* null, i8** [[TMP93]], align 8 502 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 5 503 // CHECK1-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to i64* 504 // CHECK1-NEXT: store i64 5, i64* [[TMP95]], align 8 505 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 5 506 // CHECK1-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i64* 507 // CHECK1-NEXT: store i64 5, i64* [[TMP97]], align 8 508 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i64 0, i64 5 509 // CHECK1-NEXT: store i8* null, i8** [[TMP98]], align 8 510 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 6 511 // CHECK1-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i64* 512 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP100]], align 8 513 // CHECK1-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 6 514 // CHECK1-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i64* 515 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP102]], align 8 516 // CHECK1-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i64 0, i64 6 517 // CHECK1-NEXT: store i8* null, i8** [[TMP103]], align 8 518 // CHECK1-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 7 519 // CHECK1-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to double** 520 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP105]], align 8 521 // CHECK1-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 7 522 // CHECK1-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to double** 523 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP107]], align 8 524 // CHECK1-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 525 // CHECK1-NEXT: store i64 [[TMP66]], i64* [[TMP108]], align 8 526 // CHECK1-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i64 0, i64 7 527 // CHECK1-NEXT: store i8* null, i8** [[TMP109]], align 8 528 // CHECK1-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 8 529 // CHECK1-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to %struct.TT** 530 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP111]], align 8 531 // CHECK1-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 8 532 // CHECK1-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to %struct.TT** 533 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP113]], align 8 534 // CHECK1-NEXT: [[TMP114:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS19]], i64 0, i64 8 535 // CHECK1-NEXT: store i8* null, i8** [[TMP114]], align 8 536 // CHECK1-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS17]], i32 0, i32 0 537 // CHECK1-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS18]], i32 0, i32 0 538 // CHECK1-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 539 // CHECK1-NEXT: [[KERNEL_ARGS20:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 540 // CHECK1-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 0 541 // CHECK1-NEXT: store i32 1, i32* [[TMP118]], align 4 542 // CHECK1-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 1 543 // CHECK1-NEXT: store i32 9, i32* [[TMP119]], align 4 544 // CHECK1-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 2 545 // CHECK1-NEXT: store i8** [[TMP115]], i8*** [[TMP120]], align 8 546 // CHECK1-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 3 547 // CHECK1-NEXT: store i8** [[TMP116]], i8*** [[TMP121]], align 8 548 // CHECK1-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 4 549 // CHECK1-NEXT: store i64* [[TMP117]], i64** [[TMP122]], align 8 550 // CHECK1-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 5 551 // CHECK1-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP123]], align 8 552 // CHECK1-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 6 553 // CHECK1-NEXT: store i8** null, i8*** [[TMP124]], align 8 554 // CHECK1-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 7 555 // CHECK1-NEXT: store i8** null, i8*** [[TMP125]], align 8 556 // CHECK1-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]], i32 0, i32 8 557 // CHECK1-NEXT: store i64 0, i64* [[TMP126]], align 8 558 // CHECK1-NEXT: [[TMP127:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS20]]) 559 // CHECK1-NEXT: [[TMP128:%.*]] = icmp ne i32 [[TMP127]], 0 560 // CHECK1-NEXT: br i1 [[TMP128]], label [[OMP_OFFLOAD_FAILED21:%.*]], label [[OMP_OFFLOAD_CONT22:%.*]] 561 // CHECK1: omp_offload.failed21: 562 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP62]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 563 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT22]] 564 // CHECK1: omp_offload.cont22: 565 // CHECK1-NEXT: br label [[OMP_IF_END24:%.*]] 566 // CHECK1: omp_if.else23: 567 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP62]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 568 // CHECK1-NEXT: br label [[OMP_IF_END24]] 569 // CHECK1: omp_if.end24: 570 // CHECK1-NEXT: [[TMP129:%.*]] = load i32, i32* [[A]], align 4 571 // CHECK1-NEXT: [[TMP130:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 572 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP130]]) 573 // CHECK1-NEXT: ret i32 [[TMP129]] 574 // 575 // 576 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 577 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 578 // CHECK1-NEXT: entry: 579 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 580 // CHECK1-NEXT: ret void 581 // 582 // 583 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 584 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 585 // CHECK1-NEXT: entry: 586 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 587 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 588 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 589 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 590 // CHECK1-NEXT: ret void 591 // 592 // 593 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 594 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 595 // CHECK1-NEXT: entry: 596 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 597 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 598 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 599 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 600 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 601 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 602 // CHECK1-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 603 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 604 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 605 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 606 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 607 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 608 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 609 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 610 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 611 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 612 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 613 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 614 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 615 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 616 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 617 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 618 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 619 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 620 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 621 // CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 622 // CHECK1-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 623 // CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 624 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 625 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 626 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0 627 // CHECK1-NEXT: store i32 1, i32* [[TMP11]], align 4, !noalias !21 628 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1 629 // CHECK1-NEXT: store i32 0, i32* [[TMP12]], align 4, !noalias !21 630 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2 631 // CHECK1-NEXT: store i8** null, i8*** [[TMP13]], align 8, !noalias !21 632 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3 633 // CHECK1-NEXT: store i8** null, i8*** [[TMP14]], align 8, !noalias !21 634 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4 635 // CHECK1-NEXT: store i64* null, i64** [[TMP15]], align 8, !noalias !21 636 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5 637 // CHECK1-NEXT: store i64* null, i64** [[TMP16]], align 8, !noalias !21 638 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6 639 // CHECK1-NEXT: store i8** null, i8*** [[TMP17]], align 8, !noalias !21 640 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7 641 // CHECK1-NEXT: store i8** null, i8*** [[TMP18]], align 8, !noalias !21 642 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8 643 // CHECK1-NEXT: store i64 0, i64* [[TMP19]], align 8, !noalias !21 644 // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) 645 // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 646 // CHECK1-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 647 // CHECK1: omp_offload.failed.i: 648 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 649 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 650 // CHECK1: .omp_outlined..1.exit: 651 // CHECK1-NEXT: ret i32 0 652 // 653 // 654 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 655 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 656 // CHECK1-NEXT: entry: 657 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 658 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 659 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 660 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 661 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 662 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 663 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 664 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 665 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 666 // CHECK1-NEXT: ret void 667 // 668 // 669 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 670 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 671 // CHECK1-NEXT: entry: 672 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 673 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 674 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 675 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 676 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 677 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 678 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 679 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 680 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 681 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 682 // CHECK1-NEXT: ret void 683 // 684 // 685 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 686 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 687 // CHECK1-NEXT: entry: 688 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 689 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 690 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 691 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 692 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 693 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 694 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 695 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 696 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 697 // CHECK1-NEXT: ret void 698 // 699 // 700 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 701 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 702 // CHECK1-NEXT: entry: 703 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 704 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 705 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 706 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 707 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 708 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 709 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 710 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 711 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 712 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 713 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 714 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 715 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 716 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 717 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 718 // CHECK1-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 719 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 720 // CHECK1: .cancel.exit: 721 // CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 722 // CHECK1-NEXT: br label [[DOTCANCEL_CONTINUE]] 723 // CHECK1: .cancel.continue: 724 // CHECK1-NEXT: ret void 725 // 726 // 727 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 728 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 729 // CHECK1-NEXT: entry: 730 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 731 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 732 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 733 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 734 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 735 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 736 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 737 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 738 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 739 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 740 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 741 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 742 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 743 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 744 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 745 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 746 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 747 // CHECK1-NEXT: ret void 748 // 749 // 750 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 751 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 752 // CHECK1-NEXT: entry: 753 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 754 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 755 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 756 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 757 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 758 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 759 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 760 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 761 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 762 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 763 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 764 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 765 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 766 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 767 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 768 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 769 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 770 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 771 // CHECK1-NEXT: ret void 772 // 773 // 774 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 775 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 776 // CHECK1-NEXT: entry: 777 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 778 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 779 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 780 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 781 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 782 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 783 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 784 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 785 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 786 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 787 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 788 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 789 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 790 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 791 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 792 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 793 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 794 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 795 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 796 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 797 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 798 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 799 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 800 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 801 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 802 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 803 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 804 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 805 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 806 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 807 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 808 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 809 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 810 // CHECK1-NEXT: ret void 811 // 812 // 813 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 814 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 815 // CHECK1-NEXT: entry: 816 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 817 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 818 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 819 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 820 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 821 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 822 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 823 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 824 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 825 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 826 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 827 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 828 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 829 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 830 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 831 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 832 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 833 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 834 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 835 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 836 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 837 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 838 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 839 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 840 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 841 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 842 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 843 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 844 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 845 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 846 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 847 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 848 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 849 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 850 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 851 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 852 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 853 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 854 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 855 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 856 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 857 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 858 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 859 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 860 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 861 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 862 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 863 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 864 // CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 865 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 866 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 867 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 868 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 869 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 870 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 871 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 872 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 873 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 874 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 875 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 876 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 877 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 878 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 879 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 880 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 881 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 882 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 883 // CHECK1-NEXT: ret void 884 // 885 // 886 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 887 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 888 // CHECK1-NEXT: entry: 889 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 890 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 891 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 892 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 893 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 894 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 895 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 896 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 897 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 898 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 899 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 900 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 901 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 902 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 903 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 904 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 905 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 906 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 907 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 908 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 909 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 910 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 911 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 912 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 913 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 914 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 915 // CHECK1-NEXT: ret i32 [[TMP8]] 916 // 917 // 918 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 919 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 920 // CHECK1-NEXT: entry: 921 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 922 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 923 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 924 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 925 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 926 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 927 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 928 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 929 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 930 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 931 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 932 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 933 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 934 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 935 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 936 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 937 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 938 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 939 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 940 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 941 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 942 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 943 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 944 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 945 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 946 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 947 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 948 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 949 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 950 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 951 // CHECK1: omp_if.then: 952 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 953 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 954 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 955 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 956 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 957 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 958 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 959 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 960 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 961 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 962 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 963 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 964 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 965 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 966 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 967 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 968 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 969 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 970 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 971 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 972 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 973 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 974 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 975 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 976 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 977 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 978 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 979 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 980 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 981 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 982 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 983 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 984 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 985 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 986 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 987 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 988 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 989 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 990 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 991 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 992 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 993 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 994 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 995 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 996 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 997 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 998 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 999 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1000 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1001 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1002 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1003 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1004 // CHECK1-NEXT: store i32 1, i32* [[TMP40]], align 4 1005 // CHECK1-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1006 // CHECK1-NEXT: store i32 5, i32* [[TMP41]], align 4 1007 // CHECK1-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1008 // CHECK1-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 8 1009 // CHECK1-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1010 // CHECK1-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 8 1011 // CHECK1-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1012 // CHECK1-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 8 1013 // CHECK1-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1014 // CHECK1-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP45]], align 8 1015 // CHECK1-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1016 // CHECK1-NEXT: store i8** null, i8*** [[TMP46]], align 8 1017 // CHECK1-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1018 // CHECK1-NEXT: store i8** null, i8*** [[TMP47]], align 8 1019 // CHECK1-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1020 // CHECK1-NEXT: store i64 0, i64* [[TMP48]], align 8 1021 // CHECK1-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1022 // CHECK1-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 1023 // CHECK1-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1024 // CHECK1: omp_offload.failed: 1025 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1026 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1027 // CHECK1: omp_offload.cont: 1028 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1029 // CHECK1: omp_if.else: 1030 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 1031 // CHECK1-NEXT: br label [[OMP_IF_END]] 1032 // CHECK1: omp_if.end: 1033 // CHECK1-NEXT: [[TMP51:%.*]] = mul nsw i64 1, [[TMP2]] 1034 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP51]] 1035 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1036 // CHECK1-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1037 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP52]] to i32 1038 // CHECK1-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4 1039 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP53]] 1040 // CHECK1-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1041 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP54]]) 1042 // CHECK1-NEXT: ret i32 [[ADD4]] 1043 // 1044 // 1045 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 1046 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 1047 // CHECK1-NEXT: entry: 1048 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1049 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1050 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1051 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 1052 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1053 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1054 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1055 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1056 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 1057 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 1058 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 1059 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1060 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1061 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1062 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 1063 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1064 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1065 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1066 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1067 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1068 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1069 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1070 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1071 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1072 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1073 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 1074 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1075 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1076 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1077 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1078 // CHECK1: omp_if.then: 1079 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1080 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1081 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1082 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1083 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 1084 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 1085 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1086 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 1087 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1088 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1089 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1090 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1091 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 1092 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 1093 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1094 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1095 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1096 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1097 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1098 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1099 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1100 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1101 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1102 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1103 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1104 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1105 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1106 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1107 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1108 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1109 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1110 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1111 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1112 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1113 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1114 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1115 // CHECK1-NEXT: store i32 1, i32* [[TMP29]], align 4 1116 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1117 // CHECK1-NEXT: store i32 4, i32* [[TMP30]], align 4 1118 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1119 // CHECK1-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 8 1120 // CHECK1-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1121 // CHECK1-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 8 1122 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1123 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 8 1124 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1125 // CHECK1-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 8 1126 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1127 // CHECK1-NEXT: store i8** null, i8*** [[TMP35]], align 8 1128 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1129 // CHECK1-NEXT: store i8** null, i8*** [[TMP36]], align 8 1130 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1131 // CHECK1-NEXT: store i64 0, i64* [[TMP37]], align 8 1132 // CHECK1-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1133 // CHECK1-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 1134 // CHECK1-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1135 // CHECK1: omp_offload.failed: 1136 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1137 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1138 // CHECK1: omp_offload.cont: 1139 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1140 // CHECK1: omp_if.else: 1141 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1142 // CHECK1-NEXT: br label [[OMP_IF_END]] 1143 // CHECK1: omp_if.end: 1144 // CHECK1-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 1145 // CHECK1-NEXT: ret i32 [[TMP40]] 1146 // 1147 // 1148 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1149 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1150 // CHECK1-NEXT: entry: 1151 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1152 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1153 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1154 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1155 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1156 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1157 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1158 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1159 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1160 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1161 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1162 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1163 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1164 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1165 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1166 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1167 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1168 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1169 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1170 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1171 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1172 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1173 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1174 // CHECK1: omp_if.then: 1175 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1176 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1177 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1178 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1179 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1180 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1181 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1182 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1183 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1184 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1185 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1186 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1187 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1188 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1189 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1190 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1191 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1192 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1193 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1194 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1195 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1196 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1197 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1198 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1199 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1200 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1201 // CHECK1-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1202 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1203 // CHECK1-NEXT: store i32 1, i32* [[TMP22]], align 4 1204 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1205 // CHECK1-NEXT: store i32 3, i32* [[TMP23]], align 4 1206 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1207 // CHECK1-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 8 1208 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1209 // CHECK1-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 8 1210 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1211 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 8 1212 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1213 // CHECK1-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 8 1214 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1215 // CHECK1-NEXT: store i8** null, i8*** [[TMP28]], align 8 1216 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1217 // CHECK1-NEXT: store i8** null, i8*** [[TMP29]], align 8 1218 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1219 // CHECK1-NEXT: store i64 0, i64* [[TMP30]], align 8 1220 // CHECK1-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1221 // CHECK1-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 1222 // CHECK1-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1223 // CHECK1: omp_offload.failed: 1224 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1225 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1226 // CHECK1: omp_offload.cont: 1227 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1228 // CHECK1: omp_if.else: 1229 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1230 // CHECK1-NEXT: br label [[OMP_IF_END]] 1231 // CHECK1: omp_if.end: 1232 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4 1233 // CHECK1-NEXT: ret i32 [[TMP33]] 1234 // 1235 // 1236 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 1237 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1238 // CHECK1-NEXT: entry: 1239 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1240 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1241 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1242 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1243 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1244 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1245 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1246 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1247 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1248 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1249 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1250 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1251 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1252 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1253 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1254 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1255 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1256 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1257 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1258 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1259 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1260 // CHECK1-NEXT: ret void 1261 // 1262 // 1263 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 1264 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1265 // CHECK1-NEXT: entry: 1266 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1267 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1268 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1269 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1270 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1271 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1272 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1273 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1274 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1275 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1276 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1277 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1278 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1279 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1280 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1281 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1282 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1283 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1284 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1285 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1286 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 1287 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 1288 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1289 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1290 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1291 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 1292 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 1293 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 1294 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1295 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 1296 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 1297 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1298 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 1299 // CHECK1-NEXT: ret void 1300 // 1301 // 1302 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 1303 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1304 // CHECK1-NEXT: entry: 1305 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1306 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1307 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1308 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1309 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1310 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1311 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1312 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1313 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1314 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1315 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1316 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1317 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1318 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1319 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1320 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1321 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1322 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1323 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1324 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1325 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1326 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1327 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1328 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1329 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1330 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1331 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1332 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1333 // CHECK1-NEXT: ret void 1334 // 1335 // 1336 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1337 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1338 // CHECK1-NEXT: entry: 1339 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1340 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1341 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1342 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1343 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1344 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1345 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1346 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1347 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1348 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1349 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1350 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1351 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1352 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1353 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1354 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1355 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1356 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1357 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1358 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1359 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 1360 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1361 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1362 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 1363 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 1364 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 1365 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 1366 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 1367 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 1368 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1369 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1370 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 1371 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 1372 // CHECK1-NEXT: ret void 1373 // 1374 // 1375 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 1376 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1377 // CHECK1-NEXT: entry: 1378 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1379 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1380 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1381 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1382 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1383 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1384 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1385 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1386 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1387 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1388 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1389 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1390 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1391 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1392 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1393 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1394 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1395 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1396 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1397 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1398 // CHECK1-NEXT: ret void 1399 // 1400 // 1401 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1402 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1403 // CHECK1-NEXT: entry: 1404 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1405 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1406 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1407 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1408 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1409 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1410 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1411 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1412 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1413 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1414 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1415 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1416 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1417 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1418 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1419 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1420 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1421 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1422 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1423 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1424 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1425 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1426 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1427 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 1428 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 1429 // CHECK1-NEXT: ret void 1430 // 1431 // 1432 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1433 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { 1434 // CHECK1-NEXT: entry: 1435 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1436 // CHECK1-NEXT: ret void 1437 // 1438 // 1439 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1440 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1441 // CHECK3-NEXT: entry: 1442 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1443 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1444 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1445 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1446 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1447 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1448 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1449 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1450 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1451 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 1452 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1453 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1454 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1455 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1456 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1457 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 1458 // CHECK3-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 1459 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 1460 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 1461 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 1462 // CHECK3-NEXT: [[A_CASTED11:%.*]] = alloca i32, align 4 1463 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS14:%.*]] = alloca [9 x i8*], align 4 1464 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS15:%.*]] = alloca [9 x i8*], align 4 1465 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS16:%.*]] = alloca [9 x i8*], align 4 1466 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 1467 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1468 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1469 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1470 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1471 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1472 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1473 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1474 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 1475 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 1476 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1477 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 1478 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 1479 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 1480 // CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 1481 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 1482 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 1483 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 1484 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 1485 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 1486 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 1487 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 1488 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 1489 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1490 // CHECK3-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 1491 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1492 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1493 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1494 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 1495 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1496 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 1497 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 1498 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1499 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 1500 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1501 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1502 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1503 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 1504 // CHECK3-NEXT: store i32 1, i32* [[TMP20]], align 4 1505 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 1506 // CHECK3-NEXT: store i32 1, i32* [[TMP21]], align 4 1507 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 1508 // CHECK3-NEXT: store i8** [[TMP18]], i8*** [[TMP22]], align 4 1509 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 1510 // CHECK3-NEXT: store i8** [[TMP19]], i8*** [[TMP23]], align 4 1511 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 1512 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64** [[TMP24]], align 4 1513 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 1514 // CHECK3-NEXT: store i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i64** [[TMP25]], align 4 1515 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 1516 // CHECK3-NEXT: store i8** null, i8*** [[TMP26]], align 4 1517 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 1518 // CHECK3-NEXT: store i8** null, i8*** [[TMP27]], align 4 1519 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 1520 // CHECK3-NEXT: store i64 0, i64* [[TMP28]], align 8 1521 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 1522 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1523 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1524 // CHECK3: omp_offload.failed: 1525 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 1526 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1527 // CHECK3: omp_offload.cont: 1528 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1529 // CHECK3-NEXT: store i32 [[TMP31]], i32* [[A_CASTED2]], align 4 1530 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[A_CASTED2]], align 4 1531 // CHECK3-NEXT: [[TMP33:%.*]] = load i16, i16* [[AA]], align 2 1532 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 1533 // CHECK3-NEXT: store i16 [[TMP33]], i16* [[CONV4]], align 2 1534 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 1535 // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[N_ADDR]], align 4 1536 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP35]], 10 1537 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1538 // CHECK3: omp_if.then: 1539 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 1540 // CHECK3-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i32* 1541 // CHECK3-NEXT: store i32 [[TMP32]], i32* [[TMP37]], align 4 1542 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 1543 // CHECK3-NEXT: [[TMP39:%.*]] = bitcast i8** [[TMP38]] to i32* 1544 // CHECK3-NEXT: store i32 [[TMP32]], i32* [[TMP39]], align 4 1545 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 1546 // CHECK3-NEXT: store i8* null, i8** [[TMP40]], align 4 1547 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 1548 // CHECK3-NEXT: [[TMP42:%.*]] = bitcast i8** [[TMP41]] to i32* 1549 // CHECK3-NEXT: store i32 [[TMP34]], i32* [[TMP42]], align 4 1550 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 1551 // CHECK3-NEXT: [[TMP44:%.*]] = bitcast i8** [[TMP43]] to i32* 1552 // CHECK3-NEXT: store i32 [[TMP34]], i32* [[TMP44]], align 4 1553 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 1554 // CHECK3-NEXT: store i8* null, i8** [[TMP45]], align 4 1555 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 1556 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 1557 // CHECK3-NEXT: [[KERNEL_ARGS8:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1558 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]], i32 0, i32 0 1559 // CHECK3-NEXT: store i32 1, i32* [[TMP48]], align 4 1560 // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]], i32 0, i32 1 1561 // CHECK3-NEXT: store i32 2, i32* [[TMP49]], align 4 1562 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]], i32 0, i32 2 1563 // CHECK3-NEXT: store i8** [[TMP46]], i8*** [[TMP50]], align 4 1564 // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]], i32 0, i32 3 1565 // CHECK3-NEXT: store i8** [[TMP47]], i8*** [[TMP51]], align 4 1566 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]], i32 0, i32 4 1567 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64** [[TMP52]], align 4 1568 // CHECK3-NEXT: [[TMP53:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]], i32 0, i32 5 1569 // CHECK3-NEXT: store i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i64** [[TMP53]], align 4 1570 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]], i32 0, i32 6 1571 // CHECK3-NEXT: store i8** null, i8*** [[TMP54]], align 4 1572 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]], i32 0, i32 7 1573 // CHECK3-NEXT: store i8** null, i8*** [[TMP55]], align 4 1574 // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]], i32 0, i32 8 1575 // CHECK3-NEXT: store i64 0, i64* [[TMP56]], align 8 1576 // CHECK3-NEXT: [[TMP57:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS8]]) 1577 // CHECK3-NEXT: [[TMP58:%.*]] = icmp ne i32 [[TMP57]], 0 1578 // CHECK3-NEXT: br i1 [[TMP58]], label [[OMP_OFFLOAD_FAILED9:%.*]], label [[OMP_OFFLOAD_CONT10:%.*]] 1579 // CHECK3: omp_offload.failed9: 1580 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR4]] 1581 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT10]] 1582 // CHECK3: omp_offload.cont10: 1583 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1584 // CHECK3: omp_if.else: 1585 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP32]], i32 [[TMP34]]) #[[ATTR4]] 1586 // CHECK3-NEXT: br label [[OMP_IF_END]] 1587 // CHECK3: omp_if.end: 1588 // CHECK3-NEXT: [[TMP59:%.*]] = load i32, i32* [[A]], align 4 1589 // CHECK3-NEXT: store i32 [[TMP59]], i32* [[A_CASTED11]], align 4 1590 // CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* [[A_CASTED11]], align 4 1591 // CHECK3-NEXT: [[TMP61:%.*]] = load i32, i32* [[N_ADDR]], align 4 1592 // CHECK3-NEXT: [[CMP12:%.*]] = icmp sgt i32 [[TMP61]], 20 1593 // CHECK3-NEXT: br i1 [[CMP12]], label [[OMP_IF_THEN13:%.*]], label [[OMP_IF_ELSE20:%.*]] 1594 // CHECK3: omp_if.then13: 1595 // CHECK3-NEXT: [[TMP62:%.*]] = mul nuw i32 [[TMP1]], 4 1596 // CHECK3-NEXT: [[TMP63:%.*]] = sext i32 [[TMP62]] to i64 1597 // CHECK3-NEXT: [[TMP64:%.*]] = mul nuw i32 5, [[TMP3]] 1598 // CHECK3-NEXT: [[TMP65:%.*]] = mul nuw i32 [[TMP64]], 8 1599 // CHECK3-NEXT: [[TMP66:%.*]] = sext i32 [[TMP65]] to i64 1600 // CHECK3-NEXT: [[TMP67:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1601 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP67]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i32 72, i1 false) 1602 // CHECK3-NEXT: [[TMP68:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 1603 // CHECK3-NEXT: [[TMP69:%.*]] = bitcast i8** [[TMP68]] to i32* 1604 // CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP69]], align 4 1605 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 1606 // CHECK3-NEXT: [[TMP71:%.*]] = bitcast i8** [[TMP70]] to i32* 1607 // CHECK3-NEXT: store i32 [[TMP60]], i32* [[TMP71]], align 4 1608 // CHECK3-NEXT: [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 0 1609 // CHECK3-NEXT: store i8* null, i8** [[TMP72]], align 4 1610 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 1 1611 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [10 x float]** 1612 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP74]], align 4 1613 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 1 1614 // CHECK3-NEXT: [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [10 x float]** 1615 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP76]], align 4 1616 // CHECK3-NEXT: [[TMP77:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 1 1617 // CHECK3-NEXT: store i8* null, i8** [[TMP77]], align 4 1618 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 2 1619 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 1620 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP79]], align 4 1621 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 2 1622 // CHECK3-NEXT: [[TMP81:%.*]] = bitcast i8** [[TMP80]] to i32* 1623 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP81]], align 4 1624 // CHECK3-NEXT: [[TMP82:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 2 1625 // CHECK3-NEXT: store i8* null, i8** [[TMP82]], align 4 1626 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 3 1627 // CHECK3-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to float** 1628 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP84]], align 4 1629 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 3 1630 // CHECK3-NEXT: [[TMP86:%.*]] = bitcast i8** [[TMP85]] to float** 1631 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP86]], align 4 1632 // CHECK3-NEXT: [[TMP87:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1633 // CHECK3-NEXT: store i64 [[TMP63]], i64* [[TMP87]], align 4 1634 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 3 1635 // CHECK3-NEXT: store i8* null, i8** [[TMP88]], align 4 1636 // CHECK3-NEXT: [[TMP89:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 4 1637 // CHECK3-NEXT: [[TMP90:%.*]] = bitcast i8** [[TMP89]] to [5 x [10 x double]]** 1638 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP90]], align 4 1639 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 4 1640 // CHECK3-NEXT: [[TMP92:%.*]] = bitcast i8** [[TMP91]] to [5 x [10 x double]]** 1641 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP92]], align 4 1642 // CHECK3-NEXT: [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 4 1643 // CHECK3-NEXT: store i8* null, i8** [[TMP93]], align 4 1644 // CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 5 1645 // CHECK3-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to i32* 1646 // CHECK3-NEXT: store i32 5, i32* [[TMP95]], align 4 1647 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 5 1648 // CHECK3-NEXT: [[TMP97:%.*]] = bitcast i8** [[TMP96]] to i32* 1649 // CHECK3-NEXT: store i32 5, i32* [[TMP97]], align 4 1650 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 5 1651 // CHECK3-NEXT: store i8* null, i8** [[TMP98]], align 4 1652 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 6 1653 // CHECK3-NEXT: [[TMP100:%.*]] = bitcast i8** [[TMP99]] to i32* 1654 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP100]], align 4 1655 // CHECK3-NEXT: [[TMP101:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 6 1656 // CHECK3-NEXT: [[TMP102:%.*]] = bitcast i8** [[TMP101]] to i32* 1657 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP102]], align 4 1658 // CHECK3-NEXT: [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 6 1659 // CHECK3-NEXT: store i8* null, i8** [[TMP103]], align 4 1660 // CHECK3-NEXT: [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 7 1661 // CHECK3-NEXT: [[TMP105:%.*]] = bitcast i8** [[TMP104]] to double** 1662 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP105]], align 4 1663 // CHECK3-NEXT: [[TMP106:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 7 1664 // CHECK3-NEXT: [[TMP107:%.*]] = bitcast i8** [[TMP106]] to double** 1665 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP107]], align 4 1666 // CHECK3-NEXT: [[TMP108:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 1667 // CHECK3-NEXT: store i64 [[TMP66]], i64* [[TMP108]], align 4 1668 // CHECK3-NEXT: [[TMP109:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 7 1669 // CHECK3-NEXT: store i8* null, i8** [[TMP109]], align 4 1670 // CHECK3-NEXT: [[TMP110:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 8 1671 // CHECK3-NEXT: [[TMP111:%.*]] = bitcast i8** [[TMP110]] to %struct.TT** 1672 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP111]], align 4 1673 // CHECK3-NEXT: [[TMP112:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 8 1674 // CHECK3-NEXT: [[TMP113:%.*]] = bitcast i8** [[TMP112]] to %struct.TT** 1675 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP113]], align 4 1676 // CHECK3-NEXT: [[TMP114:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS16]], i32 0, i32 8 1677 // CHECK3-NEXT: store i8* null, i8** [[TMP114]], align 4 1678 // CHECK3-NEXT: [[TMP115:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS14]], i32 0, i32 0 1679 // CHECK3-NEXT: [[TMP116:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS15]], i32 0, i32 0 1680 // CHECK3-NEXT: [[TMP117:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1681 // CHECK3-NEXT: [[KERNEL_ARGS17:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS]], align 8 1682 // CHECK3-NEXT: [[TMP118:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]], i32 0, i32 0 1683 // CHECK3-NEXT: store i32 1, i32* [[TMP118]], align 4 1684 // CHECK3-NEXT: [[TMP119:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]], i32 0, i32 1 1685 // CHECK3-NEXT: store i32 9, i32* [[TMP119]], align 4 1686 // CHECK3-NEXT: [[TMP120:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]], i32 0, i32 2 1687 // CHECK3-NEXT: store i8** [[TMP115]], i8*** [[TMP120]], align 4 1688 // CHECK3-NEXT: [[TMP121:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]], i32 0, i32 3 1689 // CHECK3-NEXT: store i8** [[TMP116]], i8*** [[TMP121]], align 4 1690 // CHECK3-NEXT: [[TMP122:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]], i32 0, i32 4 1691 // CHECK3-NEXT: store i64* [[TMP117]], i64** [[TMP122]], align 4 1692 // CHECK3-NEXT: [[TMP123:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]], i32 0, i32 5 1693 // CHECK3-NEXT: store i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i64** [[TMP123]], align 4 1694 // CHECK3-NEXT: [[TMP124:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]], i32 0, i32 6 1695 // CHECK3-NEXT: store i8** null, i8*** [[TMP124]], align 4 1696 // CHECK3-NEXT: [[TMP125:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]], i32 0, i32 7 1697 // CHECK3-NEXT: store i8** null, i8*** [[TMP125]], align 4 1698 // CHECK3-NEXT: [[TMP126:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]], i32 0, i32 8 1699 // CHECK3-NEXT: store i64 0, i64* [[TMP126]], align 8 1700 // CHECK3-NEXT: [[TMP127:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS17]]) 1701 // CHECK3-NEXT: [[TMP128:%.*]] = icmp ne i32 [[TMP127]], 0 1702 // CHECK3-NEXT: br i1 [[TMP128]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] 1703 // CHECK3: omp_offload.failed18: 1704 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP60]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 1705 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT19]] 1706 // CHECK3: omp_offload.cont19: 1707 // CHECK3-NEXT: br label [[OMP_IF_END21:%.*]] 1708 // CHECK3: omp_if.else20: 1709 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP60]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 1710 // CHECK3-NEXT: br label [[OMP_IF_END21]] 1711 // CHECK3: omp_if.end21: 1712 // CHECK3-NEXT: [[TMP129:%.*]] = load i32, i32* [[A]], align 4 1713 // CHECK3-NEXT: [[TMP130:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 1714 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP130]]) 1715 // CHECK3-NEXT: ret i32 [[TMP129]] 1716 // 1717 // 1718 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 1719 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 1720 // CHECK3-NEXT: entry: 1721 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1722 // CHECK3-NEXT: ret void 1723 // 1724 // 1725 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1726 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 1727 // CHECK3-NEXT: entry: 1728 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1729 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1730 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1731 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1732 // CHECK3-NEXT: ret void 1733 // 1734 // 1735 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 1736 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 1737 // CHECK3-NEXT: entry: 1738 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 1739 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 1740 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 1741 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 1742 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 1743 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 1744 // CHECK3-NEXT: [[KERNEL_ARGS_I:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 1745 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 1746 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 1747 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 1748 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 1749 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 1750 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 1751 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 1752 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 1753 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 1754 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 1755 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 1756 // CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 1757 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 1758 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 1759 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 1760 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 1761 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 1762 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 1763 // CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 1764 // CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 1765 // CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 1766 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 1767 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 1768 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 0 1769 // CHECK3-NEXT: store i32 1, i32* [[TMP11]], align 4, !noalias !22 1770 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 1 1771 // CHECK3-NEXT: store i32 0, i32* [[TMP12]], align 4, !noalias !22 1772 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 2 1773 // CHECK3-NEXT: store i8** null, i8*** [[TMP13]], align 4, !noalias !22 1774 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 3 1775 // CHECK3-NEXT: store i8** null, i8*** [[TMP14]], align 4, !noalias !22 1776 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 4 1777 // CHECK3-NEXT: store i64* null, i64** [[TMP15]], align 4, !noalias !22 1778 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 5 1779 // CHECK3-NEXT: store i64* null, i64** [[TMP16]], align 4, !noalias !22 1780 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 6 1781 // CHECK3-NEXT: store i8** null, i8*** [[TMP17]], align 4, !noalias !22 1782 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 7 1783 // CHECK3-NEXT: store i8** null, i8*** [[TMP18]], align 4, !noalias !22 1784 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i32 8 1785 // CHECK3-NEXT: store i64 0, i64* [[TMP19]], align 8, !noalias !22 1786 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_kernel_nowait(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS_I]], i32 0, i8* null, i32 0, i8* null) 1787 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1788 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 1789 // CHECK3: omp_offload.failed.i: 1790 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 1791 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 1792 // CHECK3: .omp_outlined..1.exit: 1793 // CHECK3-NEXT: ret i32 0 1794 // 1795 // 1796 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 1797 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { 1798 // CHECK3-NEXT: entry: 1799 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1800 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1801 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1802 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1803 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 1804 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 1805 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 1806 // CHECK3-NEXT: ret void 1807 // 1808 // 1809 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 1810 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 1811 // CHECK3-NEXT: entry: 1812 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1813 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1814 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1815 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1816 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1817 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1818 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1819 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1820 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1821 // CHECK3-NEXT: ret void 1822 // 1823 // 1824 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 1825 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 1826 // CHECK3-NEXT: entry: 1827 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1828 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1829 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1830 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1831 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 1832 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1833 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 1834 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1835 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 1836 // CHECK3-NEXT: ret void 1837 // 1838 // 1839 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 1840 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 1841 // CHECK3-NEXT: entry: 1842 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1843 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1844 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1845 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1846 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1847 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1848 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1849 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 1850 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 1851 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 1852 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 1853 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 1854 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1855 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1856 // CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 1857 // CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 1858 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 1859 // CHECK3: .cancel.exit: 1860 // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 1861 // CHECK3-NEXT: br label [[DOTCANCEL_CONTINUE]] 1862 // CHECK3: .cancel.continue: 1863 // CHECK3-NEXT: ret void 1864 // 1865 // 1866 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 1867 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 1868 // CHECK3-NEXT: entry: 1869 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1870 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1871 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1872 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1873 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1874 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1875 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1876 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1877 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 1878 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 1879 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 1880 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1881 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1882 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1883 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 1884 // CHECK3-NEXT: ret void 1885 // 1886 // 1887 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1888 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 1889 // CHECK3-NEXT: entry: 1890 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1891 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1892 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1893 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1894 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1895 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1896 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1897 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1898 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1899 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1900 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1901 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1902 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 1903 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 1904 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 1905 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 1906 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 1907 // CHECK3-NEXT: ret void 1908 // 1909 // 1910 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 1911 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 1912 // CHECK3-NEXT: entry: 1913 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1914 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 1915 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1916 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 1917 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 1918 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1919 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 1920 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 1921 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 1922 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1923 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1924 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 1925 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1926 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 1927 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 1928 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1929 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 1930 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 1931 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 1932 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 1933 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1934 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 1935 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 1936 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1937 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 1938 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 1939 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 1940 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 1941 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 1942 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 1943 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 1944 // CHECK3-NEXT: ret void 1945 // 1946 // 1947 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 1948 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 1949 // CHECK3-NEXT: entry: 1950 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1951 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1952 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1953 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 1954 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1955 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 1956 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 1957 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1958 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 1959 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 1960 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 1961 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1962 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1963 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1964 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 1965 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1966 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 1967 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 1968 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1969 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 1970 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 1971 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 1972 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 1973 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1974 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 1975 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 1976 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1977 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 1978 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 1979 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 1980 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 1981 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 1982 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1983 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 1984 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 1985 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 1986 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 1987 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 1988 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 1989 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 1990 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 1991 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 1992 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 1993 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 1994 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 1995 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 1996 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 1997 // CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 1998 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 1999 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 2000 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 2001 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 2002 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 2003 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 2004 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 2005 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 2006 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2007 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 2008 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 2009 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 2010 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2011 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 2012 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 2013 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 2014 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 2015 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 2016 // CHECK3-NEXT: ret void 2017 // 2018 // 2019 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 2020 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2021 // CHECK3-NEXT: entry: 2022 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2023 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2024 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 2025 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2026 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2027 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2028 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 2029 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 2030 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 2031 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 2032 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 2033 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 2034 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 2035 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 2036 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 2037 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2038 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 2039 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 2040 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 2041 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 2042 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2043 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 2044 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 2045 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 2046 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 2047 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 2048 // CHECK3-NEXT: ret i32 [[TMP8]] 2049 // 2050 // 2051 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 2052 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 2053 // CHECK3-NEXT: entry: 2054 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2055 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2056 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 2057 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 2058 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 2059 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2060 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 2061 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 2062 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 2063 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 2064 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2065 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2066 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2067 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2068 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2069 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 2070 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 2071 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2072 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 2073 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 2074 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 2075 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 2076 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 2077 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 2078 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 2079 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2080 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 2081 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2082 // CHECK3: omp_if.then: 2083 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 2084 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 2085 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 2086 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 2087 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 2088 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 2089 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2090 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 2091 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 2092 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2093 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 2094 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 2095 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2096 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 2097 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2098 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 2099 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 2100 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2101 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 2102 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 2103 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2104 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 2105 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2106 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 2107 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 2108 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2109 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 2110 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 2111 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2112 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 2113 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2114 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 2115 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 2116 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2117 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 2118 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 2119 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2120 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 2121 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 2122 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 2123 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 2124 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 2125 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 2126 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 2127 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 2128 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 2129 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 2130 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 2131 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2132 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2133 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 2134 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2135 // CHECK3-NEXT: [[TMP40:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 2136 // CHECK3-NEXT: store i32 1, i32* [[TMP40]], align 4 2137 // CHECK3-NEXT: [[TMP41:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 2138 // CHECK3-NEXT: store i32 5, i32* [[TMP41]], align 4 2139 // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 2140 // CHECK3-NEXT: store i8** [[TMP37]], i8*** [[TMP42]], align 4 2141 // CHECK3-NEXT: [[TMP43:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 2142 // CHECK3-NEXT: store i8** [[TMP38]], i8*** [[TMP43]], align 4 2143 // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 2144 // CHECK3-NEXT: store i64* [[TMP39]], i64** [[TMP44]], align 4 2145 // CHECK3-NEXT: [[TMP45:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 2146 // CHECK3-NEXT: store i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i64** [[TMP45]], align 4 2147 // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 2148 // CHECK3-NEXT: store i8** null, i8*** [[TMP46]], align 4 2149 // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 2150 // CHECK3-NEXT: store i8** null, i8*** [[TMP47]], align 4 2151 // CHECK3-NEXT: [[TMP48:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 2152 // CHECK3-NEXT: store i64 0, i64* [[TMP48]], align 8 2153 // CHECK3-NEXT: [[TMP49:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 2154 // CHECK3-NEXT: [[TMP50:%.*]] = icmp ne i32 [[TMP49]], 0 2155 // CHECK3-NEXT: br i1 [[TMP50]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2156 // CHECK3: omp_offload.failed: 2157 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 2158 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2159 // CHECK3: omp_offload.cont: 2160 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2161 // CHECK3: omp_if.else: 2162 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 2163 // CHECK3-NEXT: br label [[OMP_IF_END]] 2164 // CHECK3: omp_if.end: 2165 // CHECK3-NEXT: [[TMP51:%.*]] = mul nsw i32 1, [[TMP1]] 2166 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP51]] 2167 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 2168 // CHECK3-NEXT: [[TMP52:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 2169 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP52]] to i32 2170 // CHECK3-NEXT: [[TMP53:%.*]] = load i32, i32* [[B]], align 4 2171 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP53]] 2172 // CHECK3-NEXT: [[TMP54:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 2173 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP54]]) 2174 // CHECK3-NEXT: ret i32 [[ADD3]] 2175 // 2176 // 2177 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 2178 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 2179 // CHECK3-NEXT: entry: 2180 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2181 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2182 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2183 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 2184 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2185 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2186 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2187 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 2188 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 2189 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 2190 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 2191 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2192 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2193 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2194 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 2195 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2196 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2197 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2198 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2199 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2200 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 2201 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2202 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 2203 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 2204 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 2205 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 2206 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2207 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 2208 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2209 // CHECK3: omp_if.then: 2210 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2211 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2212 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 2213 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2214 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 2215 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 2216 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2217 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 2218 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2219 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2220 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2221 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2222 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 2223 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 2224 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2225 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 2226 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2227 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2228 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 2229 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2230 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 2231 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 2232 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2233 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 2234 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2235 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 2236 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 2237 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2238 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 2239 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 2240 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2241 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 2242 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2243 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2244 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2245 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 2246 // CHECK3-NEXT: store i32 1, i32* [[TMP29]], align 4 2247 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 2248 // CHECK3-NEXT: store i32 4, i32* [[TMP30]], align 4 2249 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 2250 // CHECK3-NEXT: store i8** [[TMP27]], i8*** [[TMP31]], align 4 2251 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 2252 // CHECK3-NEXT: store i8** [[TMP28]], i8*** [[TMP32]], align 4 2253 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 2254 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64** [[TMP33]], align 4 2255 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 2256 // CHECK3-NEXT: store i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i64** [[TMP34]], align 4 2257 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 2258 // CHECK3-NEXT: store i8** null, i8*** [[TMP35]], align 4 2259 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 2260 // CHECK3-NEXT: store i8** null, i8*** [[TMP36]], align 4 2261 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 2262 // CHECK3-NEXT: store i64 0, i64* [[TMP37]], align 8 2263 // CHECK3-NEXT: [[TMP38:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 2264 // CHECK3-NEXT: [[TMP39:%.*]] = icmp ne i32 [[TMP38]], 0 2265 // CHECK3-NEXT: br i1 [[TMP39]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2266 // CHECK3: omp_offload.failed: 2267 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 2268 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2269 // CHECK3: omp_offload.cont: 2270 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2271 // CHECK3: omp_if.else: 2272 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 2273 // CHECK3-NEXT: br label [[OMP_IF_END]] 2274 // CHECK3: omp_if.end: 2275 // CHECK3-NEXT: [[TMP40:%.*]] = load i32, i32* [[A]], align 4 2276 // CHECK3-NEXT: ret i32 [[TMP40]] 2277 // 2278 // 2279 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2280 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 2281 // CHECK3-NEXT: entry: 2282 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2283 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2284 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2285 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2286 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2287 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2288 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 2289 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 2290 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 2291 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2292 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2293 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2294 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2295 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2296 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2297 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2298 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2299 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 2300 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2301 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2302 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 2303 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2304 // CHECK3: omp_if.then: 2305 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2306 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 2307 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 2308 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2309 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2310 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 2311 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2312 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 2313 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2314 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 2315 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 2316 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2317 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2318 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2319 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2320 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 2321 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2322 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 2323 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 2324 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2325 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 2326 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 2327 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2328 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 2329 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2330 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2331 // CHECK3-NEXT: [[KERNEL_ARGS:%.*]] = alloca [[STRUCT___TGT_KERNEL_ARGUMENTS:%.*]], align 8 2332 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 0 2333 // CHECK3-NEXT: store i32 1, i32* [[TMP22]], align 4 2334 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 1 2335 // CHECK3-NEXT: store i32 3, i32* [[TMP23]], align 4 2336 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 2 2337 // CHECK3-NEXT: store i8** [[TMP20]], i8*** [[TMP24]], align 4 2338 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 3 2339 // CHECK3-NEXT: store i8** [[TMP21]], i8*** [[TMP25]], align 4 2340 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 4 2341 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64** [[TMP26]], align 4 2342 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 5 2343 // CHECK3-NEXT: store i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i64** [[TMP27]], align 4 2344 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 6 2345 // CHECK3-NEXT: store i8** null, i8*** [[TMP28]], align 4 2346 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 7 2347 // CHECK3-NEXT: store i8** null, i8*** [[TMP29]], align 4 2348 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [[STRUCT___TGT_KERNEL_ARGUMENTS]], %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]], i32 0, i32 8 2349 // CHECK3-NEXT: store i64 0, i64* [[TMP30]], align 8 2350 // CHECK3-NEXT: [[TMP31:%.*]] = call i32 @__tgt_target_kernel(%struct.ident_t* @[[GLOB1]], i64 -1, i32 1, i32 0, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, %struct.__tgt_kernel_arguments* [[KERNEL_ARGS]]) 2351 // CHECK3-NEXT: [[TMP32:%.*]] = icmp ne i32 [[TMP31]], 0 2352 // CHECK3-NEXT: br i1 [[TMP32]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2353 // CHECK3: omp_offload.failed: 2354 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 2355 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2356 // CHECK3: omp_offload.cont: 2357 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2358 // CHECK3: omp_if.else: 2359 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 2360 // CHECK3-NEXT: br label [[OMP_IF_END]] 2361 // CHECK3: omp_if.end: 2362 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[A]], align 4 2363 // CHECK3-NEXT: ret i32 [[TMP33]] 2364 // 2365 // 2366 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 2367 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2368 // CHECK3-NEXT: entry: 2369 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2370 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2371 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2372 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2373 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 2374 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2375 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2376 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2377 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2378 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2379 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 2380 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2381 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2382 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2383 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 2384 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 2385 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 2386 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 2387 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 2388 // CHECK3-NEXT: ret void 2389 // 2390 // 2391 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 2392 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 2393 // CHECK3-NEXT: entry: 2394 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2395 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2396 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2397 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2398 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2399 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2400 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 2401 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2402 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2403 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2404 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2405 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2406 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2407 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 2408 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2409 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2410 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2411 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 2412 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 2413 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 2414 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2415 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2416 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 2417 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2418 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 2419 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 2420 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 4 2421 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 2422 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 2423 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 2424 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 2425 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 2426 // CHECK3-NEXT: ret void 2427 // 2428 // 2429 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 2430 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2431 // CHECK3-NEXT: entry: 2432 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2433 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2434 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 2435 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2436 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2437 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2438 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 2439 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2440 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2441 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 2442 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2443 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2444 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 2445 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2446 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2447 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2448 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2449 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2450 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2451 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 2452 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2453 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 2454 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 2455 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 2456 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 2457 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 2458 // CHECK3-NEXT: ret void 2459 // 2460 // 2461 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 2462 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 2463 // CHECK3-NEXT: entry: 2464 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2465 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2466 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2467 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2468 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 2469 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2470 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2471 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2472 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2473 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2474 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 2475 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2476 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2477 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 2478 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2479 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2480 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2481 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2482 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2483 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 2484 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2485 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2486 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 2487 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 2488 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 2489 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 2490 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 2491 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 2492 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 2493 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2494 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 2495 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 2496 // CHECK3-NEXT: ret void 2497 // 2498 // 2499 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 2500 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2501 // CHECK3-NEXT: entry: 2502 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2503 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2504 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2505 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2506 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2507 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2508 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2509 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2510 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2511 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2512 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2513 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2514 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2515 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2516 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2517 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 2518 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2519 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 2520 // CHECK3-NEXT: ret void 2521 // 2522 // 2523 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 2524 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 2525 // CHECK3-NEXT: entry: 2526 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2527 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2528 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2529 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2530 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2531 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2532 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2533 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2534 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2535 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2536 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2537 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2538 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2539 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2540 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2541 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2542 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 2543 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 2544 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 2545 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 2546 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 2547 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2548 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 2549 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 2550 // CHECK3-NEXT: ret void 2551 // 2552 // 2553 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2554 // CHECK3-SAME: () #[[ATTR8:[0-9]+]] { 2555 // CHECK3-NEXT: entry: 2556 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 2557 // CHECK3-NEXT: ret void 2558 // 2559 // 2560 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 2561 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2562 // CHECK9-NEXT: entry: 2563 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2564 // CHECK9-NEXT: ret void 2565 // 2566 // 2567 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2568 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 2569 // CHECK9-NEXT: entry: 2570 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2571 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2572 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2573 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2574 // CHECK9-NEXT: ret void 2575 // 2576 // 2577 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 2578 // CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 2579 // CHECK9-NEXT: entry: 2580 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2581 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2582 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2583 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2584 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2585 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2586 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2587 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2588 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2589 // CHECK9-NEXT: ret void 2590 // 2591 // 2592 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 2593 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 2594 // CHECK9-NEXT: entry: 2595 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2596 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2597 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2598 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2599 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2600 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2601 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2602 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2603 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2604 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 2605 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2606 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 2607 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2608 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2609 // CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 2610 // CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 2611 // CHECK9-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 2612 // CHECK9: .cancel.exit: 2613 // CHECK9-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 2614 // CHECK9-NEXT: br label [[DOTCANCEL_CONTINUE]] 2615 // CHECK9: .cancel.continue: 2616 // CHECK9-NEXT: ret void 2617 // 2618 // 2619 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 2620 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 2621 // CHECK9-NEXT: entry: 2622 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2623 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2624 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2625 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2626 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2627 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2628 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2629 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2630 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2631 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2632 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 2633 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2634 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2635 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2636 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 2637 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2638 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 2639 // CHECK9-NEXT: ret void 2640 // 2641 // 2642 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 2643 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 2644 // CHECK9-NEXT: entry: 2645 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2646 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2647 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2648 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2649 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2650 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2651 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2652 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2653 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2654 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2655 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2656 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2657 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2658 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 2659 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 2660 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2661 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2662 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 2663 // CHECK9-NEXT: ret void 2664 // 2665 // 2666 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 2667 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 2668 // CHECK9-NEXT: entry: 2669 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2670 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2671 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2672 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2673 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2674 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2675 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2676 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2677 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2678 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2679 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2680 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2681 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2682 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2683 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2684 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2685 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2686 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2687 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2688 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2689 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2690 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2691 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2692 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2693 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2694 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2695 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2696 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2697 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2698 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2699 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 2700 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 2701 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2702 // CHECK9-NEXT: ret void 2703 // 2704 // 2705 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 2706 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 2707 // CHECK9-NEXT: entry: 2708 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2709 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2710 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2711 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2712 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2713 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2714 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2715 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2716 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2717 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2718 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2719 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2720 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2721 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2722 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2723 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2724 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2725 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2726 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2727 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2728 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2729 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2730 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2731 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2732 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2733 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2734 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2735 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2736 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2737 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2738 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2739 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2740 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 2741 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2742 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 2743 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2744 // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 2745 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 2746 // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 2747 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 2748 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 2749 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 2750 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 2751 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 2752 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 2753 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 2754 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 2755 // CHECK9-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 2756 // CHECK9-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 2757 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 2758 // CHECK9-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 2759 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 2760 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 2761 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 2762 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 2763 // CHECK9-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 2764 // CHECK9-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 2765 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2766 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 2767 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 2768 // CHECK9-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 2769 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2770 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 2771 // CHECK9-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 2772 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 2773 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 2774 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 2775 // CHECK9-NEXT: ret void 2776 // 2777 // 2778 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 2779 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 2780 // CHECK9-NEXT: entry: 2781 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2782 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2783 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2784 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2785 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2786 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2787 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2788 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2789 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2790 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2791 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2792 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2793 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2794 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2795 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2796 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2797 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2798 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 2799 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2800 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2801 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2802 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 2803 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2804 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 2805 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 2806 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 2807 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 2808 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 2809 // CHECK9-NEXT: ret void 2810 // 2811 // 2812 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 2813 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 2814 // CHECK9-NEXT: entry: 2815 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2816 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2817 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2818 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2819 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2820 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2821 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2822 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2823 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2824 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2825 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2826 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2827 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2828 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2829 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2830 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2831 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2832 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2833 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2834 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2835 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 2836 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2837 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2838 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 2839 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 2840 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 2841 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 2842 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 2843 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 2844 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 2845 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2846 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 2847 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 2848 // CHECK9-NEXT: ret void 2849 // 2850 // 2851 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 2852 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 2853 // CHECK9-NEXT: entry: 2854 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2855 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2856 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2857 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2858 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2859 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2860 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2861 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2862 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2863 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2864 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2865 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2866 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2867 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2868 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2869 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2870 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2871 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2872 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 2873 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 2874 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 2875 // CHECK9-NEXT: ret void 2876 // 2877 // 2878 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 2879 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 2880 // CHECK9-NEXT: entry: 2881 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2882 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2883 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2884 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2885 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2886 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2887 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2888 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2889 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2890 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2891 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2892 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2893 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2894 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2895 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2896 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2897 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2898 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2899 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2900 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2901 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 2902 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 2903 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2904 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 2905 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2906 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 2907 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 2908 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 2909 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 2910 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 2911 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 2912 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 2913 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 2914 // CHECK9-NEXT: ret void 2915 // 2916 // 2917 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 2918 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 2919 // CHECK9-NEXT: entry: 2920 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2921 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2922 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2923 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2924 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2925 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2926 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2927 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2928 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2929 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2930 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2931 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2932 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2933 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 2934 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2935 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2936 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2937 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 2938 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2939 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 2940 // CHECK9-NEXT: ret void 2941 // 2942 // 2943 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 2944 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 2945 // CHECK9-NEXT: entry: 2946 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2947 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2948 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2949 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2950 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2951 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2952 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2953 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2954 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2955 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2956 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2957 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2958 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2959 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2960 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2961 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2962 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2963 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 2964 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2965 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2966 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 2967 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 2968 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2969 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 2970 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 2971 // CHECK9-NEXT: ret void 2972 // 2973 // 2974 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 2975 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2976 // CHECK11-NEXT: entry: 2977 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2978 // CHECK11-NEXT: ret void 2979 // 2980 // 2981 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 2982 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 2983 // CHECK11-NEXT: entry: 2984 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2985 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2986 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2987 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2988 // CHECK11-NEXT: ret void 2989 // 2990 // 2991 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 2992 // CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 2993 // CHECK11-NEXT: entry: 2994 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2995 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2996 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2997 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2998 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2999 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3000 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 3001 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3002 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 3003 // CHECK11-NEXT: ret void 3004 // 3005 // 3006 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 3007 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 3008 // CHECK11-NEXT: entry: 3009 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3010 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3011 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3012 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3013 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3014 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3015 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3016 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 3017 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 3018 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 3019 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 3020 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 3021 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 3022 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 3023 // CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 3024 // CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 3025 // CHECK11-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 3026 // CHECK11: .cancel.exit: 3027 // CHECK11-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 3028 // CHECK11-NEXT: br label [[DOTCANCEL_CONTINUE]] 3029 // CHECK11: .cancel.continue: 3030 // CHECK11-NEXT: ret void 3031 // 3032 // 3033 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 3034 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 3035 // CHECK11-NEXT: entry: 3036 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3037 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3038 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3039 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3040 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3041 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3042 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3043 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3044 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 3045 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 3046 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3047 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3048 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 3049 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3050 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 3051 // CHECK11-NEXT: ret void 3052 // 3053 // 3054 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 3055 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 3056 // CHECK11-NEXT: entry: 3057 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3058 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3059 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3060 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3061 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3062 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3063 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3064 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3065 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3066 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 3067 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 3068 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3069 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 3070 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 3071 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3072 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3073 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3074 // CHECK11-NEXT: ret void 3075 // 3076 // 3077 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 3078 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 3079 // CHECK11-NEXT: entry: 3080 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3081 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3082 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3083 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3084 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3085 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3086 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3087 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3088 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3089 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3090 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3091 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3092 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3093 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3094 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3095 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3096 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3097 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3098 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3099 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3100 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3101 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3102 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3103 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3104 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3105 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3106 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3107 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3108 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 3109 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 3110 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 3111 // CHECK11-NEXT: ret void 3112 // 3113 // 3114 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 3115 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 3116 // CHECK11-NEXT: entry: 3117 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3118 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3119 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3120 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 3121 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3122 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 3123 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 3124 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3125 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 3126 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 3127 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 3128 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3129 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3130 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3131 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 3132 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3133 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 3134 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 3135 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3136 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 3137 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 3138 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 3139 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 3140 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3141 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 3142 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 3143 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3144 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 3145 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 3146 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 3147 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 3148 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 3149 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3150 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 3151 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 3152 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 3153 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 3154 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 3155 // CHECK11-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 3156 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 3157 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3158 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 3159 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 3160 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 3161 // CHECK11-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 3162 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 3163 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 3164 // CHECK11-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 3165 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 3166 // CHECK11-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 3167 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 3168 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 3169 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 3170 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 3171 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 3172 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 3173 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 3174 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 3175 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 3176 // CHECK11-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 3177 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 3178 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 3179 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 3180 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 3181 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 3182 // CHECK11-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 3183 // CHECK11-NEXT: ret void 3184 // 3185 // 3186 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 3187 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3188 // CHECK11-NEXT: entry: 3189 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3190 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3191 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3192 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3193 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3194 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3195 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 3196 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3197 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3198 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3199 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3200 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3201 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3202 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3203 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3204 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3205 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3206 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3207 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3208 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 3209 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3210 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 3211 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 3212 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 3213 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 3214 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 3215 // CHECK11-NEXT: ret void 3216 // 3217 // 3218 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 3219 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 3220 // CHECK11-NEXT: entry: 3221 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3222 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3223 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3224 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3225 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 3226 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3227 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3228 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3229 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3230 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3231 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 3232 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3233 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3234 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 3235 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3236 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3237 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3238 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3239 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3240 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 3241 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 3242 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 3243 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 3244 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 3245 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 3246 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 3247 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 3248 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 3249 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3250 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3251 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 3252 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 3253 // CHECK11-NEXT: ret void 3254 // 3255 // 3256 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 3257 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 3258 // CHECK11-NEXT: entry: 3259 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3260 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3261 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3262 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3263 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3264 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 3265 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3266 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3267 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3268 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3269 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3270 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3271 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3272 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3273 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3274 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3275 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3276 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3277 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3278 // CHECK11-NEXT: ret void 3279 // 3280 // 3281 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 3282 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 3283 // CHECK11-NEXT: entry: 3284 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3285 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3286 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3287 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3288 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3289 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3290 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3291 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3292 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3293 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3294 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3295 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3296 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3297 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3298 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3299 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3300 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3301 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3302 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3303 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 3304 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3305 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3306 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 3307 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3308 // CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 3309 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 3310 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 3311 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 3312 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 3313 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 3314 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3315 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 3316 // CHECK11-NEXT: ret void 3317 // 3318 // 3319 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 3320 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3321 // CHECK11-NEXT: entry: 3322 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3323 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3324 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3325 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3326 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3327 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3328 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3329 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3330 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3331 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3332 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3333 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3334 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3335 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3336 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3337 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3338 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3339 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3340 // CHECK11-NEXT: ret void 3341 // 3342 // 3343 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 3344 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 3345 // CHECK11-NEXT: entry: 3346 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3347 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3348 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3349 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3350 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3351 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3352 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3353 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3354 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3355 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3356 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3357 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3358 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3359 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3360 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3361 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3362 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 3363 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3364 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3365 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3366 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3367 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3368 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 3369 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 3370 // CHECK11-NEXT: ret void 3371 // 3372