1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // Test host codegen. 3 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 4 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 5 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 6 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 7 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 8 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 9 10 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 11 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 12 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 13 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 14 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 15 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 16 17 // Test target codegen - host bc file has to be created first. 18 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 19 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 20 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 21 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 22 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 23 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 24 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 25 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 26 27 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 28 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 29 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 30 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 31 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 32 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 33 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 34 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 35 36 // Test host codegen. 37 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 38 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 39 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK1 40 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3 41 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 42 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 43 44 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 45 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 46 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 47 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 48 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 49 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 50 51 // Test target codegen - host bc file has to be created first. 52 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 53 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9 54 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 55 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK9 56 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 57 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11 58 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 59 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 60 61 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 62 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 63 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 64 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 65 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 66 // RUN: %clang_cc1 -no-opaque-pointers -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 67 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 68 // RUN: %clang_cc1 -no-opaque-pointers -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 69 70 // expected-no-diagnostics 71 #ifndef HEADER 72 #define HEADER 73 74 75 76 77 // We have 8 target regions, but only 6 that actually will generate offloading 78 // code and have mapped arguments, and only 4 have all-constant map sizes. 79 80 81 82 // Check target registration is registered as a Ctor. 83 84 85 template<typename tx, typename ty> 86 struct TT{ 87 tx X; 88 ty Y; 89 }; 90 91 int foo(int n) { 92 int a = 0; 93 short aa = 0; 94 float b[10]; 95 float bn[n]; 96 double c[5][10]; 97 double cn[5][n]; 98 TT<long long, char> d; 99 100 #pragma omp target parallel nowait 101 { 102 } 103 104 #pragma omp target parallel if(target: 0) 105 { 106 a += 1; 107 } 108 109 110 #pragma omp target parallel if(target: 1) 111 { 112 aa += 1; 113 #pragma omp cancel parallel 114 } 115 116 117 118 119 #pragma omp target parallel if(target: n>10) 120 { 121 a += 1; 122 aa += 1; 123 } 124 125 // We capture 3 VLA sizes in this target region 126 127 128 129 130 131 // The names below are not necessarily consistent with the names used for the 132 // addresses above as some are repeated. 133 134 135 136 137 138 139 140 141 142 143 144 #pragma omp target parallel if(target: n>20) 145 { 146 a += 1; 147 b[2] += 1.0; 148 bn[3] += 1.0; 149 c[1][2] += 1.0; 150 cn[1][3] += 1.0; 151 d.X += 1; 152 d.Y += 1; 153 } 154 155 return a; 156 } 157 158 // Check that the offloading functions are emitted and that the arguments are 159 // correct and loaded correctly for the target regions in foo(). 160 161 162 163 // Create stack storage and store argument in there. 164 165 // Create stack storage and store argument in there. 166 167 // Create stack storage and store argument in there. 168 169 // Create local storage for each capture. 170 171 172 173 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 174 175 template<typename tx> 176 tx ftemplate(int n) { 177 tx a = 0; 178 short aa = 0; 179 tx b[10]; 180 181 #pragma omp target parallel if(target: n>40) 182 { 183 a += 1; 184 aa += 1; 185 b[2] += 1; 186 } 187 188 return a; 189 } 190 191 static 192 int fstatic(int n) { 193 int a = 0; 194 short aa = 0; 195 char aaa = 0; 196 int b[10]; 197 198 #pragma omp target parallel if(target: n>50) 199 { 200 a += 1; 201 aa += 1; 202 aaa += 1; 203 b[2] += 1; 204 } 205 206 return a; 207 } 208 209 struct S1 { 210 double a; 211 212 int r1(int n){ 213 int b = n+1; 214 short int c[2][n]; 215 216 #pragma omp target parallel if(target: n>60) 217 { 218 this->a = (double)b + 1.5; 219 c[1][1] = ++a; 220 } 221 222 return c[1][1] + (int)b; 223 } 224 }; 225 226 int bar(int n){ 227 int a = 0; 228 229 a += foo(n); 230 231 S1 S; 232 a += S.r1(n); 233 234 a += fstatic(n); 235 236 a += ftemplate<int>(n); 237 238 return a; 239 } 240 241 242 243 // We capture 2 VLA sizes in this target region 244 245 246 // The names below are not necessarily consistent with the names used for the 247 // addresses above as some are repeated. 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 // Check that the offloading functions are emitted and that the arguments are 268 // correct and loaded correctly for the target regions of the callees of bar(). 269 270 // Create local storage for each capture. 271 // Store captures in the context. 272 273 274 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 275 276 277 // Create local storage for each capture. 278 // Store captures in the context. 279 280 281 282 283 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 284 285 // Create local storage for each capture. 286 // Store captures in the context. 287 288 289 290 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function. 291 292 293 #endif 294 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi 295 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0:[0-9]+]] { 296 // CHECK1-NEXT: entry: 297 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 298 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 299 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 300 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x float], align 4 301 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 302 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 303 // CHECK1-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 304 // CHECK1-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 305 // CHECK1-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8 306 // CHECK1-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 307 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 308 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 309 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8 310 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8 311 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8 312 // CHECK1-NEXT: [[A_CASTED3:%.*]] = alloca i64, align 8 313 // CHECK1-NEXT: [[AA_CASTED5:%.*]] = alloca i64, align 8 314 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8 315 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8 316 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8 317 // CHECK1-NEXT: [[A_CASTED12:%.*]] = alloca i64, align 8 318 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8 319 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8 320 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8 321 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8 322 // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 323 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 324 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 325 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 326 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 327 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 328 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 329 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 330 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4 331 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 332 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 333 // CHECK1-NEXT: [[TMP5:%.*]] = zext i32 [[TMP4]] to i64 334 // CHECK1-NEXT: [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]] 335 // CHECK1-NEXT: [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8 336 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8 337 // CHECK1-NEXT: [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 338 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates* 339 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0 340 // CHECK1-NEXT: [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]]) 341 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[A]], align 4 342 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 343 // CHECK1-NEXT: store i32 [[TMP11]], i32* [[CONV]], align 4 344 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8 345 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR4:[0-9]+]] 346 // CHECK1-NEXT: [[TMP13:%.*]] = load i16, i16* [[AA]], align 2 347 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 348 // CHECK1-NEXT: store i16 [[TMP13]], i16* [[CONV2]], align 2 349 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8 350 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 351 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64* 352 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP16]], align 8 353 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 354 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 355 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[TMP18]], align 8 356 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 357 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 358 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 359 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 360 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 361 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 362 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 363 // CHECK1: omp_offload.failed: 364 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR4]] 365 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 366 // CHECK1: omp_offload.cont: 367 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 368 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32* 369 // CHECK1-NEXT: store i32 [[TMP24]], i32* [[CONV4]], align 4 370 // CHECK1-NEXT: [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8 371 // CHECK1-NEXT: [[TMP26:%.*]] = load i16, i16* [[AA]], align 2 372 // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16* 373 // CHECK1-NEXT: store i16 [[TMP26]], i16* [[CONV6]], align 2 374 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8 375 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4 376 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10 377 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 378 // CHECK1: omp_if.then: 379 // CHECK1-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 380 // CHECK1-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64* 381 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP30]], align 8 382 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 383 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64* 384 // CHECK1-NEXT: store i64 [[TMP25]], i64* [[TMP32]], align 8 385 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0 386 // CHECK1-NEXT: store i8* null, i8** [[TMP33]], align 8 387 // CHECK1-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1 388 // CHECK1-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64* 389 // CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP35]], align 8 390 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1 391 // CHECK1-NEXT: [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64* 392 // CHECK1-NEXT: store i64 [[TMP27]], i64* [[TMP37]], align 8 393 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1 394 // CHECK1-NEXT: store i8* null, i8** [[TMP38]], align 8 395 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0 396 // CHECK1-NEXT: [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0 397 // CHECK1-NEXT: [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 398 // CHECK1-NEXT: [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0 399 // CHECK1-NEXT: br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]] 400 // CHECK1: omp_offload.failed10: 401 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 402 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT11]] 403 // CHECK1: omp_offload.cont11: 404 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 405 // CHECK1: omp_if.else: 406 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR4]] 407 // CHECK1-NEXT: br label [[OMP_IF_END]] 408 // CHECK1: omp_if.end: 409 // CHECK1-NEXT: [[TMP43:%.*]] = load i32, i32* [[A]], align 4 410 // CHECK1-NEXT: [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32* 411 // CHECK1-NEXT: store i32 [[TMP43]], i32* [[CONV13]], align 4 412 // CHECK1-NEXT: [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8 413 // CHECK1-NEXT: [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4 414 // CHECK1-NEXT: [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20 415 // CHECK1-NEXT: br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]] 416 // CHECK1: omp_if.then15: 417 // CHECK1-NEXT: [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4 418 // CHECK1-NEXT: [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]] 419 // CHECK1-NEXT: [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8 420 // CHECK1-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 421 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP49]], i8* align 8 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i64 72, i1 false) 422 // CHECK1-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 423 // CHECK1-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i64* 424 // CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP51]], align 8 425 // CHECK1-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 426 // CHECK1-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i64* 427 // CHECK1-NEXT: store i64 [[TMP44]], i64* [[TMP53]], align 8 428 // CHECK1-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0 429 // CHECK1-NEXT: store i8* null, i8** [[TMP54]], align 8 430 // CHECK1-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1 431 // CHECK1-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 432 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8 433 // CHECK1-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1 434 // CHECK1-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 435 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8 436 // CHECK1-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1 437 // CHECK1-NEXT: store i8* null, i8** [[TMP59]], align 8 438 // CHECK1-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2 439 // CHECK1-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i64* 440 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP61]], align 8 441 // CHECK1-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2 442 // CHECK1-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i64* 443 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP63]], align 8 444 // CHECK1-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2 445 // CHECK1-NEXT: store i8* null, i8** [[TMP64]], align 8 446 // CHECK1-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3 447 // CHECK1-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 448 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP66]], align 8 449 // CHECK1-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3 450 // CHECK1-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 451 // CHECK1-NEXT: store float* [[VLA]], float** [[TMP68]], align 8 452 // CHECK1-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 453 // CHECK1-NEXT: store i64 [[TMP46]], i64* [[TMP69]], align 8 454 // CHECK1-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3 455 // CHECK1-NEXT: store i8* null, i8** [[TMP70]], align 8 456 // CHECK1-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4 457 // CHECK1-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 458 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 8 459 // CHECK1-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4 460 // CHECK1-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 461 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8 462 // CHECK1-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4 463 // CHECK1-NEXT: store i8* null, i8** [[TMP75]], align 8 464 // CHECK1-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5 465 // CHECK1-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i64* 466 // CHECK1-NEXT: store i64 5, i64* [[TMP77]], align 8 467 // CHECK1-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5 468 // CHECK1-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i64* 469 // CHECK1-NEXT: store i64 5, i64* [[TMP79]], align 8 470 // CHECK1-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5 471 // CHECK1-NEXT: store i8* null, i8** [[TMP80]], align 8 472 // CHECK1-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6 473 // CHECK1-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64* 474 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP82]], align 8 475 // CHECK1-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6 476 // CHECK1-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i64* 477 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP84]], align 8 478 // CHECK1-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6 479 // CHECK1-NEXT: store i8* null, i8** [[TMP85]], align 8 480 // CHECK1-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7 481 // CHECK1-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 482 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP87]], align 8 483 // CHECK1-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7 484 // CHECK1-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 485 // CHECK1-NEXT: store double* [[VLA1]], double** [[TMP89]], align 8 486 // CHECK1-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 487 // CHECK1-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 8 488 // CHECK1-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7 489 // CHECK1-NEXT: store i8* null, i8** [[TMP91]], align 8 490 // CHECK1-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8 491 // CHECK1-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 492 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 8 493 // CHECK1-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8 494 // CHECK1-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 495 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 8 496 // CHECK1-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8 497 // CHECK1-NEXT: store i8* null, i8** [[TMP96]], align 8 498 // CHECK1-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0 499 // CHECK1-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0 500 // CHECK1-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 501 // CHECK1-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 502 // CHECK1-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 503 // CHECK1-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]] 504 // CHECK1: omp_offload.failed19: 505 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 506 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT20]] 507 // CHECK1: omp_offload.cont20: 508 // CHECK1-NEXT: br label [[OMP_IF_END22:%.*]] 509 // CHECK1: omp_if.else21: 510 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 511 // CHECK1-NEXT: br label [[OMP_IF_END22]] 512 // CHECK1: omp_if.end22: 513 // CHECK1-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 514 // CHECK1-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 515 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 516 // CHECK1-NEXT: ret i32 [[TMP102]] 517 // 518 // 519 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 520 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] { 521 // CHECK1-NEXT: entry: 522 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 523 // CHECK1-NEXT: ret void 524 // 525 // 526 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 527 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 528 // CHECK1-NEXT: entry: 529 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 530 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 531 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 532 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 533 // CHECK1-NEXT: ret void 534 // 535 // 536 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry. 537 // CHECK1-SAME: (i32 noundef signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 538 // CHECK1-NEXT: entry: 539 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 540 // CHECK1-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8 541 // CHECK1-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8 542 // CHECK1-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8 543 // CHECK1-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8 544 // CHECK1-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8 545 // CHECK1-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 546 // CHECK1-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8 547 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 548 // CHECK1-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 549 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 550 // CHECK1-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8 551 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 552 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 553 // CHECK1-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 554 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8 555 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 556 // CHECK1-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 557 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]]) 558 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]]) 559 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]]) 560 // CHECK1-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]]) 561 // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21 562 // CHECK1-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !21 563 // CHECK1-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !21 564 // CHECK1-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !21 565 // CHECK1-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !21 566 // CHECK1-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 567 // CHECK1-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !21 568 // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 569 // CHECK1-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 570 // CHECK1-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 571 // CHECK1: omp_offload.failed.i: 572 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 573 // CHECK1-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 574 // CHECK1: .omp_outlined..1.exit: 575 // CHECK1-NEXT: ret i32 0 576 // 577 // 578 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 579 // CHECK1-SAME: (i64 noundef [[A:%.*]]) #[[ATTR3]] { 580 // CHECK1-NEXT: entry: 581 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 582 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 583 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 584 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 585 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 586 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32* 587 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV1]], align 4 588 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 589 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 590 // CHECK1-NEXT: ret void 591 // 592 // 593 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 594 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]]) #[[ATTR3]] { 595 // CHECK1-NEXT: entry: 596 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 597 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 598 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 599 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 600 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 601 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 602 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 603 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 604 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 605 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 606 // CHECK1-NEXT: ret void 607 // 608 // 609 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 610 // CHECK1-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR2]] { 611 // CHECK1-NEXT: entry: 612 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 613 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 614 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 615 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 616 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 617 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 618 // CHECK1-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 619 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 620 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 621 // CHECK1-NEXT: ret void 622 // 623 // 624 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 625 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 626 // CHECK1-NEXT: entry: 627 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 628 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 629 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 630 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 631 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 632 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 633 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 634 // CHECK1-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 635 // CHECK1-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 636 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 637 // CHECK1-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 638 // CHECK1-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 639 // CHECK1-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 640 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 641 // CHECK1-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 642 // CHECK1-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 643 // CHECK1-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 644 // CHECK1: .cancel.exit: 645 // CHECK1-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 646 // CHECK1-NEXT: br label [[DOTCANCEL_CONTINUE]] 647 // CHECK1: .cancel.continue: 648 // CHECK1-NEXT: ret void 649 // 650 // 651 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 652 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR2]] { 653 // CHECK1-NEXT: entry: 654 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 655 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 656 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 657 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 658 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 659 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 660 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 661 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 662 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 663 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 664 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 665 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 666 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 667 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 668 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 669 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 670 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 671 // CHECK1-NEXT: ret void 672 // 673 // 674 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 675 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR3]] { 676 // CHECK1-NEXT: entry: 677 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 678 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 679 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 680 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 681 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 682 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 683 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 684 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 685 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 686 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 687 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 688 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 689 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 690 // CHECK1-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 691 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 692 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 693 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 694 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 695 // CHECK1-NEXT: ret void 696 // 697 // 698 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 699 // CHECK1-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] { 700 // CHECK1-NEXT: entry: 701 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 702 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 703 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 704 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 705 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 706 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 707 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 708 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 709 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 710 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 711 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 712 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 713 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 714 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 715 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 716 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 717 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 718 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 719 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 720 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 721 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 722 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 723 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 724 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 725 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 726 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 727 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 728 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 729 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 730 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 731 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 732 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 733 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 734 // CHECK1-NEXT: ret void 735 // 736 // 737 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 738 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR3]] { 739 // CHECK1-NEXT: entry: 740 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 741 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 742 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 743 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 744 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 745 // CHECK1-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 746 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 747 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 748 // CHECK1-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 749 // CHECK1-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 750 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 751 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 752 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 753 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 754 // CHECK1-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 755 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 756 // CHECK1-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 757 // CHECK1-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 758 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 759 // CHECK1-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 760 // CHECK1-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 761 // CHECK1-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 762 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 763 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 764 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 765 // CHECK1-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 766 // CHECK1-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 767 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 768 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 769 // CHECK1-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 770 // CHECK1-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 771 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 772 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 773 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 774 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 775 // CHECK1-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 776 // CHECK1-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 777 // CHECK1-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 778 // CHECK1-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 779 // CHECK1-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 780 // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 781 // CHECK1-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 782 // CHECK1-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 783 // CHECK1-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 784 // CHECK1-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 785 // CHECK1-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 786 // CHECK1-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 787 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 788 // CHECK1-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 789 // CHECK1-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 790 // CHECK1-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 791 // CHECK1-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 792 // CHECK1-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 793 // CHECK1-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 794 // CHECK1-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 795 // CHECK1-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 796 // CHECK1-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 797 // CHECK1-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 798 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 799 // CHECK1-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 800 // CHECK1-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 801 // CHECK1-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 802 // CHECK1-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 803 // CHECK1-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 804 // CHECK1-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 805 // CHECK1-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 806 // CHECK1-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 807 // CHECK1-NEXT: ret void 808 // 809 // 810 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari 811 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 812 // CHECK1-NEXT: entry: 813 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 814 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 815 // CHECK1-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8 816 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 817 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 818 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 819 // CHECK1-NEXT: [[CALL:%.*]] = call noundef signext i32 @_Z3fooi(i32 noundef signext [[TMP0]]) 820 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 821 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 822 // CHECK1-NEXT: store i32 [[ADD]], i32* [[A]], align 4 823 // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 824 // CHECK1-NEXT: [[CALL1:%.*]] = call noundef signext i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 8 dereferenceable(8) [[S]], i32 noundef signext [[TMP2]]) 825 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 826 // CHECK1-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 827 // CHECK1-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 828 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 829 // CHECK1-NEXT: [[CALL3:%.*]] = call noundef signext i32 @_ZL7fstatici(i32 noundef signext [[TMP4]]) 830 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 831 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 832 // CHECK1-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 833 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 834 // CHECK1-NEXT: [[CALL5:%.*]] = call noundef signext i32 @_Z9ftemplateIiET_i(i32 noundef signext [[TMP6]]) 835 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 836 // CHECK1-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 837 // CHECK1-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 838 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 839 // CHECK1-NEXT: ret i32 [[TMP8]] 840 // 841 // 842 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 843 // CHECK1-SAME: (%struct.S1* noundef nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat align 2 { 844 // CHECK1-NEXT: entry: 845 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 846 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 847 // CHECK1-NEXT: [[B:%.*]] = alloca i32, align 4 848 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 849 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 850 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 851 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8 852 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8 853 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8 854 // CHECK1-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8 855 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 856 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 857 // CHECK1-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 858 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 859 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 860 // CHECK1-NEXT: store i32 [[ADD]], i32* [[B]], align 4 861 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 862 // CHECK1-NEXT: [[TMP2:%.*]] = zext i32 [[TMP1]] to i64 863 // CHECK1-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 864 // CHECK1-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8 865 // CHECK1-NEXT: [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]] 866 // CHECK1-NEXT: [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2 867 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8 868 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[B]], align 4 869 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32* 870 // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV]], align 4 871 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8 872 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 873 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60 874 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 875 // CHECK1: omp_if.then: 876 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 877 // CHECK1-NEXT: [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]] 878 // CHECK1-NEXT: [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2 879 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 880 // CHECK1-NEXT: call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 8 [[TMP10]], i8* align 8 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i64 40, i1 false) 881 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 882 // CHECK1-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 883 // CHECK1-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 8 884 // CHECK1-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 885 // CHECK1-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 886 // CHECK1-NEXT: store double* [[A]], double** [[TMP14]], align 8 887 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 888 // CHECK1-NEXT: store i8* null, i8** [[TMP15]], align 8 889 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 890 // CHECK1-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64* 891 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP17]], align 8 892 // CHECK1-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 893 // CHECK1-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64* 894 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[TMP19]], align 8 895 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 896 // CHECK1-NEXT: store i8* null, i8** [[TMP20]], align 8 897 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 898 // CHECK1-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* 899 // CHECK1-NEXT: store i64 2, i64* [[TMP22]], align 8 900 // CHECK1-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 901 // CHECK1-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i64* 902 // CHECK1-NEXT: store i64 2, i64* [[TMP24]], align 8 903 // CHECK1-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 904 // CHECK1-NEXT: store i8* null, i8** [[TMP25]], align 8 905 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 906 // CHECK1-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* 907 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP27]], align 8 908 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 909 // CHECK1-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64* 910 // CHECK1-NEXT: store i64 [[TMP2]], i64* [[TMP29]], align 8 911 // CHECK1-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 912 // CHECK1-NEXT: store i8* null, i8** [[TMP30]], align 8 913 // CHECK1-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 914 // CHECK1-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 915 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 8 916 // CHECK1-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 917 // CHECK1-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 918 // CHECK1-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 8 919 // CHECK1-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 920 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 8 921 // CHECK1-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4 922 // CHECK1-NEXT: store i8* null, i8** [[TMP36]], align 8 923 // CHECK1-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 924 // CHECK1-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 925 // CHECK1-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 926 // CHECK1-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 927 // CHECK1-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 928 // CHECK1-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 929 // CHECK1: omp_offload.failed: 930 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 931 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 932 // CHECK1: omp_offload.cont: 933 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 934 // CHECK1: omp_if.else: 935 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR4]] 936 // CHECK1-NEXT: br label [[OMP_IF_END]] 937 // CHECK1: omp_if.end: 938 // CHECK1-NEXT: [[TMP42:%.*]] = mul nsw i64 1, [[TMP2]] 939 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP42]] 940 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 941 // CHECK1-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 942 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP43]] to i32 943 // CHECK1-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 944 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP44]] 945 // CHECK1-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 946 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 947 // CHECK1-NEXT: ret i32 [[ADD4]] 948 // 949 // 950 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici 951 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] { 952 // CHECK1-NEXT: entry: 953 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 954 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 955 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 956 // CHECK1-NEXT: [[AAA:%.*]] = alloca i8, align 1 957 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 958 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 959 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 960 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 961 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 962 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 963 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 964 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 965 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 966 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 967 // CHECK1-NEXT: store i8 0, i8* [[AAA]], align 1 968 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 969 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 970 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 971 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 972 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 973 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 974 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 975 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 976 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 977 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 978 // CHECK1-NEXT: store i8 [[TMP4]], i8* [[CONV2]], align 1 979 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 980 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 981 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 982 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 983 // CHECK1: omp_if.then: 984 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 985 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 986 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 987 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 988 // CHECK1-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* 989 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP10]], align 8 990 // CHECK1-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 991 // CHECK1-NEXT: store i8* null, i8** [[TMP11]], align 8 992 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 993 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 994 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 995 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 996 // CHECK1-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64* 997 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP15]], align 8 998 // CHECK1-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 999 // CHECK1-NEXT: store i8* null, i8** [[TMP16]], align 8 1000 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1001 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64* 1002 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP18]], align 8 1003 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1004 // CHECK1-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* 1005 // CHECK1-NEXT: store i64 [[TMP5]], i64* [[TMP20]], align 8 1006 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1007 // CHECK1-NEXT: store i8* null, i8** [[TMP21]], align 8 1008 // CHECK1-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1009 // CHECK1-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 1010 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8 1011 // CHECK1-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1012 // CHECK1-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 1013 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8 1014 // CHECK1-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 1015 // CHECK1-NEXT: store i8* null, i8** [[TMP26]], align 8 1016 // CHECK1-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1017 // CHECK1-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1018 // CHECK1-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1019 // CHECK1-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 1020 // CHECK1-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1021 // CHECK1: omp_offload.failed: 1022 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1023 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1024 // CHECK1: omp_offload.cont: 1025 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1026 // CHECK1: omp_if.else: 1027 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 1028 // CHECK1-NEXT: br label [[OMP_IF_END]] 1029 // CHECK1: omp_if.end: 1030 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 1031 // CHECK1-NEXT: ret i32 [[TMP31]] 1032 // 1033 // 1034 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 1035 // CHECK1-SAME: (i32 noundef signext [[N:%.*]]) #[[ATTR0]] comdat { 1036 // CHECK1-NEXT: entry: 1037 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1038 // CHECK1-NEXT: [[A:%.*]] = alloca i32, align 4 1039 // CHECK1-NEXT: [[AA:%.*]] = alloca i16, align 2 1040 // CHECK1-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1041 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1042 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1043 // CHECK1-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8 1044 // CHECK1-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8 1045 // CHECK1-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8 1046 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1047 // CHECK1-NEXT: store i32 0, i32* [[A]], align 4 1048 // CHECK1-NEXT: store i16 0, i16* [[AA]], align 2 1049 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1050 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1051 // CHECK1-NEXT: store i32 [[TMP0]], i32* [[CONV]], align 4 1052 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 1053 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1054 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1055 // CHECK1-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1056 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1057 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1058 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 1059 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1060 // CHECK1: omp_if.then: 1061 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1062 // CHECK1-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64* 1063 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP6]], align 8 1064 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1065 // CHECK1-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64* 1066 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP8]], align 8 1067 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 1068 // CHECK1-NEXT: store i8* null, i8** [[TMP9]], align 8 1069 // CHECK1-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1070 // CHECK1-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64* 1071 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP11]], align 8 1072 // CHECK1-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1073 // CHECK1-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64* 1074 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[TMP13]], align 8 1075 // CHECK1-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 1076 // CHECK1-NEXT: store i8* null, i8** [[TMP14]], align 8 1077 // CHECK1-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1078 // CHECK1-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 1079 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8 1080 // CHECK1-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1081 // CHECK1-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 1082 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8 1083 // CHECK1-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 1084 // CHECK1-NEXT: store i8* null, i8** [[TMP19]], align 8 1085 // CHECK1-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1086 // CHECK1-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1087 // CHECK1-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1088 // CHECK1-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 1089 // CHECK1-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1090 // CHECK1: omp_offload.failed: 1091 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1092 // CHECK1-NEXT: br label [[OMP_OFFLOAD_CONT]] 1093 // CHECK1: omp_offload.cont: 1094 // CHECK1-NEXT: br label [[OMP_IF_END:%.*]] 1095 // CHECK1: omp_if.else: 1096 // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 1097 // CHECK1-NEXT: br label [[OMP_IF_END]] 1098 // CHECK1: omp_if.end: 1099 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 1100 // CHECK1-NEXT: ret i32 [[TMP24]] 1101 // 1102 // 1103 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 1104 // CHECK1-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 1105 // CHECK1-NEXT: entry: 1106 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1107 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1108 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1109 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1110 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1111 // CHECK1-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 1112 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1113 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1114 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1115 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1116 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1117 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1118 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1119 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1120 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1121 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1122 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1123 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 1124 // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 1125 // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 1126 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 1127 // CHECK1-NEXT: ret void 1128 // 1129 // 1130 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10 1131 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 1132 // CHECK1-NEXT: entry: 1133 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1134 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1135 // CHECK1-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 1136 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 1137 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1138 // CHECK1-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 1139 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 1140 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1141 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1142 // CHECK1-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 1143 // CHECK1-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 1144 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1145 // CHECK1-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 1146 // CHECK1-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 1147 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 1148 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 1149 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1150 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 1151 // CHECK1-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 1152 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 1153 // CHECK1-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 1154 // CHECK1-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 1155 // CHECK1-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 1156 // CHECK1-NEXT: store double [[ADD]], double* [[A]], align 8 1157 // CHECK1-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 1158 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 1159 // CHECK1-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 1160 // CHECK1-NEXT: store double [[INC]], double* [[A4]], align 8 1161 // CHECK1-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 1162 // CHECK1-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 1163 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 1164 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 1165 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 1166 // CHECK1-NEXT: ret void 1167 // 1168 // 1169 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 1170 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1171 // CHECK1-NEXT: entry: 1172 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1173 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1174 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1175 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1176 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1177 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1178 // CHECK1-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 1179 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1180 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1181 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1182 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1183 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1184 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1185 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1186 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1187 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1188 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1189 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 1190 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1191 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1192 // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1193 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 1194 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1195 // CHECK1-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 1196 // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 1197 // CHECK1-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 1198 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 1199 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 1200 // CHECK1-NEXT: ret void 1201 // 1202 // 1203 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..13 1204 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1205 // CHECK1-NEXT: entry: 1206 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1207 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1208 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1209 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1210 // CHECK1-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 1211 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1212 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1213 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1214 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1215 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1216 // CHECK1-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 1217 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1218 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1219 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1220 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 1221 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1222 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1223 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1224 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1225 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1226 // CHECK1-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 1227 // CHECK1-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 1228 // CHECK1-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 1229 // CHECK1-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 1230 // CHECK1-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 1231 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 1232 // CHECK1-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 1233 // CHECK1-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 1234 // CHECK1-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 1235 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1236 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1237 // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 1238 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 1239 // CHECK1-NEXT: ret void 1240 // 1241 // 1242 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 1243 // CHECK1-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 1244 // CHECK1-NEXT: entry: 1245 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1246 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1247 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1248 // CHECK1-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 1249 // CHECK1-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 1250 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1251 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1252 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1253 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1254 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1255 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1256 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1257 // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 1258 // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 1259 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 1260 // CHECK1-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 1261 // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 1262 // CHECK1-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 1263 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 1264 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 1265 // CHECK1-NEXT: ret void 1266 // 1267 // 1268 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..16 1269 // CHECK1-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 1270 // CHECK1-NEXT: entry: 1271 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1272 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1273 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 1274 // CHECK1-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 1275 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 1276 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1277 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1278 // CHECK1-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 1279 // CHECK1-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 1280 // CHECK1-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 1281 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 1282 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 1283 // CHECK1-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 1284 // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 1285 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 1286 // CHECK1-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 1287 // CHECK1-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 1288 // CHECK1-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 1289 // CHECK1-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 1290 // CHECK1-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 1291 // CHECK1-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 1292 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 1293 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 1294 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 1295 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 1296 // CHECK1-NEXT: ret void 1297 // 1298 // 1299 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 1300 // CHECK1-SAME: () #[[ATTR8:[0-9]+]] { 1301 // CHECK1-NEXT: entry: 1302 // CHECK1-NEXT: call void @__tgt_register_requires(i64 1) 1303 // CHECK1-NEXT: ret void 1304 // 1305 // 1306 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi 1307 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0:[0-9]+]] { 1308 // CHECK3-NEXT: entry: 1309 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1310 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1311 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1312 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x float], align 4 1313 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1314 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1315 // CHECK3-NEXT: [[C:%.*]] = alloca [5 x [10 x double]], align 8 1316 // CHECK3-NEXT: [[__VLA_EXPR1:%.*]] = alloca i32, align 4 1317 // CHECK3-NEXT: [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4 1318 // CHECK3-NEXT: [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 1319 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1320 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1321 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4 1322 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4 1323 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4 1324 // CHECK3-NEXT: [[A_CASTED2:%.*]] = alloca i32, align 4 1325 // CHECK3-NEXT: [[AA_CASTED3:%.*]] = alloca i32, align 4 1326 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4 1327 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4 1328 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4 1329 // CHECK3-NEXT: [[A_CASTED10:%.*]] = alloca i32, align 4 1330 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4 1331 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4 1332 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4 1333 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4 1334 // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]]) 1335 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1336 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1337 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1338 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1339 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1340 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1341 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4 1342 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 1343 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1344 // CHECK3-NEXT: [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]] 1345 // CHECK3-NEXT: [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8 1346 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4 1347 // CHECK3-NEXT: [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1) 1348 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates* 1349 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0 1350 // CHECK3-NEXT: [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]]) 1351 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A]], align 4 1352 // CHECK3-NEXT: store i32 [[TMP9]], i32* [[A_CASTED]], align 4 1353 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4 1354 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR4:[0-9]+]] 1355 // CHECK3-NEXT: [[TMP11:%.*]] = load i16, i16* [[AA]], align 2 1356 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1357 // CHECK3-NEXT: store i16 [[TMP11]], i16* [[CONV]], align 2 1358 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1359 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1360 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32* 1361 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP14]], align 4 1362 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1363 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32* 1364 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[TMP16]], align 4 1365 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1366 // CHECK3-NEXT: store i8* null, i8** [[TMP17]], align 4 1367 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1368 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1369 // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1370 // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 1371 // CHECK3-NEXT: br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1372 // CHECK3: omp_offload.failed: 1373 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR4]] 1374 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1375 // CHECK3: omp_offload.cont: 1376 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[A]], align 4 1377 // CHECK3-NEXT: store i32 [[TMP22]], i32* [[A_CASTED2]], align 4 1378 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4 1379 // CHECK3-NEXT: [[TMP24:%.*]] = load i16, i16* [[AA]], align 2 1380 // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16* 1381 // CHECK3-NEXT: store i16 [[TMP24]], i16* [[CONV4]], align 2 1382 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4 1383 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4 1384 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10 1385 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1386 // CHECK3: omp_if.then: 1387 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 1388 // CHECK3-NEXT: [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32* 1389 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP28]], align 4 1390 // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 1391 // CHECK3-NEXT: [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32* 1392 // CHECK3-NEXT: store i32 [[TMP23]], i32* [[TMP30]], align 4 1393 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0 1394 // CHECK3-NEXT: store i8* null, i8** [[TMP31]], align 4 1395 // CHECK3-NEXT: [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1 1396 // CHECK3-NEXT: [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32* 1397 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP33]], align 4 1398 // CHECK3-NEXT: [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1 1399 // CHECK3-NEXT: [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32* 1400 // CHECK3-NEXT: store i32 [[TMP25]], i32* [[TMP35]], align 4 1401 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1 1402 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 1403 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0 1404 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0 1405 // CHECK3-NEXT: [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1406 // CHECK3-NEXT: [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0 1407 // CHECK3-NEXT: br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]] 1408 // CHECK3: omp_offload.failed8: 1409 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 1410 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT9]] 1411 // CHECK3: omp_offload.cont9: 1412 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1413 // CHECK3: omp_if.else: 1414 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR4]] 1415 // CHECK3-NEXT: br label [[OMP_IF_END]] 1416 // CHECK3: omp_if.end: 1417 // CHECK3-NEXT: [[TMP41:%.*]] = load i32, i32* [[A]], align 4 1418 // CHECK3-NEXT: store i32 [[TMP41]], i32* [[A_CASTED10]], align 4 1419 // CHECK3-NEXT: [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4 1420 // CHECK3-NEXT: [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4 1421 // CHECK3-NEXT: [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20 1422 // CHECK3-NEXT: br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]] 1423 // CHECK3: omp_if.then12: 1424 // CHECK3-NEXT: [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4 1425 // CHECK3-NEXT: [[TMP45:%.*]] = sext i32 [[TMP44]] to i64 1426 // CHECK3-NEXT: [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]] 1427 // CHECK3-NEXT: [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8 1428 // CHECK3-NEXT: [[TMP48:%.*]] = sext i32 [[TMP47]] to i64 1429 // CHECK3-NEXT: [[TMP49:%.*]] = bitcast [9 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1430 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP49]], i8* align 4 bitcast ([9 x i64]* @.offload_sizes.8 to i8*), i32 72, i1 false) 1431 // CHECK3-NEXT: [[TMP50:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 1432 // CHECK3-NEXT: [[TMP51:%.*]] = bitcast i8** [[TMP50]] to i32* 1433 // CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP51]], align 4 1434 // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 1435 // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32* 1436 // CHECK3-NEXT: store i32 [[TMP42]], i32* [[TMP53]], align 4 1437 // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0 1438 // CHECK3-NEXT: store i8* null, i8** [[TMP54]], align 4 1439 // CHECK3-NEXT: [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1 1440 // CHECK3-NEXT: [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]** 1441 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4 1442 // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1 1443 // CHECK3-NEXT: [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]** 1444 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4 1445 // CHECK3-NEXT: [[TMP59:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1 1446 // CHECK3-NEXT: store i8* null, i8** [[TMP59]], align 4 1447 // CHECK3-NEXT: [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2 1448 // CHECK3-NEXT: [[TMP61:%.*]] = bitcast i8** [[TMP60]] to i32* 1449 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP61]], align 4 1450 // CHECK3-NEXT: [[TMP62:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2 1451 // CHECK3-NEXT: [[TMP63:%.*]] = bitcast i8** [[TMP62]] to i32* 1452 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP63]], align 4 1453 // CHECK3-NEXT: [[TMP64:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2 1454 // CHECK3-NEXT: store i8* null, i8** [[TMP64]], align 4 1455 // CHECK3-NEXT: [[TMP65:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3 1456 // CHECK3-NEXT: [[TMP66:%.*]] = bitcast i8** [[TMP65]] to float** 1457 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP66]], align 4 1458 // CHECK3-NEXT: [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3 1459 // CHECK3-NEXT: [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float** 1460 // CHECK3-NEXT: store float* [[VLA]], float** [[TMP68]], align 4 1461 // CHECK3-NEXT: [[TMP69:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3 1462 // CHECK3-NEXT: store i64 [[TMP45]], i64* [[TMP69]], align 4 1463 // CHECK3-NEXT: [[TMP70:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3 1464 // CHECK3-NEXT: store i8* null, i8** [[TMP70]], align 4 1465 // CHECK3-NEXT: [[TMP71:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4 1466 // CHECK3-NEXT: [[TMP72:%.*]] = bitcast i8** [[TMP71]] to [5 x [10 x double]]** 1467 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP72]], align 4 1468 // CHECK3-NEXT: [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4 1469 // CHECK3-NEXT: [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]** 1470 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4 1471 // CHECK3-NEXT: [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4 1472 // CHECK3-NEXT: store i8* null, i8** [[TMP75]], align 4 1473 // CHECK3-NEXT: [[TMP76:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5 1474 // CHECK3-NEXT: [[TMP77:%.*]] = bitcast i8** [[TMP76]] to i32* 1475 // CHECK3-NEXT: store i32 5, i32* [[TMP77]], align 4 1476 // CHECK3-NEXT: [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5 1477 // CHECK3-NEXT: [[TMP79:%.*]] = bitcast i8** [[TMP78]] to i32* 1478 // CHECK3-NEXT: store i32 5, i32* [[TMP79]], align 4 1479 // CHECK3-NEXT: [[TMP80:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5 1480 // CHECK3-NEXT: store i8* null, i8** [[TMP80]], align 4 1481 // CHECK3-NEXT: [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6 1482 // CHECK3-NEXT: [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32* 1483 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP82]], align 4 1484 // CHECK3-NEXT: [[TMP83:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6 1485 // CHECK3-NEXT: [[TMP84:%.*]] = bitcast i8** [[TMP83]] to i32* 1486 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP84]], align 4 1487 // CHECK3-NEXT: [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6 1488 // CHECK3-NEXT: store i8* null, i8** [[TMP85]], align 4 1489 // CHECK3-NEXT: [[TMP86:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7 1490 // CHECK3-NEXT: [[TMP87:%.*]] = bitcast i8** [[TMP86]] to double** 1491 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP87]], align 4 1492 // CHECK3-NEXT: [[TMP88:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7 1493 // CHECK3-NEXT: [[TMP89:%.*]] = bitcast i8** [[TMP88]] to double** 1494 // CHECK3-NEXT: store double* [[VLA1]], double** [[TMP89]], align 4 1495 // CHECK3-NEXT: [[TMP90:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7 1496 // CHECK3-NEXT: store i64 [[TMP48]], i64* [[TMP90]], align 4 1497 // CHECK3-NEXT: [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7 1498 // CHECK3-NEXT: store i8* null, i8** [[TMP91]], align 4 1499 // CHECK3-NEXT: [[TMP92:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8 1500 // CHECK3-NEXT: [[TMP93:%.*]] = bitcast i8** [[TMP92]] to %struct.TT** 1501 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP93]], align 4 1502 // CHECK3-NEXT: [[TMP94:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8 1503 // CHECK3-NEXT: [[TMP95:%.*]] = bitcast i8** [[TMP94]] to %struct.TT** 1504 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[TMP95]], align 4 1505 // CHECK3-NEXT: [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8 1506 // CHECK3-NEXT: store i8* null, i8** [[TMP96]], align 4 1507 // CHECK3-NEXT: [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0 1508 // CHECK3-NEXT: [[TMP98:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0 1509 // CHECK3-NEXT: [[TMP99:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1510 // CHECK3-NEXT: [[TMP100:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP97]], i8** [[TMP98]], i64* [[TMP99]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.9, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1511 // CHECK3-NEXT: [[TMP101:%.*]] = icmp ne i32 [[TMP100]], 0 1512 // CHECK3-NEXT: br i1 [[TMP101]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]] 1513 // CHECK3: omp_offload.failed16: 1514 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 1515 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT17]] 1516 // CHECK3: omp_offload.cont17: 1517 // CHECK3-NEXT: br label [[OMP_IF_END19:%.*]] 1518 // CHECK3: omp_if.else18: 1519 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR4]] 1520 // CHECK3-NEXT: br label [[OMP_IF_END19]] 1521 // CHECK3: omp_if.end19: 1522 // CHECK3-NEXT: [[TMP102:%.*]] = load i32, i32* [[A]], align 4 1523 // CHECK3-NEXT: [[TMP103:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 1524 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP103]]) 1525 // CHECK3-NEXT: ret i32 [[TMP102]] 1526 // 1527 // 1528 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 1529 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] { 1530 // CHECK3-NEXT: entry: 1531 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 1532 // CHECK3-NEXT: ret void 1533 // 1534 // 1535 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 1536 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] { 1537 // CHECK3-NEXT: entry: 1538 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1539 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1540 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1541 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1542 // CHECK3-NEXT: ret void 1543 // 1544 // 1545 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry. 1546 // CHECK3-SAME: (i32 noundef [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias noundef [[TMP1:%.*]]) #[[ATTR5:[0-9]+]] { 1547 // CHECK3-NEXT: entry: 1548 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4 1549 // CHECK3-NEXT: [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4 1550 // CHECK3-NEXT: [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4 1551 // CHECK3-NEXT: [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4 1552 // CHECK3-NEXT: [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4 1553 // CHECK3-NEXT: [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4 1554 // CHECK3-NEXT: [[DOTADDR:%.*]] = alloca i32, align 4 1555 // CHECK3-NEXT: [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4 1556 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[DOTADDR]], align 4 1557 // CHECK3-NEXT: store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 1558 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4 1559 // CHECK3-NEXT: [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4 1560 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0 1561 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2 1562 // CHECK3-NEXT: [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0 1563 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4 1564 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon* 1565 // CHECK3-NEXT: [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8* 1566 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META13:![0-9]+]]) 1567 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]]) 1568 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]]) 1569 // CHECK3-NEXT: call void @llvm.experimental.noalias.scope.decl(metadata [[META20:![0-9]+]]) 1570 // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !22 1571 // CHECK3-NEXT: store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !22 1572 // CHECK3-NEXT: store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !22 1573 // CHECK3-NEXT: store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !22 1574 // CHECK3-NEXT: store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !22 1575 // CHECK3-NEXT: store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 1576 // CHECK3-NEXT: [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !22 1577 // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0, i32 0, i8* null, i32 0, i8* null) #[[ATTR4]] 1578 // CHECK3-NEXT: [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0 1579 // CHECK3-NEXT: br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]] 1580 // CHECK3: omp_offload.failed.i: 1581 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR4]] 1582 // CHECK3-NEXT: br label [[DOTOMP_OUTLINED__1_EXIT]] 1583 // CHECK3: .omp_outlined..1.exit: 1584 // CHECK3-NEXT: ret i32 0 1585 // 1586 // 1587 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104 1588 // CHECK3-SAME: (i32 noundef [[A:%.*]]) #[[ATTR3]] { 1589 // CHECK3-NEXT: entry: 1590 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1591 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1592 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1593 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1594 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 1595 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 1596 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 1597 // CHECK3-NEXT: ret void 1598 // 1599 // 1600 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 1601 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]]) #[[ATTR3]] { 1602 // CHECK3-NEXT: entry: 1603 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1604 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1605 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1606 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1607 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1608 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1609 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1610 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1611 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1612 // CHECK3-NEXT: ret void 1613 // 1614 // 1615 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 1616 // CHECK3-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR2]] { 1617 // CHECK3-NEXT: entry: 1618 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1619 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1620 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1621 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1622 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 1623 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1624 // CHECK3-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 1625 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1626 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 1627 // CHECK3-NEXT: ret void 1628 // 1629 // 1630 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 1631 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 1632 // CHECK3-NEXT: entry: 1633 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1634 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1635 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1636 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1637 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1638 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1639 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1640 // CHECK3-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 1641 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 1642 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 1643 // CHECK3-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 1644 // CHECK3-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 1645 // CHECK3-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 1646 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 1647 // CHECK3-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 1648 // CHECK3-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 1649 // CHECK3-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 1650 // CHECK3: .cancel.exit: 1651 // CHECK3-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 1652 // CHECK3-NEXT: br label [[DOTCANCEL_CONTINUE]] 1653 // CHECK3: .cancel.continue: 1654 // CHECK3-NEXT: ret void 1655 // 1656 // 1657 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 1658 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR2]] { 1659 // CHECK3-NEXT: entry: 1660 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1661 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1662 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1663 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1664 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1665 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1666 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1667 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1668 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 1669 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 1670 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 1671 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1672 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 1673 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1674 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 1675 // CHECK3-NEXT: ret void 1676 // 1677 // 1678 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 1679 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR3]] { 1680 // CHECK3-NEXT: entry: 1681 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1682 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1683 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1684 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 1685 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1686 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1687 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1688 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 1689 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 1690 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 1691 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1692 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1693 // CHECK3-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 1694 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 1695 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 1696 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 1697 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 1698 // CHECK3-NEXT: ret void 1699 // 1700 // 1701 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 1702 // CHECK3-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] { 1703 // CHECK3-NEXT: entry: 1704 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1705 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 1706 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1707 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 1708 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 1709 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1710 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 1711 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 1712 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 1713 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1714 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1715 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 1716 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1717 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 1718 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 1719 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1720 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 1721 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 1722 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 1723 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 1724 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1725 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 1726 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 1727 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1728 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 1729 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 1730 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 1731 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 1732 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 1733 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 1734 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 1735 // CHECK3-NEXT: ret void 1736 // 1737 // 1738 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 1739 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR3]] { 1740 // CHECK3-NEXT: entry: 1741 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 1742 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 1743 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 1744 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 1745 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 1746 // CHECK3-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 1747 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 1748 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 1749 // CHECK3-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 1750 // CHECK3-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 1751 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 1752 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 1753 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 1754 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 1755 // CHECK3-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 1756 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 1757 // CHECK3-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 1758 // CHECK3-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 1759 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 1760 // CHECK3-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 1761 // CHECK3-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 1762 // CHECK3-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 1763 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 1764 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 1765 // CHECK3-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 1766 // CHECK3-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 1767 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 1768 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 1769 // CHECK3-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 1770 // CHECK3-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 1771 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 1772 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 1773 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 1774 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 1775 // CHECK3-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 1776 // CHECK3-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 1777 // CHECK3-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 1778 // CHECK3-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 1779 // CHECK3-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 1780 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 1781 // CHECK3-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 1782 // CHECK3-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 1783 // CHECK3-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 1784 // CHECK3-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 1785 // CHECK3-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 1786 // CHECK3-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 1787 // CHECK3-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 1788 // CHECK3-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 1789 // CHECK3-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 1790 // CHECK3-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 1791 // CHECK3-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 1792 // CHECK3-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 1793 // CHECK3-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 1794 // CHECK3-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 1795 // CHECK3-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 1796 // CHECK3-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 1797 // CHECK3-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 1798 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 1799 // CHECK3-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 1800 // CHECK3-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 1801 // CHECK3-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 1802 // CHECK3-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 1803 // CHECK3-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 1804 // CHECK3-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 1805 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 1806 // CHECK3-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 1807 // CHECK3-NEXT: ret void 1808 // 1809 // 1810 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari 1811 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 1812 // CHECK3-NEXT: entry: 1813 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1814 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1815 // CHECK3-NEXT: [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4 1816 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1817 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1818 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1819 // CHECK3-NEXT: [[CALL:%.*]] = call noundef i32 @_Z3fooi(i32 noundef [[TMP0]]) 1820 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A]], align 4 1821 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]] 1822 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A]], align 4 1823 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4 1824 // CHECK3-NEXT: [[CALL1:%.*]] = call noundef i32 @_ZN2S12r1Ei(%struct.S1* noundef nonnull align 4 dereferenceable(8) [[S]], i32 noundef [[TMP2]]) 1825 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[A]], align 4 1826 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]] 1827 // CHECK3-NEXT: store i32 [[ADD2]], i32* [[A]], align 4 1828 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 1829 // CHECK3-NEXT: [[CALL3:%.*]] = call noundef i32 @_ZL7fstatici(i32 noundef [[TMP4]]) 1830 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[A]], align 4 1831 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]] 1832 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[A]], align 4 1833 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1834 // CHECK3-NEXT: [[CALL5:%.*]] = call noundef i32 @_Z9ftemplateIiET_i(i32 noundef [[TMP6]]) 1835 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[A]], align 4 1836 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]] 1837 // CHECK3-NEXT: store i32 [[ADD6]], i32* [[A]], align 4 1838 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[A]], align 4 1839 // CHECK3-NEXT: ret i32 [[TMP8]] 1840 // 1841 // 1842 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei 1843 // CHECK3-SAME: (%struct.S1* noundef nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 noundef [[N:%.*]]) #[[ATTR0]] comdat align 2 { 1844 // CHECK3-NEXT: entry: 1845 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 1846 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1847 // CHECK3-NEXT: [[B:%.*]] = alloca i32, align 4 1848 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 4 1849 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i32, align 4 1850 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 1851 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4 1852 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4 1853 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4 1854 // CHECK3-NEXT: [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4 1855 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 1856 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1857 // CHECK3-NEXT: [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 1858 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1859 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 1860 // CHECK3-NEXT: store i32 [[ADD]], i32* [[B]], align 4 1861 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 1862 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1863 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4 1864 // CHECK3-NEXT: [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]] 1865 // CHECK3-NEXT: [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2 1866 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4 1867 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B]], align 4 1868 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 1869 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 1870 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1871 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60 1872 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1873 // CHECK3: omp_if.then: 1874 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0 1875 // CHECK3-NEXT: [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]] 1876 // CHECK3-NEXT: [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2 1877 // CHECK3-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 1878 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast [5 x i64]* [[DOTOFFLOAD_SIZES]] to i8* 1879 // CHECK3-NEXT: call void @llvm.memcpy.p0i8.p0i8.i32(i8* align 4 [[TMP10]], i8* align 4 bitcast ([5 x i64]* @.offload_sizes.11 to i8*), i32 40, i1 false) 1880 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1881 // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to %struct.S1** 1882 // CHECK3-NEXT: store %struct.S1* [[THIS1]], %struct.S1** [[TMP12]], align 4 1883 // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1884 // CHECK3-NEXT: [[TMP14:%.*]] = bitcast i8** [[TMP13]] to double** 1885 // CHECK3-NEXT: store double* [[A]], double** [[TMP14]], align 4 1886 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1887 // CHECK3-NEXT: store i8* null, i8** [[TMP15]], align 4 1888 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1889 // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32* 1890 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP17]], align 4 1891 // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1892 // CHECK3-NEXT: [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32* 1893 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP19]], align 4 1894 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1895 // CHECK3-NEXT: store i8* null, i8** [[TMP20]], align 4 1896 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1897 // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* 1898 // CHECK3-NEXT: store i32 2, i32* [[TMP22]], align 4 1899 // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 1900 // CHECK3-NEXT: [[TMP24:%.*]] = bitcast i8** [[TMP23]] to i32* 1901 // CHECK3-NEXT: store i32 2, i32* [[TMP24]], align 4 1902 // CHECK3-NEXT: [[TMP25:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 1903 // CHECK3-NEXT: store i8* null, i8** [[TMP25]], align 4 1904 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 1905 // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* 1906 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP27]], align 4 1907 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 1908 // CHECK3-NEXT: [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32* 1909 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP29]], align 4 1910 // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 1911 // CHECK3-NEXT: store i8* null, i8** [[TMP30]], align 4 1912 // CHECK3-NEXT: [[TMP31:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4 1913 // CHECK3-NEXT: [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i16** 1914 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP32]], align 4 1915 // CHECK3-NEXT: [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4 1916 // CHECK3-NEXT: [[TMP34:%.*]] = bitcast i8** [[TMP33]] to i16** 1917 // CHECK3-NEXT: store i16* [[VLA]], i16** [[TMP34]], align 4 1918 // CHECK3-NEXT: [[TMP35:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4 1919 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[TMP35]], align 4 1920 // CHECK3-NEXT: [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4 1921 // CHECK3-NEXT: store i8* null, i8** [[TMP36]], align 4 1922 // CHECK3-NEXT: [[TMP37:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1923 // CHECK3-NEXT: [[TMP38:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1924 // CHECK3-NEXT: [[TMP39:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0 1925 // CHECK3-NEXT: [[TMP40:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP37]], i8** [[TMP38]], i64* [[TMP39]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.12, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 1926 // CHECK3-NEXT: [[TMP41:%.*]] = icmp ne i32 [[TMP40]], 0 1927 // CHECK3-NEXT: br i1 [[TMP41]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 1928 // CHECK3: omp_offload.failed: 1929 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 1930 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 1931 // CHECK3: omp_offload.cont: 1932 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 1933 // CHECK3: omp_if.else: 1934 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR4]] 1935 // CHECK3-NEXT: br label [[OMP_IF_END]] 1936 // CHECK3: omp_if.end: 1937 // CHECK3-NEXT: [[TMP42:%.*]] = mul nsw i32 1, [[TMP1]] 1938 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP42]] 1939 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 1940 // CHECK3-NEXT: [[TMP43:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2 1941 // CHECK3-NEXT: [[CONV:%.*]] = sext i16 [[TMP43]] to i32 1942 // CHECK3-NEXT: [[TMP44:%.*]] = load i32, i32* [[B]], align 4 1943 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP44]] 1944 // CHECK3-NEXT: [[TMP45:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4 1945 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP45]]) 1946 // CHECK3-NEXT: ret i32 [[ADD3]] 1947 // 1948 // 1949 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici 1950 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] { 1951 // CHECK3-NEXT: entry: 1952 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1953 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 1954 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 1955 // CHECK3-NEXT: [[AAA:%.*]] = alloca i8, align 1 1956 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 1957 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 1958 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 1959 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 1960 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 1961 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 1962 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 1963 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1964 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 1965 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 1966 // CHECK3-NEXT: store i8 0, i8* [[AAA]], align 1 1967 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 1968 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 1969 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 1970 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 1971 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 1972 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 1973 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 1974 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1 1975 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 1976 // CHECK3-NEXT: store i8 [[TMP4]], i8* [[CONV1]], align 1 1977 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 1978 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1979 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50 1980 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 1981 // CHECK3: omp_if.then: 1982 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 1983 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 1984 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 1985 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 1986 // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* 1987 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP10]], align 4 1988 // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 1989 // CHECK3-NEXT: store i8* null, i8** [[TMP11]], align 4 1990 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 1991 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 1992 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 1993 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 1994 // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32* 1995 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP15]], align 4 1996 // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 1997 // CHECK3-NEXT: store i8* null, i8** [[TMP16]], align 4 1998 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 1999 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32* 2000 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP18]], align 4 2001 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2002 // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* 2003 // CHECK3-NEXT: store i32 [[TMP5]], i32* [[TMP20]], align 4 2004 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2005 // CHECK3-NEXT: store i8* null, i8** [[TMP21]], align 4 2006 // CHECK3-NEXT: [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 2007 // CHECK3-NEXT: [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]** 2008 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4 2009 // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 2010 // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]** 2011 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4 2012 // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 2013 // CHECK3-NEXT: store i8* null, i8** [[TMP26]], align 4 2014 // CHECK3-NEXT: [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2015 // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2016 // CHECK3-NEXT: [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.14, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.15, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2017 // CHECK3-NEXT: [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0 2018 // CHECK3-NEXT: br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2019 // CHECK3: omp_offload.failed: 2020 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 2021 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2022 // CHECK3: omp_offload.cont: 2023 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2024 // CHECK3: omp_if.else: 2025 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR4]] 2026 // CHECK3-NEXT: br label [[OMP_IF_END]] 2027 // CHECK3: omp_if.end: 2028 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[A]], align 4 2029 // CHECK3-NEXT: ret i32 [[TMP31]] 2030 // 2031 // 2032 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i 2033 // CHECK3-SAME: (i32 noundef [[N:%.*]]) #[[ATTR0]] comdat { 2034 // CHECK3-NEXT: entry: 2035 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2036 // CHECK3-NEXT: [[A:%.*]] = alloca i32, align 4 2037 // CHECK3-NEXT: [[AA:%.*]] = alloca i16, align 2 2038 // CHECK3-NEXT: [[B:%.*]] = alloca [10 x i32], align 4 2039 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2040 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2041 // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4 2042 // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4 2043 // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4 2044 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2045 // CHECK3-NEXT: store i32 0, i32* [[A]], align 4 2046 // CHECK3-NEXT: store i16 0, i16* [[AA]], align 2 2047 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[A]], align 4 2048 // CHECK3-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2049 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2050 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[AA]], align 2 2051 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2052 // CHECK3-NEXT: store i16 [[TMP2]], i16* [[CONV]], align 2 2053 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2054 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 2055 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40 2056 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]] 2057 // CHECK3: omp_if.then: 2058 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2059 // CHECK3-NEXT: [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32* 2060 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP6]], align 4 2061 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2062 // CHECK3-NEXT: [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32* 2063 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[TMP8]], align 4 2064 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 2065 // CHECK3-NEXT: store i8* null, i8** [[TMP9]], align 4 2066 // CHECK3-NEXT: [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 2067 // CHECK3-NEXT: [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32* 2068 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP11]], align 4 2069 // CHECK3-NEXT: [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 2070 // CHECK3-NEXT: [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32* 2071 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[TMP13]], align 4 2072 // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 2073 // CHECK3-NEXT: store i8* null, i8** [[TMP14]], align 4 2074 // CHECK3-NEXT: [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 2075 // CHECK3-NEXT: [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]** 2076 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4 2077 // CHECK3-NEXT: [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 2078 // CHECK3-NEXT: [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]** 2079 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4 2080 // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 2081 // CHECK3-NEXT: store i8* null, i8** [[TMP19]], align 4 2082 // CHECK3-NEXT: [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 2083 // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 2084 // CHECK3-NEXT: [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.17, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.18, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0) 2085 // CHECK3-NEXT: [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0 2086 // CHECK3-NEXT: br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] 2087 // CHECK3: omp_offload.failed: 2088 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 2089 // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] 2090 // CHECK3: omp_offload.cont: 2091 // CHECK3-NEXT: br label [[OMP_IF_END:%.*]] 2092 // CHECK3: omp_if.else: 2093 // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR4]] 2094 // CHECK3-NEXT: br label [[OMP_IF_END]] 2095 // CHECK3: omp_if.end: 2096 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[A]], align 4 2097 // CHECK3-NEXT: ret i32 [[TMP24]] 2098 // 2099 // 2100 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 2101 // CHECK3-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] { 2102 // CHECK3-NEXT: entry: 2103 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2104 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2105 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2106 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2107 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 2108 // CHECK3-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2109 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2110 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2111 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2112 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2113 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 2114 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2115 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2116 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2117 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 2118 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 2119 // CHECK3-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 2120 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 2121 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..10 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 2122 // CHECK3-NEXT: ret void 2123 // 2124 // 2125 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..10 2126 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR3]] { 2127 // CHECK3-NEXT: entry: 2128 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2129 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2130 // CHECK3-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2131 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2132 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2133 // CHECK3-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2134 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 2135 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2136 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2137 // CHECK3-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 2138 // CHECK3-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 2139 // CHECK3-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2140 // CHECK3-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2141 // CHECK3-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 2142 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 2143 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2144 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2145 // CHECK3-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 2146 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 2147 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 2148 // CHECK3-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 2149 // CHECK3-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2150 // CHECK3-NEXT: store double [[ADD]], double* [[A]], align 4 2151 // CHECK3-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2152 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 2153 // CHECK3-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 2154 // CHECK3-NEXT: store double [[INC]], double* [[A3]], align 4 2155 // CHECK3-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 2156 // CHECK3-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 2157 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 2158 // CHECK3-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 2159 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 2160 // CHECK3-NEXT: ret void 2161 // 2162 // 2163 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 2164 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2165 // CHECK3-NEXT: entry: 2166 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2167 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2168 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 2169 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2170 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2171 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2172 // CHECK3-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 2173 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2174 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2175 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 2176 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2177 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2178 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 2179 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2180 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2181 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2182 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2183 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2184 // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2185 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 2186 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2187 // CHECK3-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 2188 // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 2189 // CHECK3-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 2190 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 2191 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..13 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 2192 // CHECK3-NEXT: ret void 2193 // 2194 // 2195 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..13 2196 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 2197 // CHECK3-NEXT: entry: 2198 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2199 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2200 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2201 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2202 // CHECK3-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 2203 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2204 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2205 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2206 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2207 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2208 // CHECK3-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 2209 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2210 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2211 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 2212 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2213 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2214 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2215 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2216 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2217 // CHECK3-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 2218 // CHECK3-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2219 // CHECK3-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2220 // CHECK3-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 2221 // CHECK3-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 2222 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 2223 // CHECK3-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 2224 // CHECK3-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 2225 // CHECK3-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 2226 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 2227 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2228 // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 2229 // CHECK3-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 2230 // CHECK3-NEXT: ret void 2231 // 2232 // 2233 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 2234 // CHECK3-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] { 2235 // CHECK3-NEXT: entry: 2236 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2237 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2238 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2239 // CHECK3-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2240 // CHECK3-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2241 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2242 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2243 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2244 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2245 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2246 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2247 // CHECK3-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2248 // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2249 // CHECK3-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2250 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2251 // CHECK3-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 2252 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2253 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..16 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 2254 // CHECK3-NEXT: ret void 2255 // 2256 // 2257 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..16 2258 // CHECK3-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR3]] { 2259 // CHECK3-NEXT: entry: 2260 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2261 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2262 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2263 // CHECK3-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2264 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2265 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2266 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2267 // CHECK3-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2268 // CHECK3-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2269 // CHECK3-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2270 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2271 // CHECK3-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2272 // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2273 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2274 // CHECK3-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2275 // CHECK3-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2276 // CHECK3-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 2277 // CHECK3-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 2278 // CHECK3-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 2279 // CHECK3-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 2280 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 2281 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2282 // CHECK3-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 2283 // CHECK3-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 2284 // CHECK3-NEXT: ret void 2285 // 2286 // 2287 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg 2288 // CHECK3-SAME: () #[[ATTR8:[0-9]+]] { 2289 // CHECK3-NEXT: entry: 2290 // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) 2291 // CHECK3-NEXT: ret void 2292 // 2293 // 2294 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 2295 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] { 2296 // CHECK9-NEXT: entry: 2297 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2298 // CHECK9-NEXT: ret void 2299 // 2300 // 2301 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined. 2302 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 2303 // CHECK9-NEXT: entry: 2304 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2305 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2306 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2307 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2308 // CHECK9-NEXT: ret void 2309 // 2310 // 2311 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 2312 // CHECK9-SAME: (i64 noundef [[AA:%.*]]) #[[ATTR0]] { 2313 // CHECK9-NEXT: entry: 2314 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2315 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2316 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2317 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2318 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2319 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2320 // CHECK9-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2321 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2322 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]]) 2323 // CHECK9-NEXT: ret void 2324 // 2325 // 2326 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1 2327 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 2328 // CHECK9-NEXT: entry: 2329 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2330 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2331 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2332 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2333 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2334 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2335 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2336 // CHECK9-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2337 // CHECK9-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2338 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 2339 // CHECK9-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2340 // CHECK9-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 2341 // CHECK9-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2342 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2343 // CHECK9-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 2344 // CHECK9-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 2345 // CHECK9-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 2346 // CHECK9: .cancel.exit: 2347 // CHECK9-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 2348 // CHECK9-NEXT: br label [[DOTCANCEL_CONTINUE]] 2349 // CHECK9: .cancel.continue: 2350 // CHECK9-NEXT: ret void 2351 // 2352 // 2353 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 2354 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR0]] { 2355 // CHECK9-NEXT: entry: 2356 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2357 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2358 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2359 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2360 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2361 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2362 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2363 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2364 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2365 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2366 // CHECK9-NEXT: store i32 [[TMP0]], i32* [[CONV2]], align 4 2367 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8 2368 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2369 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2370 // CHECK9-NEXT: store i16 [[TMP2]], i16* [[CONV3]], align 2 2371 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2372 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]]) 2373 // CHECK9-NEXT: ret void 2374 // 2375 // 2376 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2 2377 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]]) #[[ATTR1]] { 2378 // CHECK9-NEXT: entry: 2379 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2380 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2381 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2382 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2383 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2384 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2385 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2386 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2387 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2388 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2389 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[CONV]], align 4 2390 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2391 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2392 // CHECK9-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 2 2393 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP1]] to i32 2394 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2395 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2396 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 2397 // CHECK9-NEXT: ret void 2398 // 2399 // 2400 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 2401 // CHECK9-SAME: (i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] { 2402 // CHECK9-NEXT: entry: 2403 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2404 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2405 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2406 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2407 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2408 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2409 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2410 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2411 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2412 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2413 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2414 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2415 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2416 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2417 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2418 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2419 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2420 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2421 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2422 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2423 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2424 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2425 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2426 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2427 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2428 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2429 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2430 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2431 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2432 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2433 // CHECK9-NEXT: store i32 [[TMP8]], i32* [[CONV5]], align 4 2434 // CHECK9-NEXT: [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8 2435 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2436 // CHECK9-NEXT: ret void 2437 // 2438 // 2439 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3 2440 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i64 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 8 dereferenceable(400) [[C:%.*]], i64 noundef [[VLA1:%.*]], i64 noundef [[VLA3:%.*]], double* noundef nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR1]] { 2441 // CHECK9-NEXT: entry: 2442 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2443 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2444 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2445 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 8 2446 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2447 // CHECK9-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 8 2448 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8 2449 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2450 // CHECK9-NEXT: [[VLA_ADDR4:%.*]] = alloca i64, align 8 2451 // CHECK9-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 8 2452 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 8 2453 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2454 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2455 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2456 // CHECK9-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8 2457 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2458 // CHECK9-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 8 2459 // CHECK9-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8 2460 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2461 // CHECK9-NEXT: store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8 2462 // CHECK9-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 8 2463 // CHECK9-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8 2464 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2465 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8 2466 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2467 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8 2468 // CHECK9-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8 2469 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2470 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8 2471 // CHECK9-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8 2472 // CHECK9-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8 2473 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[CONV]], align 4 2474 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 2475 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2476 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2 2477 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2478 // CHECK9-NEXT: [[CONV5:%.*]] = fpext float [[TMP9]] to double 2479 // CHECK9-NEXT: [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00 2480 // CHECK9-NEXT: [[CONV7:%.*]] = fptrunc double [[ADD6]] to float 2481 // CHECK9-NEXT: store float [[CONV7]], float* [[ARRAYIDX]], align 4 2482 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3 2483 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4 2484 // CHECK9-NEXT: [[CONV9:%.*]] = fpext float [[TMP10]] to double 2485 // CHECK9-NEXT: [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00 2486 // CHECK9-NEXT: [[CONV11:%.*]] = fptrunc double [[ADD10]] to float 2487 // CHECK9-NEXT: store float [[CONV11]], float* [[ARRAYIDX8]], align 4 2488 // CHECK9-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1 2489 // CHECK9-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2 2490 // CHECK9-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8 2491 // CHECK9-NEXT: [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00 2492 // CHECK9-NEXT: store double [[ADD14]], double* [[ARRAYIDX13]], align 8 2493 // CHECK9-NEXT: [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]] 2494 // CHECK9-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]] 2495 // CHECK9-NEXT: [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3 2496 // CHECK9-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8 2497 // CHECK9-NEXT: [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00 2498 // CHECK9-NEXT: store double [[ADD17]], double* [[ARRAYIDX16]], align 8 2499 // CHECK9-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2500 // CHECK9-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 8 2501 // CHECK9-NEXT: [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1 2502 // CHECK9-NEXT: store i64 [[ADD18]], i64* [[X]], align 8 2503 // CHECK9-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2504 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 8 2505 // CHECK9-NEXT: [[CONV19:%.*]] = sext i8 [[TMP15]] to i32 2506 // CHECK9-NEXT: [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1 2507 // CHECK9-NEXT: [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8 2508 // CHECK9-NEXT: store i8 [[CONV21]], i8* [[Y]], align 8 2509 // CHECK9-NEXT: ret void 2510 // 2511 // 2512 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 2513 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 2514 // CHECK9-NEXT: entry: 2515 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2516 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2517 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2518 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2519 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2520 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2521 // CHECK9-NEXT: [[AAA_CASTED:%.*]] = alloca i64, align 8 2522 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2523 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2524 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2525 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2526 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2527 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2528 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2529 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2530 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2531 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2532 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV3]], align 4 2533 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2534 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2535 // CHECK9-NEXT: [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2536 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV4]], align 2 2537 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2538 // CHECK9-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 1 2539 // CHECK9-NEXT: [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8* 2540 // CHECK9-NEXT: store i8 [[TMP5]], i8* [[CONV5]], align 1 2541 // CHECK9-NEXT: [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8 2542 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]]) 2543 // CHECK9-NEXT: ret void 2544 // 2545 // 2546 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4 2547 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], i64 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 2548 // CHECK9-NEXT: entry: 2549 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2550 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2551 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2552 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2553 // CHECK9-NEXT: [[AAA_ADDR:%.*]] = alloca i64, align 8 2554 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2555 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2556 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2557 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2558 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2559 // CHECK9-NEXT: store i64 [[AAA]], i64* [[AAA_ADDR]], align 8 2560 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2561 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2562 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2563 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8* 2564 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2565 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2566 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2567 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2568 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2569 // CHECK9-NEXT: [[CONV3:%.*]] = sext i16 [[TMP2]] to i32 2570 // CHECK9-NEXT: [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1 2571 // CHECK9-NEXT: [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16 2572 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[CONV1]], align 2 2573 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 1 2574 // CHECK9-NEXT: [[CONV6:%.*]] = sext i8 [[TMP3]] to i32 2575 // CHECK9-NEXT: [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1 2576 // CHECK9-NEXT: [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8 2577 // CHECK9-NEXT: store i8 [[CONV8]], i8* [[CONV2]], align 1 2578 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 2579 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2580 // CHECK9-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1 2581 // CHECK9-NEXT: store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4 2582 // CHECK9-NEXT: ret void 2583 // 2584 // 2585 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 2586 // CHECK9-SAME: (%struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 2587 // CHECK9-NEXT: entry: 2588 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2589 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2590 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2591 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2592 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2593 // CHECK9-NEXT: [[B_CASTED:%.*]] = alloca i64, align 8 2594 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2595 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2596 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2597 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2598 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2599 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2600 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2601 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2602 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2603 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2604 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2605 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32* 2606 // CHECK9-NEXT: store i32 [[TMP4]], i32* [[CONV3]], align 4 2607 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8 2608 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]]) 2609 // CHECK9-NEXT: ret void 2610 // 2611 // 2612 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5 2613 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i64 noundef [[B:%.*]], i64 noundef [[VLA:%.*]], i64 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 2614 // CHECK9-NEXT: entry: 2615 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2616 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2617 // CHECK9-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8 2618 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca i64, align 8 2619 // CHECK9-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2620 // CHECK9-NEXT: [[VLA_ADDR2:%.*]] = alloca i64, align 8 2621 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 8 2622 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2623 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2624 // CHECK9-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8 2625 // CHECK9-NEXT: store i64 [[B]], i64* [[B_ADDR]], align 8 2626 // CHECK9-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2627 // CHECK9-NEXT: store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8 2628 // CHECK9-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 8 2629 // CHECK9-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8 2630 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32* 2631 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2632 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8 2633 // CHECK9-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8 2634 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 4 2635 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double 2636 // CHECK9-NEXT: [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00 2637 // CHECK9-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 2638 // CHECK9-NEXT: store double [[ADD]], double* [[A]], align 8 2639 // CHECK9-NEXT: [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 2640 // CHECK9-NEXT: [[TMP5:%.*]] = load double, double* [[A4]], align 8 2641 // CHECK9-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 2642 // CHECK9-NEXT: store double [[INC]], double* [[A4]], align 8 2643 // CHECK9-NEXT: [[CONV5:%.*]] = fptosi double [[INC]] to i16 2644 // CHECK9-NEXT: [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]] 2645 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]] 2646 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1 2647 // CHECK9-NEXT: store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2 2648 // CHECK9-NEXT: ret void 2649 // 2650 // 2651 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 2652 // CHECK9-SAME: (i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 2653 // CHECK9-NEXT: entry: 2654 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2655 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2656 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2657 // CHECK9-NEXT: [[A_CASTED:%.*]] = alloca i64, align 8 2658 // CHECK9-NEXT: [[AA_CASTED:%.*]] = alloca i64, align 8 2659 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2660 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2661 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2662 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2663 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2664 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2665 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2666 // CHECK9-NEXT: [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32* 2667 // CHECK9-NEXT: store i32 [[TMP1]], i32* [[CONV2]], align 4 2668 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8 2669 // CHECK9-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 2 2670 // CHECK9-NEXT: [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16* 2671 // CHECK9-NEXT: store i16 [[TMP3]], i16* [[CONV3]], align 2 2672 // CHECK9-NEXT: [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8 2673 // CHECK9-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]]) 2674 // CHECK9-NEXT: ret void 2675 // 2676 // 2677 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6 2678 // CHECK9-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i64 noundef [[A:%.*]], i64 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 2679 // CHECK9-NEXT: entry: 2680 // CHECK9-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2681 // CHECK9-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2682 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca i64, align 8 2683 // CHECK9-NEXT: [[AA_ADDR:%.*]] = alloca i64, align 8 2684 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8 2685 // CHECK9-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2686 // CHECK9-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2687 // CHECK9-NEXT: store i64 [[A]], i64* [[A_ADDR]], align 8 2688 // CHECK9-NEXT: store i64 [[AA]], i64* [[AA_ADDR]], align 8 2689 // CHECK9-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8 2690 // CHECK9-NEXT: [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32* 2691 // CHECK9-NEXT: [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16* 2692 // CHECK9-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8 2693 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 4 2694 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2695 // CHECK9-NEXT: store i32 [[ADD]], i32* [[CONV]], align 4 2696 // CHECK9-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 2 2697 // CHECK9-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 2698 // CHECK9-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2699 // CHECK9-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2700 // CHECK9-NEXT: store i16 [[CONV4]], i16* [[CONV1]], align 2 2701 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2 2702 // CHECK9-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2703 // CHECK9-NEXT: [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1 2704 // CHECK9-NEXT: store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4 2705 // CHECK9-NEXT: ret void 2706 // 2707 // 2708 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100 2709 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 2710 // CHECK11-NEXT: entry: 2711 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*)) 2712 // CHECK11-NEXT: ret void 2713 // 2714 // 2715 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 2716 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]]) #[[ATTR1:[0-9]+]] { 2717 // CHECK11-NEXT: entry: 2718 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2719 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2720 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2721 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2722 // CHECK11-NEXT: ret void 2723 // 2724 // 2725 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110 2726 // CHECK11-SAME: (i32 noundef [[AA:%.*]]) #[[ATTR0]] { 2727 // CHECK11-NEXT: entry: 2728 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2729 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2730 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2731 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2732 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2733 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2734 // CHECK11-NEXT: store i16 [[TMP0]], i16* [[CONV1]], align 2 2735 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2736 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]]) 2737 // CHECK11-NEXT: ret void 2738 // 2739 // 2740 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 2741 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 2742 // CHECK11-NEXT: entry: 2743 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2744 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2745 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2746 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2747 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2748 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2749 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2750 // CHECK11-NEXT: [[TMP0:%.*]] = load i16, i16* [[CONV]], align 2 2751 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP0]] to i32 2752 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[CONV1]], 1 2753 // CHECK11-NEXT: [[CONV2:%.*]] = trunc i32 [[ADD]] to i16 2754 // CHECK11-NEXT: store i16 [[CONV2]], i16* [[CONV]], align 2 2755 // CHECK11-NEXT: [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 2756 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4 2757 // CHECK11-NEXT: [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1) 2758 // CHECK11-NEXT: [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0 2759 // CHECK11-NEXT: br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] 2760 // CHECK11: .cancel.exit: 2761 // CHECK11-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_cancel_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP2]]) 2762 // CHECK11-NEXT: br label [[DOTCANCEL_CONTINUE]] 2763 // CHECK11: .cancel.continue: 2764 // CHECK11-NEXT: ret void 2765 // 2766 // 2767 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119 2768 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR0]] { 2769 // CHECK11-NEXT: entry: 2770 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2771 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2772 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2773 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2774 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2775 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2776 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2777 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2778 // CHECK11-NEXT: store i32 [[TMP0]], i32* [[A_CASTED]], align 4 2779 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4 2780 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2781 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2782 // CHECK11-NEXT: store i16 [[TMP2]], i16* [[CONV1]], align 2 2783 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2784 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]]) 2785 // CHECK11-NEXT: ret void 2786 // 2787 // 2788 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 2789 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]]) #[[ATTR1]] { 2790 // CHECK11-NEXT: entry: 2791 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2792 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2793 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2794 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2795 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2796 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2797 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2798 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2799 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2800 // CHECK11-NEXT: [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4 2801 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP0]], 1 2802 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2803 // CHECK11-NEXT: [[TMP1:%.*]] = load i16, i16* [[CONV]], align 2 2804 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP1]] to i32 2805 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 2806 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 2807 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 2808 // CHECK11-NEXT: ret void 2809 // 2810 // 2811 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144 2812 // CHECK11-SAME: (i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] { 2813 // CHECK11-NEXT: entry: 2814 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2815 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2816 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2817 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2818 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2819 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2820 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2821 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2822 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2823 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2824 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2825 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2826 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2827 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2828 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2829 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2830 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2831 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2832 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2833 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2834 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2835 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2836 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2837 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2838 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2839 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2840 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2841 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2842 // CHECK11-NEXT: store i32 [[TMP8]], i32* [[A_CASTED]], align 4 2843 // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4 2844 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]]) 2845 // CHECK11-NEXT: ret void 2846 // 2847 // 2848 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 2849 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], [10 x float]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]], i32 noundef [[VLA:%.*]], float* noundef nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* noundef nonnull align 4 dereferenceable(400) [[C:%.*]], i32 noundef [[VLA1:%.*]], i32 noundef [[VLA3:%.*]], double* noundef nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* noundef nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR1]] { 2850 // CHECK11-NEXT: entry: 2851 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2852 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2853 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2854 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x float]*, align 4 2855 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2856 // CHECK11-NEXT: [[BN_ADDR:%.*]] = alloca float*, align 4 2857 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4 2858 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2859 // CHECK11-NEXT: [[VLA_ADDR4:%.*]] = alloca i32, align 4 2860 // CHECK11-NEXT: [[CN_ADDR:%.*]] = alloca double*, align 4 2861 // CHECK11-NEXT: [[D_ADDR:%.*]] = alloca %struct.TT*, align 4 2862 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2863 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2864 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2865 // CHECK11-NEXT: store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4 2866 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 2867 // CHECK11-NEXT: store float* [[BN]], float** [[BN_ADDR]], align 4 2868 // CHECK11-NEXT: store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4 2869 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 2870 // CHECK11-NEXT: store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4 2871 // CHECK11-NEXT: store double* [[CN]], double** [[CN_ADDR]], align 4 2872 // CHECK11-NEXT: store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4 2873 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4 2874 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 2875 // CHECK11-NEXT: [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4 2876 // CHECK11-NEXT: [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4 2877 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 2878 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4 2879 // CHECK11-NEXT: [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4 2880 // CHECK11-NEXT: [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4 2881 // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4 2882 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP8]], 1 2883 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2884 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2 2885 // CHECK11-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4 2886 // CHECK11-NEXT: [[CONV:%.*]] = fpext float [[TMP9]] to double 2887 // CHECK11-NEXT: [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00 2888 // CHECK11-NEXT: [[CONV6:%.*]] = fptrunc double [[ADD5]] to float 2889 // CHECK11-NEXT: store float [[CONV6]], float* [[ARRAYIDX]], align 4 2890 // CHECK11-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3 2891 // CHECK11-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2892 // CHECK11-NEXT: [[CONV8:%.*]] = fpext float [[TMP10]] to double 2893 // CHECK11-NEXT: [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00 2894 // CHECK11-NEXT: [[CONV10:%.*]] = fptrunc double [[ADD9]] to float 2895 // CHECK11-NEXT: store float [[CONV10]], float* [[ARRAYIDX7]], align 4 2896 // CHECK11-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1 2897 // CHECK11-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2 2898 // CHECK11-NEXT: [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8 2899 // CHECK11-NEXT: [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00 2900 // CHECK11-NEXT: store double [[ADD13]], double* [[ARRAYIDX12]], align 8 2901 // CHECK11-NEXT: [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]] 2902 // CHECK11-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]] 2903 // CHECK11-NEXT: [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3 2904 // CHECK11-NEXT: [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8 2905 // CHECK11-NEXT: [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00 2906 // CHECK11-NEXT: store double [[ADD16]], double* [[ARRAYIDX15]], align 8 2907 // CHECK11-NEXT: [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0 2908 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[X]], align 4 2909 // CHECK11-NEXT: [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1 2910 // CHECK11-NEXT: store i64 [[ADD17]], i64* [[X]], align 4 2911 // CHECK11-NEXT: [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1 2912 // CHECK11-NEXT: [[TMP15:%.*]] = load i8, i8* [[Y]], align 4 2913 // CHECK11-NEXT: [[CONV18:%.*]] = sext i8 [[TMP15]] to i32 2914 // CHECK11-NEXT: [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1 2915 // CHECK11-NEXT: [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8 2916 // CHECK11-NEXT: store i8 [[CONV20]], i8* [[Y]], align 4 2917 // CHECK11-NEXT: ret void 2918 // 2919 // 2920 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198 2921 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 2922 // CHECK11-NEXT: entry: 2923 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2924 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2925 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 2926 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2927 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 2928 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 2929 // CHECK11-NEXT: [[AAA_CASTED:%.*]] = alloca i32, align 4 2930 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2931 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2932 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 2933 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2934 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2935 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 2936 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2937 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2938 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 2939 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 2940 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 2941 // CHECK11-NEXT: [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 2942 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV2]], align 2 2943 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 2944 // CHECK11-NEXT: [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 1 2945 // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8* 2946 // CHECK11-NEXT: store i8 [[TMP5]], i8* [[CONV3]], align 1 2947 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4 2948 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]]) 2949 // CHECK11-NEXT: ret void 2950 // 2951 // 2952 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4 2953 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], i32 noundef [[AAA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 2954 // CHECK11-NEXT: entry: 2955 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 2956 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 2957 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 2958 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 2959 // CHECK11-NEXT: [[AAA_ADDR:%.*]] = alloca i32, align 4 2960 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 2961 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 2962 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 2963 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 2964 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 2965 // CHECK11-NEXT: store i32 [[AAA]], i32* [[AAA_ADDR]], align 4 2966 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 2967 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 2968 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8* 2969 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 2970 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 2971 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 2972 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 2973 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 2974 // CHECK11-NEXT: [[CONV2:%.*]] = sext i16 [[TMP2]] to i32 2975 // CHECK11-NEXT: [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1 2976 // CHECK11-NEXT: [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16 2977 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[CONV]], align 2 2978 // CHECK11-NEXT: [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 1 2979 // CHECK11-NEXT: [[CONV5:%.*]] = sext i8 [[TMP3]] to i32 2980 // CHECK11-NEXT: [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1 2981 // CHECK11-NEXT: [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8 2982 // CHECK11-NEXT: store i8 [[CONV7]], i8* [[CONV1]], align 1 2983 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 2984 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 2985 // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1 2986 // CHECK11-NEXT: store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4 2987 // CHECK11-NEXT: ret void 2988 // 2989 // 2990 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216 2991 // CHECK11-SAME: (%struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] { 2992 // CHECK11-NEXT: entry: 2993 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 2994 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 2995 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 2996 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 2997 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 2998 // CHECK11-NEXT: [[B_CASTED:%.*]] = alloca i32, align 4 2999 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3000 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3001 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3002 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3003 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3004 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3005 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3006 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3007 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3008 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3009 // CHECK11-NEXT: store i32 [[TMP4]], i32* [[B_CASTED]], align 4 3010 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4 3011 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]]) 3012 // CHECK11-NEXT: ret void 3013 // 3014 // 3015 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5 3016 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], %struct.S1* noundef [[THIS:%.*]], i32 noundef [[B:%.*]], i32 noundef [[VLA:%.*]], i32 noundef [[VLA1:%.*]], i16* noundef nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR1]] { 3017 // CHECK11-NEXT: entry: 3018 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3019 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3020 // CHECK11-NEXT: [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4 3021 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca i32, align 4 3022 // CHECK11-NEXT: [[VLA_ADDR:%.*]] = alloca i32, align 4 3023 // CHECK11-NEXT: [[VLA_ADDR2:%.*]] = alloca i32, align 4 3024 // CHECK11-NEXT: [[C_ADDR:%.*]] = alloca i16*, align 4 3025 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3026 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3027 // CHECK11-NEXT: store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4 3028 // CHECK11-NEXT: store i32 [[B]], i32* [[B_ADDR]], align 4 3029 // CHECK11-NEXT: store i32 [[VLA]], i32* [[VLA_ADDR]], align 4 3030 // CHECK11-NEXT: store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4 3031 // CHECK11-NEXT: store i16* [[C]], i16** [[C_ADDR]], align 4 3032 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4 3033 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4 3034 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4 3035 // CHECK11-NEXT: [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4 3036 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4 3037 // CHECK11-NEXT: [[CONV:%.*]] = sitofp i32 [[TMP4]] to double 3038 // CHECK11-NEXT: [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00 3039 // CHECK11-NEXT: [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0 3040 // CHECK11-NEXT: store double [[ADD]], double* [[A]], align 4 3041 // CHECK11-NEXT: [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0 3042 // CHECK11-NEXT: [[TMP5:%.*]] = load double, double* [[A3]], align 4 3043 // CHECK11-NEXT: [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00 3044 // CHECK11-NEXT: store double [[INC]], double* [[A3]], align 4 3045 // CHECK11-NEXT: [[CONV4:%.*]] = fptosi double [[INC]] to i16 3046 // CHECK11-NEXT: [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]] 3047 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]] 3048 // CHECK11-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1 3049 // CHECK11-NEXT: store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2 3050 // CHECK11-NEXT: ret void 3051 // 3052 // 3053 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181 3054 // CHECK11-SAME: (i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] { 3055 // CHECK11-NEXT: entry: 3056 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3057 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3058 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3059 // CHECK11-NEXT: [[A_CASTED:%.*]] = alloca i32, align 4 3060 // CHECK11-NEXT: [[AA_CASTED:%.*]] = alloca i32, align 4 3061 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3062 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3063 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3064 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3065 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3066 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3067 // CHECK11-NEXT: store i32 [[TMP1]], i32* [[A_CASTED]], align 4 3068 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4 3069 // CHECK11-NEXT: [[TMP3:%.*]] = load i16, i16* [[CONV]], align 2 3070 // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16* 3071 // CHECK11-NEXT: store i16 [[TMP3]], i16* [[CONV1]], align 2 3072 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4 3073 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]]) 3074 // CHECK11-NEXT: ret void 3075 // 3076 // 3077 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6 3078 // CHECK11-SAME: (i32* noalias noundef [[DOTGLOBAL_TID_:%.*]], i32* noalias noundef [[DOTBOUND_TID_:%.*]], i32 noundef [[A:%.*]], i32 noundef [[AA:%.*]], [10 x i32]* noundef nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR1]] { 3079 // CHECK11-NEXT: entry: 3080 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 3081 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 3082 // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca i32, align 4 3083 // CHECK11-NEXT: [[AA_ADDR:%.*]] = alloca i32, align 4 3084 // CHECK11-NEXT: [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4 3085 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 3086 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 3087 // CHECK11-NEXT: store i32 [[A]], i32* [[A_ADDR]], align 4 3088 // CHECK11-NEXT: store i32 [[AA]], i32* [[AA_ADDR]], align 4 3089 // CHECK11-NEXT: store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4 3090 // CHECK11-NEXT: [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16* 3091 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4 3092 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4 3093 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP1]], 1 3094 // CHECK11-NEXT: store i32 [[ADD]], i32* [[A_ADDR]], align 4 3095 // CHECK11-NEXT: [[TMP2:%.*]] = load i16, i16* [[CONV]], align 2 3096 // CHECK11-NEXT: [[CONV1:%.*]] = sext i16 [[TMP2]] to i32 3097 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1 3098 // CHECK11-NEXT: [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16 3099 // CHECK11-NEXT: store i16 [[CONV3]], i16* [[CONV]], align 2 3100 // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2 3101 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 3102 // CHECK11-NEXT: [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1 3103 // CHECK11-NEXT: store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4 3104 // CHECK11-NEXT: ret void 3105 // 3106