1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // Test host codegen.
3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
4 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
5 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
6 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4
9 
10 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
11 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
12 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK6
13 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK7
14 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
15 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8
16 
17 // Test target codegen - host bc file has to be created first.
18 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
19 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK9
20 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
21 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK10
22 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
23 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK11
24 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
25 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12
26 
27 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
28 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK13
29 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
30 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14
31 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
32 // RUN: %clang_cc1 -verify -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK15
33 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
34 // RUN: %clang_cc1 -fopenmp-simd -fopenmp-version=45 -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK16
35 
36 // Test host codegen.
37 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17
38 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
39 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18
40 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19
41 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
42 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK20
43 
44 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21
45 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s
46 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK22
47 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK23
48 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s
49 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK24
50 
51 // Test target codegen - host bc file has to be created first.
52 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
53 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK25
54 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
55 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK26
56 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
57 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK27
58 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
59 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK28
60 
61 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc
62 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK29
63 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s
64 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK30
65 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc
66 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK31
67 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s
68 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK32
69 
70 // expected-no-diagnostics
71 #ifndef HEADER
72 #define HEADER
73 
74 
75 
76 
77 // We have 8 target regions, but only 6 that actually will generate offloading
78 // code and have mapped arguments, and only 4 have all-constant map sizes.
79 
80 
81 
82 // Check target registration is registered as a Ctor.
83 
84 
85 template<typename tx, typename ty>
86 struct TT{
87   tx X;
88   ty Y;
89 };
90 
91 int foo(int n) {
92   int a = 0;
93   short aa = 0;
94   float b[10];
95   float bn[n];
96   double c[5][10];
97   double cn[5][n];
98   TT<long long, char> d;
99 
100   #pragma omp target parallel nowait
101   {
102   }
103 
104   #pragma omp target parallel if(target: 0)
105   {
106     a += 1;
107   }
108 
109 
110   #pragma omp target parallel if(target: 1)
111   {
112     aa += 1;
113 #pragma omp cancel parallel
114   }
115 
116 
117 
118 
119   #pragma omp target parallel if(target: n>10)
120   {
121     a += 1;
122     aa += 1;
123   }
124 
125   // We capture 3 VLA sizes in this target region
126 
127 
128 
129 
130 
131   // The names below are not necessarily consistent with the names used for the
132   // addresses above as some are repeated.
133 
134 
135 
136 
137 
138 
139 
140 
141 
142 
143 
144   #pragma omp target parallel if(target: n>20)
145   {
146     a += 1;
147     b[2] += 1.0;
148     bn[3] += 1.0;
149     c[1][2] += 1.0;
150     cn[1][3] += 1.0;
151     d.X += 1;
152     d.Y += 1;
153   }
154 
155   return a;
156 }
157 
158 // Check that the offloading functions are emitted and that the arguments are
159 // correct and loaded correctly for the target regions in foo().
160 
161 
162 
163 // Create stack storage and store argument in there.
164 
165 // Create stack storage and store argument in there.
166 
167 // Create stack storage and store argument in there.
168 
169 // Create local storage for each capture.
170 
171 
172 
173 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
174 
175 template<typename tx>
176 tx ftemplate(int n) {
177   tx a = 0;
178   short aa = 0;
179   tx b[10];
180 
181   #pragma omp target parallel if(target: n>40)
182   {
183     a += 1;
184     aa += 1;
185     b[2] += 1;
186   }
187 
188   return a;
189 }
190 
191 static
192 int fstatic(int n) {
193   int a = 0;
194   short aa = 0;
195   char aaa = 0;
196   int b[10];
197 
198   #pragma omp target parallel if(target: n>50)
199   {
200     a += 1;
201     aa += 1;
202     aaa += 1;
203     b[2] += 1;
204   }
205 
206   return a;
207 }
208 
209 struct S1 {
210   double a;
211 
212   int r1(int n){
213     int b = n+1;
214     short int c[2][n];
215 
216     #pragma omp target parallel if(target: n>60)
217     {
218       this->a = (double)b + 1.5;
219       c[1][1] = ++a;
220     }
221 
222     return c[1][1] + (int)b;
223   }
224 };
225 
226 int bar(int n){
227   int a = 0;
228 
229   a += foo(n);
230 
231   S1 S;
232   a += S.r1(n);
233 
234   a += fstatic(n);
235 
236   a += ftemplate<int>(n);
237 
238   return a;
239 }
240 
241 
242 
243 // We capture 2 VLA sizes in this target region
244 
245 
246 // The names below are not necessarily consistent with the names used for the
247 // addresses above as some are repeated.
248 
249 
250 
251 
252 
253 
254 
255 
256 
257 
258 
259 
260 
261 
262 
263 
264 
265 
266 
267 // Check that the offloading functions are emitted and that the arguments are
268 // correct and loaded correctly for the target regions of the callees of bar().
269 
270 // Create local storage for each capture.
271 // Store captures in the context.
272 
273 
274 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
275 
276 
277 // Create local storage for each capture.
278 // Store captures in the context.
279 
280 
281 
282 
283 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
284 
285 // Create local storage for each capture.
286 // Store captures in the context.
287 
288 
289 
290 // To reduce complexity, we're only going as far as validating the signature of the outlined parallel function.
291 
292 
293 #endif
294 // CHECK1-LABEL: define {{[^@]+}}@_Z3fooi
295 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
296 // CHECK1-NEXT:  entry:
297 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
298 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
299 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
300 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
301 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
302 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
303 // CHECK1-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
304 // CHECK1-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
305 // CHECK1-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
306 // CHECK1-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
307 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
308 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
309 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
310 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
311 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
312 // CHECK1-NEXT:    [[A_CASTED3:%.*]] = alloca i64, align 8
313 // CHECK1-NEXT:    [[AA_CASTED5:%.*]] = alloca i64, align 8
314 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8
315 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8
316 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8
317 // CHECK1-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
318 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8
319 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8
320 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8
321 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
322 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
323 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
324 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
325 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
326 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
327 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
328 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
329 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
330 // CHECK1-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
331 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
332 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
333 // CHECK1-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
334 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
335 // CHECK1-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
336 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
337 // CHECK1-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
338 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
339 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
340 // CHECK1-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]])
341 // CHECK1-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
342 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
343 // CHECK1-NEXT:    store i32 [[TMP11]], i32* [[CONV]], align 4
344 // CHECK1-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
345 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR3:[0-9]+]]
346 // CHECK1-NEXT:    [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
347 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
348 // CHECK1-NEXT:    store i16 [[TMP13]], i16* [[CONV2]], align 2
349 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
350 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
351 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
352 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP16]], align 8
353 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
354 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
355 // CHECK1-NEXT:    store i64 [[TMP14]], i64* [[TMP18]], align 8
356 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
357 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
358 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
359 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
360 // CHECK1-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
361 // CHECK1-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
362 // CHECK1-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
363 // CHECK1:       omp_offload.failed:
364 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR3]]
365 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
366 // CHECK1:       omp_offload.cont:
367 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
368 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32*
369 // CHECK1-NEXT:    store i32 [[TMP24]], i32* [[CONV4]], align 4
370 // CHECK1-NEXT:    [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8
371 // CHECK1-NEXT:    [[TMP26:%.*]] = load i16, i16* [[AA]], align 2
372 // CHECK1-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16*
373 // CHECK1-NEXT:    store i16 [[TMP26]], i16* [[CONV6]], align 2
374 // CHECK1-NEXT:    [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8
375 // CHECK1-NEXT:    [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4
376 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10
377 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
378 // CHECK1:       omp_if.then:
379 // CHECK1-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
380 // CHECK1-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
381 // CHECK1-NEXT:    store i64 [[TMP25]], i64* [[TMP30]], align 8
382 // CHECK1-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
383 // CHECK1-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
384 // CHECK1-NEXT:    store i64 [[TMP25]], i64* [[TMP32]], align 8
385 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
386 // CHECK1-NEXT:    store i8* null, i8** [[TMP33]], align 8
387 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1
388 // CHECK1-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64*
389 // CHECK1-NEXT:    store i64 [[TMP27]], i64* [[TMP35]], align 8
390 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1
391 // CHECK1-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
392 // CHECK1-NEXT:    store i64 [[TMP27]], i64* [[TMP37]], align 8
393 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1
394 // CHECK1-NEXT:    store i8* null, i8** [[TMP38]], align 8
395 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
396 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
397 // CHECK1-NEXT:    [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
398 // CHECK1-NEXT:    [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
399 // CHECK1-NEXT:    br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]]
400 // CHECK1:       omp_offload.failed10:
401 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]]
402 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT11]]
403 // CHECK1:       omp_offload.cont11:
404 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
405 // CHECK1:       omp_if.else:
406 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]]
407 // CHECK1-NEXT:    br label [[OMP_IF_END]]
408 // CHECK1:       omp_if.end:
409 // CHECK1-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4
410 // CHECK1-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
411 // CHECK1-NEXT:    store i32 [[TMP43]], i32* [[CONV13]], align 4
412 // CHECK1-NEXT:    [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8
413 // CHECK1-NEXT:    [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4
414 // CHECK1-NEXT:    [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20
415 // CHECK1-NEXT:    br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]]
416 // CHECK1:       omp_if.then15:
417 // CHECK1-NEXT:    [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4
418 // CHECK1-NEXT:    [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]]
419 // CHECK1-NEXT:    [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8
420 // CHECK1-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
421 // CHECK1-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64*
422 // CHECK1-NEXT:    store i64 [[TMP44]], i64* [[TMP50]], align 8
423 // CHECK1-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
424 // CHECK1-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
425 // CHECK1-NEXT:    store i64 [[TMP44]], i64* [[TMP52]], align 8
426 // CHECK1-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
427 // CHECK1-NEXT:    store i64 4, i64* [[TMP53]], align 8
428 // CHECK1-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
429 // CHECK1-NEXT:    store i8* null, i8** [[TMP54]], align 8
430 // CHECK1-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
431 // CHECK1-NEXT:    [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]**
432 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8
433 // CHECK1-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
434 // CHECK1-NEXT:    [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]**
435 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8
436 // CHECK1-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
437 // CHECK1-NEXT:    store i64 40, i64* [[TMP59]], align 8
438 // CHECK1-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
439 // CHECK1-NEXT:    store i8* null, i8** [[TMP60]], align 8
440 // CHECK1-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2
441 // CHECK1-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
442 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP62]], align 8
443 // CHECK1-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2
444 // CHECK1-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
445 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP64]], align 8
446 // CHECK1-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
447 // CHECK1-NEXT:    store i64 8, i64* [[TMP65]], align 8
448 // CHECK1-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2
449 // CHECK1-NEXT:    store i8* null, i8** [[TMP66]], align 8
450 // CHECK1-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3
451 // CHECK1-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float**
452 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP68]], align 8
453 // CHECK1-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3
454 // CHECK1-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float**
455 // CHECK1-NEXT:    store float* [[VLA]], float** [[TMP70]], align 8
456 // CHECK1-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
457 // CHECK1-NEXT:    store i64 [[TMP46]], i64* [[TMP71]], align 8
458 // CHECK1-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3
459 // CHECK1-NEXT:    store i8* null, i8** [[TMP72]], align 8
460 // CHECK1-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4
461 // CHECK1-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]**
462 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8
463 // CHECK1-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4
464 // CHECK1-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]**
465 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8
466 // CHECK1-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
467 // CHECK1-NEXT:    store i64 400, i64* [[TMP77]], align 8
468 // CHECK1-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4
469 // CHECK1-NEXT:    store i8* null, i8** [[TMP78]], align 8
470 // CHECK1-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5
471 // CHECK1-NEXT:    [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*
472 // CHECK1-NEXT:    store i64 5, i64* [[TMP80]], align 8
473 // CHECK1-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5
474 // CHECK1-NEXT:    [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64*
475 // CHECK1-NEXT:    store i64 5, i64* [[TMP82]], align 8
476 // CHECK1-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
477 // CHECK1-NEXT:    store i64 8, i64* [[TMP83]], align 8
478 // CHECK1-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5
479 // CHECK1-NEXT:    store i8* null, i8** [[TMP84]], align 8
480 // CHECK1-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6
481 // CHECK1-NEXT:    [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64*
482 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP86]], align 8
483 // CHECK1-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6
484 // CHECK1-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64*
485 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP88]], align 8
486 // CHECK1-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
487 // CHECK1-NEXT:    store i64 8, i64* [[TMP89]], align 8
488 // CHECK1-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6
489 // CHECK1-NEXT:    store i8* null, i8** [[TMP90]], align 8
490 // CHECK1-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7
491 // CHECK1-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double**
492 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP92]], align 8
493 // CHECK1-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7
494 // CHECK1-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double**
495 // CHECK1-NEXT:    store double* [[VLA1]], double** [[TMP94]], align 8
496 // CHECK1-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
497 // CHECK1-NEXT:    store i64 [[TMP48]], i64* [[TMP95]], align 8
498 // CHECK1-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7
499 // CHECK1-NEXT:    store i8* null, i8** [[TMP96]], align 8
500 // CHECK1-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8
501 // CHECK1-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT**
502 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8
503 // CHECK1-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8
504 // CHECK1-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT**
505 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8
506 // CHECK1-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
507 // CHECK1-NEXT:    store i64 16, i64* [[TMP101]], align 8
508 // CHECK1-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8
509 // CHECK1-NEXT:    store i8* null, i8** [[TMP102]], align 8
510 // CHECK1-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
511 // CHECK1-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
512 // CHECK1-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
513 // CHECK1-NEXT:    [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
514 // CHECK1-NEXT:    [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0
515 // CHECK1-NEXT:    br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
516 // CHECK1:       omp_offload.failed19:
517 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
518 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT20]]
519 // CHECK1:       omp_offload.cont20:
520 // CHECK1-NEXT:    br label [[OMP_IF_END22:%.*]]
521 // CHECK1:       omp_if.else21:
522 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
523 // CHECK1-NEXT:    br label [[OMP_IF_END22]]
524 // CHECK1:       omp_if.end22:
525 // CHECK1-NEXT:    [[TMP108:%.*]] = load i32, i32* [[A]], align 4
526 // CHECK1-NEXT:    [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
527 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP109]])
528 // CHECK1-NEXT:    ret i32 [[TMP108]]
529 //
530 //
531 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
532 // CHECK1-SAME: () #[[ATTR2:[0-9]+]] {
533 // CHECK1-NEXT:  entry:
534 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
535 // CHECK1-NEXT:    ret void
536 //
537 //
538 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
539 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
540 // CHECK1-NEXT:  entry:
541 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
542 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
543 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
544 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
545 // CHECK1-NEXT:    ret void
546 //
547 //
548 // CHECK1-LABEL: define {{[^@]+}}@.omp_task_entry.
549 // CHECK1-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
550 // CHECK1-NEXT:  entry:
551 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
552 // CHECK1-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
553 // CHECK1-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
554 // CHECK1-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
555 // CHECK1-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
556 // CHECK1-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
557 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
558 // CHECK1-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
559 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
560 // CHECK1-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
561 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
562 // CHECK1-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
563 // CHECK1-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
564 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
565 // CHECK1-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
566 // CHECK1-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
567 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
568 // CHECK1-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
569 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])
570 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
571 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
572 // CHECK1-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
573 // CHECK1-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20
574 // CHECK1-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20
575 // CHECK1-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
576 // CHECK1-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
577 // CHECK1-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20
578 // CHECK1-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
579 // CHECK1-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
580 // CHECK1-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
581 // CHECK1-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
582 // CHECK1-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
583 // CHECK1:       omp_offload.failed.i:
584 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
585 // CHECK1-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
586 // CHECK1:       .omp_outlined..1.exit:
587 // CHECK1-NEXT:    ret i32 0
588 //
589 //
590 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
591 // CHECK1-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
592 // CHECK1-NEXT:  entry:
593 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
594 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
595 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
596 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
597 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
598 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
599 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
600 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
601 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
602 // CHECK1-NEXT:    ret void
603 //
604 //
605 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2
606 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
607 // CHECK1-NEXT:  entry:
608 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
609 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
610 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
611 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
612 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
613 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
614 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
615 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
616 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
617 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
618 // CHECK1-NEXT:    ret void
619 //
620 //
621 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
622 // CHECK1-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
623 // CHECK1-NEXT:  entry:
624 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
625 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
626 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
627 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
628 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
629 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
630 // CHECK1-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
631 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
632 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
633 // CHECK1-NEXT:    ret void
634 //
635 //
636 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
637 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
638 // CHECK1-NEXT:  entry:
639 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
640 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
641 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
642 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
643 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
644 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
645 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
646 // CHECK1-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
647 // CHECK1-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
648 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
649 // CHECK1-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
650 // CHECK1-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 8
651 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
652 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
653 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
654 // CHECK1-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
655 // CHECK1-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
656 // CHECK1:       .cancel.exit:
657 // CHECK1-NEXT:    br label [[DOTCANCEL_CONTINUE]]
658 // CHECK1:       .cancel.continue:
659 // CHECK1-NEXT:    ret void
660 //
661 //
662 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
663 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
664 // CHECK1-NEXT:  entry:
665 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
666 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
667 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
668 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
669 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
670 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
671 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
672 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
673 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
674 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
675 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
676 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
677 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
678 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
679 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
680 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
681 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
682 // CHECK1-NEXT:    ret void
683 //
684 //
685 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4
686 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
687 // CHECK1-NEXT:  entry:
688 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
689 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
690 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
691 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
692 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
693 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
694 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
695 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
696 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
697 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
698 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
699 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
700 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
701 // CHECK1-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
702 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
703 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
704 // CHECK1-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
705 // CHECK1-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
706 // CHECK1-NEXT:    ret void
707 //
708 //
709 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
710 // CHECK1-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
711 // CHECK1-NEXT:  entry:
712 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
713 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
714 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
715 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
716 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
717 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
718 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
719 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
720 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
721 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
722 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
723 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
724 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
725 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
726 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
727 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
728 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
729 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
730 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
731 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
732 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
733 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
734 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
735 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
736 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
737 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
738 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
739 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
740 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
741 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
742 // CHECK1-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
743 // CHECK1-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
744 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
745 // CHECK1-NEXT:    ret void
746 //
747 //
748 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7
749 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
750 // CHECK1-NEXT:  entry:
751 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
752 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
753 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
754 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
755 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
756 // CHECK1-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
757 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
758 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
759 // CHECK1-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
760 // CHECK1-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
761 // CHECK1-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
762 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
763 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
764 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
765 // CHECK1-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
766 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
767 // CHECK1-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
768 // CHECK1-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
769 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
770 // CHECK1-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
771 // CHECK1-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
772 // CHECK1-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
773 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
774 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
775 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
776 // CHECK1-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
777 // CHECK1-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
778 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
779 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
780 // CHECK1-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
781 // CHECK1-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
782 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
783 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
784 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
785 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
786 // CHECK1-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
787 // CHECK1-NEXT:    [[CONV5:%.*]] = fpext float [[TMP9]] to double
788 // CHECK1-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
789 // CHECK1-NEXT:    [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
790 // CHECK1-NEXT:    store float [[CONV7]], float* [[ARRAYIDX]], align 4
791 // CHECK1-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
792 // CHECK1-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
793 // CHECK1-NEXT:    [[CONV9:%.*]] = fpext float [[TMP10]] to double
794 // CHECK1-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
795 // CHECK1-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
796 // CHECK1-NEXT:    store float [[CONV11]], float* [[ARRAYIDX8]], align 4
797 // CHECK1-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
798 // CHECK1-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
799 // CHECK1-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
800 // CHECK1-NEXT:    [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
801 // CHECK1-NEXT:    store double [[ADD14]], double* [[ARRAYIDX13]], align 8
802 // CHECK1-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
803 // CHECK1-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
804 // CHECK1-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
805 // CHECK1-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
806 // CHECK1-NEXT:    [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
807 // CHECK1-NEXT:    store double [[ADD17]], double* [[ARRAYIDX16]], align 8
808 // CHECK1-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
809 // CHECK1-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 8
810 // CHECK1-NEXT:    [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
811 // CHECK1-NEXT:    store i64 [[ADD18]], i64* [[X]], align 8
812 // CHECK1-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
813 // CHECK1-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
814 // CHECK1-NEXT:    [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
815 // CHECK1-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
816 // CHECK1-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
817 // CHECK1-NEXT:    store i8 [[CONV21]], i8* [[Y]], align 8
818 // CHECK1-NEXT:    ret void
819 //
820 //
821 // CHECK1-LABEL: define {{[^@]+}}@_Z3bari
822 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
823 // CHECK1-NEXT:  entry:
824 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
825 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
826 // CHECK1-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
827 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
828 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
829 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
830 // CHECK1-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
831 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
832 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
833 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
834 // CHECK1-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
835 // CHECK1-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
836 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
837 // CHECK1-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
838 // CHECK1-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
839 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
840 // CHECK1-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
841 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
842 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
843 // CHECK1-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
844 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
845 // CHECK1-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
846 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
847 // CHECK1-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
848 // CHECK1-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
849 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
850 // CHECK1-NEXT:    ret i32 [[TMP8]]
851 //
852 //
853 // CHECK1-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
854 // CHECK1-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
855 // CHECK1-NEXT:  entry:
856 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
857 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
858 // CHECK1-NEXT:    [[B:%.*]] = alloca i32, align 4
859 // CHECK1-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
860 // CHECK1-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
861 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
862 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
863 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
864 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
865 // CHECK1-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
866 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
867 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
868 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
869 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
870 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
871 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
872 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
873 // CHECK1-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
874 // CHECK1-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
875 // CHECK1-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
876 // CHECK1-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
877 // CHECK1-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
878 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
879 // CHECK1-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
880 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
881 // CHECK1-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
882 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
883 // CHECK1-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
884 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
885 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
886 // CHECK1:       omp_if.then:
887 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
888 // CHECK1-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
889 // CHECK1-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
890 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
891 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
892 // CHECK1-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
893 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
894 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
895 // CHECK1-NEXT:    store double* [[A]], double** [[TMP13]], align 8
896 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
897 // CHECK1-NEXT:    store i64 8, i64* [[TMP14]], align 8
898 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
899 // CHECK1-NEXT:    store i8* null, i8** [[TMP15]], align 8
900 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
901 // CHECK1-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
902 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
903 // CHECK1-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
904 // CHECK1-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
905 // CHECK1-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
906 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
907 // CHECK1-NEXT:    store i64 4, i64* [[TMP20]], align 8
908 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
909 // CHECK1-NEXT:    store i8* null, i8** [[TMP21]], align 8
910 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
911 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
912 // CHECK1-NEXT:    store i64 2, i64* [[TMP23]], align 8
913 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
914 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
915 // CHECK1-NEXT:    store i64 2, i64* [[TMP25]], align 8
916 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
917 // CHECK1-NEXT:    store i64 8, i64* [[TMP26]], align 8
918 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
919 // CHECK1-NEXT:    store i8* null, i8** [[TMP27]], align 8
920 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
921 // CHECK1-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
922 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
923 // CHECK1-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
924 // CHECK1-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
925 // CHECK1-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
926 // CHECK1-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
927 // CHECK1-NEXT:    store i64 8, i64* [[TMP32]], align 8
928 // CHECK1-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
929 // CHECK1-NEXT:    store i8* null, i8** [[TMP33]], align 8
930 // CHECK1-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
931 // CHECK1-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
932 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
933 // CHECK1-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
934 // CHECK1-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
935 // CHECK1-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
936 // CHECK1-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
937 // CHECK1-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
938 // CHECK1-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
939 // CHECK1-NEXT:    store i8* null, i8** [[TMP39]], align 8
940 // CHECK1-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
941 // CHECK1-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
942 // CHECK1-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
943 // CHECK1-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
944 // CHECK1-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
945 // CHECK1-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
946 // CHECK1:       omp_offload.failed:
947 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
948 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
949 // CHECK1:       omp_offload.cont:
950 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
951 // CHECK1:       omp_if.else:
952 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
953 // CHECK1-NEXT:    br label [[OMP_IF_END]]
954 // CHECK1:       omp_if.end:
955 // CHECK1-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
956 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
957 // CHECK1-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
958 // CHECK1-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
959 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
960 // CHECK1-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
961 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
962 // CHECK1-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
963 // CHECK1-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
964 // CHECK1-NEXT:    ret i32 [[ADD4]]
965 //
966 //
967 // CHECK1-LABEL: define {{[^@]+}}@_ZL7fstatici
968 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
969 // CHECK1-NEXT:  entry:
970 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
971 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
972 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
973 // CHECK1-NEXT:    [[AAA:%.*]] = alloca i8, align 1
974 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
975 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
976 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
977 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
978 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
979 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
980 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
981 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
982 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
983 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
984 // CHECK1-NEXT:    store i8 0, i8* [[AAA]], align 1
985 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
986 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
987 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
988 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
989 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
990 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
991 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
992 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
993 // CHECK1-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
994 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
995 // CHECK1-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
996 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
997 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
998 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
999 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1000 // CHECK1:       omp_if.then:
1001 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1002 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1003 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
1004 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1005 // CHECK1-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
1006 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
1007 // CHECK1-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1008 // CHECK1-NEXT:    store i8* null, i8** [[TMP11]], align 8
1009 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1010 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1011 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
1012 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1013 // CHECK1-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
1014 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
1015 // CHECK1-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1016 // CHECK1-NEXT:    store i8* null, i8** [[TMP16]], align 8
1017 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1018 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
1019 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
1020 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1021 // CHECK1-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
1022 // CHECK1-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
1023 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1024 // CHECK1-NEXT:    store i8* null, i8** [[TMP21]], align 8
1025 // CHECK1-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1026 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
1027 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
1028 // CHECK1-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1029 // CHECK1-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
1030 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
1031 // CHECK1-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1032 // CHECK1-NEXT:    store i8* null, i8** [[TMP26]], align 8
1033 // CHECK1-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1034 // CHECK1-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1035 // CHECK1-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1036 // CHECK1-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
1037 // CHECK1-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1038 // CHECK1:       omp_offload.failed:
1039 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
1040 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1041 // CHECK1:       omp_offload.cont:
1042 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1043 // CHECK1:       omp_if.else:
1044 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
1045 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1046 // CHECK1:       omp_if.end:
1047 // CHECK1-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
1048 // CHECK1-NEXT:    ret i32 [[TMP31]]
1049 //
1050 //
1051 // CHECK1-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
1052 // CHECK1-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
1053 // CHECK1-NEXT:  entry:
1054 // CHECK1-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1055 // CHECK1-NEXT:    [[A:%.*]] = alloca i32, align 4
1056 // CHECK1-NEXT:    [[AA:%.*]] = alloca i16, align 2
1057 // CHECK1-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
1058 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1059 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1060 // CHECK1-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
1061 // CHECK1-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
1062 // CHECK1-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
1063 // CHECK1-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1064 // CHECK1-NEXT:    store i32 0, i32* [[A]], align 4
1065 // CHECK1-NEXT:    store i16 0, i16* [[AA]], align 2
1066 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
1067 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1068 // CHECK1-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
1069 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1070 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
1071 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1072 // CHECK1-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
1073 // CHECK1-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1074 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1075 // CHECK1-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
1076 // CHECK1-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1077 // CHECK1:       omp_if.then:
1078 // CHECK1-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1079 // CHECK1-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
1080 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
1081 // CHECK1-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1082 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
1083 // CHECK1-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
1084 // CHECK1-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1085 // CHECK1-NEXT:    store i8* null, i8** [[TMP9]], align 8
1086 // CHECK1-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1087 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
1088 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
1089 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1090 // CHECK1-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
1091 // CHECK1-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
1092 // CHECK1-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1093 // CHECK1-NEXT:    store i8* null, i8** [[TMP14]], align 8
1094 // CHECK1-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1095 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
1096 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
1097 // CHECK1-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1098 // CHECK1-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
1099 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
1100 // CHECK1-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1101 // CHECK1-NEXT:    store i8* null, i8** [[TMP19]], align 8
1102 // CHECK1-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1103 // CHECK1-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1104 // CHECK1-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1105 // CHECK1-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1106 // CHECK1-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1107 // CHECK1:       omp_offload.failed:
1108 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
1109 // CHECK1-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1110 // CHECK1:       omp_offload.cont:
1111 // CHECK1-NEXT:    br label [[OMP_IF_END:%.*]]
1112 // CHECK1:       omp_if.else:
1113 // CHECK1-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
1114 // CHECK1-NEXT:    br label [[OMP_IF_END]]
1115 // CHECK1:       omp_if.end:
1116 // CHECK1-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
1117 // CHECK1-NEXT:    ret i32 [[TMP24]]
1118 //
1119 //
1120 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
1121 // CHECK1-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1122 // CHECK1-NEXT:  entry:
1123 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1124 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1125 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1126 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1127 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1128 // CHECK1-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1129 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1130 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1131 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1132 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1133 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1134 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1135 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1136 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1137 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1138 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1139 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
1140 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1141 // CHECK1-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
1142 // CHECK1-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
1143 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
1144 // CHECK1-NEXT:    ret void
1145 //
1146 //
1147 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
1148 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
1149 // CHECK1-NEXT:  entry:
1150 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1151 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1152 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1153 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
1154 // CHECK1-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1155 // CHECK1-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1156 // CHECK1-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
1157 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1158 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1159 // CHECK1-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1160 // CHECK1-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
1161 // CHECK1-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1162 // CHECK1-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1163 // CHECK1-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
1164 // CHECK1-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1165 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
1166 // CHECK1-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1167 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1168 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
1169 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
1170 // CHECK1-NEXT:    [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
1171 // CHECK1-NEXT:    [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
1172 // CHECK1-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
1173 // CHECK1-NEXT:    store double [[ADD]], double* [[A]], align 8
1174 // CHECK1-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
1175 // CHECK1-NEXT:    [[TMP5:%.*]] = load double, double* [[A4]], align 8
1176 // CHECK1-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
1177 // CHECK1-NEXT:    store double [[INC]], double* [[A4]], align 8
1178 // CHECK1-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
1179 // CHECK1-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
1180 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
1181 // CHECK1-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1182 // CHECK1-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
1183 // CHECK1-NEXT:    ret void
1184 //
1185 //
1186 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
1187 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1188 // CHECK1-NEXT:  entry:
1189 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1190 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1191 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1192 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1193 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1194 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1195 // CHECK1-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
1196 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1197 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1198 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1199 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1200 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1201 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1202 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1203 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1204 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1205 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1206 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
1207 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1208 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
1209 // CHECK1-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1210 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
1211 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1212 // CHECK1-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
1213 // CHECK1-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
1214 // CHECK1-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
1215 // CHECK1-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
1216 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
1217 // CHECK1-NEXT:    ret void
1218 //
1219 //
1220 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..11
1221 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1222 // CHECK1-NEXT:  entry:
1223 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1224 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1225 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1226 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1227 // CHECK1-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
1228 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1229 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1230 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1231 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1232 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1233 // CHECK1-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
1234 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1235 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1236 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1237 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
1238 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1239 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1240 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
1241 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
1242 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
1243 // CHECK1-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
1244 // CHECK1-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
1245 // CHECK1-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
1246 // CHECK1-NEXT:    store i16 [[CONV5]], i16* [[CONV1]], align 8
1247 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
1248 // CHECK1-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
1249 // CHECK1-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
1250 // CHECK1-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
1251 // CHECK1-NEXT:    store i8 [[CONV8]], i8* [[CONV2]], align 8
1252 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1253 // CHECK1-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
1254 // CHECK1-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
1255 // CHECK1-NEXT:    store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
1256 // CHECK1-NEXT:    ret void
1257 //
1258 //
1259 // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
1260 // CHECK1-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1261 // CHECK1-NEXT:  entry:
1262 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1263 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1264 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1265 // CHECK1-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1266 // CHECK1-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1267 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1268 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1269 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1270 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1271 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1272 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1273 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1274 // CHECK1-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1275 // CHECK1-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
1276 // CHECK1-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
1277 // CHECK1-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
1278 // CHECK1-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1279 // CHECK1-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
1280 // CHECK1-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1281 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
1282 // CHECK1-NEXT:    ret void
1283 //
1284 //
1285 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..14
1286 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
1287 // CHECK1-NEXT:  entry:
1288 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1289 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1290 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1291 // CHECK1-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1292 // CHECK1-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
1293 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1294 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1295 // CHECK1-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1296 // CHECK1-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1297 // CHECK1-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
1298 // CHECK1-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1299 // CHECK1-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1300 // CHECK1-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
1301 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
1302 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
1303 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
1304 // CHECK1-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
1305 // CHECK1-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
1306 // CHECK1-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
1307 // CHECK1-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
1308 // CHECK1-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
1309 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
1310 // CHECK1-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
1311 // CHECK1-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
1312 // CHECK1-NEXT:    store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
1313 // CHECK1-NEXT:    ret void
1314 //
1315 //
1316 // CHECK1-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
1317 // CHECK1-SAME: () #[[ATTR5:[0-9]+]] {
1318 // CHECK1-NEXT:  entry:
1319 // CHECK1-NEXT:    call void @__tgt_register_requires(i64 1)
1320 // CHECK1-NEXT:    ret void
1321 //
1322 //
1323 // CHECK2-LABEL: define {{[^@]+}}@_Z3fooi
1324 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
1325 // CHECK2-NEXT:  entry:
1326 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1327 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
1328 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
1329 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
1330 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
1331 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1332 // CHECK2-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
1333 // CHECK2-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
1334 // CHECK2-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
1335 // CHECK2-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
1336 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1337 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1338 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
1339 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
1340 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
1341 // CHECK2-NEXT:    [[A_CASTED3:%.*]] = alloca i64, align 8
1342 // CHECK2-NEXT:    [[AA_CASTED5:%.*]] = alloca i64, align 8
1343 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8
1344 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8
1345 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8
1346 // CHECK2-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
1347 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8
1348 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8
1349 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8
1350 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
1351 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
1352 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1353 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
1354 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
1355 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1356 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1357 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
1358 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1359 // CHECK2-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
1360 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1361 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1362 // CHECK2-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
1363 // CHECK2-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
1364 // CHECK2-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
1365 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
1366 // CHECK2-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
1367 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
1368 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
1369 // CHECK2-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]])
1370 // CHECK2-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
1371 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1372 // CHECK2-NEXT:    store i32 [[TMP11]], i32* [[CONV]], align 4
1373 // CHECK2-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
1374 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR3:[0-9]+]]
1375 // CHECK2-NEXT:    [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
1376 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1377 // CHECK2-NEXT:    store i16 [[TMP13]], i16* [[CONV2]], align 2
1378 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1379 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1380 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
1381 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP16]], align 8
1382 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1383 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
1384 // CHECK2-NEXT:    store i64 [[TMP14]], i64* [[TMP18]], align 8
1385 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1386 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
1387 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1388 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1389 // CHECK2-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1390 // CHECK2-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
1391 // CHECK2-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1392 // CHECK2:       omp_offload.failed:
1393 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR3]]
1394 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1395 // CHECK2:       omp_offload.cont:
1396 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
1397 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32*
1398 // CHECK2-NEXT:    store i32 [[TMP24]], i32* [[CONV4]], align 4
1399 // CHECK2-NEXT:    [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8
1400 // CHECK2-NEXT:    [[TMP26:%.*]] = load i16, i16* [[AA]], align 2
1401 // CHECK2-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16*
1402 // CHECK2-NEXT:    store i16 [[TMP26]], i16* [[CONV6]], align 2
1403 // CHECK2-NEXT:    [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8
1404 // CHECK2-NEXT:    [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4
1405 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10
1406 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1407 // CHECK2:       omp_if.then:
1408 // CHECK2-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
1409 // CHECK2-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
1410 // CHECK2-NEXT:    store i64 [[TMP25]], i64* [[TMP30]], align 8
1411 // CHECK2-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
1412 // CHECK2-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
1413 // CHECK2-NEXT:    store i64 [[TMP25]], i64* [[TMP32]], align 8
1414 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
1415 // CHECK2-NEXT:    store i8* null, i8** [[TMP33]], align 8
1416 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1
1417 // CHECK2-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64*
1418 // CHECK2-NEXT:    store i64 [[TMP27]], i64* [[TMP35]], align 8
1419 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1
1420 // CHECK2-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
1421 // CHECK2-NEXT:    store i64 [[TMP27]], i64* [[TMP37]], align 8
1422 // CHECK2-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1
1423 // CHECK2-NEXT:    store i8* null, i8** [[TMP38]], align 8
1424 // CHECK2-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
1425 // CHECK2-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
1426 // CHECK2-NEXT:    [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1427 // CHECK2-NEXT:    [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
1428 // CHECK2-NEXT:    br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]]
1429 // CHECK2:       omp_offload.failed10:
1430 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]]
1431 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT11]]
1432 // CHECK2:       omp_offload.cont11:
1433 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
1434 // CHECK2:       omp_if.else:
1435 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]]
1436 // CHECK2-NEXT:    br label [[OMP_IF_END]]
1437 // CHECK2:       omp_if.end:
1438 // CHECK2-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4
1439 // CHECK2-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
1440 // CHECK2-NEXT:    store i32 [[TMP43]], i32* [[CONV13]], align 4
1441 // CHECK2-NEXT:    [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8
1442 // CHECK2-NEXT:    [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4
1443 // CHECK2-NEXT:    [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20
1444 // CHECK2-NEXT:    br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]]
1445 // CHECK2:       omp_if.then15:
1446 // CHECK2-NEXT:    [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4
1447 // CHECK2-NEXT:    [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]]
1448 // CHECK2-NEXT:    [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8
1449 // CHECK2-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
1450 // CHECK2-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64*
1451 // CHECK2-NEXT:    store i64 [[TMP44]], i64* [[TMP50]], align 8
1452 // CHECK2-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
1453 // CHECK2-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
1454 // CHECK2-NEXT:    store i64 [[TMP44]], i64* [[TMP52]], align 8
1455 // CHECK2-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1456 // CHECK2-NEXT:    store i64 4, i64* [[TMP53]], align 8
1457 // CHECK2-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
1458 // CHECK2-NEXT:    store i8* null, i8** [[TMP54]], align 8
1459 // CHECK2-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
1460 // CHECK2-NEXT:    [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]**
1461 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8
1462 // CHECK2-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
1463 // CHECK2-NEXT:    [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]**
1464 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8
1465 // CHECK2-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1466 // CHECK2-NEXT:    store i64 40, i64* [[TMP59]], align 8
1467 // CHECK2-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
1468 // CHECK2-NEXT:    store i8* null, i8** [[TMP60]], align 8
1469 // CHECK2-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2
1470 // CHECK2-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
1471 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP62]], align 8
1472 // CHECK2-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2
1473 // CHECK2-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
1474 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP64]], align 8
1475 // CHECK2-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1476 // CHECK2-NEXT:    store i64 8, i64* [[TMP65]], align 8
1477 // CHECK2-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2
1478 // CHECK2-NEXT:    store i8* null, i8** [[TMP66]], align 8
1479 // CHECK2-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3
1480 // CHECK2-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float**
1481 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP68]], align 8
1482 // CHECK2-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3
1483 // CHECK2-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float**
1484 // CHECK2-NEXT:    store float* [[VLA]], float** [[TMP70]], align 8
1485 // CHECK2-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1486 // CHECK2-NEXT:    store i64 [[TMP46]], i64* [[TMP71]], align 8
1487 // CHECK2-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3
1488 // CHECK2-NEXT:    store i8* null, i8** [[TMP72]], align 8
1489 // CHECK2-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4
1490 // CHECK2-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]**
1491 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8
1492 // CHECK2-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4
1493 // CHECK2-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]**
1494 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8
1495 // CHECK2-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1496 // CHECK2-NEXT:    store i64 400, i64* [[TMP77]], align 8
1497 // CHECK2-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4
1498 // CHECK2-NEXT:    store i8* null, i8** [[TMP78]], align 8
1499 // CHECK2-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5
1500 // CHECK2-NEXT:    [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*
1501 // CHECK2-NEXT:    store i64 5, i64* [[TMP80]], align 8
1502 // CHECK2-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5
1503 // CHECK2-NEXT:    [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64*
1504 // CHECK2-NEXT:    store i64 5, i64* [[TMP82]], align 8
1505 // CHECK2-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
1506 // CHECK2-NEXT:    store i64 8, i64* [[TMP83]], align 8
1507 // CHECK2-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5
1508 // CHECK2-NEXT:    store i8* null, i8** [[TMP84]], align 8
1509 // CHECK2-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6
1510 // CHECK2-NEXT:    [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64*
1511 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP86]], align 8
1512 // CHECK2-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6
1513 // CHECK2-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64*
1514 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP88]], align 8
1515 // CHECK2-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
1516 // CHECK2-NEXT:    store i64 8, i64* [[TMP89]], align 8
1517 // CHECK2-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6
1518 // CHECK2-NEXT:    store i8* null, i8** [[TMP90]], align 8
1519 // CHECK2-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7
1520 // CHECK2-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double**
1521 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP92]], align 8
1522 // CHECK2-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7
1523 // CHECK2-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double**
1524 // CHECK2-NEXT:    store double* [[VLA1]], double** [[TMP94]], align 8
1525 // CHECK2-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
1526 // CHECK2-NEXT:    store i64 [[TMP48]], i64* [[TMP95]], align 8
1527 // CHECK2-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7
1528 // CHECK2-NEXT:    store i8* null, i8** [[TMP96]], align 8
1529 // CHECK2-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8
1530 // CHECK2-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT**
1531 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8
1532 // CHECK2-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8
1533 // CHECK2-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT**
1534 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8
1535 // CHECK2-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
1536 // CHECK2-NEXT:    store i64 16, i64* [[TMP101]], align 8
1537 // CHECK2-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8
1538 // CHECK2-NEXT:    store i8* null, i8** [[TMP102]], align 8
1539 // CHECK2-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
1540 // CHECK2-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
1541 // CHECK2-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1542 // CHECK2-NEXT:    [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1543 // CHECK2-NEXT:    [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0
1544 // CHECK2-NEXT:    br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
1545 // CHECK2:       omp_offload.failed19:
1546 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
1547 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT20]]
1548 // CHECK2:       omp_offload.cont20:
1549 // CHECK2-NEXT:    br label [[OMP_IF_END22:%.*]]
1550 // CHECK2:       omp_if.else21:
1551 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
1552 // CHECK2-NEXT:    br label [[OMP_IF_END22]]
1553 // CHECK2:       omp_if.end22:
1554 // CHECK2-NEXT:    [[TMP108:%.*]] = load i32, i32* [[A]], align 4
1555 // CHECK2-NEXT:    [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1556 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP109]])
1557 // CHECK2-NEXT:    ret i32 [[TMP108]]
1558 //
1559 //
1560 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
1561 // CHECK2-SAME: () #[[ATTR2:[0-9]+]] {
1562 // CHECK2-NEXT:  entry:
1563 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1564 // CHECK2-NEXT:    ret void
1565 //
1566 //
1567 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
1568 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
1569 // CHECK2-NEXT:  entry:
1570 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1571 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1572 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1573 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1574 // CHECK2-NEXT:    ret void
1575 //
1576 //
1577 // CHECK2-LABEL: define {{[^@]+}}@.omp_task_entry.
1578 // CHECK2-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
1579 // CHECK2-NEXT:  entry:
1580 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
1581 // CHECK2-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
1582 // CHECK2-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
1583 // CHECK2-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
1584 // CHECK2-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
1585 // CHECK2-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
1586 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
1587 // CHECK2-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
1588 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
1589 // CHECK2-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
1590 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
1591 // CHECK2-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
1592 // CHECK2-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
1593 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
1594 // CHECK2-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
1595 // CHECK2-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
1596 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
1597 // CHECK2-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
1598 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])
1599 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
1600 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
1601 // CHECK2-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
1602 // CHECK2-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20
1603 // CHECK2-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20
1604 // CHECK2-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
1605 // CHECK2-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
1606 // CHECK2-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20
1607 // CHECK2-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
1608 // CHECK2-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
1609 // CHECK2-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
1610 // CHECK2-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
1611 // CHECK2-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
1612 // CHECK2:       omp_offload.failed.i:
1613 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
1614 // CHECK2-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
1615 // CHECK2:       .omp_outlined..1.exit:
1616 // CHECK2-NEXT:    ret i32 0
1617 //
1618 //
1619 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
1620 // CHECK2-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
1621 // CHECK2-NEXT:  entry:
1622 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1623 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1624 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1625 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1626 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1627 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1628 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
1629 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1630 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
1631 // CHECK2-NEXT:    ret void
1632 //
1633 //
1634 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2
1635 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
1636 // CHECK2-NEXT:  entry:
1637 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1638 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1639 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1640 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1641 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1642 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1643 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1644 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1645 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1646 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
1647 // CHECK2-NEXT:    ret void
1648 //
1649 //
1650 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
1651 // CHECK2-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
1652 // CHECK2-NEXT:  entry:
1653 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1654 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1655 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1656 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1657 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
1658 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1659 // CHECK2-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
1660 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1661 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
1662 // CHECK2-NEXT:    ret void
1663 //
1664 //
1665 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
1666 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
1667 // CHECK2-NEXT:  entry:
1668 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1669 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1670 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1671 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1672 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1673 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1674 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1675 // CHECK2-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
1676 // CHECK2-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
1677 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
1678 // CHECK2-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
1679 // CHECK2-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 8
1680 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1681 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
1682 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
1683 // CHECK2-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
1684 // CHECK2-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
1685 // CHECK2:       .cancel.exit:
1686 // CHECK2-NEXT:    br label [[DOTCANCEL_CONTINUE]]
1687 // CHECK2:       .cancel.continue:
1688 // CHECK2-NEXT:    ret void
1689 //
1690 //
1691 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
1692 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
1693 // CHECK2-NEXT:  entry:
1694 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1695 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1696 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1697 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
1698 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1699 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1700 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1701 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1702 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1703 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1704 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
1705 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
1706 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
1707 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
1708 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
1709 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
1710 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
1711 // CHECK2-NEXT:    ret void
1712 //
1713 //
1714 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4
1715 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
1716 // CHECK2-NEXT:  entry:
1717 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1718 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1719 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1720 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
1721 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1722 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1723 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1724 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
1725 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1726 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
1727 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
1728 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1729 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
1730 // CHECK2-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
1731 // CHECK2-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
1732 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
1733 // CHECK2-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
1734 // CHECK2-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
1735 // CHECK2-NEXT:    ret void
1736 //
1737 //
1738 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
1739 // CHECK2-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
1740 // CHECK2-NEXT:  entry:
1741 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1742 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1743 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1744 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1745 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1746 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1747 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1748 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1749 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1750 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
1751 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1752 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1753 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1754 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1755 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1756 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1757 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1758 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1759 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1760 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1761 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1762 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1763 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1764 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1765 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1766 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1767 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1768 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1769 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
1770 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
1771 // CHECK2-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
1772 // CHECK2-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
1773 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
1774 // CHECK2-NEXT:    ret void
1775 //
1776 //
1777 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7
1778 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
1779 // CHECK2-NEXT:  entry:
1780 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1781 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1782 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
1783 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
1784 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
1785 // CHECK2-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
1786 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
1787 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
1788 // CHECK2-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
1789 // CHECK2-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
1790 // CHECK2-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
1791 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1792 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1793 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
1794 // CHECK2-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
1795 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
1796 // CHECK2-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
1797 // CHECK2-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
1798 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
1799 // CHECK2-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
1800 // CHECK2-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
1801 // CHECK2-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
1802 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
1803 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
1804 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
1805 // CHECK2-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
1806 // CHECK2-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
1807 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
1808 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
1809 // CHECK2-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
1810 // CHECK2-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
1811 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
1812 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
1813 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
1814 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
1815 // CHECK2-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
1816 // CHECK2-NEXT:    [[CONV5:%.*]] = fpext float [[TMP9]] to double
1817 // CHECK2-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
1818 // CHECK2-NEXT:    [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
1819 // CHECK2-NEXT:    store float [[CONV7]], float* [[ARRAYIDX]], align 4
1820 // CHECK2-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
1821 // CHECK2-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
1822 // CHECK2-NEXT:    [[CONV9:%.*]] = fpext float [[TMP10]] to double
1823 // CHECK2-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
1824 // CHECK2-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
1825 // CHECK2-NEXT:    store float [[CONV11]], float* [[ARRAYIDX8]], align 4
1826 // CHECK2-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
1827 // CHECK2-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
1828 // CHECK2-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
1829 // CHECK2-NEXT:    [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
1830 // CHECK2-NEXT:    store double [[ADD14]], double* [[ARRAYIDX13]], align 8
1831 // CHECK2-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
1832 // CHECK2-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
1833 // CHECK2-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
1834 // CHECK2-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
1835 // CHECK2-NEXT:    [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
1836 // CHECK2-NEXT:    store double [[ADD17]], double* [[ARRAYIDX16]], align 8
1837 // CHECK2-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
1838 // CHECK2-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 8
1839 // CHECK2-NEXT:    [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
1840 // CHECK2-NEXT:    store i64 [[ADD18]], i64* [[X]], align 8
1841 // CHECK2-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
1842 // CHECK2-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
1843 // CHECK2-NEXT:    [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
1844 // CHECK2-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
1845 // CHECK2-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
1846 // CHECK2-NEXT:    store i8 [[CONV21]], i8* [[Y]], align 8
1847 // CHECK2-NEXT:    ret void
1848 //
1849 //
1850 // CHECK2-LABEL: define {{[^@]+}}@_Z3bari
1851 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1852 // CHECK2-NEXT:  entry:
1853 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1854 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
1855 // CHECK2-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
1856 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1857 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
1858 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1859 // CHECK2-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
1860 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
1861 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
1862 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
1863 // CHECK2-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
1864 // CHECK2-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
1865 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
1866 // CHECK2-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
1867 // CHECK2-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
1868 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
1869 // CHECK2-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
1870 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
1871 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
1872 // CHECK2-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
1873 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
1874 // CHECK2-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
1875 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
1876 // CHECK2-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
1877 // CHECK2-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
1878 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
1879 // CHECK2-NEXT:    ret i32 [[TMP8]]
1880 //
1881 //
1882 // CHECK2-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
1883 // CHECK2-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
1884 // CHECK2-NEXT:  entry:
1885 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
1886 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
1887 // CHECK2-NEXT:    [[B:%.*]] = alloca i32, align 4
1888 // CHECK2-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
1889 // CHECK2-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
1890 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
1891 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
1892 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
1893 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
1894 // CHECK2-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
1895 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
1896 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
1897 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
1898 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
1899 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
1900 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
1901 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
1902 // CHECK2-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
1903 // CHECK2-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
1904 // CHECK2-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
1905 // CHECK2-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
1906 // CHECK2-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
1907 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
1908 // CHECK2-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
1909 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
1910 // CHECK2-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
1911 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
1912 // CHECK2-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
1913 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
1914 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
1915 // CHECK2:       omp_if.then:
1916 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
1917 // CHECK2-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
1918 // CHECK2-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
1919 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1920 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
1921 // CHECK2-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
1922 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1923 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
1924 // CHECK2-NEXT:    store double* [[A]], double** [[TMP13]], align 8
1925 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1926 // CHECK2-NEXT:    store i64 8, i64* [[TMP14]], align 8
1927 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
1928 // CHECK2-NEXT:    store i8* null, i8** [[TMP15]], align 8
1929 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
1930 // CHECK2-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
1931 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
1932 // CHECK2-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
1933 // CHECK2-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
1934 // CHECK2-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
1935 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
1936 // CHECK2-NEXT:    store i64 4, i64* [[TMP20]], align 8
1937 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
1938 // CHECK2-NEXT:    store i8* null, i8** [[TMP21]], align 8
1939 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
1940 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
1941 // CHECK2-NEXT:    store i64 2, i64* [[TMP23]], align 8
1942 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
1943 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
1944 // CHECK2-NEXT:    store i64 2, i64* [[TMP25]], align 8
1945 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
1946 // CHECK2-NEXT:    store i64 8, i64* [[TMP26]], align 8
1947 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
1948 // CHECK2-NEXT:    store i8* null, i8** [[TMP27]], align 8
1949 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
1950 // CHECK2-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
1951 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
1952 // CHECK2-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
1953 // CHECK2-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
1954 // CHECK2-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
1955 // CHECK2-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
1956 // CHECK2-NEXT:    store i64 8, i64* [[TMP32]], align 8
1957 // CHECK2-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
1958 // CHECK2-NEXT:    store i8* null, i8** [[TMP33]], align 8
1959 // CHECK2-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
1960 // CHECK2-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
1961 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
1962 // CHECK2-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
1963 // CHECK2-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
1964 // CHECK2-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
1965 // CHECK2-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
1966 // CHECK2-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
1967 // CHECK2-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
1968 // CHECK2-NEXT:    store i8* null, i8** [[TMP39]], align 8
1969 // CHECK2-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
1970 // CHECK2-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
1971 // CHECK2-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
1972 // CHECK2-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
1973 // CHECK2-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
1974 // CHECK2-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
1975 // CHECK2:       omp_offload.failed:
1976 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
1977 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
1978 // CHECK2:       omp_offload.cont:
1979 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
1980 // CHECK2:       omp_if.else:
1981 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
1982 // CHECK2-NEXT:    br label [[OMP_IF_END]]
1983 // CHECK2:       omp_if.end:
1984 // CHECK2-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
1985 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
1986 // CHECK2-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
1987 // CHECK2-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
1988 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
1989 // CHECK2-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
1990 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
1991 // CHECK2-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
1992 // CHECK2-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
1993 // CHECK2-NEXT:    ret i32 [[ADD4]]
1994 //
1995 //
1996 // CHECK2-LABEL: define {{[^@]+}}@_ZL7fstatici
1997 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
1998 // CHECK2-NEXT:  entry:
1999 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2000 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
2001 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
2002 // CHECK2-NEXT:    [[AAA:%.*]] = alloca i8, align 1
2003 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
2004 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2005 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2006 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
2007 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
2008 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
2009 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
2010 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2011 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
2012 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
2013 // CHECK2-NEXT:    store i8 0, i8* [[AAA]], align 1
2014 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
2015 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2016 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
2017 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2018 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
2019 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2020 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
2021 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2022 // CHECK2-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
2023 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
2024 // CHECK2-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
2025 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
2026 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
2027 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
2028 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2029 // CHECK2:       omp_if.then:
2030 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2031 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
2032 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
2033 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2034 // CHECK2-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
2035 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
2036 // CHECK2-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2037 // CHECK2-NEXT:    store i8* null, i8** [[TMP11]], align 8
2038 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2039 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
2040 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
2041 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2042 // CHECK2-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
2043 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
2044 // CHECK2-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2045 // CHECK2-NEXT:    store i8* null, i8** [[TMP16]], align 8
2046 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2047 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
2048 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
2049 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2050 // CHECK2-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
2051 // CHECK2-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
2052 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2053 // CHECK2-NEXT:    store i8* null, i8** [[TMP21]], align 8
2054 // CHECK2-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2055 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
2056 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
2057 // CHECK2-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2058 // CHECK2-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
2059 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
2060 // CHECK2-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
2061 // CHECK2-NEXT:    store i8* null, i8** [[TMP26]], align 8
2062 // CHECK2-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2063 // CHECK2-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2064 // CHECK2-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2065 // CHECK2-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
2066 // CHECK2-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2067 // CHECK2:       omp_offload.failed:
2068 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
2069 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2070 // CHECK2:       omp_offload.cont:
2071 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
2072 // CHECK2:       omp_if.else:
2073 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
2074 // CHECK2-NEXT:    br label [[OMP_IF_END]]
2075 // CHECK2:       omp_if.end:
2076 // CHECK2-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
2077 // CHECK2-NEXT:    ret i32 [[TMP31]]
2078 //
2079 //
2080 // CHECK2-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
2081 // CHECK2-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
2082 // CHECK2-NEXT:  entry:
2083 // CHECK2-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2084 // CHECK2-NEXT:    [[A:%.*]] = alloca i32, align 4
2085 // CHECK2-NEXT:    [[AA:%.*]] = alloca i16, align 2
2086 // CHECK2-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
2087 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2088 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2089 // CHECK2-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
2090 // CHECK2-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
2091 // CHECK2-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
2092 // CHECK2-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2093 // CHECK2-NEXT:    store i32 0, i32* [[A]], align 4
2094 // CHECK2-NEXT:    store i16 0, i16* [[AA]], align 2
2095 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
2096 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2097 // CHECK2-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
2098 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
2099 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
2100 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2101 // CHECK2-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
2102 // CHECK2-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2103 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2104 // CHECK2-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
2105 // CHECK2-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2106 // CHECK2:       omp_if.then:
2107 // CHECK2-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2108 // CHECK2-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
2109 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
2110 // CHECK2-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2111 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
2112 // CHECK2-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
2113 // CHECK2-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
2114 // CHECK2-NEXT:    store i8* null, i8** [[TMP9]], align 8
2115 // CHECK2-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2116 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
2117 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
2118 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2119 // CHECK2-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
2120 // CHECK2-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
2121 // CHECK2-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
2122 // CHECK2-NEXT:    store i8* null, i8** [[TMP14]], align 8
2123 // CHECK2-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2124 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
2125 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
2126 // CHECK2-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2127 // CHECK2-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
2128 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
2129 // CHECK2-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
2130 // CHECK2-NEXT:    store i8* null, i8** [[TMP19]], align 8
2131 // CHECK2-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2132 // CHECK2-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2133 // CHECK2-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2134 // CHECK2-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
2135 // CHECK2-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2136 // CHECK2:       omp_offload.failed:
2137 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
2138 // CHECK2-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2139 // CHECK2:       omp_offload.cont:
2140 // CHECK2-NEXT:    br label [[OMP_IF_END:%.*]]
2141 // CHECK2:       omp_if.else:
2142 // CHECK2-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
2143 // CHECK2-NEXT:    br label [[OMP_IF_END]]
2144 // CHECK2:       omp_if.end:
2145 // CHECK2-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
2146 // CHECK2-NEXT:    ret i32 [[TMP24]]
2147 //
2148 //
2149 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
2150 // CHECK2-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
2151 // CHECK2-NEXT:  entry:
2152 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2153 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2154 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2155 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2156 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
2157 // CHECK2-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
2158 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2159 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
2160 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2161 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2162 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
2163 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2164 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2165 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2166 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2167 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
2168 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
2169 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
2170 // CHECK2-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
2171 // CHECK2-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
2172 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
2173 // CHECK2-NEXT:    ret void
2174 //
2175 //
2176 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
2177 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
2178 // CHECK2-NEXT:  entry:
2179 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2180 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2181 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
2182 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
2183 // CHECK2-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
2184 // CHECK2-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
2185 // CHECK2-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
2186 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2187 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2188 // CHECK2-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
2189 // CHECK2-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
2190 // CHECK2-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
2191 // CHECK2-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
2192 // CHECK2-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
2193 // CHECK2-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
2194 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
2195 // CHECK2-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
2196 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
2197 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
2198 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
2199 // CHECK2-NEXT:    [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
2200 // CHECK2-NEXT:    [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
2201 // CHECK2-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
2202 // CHECK2-NEXT:    store double [[ADD]], double* [[A]], align 8
2203 // CHECK2-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
2204 // CHECK2-NEXT:    [[TMP5:%.*]] = load double, double* [[A4]], align 8
2205 // CHECK2-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
2206 // CHECK2-NEXT:    store double [[INC]], double* [[A4]], align 8
2207 // CHECK2-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
2208 // CHECK2-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
2209 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
2210 // CHECK2-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
2211 // CHECK2-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
2212 // CHECK2-NEXT:    ret void
2213 //
2214 //
2215 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
2216 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2217 // CHECK2-NEXT:  entry:
2218 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2219 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2220 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
2221 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
2222 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2223 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2224 // CHECK2-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
2225 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2226 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2227 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
2228 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
2229 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2230 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2231 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
2232 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
2233 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
2234 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2235 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
2236 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
2237 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
2238 // CHECK2-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2239 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
2240 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2241 // CHECK2-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
2242 // CHECK2-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
2243 // CHECK2-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
2244 // CHECK2-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
2245 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
2246 // CHECK2-NEXT:    ret void
2247 //
2248 //
2249 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..11
2250 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2251 // CHECK2-NEXT:  entry:
2252 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2253 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2254 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2255 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2256 // CHECK2-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
2257 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
2258 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2259 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2260 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2261 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2262 // CHECK2-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
2263 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
2264 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2265 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2266 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
2267 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
2268 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
2269 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2270 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
2271 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
2272 // CHECK2-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
2273 // CHECK2-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
2274 // CHECK2-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
2275 // CHECK2-NEXT:    store i16 [[CONV5]], i16* [[CONV1]], align 8
2276 // CHECK2-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
2277 // CHECK2-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
2278 // CHECK2-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
2279 // CHECK2-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
2280 // CHECK2-NEXT:    store i8 [[CONV8]], i8* [[CONV2]], align 8
2281 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
2282 // CHECK2-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
2283 // CHECK2-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
2284 // CHECK2-NEXT:    store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
2285 // CHECK2-NEXT:    ret void
2286 //
2287 //
2288 // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
2289 // CHECK2-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2290 // CHECK2-NEXT:  entry:
2291 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2292 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2293 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
2294 // CHECK2-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
2295 // CHECK2-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
2296 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2297 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2298 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
2299 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2300 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2301 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
2302 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
2303 // CHECK2-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
2304 // CHECK2-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
2305 // CHECK2-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
2306 // CHECK2-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
2307 // CHECK2-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
2308 // CHECK2-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
2309 // CHECK2-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
2310 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
2311 // CHECK2-NEXT:    ret void
2312 //
2313 //
2314 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..14
2315 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
2316 // CHECK2-NEXT:  entry:
2317 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2318 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2319 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
2320 // CHECK2-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
2321 // CHECK2-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
2322 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2323 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2324 // CHECK2-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
2325 // CHECK2-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
2326 // CHECK2-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
2327 // CHECK2-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
2328 // CHECK2-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
2329 // CHECK2-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
2330 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
2331 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
2332 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
2333 // CHECK2-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
2334 // CHECK2-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
2335 // CHECK2-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
2336 // CHECK2-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
2337 // CHECK2-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
2338 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
2339 // CHECK2-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
2340 // CHECK2-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
2341 // CHECK2-NEXT:    store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
2342 // CHECK2-NEXT:    ret void
2343 //
2344 //
2345 // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
2346 // CHECK2-SAME: () #[[ATTR5:[0-9]+]] {
2347 // CHECK2-NEXT:  entry:
2348 // CHECK2-NEXT:    call void @__tgt_register_requires(i64 1)
2349 // CHECK2-NEXT:    ret void
2350 //
2351 //
2352 // CHECK3-LABEL: define {{[^@]+}}@_Z3fooi
2353 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
2354 // CHECK3-NEXT:  entry:
2355 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2356 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
2357 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
2358 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
2359 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
2360 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
2361 // CHECK3-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
2362 // CHECK3-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
2363 // CHECK3-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
2364 // CHECK3-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
2365 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2366 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2367 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
2368 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
2369 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
2370 // CHECK3-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
2371 // CHECK3-NEXT:    [[AA_CASTED3:%.*]] = alloca i32, align 4
2372 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4
2373 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4
2374 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4
2375 // CHECK3-NEXT:    [[A_CASTED10:%.*]] = alloca i32, align 4
2376 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4
2377 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4
2378 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4
2379 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
2380 // CHECK3-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
2381 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2382 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
2383 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
2384 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2385 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
2386 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
2387 // CHECK3-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
2388 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
2389 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
2390 // CHECK3-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
2391 // CHECK3-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
2392 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
2393 // CHECK3-NEXT:    [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
2394 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
2395 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
2396 // CHECK3-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]])
2397 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
2398 // CHECK3-NEXT:    store i32 [[TMP9]], i32* [[A_CASTED]], align 4
2399 // CHECK3-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
2400 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR3:[0-9]+]]
2401 // CHECK3-NEXT:    [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
2402 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2403 // CHECK3-NEXT:    store i16 [[TMP11]], i16* [[CONV]], align 2
2404 // CHECK3-NEXT:    [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2405 // CHECK3-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2406 // CHECK3-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
2407 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP14]], align 4
2408 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2409 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
2410 // CHECK3-NEXT:    store i32 [[TMP12]], i32* [[TMP16]], align 4
2411 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2412 // CHECK3-NEXT:    store i8* null, i8** [[TMP17]], align 4
2413 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2414 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2415 // CHECK3-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2416 // CHECK3-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
2417 // CHECK3-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2418 // CHECK3:       omp_offload.failed:
2419 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR3]]
2420 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2421 // CHECK3:       omp_offload.cont:
2422 // CHECK3-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
2423 // CHECK3-NEXT:    store i32 [[TMP22]], i32* [[A_CASTED2]], align 4
2424 // CHECK3-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4
2425 // CHECK3-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2
2426 // CHECK3-NEXT:    [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16*
2427 // CHECK3-NEXT:    store i16 [[TMP24]], i16* [[CONV4]], align 2
2428 // CHECK3-NEXT:    [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4
2429 // CHECK3-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
2430 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10
2431 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2432 // CHECK3:       omp_if.then:
2433 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2434 // CHECK3-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
2435 // CHECK3-NEXT:    store i32 [[TMP23]], i32* [[TMP28]], align 4
2436 // CHECK3-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2437 // CHECK3-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
2438 // CHECK3-NEXT:    store i32 [[TMP23]], i32* [[TMP30]], align 4
2439 // CHECK3-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
2440 // CHECK3-NEXT:    store i8* null, i8** [[TMP31]], align 4
2441 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
2442 // CHECK3-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32*
2443 // CHECK3-NEXT:    store i32 [[TMP25]], i32* [[TMP33]], align 4
2444 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
2445 // CHECK3-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32*
2446 // CHECK3-NEXT:    store i32 [[TMP25]], i32* [[TMP35]], align 4
2447 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1
2448 // CHECK3-NEXT:    store i8* null, i8** [[TMP36]], align 4
2449 // CHECK3-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
2450 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
2451 // CHECK3-NEXT:    [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2452 // CHECK3-NEXT:    [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
2453 // CHECK3-NEXT:    br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
2454 // CHECK3:       omp_offload.failed8:
2455 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]]
2456 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT9]]
2457 // CHECK3:       omp_offload.cont9:
2458 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
2459 // CHECK3:       omp_if.else:
2460 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]]
2461 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2462 // CHECK3:       omp_if.end:
2463 // CHECK3-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4
2464 // CHECK3-NEXT:    store i32 [[TMP41]], i32* [[A_CASTED10]], align 4
2465 // CHECK3-NEXT:    [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4
2466 // CHECK3-NEXT:    [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4
2467 // CHECK3-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20
2468 // CHECK3-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]]
2469 // CHECK3:       omp_if.then12:
2470 // CHECK3-NEXT:    [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4
2471 // CHECK3-NEXT:    [[TMP45:%.*]] = sext i32 [[TMP44]] to i64
2472 // CHECK3-NEXT:    [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]]
2473 // CHECK3-NEXT:    [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8
2474 // CHECK3-NEXT:    [[TMP48:%.*]] = sext i32 [[TMP47]] to i64
2475 // CHECK3-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
2476 // CHECK3-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
2477 // CHECK3-NEXT:    store i32 [[TMP42]], i32* [[TMP50]], align 4
2478 // CHECK3-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
2479 // CHECK3-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
2480 // CHECK3-NEXT:    store i32 [[TMP42]], i32* [[TMP52]], align 4
2481 // CHECK3-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2482 // CHECK3-NEXT:    store i64 4, i64* [[TMP53]], align 4
2483 // CHECK3-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
2484 // CHECK3-NEXT:    store i8* null, i8** [[TMP54]], align 4
2485 // CHECK3-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
2486 // CHECK3-NEXT:    [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]**
2487 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4
2488 // CHECK3-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
2489 // CHECK3-NEXT:    [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]**
2490 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4
2491 // CHECK3-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2492 // CHECK3-NEXT:    store i64 40, i64* [[TMP59]], align 4
2493 // CHECK3-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1
2494 // CHECK3-NEXT:    store i8* null, i8** [[TMP60]], align 4
2495 // CHECK3-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2
2496 // CHECK3-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
2497 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP62]], align 4
2498 // CHECK3-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2
2499 // CHECK3-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*
2500 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP64]], align 4
2501 // CHECK3-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2502 // CHECK3-NEXT:    store i64 4, i64* [[TMP65]], align 4
2503 // CHECK3-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2
2504 // CHECK3-NEXT:    store i8* null, i8** [[TMP66]], align 4
2505 // CHECK3-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3
2506 // CHECK3-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float**
2507 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP68]], align 4
2508 // CHECK3-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3
2509 // CHECK3-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float**
2510 // CHECK3-NEXT:    store float* [[VLA]], float** [[TMP70]], align 4
2511 // CHECK3-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2512 // CHECK3-NEXT:    store i64 [[TMP45]], i64* [[TMP71]], align 4
2513 // CHECK3-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3
2514 // CHECK3-NEXT:    store i8* null, i8** [[TMP72]], align 4
2515 // CHECK3-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4
2516 // CHECK3-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]**
2517 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4
2518 // CHECK3-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4
2519 // CHECK3-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]**
2520 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4
2521 // CHECK3-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2522 // CHECK3-NEXT:    store i64 400, i64* [[TMP77]], align 4
2523 // CHECK3-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4
2524 // CHECK3-NEXT:    store i8* null, i8** [[TMP78]], align 4
2525 // CHECK3-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5
2526 // CHECK3-NEXT:    [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*
2527 // CHECK3-NEXT:    store i32 5, i32* [[TMP80]], align 4
2528 // CHECK3-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5
2529 // CHECK3-NEXT:    [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32*
2530 // CHECK3-NEXT:    store i32 5, i32* [[TMP82]], align 4
2531 // CHECK3-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
2532 // CHECK3-NEXT:    store i64 4, i64* [[TMP83]], align 4
2533 // CHECK3-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5
2534 // CHECK3-NEXT:    store i8* null, i8** [[TMP84]], align 4
2535 // CHECK3-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6
2536 // CHECK3-NEXT:    [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32*
2537 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP86]], align 4
2538 // CHECK3-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6
2539 // CHECK3-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
2540 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP88]], align 4
2541 // CHECK3-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
2542 // CHECK3-NEXT:    store i64 4, i64* [[TMP89]], align 4
2543 // CHECK3-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6
2544 // CHECK3-NEXT:    store i8* null, i8** [[TMP90]], align 4
2545 // CHECK3-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7
2546 // CHECK3-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double**
2547 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP92]], align 4
2548 // CHECK3-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7
2549 // CHECK3-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double**
2550 // CHECK3-NEXT:    store double* [[VLA1]], double** [[TMP94]], align 4
2551 // CHECK3-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
2552 // CHECK3-NEXT:    store i64 [[TMP48]], i64* [[TMP95]], align 4
2553 // CHECK3-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7
2554 // CHECK3-NEXT:    store i8* null, i8** [[TMP96]], align 4
2555 // CHECK3-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8
2556 // CHECK3-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT**
2557 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4
2558 // CHECK3-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8
2559 // CHECK3-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT**
2560 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4
2561 // CHECK3-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
2562 // CHECK3-NEXT:    store i64 12, i64* [[TMP101]], align 4
2563 // CHECK3-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8
2564 // CHECK3-NEXT:    store i8* null, i8** [[TMP102]], align 4
2565 // CHECK3-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
2566 // CHECK3-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
2567 // CHECK3-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2568 // CHECK3-NEXT:    [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2569 // CHECK3-NEXT:    [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0
2570 // CHECK3-NEXT:    br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
2571 // CHECK3:       omp_offload.failed16:
2572 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
2573 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
2574 // CHECK3:       omp_offload.cont17:
2575 // CHECK3-NEXT:    br label [[OMP_IF_END19:%.*]]
2576 // CHECK3:       omp_if.else18:
2577 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
2578 // CHECK3-NEXT:    br label [[OMP_IF_END19]]
2579 // CHECK3:       omp_if.end19:
2580 // CHECK3-NEXT:    [[TMP108:%.*]] = load i32, i32* [[A]], align 4
2581 // CHECK3-NEXT:    [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
2582 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP109]])
2583 // CHECK3-NEXT:    ret i32 [[TMP108]]
2584 //
2585 //
2586 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
2587 // CHECK3-SAME: () #[[ATTR2:[0-9]+]] {
2588 // CHECK3-NEXT:  entry:
2589 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
2590 // CHECK3-NEXT:    ret void
2591 //
2592 //
2593 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
2594 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
2595 // CHECK3-NEXT:  entry:
2596 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2597 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2598 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2599 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2600 // CHECK3-NEXT:    ret void
2601 //
2602 //
2603 // CHECK3-LABEL: define {{[^@]+}}@.omp_task_entry.
2604 // CHECK3-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
2605 // CHECK3-NEXT:  entry:
2606 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
2607 // CHECK3-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
2608 // CHECK3-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
2609 // CHECK3-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
2610 // CHECK3-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
2611 // CHECK3-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
2612 // CHECK3-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
2613 // CHECK3-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
2614 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
2615 // CHECK3-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
2616 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
2617 // CHECK3-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
2618 // CHECK3-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
2619 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
2620 // CHECK3-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
2621 // CHECK3-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
2622 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
2623 // CHECK3-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
2624 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
2625 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
2626 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
2627 // CHECK3-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
2628 // CHECK3-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
2629 // CHECK3-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21
2630 // CHECK3-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
2631 // CHECK3-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
2632 // CHECK3-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21
2633 // CHECK3-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
2634 // CHECK3-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
2635 // CHECK3-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
2636 // CHECK3-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
2637 // CHECK3-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
2638 // CHECK3:       omp_offload.failed.i:
2639 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
2640 // CHECK3-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
2641 // CHECK3:       .omp_outlined..1.exit:
2642 // CHECK3-NEXT:    ret i32 0
2643 //
2644 //
2645 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
2646 // CHECK3-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
2647 // CHECK3-NEXT:  entry:
2648 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2649 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2650 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2651 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2652 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
2653 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
2654 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
2655 // CHECK3-NEXT:    ret void
2656 //
2657 //
2658 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2
2659 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
2660 // CHECK3-NEXT:  entry:
2661 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2662 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2663 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2664 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2665 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2666 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2667 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2668 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2669 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
2670 // CHECK3-NEXT:    ret void
2671 //
2672 //
2673 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
2674 // CHECK3-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
2675 // CHECK3-NEXT:  entry:
2676 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2677 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2678 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2679 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2680 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
2681 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2682 // CHECK3-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
2683 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2684 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
2685 // CHECK3-NEXT:    ret void
2686 //
2687 //
2688 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3
2689 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
2690 // CHECK3-NEXT:  entry:
2691 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2692 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2693 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2694 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2695 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2696 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2697 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2698 // CHECK3-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
2699 // CHECK3-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
2700 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
2701 // CHECK3-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
2702 // CHECK3-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 4
2703 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
2704 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
2705 // CHECK3-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
2706 // CHECK3-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
2707 // CHECK3-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
2708 // CHECK3:       .cancel.exit:
2709 // CHECK3-NEXT:    br label [[DOTCANCEL_CONTINUE]]
2710 // CHECK3:       .cancel.continue:
2711 // CHECK3-NEXT:    ret void
2712 //
2713 //
2714 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
2715 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
2716 // CHECK3-NEXT:  entry:
2717 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2718 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2719 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2720 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
2721 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2722 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2723 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2724 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2725 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
2726 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
2727 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
2728 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
2729 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
2730 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
2731 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
2732 // CHECK3-NEXT:    ret void
2733 //
2734 //
2735 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4
2736 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
2737 // CHECK3-NEXT:  entry:
2738 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2739 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2740 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2741 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
2742 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2743 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2744 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2745 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
2746 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
2747 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2748 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2749 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
2750 // CHECK3-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
2751 // CHECK3-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
2752 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
2753 // CHECK3-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
2754 // CHECK3-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
2755 // CHECK3-NEXT:    ret void
2756 //
2757 //
2758 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
2759 // CHECK3-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
2760 // CHECK3-NEXT:  entry:
2761 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2762 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
2763 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2764 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
2765 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
2766 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2767 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
2768 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
2769 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
2770 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
2771 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2772 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
2773 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
2774 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
2775 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
2776 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
2777 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
2778 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
2779 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
2780 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
2781 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
2782 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
2783 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
2784 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
2785 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
2786 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
2787 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
2788 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
2789 // CHECK3-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
2790 // CHECK3-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
2791 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
2792 // CHECK3-NEXT:    ret void
2793 //
2794 //
2795 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7
2796 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
2797 // CHECK3-NEXT:  entry:
2798 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
2799 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
2800 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2801 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
2802 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
2803 // CHECK3-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
2804 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
2805 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
2806 // CHECK3-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
2807 // CHECK3-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
2808 // CHECK3-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
2809 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
2810 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
2811 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2812 // CHECK3-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
2813 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
2814 // CHECK3-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
2815 // CHECK3-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
2816 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
2817 // CHECK3-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
2818 // CHECK3-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
2819 // CHECK3-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
2820 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
2821 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
2822 // CHECK3-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
2823 // CHECK3-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
2824 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
2825 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
2826 // CHECK3-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
2827 // CHECK3-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
2828 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
2829 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
2830 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
2831 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
2832 // CHECK3-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
2833 // CHECK3-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
2834 // CHECK3-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
2835 // CHECK3-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
2836 // CHECK3-NEXT:    store float [[CONV6]], float* [[ARRAYIDX]], align 4
2837 // CHECK3-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
2838 // CHECK3-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
2839 // CHECK3-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
2840 // CHECK3-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
2841 // CHECK3-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
2842 // CHECK3-NEXT:    store float [[CONV10]], float* [[ARRAYIDX7]], align 4
2843 // CHECK3-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
2844 // CHECK3-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
2845 // CHECK3-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
2846 // CHECK3-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
2847 // CHECK3-NEXT:    store double [[ADD13]], double* [[ARRAYIDX12]], align 8
2848 // CHECK3-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
2849 // CHECK3-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
2850 // CHECK3-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
2851 // CHECK3-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
2852 // CHECK3-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
2853 // CHECK3-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
2854 // CHECK3-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
2855 // CHECK3-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
2856 // CHECK3-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
2857 // CHECK3-NEXT:    store i64 [[ADD17]], i64* [[X]], align 4
2858 // CHECK3-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
2859 // CHECK3-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
2860 // CHECK3-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
2861 // CHECK3-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
2862 // CHECK3-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
2863 // CHECK3-NEXT:    store i8 [[CONV20]], i8* [[Y]], align 4
2864 // CHECK3-NEXT:    ret void
2865 //
2866 //
2867 // CHECK3-LABEL: define {{[^@]+}}@_Z3bari
2868 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
2869 // CHECK3-NEXT:  entry:
2870 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2871 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
2872 // CHECK3-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
2873 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2874 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
2875 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2876 // CHECK3-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
2877 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
2878 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
2879 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
2880 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
2881 // CHECK3-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
2882 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
2883 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
2884 // CHECK3-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
2885 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
2886 // CHECK3-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
2887 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
2888 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
2889 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
2890 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
2891 // CHECK3-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
2892 // CHECK3-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
2893 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
2894 // CHECK3-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
2895 // CHECK3-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
2896 // CHECK3-NEXT:    ret i32 [[TMP8]]
2897 //
2898 //
2899 // CHECK3-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
2900 // CHECK3-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
2901 // CHECK3-NEXT:  entry:
2902 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
2903 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
2904 // CHECK3-NEXT:    [[B:%.*]] = alloca i32, align 4
2905 // CHECK3-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
2906 // CHECK3-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
2907 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
2908 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
2909 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
2910 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
2911 // CHECK3-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
2912 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
2913 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
2914 // CHECK3-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
2915 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
2916 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
2917 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
2918 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
2919 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
2920 // CHECK3-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
2921 // CHECK3-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
2922 // CHECK3-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
2923 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
2924 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
2925 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
2926 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
2927 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
2928 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
2929 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
2930 // CHECK3:       omp_if.then:
2931 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
2932 // CHECK3-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
2933 // CHECK3-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
2934 // CHECK3-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
2935 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2936 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
2937 // CHECK3-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
2938 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2939 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
2940 // CHECK3-NEXT:    store double* [[A]], double** [[TMP13]], align 4
2941 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2942 // CHECK3-NEXT:    store i64 8, i64* [[TMP14]], align 4
2943 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
2944 // CHECK3-NEXT:    store i8* null, i8** [[TMP15]], align 4
2945 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
2946 // CHECK3-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
2947 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
2948 // CHECK3-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
2949 // CHECK3-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
2950 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
2951 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
2952 // CHECK3-NEXT:    store i64 4, i64* [[TMP20]], align 4
2953 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
2954 // CHECK3-NEXT:    store i8* null, i8** [[TMP21]], align 4
2955 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
2956 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
2957 // CHECK3-NEXT:    store i32 2, i32* [[TMP23]], align 4
2958 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
2959 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
2960 // CHECK3-NEXT:    store i32 2, i32* [[TMP25]], align 4
2961 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
2962 // CHECK3-NEXT:    store i64 4, i64* [[TMP26]], align 4
2963 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
2964 // CHECK3-NEXT:    store i8* null, i8** [[TMP27]], align 4
2965 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
2966 // CHECK3-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
2967 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
2968 // CHECK3-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
2969 // CHECK3-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
2970 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
2971 // CHECK3-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
2972 // CHECK3-NEXT:    store i64 4, i64* [[TMP32]], align 4
2973 // CHECK3-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
2974 // CHECK3-NEXT:    store i8* null, i8** [[TMP33]], align 4
2975 // CHECK3-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
2976 // CHECK3-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
2977 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
2978 // CHECK3-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
2979 // CHECK3-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
2980 // CHECK3-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
2981 // CHECK3-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
2982 // CHECK3-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
2983 // CHECK3-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
2984 // CHECK3-NEXT:    store i8* null, i8** [[TMP39]], align 4
2985 // CHECK3-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
2986 // CHECK3-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
2987 // CHECK3-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
2988 // CHECK3-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
2989 // CHECK3-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
2990 // CHECK3-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
2991 // CHECK3:       omp_offload.failed:
2992 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
2993 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
2994 // CHECK3:       omp_offload.cont:
2995 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
2996 // CHECK3:       omp_if.else:
2997 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
2998 // CHECK3-NEXT:    br label [[OMP_IF_END]]
2999 // CHECK3:       omp_if.end:
3000 // CHECK3-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
3001 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
3002 // CHECK3-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
3003 // CHECK3-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
3004 // CHECK3-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
3005 // CHECK3-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
3006 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
3007 // CHECK3-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
3008 // CHECK3-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
3009 // CHECK3-NEXT:    ret i32 [[ADD3]]
3010 //
3011 //
3012 // CHECK3-LABEL: define {{[^@]+}}@_ZL7fstatici
3013 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
3014 // CHECK3-NEXT:  entry:
3015 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3016 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3017 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3018 // CHECK3-NEXT:    [[AAA:%.*]] = alloca i8, align 1
3019 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3020 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3021 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3022 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3023 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
3024 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
3025 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
3026 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3027 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
3028 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
3029 // CHECK3-NEXT:    store i8 0, i8* [[AAA]], align 1
3030 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3031 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3032 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3033 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3034 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3035 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
3036 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3037 // CHECK3-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
3038 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
3039 // CHECK3-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
3040 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
3041 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3042 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
3043 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3044 // CHECK3:       omp_if.then:
3045 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3046 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
3047 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
3048 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3049 // CHECK3-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
3050 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
3051 // CHECK3-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3052 // CHECK3-NEXT:    store i8* null, i8** [[TMP11]], align 4
3053 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3054 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
3055 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
3056 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3057 // CHECK3-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
3058 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
3059 // CHECK3-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3060 // CHECK3-NEXT:    store i8* null, i8** [[TMP16]], align 4
3061 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3062 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
3063 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
3064 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3065 // CHECK3-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
3066 // CHECK3-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
3067 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3068 // CHECK3-NEXT:    store i8* null, i8** [[TMP21]], align 4
3069 // CHECK3-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3070 // CHECK3-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
3071 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
3072 // CHECK3-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3073 // CHECK3-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
3074 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
3075 // CHECK3-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3076 // CHECK3-NEXT:    store i8* null, i8** [[TMP26]], align 4
3077 // CHECK3-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3078 // CHECK3-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3079 // CHECK3-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3080 // CHECK3-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
3081 // CHECK3-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3082 // CHECK3:       omp_offload.failed:
3083 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
3084 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3085 // CHECK3:       omp_offload.cont:
3086 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3087 // CHECK3:       omp_if.else:
3088 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
3089 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3090 // CHECK3:       omp_if.end:
3091 // CHECK3-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
3092 // CHECK3-NEXT:    ret i32 [[TMP31]]
3093 //
3094 //
3095 // CHECK3-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
3096 // CHECK3-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
3097 // CHECK3-NEXT:  entry:
3098 // CHECK3-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3099 // CHECK3-NEXT:    [[A:%.*]] = alloca i32, align 4
3100 // CHECK3-NEXT:    [[AA:%.*]] = alloca i16, align 2
3101 // CHECK3-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
3102 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3103 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3104 // CHECK3-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
3105 // CHECK3-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
3106 // CHECK3-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
3107 // CHECK3-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3108 // CHECK3-NEXT:    store i32 0, i32* [[A]], align 4
3109 // CHECK3-NEXT:    store i16 0, i16* [[AA]], align 2
3110 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
3111 // CHECK3-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3112 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3113 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
3114 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3115 // CHECK3-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
3116 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3117 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3118 // CHECK3-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
3119 // CHECK3-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3120 // CHECK3:       omp_if.then:
3121 // CHECK3-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3122 // CHECK3-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
3123 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
3124 // CHECK3-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3125 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
3126 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
3127 // CHECK3-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3128 // CHECK3-NEXT:    store i8* null, i8** [[TMP9]], align 4
3129 // CHECK3-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3130 // CHECK3-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
3131 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
3132 // CHECK3-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3133 // CHECK3-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
3134 // CHECK3-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
3135 // CHECK3-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3136 // CHECK3-NEXT:    store i8* null, i8** [[TMP14]], align 4
3137 // CHECK3-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3138 // CHECK3-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
3139 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
3140 // CHECK3-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3141 // CHECK3-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
3142 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
3143 // CHECK3-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3144 // CHECK3-NEXT:    store i8* null, i8** [[TMP19]], align 4
3145 // CHECK3-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3146 // CHECK3-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3147 // CHECK3-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3148 // CHECK3-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
3149 // CHECK3-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3150 // CHECK3:       omp_offload.failed:
3151 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
3152 // CHECK3-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3153 // CHECK3:       omp_offload.cont:
3154 // CHECK3-NEXT:    br label [[OMP_IF_END:%.*]]
3155 // CHECK3:       omp_if.else:
3156 // CHECK3-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
3157 // CHECK3-NEXT:    br label [[OMP_IF_END]]
3158 // CHECK3:       omp_if.end:
3159 // CHECK3-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
3160 // CHECK3-NEXT:    ret i32 [[TMP24]]
3161 //
3162 //
3163 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
3164 // CHECK3-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3165 // CHECK3-NEXT:  entry:
3166 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3167 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3168 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3169 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3170 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
3171 // CHECK3-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3172 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3173 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3174 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3175 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3176 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
3177 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3178 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3179 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3180 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
3181 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
3182 // CHECK3-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
3183 // CHECK3-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
3184 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
3185 // CHECK3-NEXT:    ret void
3186 //
3187 //
3188 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..9
3189 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
3190 // CHECK3-NEXT:  entry:
3191 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3192 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3193 // CHECK3-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3194 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
3195 // CHECK3-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3196 // CHECK3-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3197 // CHECK3-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
3198 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3199 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3200 // CHECK3-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3201 // CHECK3-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
3202 // CHECK3-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3203 // CHECK3-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3204 // CHECK3-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
3205 // CHECK3-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3206 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3207 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3208 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
3209 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
3210 // CHECK3-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
3211 // CHECK3-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
3212 // CHECK3-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
3213 // CHECK3-NEXT:    store double [[ADD]], double* [[A]], align 4
3214 // CHECK3-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
3215 // CHECK3-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
3216 // CHECK3-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
3217 // CHECK3-NEXT:    store double [[INC]], double* [[A3]], align 4
3218 // CHECK3-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
3219 // CHECK3-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
3220 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
3221 // CHECK3-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
3222 // CHECK3-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
3223 // CHECK3-NEXT:    ret void
3224 //
3225 //
3226 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
3227 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3228 // CHECK3-NEXT:  entry:
3229 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3230 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3231 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3232 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3233 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3234 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3235 // CHECK3-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
3236 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3237 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3238 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
3239 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3240 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3241 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
3242 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3243 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3244 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
3245 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
3246 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
3247 // CHECK3-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3248 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
3249 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3250 // CHECK3-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
3251 // CHECK3-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
3252 // CHECK3-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
3253 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
3254 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
3255 // CHECK3-NEXT:    ret void
3256 //
3257 //
3258 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..11
3259 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3260 // CHECK3-NEXT:  entry:
3261 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3262 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3263 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3264 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3265 // CHECK3-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
3266 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3267 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3268 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3269 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3270 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3271 // CHECK3-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
3272 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3273 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3274 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
3275 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3276 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3277 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3278 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
3279 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
3280 // CHECK3-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
3281 // CHECK3-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
3282 // CHECK3-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
3283 // CHECK3-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
3284 // CHECK3-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
3285 // CHECK3-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
3286 // CHECK3-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
3287 // CHECK3-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
3288 // CHECK3-NEXT:    store i8 [[CONV7]], i8* [[CONV1]], align 4
3289 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
3290 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
3291 // CHECK3-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
3292 // CHECK3-NEXT:    store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
3293 // CHECK3-NEXT:    ret void
3294 //
3295 //
3296 // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
3297 // CHECK3-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3298 // CHECK3-NEXT:  entry:
3299 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3300 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3301 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3302 // CHECK3-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3303 // CHECK3-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3304 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3305 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3306 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3307 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3308 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3309 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3310 // CHECK3-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
3311 // CHECK3-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
3312 // CHECK3-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
3313 // CHECK3-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3314 // CHECK3-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
3315 // CHECK3-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3316 // CHECK3-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
3317 // CHECK3-NEXT:    ret void
3318 //
3319 //
3320 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..14
3321 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
3322 // CHECK3-NEXT:  entry:
3323 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3324 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3325 // CHECK3-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3326 // CHECK3-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3327 // CHECK3-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
3328 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3329 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3330 // CHECK3-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3331 // CHECK3-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3332 // CHECK3-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
3333 // CHECK3-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3334 // CHECK3-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
3335 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
3336 // CHECK3-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
3337 // CHECK3-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
3338 // CHECK3-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
3339 // CHECK3-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
3340 // CHECK3-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
3341 // CHECK3-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
3342 // CHECK3-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
3343 // CHECK3-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
3344 // CHECK3-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
3345 // CHECK3-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
3346 // CHECK3-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
3347 // CHECK3-NEXT:    ret void
3348 //
3349 //
3350 // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
3351 // CHECK3-SAME: () #[[ATTR5:[0-9]+]] {
3352 // CHECK3-NEXT:  entry:
3353 // CHECK3-NEXT:    call void @__tgt_register_requires(i64 1)
3354 // CHECK3-NEXT:    ret void
3355 //
3356 //
3357 // CHECK4-LABEL: define {{[^@]+}}@_Z3fooi
3358 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
3359 // CHECK4-NEXT:  entry:
3360 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3361 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
3362 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
3363 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
3364 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
3365 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3366 // CHECK4-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
3367 // CHECK4-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
3368 // CHECK4-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
3369 // CHECK4-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
3370 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3371 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3372 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
3373 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
3374 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
3375 // CHECK4-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
3376 // CHECK4-NEXT:    [[AA_CASTED3:%.*]] = alloca i32, align 4
3377 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4
3378 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4
3379 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4
3380 // CHECK4-NEXT:    [[A_CASTED10:%.*]] = alloca i32, align 4
3381 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4
3382 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4
3383 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4
3384 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
3385 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
3386 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3387 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
3388 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
3389 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3390 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
3391 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3392 // CHECK4-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
3393 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3394 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
3395 // CHECK4-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
3396 // CHECK4-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
3397 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
3398 // CHECK4-NEXT:    [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
3399 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
3400 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
3401 // CHECK4-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]])
3402 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
3403 // CHECK4-NEXT:    store i32 [[TMP9]], i32* [[A_CASTED]], align 4
3404 // CHECK4-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
3405 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR3:[0-9]+]]
3406 // CHECK4-NEXT:    [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
3407 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3408 // CHECK4-NEXT:    store i16 [[TMP11]], i16* [[CONV]], align 2
3409 // CHECK4-NEXT:    [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3410 // CHECK4-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3411 // CHECK4-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
3412 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP14]], align 4
3413 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3414 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
3415 // CHECK4-NEXT:    store i32 [[TMP12]], i32* [[TMP16]], align 4
3416 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3417 // CHECK4-NEXT:    store i8* null, i8** [[TMP17]], align 4
3418 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3419 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3420 // CHECK4-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3421 // CHECK4-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
3422 // CHECK4-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3423 // CHECK4:       omp_offload.failed:
3424 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR3]]
3425 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3426 // CHECK4:       omp_offload.cont:
3427 // CHECK4-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
3428 // CHECK4-NEXT:    store i32 [[TMP22]], i32* [[A_CASTED2]], align 4
3429 // CHECK4-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4
3430 // CHECK4-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2
3431 // CHECK4-NEXT:    [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16*
3432 // CHECK4-NEXT:    store i16 [[TMP24]], i16* [[CONV4]], align 2
3433 // CHECK4-NEXT:    [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4
3434 // CHECK4-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
3435 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10
3436 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3437 // CHECK4:       omp_if.then:
3438 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
3439 // CHECK4-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
3440 // CHECK4-NEXT:    store i32 [[TMP23]], i32* [[TMP28]], align 4
3441 // CHECK4-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
3442 // CHECK4-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
3443 // CHECK4-NEXT:    store i32 [[TMP23]], i32* [[TMP30]], align 4
3444 // CHECK4-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
3445 // CHECK4-NEXT:    store i8* null, i8** [[TMP31]], align 4
3446 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
3447 // CHECK4-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32*
3448 // CHECK4-NEXT:    store i32 [[TMP25]], i32* [[TMP33]], align 4
3449 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
3450 // CHECK4-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32*
3451 // CHECK4-NEXT:    store i32 [[TMP25]], i32* [[TMP35]], align 4
3452 // CHECK4-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1
3453 // CHECK4-NEXT:    store i8* null, i8** [[TMP36]], align 4
3454 // CHECK4-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
3455 // CHECK4-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
3456 // CHECK4-NEXT:    [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3457 // CHECK4-NEXT:    [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
3458 // CHECK4-NEXT:    br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
3459 // CHECK4:       omp_offload.failed8:
3460 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]]
3461 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT9]]
3462 // CHECK4:       omp_offload.cont9:
3463 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
3464 // CHECK4:       omp_if.else:
3465 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]]
3466 // CHECK4-NEXT:    br label [[OMP_IF_END]]
3467 // CHECK4:       omp_if.end:
3468 // CHECK4-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4
3469 // CHECK4-NEXT:    store i32 [[TMP41]], i32* [[A_CASTED10]], align 4
3470 // CHECK4-NEXT:    [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4
3471 // CHECK4-NEXT:    [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4
3472 // CHECK4-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20
3473 // CHECK4-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]]
3474 // CHECK4:       omp_if.then12:
3475 // CHECK4-NEXT:    [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4
3476 // CHECK4-NEXT:    [[TMP45:%.*]] = sext i32 [[TMP44]] to i64
3477 // CHECK4-NEXT:    [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]]
3478 // CHECK4-NEXT:    [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8
3479 // CHECK4-NEXT:    [[TMP48:%.*]] = sext i32 [[TMP47]] to i64
3480 // CHECK4-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
3481 // CHECK4-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
3482 // CHECK4-NEXT:    store i32 [[TMP42]], i32* [[TMP50]], align 4
3483 // CHECK4-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
3484 // CHECK4-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
3485 // CHECK4-NEXT:    store i32 [[TMP42]], i32* [[TMP52]], align 4
3486 // CHECK4-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3487 // CHECK4-NEXT:    store i64 4, i64* [[TMP53]], align 4
3488 // CHECK4-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
3489 // CHECK4-NEXT:    store i8* null, i8** [[TMP54]], align 4
3490 // CHECK4-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
3491 // CHECK4-NEXT:    [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]**
3492 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4
3493 // CHECK4-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
3494 // CHECK4-NEXT:    [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]**
3495 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4
3496 // CHECK4-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
3497 // CHECK4-NEXT:    store i64 40, i64* [[TMP59]], align 4
3498 // CHECK4-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1
3499 // CHECK4-NEXT:    store i8* null, i8** [[TMP60]], align 4
3500 // CHECK4-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2
3501 // CHECK4-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
3502 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP62]], align 4
3503 // CHECK4-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2
3504 // CHECK4-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*
3505 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP64]], align 4
3506 // CHECK4-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
3507 // CHECK4-NEXT:    store i64 4, i64* [[TMP65]], align 4
3508 // CHECK4-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2
3509 // CHECK4-NEXT:    store i8* null, i8** [[TMP66]], align 4
3510 // CHECK4-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3
3511 // CHECK4-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float**
3512 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP68]], align 4
3513 // CHECK4-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3
3514 // CHECK4-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float**
3515 // CHECK4-NEXT:    store float* [[VLA]], float** [[TMP70]], align 4
3516 // CHECK4-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3517 // CHECK4-NEXT:    store i64 [[TMP45]], i64* [[TMP71]], align 4
3518 // CHECK4-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3
3519 // CHECK4-NEXT:    store i8* null, i8** [[TMP72]], align 4
3520 // CHECK4-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4
3521 // CHECK4-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]**
3522 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4
3523 // CHECK4-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4
3524 // CHECK4-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]**
3525 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4
3526 // CHECK4-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3527 // CHECK4-NEXT:    store i64 400, i64* [[TMP77]], align 4
3528 // CHECK4-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4
3529 // CHECK4-NEXT:    store i8* null, i8** [[TMP78]], align 4
3530 // CHECK4-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5
3531 // CHECK4-NEXT:    [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*
3532 // CHECK4-NEXT:    store i32 5, i32* [[TMP80]], align 4
3533 // CHECK4-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5
3534 // CHECK4-NEXT:    [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32*
3535 // CHECK4-NEXT:    store i32 5, i32* [[TMP82]], align 4
3536 // CHECK4-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
3537 // CHECK4-NEXT:    store i64 4, i64* [[TMP83]], align 4
3538 // CHECK4-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5
3539 // CHECK4-NEXT:    store i8* null, i8** [[TMP84]], align 4
3540 // CHECK4-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6
3541 // CHECK4-NEXT:    [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32*
3542 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP86]], align 4
3543 // CHECK4-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6
3544 // CHECK4-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
3545 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP88]], align 4
3546 // CHECK4-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
3547 // CHECK4-NEXT:    store i64 4, i64* [[TMP89]], align 4
3548 // CHECK4-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6
3549 // CHECK4-NEXT:    store i8* null, i8** [[TMP90]], align 4
3550 // CHECK4-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7
3551 // CHECK4-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double**
3552 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP92]], align 4
3553 // CHECK4-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7
3554 // CHECK4-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double**
3555 // CHECK4-NEXT:    store double* [[VLA1]], double** [[TMP94]], align 4
3556 // CHECK4-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
3557 // CHECK4-NEXT:    store i64 [[TMP48]], i64* [[TMP95]], align 4
3558 // CHECK4-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7
3559 // CHECK4-NEXT:    store i8* null, i8** [[TMP96]], align 4
3560 // CHECK4-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8
3561 // CHECK4-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT**
3562 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4
3563 // CHECK4-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8
3564 // CHECK4-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT**
3565 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4
3566 // CHECK4-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
3567 // CHECK4-NEXT:    store i64 12, i64* [[TMP101]], align 4
3568 // CHECK4-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8
3569 // CHECK4-NEXT:    store i8* null, i8** [[TMP102]], align 4
3570 // CHECK4-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
3571 // CHECK4-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
3572 // CHECK4-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3573 // CHECK4-NEXT:    [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3574 // CHECK4-NEXT:    [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0
3575 // CHECK4-NEXT:    br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
3576 // CHECK4:       omp_offload.failed16:
3577 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
3578 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
3579 // CHECK4:       omp_offload.cont17:
3580 // CHECK4-NEXT:    br label [[OMP_IF_END19:%.*]]
3581 // CHECK4:       omp_if.else18:
3582 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
3583 // CHECK4-NEXT:    br label [[OMP_IF_END19]]
3584 // CHECK4:       omp_if.end19:
3585 // CHECK4-NEXT:    [[TMP108:%.*]] = load i32, i32* [[A]], align 4
3586 // CHECK4-NEXT:    [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
3587 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP109]])
3588 // CHECK4-NEXT:    ret i32 [[TMP108]]
3589 //
3590 //
3591 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
3592 // CHECK4-SAME: () #[[ATTR2:[0-9]+]] {
3593 // CHECK4-NEXT:  entry:
3594 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3595 // CHECK4-NEXT:    ret void
3596 //
3597 //
3598 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
3599 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
3600 // CHECK4-NEXT:  entry:
3601 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3602 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3603 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3604 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3605 // CHECK4-NEXT:    ret void
3606 //
3607 //
3608 // CHECK4-LABEL: define {{[^@]+}}@.omp_task_entry.
3609 // CHECK4-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
3610 // CHECK4-NEXT:  entry:
3611 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
3612 // CHECK4-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
3613 // CHECK4-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
3614 // CHECK4-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
3615 // CHECK4-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
3616 // CHECK4-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
3617 // CHECK4-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
3618 // CHECK4-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
3619 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
3620 // CHECK4-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
3621 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
3622 // CHECK4-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
3623 // CHECK4-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
3624 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
3625 // CHECK4-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
3626 // CHECK4-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
3627 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
3628 // CHECK4-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
3629 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
3630 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
3631 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
3632 // CHECK4-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
3633 // CHECK4-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
3634 // CHECK4-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21
3635 // CHECK4-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
3636 // CHECK4-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
3637 // CHECK4-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21
3638 // CHECK4-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
3639 // CHECK4-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
3640 // CHECK4-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
3641 // CHECK4-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
3642 // CHECK4-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
3643 // CHECK4:       omp_offload.failed.i:
3644 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
3645 // CHECK4-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
3646 // CHECK4:       .omp_outlined..1.exit:
3647 // CHECK4-NEXT:    ret i32 0
3648 //
3649 //
3650 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
3651 // CHECK4-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
3652 // CHECK4-NEXT:  entry:
3653 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3654 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3655 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3656 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3657 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3658 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3659 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
3660 // CHECK4-NEXT:    ret void
3661 //
3662 //
3663 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2
3664 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
3665 // CHECK4-NEXT:  entry:
3666 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3667 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3668 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3669 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3670 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3671 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3672 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3673 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3674 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
3675 // CHECK4-NEXT:    ret void
3676 //
3677 //
3678 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
3679 // CHECK4-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
3680 // CHECK4-NEXT:  entry:
3681 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3682 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3683 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3684 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3685 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
3686 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3687 // CHECK4-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
3688 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3689 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
3690 // CHECK4-NEXT:    ret void
3691 //
3692 //
3693 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3
3694 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
3695 // CHECK4-NEXT:  entry:
3696 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3697 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3698 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3699 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3700 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3701 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3702 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3703 // CHECK4-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
3704 // CHECK4-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
3705 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
3706 // CHECK4-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
3707 // CHECK4-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 4
3708 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
3709 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
3710 // CHECK4-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
3711 // CHECK4-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
3712 // CHECK4-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
3713 // CHECK4:       .cancel.exit:
3714 // CHECK4-NEXT:    br label [[DOTCANCEL_CONTINUE]]
3715 // CHECK4:       .cancel.continue:
3716 // CHECK4-NEXT:    ret void
3717 //
3718 //
3719 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
3720 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
3721 // CHECK4-NEXT:  entry:
3722 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3723 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3724 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3725 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
3726 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3727 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3728 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3729 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3730 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
3731 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
3732 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
3733 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
3734 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
3735 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
3736 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
3737 // CHECK4-NEXT:    ret void
3738 //
3739 //
3740 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4
3741 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
3742 // CHECK4-NEXT:  entry:
3743 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3744 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3745 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3746 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
3747 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3748 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3749 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3750 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
3751 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
3752 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3753 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3754 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
3755 // CHECK4-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
3756 // CHECK4-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
3757 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
3758 // CHECK4-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
3759 // CHECK4-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
3760 // CHECK4-NEXT:    ret void
3761 //
3762 //
3763 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
3764 // CHECK4-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
3765 // CHECK4-NEXT:  entry:
3766 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3767 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
3768 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3769 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
3770 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
3771 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3772 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
3773 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
3774 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
3775 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
3776 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3777 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
3778 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3779 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
3780 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
3781 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3782 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
3783 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
3784 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
3785 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
3786 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3787 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
3788 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
3789 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3790 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
3791 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
3792 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
3793 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
3794 // CHECK4-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
3795 // CHECK4-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
3796 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
3797 // CHECK4-NEXT:    ret void
3798 //
3799 //
3800 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7
3801 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
3802 // CHECK4-NEXT:  entry:
3803 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
3804 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
3805 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3806 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
3807 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
3808 // CHECK4-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
3809 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
3810 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
3811 // CHECK4-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
3812 // CHECK4-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
3813 // CHECK4-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
3814 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
3815 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
3816 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3817 // CHECK4-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
3818 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
3819 // CHECK4-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
3820 // CHECK4-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
3821 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
3822 // CHECK4-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
3823 // CHECK4-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
3824 // CHECK4-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
3825 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
3826 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
3827 // CHECK4-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
3828 // CHECK4-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
3829 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
3830 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
3831 // CHECK4-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
3832 // CHECK4-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
3833 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
3834 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
3835 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
3836 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
3837 // CHECK4-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
3838 // CHECK4-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
3839 // CHECK4-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
3840 // CHECK4-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
3841 // CHECK4-NEXT:    store float [[CONV6]], float* [[ARRAYIDX]], align 4
3842 // CHECK4-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
3843 // CHECK4-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
3844 // CHECK4-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
3845 // CHECK4-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
3846 // CHECK4-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
3847 // CHECK4-NEXT:    store float [[CONV10]], float* [[ARRAYIDX7]], align 4
3848 // CHECK4-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
3849 // CHECK4-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
3850 // CHECK4-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
3851 // CHECK4-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
3852 // CHECK4-NEXT:    store double [[ADD13]], double* [[ARRAYIDX12]], align 8
3853 // CHECK4-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
3854 // CHECK4-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
3855 // CHECK4-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
3856 // CHECK4-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
3857 // CHECK4-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
3858 // CHECK4-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
3859 // CHECK4-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
3860 // CHECK4-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
3861 // CHECK4-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
3862 // CHECK4-NEXT:    store i64 [[ADD17]], i64* [[X]], align 4
3863 // CHECK4-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
3864 // CHECK4-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
3865 // CHECK4-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
3866 // CHECK4-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
3867 // CHECK4-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
3868 // CHECK4-NEXT:    store i8 [[CONV20]], i8* [[Y]], align 4
3869 // CHECK4-NEXT:    ret void
3870 //
3871 //
3872 // CHECK4-LABEL: define {{[^@]+}}@_Z3bari
3873 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
3874 // CHECK4-NEXT:  entry:
3875 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3876 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
3877 // CHECK4-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
3878 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3879 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
3880 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3881 // CHECK4-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
3882 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
3883 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
3884 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
3885 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
3886 // CHECK4-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
3887 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
3888 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
3889 // CHECK4-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
3890 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
3891 // CHECK4-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
3892 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
3893 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
3894 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
3895 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3896 // CHECK4-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
3897 // CHECK4-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
3898 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
3899 // CHECK4-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
3900 // CHECK4-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
3901 // CHECK4-NEXT:    ret i32 [[TMP8]]
3902 //
3903 //
3904 // CHECK4-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
3905 // CHECK4-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
3906 // CHECK4-NEXT:  entry:
3907 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
3908 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
3909 // CHECK4-NEXT:    [[B:%.*]] = alloca i32, align 4
3910 // CHECK4-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
3911 // CHECK4-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
3912 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
3913 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
3914 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
3915 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
3916 // CHECK4-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
3917 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
3918 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
3919 // CHECK4-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
3920 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
3921 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
3922 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
3923 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
3924 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
3925 // CHECK4-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
3926 // CHECK4-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
3927 // CHECK4-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
3928 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
3929 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
3930 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
3931 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
3932 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
3933 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
3934 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
3935 // CHECK4:       omp_if.then:
3936 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
3937 // CHECK4-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
3938 // CHECK4-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
3939 // CHECK4-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
3940 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3941 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
3942 // CHECK4-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
3943 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3944 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
3945 // CHECK4-NEXT:    store double* [[A]], double** [[TMP13]], align 4
3946 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3947 // CHECK4-NEXT:    store i64 8, i64* [[TMP14]], align 4
3948 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
3949 // CHECK4-NEXT:    store i8* null, i8** [[TMP15]], align 4
3950 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
3951 // CHECK4-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
3952 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
3953 // CHECK4-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
3954 // CHECK4-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
3955 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
3956 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
3957 // CHECK4-NEXT:    store i64 4, i64* [[TMP20]], align 4
3958 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
3959 // CHECK4-NEXT:    store i8* null, i8** [[TMP21]], align 4
3960 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
3961 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
3962 // CHECK4-NEXT:    store i32 2, i32* [[TMP23]], align 4
3963 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
3964 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
3965 // CHECK4-NEXT:    store i32 2, i32* [[TMP25]], align 4
3966 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
3967 // CHECK4-NEXT:    store i64 4, i64* [[TMP26]], align 4
3968 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
3969 // CHECK4-NEXT:    store i8* null, i8** [[TMP27]], align 4
3970 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
3971 // CHECK4-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
3972 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
3973 // CHECK4-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
3974 // CHECK4-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
3975 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
3976 // CHECK4-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
3977 // CHECK4-NEXT:    store i64 4, i64* [[TMP32]], align 4
3978 // CHECK4-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
3979 // CHECK4-NEXT:    store i8* null, i8** [[TMP33]], align 4
3980 // CHECK4-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
3981 // CHECK4-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
3982 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
3983 // CHECK4-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
3984 // CHECK4-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
3985 // CHECK4-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
3986 // CHECK4-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
3987 // CHECK4-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
3988 // CHECK4-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
3989 // CHECK4-NEXT:    store i8* null, i8** [[TMP39]], align 4
3990 // CHECK4-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
3991 // CHECK4-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
3992 // CHECK4-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
3993 // CHECK4-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
3994 // CHECK4-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
3995 // CHECK4-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
3996 // CHECK4:       omp_offload.failed:
3997 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
3998 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
3999 // CHECK4:       omp_offload.cont:
4000 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
4001 // CHECK4:       omp_if.else:
4002 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
4003 // CHECK4-NEXT:    br label [[OMP_IF_END]]
4004 // CHECK4:       omp_if.end:
4005 // CHECK4-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
4006 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
4007 // CHECK4-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4008 // CHECK4-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
4009 // CHECK4-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
4010 // CHECK4-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
4011 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
4012 // CHECK4-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4013 // CHECK4-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
4014 // CHECK4-NEXT:    ret i32 [[ADD3]]
4015 //
4016 //
4017 // CHECK4-LABEL: define {{[^@]+}}@_ZL7fstatici
4018 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4019 // CHECK4-NEXT:  entry:
4020 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4021 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
4022 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
4023 // CHECK4-NEXT:    [[AAA:%.*]] = alloca i8, align 1
4024 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4025 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4026 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4027 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
4028 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
4029 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
4030 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
4031 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4032 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
4033 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
4034 // CHECK4-NEXT:    store i8 0, i8* [[AAA]], align 1
4035 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4036 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4037 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4038 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4039 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4040 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
4041 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4042 // CHECK4-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
4043 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
4044 // CHECK4-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
4045 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
4046 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4047 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
4048 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4049 // CHECK4:       omp_if.then:
4050 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4051 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4052 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
4053 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4054 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
4055 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
4056 // CHECK4-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4057 // CHECK4-NEXT:    store i8* null, i8** [[TMP11]], align 4
4058 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4059 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4060 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
4061 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4062 // CHECK4-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
4063 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
4064 // CHECK4-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4065 // CHECK4-NEXT:    store i8* null, i8** [[TMP16]], align 4
4066 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4067 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
4068 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
4069 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4070 // CHECK4-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
4071 // CHECK4-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
4072 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4073 // CHECK4-NEXT:    store i8* null, i8** [[TMP21]], align 4
4074 // CHECK4-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
4075 // CHECK4-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
4076 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
4077 // CHECK4-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
4078 // CHECK4-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
4079 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
4080 // CHECK4-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
4081 // CHECK4-NEXT:    store i8* null, i8** [[TMP26]], align 4
4082 // CHECK4-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4083 // CHECK4-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4084 // CHECK4-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4085 // CHECK4-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
4086 // CHECK4-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4087 // CHECK4:       omp_offload.failed:
4088 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
4089 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4090 // CHECK4:       omp_offload.cont:
4091 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
4092 // CHECK4:       omp_if.else:
4093 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
4094 // CHECK4-NEXT:    br label [[OMP_IF_END]]
4095 // CHECK4:       omp_if.end:
4096 // CHECK4-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
4097 // CHECK4-NEXT:    ret i32 [[TMP31]]
4098 //
4099 //
4100 // CHECK4-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4101 // CHECK4-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
4102 // CHECK4-NEXT:  entry:
4103 // CHECK4-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4104 // CHECK4-NEXT:    [[A:%.*]] = alloca i32, align 4
4105 // CHECK4-NEXT:    [[AA:%.*]] = alloca i16, align 2
4106 // CHECK4-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4107 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4108 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4109 // CHECK4-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
4110 // CHECK4-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
4111 // CHECK4-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
4112 // CHECK4-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4113 // CHECK4-NEXT:    store i32 0, i32* [[A]], align 4
4114 // CHECK4-NEXT:    store i16 0, i16* [[AA]], align 2
4115 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4116 // CHECK4-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
4117 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
4118 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
4119 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4120 // CHECK4-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
4121 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4122 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4123 // CHECK4-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
4124 // CHECK4-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
4125 // CHECK4:       omp_if.then:
4126 // CHECK4-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4127 // CHECK4-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
4128 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
4129 // CHECK4-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4130 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
4131 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
4132 // CHECK4-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
4133 // CHECK4-NEXT:    store i8* null, i8** [[TMP9]], align 4
4134 // CHECK4-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
4135 // CHECK4-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
4136 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
4137 // CHECK4-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
4138 // CHECK4-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
4139 // CHECK4-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
4140 // CHECK4-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
4141 // CHECK4-NEXT:    store i8* null, i8** [[TMP14]], align 4
4142 // CHECK4-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
4143 // CHECK4-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
4144 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
4145 // CHECK4-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
4146 // CHECK4-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
4147 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
4148 // CHECK4-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
4149 // CHECK4-NEXT:    store i8* null, i8** [[TMP19]], align 4
4150 // CHECK4-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
4151 // CHECK4-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
4152 // CHECK4-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
4153 // CHECK4-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
4154 // CHECK4-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
4155 // CHECK4:       omp_offload.failed:
4156 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
4157 // CHECK4-NEXT:    br label [[OMP_OFFLOAD_CONT]]
4158 // CHECK4:       omp_offload.cont:
4159 // CHECK4-NEXT:    br label [[OMP_IF_END:%.*]]
4160 // CHECK4:       omp_if.else:
4161 // CHECK4-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
4162 // CHECK4-NEXT:    br label [[OMP_IF_END]]
4163 // CHECK4:       omp_if.end:
4164 // CHECK4-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
4165 // CHECK4-NEXT:    ret i32 [[TMP24]]
4166 //
4167 //
4168 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
4169 // CHECK4-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
4170 // CHECK4-NEXT:  entry:
4171 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4172 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
4173 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4174 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4175 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
4176 // CHECK4-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
4177 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4178 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
4179 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4180 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4181 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
4182 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4183 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4184 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4185 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
4186 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
4187 // CHECK4-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
4188 // CHECK4-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
4189 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
4190 // CHECK4-NEXT:    ret void
4191 //
4192 //
4193 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..9
4194 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
4195 // CHECK4-NEXT:  entry:
4196 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4197 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4198 // CHECK4-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4199 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
4200 // CHECK4-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
4201 // CHECK4-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
4202 // CHECK4-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
4203 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4204 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4205 // CHECK4-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4206 // CHECK4-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
4207 // CHECK4-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
4208 // CHECK4-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
4209 // CHECK4-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
4210 // CHECK4-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4211 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
4212 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
4213 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
4214 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
4215 // CHECK4-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
4216 // CHECK4-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
4217 // CHECK4-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
4218 // CHECK4-NEXT:    store double [[ADD]], double* [[A]], align 4
4219 // CHECK4-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
4220 // CHECK4-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
4221 // CHECK4-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
4222 // CHECK4-NEXT:    store double [[INC]], double* [[A3]], align 4
4223 // CHECK4-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
4224 // CHECK4-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
4225 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
4226 // CHECK4-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4227 // CHECK4-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
4228 // CHECK4-NEXT:    ret void
4229 //
4230 //
4231 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
4232 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4233 // CHECK4-NEXT:  entry:
4234 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4235 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4236 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
4237 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4238 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4239 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4240 // CHECK4-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
4241 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4242 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4243 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
4244 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4245 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4246 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
4247 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4248 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4249 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
4250 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
4251 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
4252 // CHECK4-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4253 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
4254 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4255 // CHECK4-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
4256 // CHECK4-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
4257 // CHECK4-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
4258 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
4259 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
4260 // CHECK4-NEXT:    ret void
4261 //
4262 //
4263 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..11
4264 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4265 // CHECK4-NEXT:  entry:
4266 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4267 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4268 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4269 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4270 // CHECK4-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
4271 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4272 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4273 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4274 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4275 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4276 // CHECK4-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
4277 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4278 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4279 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
4280 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4281 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4282 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
4283 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
4284 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
4285 // CHECK4-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
4286 // CHECK4-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
4287 // CHECK4-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
4288 // CHECK4-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
4289 // CHECK4-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
4290 // CHECK4-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
4291 // CHECK4-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
4292 // CHECK4-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
4293 // CHECK4-NEXT:    store i8 [[CONV7]], i8* [[CONV1]], align 4
4294 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
4295 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4296 // CHECK4-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
4297 // CHECK4-NEXT:    store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
4298 // CHECK4-NEXT:    ret void
4299 //
4300 //
4301 // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
4302 // CHECK4-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4303 // CHECK4-NEXT:  entry:
4304 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4305 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4306 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4307 // CHECK4-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
4308 // CHECK4-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
4309 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4310 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4311 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4312 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4313 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4314 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4315 // CHECK4-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
4316 // CHECK4-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
4317 // CHECK4-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
4318 // CHECK4-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
4319 // CHECK4-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
4320 // CHECK4-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
4321 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
4322 // CHECK4-NEXT:    ret void
4323 //
4324 //
4325 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..14
4326 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
4327 // CHECK4-NEXT:  entry:
4328 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
4329 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
4330 // CHECK4-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4331 // CHECK4-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
4332 // CHECK4-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
4333 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
4334 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
4335 // CHECK4-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4336 // CHECK4-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
4337 // CHECK4-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
4338 // CHECK4-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
4339 // CHECK4-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
4340 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
4341 // CHECK4-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
4342 // CHECK4-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
4343 // CHECK4-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
4344 // CHECK4-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
4345 // CHECK4-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
4346 // CHECK4-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
4347 // CHECK4-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
4348 // CHECK4-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
4349 // CHECK4-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4350 // CHECK4-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
4351 // CHECK4-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
4352 // CHECK4-NEXT:    ret void
4353 //
4354 //
4355 // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
4356 // CHECK4-SAME: () #[[ATTR5:[0-9]+]] {
4357 // CHECK4-NEXT:  entry:
4358 // CHECK4-NEXT:    call void @__tgt_register_requires(i64 1)
4359 // CHECK4-NEXT:    ret void
4360 //
4361 //
4362 // CHECK5-LABEL: define {{[^@]+}}@_Z3fooi
4363 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
4364 // CHECK5-NEXT:  entry:
4365 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4366 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
4367 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
4368 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
4369 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
4370 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
4371 // CHECK5-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
4372 // CHECK5-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
4373 // CHECK5-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
4374 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4375 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
4376 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
4377 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4378 // CHECK5-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
4379 // CHECK5-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
4380 // CHECK5-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
4381 // CHECK5-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
4382 // CHECK5-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
4383 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
4384 // CHECK5-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
4385 // CHECK5-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
4386 // CHECK5-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
4387 // CHECK5-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
4388 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
4389 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
4390 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4391 // CHECK5-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
4392 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
4393 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
4394 // CHECK5-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
4395 // CHECK5-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
4396 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4397 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
4398 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4399 // CHECK5-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
4400 // CHECK5-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
4401 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
4402 // CHECK5-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
4403 // CHECK5-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
4404 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A]], align 4
4405 // CHECK5-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
4406 // CHECK5-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
4407 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
4408 // CHECK5-NEXT:    [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4
4409 // CHECK5-NEXT:    [[CONV9:%.*]] = fpext float [[TMP11]] to double
4410 // CHECK5-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
4411 // CHECK5-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
4412 // CHECK5-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
4413 // CHECK5-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
4414 // CHECK5-NEXT:    [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4
4415 // CHECK5-NEXT:    [[CONV13:%.*]] = fpext float [[TMP12]] to double
4416 // CHECK5-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
4417 // CHECK5-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
4418 // CHECK5-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
4419 // CHECK5-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
4420 // CHECK5-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
4421 // CHECK5-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8
4422 // CHECK5-NEXT:    [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00
4423 // CHECK5-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
4424 // CHECK5-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]]
4425 // CHECK5-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]]
4426 // CHECK5-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
4427 // CHECK5-NEXT:    [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8
4428 // CHECK5-NEXT:    [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00
4429 // CHECK5-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
4430 // CHECK5-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
4431 // CHECK5-NEXT:    [[TMP16:%.*]] = load i64, i64* [[X]], align 8
4432 // CHECK5-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1
4433 // CHECK5-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
4434 // CHECK5-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
4435 // CHECK5-NEXT:    [[TMP17:%.*]] = load i8, i8* [[Y]], align 8
4436 // CHECK5-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP17]] to i32
4437 // CHECK5-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
4438 // CHECK5-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
4439 // CHECK5-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
4440 // CHECK5-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
4441 // CHECK5-NEXT:    [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
4442 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP19]])
4443 // CHECK5-NEXT:    ret i32 [[TMP18]]
4444 //
4445 //
4446 // CHECK5-LABEL: define {{[^@]+}}@_Z3bari
4447 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
4448 // CHECK5-NEXT:  entry:
4449 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4450 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
4451 // CHECK5-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
4452 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4453 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
4454 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4455 // CHECK5-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
4456 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
4457 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4458 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4459 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4460 // CHECK5-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
4461 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4462 // CHECK5-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4463 // CHECK5-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
4464 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4465 // CHECK5-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
4466 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4467 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4468 // CHECK5-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4469 // CHECK5-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4470 // CHECK5-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
4471 // CHECK5-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
4472 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
4473 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
4474 // CHECK5-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4475 // CHECK5-NEXT:    ret i32 [[TMP8]]
4476 //
4477 //
4478 // CHECK5-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4479 // CHECK5-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
4480 // CHECK5-NEXT:  entry:
4481 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4482 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4483 // CHECK5-NEXT:    [[B:%.*]] = alloca i32, align 4
4484 // CHECK5-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
4485 // CHECK5-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
4486 // CHECK5-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4487 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4488 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4489 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4490 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4491 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
4492 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4493 // CHECK5-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
4494 // CHECK5-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
4495 // CHECK5-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
4496 // CHECK5-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
4497 // CHECK5-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
4498 // CHECK5-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
4499 // CHECK5-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
4500 // CHECK5-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
4501 // CHECK5-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
4502 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
4503 // CHECK5-NEXT:    store double [[ADD2]], double* [[A]], align 8
4504 // CHECK5-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
4505 // CHECK5-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 8
4506 // CHECK5-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
4507 // CHECK5-NEXT:    store double [[INC]], double* [[A3]], align 8
4508 // CHECK5-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
4509 // CHECK5-NEXT:    [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
4510 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
4511 // CHECK5-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
4512 // CHECK5-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
4513 // CHECK5-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
4514 // CHECK5-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
4515 // CHECK5-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
4516 // CHECK5-NEXT:    [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
4517 // CHECK5-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
4518 // CHECK5-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4
4519 // CHECK5-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
4520 // CHECK5-NEXT:    [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
4521 // CHECK5-NEXT:    call void @llvm.stackrestore(i8* [[TMP11]])
4522 // CHECK5-NEXT:    ret i32 [[ADD9]]
4523 //
4524 //
4525 // CHECK5-LABEL: define {{[^@]+}}@_ZL7fstatici
4526 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
4527 // CHECK5-NEXT:  entry:
4528 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4529 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
4530 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
4531 // CHECK5-NEXT:    [[AAA:%.*]] = alloca i8, align 1
4532 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4533 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4534 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
4535 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
4536 // CHECK5-NEXT:    store i8 0, i8* [[AAA]], align 1
4537 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4538 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4539 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4540 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
4541 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4542 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4543 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4544 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
4545 // CHECK5-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
4546 // CHECK5-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
4547 // CHECK5-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
4548 // CHECK5-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
4549 // CHECK5-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
4550 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
4551 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4552 // CHECK5-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
4553 // CHECK5-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
4554 // CHECK5-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
4555 // CHECK5-NEXT:    ret i32 [[TMP4]]
4556 //
4557 //
4558 // CHECK5-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4559 // CHECK5-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
4560 // CHECK5-NEXT:  entry:
4561 // CHECK5-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4562 // CHECK5-NEXT:    [[A:%.*]] = alloca i32, align 4
4563 // CHECK5-NEXT:    [[AA:%.*]] = alloca i16, align 2
4564 // CHECK5-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4565 // CHECK5-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4566 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
4567 // CHECK5-NEXT:    store i16 0, i16* [[AA]], align 2
4568 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4569 // CHECK5-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4570 // CHECK5-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4571 // CHECK5-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
4572 // CHECK5-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4573 // CHECK5-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4574 // CHECK5-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4575 // CHECK5-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
4576 // CHECK5-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
4577 // CHECK5-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4578 // CHECK5-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
4579 // CHECK5-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
4580 // CHECK5-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4581 // CHECK5-NEXT:    ret i32 [[TMP3]]
4582 //
4583 //
4584 // CHECK6-LABEL: define {{[^@]+}}@_Z3fooi
4585 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
4586 // CHECK6-NEXT:  entry:
4587 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4588 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
4589 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
4590 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
4591 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
4592 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
4593 // CHECK6-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
4594 // CHECK6-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
4595 // CHECK6-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
4596 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4597 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
4598 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
4599 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4600 // CHECK6-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
4601 // CHECK6-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
4602 // CHECK6-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
4603 // CHECK6-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
4604 // CHECK6-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
4605 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
4606 // CHECK6-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
4607 // CHECK6-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
4608 // CHECK6-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
4609 // CHECK6-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
4610 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
4611 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
4612 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4613 // CHECK6-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
4614 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
4615 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
4616 // CHECK6-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
4617 // CHECK6-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
4618 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4619 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
4620 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4621 // CHECK6-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
4622 // CHECK6-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
4623 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
4624 // CHECK6-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
4625 // CHECK6-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
4626 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A]], align 4
4627 // CHECK6-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
4628 // CHECK6-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
4629 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
4630 // CHECK6-NEXT:    [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4
4631 // CHECK6-NEXT:    [[CONV9:%.*]] = fpext float [[TMP11]] to double
4632 // CHECK6-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
4633 // CHECK6-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
4634 // CHECK6-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
4635 // CHECK6-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
4636 // CHECK6-NEXT:    [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4
4637 // CHECK6-NEXT:    [[CONV13:%.*]] = fpext float [[TMP12]] to double
4638 // CHECK6-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
4639 // CHECK6-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
4640 // CHECK6-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
4641 // CHECK6-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
4642 // CHECK6-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
4643 // CHECK6-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8
4644 // CHECK6-NEXT:    [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00
4645 // CHECK6-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
4646 // CHECK6-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]]
4647 // CHECK6-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]]
4648 // CHECK6-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
4649 // CHECK6-NEXT:    [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8
4650 // CHECK6-NEXT:    [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00
4651 // CHECK6-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
4652 // CHECK6-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
4653 // CHECK6-NEXT:    [[TMP16:%.*]] = load i64, i64* [[X]], align 8
4654 // CHECK6-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1
4655 // CHECK6-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
4656 // CHECK6-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
4657 // CHECK6-NEXT:    [[TMP17:%.*]] = load i8, i8* [[Y]], align 8
4658 // CHECK6-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP17]] to i32
4659 // CHECK6-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
4660 // CHECK6-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
4661 // CHECK6-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
4662 // CHECK6-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
4663 // CHECK6-NEXT:    [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
4664 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP19]])
4665 // CHECK6-NEXT:    ret i32 [[TMP18]]
4666 //
4667 //
4668 // CHECK6-LABEL: define {{[^@]+}}@_Z3bari
4669 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
4670 // CHECK6-NEXT:  entry:
4671 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4672 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
4673 // CHECK6-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
4674 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4675 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
4676 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4677 // CHECK6-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
4678 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
4679 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4680 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4681 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4682 // CHECK6-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
4683 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4684 // CHECK6-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4685 // CHECK6-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
4686 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4687 // CHECK6-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
4688 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4689 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4690 // CHECK6-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4691 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4692 // CHECK6-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
4693 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
4694 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
4695 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
4696 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4697 // CHECK6-NEXT:    ret i32 [[TMP8]]
4698 //
4699 //
4700 // CHECK6-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4701 // CHECK6-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
4702 // CHECK6-NEXT:  entry:
4703 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
4704 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4705 // CHECK6-NEXT:    [[B:%.*]] = alloca i32, align 4
4706 // CHECK6-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
4707 // CHECK6-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
4708 // CHECK6-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
4709 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4710 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
4711 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4712 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4713 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
4714 // CHECK6-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4715 // CHECK6-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
4716 // CHECK6-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
4717 // CHECK6-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
4718 // CHECK6-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
4719 // CHECK6-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
4720 // CHECK6-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
4721 // CHECK6-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
4722 // CHECK6-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
4723 // CHECK6-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
4724 // CHECK6-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
4725 // CHECK6-NEXT:    store double [[ADD2]], double* [[A]], align 8
4726 // CHECK6-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
4727 // CHECK6-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 8
4728 // CHECK6-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
4729 // CHECK6-NEXT:    store double [[INC]], double* [[A3]], align 8
4730 // CHECK6-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
4731 // CHECK6-NEXT:    [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
4732 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
4733 // CHECK6-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
4734 // CHECK6-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
4735 // CHECK6-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
4736 // CHECK6-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
4737 // CHECK6-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
4738 // CHECK6-NEXT:    [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
4739 // CHECK6-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
4740 // CHECK6-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4
4741 // CHECK6-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
4742 // CHECK6-NEXT:    [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
4743 // CHECK6-NEXT:    call void @llvm.stackrestore(i8* [[TMP11]])
4744 // CHECK6-NEXT:    ret i32 [[ADD9]]
4745 //
4746 //
4747 // CHECK6-LABEL: define {{[^@]+}}@_ZL7fstatici
4748 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
4749 // CHECK6-NEXT:  entry:
4750 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4751 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
4752 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
4753 // CHECK6-NEXT:    [[AAA:%.*]] = alloca i8, align 1
4754 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4755 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4756 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
4757 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
4758 // CHECK6-NEXT:    store i8 0, i8* [[AAA]], align 1
4759 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4760 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4761 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4762 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
4763 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4764 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4765 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4766 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
4767 // CHECK6-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
4768 // CHECK6-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
4769 // CHECK6-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
4770 // CHECK6-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
4771 // CHECK6-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
4772 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
4773 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4774 // CHECK6-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
4775 // CHECK6-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
4776 // CHECK6-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
4777 // CHECK6-NEXT:    ret i32 [[TMP4]]
4778 //
4779 //
4780 // CHECK6-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
4781 // CHECK6-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
4782 // CHECK6-NEXT:  entry:
4783 // CHECK6-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4784 // CHECK6-NEXT:    [[A:%.*]] = alloca i32, align 4
4785 // CHECK6-NEXT:    [[AA:%.*]] = alloca i16, align 2
4786 // CHECK6-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4787 // CHECK6-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4788 // CHECK6-NEXT:    store i32 0, i32* [[A]], align 4
4789 // CHECK6-NEXT:    store i16 0, i16* [[AA]], align 2
4790 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4791 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4792 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4793 // CHECK6-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
4794 // CHECK6-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4795 // CHECK6-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4796 // CHECK6-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4797 // CHECK6-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
4798 // CHECK6-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
4799 // CHECK6-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4800 // CHECK6-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
4801 // CHECK6-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
4802 // CHECK6-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4803 // CHECK6-NEXT:    ret i32 [[TMP3]]
4804 //
4805 //
4806 // CHECK7-LABEL: define {{[^@]+}}@_Z3fooi
4807 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
4808 // CHECK7-NEXT:  entry:
4809 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4810 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
4811 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
4812 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
4813 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
4814 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
4815 // CHECK7-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
4816 // CHECK7-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
4817 // CHECK7-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
4818 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4819 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
4820 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
4821 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4822 // CHECK7-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
4823 // CHECK7-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
4824 // CHECK7-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
4825 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
4826 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4827 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
4828 // CHECK7-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
4829 // CHECK7-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
4830 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
4831 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
4832 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4833 // CHECK7-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2
4834 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
4835 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
4836 // CHECK7-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
4837 // CHECK7-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
4838 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
4839 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
4840 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4841 // CHECK7-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
4842 // CHECK7-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP7]] to i32
4843 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
4844 // CHECK7-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
4845 // CHECK7-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
4846 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4847 // CHECK7-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
4848 // CHECK7-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
4849 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
4850 // CHECK7-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
4851 // CHECK7-NEXT:    [[CONV9:%.*]] = fpext float [[TMP9]] to double
4852 // CHECK7-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
4853 // CHECK7-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
4854 // CHECK7-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
4855 // CHECK7-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
4856 // CHECK7-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4
4857 // CHECK7-NEXT:    [[CONV13:%.*]] = fpext float [[TMP10]] to double
4858 // CHECK7-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
4859 // CHECK7-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
4860 // CHECK7-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
4861 // CHECK7-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
4862 // CHECK7-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2
4863 // CHECK7-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8
4864 // CHECK7-NEXT:    [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00
4865 // CHECK7-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
4866 // CHECK7-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
4867 // CHECK7-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]]
4868 // CHECK7-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3
4869 // CHECK7-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8
4870 // CHECK7-NEXT:    [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00
4871 // CHECK7-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
4872 // CHECK7-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
4873 // CHECK7-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
4874 // CHECK7-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1
4875 // CHECK7-NEXT:    store i64 [[ADD22]], i64* [[X]], align 4
4876 // CHECK7-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
4877 // CHECK7-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
4878 // CHECK7-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP15]] to i32
4879 // CHECK7-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
4880 // CHECK7-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
4881 // CHECK7-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 4
4882 // CHECK7-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
4883 // CHECK7-NEXT:    [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4884 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP17]])
4885 // CHECK7-NEXT:    ret i32 [[TMP16]]
4886 //
4887 //
4888 // CHECK7-LABEL: define {{[^@]+}}@_Z3bari
4889 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4890 // CHECK7-NEXT:  entry:
4891 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4892 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
4893 // CHECK7-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
4894 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4895 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
4896 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4897 // CHECK7-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
4898 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
4899 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
4900 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4901 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
4902 // CHECK7-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
4903 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
4904 // CHECK7-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
4905 // CHECK7-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
4906 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
4907 // CHECK7-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
4908 // CHECK7-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
4909 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
4910 // CHECK7-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
4911 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
4912 // CHECK7-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
4913 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
4914 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
4915 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
4916 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
4917 // CHECK7-NEXT:    ret i32 [[TMP8]]
4918 //
4919 //
4920 // CHECK7-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
4921 // CHECK7-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
4922 // CHECK7-NEXT:  entry:
4923 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
4924 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4925 // CHECK7-NEXT:    [[B:%.*]] = alloca i32, align 4
4926 // CHECK7-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
4927 // CHECK7-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
4928 // CHECK7-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
4929 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4930 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
4931 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
4932 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4933 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
4934 // CHECK7-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
4935 // CHECK7-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
4936 // CHECK7-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
4937 // CHECK7-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
4938 // CHECK7-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
4939 // CHECK7-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
4940 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
4941 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
4942 // CHECK7-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
4943 // CHECK7-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
4944 // CHECK7-NEXT:    store double [[ADD2]], double* [[A]], align 4
4945 // CHECK7-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
4946 // CHECK7-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
4947 // CHECK7-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
4948 // CHECK7-NEXT:    store double [[INC]], double* [[A3]], align 4
4949 // CHECK7-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
4950 // CHECK7-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
4951 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
4952 // CHECK7-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
4953 // CHECK7-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
4954 // CHECK7-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
4955 // CHECK7-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
4956 // CHECK7-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
4957 // CHECK7-NEXT:    [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
4958 // CHECK7-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
4959 // CHECK7-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4
4960 // CHECK7-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
4961 // CHECK7-NEXT:    [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
4962 // CHECK7-NEXT:    call void @llvm.stackrestore(i8* [[TMP10]])
4963 // CHECK7-NEXT:    ret i32 [[ADD9]]
4964 //
4965 //
4966 // CHECK7-LABEL: define {{[^@]+}}@_ZL7fstatici
4967 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
4968 // CHECK7-NEXT:  entry:
4969 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
4970 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
4971 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
4972 // CHECK7-NEXT:    [[AAA:%.*]] = alloca i8, align 1
4973 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
4974 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
4975 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
4976 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
4977 // CHECK7-NEXT:    store i8 0, i8* [[AAA]], align 1
4978 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
4979 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
4980 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
4981 // CHECK7-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
4982 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
4983 // CHECK7-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
4984 // CHECK7-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
4985 // CHECK7-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
4986 // CHECK7-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
4987 // CHECK7-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
4988 // CHECK7-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
4989 // CHECK7-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
4990 // CHECK7-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
4991 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
4992 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
4993 // CHECK7-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
4994 // CHECK7-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
4995 // CHECK7-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
4996 // CHECK7-NEXT:    ret i32 [[TMP4]]
4997 //
4998 //
4999 // CHECK7-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
5000 // CHECK7-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
5001 // CHECK7-NEXT:  entry:
5002 // CHECK7-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5003 // CHECK7-NEXT:    [[A:%.*]] = alloca i32, align 4
5004 // CHECK7-NEXT:    [[AA:%.*]] = alloca i16, align 2
5005 // CHECK7-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
5006 // CHECK7-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5007 // CHECK7-NEXT:    store i32 0, i32* [[A]], align 4
5008 // CHECK7-NEXT:    store i16 0, i16* [[AA]], align 2
5009 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
5010 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5011 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
5012 // CHECK7-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
5013 // CHECK7-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
5014 // CHECK7-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
5015 // CHECK7-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
5016 // CHECK7-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
5017 // CHECK7-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
5018 // CHECK7-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5019 // CHECK7-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
5020 // CHECK7-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
5021 // CHECK7-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
5022 // CHECK7-NEXT:    ret i32 [[TMP3]]
5023 //
5024 //
5025 // CHECK8-LABEL: define {{[^@]+}}@_Z3fooi
5026 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
5027 // CHECK8-NEXT:  entry:
5028 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5029 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
5030 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
5031 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
5032 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
5033 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
5034 // CHECK8-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
5035 // CHECK8-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
5036 // CHECK8-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
5037 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5038 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
5039 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
5040 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5041 // CHECK8-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
5042 // CHECK8-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
5043 // CHECK8-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
5044 // CHECK8-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
5045 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5046 // CHECK8-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
5047 // CHECK8-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
5048 // CHECK8-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
5049 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
5050 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
5051 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
5052 // CHECK8-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2
5053 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
5054 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
5055 // CHECK8-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
5056 // CHECK8-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
5057 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
5058 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
5059 // CHECK8-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
5060 // CHECK8-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
5061 // CHECK8-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP7]] to i32
5062 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
5063 // CHECK8-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
5064 // CHECK8-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
5065 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
5066 // CHECK8-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
5067 // CHECK8-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
5068 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
5069 // CHECK8-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
5070 // CHECK8-NEXT:    [[CONV9:%.*]] = fpext float [[TMP9]] to double
5071 // CHECK8-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
5072 // CHECK8-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
5073 // CHECK8-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
5074 // CHECK8-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
5075 // CHECK8-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4
5076 // CHECK8-NEXT:    [[CONV13:%.*]] = fpext float [[TMP10]] to double
5077 // CHECK8-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
5078 // CHECK8-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
5079 // CHECK8-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
5080 // CHECK8-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
5081 // CHECK8-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2
5082 // CHECK8-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8
5083 // CHECK8-NEXT:    [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00
5084 // CHECK8-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
5085 // CHECK8-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
5086 // CHECK8-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]]
5087 // CHECK8-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3
5088 // CHECK8-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8
5089 // CHECK8-NEXT:    [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00
5090 // CHECK8-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
5091 // CHECK8-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
5092 // CHECK8-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
5093 // CHECK8-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1
5094 // CHECK8-NEXT:    store i64 [[ADD22]], i64* [[X]], align 4
5095 // CHECK8-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
5096 // CHECK8-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
5097 // CHECK8-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP15]] to i32
5098 // CHECK8-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
5099 // CHECK8-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
5100 // CHECK8-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 4
5101 // CHECK8-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
5102 // CHECK8-NEXT:    [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
5103 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP17]])
5104 // CHECK8-NEXT:    ret i32 [[TMP16]]
5105 //
5106 //
5107 // CHECK8-LABEL: define {{[^@]+}}@_Z3bari
5108 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
5109 // CHECK8-NEXT:  entry:
5110 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5111 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
5112 // CHECK8-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
5113 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5114 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
5115 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5116 // CHECK8-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
5117 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
5118 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
5119 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
5120 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
5121 // CHECK8-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
5122 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
5123 // CHECK8-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
5124 // CHECK8-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
5125 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
5126 // CHECK8-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
5127 // CHECK8-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
5128 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
5129 // CHECK8-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
5130 // CHECK8-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
5131 // CHECK8-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
5132 // CHECK8-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
5133 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
5134 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
5135 // CHECK8-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
5136 // CHECK8-NEXT:    ret i32 [[TMP8]]
5137 //
5138 //
5139 // CHECK8-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
5140 // CHECK8-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
5141 // CHECK8-NEXT:  entry:
5142 // CHECK8-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
5143 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5144 // CHECK8-NEXT:    [[B:%.*]] = alloca i32, align 4
5145 // CHECK8-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
5146 // CHECK8-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
5147 // CHECK8-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
5148 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5149 // CHECK8-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
5150 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
5151 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5152 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
5153 // CHECK8-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
5154 // CHECK8-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
5155 // CHECK8-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
5156 // CHECK8-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
5157 // CHECK8-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
5158 // CHECK8-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
5159 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
5160 // CHECK8-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
5161 // CHECK8-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
5162 // CHECK8-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
5163 // CHECK8-NEXT:    store double [[ADD2]], double* [[A]], align 4
5164 // CHECK8-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
5165 // CHECK8-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
5166 // CHECK8-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
5167 // CHECK8-NEXT:    store double [[INC]], double* [[A3]], align 4
5168 // CHECK8-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
5169 // CHECK8-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
5170 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
5171 // CHECK8-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
5172 // CHECK8-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
5173 // CHECK8-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
5174 // CHECK8-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
5175 // CHECK8-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
5176 // CHECK8-NEXT:    [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
5177 // CHECK8-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
5178 // CHECK8-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4
5179 // CHECK8-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
5180 // CHECK8-NEXT:    [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
5181 // CHECK8-NEXT:    call void @llvm.stackrestore(i8* [[TMP10]])
5182 // CHECK8-NEXT:    ret i32 [[ADD9]]
5183 //
5184 //
5185 // CHECK8-LABEL: define {{[^@]+}}@_ZL7fstatici
5186 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
5187 // CHECK8-NEXT:  entry:
5188 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5189 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
5190 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
5191 // CHECK8-NEXT:    [[AAA:%.*]] = alloca i8, align 1
5192 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
5193 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5194 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
5195 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
5196 // CHECK8-NEXT:    store i8 0, i8* [[AAA]], align 1
5197 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
5198 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5199 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
5200 // CHECK8-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
5201 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
5202 // CHECK8-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
5203 // CHECK8-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
5204 // CHECK8-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
5205 // CHECK8-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
5206 // CHECK8-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
5207 // CHECK8-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
5208 // CHECK8-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
5209 // CHECK8-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
5210 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
5211 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5212 // CHECK8-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
5213 // CHECK8-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
5214 // CHECK8-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
5215 // CHECK8-NEXT:    ret i32 [[TMP4]]
5216 //
5217 //
5218 // CHECK8-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
5219 // CHECK8-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
5220 // CHECK8-NEXT:  entry:
5221 // CHECK8-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
5222 // CHECK8-NEXT:    [[A:%.*]] = alloca i32, align 4
5223 // CHECK8-NEXT:    [[AA:%.*]] = alloca i16, align 2
5224 // CHECK8-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
5225 // CHECK8-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
5226 // CHECK8-NEXT:    store i32 0, i32* [[A]], align 4
5227 // CHECK8-NEXT:    store i16 0, i16* [[AA]], align 2
5228 // CHECK8-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
5229 // CHECK8-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5230 // CHECK8-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
5231 // CHECK8-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
5232 // CHECK8-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
5233 // CHECK8-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
5234 // CHECK8-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
5235 // CHECK8-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
5236 // CHECK8-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
5237 // CHECK8-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5238 // CHECK8-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
5239 // CHECK8-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
5240 // CHECK8-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
5241 // CHECK8-NEXT:    ret i32 [[TMP3]]
5242 //
5243 //
5244 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
5245 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] {
5246 // CHECK9-NEXT:  entry:
5247 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
5248 // CHECK9-NEXT:    ret void
5249 //
5250 //
5251 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined.
5252 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
5253 // CHECK9-NEXT:  entry:
5254 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5255 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5256 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5257 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5258 // CHECK9-NEXT:    ret void
5259 //
5260 //
5261 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
5262 // CHECK9-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
5263 // CHECK9-NEXT:  entry:
5264 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5265 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5266 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5267 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5268 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
5269 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5270 // CHECK9-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
5271 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5272 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
5273 // CHECK9-NEXT:    ret void
5274 //
5275 //
5276 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..1
5277 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5278 // CHECK9-NEXT:  entry:
5279 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5280 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5281 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5282 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5283 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5284 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5285 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5286 // CHECK9-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
5287 // CHECK9-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
5288 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
5289 // CHECK9-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
5290 // CHECK9-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 8
5291 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5292 // CHECK9-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
5293 // CHECK9-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
5294 // CHECK9-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
5295 // CHECK9-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
5296 // CHECK9:       .cancel.exit:
5297 // CHECK9-NEXT:    br label [[DOTCANCEL_CONTINUE]]
5298 // CHECK9:       .cancel.continue:
5299 // CHECK9-NEXT:    ret void
5300 //
5301 //
5302 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
5303 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5304 // CHECK9-NEXT:  entry:
5305 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5306 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5307 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5308 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5309 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5310 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5311 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5312 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5313 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5314 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5315 // CHECK9-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
5316 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
5317 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
5318 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5319 // CHECK9-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
5320 // CHECK9-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5321 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
5322 // CHECK9-NEXT:    ret void
5323 //
5324 //
5325 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..2
5326 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5327 // CHECK9-NEXT:  entry:
5328 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5329 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5330 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5331 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5332 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5333 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5334 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5335 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5336 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5337 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5338 // CHECK9-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5339 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5340 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
5341 // CHECK9-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
5342 // CHECK9-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
5343 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
5344 // CHECK9-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
5345 // CHECK9-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
5346 // CHECK9-NEXT:    ret void
5347 //
5348 //
5349 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
5350 // CHECK9-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
5351 // CHECK9-NEXT:  entry:
5352 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5353 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
5354 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5355 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
5356 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
5357 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5358 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
5359 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
5360 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
5361 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5362 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5363 // CHECK9-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
5364 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5365 // CHECK9-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
5366 // CHECK9-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
5367 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5368 // CHECK9-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
5369 // CHECK9-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
5370 // CHECK9-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
5371 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5372 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
5373 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5374 // CHECK9-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
5375 // CHECK9-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
5376 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5377 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
5378 // CHECK9-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
5379 // CHECK9-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
5380 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
5381 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5382 // CHECK9-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
5383 // CHECK9-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
5384 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
5385 // CHECK9-NEXT:    ret void
5386 //
5387 //
5388 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..3
5389 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
5390 // CHECK9-NEXT:  entry:
5391 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5392 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5393 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5394 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
5395 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5396 // CHECK9-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
5397 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
5398 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5399 // CHECK9-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
5400 // CHECK9-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
5401 // CHECK9-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
5402 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5403 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5404 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5405 // CHECK9-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
5406 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5407 // CHECK9-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
5408 // CHECK9-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
5409 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5410 // CHECK9-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
5411 // CHECK9-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
5412 // CHECK9-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
5413 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5414 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
5415 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5416 // CHECK9-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
5417 // CHECK9-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
5418 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5419 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
5420 // CHECK9-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
5421 // CHECK9-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
5422 // CHECK9-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
5423 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
5424 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
5425 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
5426 // CHECK9-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
5427 // CHECK9-NEXT:    [[CONV5:%.*]] = fpext float [[TMP9]] to double
5428 // CHECK9-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
5429 // CHECK9-NEXT:    [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
5430 // CHECK9-NEXT:    store float [[CONV7]], float* [[ARRAYIDX]], align 4
5431 // CHECK9-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
5432 // CHECK9-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
5433 // CHECK9-NEXT:    [[CONV9:%.*]] = fpext float [[TMP10]] to double
5434 // CHECK9-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
5435 // CHECK9-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
5436 // CHECK9-NEXT:    store float [[CONV11]], float* [[ARRAYIDX8]], align 4
5437 // CHECK9-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
5438 // CHECK9-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
5439 // CHECK9-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
5440 // CHECK9-NEXT:    [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
5441 // CHECK9-NEXT:    store double [[ADD14]], double* [[ARRAYIDX13]], align 8
5442 // CHECK9-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
5443 // CHECK9-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
5444 // CHECK9-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
5445 // CHECK9-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
5446 // CHECK9-NEXT:    [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
5447 // CHECK9-NEXT:    store double [[ADD17]], double* [[ARRAYIDX16]], align 8
5448 // CHECK9-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
5449 // CHECK9-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 8
5450 // CHECK9-NEXT:    [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
5451 // CHECK9-NEXT:    store i64 [[ADD18]], i64* [[X]], align 8
5452 // CHECK9-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
5453 // CHECK9-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
5454 // CHECK9-NEXT:    [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
5455 // CHECK9-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
5456 // CHECK9-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
5457 // CHECK9-NEXT:    store i8 [[CONV21]], i8* [[Y]], align 8
5458 // CHECK9-NEXT:    ret void
5459 //
5460 //
5461 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
5462 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5463 // CHECK9-NEXT:  entry:
5464 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5465 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5466 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
5467 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5468 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5469 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5470 // CHECK9-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
5471 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5472 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5473 // CHECK9-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
5474 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5475 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5476 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5477 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
5478 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5479 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
5480 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5481 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
5482 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
5483 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
5484 // CHECK9-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5485 // CHECK9-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
5486 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5487 // CHECK9-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
5488 // CHECK9-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
5489 // CHECK9-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
5490 // CHECK9-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
5491 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
5492 // CHECK9-NEXT:    ret void
5493 //
5494 //
5495 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..4
5496 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5497 // CHECK9-NEXT:  entry:
5498 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5499 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5500 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5501 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5502 // CHECK9-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
5503 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5504 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5505 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5506 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5507 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5508 // CHECK9-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
5509 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5510 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5511 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5512 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
5513 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5514 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
5515 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
5516 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
5517 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
5518 // CHECK9-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
5519 // CHECK9-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
5520 // CHECK9-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
5521 // CHECK9-NEXT:    store i16 [[CONV5]], i16* [[CONV1]], align 8
5522 // CHECK9-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
5523 // CHECK9-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
5524 // CHECK9-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
5525 // CHECK9-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
5526 // CHECK9-NEXT:    store i8 [[CONV8]], i8* [[CONV2]], align 8
5527 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
5528 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5529 // CHECK9-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
5530 // CHECK9-NEXT:    store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
5531 // CHECK9-NEXT:    ret void
5532 //
5533 //
5534 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
5535 // CHECK9-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
5536 // CHECK9-NEXT:  entry:
5537 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
5538 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5539 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5540 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5541 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
5542 // CHECK9-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
5543 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
5544 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
5545 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5546 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5547 // CHECK9-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
5548 // CHECK9-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
5549 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
5550 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5551 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5552 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
5553 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
5554 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
5555 // CHECK9-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
5556 // CHECK9-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
5557 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
5558 // CHECK9-NEXT:    ret void
5559 //
5560 //
5561 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..5
5562 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
5563 // CHECK9-NEXT:  entry:
5564 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5565 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5566 // CHECK9-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
5567 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5568 // CHECK9-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5569 // CHECK9-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5570 // CHECK9-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
5571 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5572 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5573 // CHECK9-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
5574 // CHECK9-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
5575 // CHECK9-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5576 // CHECK9-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5577 // CHECK9-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
5578 // CHECK9-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
5579 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
5580 // CHECK9-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5581 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5582 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
5583 // CHECK9-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
5584 // CHECK9-NEXT:    [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
5585 // CHECK9-NEXT:    [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
5586 // CHECK9-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
5587 // CHECK9-NEXT:    store double [[ADD]], double* [[A]], align 8
5588 // CHECK9-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
5589 // CHECK9-NEXT:    [[TMP5:%.*]] = load double, double* [[A4]], align 8
5590 // CHECK9-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
5591 // CHECK9-NEXT:    store double [[INC]], double* [[A4]], align 8
5592 // CHECK9-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
5593 // CHECK9-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
5594 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
5595 // CHECK9-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
5596 // CHECK9-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
5597 // CHECK9-NEXT:    ret void
5598 //
5599 //
5600 // CHECK9-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
5601 // CHECK9-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5602 // CHECK9-NEXT:  entry:
5603 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5604 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5605 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5606 // CHECK9-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5607 // CHECK9-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5608 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5609 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5610 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5611 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5612 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5613 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5614 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
5615 // CHECK9-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5616 // CHECK9-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
5617 // CHECK9-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
5618 // CHECK9-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
5619 // CHECK9-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5620 // CHECK9-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
5621 // CHECK9-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5622 // CHECK9-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
5623 // CHECK9-NEXT:    ret void
5624 //
5625 //
5626 // CHECK9-LABEL: define {{[^@]+}}@.omp_outlined..6
5627 // CHECK9-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5628 // CHECK9-NEXT:  entry:
5629 // CHECK9-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5630 // CHECK9-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5631 // CHECK9-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5632 // CHECK9-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5633 // CHECK9-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5634 // CHECK9-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5635 // CHECK9-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5636 // CHECK9-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5637 // CHECK9-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5638 // CHECK9-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5639 // CHECK9-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5640 // CHECK9-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5641 // CHECK9-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5642 // CHECK9-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
5643 // CHECK9-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
5644 // CHECK9-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
5645 // CHECK9-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
5646 // CHECK9-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
5647 // CHECK9-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
5648 // CHECK9-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
5649 // CHECK9-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
5650 // CHECK9-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
5651 // CHECK9-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5652 // CHECK9-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
5653 // CHECK9-NEXT:    store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
5654 // CHECK9-NEXT:    ret void
5655 //
5656 //
5657 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
5658 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
5659 // CHECK10-NEXT:  entry:
5660 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
5661 // CHECK10-NEXT:    ret void
5662 //
5663 //
5664 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined.
5665 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
5666 // CHECK10-NEXT:  entry:
5667 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5668 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5669 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5670 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5671 // CHECK10-NEXT:    ret void
5672 //
5673 //
5674 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
5675 // CHECK10-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
5676 // CHECK10-NEXT:  entry:
5677 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5678 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5679 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5680 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5681 // CHECK10-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
5682 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5683 // CHECK10-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
5684 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5685 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
5686 // CHECK10-NEXT:    ret void
5687 //
5688 //
5689 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1
5690 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5691 // CHECK10-NEXT:  entry:
5692 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5693 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5694 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5695 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5696 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5697 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5698 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5699 // CHECK10-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
5700 // CHECK10-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
5701 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
5702 // CHECK10-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
5703 // CHECK10-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 8
5704 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
5705 // CHECK10-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
5706 // CHECK10-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
5707 // CHECK10-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
5708 // CHECK10-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
5709 // CHECK10:       .cancel.exit:
5710 // CHECK10-NEXT:    br label [[DOTCANCEL_CONTINUE]]
5711 // CHECK10:       .cancel.continue:
5712 // CHECK10-NEXT:    ret void
5713 //
5714 //
5715 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
5716 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5717 // CHECK10-NEXT:  entry:
5718 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5719 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5720 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5721 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5722 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5723 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5724 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5725 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5726 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5727 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5728 // CHECK10-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
5729 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
5730 // CHECK10-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
5731 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5732 // CHECK10-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
5733 // CHECK10-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5734 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
5735 // CHECK10-NEXT:    ret void
5736 //
5737 //
5738 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2
5739 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
5740 // CHECK10-NEXT:  entry:
5741 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5742 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5743 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5744 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5745 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5746 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5747 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5748 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5749 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5750 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5751 // CHECK10-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
5752 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
5753 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
5754 // CHECK10-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
5755 // CHECK10-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
5756 // CHECK10-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
5757 // CHECK10-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
5758 // CHECK10-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
5759 // CHECK10-NEXT:    ret void
5760 //
5761 //
5762 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
5763 // CHECK10-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
5764 // CHECK10-NEXT:  entry:
5765 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5766 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
5767 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5768 // CHECK10-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
5769 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
5770 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5771 // CHECK10-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
5772 // CHECK10-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
5773 // CHECK10-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
5774 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5775 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5776 // CHECK10-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
5777 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5778 // CHECK10-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
5779 // CHECK10-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
5780 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5781 // CHECK10-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
5782 // CHECK10-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
5783 // CHECK10-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
5784 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5785 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
5786 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5787 // CHECK10-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
5788 // CHECK10-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
5789 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5790 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
5791 // CHECK10-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
5792 // CHECK10-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
5793 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
5794 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5795 // CHECK10-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
5796 // CHECK10-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
5797 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
5798 // CHECK10-NEXT:    ret void
5799 //
5800 //
5801 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3
5802 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
5803 // CHECK10-NEXT:  entry:
5804 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5805 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5806 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5807 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
5808 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5809 // CHECK10-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
5810 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
5811 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5812 // CHECK10-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
5813 // CHECK10-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
5814 // CHECK10-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
5815 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5816 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5817 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5818 // CHECK10-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
5819 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5820 // CHECK10-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
5821 // CHECK10-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
5822 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5823 // CHECK10-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
5824 // CHECK10-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
5825 // CHECK10-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
5826 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5827 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
5828 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5829 // CHECK10-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
5830 // CHECK10-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
5831 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5832 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
5833 // CHECK10-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
5834 // CHECK10-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
5835 // CHECK10-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
5836 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
5837 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
5838 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
5839 // CHECK10-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
5840 // CHECK10-NEXT:    [[CONV5:%.*]] = fpext float [[TMP9]] to double
5841 // CHECK10-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
5842 // CHECK10-NEXT:    [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
5843 // CHECK10-NEXT:    store float [[CONV7]], float* [[ARRAYIDX]], align 4
5844 // CHECK10-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
5845 // CHECK10-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
5846 // CHECK10-NEXT:    [[CONV9:%.*]] = fpext float [[TMP10]] to double
5847 // CHECK10-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
5848 // CHECK10-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
5849 // CHECK10-NEXT:    store float [[CONV11]], float* [[ARRAYIDX8]], align 4
5850 // CHECK10-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
5851 // CHECK10-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
5852 // CHECK10-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
5853 // CHECK10-NEXT:    [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
5854 // CHECK10-NEXT:    store double [[ADD14]], double* [[ARRAYIDX13]], align 8
5855 // CHECK10-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
5856 // CHECK10-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
5857 // CHECK10-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
5858 // CHECK10-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
5859 // CHECK10-NEXT:    [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
5860 // CHECK10-NEXT:    store double [[ADD17]], double* [[ARRAYIDX16]], align 8
5861 // CHECK10-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
5862 // CHECK10-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 8
5863 // CHECK10-NEXT:    [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
5864 // CHECK10-NEXT:    store i64 [[ADD18]], i64* [[X]], align 8
5865 // CHECK10-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
5866 // CHECK10-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
5867 // CHECK10-NEXT:    [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
5868 // CHECK10-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
5869 // CHECK10-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
5870 // CHECK10-NEXT:    store i8 [[CONV21]], i8* [[Y]], align 8
5871 // CHECK10-NEXT:    ret void
5872 //
5873 //
5874 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
5875 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5876 // CHECK10-NEXT:  entry:
5877 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5878 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5879 // CHECK10-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
5880 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5881 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
5882 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
5883 // CHECK10-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
5884 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5885 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5886 // CHECK10-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
5887 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5888 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5889 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5890 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
5891 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5892 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
5893 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
5894 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
5895 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
5896 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
5897 // CHECK10-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
5898 // CHECK10-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
5899 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
5900 // CHECK10-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
5901 // CHECK10-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
5902 // CHECK10-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
5903 // CHECK10-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
5904 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
5905 // CHECK10-NEXT:    ret void
5906 //
5907 //
5908 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..4
5909 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
5910 // CHECK10-NEXT:  entry:
5911 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5912 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5913 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
5914 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
5915 // CHECK10-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
5916 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
5917 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5918 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5919 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
5920 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
5921 // CHECK10-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
5922 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
5923 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
5924 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
5925 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
5926 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
5927 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
5928 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
5929 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
5930 // CHECK10-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
5931 // CHECK10-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
5932 // CHECK10-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
5933 // CHECK10-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
5934 // CHECK10-NEXT:    store i16 [[CONV5]], i16* [[CONV1]], align 8
5935 // CHECK10-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
5936 // CHECK10-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
5937 // CHECK10-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
5938 // CHECK10-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
5939 // CHECK10-NEXT:    store i8 [[CONV8]], i8* [[CONV2]], align 8
5940 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
5941 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
5942 // CHECK10-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
5943 // CHECK10-NEXT:    store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
5944 // CHECK10-NEXT:    ret void
5945 //
5946 //
5947 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
5948 // CHECK10-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
5949 // CHECK10-NEXT:  entry:
5950 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
5951 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5952 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5953 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5954 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
5955 // CHECK10-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
5956 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
5957 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
5958 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5959 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5960 // CHECK10-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
5961 // CHECK10-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
5962 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
5963 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5964 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5965 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
5966 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
5967 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
5968 // CHECK10-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
5969 // CHECK10-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
5970 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
5971 // CHECK10-NEXT:    ret void
5972 //
5973 //
5974 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..5
5975 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
5976 // CHECK10-NEXT:  entry:
5977 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
5978 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
5979 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
5980 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
5981 // CHECK10-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
5982 // CHECK10-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
5983 // CHECK10-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
5984 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
5985 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
5986 // CHECK10-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
5987 // CHECK10-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
5988 // CHECK10-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
5989 // CHECK10-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
5990 // CHECK10-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
5991 // CHECK10-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
5992 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
5993 // CHECK10-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
5994 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
5995 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
5996 // CHECK10-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
5997 // CHECK10-NEXT:    [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
5998 // CHECK10-NEXT:    [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
5999 // CHECK10-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6000 // CHECK10-NEXT:    store double [[ADD]], double* [[A]], align 8
6001 // CHECK10-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6002 // CHECK10-NEXT:    [[TMP5:%.*]] = load double, double* [[A4]], align 8
6003 // CHECK10-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
6004 // CHECK10-NEXT:    store double [[INC]], double* [[A4]], align 8
6005 // CHECK10-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
6006 // CHECK10-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
6007 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
6008 // CHECK10-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
6009 // CHECK10-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
6010 // CHECK10-NEXT:    ret void
6011 //
6012 //
6013 // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
6014 // CHECK10-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6015 // CHECK10-NEXT:  entry:
6016 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6017 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
6018 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6019 // CHECK10-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
6020 // CHECK10-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
6021 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
6022 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
6023 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6024 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6025 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6026 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6027 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6028 // CHECK10-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
6029 // CHECK10-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
6030 // CHECK10-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
6031 // CHECK10-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
6032 // CHECK10-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
6033 // CHECK10-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
6034 // CHECK10-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
6035 // CHECK10-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
6036 // CHECK10-NEXT:    ret void
6037 //
6038 //
6039 // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..6
6040 // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6041 // CHECK10-NEXT:  entry:
6042 // CHECK10-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
6043 // CHECK10-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
6044 // CHECK10-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
6045 // CHECK10-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
6046 // CHECK10-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
6047 // CHECK10-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
6048 // CHECK10-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
6049 // CHECK10-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
6050 // CHECK10-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
6051 // CHECK10-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
6052 // CHECK10-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
6053 // CHECK10-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
6054 // CHECK10-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
6055 // CHECK10-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
6056 // CHECK10-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6057 // CHECK10-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
6058 // CHECK10-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
6059 // CHECK10-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
6060 // CHECK10-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
6061 // CHECK10-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6062 // CHECK10-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
6063 // CHECK10-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
6064 // CHECK10-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6065 // CHECK10-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
6066 // CHECK10-NEXT:    store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
6067 // CHECK10-NEXT:    ret void
6068 //
6069 //
6070 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
6071 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
6072 // CHECK11-NEXT:  entry:
6073 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
6074 // CHECK11-NEXT:    ret void
6075 //
6076 //
6077 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
6078 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
6079 // CHECK11-NEXT:  entry:
6080 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6081 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6082 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6083 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6084 // CHECK11-NEXT:    ret void
6085 //
6086 //
6087 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
6088 // CHECK11-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
6089 // CHECK11-NEXT:  entry:
6090 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6091 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6092 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6093 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6094 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
6095 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6096 // CHECK11-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
6097 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6098 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
6099 // CHECK11-NEXT:    ret void
6100 //
6101 //
6102 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
6103 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6104 // CHECK11-NEXT:  entry:
6105 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6106 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6107 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6108 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6109 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6110 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6111 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6112 // CHECK11-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
6113 // CHECK11-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
6114 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
6115 // CHECK11-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
6116 // CHECK11-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 4
6117 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6118 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
6119 // CHECK11-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
6120 // CHECK11-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
6121 // CHECK11-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
6122 // CHECK11:       .cancel.exit:
6123 // CHECK11-NEXT:    br label [[DOTCANCEL_CONTINUE]]
6124 // CHECK11:       .cancel.continue:
6125 // CHECK11-NEXT:    ret void
6126 //
6127 //
6128 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
6129 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6130 // CHECK11-NEXT:  entry:
6131 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6132 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6133 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6134 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6135 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6136 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6137 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6138 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6139 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6140 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6141 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
6142 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6143 // CHECK11-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
6144 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6145 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
6146 // CHECK11-NEXT:    ret void
6147 //
6148 //
6149 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2
6150 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6151 // CHECK11-NEXT:  entry:
6152 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6153 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6154 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6155 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6156 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6157 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6158 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6159 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6160 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6161 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6162 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6163 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6164 // CHECK11-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
6165 // CHECK11-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
6166 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
6167 // CHECK11-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
6168 // CHECK11-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
6169 // CHECK11-NEXT:    ret void
6170 //
6171 //
6172 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
6173 // CHECK11-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
6174 // CHECK11-NEXT:  entry:
6175 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6176 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6177 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6178 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6179 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6180 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6181 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6182 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6183 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6184 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6185 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6186 // CHECK11-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6187 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6188 // CHECK11-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6189 // CHECK11-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6190 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6191 // CHECK11-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6192 // CHECK11-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6193 // CHECK11-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6194 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6195 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6196 // CHECK11-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6197 // CHECK11-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6198 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6199 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6200 // CHECK11-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6201 // CHECK11-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6202 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6203 // CHECK11-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
6204 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
6205 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
6206 // CHECK11-NEXT:    ret void
6207 //
6208 //
6209 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
6210 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
6211 // CHECK11-NEXT:  entry:
6212 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6213 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6214 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6215 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6216 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6217 // CHECK11-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6218 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6219 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6220 // CHECK11-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6221 // CHECK11-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6222 // CHECK11-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6223 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6224 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6225 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6226 // CHECK11-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6227 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6228 // CHECK11-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6229 // CHECK11-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6230 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6231 // CHECK11-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6232 // CHECK11-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6233 // CHECK11-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6234 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6235 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6236 // CHECK11-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6237 // CHECK11-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6238 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6239 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6240 // CHECK11-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6241 // CHECK11-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6242 // CHECK11-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6243 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
6244 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6245 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
6246 // CHECK11-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
6247 // CHECK11-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
6248 // CHECK11-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
6249 // CHECK11-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
6250 // CHECK11-NEXT:    store float [[CONV6]], float* [[ARRAYIDX]], align 4
6251 // CHECK11-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
6252 // CHECK11-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
6253 // CHECK11-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
6254 // CHECK11-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
6255 // CHECK11-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
6256 // CHECK11-NEXT:    store float [[CONV10]], float* [[ARRAYIDX7]], align 4
6257 // CHECK11-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
6258 // CHECK11-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
6259 // CHECK11-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
6260 // CHECK11-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
6261 // CHECK11-NEXT:    store double [[ADD13]], double* [[ARRAYIDX12]], align 8
6262 // CHECK11-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
6263 // CHECK11-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
6264 // CHECK11-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
6265 // CHECK11-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
6266 // CHECK11-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
6267 // CHECK11-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
6268 // CHECK11-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
6269 // CHECK11-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
6270 // CHECK11-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
6271 // CHECK11-NEXT:    store i64 [[ADD17]], i64* [[X]], align 4
6272 // CHECK11-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
6273 // CHECK11-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
6274 // CHECK11-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
6275 // CHECK11-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
6276 // CHECK11-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
6277 // CHECK11-NEXT:    store i8 [[CONV20]], i8* [[Y]], align 4
6278 // CHECK11-NEXT:    ret void
6279 //
6280 //
6281 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
6282 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6283 // CHECK11-NEXT:  entry:
6284 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6285 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6286 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6287 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6288 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6289 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6290 // CHECK11-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6291 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6292 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6293 // CHECK11-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6294 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6295 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6296 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6297 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6298 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6299 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6300 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6301 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
6302 // CHECK11-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6303 // CHECK11-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
6304 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6305 // CHECK11-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
6306 // CHECK11-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6307 // CHECK11-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
6308 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6309 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
6310 // CHECK11-NEXT:    ret void
6311 //
6312 //
6313 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
6314 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6315 // CHECK11-NEXT:  entry:
6316 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6317 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6318 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6319 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6320 // CHECK11-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6321 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6322 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6323 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6324 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6325 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6326 // CHECK11-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6327 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6328 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6329 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6330 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6331 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6332 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6333 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6334 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
6335 // CHECK11-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
6336 // CHECK11-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
6337 // CHECK11-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6338 // CHECK11-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
6339 // CHECK11-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
6340 // CHECK11-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
6341 // CHECK11-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
6342 // CHECK11-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
6343 // CHECK11-NEXT:    store i8 [[CONV7]], i8* [[CONV1]], align 4
6344 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
6345 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6346 // CHECK11-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
6347 // CHECK11-NEXT:    store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
6348 // CHECK11-NEXT:    ret void
6349 //
6350 //
6351 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
6352 // CHECK11-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
6353 // CHECK11-NEXT:  entry:
6354 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6355 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6356 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6357 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6358 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6359 // CHECK11-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6360 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6361 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6362 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6363 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6364 // CHECK11-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6365 // CHECK11-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6366 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6367 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6368 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6369 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
6370 // CHECK11-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6371 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6372 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
6373 // CHECK11-NEXT:    ret void
6374 //
6375 //
6376 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..5
6377 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
6378 // CHECK11-NEXT:  entry:
6379 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6380 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6381 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6382 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6383 // CHECK11-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6384 // CHECK11-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6385 // CHECK11-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6386 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6387 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6388 // CHECK11-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6389 // CHECK11-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6390 // CHECK11-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6391 // CHECK11-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6392 // CHECK11-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6393 // CHECK11-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6394 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6395 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6396 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6397 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
6398 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
6399 // CHECK11-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6400 // CHECK11-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6401 // CHECK11-NEXT:    store double [[ADD]], double* [[A]], align 4
6402 // CHECK11-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6403 // CHECK11-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
6404 // CHECK11-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
6405 // CHECK11-NEXT:    store double [[INC]], double* [[A3]], align 4
6406 // CHECK11-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
6407 // CHECK11-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
6408 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
6409 // CHECK11-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6410 // CHECK11-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
6411 // CHECK11-NEXT:    ret void
6412 //
6413 //
6414 // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
6415 // CHECK11-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6416 // CHECK11-NEXT:  entry:
6417 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6418 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6419 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6420 // CHECK11-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6421 // CHECK11-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6422 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6423 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6424 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6425 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6426 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6427 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6428 // CHECK11-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6429 // CHECK11-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6430 // CHECK11-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
6431 // CHECK11-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6432 // CHECK11-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
6433 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6434 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
6435 // CHECK11-NEXT:    ret void
6436 //
6437 //
6438 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..6
6439 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6440 // CHECK11-NEXT:  entry:
6441 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6442 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6443 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6444 // CHECK11-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6445 // CHECK11-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6446 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6447 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6448 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6449 // CHECK11-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6450 // CHECK11-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6451 // CHECK11-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6452 // CHECK11-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6453 // CHECK11-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6454 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6455 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6456 // CHECK11-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
6457 // CHECK11-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
6458 // CHECK11-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
6459 // CHECK11-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
6460 // CHECK11-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
6461 // CHECK11-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
6462 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6463 // CHECK11-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
6464 // CHECK11-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
6465 // CHECK11-NEXT:    ret void
6466 //
6467 //
6468 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
6469 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
6470 // CHECK12-NEXT:  entry:
6471 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
6472 // CHECK12-NEXT:    ret void
6473 //
6474 //
6475 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
6476 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
6477 // CHECK12-NEXT:  entry:
6478 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6479 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6480 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6481 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6482 // CHECK12-NEXT:    ret void
6483 //
6484 //
6485 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
6486 // CHECK12-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
6487 // CHECK12-NEXT:  entry:
6488 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6489 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6490 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6491 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6492 // CHECK12-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
6493 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6494 // CHECK12-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
6495 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6496 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
6497 // CHECK12-NEXT:    ret void
6498 //
6499 //
6500 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
6501 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6502 // CHECK12-NEXT:  entry:
6503 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6504 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6505 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6506 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6507 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6508 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6509 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6510 // CHECK12-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
6511 // CHECK12-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
6512 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
6513 // CHECK12-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
6514 // CHECK12-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 4
6515 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
6516 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
6517 // CHECK12-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
6518 // CHECK12-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
6519 // CHECK12-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
6520 // CHECK12:       .cancel.exit:
6521 // CHECK12-NEXT:    br label [[DOTCANCEL_CONTINUE]]
6522 // CHECK12:       .cancel.continue:
6523 // CHECK12-NEXT:    ret void
6524 //
6525 //
6526 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
6527 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6528 // CHECK12-NEXT:  entry:
6529 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6530 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6531 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6532 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6533 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6534 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6535 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6536 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6537 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
6538 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
6539 // CHECK12-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
6540 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6541 // CHECK12-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
6542 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6543 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
6544 // CHECK12-NEXT:    ret void
6545 //
6546 //
6547 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2
6548 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
6549 // CHECK12-NEXT:  entry:
6550 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6551 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6552 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6553 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6554 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6555 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6556 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6557 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6558 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6559 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
6560 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6561 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6562 // CHECK12-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
6563 // CHECK12-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
6564 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
6565 // CHECK12-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
6566 // CHECK12-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
6567 // CHECK12-NEXT:    ret void
6568 //
6569 //
6570 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
6571 // CHECK12-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
6572 // CHECK12-NEXT:  entry:
6573 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6574 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6575 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6576 // CHECK12-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6577 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6578 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6579 // CHECK12-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6580 // CHECK12-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6581 // CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6582 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6583 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6584 // CHECK12-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6585 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6586 // CHECK12-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6587 // CHECK12-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6588 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6589 // CHECK12-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6590 // CHECK12-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6591 // CHECK12-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6592 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6593 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6594 // CHECK12-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6595 // CHECK12-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6596 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6597 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6598 // CHECK12-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6599 // CHECK12-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6600 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6601 // CHECK12-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
6602 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
6603 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
6604 // CHECK12-NEXT:    ret void
6605 //
6606 //
6607 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
6608 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
6609 // CHECK12-NEXT:  entry:
6610 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6611 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6612 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6613 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
6614 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6615 // CHECK12-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
6616 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
6617 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6618 // CHECK12-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
6619 // CHECK12-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
6620 // CHECK12-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
6621 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6622 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6623 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6624 // CHECK12-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
6625 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6626 // CHECK12-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
6627 // CHECK12-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
6628 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6629 // CHECK12-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
6630 // CHECK12-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
6631 // CHECK12-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
6632 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
6633 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6634 // CHECK12-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
6635 // CHECK12-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
6636 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6637 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
6638 // CHECK12-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
6639 // CHECK12-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
6640 // CHECK12-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
6641 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
6642 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6643 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
6644 // CHECK12-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
6645 // CHECK12-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
6646 // CHECK12-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
6647 // CHECK12-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
6648 // CHECK12-NEXT:    store float [[CONV6]], float* [[ARRAYIDX]], align 4
6649 // CHECK12-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
6650 // CHECK12-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
6651 // CHECK12-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
6652 // CHECK12-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
6653 // CHECK12-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
6654 // CHECK12-NEXT:    store float [[CONV10]], float* [[ARRAYIDX7]], align 4
6655 // CHECK12-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
6656 // CHECK12-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
6657 // CHECK12-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
6658 // CHECK12-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
6659 // CHECK12-NEXT:    store double [[ADD13]], double* [[ARRAYIDX12]], align 8
6660 // CHECK12-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
6661 // CHECK12-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
6662 // CHECK12-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
6663 // CHECK12-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
6664 // CHECK12-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
6665 // CHECK12-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
6666 // CHECK12-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
6667 // CHECK12-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
6668 // CHECK12-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
6669 // CHECK12-NEXT:    store i64 [[ADD17]], i64* [[X]], align 4
6670 // CHECK12-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
6671 // CHECK12-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
6672 // CHECK12-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
6673 // CHECK12-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
6674 // CHECK12-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
6675 // CHECK12-NEXT:    store i8 [[CONV20]], i8* [[Y]], align 4
6676 // CHECK12-NEXT:    ret void
6677 //
6678 //
6679 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
6680 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6681 // CHECK12-NEXT:  entry:
6682 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6683 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6684 // CHECK12-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6685 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6686 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6687 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6688 // CHECK12-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
6689 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6690 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6691 // CHECK12-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6692 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6693 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6694 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6695 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6696 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6697 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6698 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6699 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
6700 // CHECK12-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6701 // CHECK12-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
6702 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6703 // CHECK12-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
6704 // CHECK12-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
6705 // CHECK12-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
6706 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
6707 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
6708 // CHECK12-NEXT:    ret void
6709 //
6710 //
6711 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
6712 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6713 // CHECK12-NEXT:  entry:
6714 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6715 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6716 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6717 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6718 // CHECK12-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
6719 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6720 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6721 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6722 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6723 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6724 // CHECK12-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
6725 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6726 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6727 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
6728 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6729 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6730 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6731 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6732 // CHECK12-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
6733 // CHECK12-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
6734 // CHECK12-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
6735 // CHECK12-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
6736 // CHECK12-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
6737 // CHECK12-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
6738 // CHECK12-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
6739 // CHECK12-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
6740 // CHECK12-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
6741 // CHECK12-NEXT:    store i8 [[CONV7]], i8* [[CONV1]], align 4
6742 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
6743 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6744 // CHECK12-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
6745 // CHECK12-NEXT:    store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
6746 // CHECK12-NEXT:    ret void
6747 //
6748 //
6749 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
6750 // CHECK12-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
6751 // CHECK12-NEXT:  entry:
6752 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6753 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6754 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6755 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6756 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6757 // CHECK12-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
6758 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6759 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6760 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6761 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6762 // CHECK12-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6763 // CHECK12-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6764 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6765 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6766 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6767 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
6768 // CHECK12-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
6769 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
6770 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
6771 // CHECK12-NEXT:    ret void
6772 //
6773 //
6774 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..5
6775 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
6776 // CHECK12-NEXT:  entry:
6777 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6778 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6779 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
6780 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
6781 // CHECK12-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
6782 // CHECK12-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
6783 // CHECK12-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
6784 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6785 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6786 // CHECK12-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
6787 // CHECK12-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
6788 // CHECK12-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
6789 // CHECK12-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
6790 // CHECK12-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
6791 // CHECK12-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
6792 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
6793 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
6794 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
6795 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
6796 // CHECK12-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
6797 // CHECK12-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
6798 // CHECK12-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
6799 // CHECK12-NEXT:    store double [[ADD]], double* [[A]], align 4
6800 // CHECK12-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
6801 // CHECK12-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
6802 // CHECK12-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
6803 // CHECK12-NEXT:    store double [[INC]], double* [[A3]], align 4
6804 // CHECK12-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
6805 // CHECK12-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
6806 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
6807 // CHECK12-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
6808 // CHECK12-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
6809 // CHECK12-NEXT:    ret void
6810 //
6811 //
6812 // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
6813 // CHECK12-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6814 // CHECK12-NEXT:  entry:
6815 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6816 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6817 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6818 // CHECK12-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
6819 // CHECK12-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
6820 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6821 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6822 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6823 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6824 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6825 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6826 // CHECK12-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
6827 // CHECK12-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
6828 // CHECK12-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
6829 // CHECK12-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
6830 // CHECK12-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
6831 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
6832 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
6833 // CHECK12-NEXT:    ret void
6834 //
6835 //
6836 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..6
6837 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
6838 // CHECK12-NEXT:  entry:
6839 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
6840 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
6841 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
6842 // CHECK12-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
6843 // CHECK12-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
6844 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
6845 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
6846 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
6847 // CHECK12-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
6848 // CHECK12-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
6849 // CHECK12-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
6850 // CHECK12-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
6851 // CHECK12-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
6852 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
6853 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
6854 // CHECK12-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
6855 // CHECK12-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
6856 // CHECK12-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
6857 // CHECK12-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
6858 // CHECK12-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
6859 // CHECK12-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
6860 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
6861 // CHECK12-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
6862 // CHECK12-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
6863 // CHECK12-NEXT:    ret void
6864 //
6865 //
6866 // CHECK13-LABEL: define {{[^@]+}}@_Z3fooi
6867 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
6868 // CHECK13-NEXT:  entry:
6869 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6870 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
6871 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
6872 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
6873 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
6874 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
6875 // CHECK13-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
6876 // CHECK13-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
6877 // CHECK13-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
6878 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6879 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
6880 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
6881 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6882 // CHECK13-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
6883 // CHECK13-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
6884 // CHECK13-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
6885 // CHECK13-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
6886 // CHECK13-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
6887 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
6888 // CHECK13-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
6889 // CHECK13-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
6890 // CHECK13-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
6891 // CHECK13-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
6892 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
6893 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
6894 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6895 // CHECK13-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
6896 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
6897 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
6898 // CHECK13-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
6899 // CHECK13-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
6900 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
6901 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
6902 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6903 // CHECK13-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
6904 // CHECK13-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
6905 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
6906 // CHECK13-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
6907 // CHECK13-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
6908 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A]], align 4
6909 // CHECK13-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
6910 // CHECK13-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
6911 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
6912 // CHECK13-NEXT:    [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4
6913 // CHECK13-NEXT:    [[CONV9:%.*]] = fpext float [[TMP11]] to double
6914 // CHECK13-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
6915 // CHECK13-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
6916 // CHECK13-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
6917 // CHECK13-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
6918 // CHECK13-NEXT:    [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4
6919 // CHECK13-NEXT:    [[CONV13:%.*]] = fpext float [[TMP12]] to double
6920 // CHECK13-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
6921 // CHECK13-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
6922 // CHECK13-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
6923 // CHECK13-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
6924 // CHECK13-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
6925 // CHECK13-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8
6926 // CHECK13-NEXT:    [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00
6927 // CHECK13-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
6928 // CHECK13-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]]
6929 // CHECK13-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]]
6930 // CHECK13-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
6931 // CHECK13-NEXT:    [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8
6932 // CHECK13-NEXT:    [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00
6933 // CHECK13-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
6934 // CHECK13-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
6935 // CHECK13-NEXT:    [[TMP16:%.*]] = load i64, i64* [[X]], align 8
6936 // CHECK13-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1
6937 // CHECK13-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
6938 // CHECK13-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
6939 // CHECK13-NEXT:    [[TMP17:%.*]] = load i8, i8* [[Y]], align 8
6940 // CHECK13-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP17]] to i32
6941 // CHECK13-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
6942 // CHECK13-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
6943 // CHECK13-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
6944 // CHECK13-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
6945 // CHECK13-NEXT:    [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
6946 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP19]])
6947 // CHECK13-NEXT:    ret i32 [[TMP18]]
6948 //
6949 //
6950 // CHECK13-LABEL: define {{[^@]+}}@_Z3bari
6951 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
6952 // CHECK13-NEXT:  entry:
6953 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6954 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
6955 // CHECK13-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
6956 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6957 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
6958 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6959 // CHECK13-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
6960 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
6961 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
6962 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
6963 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
6964 // CHECK13-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
6965 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
6966 // CHECK13-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
6967 // CHECK13-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
6968 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
6969 // CHECK13-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
6970 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
6971 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
6972 // CHECK13-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
6973 // CHECK13-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
6974 // CHECK13-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
6975 // CHECK13-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
6976 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
6977 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
6978 // CHECK13-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
6979 // CHECK13-NEXT:    ret i32 [[TMP8]]
6980 //
6981 //
6982 // CHECK13-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
6983 // CHECK13-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
6984 // CHECK13-NEXT:  entry:
6985 // CHECK13-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
6986 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
6987 // CHECK13-NEXT:    [[B:%.*]] = alloca i32, align 4
6988 // CHECK13-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
6989 // CHECK13-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
6990 // CHECK13-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
6991 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
6992 // CHECK13-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
6993 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
6994 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
6995 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
6996 // CHECK13-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
6997 // CHECK13-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
6998 // CHECK13-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
6999 // CHECK13-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7000 // CHECK13-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
7001 // CHECK13-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
7002 // CHECK13-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7003 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
7004 // CHECK13-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
7005 // CHECK13-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
7006 // CHECK13-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7007 // CHECK13-NEXT:    store double [[ADD2]], double* [[A]], align 8
7008 // CHECK13-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7009 // CHECK13-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 8
7010 // CHECK13-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
7011 // CHECK13-NEXT:    store double [[INC]], double* [[A3]], align 8
7012 // CHECK13-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
7013 // CHECK13-NEXT:    [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
7014 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
7015 // CHECK13-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
7016 // CHECK13-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7017 // CHECK13-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
7018 // CHECK13-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
7019 // CHECK13-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
7020 // CHECK13-NEXT:    [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
7021 // CHECK13-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
7022 // CHECK13-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4
7023 // CHECK13-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
7024 // CHECK13-NEXT:    [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7025 // CHECK13-NEXT:    call void @llvm.stackrestore(i8* [[TMP11]])
7026 // CHECK13-NEXT:    ret i32 [[ADD9]]
7027 //
7028 //
7029 // CHECK13-LABEL: define {{[^@]+}}@_ZL7fstatici
7030 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7031 // CHECK13-NEXT:  entry:
7032 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7033 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
7034 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
7035 // CHECK13-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7036 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7037 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7038 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
7039 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
7040 // CHECK13-NEXT:    store i8 0, i8* [[AAA]], align 1
7041 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7042 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7043 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7044 // CHECK13-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
7045 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7046 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7047 // CHECK13-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7048 // CHECK13-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7049 // CHECK13-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
7050 // CHECK13-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
7051 // CHECK13-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7052 // CHECK13-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
7053 // CHECK13-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
7054 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7055 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7056 // CHECK13-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
7057 // CHECK13-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7058 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
7059 // CHECK13-NEXT:    ret i32 [[TMP4]]
7060 //
7061 //
7062 // CHECK13-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7063 // CHECK13-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
7064 // CHECK13-NEXT:  entry:
7065 // CHECK13-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7066 // CHECK13-NEXT:    [[A:%.*]] = alloca i32, align 4
7067 // CHECK13-NEXT:    [[AA:%.*]] = alloca i16, align 2
7068 // CHECK13-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7069 // CHECK13-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7070 // CHECK13-NEXT:    store i32 0, i32* [[A]], align 4
7071 // CHECK13-NEXT:    store i16 0, i16* [[AA]], align 2
7072 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7073 // CHECK13-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7074 // CHECK13-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7075 // CHECK13-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
7076 // CHECK13-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7077 // CHECK13-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7078 // CHECK13-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7079 // CHECK13-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7080 // CHECK13-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7081 // CHECK13-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7082 // CHECK13-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
7083 // CHECK13-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
7084 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7085 // CHECK13-NEXT:    ret i32 [[TMP3]]
7086 //
7087 //
7088 // CHECK14-LABEL: define {{[^@]+}}@_Z3fooi
7089 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7090 // CHECK14-NEXT:  entry:
7091 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7092 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
7093 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
7094 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7095 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7096 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7097 // CHECK14-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7098 // CHECK14-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
7099 // CHECK14-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
7100 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7101 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
7102 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
7103 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7104 // CHECK14-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
7105 // CHECK14-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
7106 // CHECK14-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
7107 // CHECK14-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
7108 // CHECK14-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
7109 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
7110 // CHECK14-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
7111 // CHECK14-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
7112 // CHECK14-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
7113 // CHECK14-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
7114 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7115 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
7116 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7117 // CHECK14-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
7118 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
7119 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
7120 // CHECK14-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
7121 // CHECK14-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
7122 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7123 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
7124 // CHECK14-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7125 // CHECK14-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
7126 // CHECK14-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
7127 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
7128 // CHECK14-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
7129 // CHECK14-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
7130 // CHECK14-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A]], align 4
7131 // CHECK14-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
7132 // CHECK14-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
7133 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
7134 // CHECK14-NEXT:    [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4
7135 // CHECK14-NEXT:    [[CONV9:%.*]] = fpext float [[TMP11]] to double
7136 // CHECK14-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
7137 // CHECK14-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
7138 // CHECK14-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
7139 // CHECK14-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
7140 // CHECK14-NEXT:    [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4
7141 // CHECK14-NEXT:    [[CONV13:%.*]] = fpext float [[TMP12]] to double
7142 // CHECK14-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
7143 // CHECK14-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
7144 // CHECK14-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
7145 // CHECK14-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
7146 // CHECK14-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
7147 // CHECK14-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8
7148 // CHECK14-NEXT:    [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00
7149 // CHECK14-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
7150 // CHECK14-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]]
7151 // CHECK14-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]]
7152 // CHECK14-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
7153 // CHECK14-NEXT:    [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8
7154 // CHECK14-NEXT:    [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00
7155 // CHECK14-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
7156 // CHECK14-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
7157 // CHECK14-NEXT:    [[TMP16:%.*]] = load i64, i64* [[X]], align 8
7158 // CHECK14-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1
7159 // CHECK14-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
7160 // CHECK14-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
7161 // CHECK14-NEXT:    [[TMP17:%.*]] = load i8, i8* [[Y]], align 8
7162 // CHECK14-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP17]] to i32
7163 // CHECK14-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
7164 // CHECK14-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
7165 // CHECK14-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
7166 // CHECK14-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
7167 // CHECK14-NEXT:    [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7168 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP19]])
7169 // CHECK14-NEXT:    ret i32 [[TMP18]]
7170 //
7171 //
7172 // CHECK14-LABEL: define {{[^@]+}}@_Z3bari
7173 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7174 // CHECK14-NEXT:  entry:
7175 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7176 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
7177 // CHECK14-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
7178 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7179 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
7180 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7181 // CHECK14-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
7182 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7183 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7184 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7185 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7186 // CHECK14-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
7187 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7188 // CHECK14-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7189 // CHECK14-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7190 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7191 // CHECK14-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
7192 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7193 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7194 // CHECK14-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7195 // CHECK14-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7196 // CHECK14-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
7197 // CHECK14-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7198 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7199 // CHECK14-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7200 // CHECK14-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7201 // CHECK14-NEXT:    ret i32 [[TMP8]]
7202 //
7203 //
7204 // CHECK14-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7205 // CHECK14-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7206 // CHECK14-NEXT:  entry:
7207 // CHECK14-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
7208 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7209 // CHECK14-NEXT:    [[B:%.*]] = alloca i32, align 4
7210 // CHECK14-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7211 // CHECK14-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7212 // CHECK14-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
7213 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7214 // CHECK14-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
7215 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7216 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7217 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
7218 // CHECK14-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7219 // CHECK14-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7220 // CHECK14-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
7221 // CHECK14-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7222 // CHECK14-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
7223 // CHECK14-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
7224 // CHECK14-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7225 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
7226 // CHECK14-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
7227 // CHECK14-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
7228 // CHECK14-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7229 // CHECK14-NEXT:    store double [[ADD2]], double* [[A]], align 8
7230 // CHECK14-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7231 // CHECK14-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 8
7232 // CHECK14-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
7233 // CHECK14-NEXT:    store double [[INC]], double* [[A3]], align 8
7234 // CHECK14-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
7235 // CHECK14-NEXT:    [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
7236 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
7237 // CHECK14-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
7238 // CHECK14-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7239 // CHECK14-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
7240 // CHECK14-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
7241 // CHECK14-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
7242 // CHECK14-NEXT:    [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
7243 // CHECK14-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
7244 // CHECK14-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4
7245 // CHECK14-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
7246 // CHECK14-NEXT:    [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7247 // CHECK14-NEXT:    call void @llvm.stackrestore(i8* [[TMP11]])
7248 // CHECK14-NEXT:    ret i32 [[ADD9]]
7249 //
7250 //
7251 // CHECK14-LABEL: define {{[^@]+}}@_ZL7fstatici
7252 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
7253 // CHECK14-NEXT:  entry:
7254 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7255 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
7256 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
7257 // CHECK14-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7258 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7259 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7260 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
7261 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
7262 // CHECK14-NEXT:    store i8 0, i8* [[AAA]], align 1
7263 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7264 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7265 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7266 // CHECK14-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
7267 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7268 // CHECK14-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7269 // CHECK14-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7270 // CHECK14-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7271 // CHECK14-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
7272 // CHECK14-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
7273 // CHECK14-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7274 // CHECK14-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
7275 // CHECK14-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
7276 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7277 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7278 // CHECK14-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
7279 // CHECK14-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7280 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
7281 // CHECK14-NEXT:    ret i32 [[TMP4]]
7282 //
7283 //
7284 // CHECK14-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7285 // CHECK14-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
7286 // CHECK14-NEXT:  entry:
7287 // CHECK14-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7288 // CHECK14-NEXT:    [[A:%.*]] = alloca i32, align 4
7289 // CHECK14-NEXT:    [[AA:%.*]] = alloca i16, align 2
7290 // CHECK14-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7291 // CHECK14-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7292 // CHECK14-NEXT:    store i32 0, i32* [[A]], align 4
7293 // CHECK14-NEXT:    store i16 0, i16* [[AA]], align 2
7294 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7295 // CHECK14-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7296 // CHECK14-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7297 // CHECK14-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
7298 // CHECK14-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7299 // CHECK14-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7300 // CHECK14-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7301 // CHECK14-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7302 // CHECK14-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
7303 // CHECK14-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7304 // CHECK14-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
7305 // CHECK14-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
7306 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7307 // CHECK14-NEXT:    ret i32 [[TMP3]]
7308 //
7309 //
7310 // CHECK15-LABEL: define {{[^@]+}}@_Z3fooi
7311 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7312 // CHECK15-NEXT:  entry:
7313 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7314 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
7315 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
7316 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7317 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
7318 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7319 // CHECK15-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7320 // CHECK15-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
7321 // CHECK15-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
7322 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7323 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
7324 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
7325 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7326 // CHECK15-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
7327 // CHECK15-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
7328 // CHECK15-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
7329 // CHECK15-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
7330 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7331 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
7332 // CHECK15-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
7333 // CHECK15-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
7334 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
7335 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
7336 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7337 // CHECK15-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2
7338 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
7339 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
7340 // CHECK15-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
7341 // CHECK15-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
7342 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7343 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
7344 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7345 // CHECK15-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
7346 // CHECK15-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP7]] to i32
7347 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
7348 // CHECK15-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
7349 // CHECK15-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
7350 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7351 // CHECK15-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
7352 // CHECK15-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
7353 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
7354 // CHECK15-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
7355 // CHECK15-NEXT:    [[CONV9:%.*]] = fpext float [[TMP9]] to double
7356 // CHECK15-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
7357 // CHECK15-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
7358 // CHECK15-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
7359 // CHECK15-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
7360 // CHECK15-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4
7361 // CHECK15-NEXT:    [[CONV13:%.*]] = fpext float [[TMP10]] to double
7362 // CHECK15-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
7363 // CHECK15-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
7364 // CHECK15-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
7365 // CHECK15-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
7366 // CHECK15-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2
7367 // CHECK15-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8
7368 // CHECK15-NEXT:    [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00
7369 // CHECK15-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
7370 // CHECK15-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
7371 // CHECK15-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]]
7372 // CHECK15-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3
7373 // CHECK15-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8
7374 // CHECK15-NEXT:    [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00
7375 // CHECK15-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
7376 // CHECK15-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
7377 // CHECK15-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
7378 // CHECK15-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1
7379 // CHECK15-NEXT:    store i64 [[ADD22]], i64* [[X]], align 4
7380 // CHECK15-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
7381 // CHECK15-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
7382 // CHECK15-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP15]] to i32
7383 // CHECK15-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
7384 // CHECK15-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
7385 // CHECK15-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 4
7386 // CHECK15-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
7387 // CHECK15-NEXT:    [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
7388 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP17]])
7389 // CHECK15-NEXT:    ret i32 [[TMP16]]
7390 //
7391 //
7392 // CHECK15-LABEL: define {{[^@]+}}@_Z3bari
7393 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7394 // CHECK15-NEXT:  entry:
7395 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7396 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
7397 // CHECK15-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
7398 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7399 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
7400 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7401 // CHECK15-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
7402 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7403 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7404 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7405 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7406 // CHECK15-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
7407 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7408 // CHECK15-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7409 // CHECK15-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7410 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7411 // CHECK15-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
7412 // CHECK15-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7413 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7414 // CHECK15-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7415 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7416 // CHECK15-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
7417 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7418 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7419 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7420 // CHECK15-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7421 // CHECK15-NEXT:    ret i32 [[TMP8]]
7422 //
7423 //
7424 // CHECK15-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7425 // CHECK15-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7426 // CHECK15-NEXT:  entry:
7427 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7428 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7429 // CHECK15-NEXT:    [[B:%.*]] = alloca i32, align 4
7430 // CHECK15-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
7431 // CHECK15-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7432 // CHECK15-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7433 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7434 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7435 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7436 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7437 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
7438 // CHECK15-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7439 // CHECK15-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
7440 // CHECK15-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
7441 // CHECK15-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
7442 // CHECK15-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
7443 // CHECK15-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
7444 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
7445 // CHECK15-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
7446 // CHECK15-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
7447 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7448 // CHECK15-NEXT:    store double [[ADD2]], double* [[A]], align 4
7449 // CHECK15-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7450 // CHECK15-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
7451 // CHECK15-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
7452 // CHECK15-NEXT:    store double [[INC]], double* [[A3]], align 4
7453 // CHECK15-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
7454 // CHECK15-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
7455 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
7456 // CHECK15-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
7457 // CHECK15-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7458 // CHECK15-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
7459 // CHECK15-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
7460 // CHECK15-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
7461 // CHECK15-NEXT:    [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
7462 // CHECK15-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
7463 // CHECK15-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4
7464 // CHECK15-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
7465 // CHECK15-NEXT:    [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
7466 // CHECK15-NEXT:    call void @llvm.stackrestore(i8* [[TMP10]])
7467 // CHECK15-NEXT:    ret i32 [[ADD9]]
7468 //
7469 //
7470 // CHECK15-LABEL: define {{[^@]+}}@_ZL7fstatici
7471 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7472 // CHECK15-NEXT:  entry:
7473 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7474 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
7475 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
7476 // CHECK15-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7477 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7478 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7479 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
7480 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
7481 // CHECK15-NEXT:    store i8 0, i8* [[AAA]], align 1
7482 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7483 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7484 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7485 // CHECK15-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
7486 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7487 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7488 // CHECK15-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7489 // CHECK15-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7490 // CHECK15-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
7491 // CHECK15-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
7492 // CHECK15-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7493 // CHECK15-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
7494 // CHECK15-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
7495 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
7496 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7497 // CHECK15-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
7498 // CHECK15-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7499 // CHECK15-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
7500 // CHECK15-NEXT:    ret i32 [[TMP4]]
7501 //
7502 //
7503 // CHECK15-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7504 // CHECK15-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
7505 // CHECK15-NEXT:  entry:
7506 // CHECK15-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7507 // CHECK15-NEXT:    [[A:%.*]] = alloca i32, align 4
7508 // CHECK15-NEXT:    [[AA:%.*]] = alloca i16, align 2
7509 // CHECK15-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7510 // CHECK15-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7511 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
7512 // CHECK15-NEXT:    store i16 0, i16* [[AA]], align 2
7513 // CHECK15-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7514 // CHECK15-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7515 // CHECK15-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7516 // CHECK15-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
7517 // CHECK15-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7518 // CHECK15-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7519 // CHECK15-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7520 // CHECK15-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7521 // CHECK15-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
7522 // CHECK15-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7523 // CHECK15-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
7524 // CHECK15-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
7525 // CHECK15-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7526 // CHECK15-NEXT:    ret i32 [[TMP3]]
7527 //
7528 //
7529 // CHECK16-LABEL: define {{[^@]+}}@_Z3fooi
7530 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7531 // CHECK16-NEXT:  entry:
7532 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7533 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
7534 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
7535 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7536 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
7537 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7538 // CHECK16-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7539 // CHECK16-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
7540 // CHECK16-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
7541 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7542 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
7543 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
7544 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7545 // CHECK16-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
7546 // CHECK16-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
7547 // CHECK16-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
7548 // CHECK16-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
7549 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7550 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
7551 // CHECK16-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
7552 // CHECK16-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
7553 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
7554 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
7555 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7556 // CHECK16-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2
7557 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
7558 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
7559 // CHECK16-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
7560 // CHECK16-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
7561 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
7562 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
7563 // CHECK16-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7564 // CHECK16-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
7565 // CHECK16-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP7]] to i32
7566 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
7567 // CHECK16-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
7568 // CHECK16-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
7569 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7570 // CHECK16-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
7571 // CHECK16-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
7572 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
7573 // CHECK16-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
7574 // CHECK16-NEXT:    [[CONV9:%.*]] = fpext float [[TMP9]] to double
7575 // CHECK16-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
7576 // CHECK16-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
7577 // CHECK16-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
7578 // CHECK16-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
7579 // CHECK16-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4
7580 // CHECK16-NEXT:    [[CONV13:%.*]] = fpext float [[TMP10]] to double
7581 // CHECK16-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
7582 // CHECK16-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
7583 // CHECK16-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
7584 // CHECK16-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
7585 // CHECK16-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2
7586 // CHECK16-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8
7587 // CHECK16-NEXT:    [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00
7588 // CHECK16-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
7589 // CHECK16-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
7590 // CHECK16-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]]
7591 // CHECK16-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3
7592 // CHECK16-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8
7593 // CHECK16-NEXT:    [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00
7594 // CHECK16-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
7595 // CHECK16-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
7596 // CHECK16-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
7597 // CHECK16-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1
7598 // CHECK16-NEXT:    store i64 [[ADD22]], i64* [[X]], align 4
7599 // CHECK16-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
7600 // CHECK16-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
7601 // CHECK16-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP15]] to i32
7602 // CHECK16-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
7603 // CHECK16-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
7604 // CHECK16-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 4
7605 // CHECK16-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
7606 // CHECK16-NEXT:    [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
7607 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP17]])
7608 // CHECK16-NEXT:    ret i32 [[TMP16]]
7609 //
7610 //
7611 // CHECK16-LABEL: define {{[^@]+}}@_Z3bari
7612 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7613 // CHECK16-NEXT:  entry:
7614 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7615 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
7616 // CHECK16-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
7617 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7618 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
7619 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7620 // CHECK16-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
7621 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
7622 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
7623 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7624 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
7625 // CHECK16-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
7626 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7627 // CHECK16-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
7628 // CHECK16-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
7629 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7630 // CHECK16-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
7631 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
7632 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
7633 // CHECK16-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
7634 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
7635 // CHECK16-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
7636 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
7637 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
7638 // CHECK16-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
7639 // CHECK16-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
7640 // CHECK16-NEXT:    ret i32 [[TMP8]]
7641 //
7642 //
7643 // CHECK16-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
7644 // CHECK16-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
7645 // CHECK16-NEXT:  entry:
7646 // CHECK16-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
7647 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7648 // CHECK16-NEXT:    [[B:%.*]] = alloca i32, align 4
7649 // CHECK16-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
7650 // CHECK16-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
7651 // CHECK16-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
7652 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7653 // CHECK16-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
7654 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
7655 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7656 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
7657 // CHECK16-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7658 // CHECK16-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
7659 // CHECK16-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
7660 // CHECK16-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
7661 // CHECK16-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
7662 // CHECK16-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
7663 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
7664 // CHECK16-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
7665 // CHECK16-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
7666 // CHECK16-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
7667 // CHECK16-NEXT:    store double [[ADD2]], double* [[A]], align 4
7668 // CHECK16-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
7669 // CHECK16-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
7670 // CHECK16-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
7671 // CHECK16-NEXT:    store double [[INC]], double* [[A3]], align 4
7672 // CHECK16-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
7673 // CHECK16-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
7674 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
7675 // CHECK16-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
7676 // CHECK16-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
7677 // CHECK16-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
7678 // CHECK16-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
7679 // CHECK16-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
7680 // CHECK16-NEXT:    [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
7681 // CHECK16-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
7682 // CHECK16-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4
7683 // CHECK16-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
7684 // CHECK16-NEXT:    [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
7685 // CHECK16-NEXT:    call void @llvm.stackrestore(i8* [[TMP10]])
7686 // CHECK16-NEXT:    ret i32 [[ADD9]]
7687 //
7688 //
7689 // CHECK16-LABEL: define {{[^@]+}}@_ZL7fstatici
7690 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
7691 // CHECK16-NEXT:  entry:
7692 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7693 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
7694 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
7695 // CHECK16-NEXT:    [[AAA:%.*]] = alloca i8, align 1
7696 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7697 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7698 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
7699 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
7700 // CHECK16-NEXT:    store i8 0, i8* [[AAA]], align 1
7701 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7702 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7703 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7704 // CHECK16-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
7705 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7706 // CHECK16-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7707 // CHECK16-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7708 // CHECK16-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7709 // CHECK16-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
7710 // CHECK16-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
7711 // CHECK16-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
7712 // CHECK16-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
7713 // CHECK16-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
7714 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
7715 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7716 // CHECK16-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
7717 // CHECK16-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
7718 // CHECK16-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
7719 // CHECK16-NEXT:    ret i32 [[TMP4]]
7720 //
7721 //
7722 // CHECK16-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
7723 // CHECK16-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
7724 // CHECK16-NEXT:  entry:
7725 // CHECK16-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7726 // CHECK16-NEXT:    [[A:%.*]] = alloca i32, align 4
7727 // CHECK16-NEXT:    [[AA:%.*]] = alloca i16, align 2
7728 // CHECK16-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
7729 // CHECK16-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7730 // CHECK16-NEXT:    store i32 0, i32* [[A]], align 4
7731 // CHECK16-NEXT:    store i16 0, i16* [[AA]], align 2
7732 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
7733 // CHECK16-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
7734 // CHECK16-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
7735 // CHECK16-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
7736 // CHECK16-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
7737 // CHECK16-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
7738 // CHECK16-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
7739 // CHECK16-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
7740 // CHECK16-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
7741 // CHECK16-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
7742 // CHECK16-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
7743 // CHECK16-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
7744 // CHECK16-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
7745 // CHECK16-NEXT:    ret i32 [[TMP3]]
7746 //
7747 //
7748 // CHECK17-LABEL: define {{[^@]+}}@_Z3fooi
7749 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
7750 // CHECK17-NEXT:  entry:
7751 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
7752 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
7753 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
7754 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
7755 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
7756 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
7757 // CHECK17-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
7758 // CHECK17-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
7759 // CHECK17-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
7760 // CHECK17-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
7761 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
7762 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
7763 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
7764 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
7765 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
7766 // CHECK17-NEXT:    [[A_CASTED3:%.*]] = alloca i64, align 8
7767 // CHECK17-NEXT:    [[AA_CASTED5:%.*]] = alloca i64, align 8
7768 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8
7769 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8
7770 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8
7771 // CHECK17-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
7772 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8
7773 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8
7774 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8
7775 // CHECK17-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
7776 // CHECK17-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
7777 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
7778 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
7779 // CHECK17-NEXT:    store i16 0, i16* [[AA]], align 2
7780 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
7781 // CHECK17-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
7782 // CHECK17-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
7783 // CHECK17-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
7784 // CHECK17-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
7785 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
7786 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
7787 // CHECK17-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
7788 // CHECK17-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
7789 // CHECK17-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
7790 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
7791 // CHECK17-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
7792 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
7793 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
7794 // CHECK17-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]])
7795 // CHECK17-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
7796 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
7797 // CHECK17-NEXT:    store i32 [[TMP11]], i32* [[CONV]], align 4
7798 // CHECK17-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
7799 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR3:[0-9]+]]
7800 // CHECK17-NEXT:    [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
7801 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
7802 // CHECK17-NEXT:    store i16 [[TMP13]], i16* [[CONV2]], align 2
7803 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
7804 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7805 // CHECK17-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
7806 // CHECK17-NEXT:    store i64 [[TMP14]], i64* [[TMP16]], align 8
7807 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7808 // CHECK17-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
7809 // CHECK17-NEXT:    store i64 [[TMP14]], i64* [[TMP18]], align 8
7810 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
7811 // CHECK17-NEXT:    store i8* null, i8** [[TMP19]], align 8
7812 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
7813 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
7814 // CHECK17-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
7815 // CHECK17-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
7816 // CHECK17-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
7817 // CHECK17:       omp_offload.failed:
7818 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR3]]
7819 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
7820 // CHECK17:       omp_offload.cont:
7821 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
7822 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32*
7823 // CHECK17-NEXT:    store i32 [[TMP24]], i32* [[CONV4]], align 4
7824 // CHECK17-NEXT:    [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8
7825 // CHECK17-NEXT:    [[TMP26:%.*]] = load i16, i16* [[AA]], align 2
7826 // CHECK17-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16*
7827 // CHECK17-NEXT:    store i16 [[TMP26]], i16* [[CONV6]], align 2
7828 // CHECK17-NEXT:    [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8
7829 // CHECK17-NEXT:    [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4
7830 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10
7831 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
7832 // CHECK17:       omp_if.then:
7833 // CHECK17-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
7834 // CHECK17-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
7835 // CHECK17-NEXT:    store i64 [[TMP25]], i64* [[TMP30]], align 8
7836 // CHECK17-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
7837 // CHECK17-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
7838 // CHECK17-NEXT:    store i64 [[TMP25]], i64* [[TMP32]], align 8
7839 // CHECK17-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
7840 // CHECK17-NEXT:    store i8* null, i8** [[TMP33]], align 8
7841 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1
7842 // CHECK17-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64*
7843 // CHECK17-NEXT:    store i64 [[TMP27]], i64* [[TMP35]], align 8
7844 // CHECK17-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1
7845 // CHECK17-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
7846 // CHECK17-NEXT:    store i64 [[TMP27]], i64* [[TMP37]], align 8
7847 // CHECK17-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1
7848 // CHECK17-NEXT:    store i8* null, i8** [[TMP38]], align 8
7849 // CHECK17-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
7850 // CHECK17-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
7851 // CHECK17-NEXT:    [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
7852 // CHECK17-NEXT:    [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
7853 // CHECK17-NEXT:    br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]]
7854 // CHECK17:       omp_offload.failed10:
7855 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]]
7856 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT11]]
7857 // CHECK17:       omp_offload.cont11:
7858 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
7859 // CHECK17:       omp_if.else:
7860 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]]
7861 // CHECK17-NEXT:    br label [[OMP_IF_END]]
7862 // CHECK17:       omp_if.end:
7863 // CHECK17-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4
7864 // CHECK17-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
7865 // CHECK17-NEXT:    store i32 [[TMP43]], i32* [[CONV13]], align 4
7866 // CHECK17-NEXT:    [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8
7867 // CHECK17-NEXT:    [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4
7868 // CHECK17-NEXT:    [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20
7869 // CHECK17-NEXT:    br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]]
7870 // CHECK17:       omp_if.then15:
7871 // CHECK17-NEXT:    [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4
7872 // CHECK17-NEXT:    [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]]
7873 // CHECK17-NEXT:    [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8
7874 // CHECK17-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
7875 // CHECK17-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64*
7876 // CHECK17-NEXT:    store i64 [[TMP44]], i64* [[TMP50]], align 8
7877 // CHECK17-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
7878 // CHECK17-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
7879 // CHECK17-NEXT:    store i64 [[TMP44]], i64* [[TMP52]], align 8
7880 // CHECK17-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
7881 // CHECK17-NEXT:    store i64 4, i64* [[TMP53]], align 8
7882 // CHECK17-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
7883 // CHECK17-NEXT:    store i8* null, i8** [[TMP54]], align 8
7884 // CHECK17-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
7885 // CHECK17-NEXT:    [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]**
7886 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8
7887 // CHECK17-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
7888 // CHECK17-NEXT:    [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]**
7889 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8
7890 // CHECK17-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
7891 // CHECK17-NEXT:    store i64 40, i64* [[TMP59]], align 8
7892 // CHECK17-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
7893 // CHECK17-NEXT:    store i8* null, i8** [[TMP60]], align 8
7894 // CHECK17-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2
7895 // CHECK17-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
7896 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP62]], align 8
7897 // CHECK17-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2
7898 // CHECK17-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
7899 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP64]], align 8
7900 // CHECK17-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
7901 // CHECK17-NEXT:    store i64 8, i64* [[TMP65]], align 8
7902 // CHECK17-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2
7903 // CHECK17-NEXT:    store i8* null, i8** [[TMP66]], align 8
7904 // CHECK17-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3
7905 // CHECK17-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float**
7906 // CHECK17-NEXT:    store float* [[VLA]], float** [[TMP68]], align 8
7907 // CHECK17-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3
7908 // CHECK17-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float**
7909 // CHECK17-NEXT:    store float* [[VLA]], float** [[TMP70]], align 8
7910 // CHECK17-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
7911 // CHECK17-NEXT:    store i64 [[TMP46]], i64* [[TMP71]], align 8
7912 // CHECK17-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3
7913 // CHECK17-NEXT:    store i8* null, i8** [[TMP72]], align 8
7914 // CHECK17-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4
7915 // CHECK17-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]**
7916 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8
7917 // CHECK17-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4
7918 // CHECK17-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]**
7919 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8
7920 // CHECK17-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
7921 // CHECK17-NEXT:    store i64 400, i64* [[TMP77]], align 8
7922 // CHECK17-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4
7923 // CHECK17-NEXT:    store i8* null, i8** [[TMP78]], align 8
7924 // CHECK17-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5
7925 // CHECK17-NEXT:    [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*
7926 // CHECK17-NEXT:    store i64 5, i64* [[TMP80]], align 8
7927 // CHECK17-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5
7928 // CHECK17-NEXT:    [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64*
7929 // CHECK17-NEXT:    store i64 5, i64* [[TMP82]], align 8
7930 // CHECK17-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
7931 // CHECK17-NEXT:    store i64 8, i64* [[TMP83]], align 8
7932 // CHECK17-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5
7933 // CHECK17-NEXT:    store i8* null, i8** [[TMP84]], align 8
7934 // CHECK17-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6
7935 // CHECK17-NEXT:    [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64*
7936 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP86]], align 8
7937 // CHECK17-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6
7938 // CHECK17-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64*
7939 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP88]], align 8
7940 // CHECK17-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
7941 // CHECK17-NEXT:    store i64 8, i64* [[TMP89]], align 8
7942 // CHECK17-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6
7943 // CHECK17-NEXT:    store i8* null, i8** [[TMP90]], align 8
7944 // CHECK17-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7
7945 // CHECK17-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double**
7946 // CHECK17-NEXT:    store double* [[VLA1]], double** [[TMP92]], align 8
7947 // CHECK17-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7
7948 // CHECK17-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double**
7949 // CHECK17-NEXT:    store double* [[VLA1]], double** [[TMP94]], align 8
7950 // CHECK17-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
7951 // CHECK17-NEXT:    store i64 [[TMP48]], i64* [[TMP95]], align 8
7952 // CHECK17-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7
7953 // CHECK17-NEXT:    store i8* null, i8** [[TMP96]], align 8
7954 // CHECK17-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8
7955 // CHECK17-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT**
7956 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8
7957 // CHECK17-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8
7958 // CHECK17-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT**
7959 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8
7960 // CHECK17-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
7961 // CHECK17-NEXT:    store i64 16, i64* [[TMP101]], align 8
7962 // CHECK17-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8
7963 // CHECK17-NEXT:    store i8* null, i8** [[TMP102]], align 8
7964 // CHECK17-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
7965 // CHECK17-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
7966 // CHECK17-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
7967 // CHECK17-NEXT:    [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
7968 // CHECK17-NEXT:    [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0
7969 // CHECK17-NEXT:    br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
7970 // CHECK17:       omp_offload.failed19:
7971 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
7972 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT20]]
7973 // CHECK17:       omp_offload.cont20:
7974 // CHECK17-NEXT:    br label [[OMP_IF_END22:%.*]]
7975 // CHECK17:       omp_if.else21:
7976 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
7977 // CHECK17-NEXT:    br label [[OMP_IF_END22]]
7978 // CHECK17:       omp_if.end22:
7979 // CHECK17-NEXT:    [[TMP108:%.*]] = load i32, i32* [[A]], align 4
7980 // CHECK17-NEXT:    [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
7981 // CHECK17-NEXT:    call void @llvm.stackrestore(i8* [[TMP109]])
7982 // CHECK17-NEXT:    ret i32 [[TMP108]]
7983 //
7984 //
7985 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
7986 // CHECK17-SAME: () #[[ATTR2:[0-9]+]] {
7987 // CHECK17-NEXT:  entry:
7988 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
7989 // CHECK17-NEXT:    ret void
7990 //
7991 //
7992 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined.
7993 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
7994 // CHECK17-NEXT:  entry:
7995 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
7996 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
7997 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
7998 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
7999 // CHECK17-NEXT:    ret void
8000 //
8001 //
8002 // CHECK17-LABEL: define {{[^@]+}}@.omp_task_entry.
8003 // CHECK17-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
8004 // CHECK17-NEXT:  entry:
8005 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
8006 // CHECK17-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
8007 // CHECK17-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
8008 // CHECK17-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
8009 // CHECK17-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
8010 // CHECK17-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
8011 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
8012 // CHECK17-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
8013 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
8014 // CHECK17-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
8015 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
8016 // CHECK17-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
8017 // CHECK17-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
8018 // CHECK17-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
8019 // CHECK17-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
8020 // CHECK17-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
8021 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
8022 // CHECK17-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
8023 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])
8024 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
8025 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
8026 // CHECK17-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
8027 // CHECK17-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20
8028 // CHECK17-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20
8029 // CHECK17-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
8030 // CHECK17-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
8031 // CHECK17-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20
8032 // CHECK17-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
8033 // CHECK17-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
8034 // CHECK17-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
8035 // CHECK17-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
8036 // CHECK17-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
8037 // CHECK17:       omp_offload.failed.i:
8038 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
8039 // CHECK17-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
8040 // CHECK17:       .omp_outlined..1.exit:
8041 // CHECK17-NEXT:    ret i32 0
8042 //
8043 //
8044 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
8045 // CHECK17-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
8046 // CHECK17-NEXT:  entry:
8047 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8048 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8049 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8050 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8051 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8052 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8053 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
8054 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8055 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
8056 // CHECK17-NEXT:    ret void
8057 //
8058 //
8059 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..2
8060 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
8061 // CHECK17-NEXT:  entry:
8062 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8063 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8064 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8065 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8066 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8067 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8068 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8069 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8070 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8071 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
8072 // CHECK17-NEXT:    ret void
8073 //
8074 //
8075 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
8076 // CHECK17-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
8077 // CHECK17-NEXT:  entry:
8078 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8079 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8080 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8081 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8082 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
8083 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8084 // CHECK17-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
8085 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8086 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
8087 // CHECK17-NEXT:    ret void
8088 //
8089 //
8090 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..3
8091 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
8092 // CHECK17-NEXT:  entry:
8093 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8094 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8095 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8096 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8097 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8098 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8099 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8100 // CHECK17-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
8101 // CHECK17-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
8102 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
8103 // CHECK17-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
8104 // CHECK17-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 8
8105 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
8106 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
8107 // CHECK17-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
8108 // CHECK17-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
8109 // CHECK17-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
8110 // CHECK17:       .cancel.exit:
8111 // CHECK17-NEXT:    br label [[DOTCANCEL_CONTINUE]]
8112 // CHECK17:       .cancel.continue:
8113 // CHECK17-NEXT:    ret void
8114 //
8115 //
8116 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
8117 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
8118 // CHECK17-NEXT:  entry:
8119 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8120 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8121 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8122 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8123 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8124 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8125 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8126 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8127 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8128 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8129 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
8130 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8131 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
8132 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8133 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
8134 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8135 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
8136 // CHECK17-NEXT:    ret void
8137 //
8138 //
8139 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..4
8140 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
8141 // CHECK17-NEXT:  entry:
8142 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8143 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8144 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8145 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8146 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8147 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8148 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8149 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8150 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8151 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8152 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
8153 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8154 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
8155 // CHECK17-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
8156 // CHECK17-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
8157 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
8158 // CHECK17-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
8159 // CHECK17-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
8160 // CHECK17-NEXT:    ret void
8161 //
8162 //
8163 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
8164 // CHECK17-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
8165 // CHECK17-NEXT:  entry:
8166 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8167 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
8168 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8169 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
8170 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
8171 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8172 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
8173 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
8174 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
8175 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8176 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8177 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
8178 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8179 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
8180 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
8181 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8182 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
8183 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
8184 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
8185 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8186 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
8187 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8188 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
8189 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
8190 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8191 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
8192 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
8193 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
8194 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
8195 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8196 // CHECK17-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
8197 // CHECK17-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
8198 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
8199 // CHECK17-NEXT:    ret void
8200 //
8201 //
8202 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..7
8203 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
8204 // CHECK17-NEXT:  entry:
8205 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8206 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8207 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8208 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
8209 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8210 // CHECK17-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
8211 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
8212 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8213 // CHECK17-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
8214 // CHECK17-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
8215 // CHECK17-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
8216 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8217 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8218 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8219 // CHECK17-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
8220 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8221 // CHECK17-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
8222 // CHECK17-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
8223 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8224 // CHECK17-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
8225 // CHECK17-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
8226 // CHECK17-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
8227 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8228 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
8229 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8230 // CHECK17-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
8231 // CHECK17-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
8232 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8233 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
8234 // CHECK17-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
8235 // CHECK17-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
8236 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
8237 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
8238 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
8239 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
8240 // CHECK17-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
8241 // CHECK17-NEXT:    [[CONV5:%.*]] = fpext float [[TMP9]] to double
8242 // CHECK17-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
8243 // CHECK17-NEXT:    [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
8244 // CHECK17-NEXT:    store float [[CONV7]], float* [[ARRAYIDX]], align 4
8245 // CHECK17-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
8246 // CHECK17-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
8247 // CHECK17-NEXT:    [[CONV9:%.*]] = fpext float [[TMP10]] to double
8248 // CHECK17-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
8249 // CHECK17-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
8250 // CHECK17-NEXT:    store float [[CONV11]], float* [[ARRAYIDX8]], align 4
8251 // CHECK17-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
8252 // CHECK17-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
8253 // CHECK17-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
8254 // CHECK17-NEXT:    [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
8255 // CHECK17-NEXT:    store double [[ADD14]], double* [[ARRAYIDX13]], align 8
8256 // CHECK17-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
8257 // CHECK17-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
8258 // CHECK17-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
8259 // CHECK17-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
8260 // CHECK17-NEXT:    [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
8261 // CHECK17-NEXT:    store double [[ADD17]], double* [[ARRAYIDX16]], align 8
8262 // CHECK17-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
8263 // CHECK17-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 8
8264 // CHECK17-NEXT:    [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
8265 // CHECK17-NEXT:    store i64 [[ADD18]], i64* [[X]], align 8
8266 // CHECK17-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
8267 // CHECK17-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
8268 // CHECK17-NEXT:    [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
8269 // CHECK17-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
8270 // CHECK17-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
8271 // CHECK17-NEXT:    store i8 [[CONV21]], i8* [[Y]], align 8
8272 // CHECK17-NEXT:    ret void
8273 //
8274 //
8275 // CHECK17-LABEL: define {{[^@]+}}@_Z3bari
8276 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
8277 // CHECK17-NEXT:  entry:
8278 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8279 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
8280 // CHECK17-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
8281 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8282 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
8283 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8284 // CHECK17-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
8285 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
8286 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
8287 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
8288 // CHECK17-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
8289 // CHECK17-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
8290 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
8291 // CHECK17-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
8292 // CHECK17-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
8293 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8294 // CHECK17-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
8295 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
8296 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
8297 // CHECK17-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
8298 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8299 // CHECK17-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
8300 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
8301 // CHECK17-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
8302 // CHECK17-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
8303 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
8304 // CHECK17-NEXT:    ret i32 [[TMP8]]
8305 //
8306 //
8307 // CHECK17-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
8308 // CHECK17-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
8309 // CHECK17-NEXT:  entry:
8310 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8311 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8312 // CHECK17-NEXT:    [[B:%.*]] = alloca i32, align 4
8313 // CHECK17-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
8314 // CHECK17-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8315 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
8316 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
8317 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
8318 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
8319 // CHECK17-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
8320 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8321 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8322 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8323 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
8324 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
8325 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
8326 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8327 // CHECK17-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
8328 // CHECK17-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
8329 // CHECK17-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
8330 // CHECK17-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
8331 // CHECK17-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
8332 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
8333 // CHECK17-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
8334 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
8335 // CHECK17-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
8336 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
8337 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
8338 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
8339 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8340 // CHECK17:       omp_if.then:
8341 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
8342 // CHECK17-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
8343 // CHECK17-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
8344 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8345 // CHECK17-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
8346 // CHECK17-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
8347 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8348 // CHECK17-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
8349 // CHECK17-NEXT:    store double* [[A]], double** [[TMP13]], align 8
8350 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8351 // CHECK17-NEXT:    store i64 8, i64* [[TMP14]], align 8
8352 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8353 // CHECK17-NEXT:    store i8* null, i8** [[TMP15]], align 8
8354 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8355 // CHECK17-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
8356 // CHECK17-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
8357 // CHECK17-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8358 // CHECK17-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
8359 // CHECK17-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
8360 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
8361 // CHECK17-NEXT:    store i64 4, i64* [[TMP20]], align 8
8362 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8363 // CHECK17-NEXT:    store i8* null, i8** [[TMP21]], align 8
8364 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8365 // CHECK17-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
8366 // CHECK17-NEXT:    store i64 2, i64* [[TMP23]], align 8
8367 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8368 // CHECK17-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
8369 // CHECK17-NEXT:    store i64 2, i64* [[TMP25]], align 8
8370 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
8371 // CHECK17-NEXT:    store i64 8, i64* [[TMP26]], align 8
8372 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
8373 // CHECK17-NEXT:    store i8* null, i8** [[TMP27]], align 8
8374 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8375 // CHECK17-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
8376 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
8377 // CHECK17-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8378 // CHECK17-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
8379 // CHECK17-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
8380 // CHECK17-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
8381 // CHECK17-NEXT:    store i64 8, i64* [[TMP32]], align 8
8382 // CHECK17-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
8383 // CHECK17-NEXT:    store i8* null, i8** [[TMP33]], align 8
8384 // CHECK17-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
8385 // CHECK17-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
8386 // CHECK17-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
8387 // CHECK17-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
8388 // CHECK17-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
8389 // CHECK17-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
8390 // CHECK17-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
8391 // CHECK17-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
8392 // CHECK17-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
8393 // CHECK17-NEXT:    store i8* null, i8** [[TMP39]], align 8
8394 // CHECK17-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8395 // CHECK17-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8396 // CHECK17-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8397 // CHECK17-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
8398 // CHECK17-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
8399 // CHECK17-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8400 // CHECK17:       omp_offload.failed:
8401 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
8402 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8403 // CHECK17:       omp_offload.cont:
8404 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
8405 // CHECK17:       omp_if.else:
8406 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
8407 // CHECK17-NEXT:    br label [[OMP_IF_END]]
8408 // CHECK17:       omp_if.end:
8409 // CHECK17-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
8410 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
8411 // CHECK17-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
8412 // CHECK17-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
8413 // CHECK17-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
8414 // CHECK17-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
8415 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
8416 // CHECK17-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
8417 // CHECK17-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
8418 // CHECK17-NEXT:    ret i32 [[ADD4]]
8419 //
8420 //
8421 // CHECK17-LABEL: define {{[^@]+}}@_ZL7fstatici
8422 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
8423 // CHECK17-NEXT:  entry:
8424 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8425 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
8426 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
8427 // CHECK17-NEXT:    [[AAA:%.*]] = alloca i8, align 1
8428 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8429 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8430 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8431 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
8432 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
8433 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
8434 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
8435 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8436 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
8437 // CHECK17-NEXT:    store i16 0, i16* [[AA]], align 2
8438 // CHECK17-NEXT:    store i8 0, i8* [[AAA]], align 1
8439 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8440 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8441 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
8442 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8443 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8444 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8445 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
8446 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8447 // CHECK17-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
8448 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
8449 // CHECK17-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
8450 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
8451 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
8452 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
8453 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8454 // CHECK17:       omp_if.then:
8455 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8456 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
8457 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
8458 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8459 // CHECK17-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
8460 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
8461 // CHECK17-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8462 // CHECK17-NEXT:    store i8* null, i8** [[TMP11]], align 8
8463 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8464 // CHECK17-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
8465 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
8466 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8467 // CHECK17-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
8468 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
8469 // CHECK17-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8470 // CHECK17-NEXT:    store i8* null, i8** [[TMP16]], align 8
8471 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8472 // CHECK17-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
8473 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
8474 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8475 // CHECK17-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
8476 // CHECK17-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
8477 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
8478 // CHECK17-NEXT:    store i8* null, i8** [[TMP21]], align 8
8479 // CHECK17-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
8480 // CHECK17-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
8481 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
8482 // CHECK17-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
8483 // CHECK17-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
8484 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
8485 // CHECK17-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
8486 // CHECK17-NEXT:    store i8* null, i8** [[TMP26]], align 8
8487 // CHECK17-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8488 // CHECK17-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8489 // CHECK17-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
8490 // CHECK17-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
8491 // CHECK17-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8492 // CHECK17:       omp_offload.failed:
8493 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
8494 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8495 // CHECK17:       omp_offload.cont:
8496 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
8497 // CHECK17:       omp_if.else:
8498 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
8499 // CHECK17-NEXT:    br label [[OMP_IF_END]]
8500 // CHECK17:       omp_if.end:
8501 // CHECK17-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
8502 // CHECK17-NEXT:    ret i32 [[TMP31]]
8503 //
8504 //
8505 // CHECK17-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
8506 // CHECK17-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
8507 // CHECK17-NEXT:  entry:
8508 // CHECK17-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8509 // CHECK17-NEXT:    [[A:%.*]] = alloca i32, align 4
8510 // CHECK17-NEXT:    [[AA:%.*]] = alloca i16, align 2
8511 // CHECK17-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
8512 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8513 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8514 // CHECK17-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
8515 // CHECK17-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
8516 // CHECK17-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
8517 // CHECK17-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8518 // CHECK17-NEXT:    store i32 0, i32* [[A]], align 4
8519 // CHECK17-NEXT:    store i16 0, i16* [[AA]], align 2
8520 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
8521 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8522 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
8523 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
8524 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
8525 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8526 // CHECK17-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
8527 // CHECK17-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8528 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8529 // CHECK17-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
8530 // CHECK17-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8531 // CHECK17:       omp_if.then:
8532 // CHECK17-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8533 // CHECK17-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
8534 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
8535 // CHECK17-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8536 // CHECK17-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
8537 // CHECK17-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
8538 // CHECK17-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8539 // CHECK17-NEXT:    store i8* null, i8** [[TMP9]], align 8
8540 // CHECK17-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
8541 // CHECK17-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
8542 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
8543 // CHECK17-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
8544 // CHECK17-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
8545 // CHECK17-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
8546 // CHECK17-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
8547 // CHECK17-NEXT:    store i8* null, i8** [[TMP14]], align 8
8548 // CHECK17-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
8549 // CHECK17-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
8550 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
8551 // CHECK17-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
8552 // CHECK17-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
8553 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
8554 // CHECK17-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
8555 // CHECK17-NEXT:    store i8* null, i8** [[TMP19]], align 8
8556 // CHECK17-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8557 // CHECK17-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8558 // CHECK17-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
8559 // CHECK17-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
8560 // CHECK17-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8561 // CHECK17:       omp_offload.failed:
8562 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
8563 // CHECK17-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8564 // CHECK17:       omp_offload.cont:
8565 // CHECK17-NEXT:    br label [[OMP_IF_END:%.*]]
8566 // CHECK17:       omp_if.else:
8567 // CHECK17-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
8568 // CHECK17-NEXT:    br label [[OMP_IF_END]]
8569 // CHECK17:       omp_if.end:
8570 // CHECK17-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
8571 // CHECK17-NEXT:    ret i32 [[TMP24]]
8572 //
8573 //
8574 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
8575 // CHECK17-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
8576 // CHECK17-NEXT:  entry:
8577 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8578 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
8579 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8580 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8581 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
8582 // CHECK17-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
8583 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8584 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
8585 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8586 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8587 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
8588 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8589 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
8590 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8591 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8592 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
8593 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
8594 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
8595 // CHECK17-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
8596 // CHECK17-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
8597 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
8598 // CHECK17-NEXT:    ret void
8599 //
8600 //
8601 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..9
8602 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
8603 // CHECK17-NEXT:  entry:
8604 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8605 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8606 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
8607 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
8608 // CHECK17-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
8609 // CHECK17-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
8610 // CHECK17-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
8611 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8612 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8613 // CHECK17-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
8614 // CHECK17-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
8615 // CHECK17-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
8616 // CHECK17-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
8617 // CHECK17-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
8618 // CHECK17-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
8619 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
8620 // CHECK17-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
8621 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
8622 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
8623 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
8624 // CHECK17-NEXT:    [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
8625 // CHECK17-NEXT:    [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
8626 // CHECK17-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
8627 // CHECK17-NEXT:    store double [[ADD]], double* [[A]], align 8
8628 // CHECK17-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
8629 // CHECK17-NEXT:    [[TMP5:%.*]] = load double, double* [[A4]], align 8
8630 // CHECK17-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
8631 // CHECK17-NEXT:    store double [[INC]], double* [[A4]], align 8
8632 // CHECK17-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
8633 // CHECK17-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
8634 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
8635 // CHECK17-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
8636 // CHECK17-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
8637 // CHECK17-NEXT:    ret void
8638 //
8639 //
8640 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
8641 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8642 // CHECK17-NEXT:  entry:
8643 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8644 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8645 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
8646 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8647 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8648 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8649 // CHECK17-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
8650 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8651 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8652 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
8653 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8654 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8655 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8656 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
8657 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8658 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
8659 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8660 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
8661 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
8662 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
8663 // CHECK17-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8664 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
8665 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8666 // CHECK17-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
8667 // CHECK17-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
8668 // CHECK17-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
8669 // CHECK17-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
8670 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
8671 // CHECK17-NEXT:    ret void
8672 //
8673 //
8674 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..11
8675 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8676 // CHECK17-NEXT:  entry:
8677 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8678 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8679 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8680 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8681 // CHECK17-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
8682 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8683 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8684 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8685 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8686 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8687 // CHECK17-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
8688 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8689 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8690 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8691 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
8692 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8693 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
8694 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
8695 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
8696 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
8697 // CHECK17-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
8698 // CHECK17-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
8699 // CHECK17-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
8700 // CHECK17-NEXT:    store i16 [[CONV5]], i16* [[CONV1]], align 8
8701 // CHECK17-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
8702 // CHECK17-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
8703 // CHECK17-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
8704 // CHECK17-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
8705 // CHECK17-NEXT:    store i8 [[CONV8]], i8* [[CONV2]], align 8
8706 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
8707 // CHECK17-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
8708 // CHECK17-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
8709 // CHECK17-NEXT:    store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
8710 // CHECK17-NEXT:    ret void
8711 //
8712 //
8713 // CHECK17-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
8714 // CHECK17-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8715 // CHECK17-NEXT:  entry:
8716 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8717 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8718 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8719 // CHECK17-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8720 // CHECK17-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8721 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8722 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8723 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8724 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8725 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8726 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8727 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
8728 // CHECK17-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8729 // CHECK17-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
8730 // CHECK17-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
8731 // CHECK17-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
8732 // CHECK17-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8733 // CHECK17-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
8734 // CHECK17-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8735 // CHECK17-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
8736 // CHECK17-NEXT:    ret void
8737 //
8738 //
8739 // CHECK17-LABEL: define {{[^@]+}}@.omp_outlined..14
8740 // CHECK17-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
8741 // CHECK17-NEXT:  entry:
8742 // CHECK17-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
8743 // CHECK17-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
8744 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
8745 // CHECK17-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
8746 // CHECK17-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
8747 // CHECK17-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
8748 // CHECK17-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
8749 // CHECK17-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
8750 // CHECK17-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
8751 // CHECK17-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
8752 // CHECK17-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
8753 // CHECK17-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
8754 // CHECK17-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
8755 // CHECK17-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
8756 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
8757 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
8758 // CHECK17-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
8759 // CHECK17-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
8760 // CHECK17-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
8761 // CHECK17-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
8762 // CHECK17-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
8763 // CHECK17-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
8764 // CHECK17-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
8765 // CHECK17-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
8766 // CHECK17-NEXT:    store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
8767 // CHECK17-NEXT:    ret void
8768 //
8769 //
8770 // CHECK17-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
8771 // CHECK17-SAME: () #[[ATTR5:[0-9]+]] {
8772 // CHECK17-NEXT:  entry:
8773 // CHECK17-NEXT:    call void @__tgt_register_requires(i64 1)
8774 // CHECK17-NEXT:    ret void
8775 //
8776 //
8777 // CHECK18-LABEL: define {{[^@]+}}@_Z3fooi
8778 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
8779 // CHECK18-NEXT:  entry:
8780 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
8781 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
8782 // CHECK18-NEXT:    [[AA:%.*]] = alloca i16, align 2
8783 // CHECK18-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
8784 // CHECK18-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
8785 // CHECK18-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
8786 // CHECK18-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
8787 // CHECK18-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
8788 // CHECK18-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
8789 // CHECK18-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
8790 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
8791 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
8792 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 8
8793 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 8
8794 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 8
8795 // CHECK18-NEXT:    [[A_CASTED3:%.*]] = alloca i64, align 8
8796 // CHECK18-NEXT:    [[AA_CASTED5:%.*]] = alloca i64, align 8
8797 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS7:%.*]] = alloca [2 x i8*], align 8
8798 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS8:%.*]] = alloca [2 x i8*], align 8
8799 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS9:%.*]] = alloca [2 x i8*], align 8
8800 // CHECK18-NEXT:    [[A_CASTED12:%.*]] = alloca i64, align 8
8801 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS16:%.*]] = alloca [9 x i8*], align 8
8802 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS17:%.*]] = alloca [9 x i8*], align 8
8803 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS18:%.*]] = alloca [9 x i8*], align 8
8804 // CHECK18-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 8
8805 // CHECK18-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
8806 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
8807 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
8808 // CHECK18-NEXT:    store i16 0, i16* [[AA]], align 2
8809 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
8810 // CHECK18-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
8811 // CHECK18-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
8812 // CHECK18-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
8813 // CHECK18-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP2]], align 4
8814 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
8815 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
8816 // CHECK18-NEXT:    [[TMP5:%.*]] = zext i32 [[TMP4]] to i64
8817 // CHECK18-NEXT:    [[TMP6:%.*]] = mul nuw i64 5, [[TMP5]]
8818 // CHECK18-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP6]], align 8
8819 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[__VLA_EXPR1]], align 8
8820 // CHECK18-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i64 40, i64 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
8821 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.kmp_task_t_with_privates*
8822 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP8]], i32 0, i32 0
8823 // CHECK18-NEXT:    [[TMP10:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP7]])
8824 // CHECK18-NEXT:    [[TMP11:%.*]] = load i32, i32* [[A]], align 4
8825 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
8826 // CHECK18-NEXT:    store i32 [[TMP11]], i32* [[CONV]], align 4
8827 // CHECK18-NEXT:    [[TMP12:%.*]] = load i64, i64* [[A_CASTED]], align 8
8828 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i64 [[TMP12]]) #[[ATTR3:[0-9]+]]
8829 // CHECK18-NEXT:    [[TMP13:%.*]] = load i16, i16* [[AA]], align 2
8830 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
8831 // CHECK18-NEXT:    store i16 [[TMP13]], i16* [[CONV2]], align 2
8832 // CHECK18-NEXT:    [[TMP14:%.*]] = load i64, i64* [[AA_CASTED]], align 8
8833 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8834 // CHECK18-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i64*
8835 // CHECK18-NEXT:    store i64 [[TMP14]], i64* [[TMP16]], align 8
8836 // CHECK18-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8837 // CHECK18-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
8838 // CHECK18-NEXT:    store i64 [[TMP14]], i64* [[TMP18]], align 8
8839 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
8840 // CHECK18-NEXT:    store i8* null, i8** [[TMP19]], align 8
8841 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
8842 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
8843 // CHECK18-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
8844 // CHECK18-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
8845 // CHECK18-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
8846 // CHECK18:       omp_offload.failed:
8847 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i64 [[TMP14]]) #[[ATTR3]]
8848 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
8849 // CHECK18:       omp_offload.cont:
8850 // CHECK18-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
8851 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[A_CASTED3]] to i32*
8852 // CHECK18-NEXT:    store i32 [[TMP24]], i32* [[CONV4]], align 4
8853 // CHECK18-NEXT:    [[TMP25:%.*]] = load i64, i64* [[A_CASTED3]], align 8
8854 // CHECK18-NEXT:    [[TMP26:%.*]] = load i16, i16* [[AA]], align 2
8855 // CHECK18-NEXT:    [[CONV6:%.*]] = bitcast i64* [[AA_CASTED5]] to i16*
8856 // CHECK18-NEXT:    store i16 [[TMP26]], i16* [[CONV6]], align 2
8857 // CHECK18-NEXT:    [[TMP27:%.*]] = load i64, i64* [[AA_CASTED5]], align 8
8858 // CHECK18-NEXT:    [[TMP28:%.*]] = load i32, i32* [[N_ADDR]], align 4
8859 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP28]], 10
8860 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
8861 // CHECK18:       omp_if.then:
8862 // CHECK18-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
8863 // CHECK18-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i64*
8864 // CHECK18-NEXT:    store i64 [[TMP25]], i64* [[TMP30]], align 8
8865 // CHECK18-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
8866 // CHECK18-NEXT:    [[TMP32:%.*]] = bitcast i8** [[TMP31]] to i64*
8867 // CHECK18-NEXT:    store i64 [[TMP25]], i64* [[TMP32]], align 8
8868 // CHECK18-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 0
8869 // CHECK18-NEXT:    store i8* null, i8** [[TMP33]], align 8
8870 // CHECK18-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 1
8871 // CHECK18-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i64*
8872 // CHECK18-NEXT:    store i64 [[TMP27]], i64* [[TMP35]], align 8
8873 // CHECK18-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 1
8874 // CHECK18-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i64*
8875 // CHECK18-NEXT:    store i64 [[TMP27]], i64* [[TMP37]], align 8
8876 // CHECK18-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS9]], i64 0, i64 1
8877 // CHECK18-NEXT:    store i8* null, i8** [[TMP38]], align 8
8878 // CHECK18-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS7]], i32 0, i32 0
8879 // CHECK18-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS8]], i32 0, i32 0
8880 // CHECK18-NEXT:    [[TMP41:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP39]], i8** [[TMP40]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
8881 // CHECK18-NEXT:    [[TMP42:%.*]] = icmp ne i32 [[TMP41]], 0
8882 // CHECK18-NEXT:    br i1 [[TMP42]], label [[OMP_OFFLOAD_FAILED10:%.*]], label [[OMP_OFFLOAD_CONT11:%.*]]
8883 // CHECK18:       omp_offload.failed10:
8884 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]]
8885 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT11]]
8886 // CHECK18:       omp_offload.cont11:
8887 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
8888 // CHECK18:       omp_if.else:
8889 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i64 [[TMP25]], i64 [[TMP27]]) #[[ATTR3]]
8890 // CHECK18-NEXT:    br label [[OMP_IF_END]]
8891 // CHECK18:       omp_if.end:
8892 // CHECK18-NEXT:    [[TMP43:%.*]] = load i32, i32* [[A]], align 4
8893 // CHECK18-NEXT:    [[CONV13:%.*]] = bitcast i64* [[A_CASTED12]] to i32*
8894 // CHECK18-NEXT:    store i32 [[TMP43]], i32* [[CONV13]], align 4
8895 // CHECK18-NEXT:    [[TMP44:%.*]] = load i64, i64* [[A_CASTED12]], align 8
8896 // CHECK18-NEXT:    [[TMP45:%.*]] = load i32, i32* [[N_ADDR]], align 4
8897 // CHECK18-NEXT:    [[CMP14:%.*]] = icmp sgt i32 [[TMP45]], 20
8898 // CHECK18-NEXT:    br i1 [[CMP14]], label [[OMP_IF_THEN15:%.*]], label [[OMP_IF_ELSE21:%.*]]
8899 // CHECK18:       omp_if.then15:
8900 // CHECK18-NEXT:    [[TMP46:%.*]] = mul nuw i64 [[TMP2]], 4
8901 // CHECK18-NEXT:    [[TMP47:%.*]] = mul nuw i64 5, [[TMP5]]
8902 // CHECK18-NEXT:    [[TMP48:%.*]] = mul nuw i64 [[TMP47]], 8
8903 // CHECK18-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
8904 // CHECK18-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i64*
8905 // CHECK18-NEXT:    store i64 [[TMP44]], i64* [[TMP50]], align 8
8906 // CHECK18-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
8907 // CHECK18-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i64*
8908 // CHECK18-NEXT:    store i64 [[TMP44]], i64* [[TMP52]], align 8
8909 // CHECK18-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8910 // CHECK18-NEXT:    store i64 4, i64* [[TMP53]], align 8
8911 // CHECK18-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 0
8912 // CHECK18-NEXT:    store i8* null, i8** [[TMP54]], align 8
8913 // CHECK18-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 1
8914 // CHECK18-NEXT:    [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]**
8915 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 8
8916 // CHECK18-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 1
8917 // CHECK18-NEXT:    [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]**
8918 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 8
8919 // CHECK18-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
8920 // CHECK18-NEXT:    store i64 40, i64* [[TMP59]], align 8
8921 // CHECK18-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 1
8922 // CHECK18-NEXT:    store i8* null, i8** [[TMP60]], align 8
8923 // CHECK18-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 2
8924 // CHECK18-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i64*
8925 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP62]], align 8
8926 // CHECK18-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 2
8927 // CHECK18-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i64*
8928 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP64]], align 8
8929 // CHECK18-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
8930 // CHECK18-NEXT:    store i64 8, i64* [[TMP65]], align 8
8931 // CHECK18-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 2
8932 // CHECK18-NEXT:    store i8* null, i8** [[TMP66]], align 8
8933 // CHECK18-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 3
8934 // CHECK18-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float**
8935 // CHECK18-NEXT:    store float* [[VLA]], float** [[TMP68]], align 8
8936 // CHECK18-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 3
8937 // CHECK18-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float**
8938 // CHECK18-NEXT:    store float* [[VLA]], float** [[TMP70]], align 8
8939 // CHECK18-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
8940 // CHECK18-NEXT:    store i64 [[TMP46]], i64* [[TMP71]], align 8
8941 // CHECK18-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 3
8942 // CHECK18-NEXT:    store i8* null, i8** [[TMP72]], align 8
8943 // CHECK18-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 4
8944 // CHECK18-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]**
8945 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 8
8946 // CHECK18-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 4
8947 // CHECK18-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]**
8948 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 8
8949 // CHECK18-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
8950 // CHECK18-NEXT:    store i64 400, i64* [[TMP77]], align 8
8951 // CHECK18-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 4
8952 // CHECK18-NEXT:    store i8* null, i8** [[TMP78]], align 8
8953 // CHECK18-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 5
8954 // CHECK18-NEXT:    [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i64*
8955 // CHECK18-NEXT:    store i64 5, i64* [[TMP80]], align 8
8956 // CHECK18-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 5
8957 // CHECK18-NEXT:    [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i64*
8958 // CHECK18-NEXT:    store i64 5, i64* [[TMP82]], align 8
8959 // CHECK18-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
8960 // CHECK18-NEXT:    store i64 8, i64* [[TMP83]], align 8
8961 // CHECK18-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 5
8962 // CHECK18-NEXT:    store i8* null, i8** [[TMP84]], align 8
8963 // CHECK18-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 6
8964 // CHECK18-NEXT:    [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i64*
8965 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP86]], align 8
8966 // CHECK18-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 6
8967 // CHECK18-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i64*
8968 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP88]], align 8
8969 // CHECK18-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
8970 // CHECK18-NEXT:    store i64 8, i64* [[TMP89]], align 8
8971 // CHECK18-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 6
8972 // CHECK18-NEXT:    store i8* null, i8** [[TMP90]], align 8
8973 // CHECK18-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 7
8974 // CHECK18-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double**
8975 // CHECK18-NEXT:    store double* [[VLA1]], double** [[TMP92]], align 8
8976 // CHECK18-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 7
8977 // CHECK18-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double**
8978 // CHECK18-NEXT:    store double* [[VLA1]], double** [[TMP94]], align 8
8979 // CHECK18-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
8980 // CHECK18-NEXT:    store i64 [[TMP48]], i64* [[TMP95]], align 8
8981 // CHECK18-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 7
8982 // CHECK18-NEXT:    store i8* null, i8** [[TMP96]], align 8
8983 // CHECK18-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 8
8984 // CHECK18-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT**
8985 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 8
8986 // CHECK18-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 8
8987 // CHECK18-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT**
8988 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 8
8989 // CHECK18-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
8990 // CHECK18-NEXT:    store i64 16, i64* [[TMP101]], align 8
8991 // CHECK18-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS18]], i64 0, i64 8
8992 // CHECK18-NEXT:    store i8* null, i8** [[TMP102]], align 8
8993 // CHECK18-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS16]], i32 0, i32 0
8994 // CHECK18-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS17]], i32 0, i32 0
8995 // CHECK18-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
8996 // CHECK18-NEXT:    [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
8997 // CHECK18-NEXT:    [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0
8998 // CHECK18-NEXT:    br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED19:%.*]], label [[OMP_OFFLOAD_CONT20:%.*]]
8999 // CHECK18:       omp_offload.failed19:
9000 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
9001 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT20]]
9002 // CHECK18:       omp_offload.cont20:
9003 // CHECK18-NEXT:    br label [[OMP_IF_END22:%.*]]
9004 // CHECK18:       omp_if.else21:
9005 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i64 [[TMP44]], [10 x float]* [[B]], i64 [[TMP2]], float* [[VLA]], [5 x [10 x double]]* [[C]], i64 5, i64 [[TMP5]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
9006 // CHECK18-NEXT:    br label [[OMP_IF_END22]]
9007 // CHECK18:       omp_if.end22:
9008 // CHECK18-NEXT:    [[TMP108:%.*]] = load i32, i32* [[A]], align 4
9009 // CHECK18-NEXT:    [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
9010 // CHECK18-NEXT:    call void @llvm.stackrestore(i8* [[TMP109]])
9011 // CHECK18-NEXT:    ret i32 [[TMP108]]
9012 //
9013 //
9014 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
9015 // CHECK18-SAME: () #[[ATTR2:[0-9]+]] {
9016 // CHECK18-NEXT:  entry:
9017 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
9018 // CHECK18-NEXT:    ret void
9019 //
9020 //
9021 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined.
9022 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
9023 // CHECK18-NEXT:  entry:
9024 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9025 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9026 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9027 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9028 // CHECK18-NEXT:    ret void
9029 //
9030 //
9031 // CHECK18-LABEL: define {{[^@]+}}@.omp_task_entry.
9032 // CHECK18-SAME: (i32 signext [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
9033 // CHECK18-NEXT:  entry:
9034 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
9035 // CHECK18-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 8
9036 // CHECK18-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 8
9037 // CHECK18-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 8
9038 // CHECK18-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 8
9039 // CHECK18-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 8
9040 // CHECK18-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
9041 // CHECK18-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 8
9042 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
9043 // CHECK18-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
9044 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
9045 // CHECK18-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 8
9046 // CHECK18-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
9047 // CHECK18-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
9048 // CHECK18-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
9049 // CHECK18-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 8
9050 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
9051 // CHECK18-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
9052 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META11:![0-9]+]])
9053 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META14:![0-9]+]])
9054 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META16:![0-9]+]])
9055 // CHECK18-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META18:![0-9]+]])
9056 // CHECK18-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !20
9057 // CHECK18-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 8, !noalias !20
9058 // CHECK18-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 8, !noalias !20
9059 // CHECK18-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 8, !noalias !20
9060 // CHECK18-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 8, !noalias !20
9061 // CHECK18-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
9062 // CHECK18-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 8, !noalias !20
9063 // CHECK18-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
9064 // CHECK18-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
9065 // CHECK18-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
9066 // CHECK18:       omp_offload.failed.i:
9067 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
9068 // CHECK18-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
9069 // CHECK18:       .omp_outlined..1.exit:
9070 // CHECK18-NEXT:    ret i32 0
9071 //
9072 //
9073 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
9074 // CHECK18-SAME: (i64 [[A:%.*]]) #[[ATTR2]] {
9075 // CHECK18-NEXT:  entry:
9076 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9077 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9078 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9079 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9080 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9081 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9082 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV1]], align 4
9083 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9084 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]])
9085 // CHECK18-NEXT:    ret void
9086 //
9087 //
9088 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..2
9089 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]]) #[[ATTR2]] {
9090 // CHECK18-NEXT:  entry:
9091 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9092 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9093 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9094 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9095 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9096 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9097 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9098 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9099 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9100 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
9101 // CHECK18-NEXT:    ret void
9102 //
9103 //
9104 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
9105 // CHECK18-SAME: (i64 [[AA:%.*]]) #[[ATTR2]] {
9106 // CHECK18-NEXT:  entry:
9107 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9108 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9109 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9110 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9111 // CHECK18-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
9112 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9113 // CHECK18-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
9114 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9115 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP1]])
9116 // CHECK18-NEXT:    ret void
9117 //
9118 //
9119 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..3
9120 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
9121 // CHECK18-NEXT:  entry:
9122 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9123 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9124 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9125 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9126 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9127 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9128 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9129 // CHECK18-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
9130 // CHECK18-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
9131 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
9132 // CHECK18-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
9133 // CHECK18-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 8
9134 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
9135 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
9136 // CHECK18-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
9137 // CHECK18-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
9138 // CHECK18-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
9139 // CHECK18:       .cancel.exit:
9140 // CHECK18-NEXT:    br label [[DOTCANCEL_CONTINUE]]
9141 // CHECK18:       .cancel.continue:
9142 // CHECK18-NEXT:    ret void
9143 //
9144 //
9145 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
9146 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
9147 // CHECK18-NEXT:  entry:
9148 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9149 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9150 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9151 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9152 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9153 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9154 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9155 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9156 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9157 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9158 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
9159 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9160 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
9161 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9162 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
9163 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9164 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
9165 // CHECK18-NEXT:    ret void
9166 //
9167 //
9168 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..4
9169 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR2]] {
9170 // CHECK18-NEXT:  entry:
9171 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9172 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9173 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9174 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9175 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9176 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9177 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9178 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9179 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9180 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9181 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
9182 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9183 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
9184 // CHECK18-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
9185 // CHECK18-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
9186 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
9187 // CHECK18-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
9188 // CHECK18-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
9189 // CHECK18-NEXT:    ret void
9190 //
9191 //
9192 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
9193 // CHECK18-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
9194 // CHECK18-NEXT:  entry:
9195 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9196 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9197 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9198 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9199 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9200 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9201 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9202 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9203 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9204 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9205 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9206 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9207 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9208 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9209 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9210 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9211 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9212 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9213 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9214 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9215 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9216 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9217 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9218 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9219 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9220 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9221 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9222 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9223 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
9224 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9225 // CHECK18-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
9226 // CHECK18-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
9227 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
9228 // CHECK18-NEXT:    ret void
9229 //
9230 //
9231 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..7
9232 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR2]] {
9233 // CHECK18-NEXT:  entry:
9234 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9235 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9236 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9237 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
9238 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9239 // CHECK18-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
9240 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
9241 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9242 // CHECK18-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
9243 // CHECK18-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
9244 // CHECK18-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
9245 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9246 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9247 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9248 // CHECK18-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
9249 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9250 // CHECK18-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
9251 // CHECK18-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
9252 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9253 // CHECK18-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
9254 // CHECK18-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
9255 // CHECK18-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
9256 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9257 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
9258 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9259 // CHECK18-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
9260 // CHECK18-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
9261 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9262 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
9263 // CHECK18-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
9264 // CHECK18-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
9265 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
9266 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
9267 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
9268 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
9269 // CHECK18-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
9270 // CHECK18-NEXT:    [[CONV5:%.*]] = fpext float [[TMP9]] to double
9271 // CHECK18-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
9272 // CHECK18-NEXT:    [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
9273 // CHECK18-NEXT:    store float [[CONV7]], float* [[ARRAYIDX]], align 4
9274 // CHECK18-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
9275 // CHECK18-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
9276 // CHECK18-NEXT:    [[CONV9:%.*]] = fpext float [[TMP10]] to double
9277 // CHECK18-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
9278 // CHECK18-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
9279 // CHECK18-NEXT:    store float [[CONV11]], float* [[ARRAYIDX8]], align 4
9280 // CHECK18-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
9281 // CHECK18-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
9282 // CHECK18-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
9283 // CHECK18-NEXT:    [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
9284 // CHECK18-NEXT:    store double [[ADD14]], double* [[ARRAYIDX13]], align 8
9285 // CHECK18-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
9286 // CHECK18-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
9287 // CHECK18-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
9288 // CHECK18-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
9289 // CHECK18-NEXT:    [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
9290 // CHECK18-NEXT:    store double [[ADD17]], double* [[ARRAYIDX16]], align 8
9291 // CHECK18-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
9292 // CHECK18-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 8
9293 // CHECK18-NEXT:    [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
9294 // CHECK18-NEXT:    store i64 [[ADD18]], i64* [[X]], align 8
9295 // CHECK18-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
9296 // CHECK18-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
9297 // CHECK18-NEXT:    [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
9298 // CHECK18-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
9299 // CHECK18-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
9300 // CHECK18-NEXT:    store i8 [[CONV21]], i8* [[Y]], align 8
9301 // CHECK18-NEXT:    ret void
9302 //
9303 //
9304 // CHECK18-LABEL: define {{[^@]+}}@_Z3bari
9305 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
9306 // CHECK18-NEXT:  entry:
9307 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9308 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
9309 // CHECK18-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
9310 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9311 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
9312 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9313 // CHECK18-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
9314 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
9315 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
9316 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
9317 // CHECK18-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
9318 // CHECK18-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
9319 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
9320 // CHECK18-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
9321 // CHECK18-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
9322 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
9323 // CHECK18-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
9324 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
9325 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
9326 // CHECK18-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
9327 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
9328 // CHECK18-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
9329 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
9330 // CHECK18-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
9331 // CHECK18-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
9332 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
9333 // CHECK18-NEXT:    ret i32 [[TMP8]]
9334 //
9335 //
9336 // CHECK18-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
9337 // CHECK18-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
9338 // CHECK18-NEXT:  entry:
9339 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9340 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9341 // CHECK18-NEXT:    [[B:%.*]] = alloca i32, align 4
9342 // CHECK18-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
9343 // CHECK18-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
9344 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
9345 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 8
9346 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 8
9347 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 8
9348 // CHECK18-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 8
9349 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9350 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9351 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9352 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
9353 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
9354 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
9355 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
9356 // CHECK18-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
9357 // CHECK18-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
9358 // CHECK18-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
9359 // CHECK18-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
9360 // CHECK18-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
9361 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
9362 // CHECK18-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
9363 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_CASTED]] to i32*
9364 // CHECK18-NEXT:    store i32 [[TMP5]], i32* [[CONV]], align 4
9365 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[B_CASTED]], align 8
9366 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4
9367 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP7]], 60
9368 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9369 // CHECK18:       omp_if.then:
9370 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
9371 // CHECK18-NEXT:    [[TMP8:%.*]] = mul nuw i64 2, [[TMP2]]
9372 // CHECK18-NEXT:    [[TMP9:%.*]] = mul nuw i64 [[TMP8]], 2
9373 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9374 // CHECK18-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
9375 // CHECK18-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 8
9376 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9377 // CHECK18-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
9378 // CHECK18-NEXT:    store double* [[A]], double** [[TMP13]], align 8
9379 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
9380 // CHECK18-NEXT:    store i64 8, i64* [[TMP14]], align 8
9381 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
9382 // CHECK18-NEXT:    store i8* null, i8** [[TMP15]], align 8
9383 // CHECK18-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
9384 // CHECK18-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i64*
9385 // CHECK18-NEXT:    store i64 [[TMP6]], i64* [[TMP17]], align 8
9386 // CHECK18-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
9387 // CHECK18-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i64*
9388 // CHECK18-NEXT:    store i64 [[TMP6]], i64* [[TMP19]], align 8
9389 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
9390 // CHECK18-NEXT:    store i64 4, i64* [[TMP20]], align 8
9391 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
9392 // CHECK18-NEXT:    store i8* null, i8** [[TMP21]], align 8
9393 // CHECK18-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
9394 // CHECK18-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i64*
9395 // CHECK18-NEXT:    store i64 2, i64* [[TMP23]], align 8
9396 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
9397 // CHECK18-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64*
9398 // CHECK18-NEXT:    store i64 2, i64* [[TMP25]], align 8
9399 // CHECK18-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
9400 // CHECK18-NEXT:    store i64 8, i64* [[TMP26]], align 8
9401 // CHECK18-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9402 // CHECK18-NEXT:    store i8* null, i8** [[TMP27]], align 8
9403 // CHECK18-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
9404 // CHECK18-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i64*
9405 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP29]], align 8
9406 // CHECK18-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
9407 // CHECK18-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i64*
9408 // CHECK18-NEXT:    store i64 [[TMP2]], i64* [[TMP31]], align 8
9409 // CHECK18-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
9410 // CHECK18-NEXT:    store i64 8, i64* [[TMP32]], align 8
9411 // CHECK18-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
9412 // CHECK18-NEXT:    store i8* null, i8** [[TMP33]], align 8
9413 // CHECK18-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
9414 // CHECK18-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
9415 // CHECK18-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 8
9416 // CHECK18-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
9417 // CHECK18-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
9418 // CHECK18-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 8
9419 // CHECK18-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
9420 // CHECK18-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 8
9421 // CHECK18-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 4
9422 // CHECK18-NEXT:    store i8* null, i8** [[TMP39]], align 8
9423 // CHECK18-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9424 // CHECK18-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9425 // CHECK18-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
9426 // CHECK18-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
9427 // CHECK18-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
9428 // CHECK18-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9429 // CHECK18:       omp_offload.failed:
9430 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
9431 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
9432 // CHECK18:       omp_offload.cont:
9433 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
9434 // CHECK18:       omp_if.else:
9435 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i64 [[TMP6]], i64 2, i64 [[TMP2]], i16* [[VLA]]) #[[ATTR3]]
9436 // CHECK18-NEXT:    br label [[OMP_IF_END]]
9437 // CHECK18:       omp_if.end:
9438 // CHECK18-NEXT:    [[TMP45:%.*]] = mul nsw i64 1, [[TMP2]]
9439 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP45]]
9440 // CHECK18-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
9441 // CHECK18-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
9442 // CHECK18-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP46]] to i32
9443 // CHECK18-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
9444 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], [[TMP47]]
9445 // CHECK18-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
9446 // CHECK18-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
9447 // CHECK18-NEXT:    ret i32 [[ADD4]]
9448 //
9449 //
9450 // CHECK18-LABEL: define {{[^@]+}}@_ZL7fstatici
9451 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
9452 // CHECK18-NEXT:  entry:
9453 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9454 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
9455 // CHECK18-NEXT:    [[AA:%.*]] = alloca i16, align 2
9456 // CHECK18-NEXT:    [[AAA:%.*]] = alloca i8, align 1
9457 // CHECK18-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9458 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9459 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9460 // CHECK18-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
9461 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8
9462 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8
9463 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8
9464 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9465 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
9466 // CHECK18-NEXT:    store i16 0, i16* [[AA]], align 2
9467 // CHECK18-NEXT:    store i8 0, i8* [[AAA]], align 1
9468 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
9469 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9470 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
9471 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9472 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
9473 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9474 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
9475 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9476 // CHECK18-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
9477 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
9478 // CHECK18-NEXT:    store i8 [[TMP4]], i8* [[CONV2]], align 1
9479 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
9480 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
9481 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
9482 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9483 // CHECK18:       omp_if.then:
9484 // CHECK18-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9485 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
9486 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
9487 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9488 // CHECK18-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64*
9489 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP10]], align 8
9490 // CHECK18-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
9491 // CHECK18-NEXT:    store i8* null, i8** [[TMP11]], align 8
9492 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
9493 // CHECK18-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
9494 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
9495 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
9496 // CHECK18-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i64*
9497 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP15]], align 8
9498 // CHECK18-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
9499 // CHECK18-NEXT:    store i8* null, i8** [[TMP16]], align 8
9500 // CHECK18-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
9501 // CHECK18-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i64*
9502 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP18]], align 8
9503 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
9504 // CHECK18-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64*
9505 // CHECK18-NEXT:    store i64 [[TMP5]], i64* [[TMP20]], align 8
9506 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9507 // CHECK18-NEXT:    store i8* null, i8** [[TMP21]], align 8
9508 // CHECK18-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
9509 // CHECK18-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
9510 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 8
9511 // CHECK18-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
9512 // CHECK18-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
9513 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 8
9514 // CHECK18-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3
9515 // CHECK18-NEXT:    store i8* null, i8** [[TMP26]], align 8
9516 // CHECK18-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9517 // CHECK18-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9518 // CHECK18-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
9519 // CHECK18-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
9520 // CHECK18-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9521 // CHECK18:       omp_offload.failed:
9522 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
9523 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
9524 // CHECK18:       omp_offload.cont:
9525 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
9526 // CHECK18:       omp_if.else:
9527 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i64 [[TMP1]], i64 [[TMP3]], i64 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
9528 // CHECK18-NEXT:    br label [[OMP_IF_END]]
9529 // CHECK18:       omp_if.end:
9530 // CHECK18-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
9531 // CHECK18-NEXT:    ret i32 [[TMP31]]
9532 //
9533 //
9534 // CHECK18-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
9535 // CHECK18-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
9536 // CHECK18-NEXT:  entry:
9537 // CHECK18-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9538 // CHECK18-NEXT:    [[A:%.*]] = alloca i32, align 4
9539 // CHECK18-NEXT:    [[AA:%.*]] = alloca i16, align 2
9540 // CHECK18-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
9541 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9542 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9543 // CHECK18-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 8
9544 // CHECK18-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 8
9545 // CHECK18-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 8
9546 // CHECK18-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9547 // CHECK18-NEXT:    store i32 0, i32* [[A]], align 4
9548 // CHECK18-NEXT:    store i16 0, i16* [[AA]], align 2
9549 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
9550 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9551 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[CONV]], align 4
9552 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
9553 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
9554 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9555 // CHECK18-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
9556 // CHECK18-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9557 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
9558 // CHECK18-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
9559 // CHECK18-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9560 // CHECK18:       omp_if.then:
9561 // CHECK18-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9562 // CHECK18-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i64*
9563 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP6]], align 8
9564 // CHECK18-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9565 // CHECK18-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i64*
9566 // CHECK18-NEXT:    store i64 [[TMP1]], i64* [[TMP8]], align 8
9567 // CHECK18-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0
9568 // CHECK18-NEXT:    store i8* null, i8** [[TMP9]], align 8
9569 // CHECK18-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
9570 // CHECK18-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i64*
9571 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP11]], align 8
9572 // CHECK18-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
9573 // CHECK18-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i64*
9574 // CHECK18-NEXT:    store i64 [[TMP3]], i64* [[TMP13]], align 8
9575 // CHECK18-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1
9576 // CHECK18-NEXT:    store i8* null, i8** [[TMP14]], align 8
9577 // CHECK18-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
9578 // CHECK18-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
9579 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 8
9580 // CHECK18-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
9581 // CHECK18-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
9582 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 8
9583 // CHECK18-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2
9584 // CHECK18-NEXT:    store i8* null, i8** [[TMP19]], align 8
9585 // CHECK18-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9586 // CHECK18-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9587 // CHECK18-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
9588 // CHECK18-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
9589 // CHECK18-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9590 // CHECK18:       omp_offload.failed:
9591 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
9592 // CHECK18-NEXT:    br label [[OMP_OFFLOAD_CONT]]
9593 // CHECK18:       omp_offload.cont:
9594 // CHECK18-NEXT:    br label [[OMP_IF_END:%.*]]
9595 // CHECK18:       omp_if.else:
9596 // CHECK18-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i64 [[TMP1]], i64 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
9597 // CHECK18-NEXT:    br label [[OMP_IF_END]]
9598 // CHECK18:       omp_if.end:
9599 // CHECK18-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
9600 // CHECK18-NEXT:    ret i32 [[TMP24]]
9601 //
9602 //
9603 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
9604 // CHECK18-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
9605 // CHECK18-NEXT:  entry:
9606 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9607 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
9608 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9609 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9610 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
9611 // CHECK18-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
9612 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9613 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
9614 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9615 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9616 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
9617 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9618 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9619 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9620 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9621 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9622 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
9623 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
9624 // CHECK18-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
9625 // CHECK18-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
9626 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
9627 // CHECK18-NEXT:    ret void
9628 //
9629 //
9630 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..9
9631 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
9632 // CHECK18-NEXT:  entry:
9633 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9634 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9635 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
9636 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
9637 // CHECK18-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
9638 // CHECK18-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
9639 // CHECK18-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
9640 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9641 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9642 // CHECK18-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
9643 // CHECK18-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
9644 // CHECK18-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
9645 // CHECK18-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
9646 // CHECK18-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
9647 // CHECK18-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
9648 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
9649 // CHECK18-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
9650 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
9651 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
9652 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
9653 // CHECK18-NEXT:    [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
9654 // CHECK18-NEXT:    [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
9655 // CHECK18-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
9656 // CHECK18-NEXT:    store double [[ADD]], double* [[A]], align 8
9657 // CHECK18-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
9658 // CHECK18-NEXT:    [[TMP5:%.*]] = load double, double* [[A4]], align 8
9659 // CHECK18-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
9660 // CHECK18-NEXT:    store double [[INC]], double* [[A4]], align 8
9661 // CHECK18-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
9662 // CHECK18-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
9663 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
9664 // CHECK18-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
9665 // CHECK18-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
9666 // CHECK18-NEXT:    ret void
9667 //
9668 //
9669 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
9670 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9671 // CHECK18-NEXT:  entry:
9672 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9673 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9674 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
9675 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9676 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9677 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9678 // CHECK18-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
9679 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9680 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9681 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9682 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9683 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9684 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9685 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9686 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9687 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9688 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9689 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
9690 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
9691 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
9692 // CHECK18-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9693 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
9694 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9695 // CHECK18-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
9696 // CHECK18-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
9697 // CHECK18-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
9698 // CHECK18-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
9699 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
9700 // CHECK18-NEXT:    ret void
9701 //
9702 //
9703 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..11
9704 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9705 // CHECK18-NEXT:  entry:
9706 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9707 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9708 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9709 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9710 // CHECK18-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
9711 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9712 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9713 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9714 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9715 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9716 // CHECK18-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
9717 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9718 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9719 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9720 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
9721 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9722 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9723 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
9724 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
9725 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
9726 // CHECK18-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
9727 // CHECK18-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
9728 // CHECK18-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
9729 // CHECK18-NEXT:    store i16 [[CONV5]], i16* [[CONV1]], align 8
9730 // CHECK18-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
9731 // CHECK18-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
9732 // CHECK18-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
9733 // CHECK18-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
9734 // CHECK18-NEXT:    store i8 [[CONV8]], i8* [[CONV2]], align 8
9735 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9736 // CHECK18-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
9737 // CHECK18-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
9738 // CHECK18-NEXT:    store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
9739 // CHECK18-NEXT:    ret void
9740 //
9741 //
9742 // CHECK18-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
9743 // CHECK18-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9744 // CHECK18-NEXT:  entry:
9745 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9746 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9747 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9748 // CHECK18-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
9749 // CHECK18-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
9750 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9751 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9752 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9753 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9754 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9755 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9756 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9757 // CHECK18-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
9758 // CHECK18-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
9759 // CHECK18-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
9760 // CHECK18-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
9761 // CHECK18-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
9762 // CHECK18-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
9763 // CHECK18-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
9764 // CHECK18-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
9765 // CHECK18-NEXT:    ret void
9766 //
9767 //
9768 // CHECK18-LABEL: define {{[^@]+}}@.omp_outlined..14
9769 // CHECK18-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
9770 // CHECK18-NEXT:  entry:
9771 // CHECK18-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
9772 // CHECK18-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
9773 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
9774 // CHECK18-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
9775 // CHECK18-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
9776 // CHECK18-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
9777 // CHECK18-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
9778 // CHECK18-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
9779 // CHECK18-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
9780 // CHECK18-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
9781 // CHECK18-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
9782 // CHECK18-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
9783 // CHECK18-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
9784 // CHECK18-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
9785 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
9786 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
9787 // CHECK18-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
9788 // CHECK18-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
9789 // CHECK18-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
9790 // CHECK18-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
9791 // CHECK18-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
9792 // CHECK18-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
9793 // CHECK18-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
9794 // CHECK18-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
9795 // CHECK18-NEXT:    store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
9796 // CHECK18-NEXT:    ret void
9797 //
9798 //
9799 // CHECK18-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
9800 // CHECK18-SAME: () #[[ATTR5:[0-9]+]] {
9801 // CHECK18-NEXT:  entry:
9802 // CHECK18-NEXT:    call void @__tgt_register_requires(i64 1)
9803 // CHECK18-NEXT:    ret void
9804 //
9805 //
9806 // CHECK19-LABEL: define {{[^@]+}}@_Z3fooi
9807 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
9808 // CHECK19-NEXT:  entry:
9809 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
9810 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
9811 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
9812 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
9813 // CHECK19-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
9814 // CHECK19-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
9815 // CHECK19-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
9816 // CHECK19-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
9817 // CHECK19-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
9818 // CHECK19-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
9819 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
9820 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
9821 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
9822 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
9823 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
9824 // CHECK19-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
9825 // CHECK19-NEXT:    [[AA_CASTED3:%.*]] = alloca i32, align 4
9826 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4
9827 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4
9828 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4
9829 // CHECK19-NEXT:    [[A_CASTED10:%.*]] = alloca i32, align 4
9830 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4
9831 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4
9832 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4
9833 // CHECK19-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
9834 // CHECK19-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
9835 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
9836 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
9837 // CHECK19-NEXT:    store i16 0, i16* [[AA]], align 2
9838 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
9839 // CHECK19-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
9840 // CHECK19-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
9841 // CHECK19-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
9842 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
9843 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
9844 // CHECK19-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
9845 // CHECK19-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
9846 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
9847 // CHECK19-NEXT:    [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
9848 // CHECK19-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
9849 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
9850 // CHECK19-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]])
9851 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
9852 // CHECK19-NEXT:    store i32 [[TMP9]], i32* [[A_CASTED]], align 4
9853 // CHECK19-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
9854 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR3:[0-9]+]]
9855 // CHECK19-NEXT:    [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
9856 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
9857 // CHECK19-NEXT:    store i16 [[TMP11]], i16* [[CONV]], align 2
9858 // CHECK19-NEXT:    [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
9859 // CHECK19-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9860 // CHECK19-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
9861 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[TMP14]], align 4
9862 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9863 // CHECK19-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
9864 // CHECK19-NEXT:    store i32 [[TMP12]], i32* [[TMP16]], align 4
9865 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
9866 // CHECK19-NEXT:    store i8* null, i8** [[TMP17]], align 4
9867 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
9868 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
9869 // CHECK19-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
9870 // CHECK19-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
9871 // CHECK19-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
9872 // CHECK19:       omp_offload.failed:
9873 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR3]]
9874 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
9875 // CHECK19:       omp_offload.cont:
9876 // CHECK19-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
9877 // CHECK19-NEXT:    store i32 [[TMP22]], i32* [[A_CASTED2]], align 4
9878 // CHECK19-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4
9879 // CHECK19-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2
9880 // CHECK19-NEXT:    [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16*
9881 // CHECK19-NEXT:    store i16 [[TMP24]], i16* [[CONV4]], align 2
9882 // CHECK19-NEXT:    [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4
9883 // CHECK19-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
9884 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10
9885 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
9886 // CHECK19:       omp_if.then:
9887 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
9888 // CHECK19-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
9889 // CHECK19-NEXT:    store i32 [[TMP23]], i32* [[TMP28]], align 4
9890 // CHECK19-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
9891 // CHECK19-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
9892 // CHECK19-NEXT:    store i32 [[TMP23]], i32* [[TMP30]], align 4
9893 // CHECK19-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
9894 // CHECK19-NEXT:    store i8* null, i8** [[TMP31]], align 4
9895 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
9896 // CHECK19-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32*
9897 // CHECK19-NEXT:    store i32 [[TMP25]], i32* [[TMP33]], align 4
9898 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
9899 // CHECK19-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32*
9900 // CHECK19-NEXT:    store i32 [[TMP25]], i32* [[TMP35]], align 4
9901 // CHECK19-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1
9902 // CHECK19-NEXT:    store i8* null, i8** [[TMP36]], align 4
9903 // CHECK19-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
9904 // CHECK19-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
9905 // CHECK19-NEXT:    [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
9906 // CHECK19-NEXT:    [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
9907 // CHECK19-NEXT:    br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
9908 // CHECK19:       omp_offload.failed8:
9909 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]]
9910 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT9]]
9911 // CHECK19:       omp_offload.cont9:
9912 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
9913 // CHECK19:       omp_if.else:
9914 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]]
9915 // CHECK19-NEXT:    br label [[OMP_IF_END]]
9916 // CHECK19:       omp_if.end:
9917 // CHECK19-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4
9918 // CHECK19-NEXT:    store i32 [[TMP41]], i32* [[A_CASTED10]], align 4
9919 // CHECK19-NEXT:    [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4
9920 // CHECK19-NEXT:    [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4
9921 // CHECK19-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20
9922 // CHECK19-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]]
9923 // CHECK19:       omp_if.then12:
9924 // CHECK19-NEXT:    [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4
9925 // CHECK19-NEXT:    [[TMP45:%.*]] = sext i32 [[TMP44]] to i64
9926 // CHECK19-NEXT:    [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]]
9927 // CHECK19-NEXT:    [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8
9928 // CHECK19-NEXT:    [[TMP48:%.*]] = sext i32 [[TMP47]] to i64
9929 // CHECK19-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
9930 // CHECK19-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
9931 // CHECK19-NEXT:    store i32 [[TMP42]], i32* [[TMP50]], align 4
9932 // CHECK19-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
9933 // CHECK19-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
9934 // CHECK19-NEXT:    store i32 [[TMP42]], i32* [[TMP52]], align 4
9935 // CHECK19-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
9936 // CHECK19-NEXT:    store i64 4, i64* [[TMP53]], align 4
9937 // CHECK19-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
9938 // CHECK19-NEXT:    store i8* null, i8** [[TMP54]], align 4
9939 // CHECK19-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
9940 // CHECK19-NEXT:    [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]**
9941 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4
9942 // CHECK19-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
9943 // CHECK19-NEXT:    [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]**
9944 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4
9945 // CHECK19-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
9946 // CHECK19-NEXT:    store i64 40, i64* [[TMP59]], align 4
9947 // CHECK19-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1
9948 // CHECK19-NEXT:    store i8* null, i8** [[TMP60]], align 4
9949 // CHECK19-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2
9950 // CHECK19-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
9951 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP62]], align 4
9952 // CHECK19-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2
9953 // CHECK19-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*
9954 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP64]], align 4
9955 // CHECK19-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
9956 // CHECK19-NEXT:    store i64 4, i64* [[TMP65]], align 4
9957 // CHECK19-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2
9958 // CHECK19-NEXT:    store i8* null, i8** [[TMP66]], align 4
9959 // CHECK19-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3
9960 // CHECK19-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float**
9961 // CHECK19-NEXT:    store float* [[VLA]], float** [[TMP68]], align 4
9962 // CHECK19-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3
9963 // CHECK19-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float**
9964 // CHECK19-NEXT:    store float* [[VLA]], float** [[TMP70]], align 4
9965 // CHECK19-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
9966 // CHECK19-NEXT:    store i64 [[TMP45]], i64* [[TMP71]], align 4
9967 // CHECK19-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3
9968 // CHECK19-NEXT:    store i8* null, i8** [[TMP72]], align 4
9969 // CHECK19-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4
9970 // CHECK19-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]**
9971 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4
9972 // CHECK19-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4
9973 // CHECK19-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]**
9974 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4
9975 // CHECK19-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
9976 // CHECK19-NEXT:    store i64 400, i64* [[TMP77]], align 4
9977 // CHECK19-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4
9978 // CHECK19-NEXT:    store i8* null, i8** [[TMP78]], align 4
9979 // CHECK19-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5
9980 // CHECK19-NEXT:    [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*
9981 // CHECK19-NEXT:    store i32 5, i32* [[TMP80]], align 4
9982 // CHECK19-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5
9983 // CHECK19-NEXT:    [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32*
9984 // CHECK19-NEXT:    store i32 5, i32* [[TMP82]], align 4
9985 // CHECK19-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
9986 // CHECK19-NEXT:    store i64 4, i64* [[TMP83]], align 4
9987 // CHECK19-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5
9988 // CHECK19-NEXT:    store i8* null, i8** [[TMP84]], align 4
9989 // CHECK19-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6
9990 // CHECK19-NEXT:    [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32*
9991 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP86]], align 4
9992 // CHECK19-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6
9993 // CHECK19-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
9994 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP88]], align 4
9995 // CHECK19-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
9996 // CHECK19-NEXT:    store i64 4, i64* [[TMP89]], align 4
9997 // CHECK19-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6
9998 // CHECK19-NEXT:    store i8* null, i8** [[TMP90]], align 4
9999 // CHECK19-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7
10000 // CHECK19-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double**
10001 // CHECK19-NEXT:    store double* [[VLA1]], double** [[TMP92]], align 4
10002 // CHECK19-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7
10003 // CHECK19-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double**
10004 // CHECK19-NEXT:    store double* [[VLA1]], double** [[TMP94]], align 4
10005 // CHECK19-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
10006 // CHECK19-NEXT:    store i64 [[TMP48]], i64* [[TMP95]], align 4
10007 // CHECK19-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7
10008 // CHECK19-NEXT:    store i8* null, i8** [[TMP96]], align 4
10009 // CHECK19-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8
10010 // CHECK19-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT**
10011 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4
10012 // CHECK19-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8
10013 // CHECK19-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT**
10014 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4
10015 // CHECK19-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
10016 // CHECK19-NEXT:    store i64 12, i64* [[TMP101]], align 4
10017 // CHECK19-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8
10018 // CHECK19-NEXT:    store i8* null, i8** [[TMP102]], align 4
10019 // CHECK19-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
10020 // CHECK19-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
10021 // CHECK19-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10022 // CHECK19-NEXT:    [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
10023 // CHECK19-NEXT:    [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0
10024 // CHECK19-NEXT:    br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
10025 // CHECK19:       omp_offload.failed16:
10026 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
10027 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
10028 // CHECK19:       omp_offload.cont17:
10029 // CHECK19-NEXT:    br label [[OMP_IF_END19:%.*]]
10030 // CHECK19:       omp_if.else18:
10031 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
10032 // CHECK19-NEXT:    br label [[OMP_IF_END19]]
10033 // CHECK19:       omp_if.end19:
10034 // CHECK19-NEXT:    [[TMP108:%.*]] = load i32, i32* [[A]], align 4
10035 // CHECK19-NEXT:    [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
10036 // CHECK19-NEXT:    call void @llvm.stackrestore(i8* [[TMP109]])
10037 // CHECK19-NEXT:    ret i32 [[TMP108]]
10038 //
10039 //
10040 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
10041 // CHECK19-SAME: () #[[ATTR2:[0-9]+]] {
10042 // CHECK19-NEXT:  entry:
10043 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
10044 // CHECK19-NEXT:    ret void
10045 //
10046 //
10047 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined.
10048 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
10049 // CHECK19-NEXT:  entry:
10050 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10051 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10052 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10053 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10054 // CHECK19-NEXT:    ret void
10055 //
10056 //
10057 // CHECK19-LABEL: define {{[^@]+}}@.omp_task_entry.
10058 // CHECK19-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
10059 // CHECK19-NEXT:  entry:
10060 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
10061 // CHECK19-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
10062 // CHECK19-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
10063 // CHECK19-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
10064 // CHECK19-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
10065 // CHECK19-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
10066 // CHECK19-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
10067 // CHECK19-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
10068 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
10069 // CHECK19-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
10070 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
10071 // CHECK19-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
10072 // CHECK19-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
10073 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
10074 // CHECK19-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
10075 // CHECK19-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
10076 // CHECK19-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
10077 // CHECK19-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
10078 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
10079 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
10080 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
10081 // CHECK19-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
10082 // CHECK19-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
10083 // CHECK19-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21
10084 // CHECK19-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
10085 // CHECK19-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
10086 // CHECK19-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21
10087 // CHECK19-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
10088 // CHECK19-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
10089 // CHECK19-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
10090 // CHECK19-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
10091 // CHECK19-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
10092 // CHECK19:       omp_offload.failed.i:
10093 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
10094 // CHECK19-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
10095 // CHECK19:       .omp_outlined..1.exit:
10096 // CHECK19-NEXT:    ret i32 0
10097 //
10098 //
10099 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
10100 // CHECK19-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
10101 // CHECK19-NEXT:  entry:
10102 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10103 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10104 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10105 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
10106 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
10107 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
10108 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
10109 // CHECK19-NEXT:    ret void
10110 //
10111 //
10112 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..2
10113 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
10114 // CHECK19-NEXT:  entry:
10115 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10116 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10117 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10118 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10119 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10120 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10121 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
10122 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
10123 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
10124 // CHECK19-NEXT:    ret void
10125 //
10126 //
10127 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
10128 // CHECK19-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
10129 // CHECK19-NEXT:  entry:
10130 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10131 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10132 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10133 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10134 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
10135 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10136 // CHECK19-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
10137 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10138 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
10139 // CHECK19-NEXT:    ret void
10140 //
10141 //
10142 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..3
10143 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
10144 // CHECK19-NEXT:  entry:
10145 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10146 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10147 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10148 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10149 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10150 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10151 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10152 // CHECK19-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
10153 // CHECK19-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
10154 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
10155 // CHECK19-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
10156 // CHECK19-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 4
10157 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
10158 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
10159 // CHECK19-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
10160 // CHECK19-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
10161 // CHECK19-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
10162 // CHECK19:       .cancel.exit:
10163 // CHECK19-NEXT:    br label [[DOTCANCEL_CONTINUE]]
10164 // CHECK19:       .cancel.continue:
10165 // CHECK19-NEXT:    ret void
10166 //
10167 //
10168 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
10169 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
10170 // CHECK19-NEXT:  entry:
10171 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10172 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10173 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10174 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10175 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10176 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10177 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10178 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
10179 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
10180 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
10181 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
10182 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10183 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
10184 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10185 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
10186 // CHECK19-NEXT:    ret void
10187 //
10188 //
10189 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..4
10190 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
10191 // CHECK19-NEXT:  entry:
10192 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10193 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10194 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10195 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10196 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10197 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10198 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10199 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10200 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10201 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
10202 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
10203 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
10204 // CHECK19-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
10205 // CHECK19-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
10206 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
10207 // CHECK19-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
10208 // CHECK19-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
10209 // CHECK19-NEXT:    ret void
10210 //
10211 //
10212 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
10213 // CHECK19-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
10214 // CHECK19-NEXT:  entry:
10215 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10216 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
10217 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10218 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
10219 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
10220 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10221 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10222 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
10223 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
10224 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10225 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10226 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
10227 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10228 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
10229 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
10230 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10231 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
10232 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
10233 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
10234 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
10235 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10236 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
10237 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
10238 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10239 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
10240 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
10241 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
10242 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
10243 // CHECK19-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
10244 // CHECK19-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
10245 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
10246 // CHECK19-NEXT:    ret void
10247 //
10248 //
10249 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..7
10250 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
10251 // CHECK19-NEXT:  entry:
10252 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10253 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10254 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10255 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
10256 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10257 // CHECK19-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
10258 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
10259 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10260 // CHECK19-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
10261 // CHECK19-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
10262 // CHECK19-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
10263 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10264 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10265 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10266 // CHECK19-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
10267 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10268 // CHECK19-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
10269 // CHECK19-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
10270 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10271 // CHECK19-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
10272 // CHECK19-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
10273 // CHECK19-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
10274 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
10275 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10276 // CHECK19-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
10277 // CHECK19-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
10278 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10279 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
10280 // CHECK19-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
10281 // CHECK19-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
10282 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
10283 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
10284 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
10285 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
10286 // CHECK19-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
10287 // CHECK19-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
10288 // CHECK19-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
10289 // CHECK19-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
10290 // CHECK19-NEXT:    store float [[CONV6]], float* [[ARRAYIDX]], align 4
10291 // CHECK19-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
10292 // CHECK19-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
10293 // CHECK19-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
10294 // CHECK19-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
10295 // CHECK19-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
10296 // CHECK19-NEXT:    store float [[CONV10]], float* [[ARRAYIDX7]], align 4
10297 // CHECK19-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
10298 // CHECK19-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
10299 // CHECK19-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
10300 // CHECK19-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
10301 // CHECK19-NEXT:    store double [[ADD13]], double* [[ARRAYIDX12]], align 8
10302 // CHECK19-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
10303 // CHECK19-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
10304 // CHECK19-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
10305 // CHECK19-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
10306 // CHECK19-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
10307 // CHECK19-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
10308 // CHECK19-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
10309 // CHECK19-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
10310 // CHECK19-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
10311 // CHECK19-NEXT:    store i64 [[ADD17]], i64* [[X]], align 4
10312 // CHECK19-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
10313 // CHECK19-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
10314 // CHECK19-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
10315 // CHECK19-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
10316 // CHECK19-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
10317 // CHECK19-NEXT:    store i8 [[CONV20]], i8* [[Y]], align 4
10318 // CHECK19-NEXT:    ret void
10319 //
10320 //
10321 // CHECK19-LABEL: define {{[^@]+}}@_Z3bari
10322 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
10323 // CHECK19-NEXT:  entry:
10324 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10325 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
10326 // CHECK19-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
10327 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10328 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
10329 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
10330 // CHECK19-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
10331 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
10332 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
10333 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
10334 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
10335 // CHECK19-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
10336 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
10337 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
10338 // CHECK19-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
10339 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
10340 // CHECK19-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
10341 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
10342 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
10343 // CHECK19-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
10344 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
10345 // CHECK19-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
10346 // CHECK19-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
10347 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
10348 // CHECK19-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
10349 // CHECK19-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
10350 // CHECK19-NEXT:    ret i32 [[TMP8]]
10351 //
10352 //
10353 // CHECK19-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
10354 // CHECK19-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
10355 // CHECK19-NEXT:  entry:
10356 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
10357 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10358 // CHECK19-NEXT:    [[B:%.*]] = alloca i32, align 4
10359 // CHECK19-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
10360 // CHECK19-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
10361 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
10362 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
10363 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
10364 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
10365 // CHECK19-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
10366 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
10367 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10368 // CHECK19-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
10369 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
10370 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
10371 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
10372 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
10373 // CHECK19-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
10374 // CHECK19-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
10375 // CHECK19-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
10376 // CHECK19-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
10377 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
10378 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
10379 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
10380 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
10381 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
10382 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
10383 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10384 // CHECK19:       omp_if.then:
10385 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
10386 // CHECK19-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
10387 // CHECK19-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
10388 // CHECK19-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
10389 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10390 // CHECK19-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
10391 // CHECK19-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
10392 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10393 // CHECK19-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
10394 // CHECK19-NEXT:    store double* [[A]], double** [[TMP13]], align 4
10395 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10396 // CHECK19-NEXT:    store i64 8, i64* [[TMP14]], align 4
10397 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
10398 // CHECK19-NEXT:    store i8* null, i8** [[TMP15]], align 4
10399 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10400 // CHECK19-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
10401 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
10402 // CHECK19-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10403 // CHECK19-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
10404 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
10405 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
10406 // CHECK19-NEXT:    store i64 4, i64* [[TMP20]], align 4
10407 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
10408 // CHECK19-NEXT:    store i8* null, i8** [[TMP21]], align 4
10409 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10410 // CHECK19-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
10411 // CHECK19-NEXT:    store i32 2, i32* [[TMP23]], align 4
10412 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10413 // CHECK19-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
10414 // CHECK19-NEXT:    store i32 2, i32* [[TMP25]], align 4
10415 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
10416 // CHECK19-NEXT:    store i64 4, i64* [[TMP26]], align 4
10417 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
10418 // CHECK19-NEXT:    store i8* null, i8** [[TMP27]], align 4
10419 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
10420 // CHECK19-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
10421 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
10422 // CHECK19-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
10423 // CHECK19-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
10424 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
10425 // CHECK19-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
10426 // CHECK19-NEXT:    store i64 4, i64* [[TMP32]], align 4
10427 // CHECK19-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
10428 // CHECK19-NEXT:    store i8* null, i8** [[TMP33]], align 4
10429 // CHECK19-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
10430 // CHECK19-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
10431 // CHECK19-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
10432 // CHECK19-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
10433 // CHECK19-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
10434 // CHECK19-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
10435 // CHECK19-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
10436 // CHECK19-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
10437 // CHECK19-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
10438 // CHECK19-NEXT:    store i8* null, i8** [[TMP39]], align 4
10439 // CHECK19-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10440 // CHECK19-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10441 // CHECK19-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10442 // CHECK19-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
10443 // CHECK19-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
10444 // CHECK19-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10445 // CHECK19:       omp_offload.failed:
10446 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
10447 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
10448 // CHECK19:       omp_offload.cont:
10449 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
10450 // CHECK19:       omp_if.else:
10451 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
10452 // CHECK19-NEXT:    br label [[OMP_IF_END]]
10453 // CHECK19:       omp_if.end:
10454 // CHECK19-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
10455 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
10456 // CHECK19-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
10457 // CHECK19-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
10458 // CHECK19-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
10459 // CHECK19-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
10460 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
10461 // CHECK19-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
10462 // CHECK19-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
10463 // CHECK19-NEXT:    ret i32 [[ADD3]]
10464 //
10465 //
10466 // CHECK19-LABEL: define {{[^@]+}}@_ZL7fstatici
10467 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
10468 // CHECK19-NEXT:  entry:
10469 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10470 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
10471 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
10472 // CHECK19-NEXT:    [[AAA:%.*]] = alloca i8, align 1
10473 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
10474 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10475 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10476 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
10477 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
10478 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
10479 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
10480 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10481 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
10482 // CHECK19-NEXT:    store i16 0, i16* [[AA]], align 2
10483 // CHECK19-NEXT:    store i8 0, i8* [[AAA]], align 1
10484 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
10485 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
10486 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
10487 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
10488 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10489 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
10490 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10491 // CHECK19-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
10492 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
10493 // CHECK19-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
10494 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
10495 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
10496 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
10497 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10498 // CHECK19:       omp_if.then:
10499 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10500 // CHECK19-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
10501 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
10502 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10503 // CHECK19-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
10504 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
10505 // CHECK19-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
10506 // CHECK19-NEXT:    store i8* null, i8** [[TMP11]], align 4
10507 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10508 // CHECK19-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
10509 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
10510 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10511 // CHECK19-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
10512 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
10513 // CHECK19-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
10514 // CHECK19-NEXT:    store i8* null, i8** [[TMP16]], align 4
10515 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10516 // CHECK19-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
10517 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
10518 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10519 // CHECK19-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
10520 // CHECK19-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
10521 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
10522 // CHECK19-NEXT:    store i8* null, i8** [[TMP21]], align 4
10523 // CHECK19-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
10524 // CHECK19-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
10525 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
10526 // CHECK19-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
10527 // CHECK19-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
10528 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
10529 // CHECK19-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
10530 // CHECK19-NEXT:    store i8* null, i8** [[TMP26]], align 4
10531 // CHECK19-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10532 // CHECK19-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10533 // CHECK19-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
10534 // CHECK19-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
10535 // CHECK19-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10536 // CHECK19:       omp_offload.failed:
10537 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
10538 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
10539 // CHECK19:       omp_offload.cont:
10540 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
10541 // CHECK19:       omp_if.else:
10542 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
10543 // CHECK19-NEXT:    br label [[OMP_IF_END]]
10544 // CHECK19:       omp_if.end:
10545 // CHECK19-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
10546 // CHECK19-NEXT:    ret i32 [[TMP31]]
10547 //
10548 //
10549 // CHECK19-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
10550 // CHECK19-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
10551 // CHECK19-NEXT:  entry:
10552 // CHECK19-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10553 // CHECK19-NEXT:    [[A:%.*]] = alloca i32, align 4
10554 // CHECK19-NEXT:    [[AA:%.*]] = alloca i16, align 2
10555 // CHECK19-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
10556 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10557 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10558 // CHECK19-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
10559 // CHECK19-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
10560 // CHECK19-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
10561 // CHECK19-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10562 // CHECK19-NEXT:    store i32 0, i32* [[A]], align 4
10563 // CHECK19-NEXT:    store i16 0, i16* [[AA]], align 2
10564 // CHECK19-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
10565 // CHECK19-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
10566 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
10567 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
10568 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10569 // CHECK19-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
10570 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10571 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
10572 // CHECK19-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
10573 // CHECK19-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10574 // CHECK19:       omp_if.then:
10575 // CHECK19-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10576 // CHECK19-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
10577 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
10578 // CHECK19-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10579 // CHECK19-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
10580 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
10581 // CHECK19-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
10582 // CHECK19-NEXT:    store i8* null, i8** [[TMP9]], align 4
10583 // CHECK19-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
10584 // CHECK19-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
10585 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
10586 // CHECK19-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
10587 // CHECK19-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
10588 // CHECK19-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
10589 // CHECK19-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
10590 // CHECK19-NEXT:    store i8* null, i8** [[TMP14]], align 4
10591 // CHECK19-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
10592 // CHECK19-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
10593 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
10594 // CHECK19-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
10595 // CHECK19-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
10596 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
10597 // CHECK19-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
10598 // CHECK19-NEXT:    store i8* null, i8** [[TMP19]], align 4
10599 // CHECK19-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10600 // CHECK19-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10601 // CHECK19-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
10602 // CHECK19-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
10603 // CHECK19-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10604 // CHECK19:       omp_offload.failed:
10605 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
10606 // CHECK19-NEXT:    br label [[OMP_OFFLOAD_CONT]]
10607 // CHECK19:       omp_offload.cont:
10608 // CHECK19-NEXT:    br label [[OMP_IF_END:%.*]]
10609 // CHECK19:       omp_if.else:
10610 // CHECK19-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
10611 // CHECK19-NEXT:    br label [[OMP_IF_END]]
10612 // CHECK19:       omp_if.end:
10613 // CHECK19-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
10614 // CHECK19-NEXT:    ret i32 [[TMP24]]
10615 //
10616 //
10617 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
10618 // CHECK19-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
10619 // CHECK19-NEXT:  entry:
10620 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
10621 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
10622 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10623 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10624 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
10625 // CHECK19-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
10626 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
10627 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
10628 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10629 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10630 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
10631 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
10632 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10633 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10634 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
10635 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
10636 // CHECK19-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
10637 // CHECK19-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
10638 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
10639 // CHECK19-NEXT:    ret void
10640 //
10641 //
10642 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..9
10643 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
10644 // CHECK19-NEXT:  entry:
10645 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10646 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10647 // CHECK19-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
10648 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
10649 // CHECK19-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
10650 // CHECK19-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
10651 // CHECK19-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
10652 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10653 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10654 // CHECK19-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
10655 // CHECK19-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
10656 // CHECK19-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
10657 // CHECK19-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
10658 // CHECK19-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
10659 // CHECK19-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
10660 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
10661 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
10662 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
10663 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
10664 // CHECK19-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
10665 // CHECK19-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
10666 // CHECK19-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
10667 // CHECK19-NEXT:    store double [[ADD]], double* [[A]], align 4
10668 // CHECK19-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
10669 // CHECK19-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
10670 // CHECK19-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
10671 // CHECK19-NEXT:    store double [[INC]], double* [[A3]], align 4
10672 // CHECK19-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
10673 // CHECK19-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
10674 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
10675 // CHECK19-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
10676 // CHECK19-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
10677 // CHECK19-NEXT:    ret void
10678 //
10679 //
10680 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
10681 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10682 // CHECK19-NEXT:  entry:
10683 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10684 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10685 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
10686 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10687 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10688 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10689 // CHECK19-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
10690 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10691 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10692 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
10693 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10694 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10695 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
10696 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10697 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10698 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
10699 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
10700 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
10701 // CHECK19-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10702 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
10703 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10704 // CHECK19-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
10705 // CHECK19-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
10706 // CHECK19-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
10707 // CHECK19-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
10708 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
10709 // CHECK19-NEXT:    ret void
10710 //
10711 //
10712 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..11
10713 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10714 // CHECK19-NEXT:  entry:
10715 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10716 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10717 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10718 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10719 // CHECK19-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
10720 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10721 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10722 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10723 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10724 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10725 // CHECK19-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
10726 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10727 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10728 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
10729 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10730 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10731 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
10732 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
10733 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
10734 // CHECK19-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
10735 // CHECK19-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
10736 // CHECK19-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
10737 // CHECK19-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
10738 // CHECK19-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
10739 // CHECK19-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
10740 // CHECK19-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
10741 // CHECK19-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
10742 // CHECK19-NEXT:    store i8 [[CONV7]], i8* [[CONV1]], align 4
10743 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
10744 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
10745 // CHECK19-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
10746 // CHECK19-NEXT:    store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
10747 // CHECK19-NEXT:    ret void
10748 //
10749 //
10750 // CHECK19-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
10751 // CHECK19-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10752 // CHECK19-NEXT:  entry:
10753 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10754 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10755 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10756 // CHECK19-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10757 // CHECK19-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10758 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10759 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10760 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10761 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10762 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10763 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10764 // CHECK19-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
10765 // CHECK19-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
10766 // CHECK19-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
10767 // CHECK19-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10768 // CHECK19-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
10769 // CHECK19-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10770 // CHECK19-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
10771 // CHECK19-NEXT:    ret void
10772 //
10773 //
10774 // CHECK19-LABEL: define {{[^@]+}}@.omp_outlined..14
10775 // CHECK19-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
10776 // CHECK19-NEXT:  entry:
10777 // CHECK19-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
10778 // CHECK19-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
10779 // CHECK19-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
10780 // CHECK19-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
10781 // CHECK19-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
10782 // CHECK19-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
10783 // CHECK19-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
10784 // CHECK19-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
10785 // CHECK19-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
10786 // CHECK19-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
10787 // CHECK19-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
10788 // CHECK19-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
10789 // CHECK19-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
10790 // CHECK19-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
10791 // CHECK19-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
10792 // CHECK19-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
10793 // CHECK19-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
10794 // CHECK19-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
10795 // CHECK19-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
10796 // CHECK19-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
10797 // CHECK19-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
10798 // CHECK19-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
10799 // CHECK19-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
10800 // CHECK19-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
10801 // CHECK19-NEXT:    ret void
10802 //
10803 //
10804 // CHECK19-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
10805 // CHECK19-SAME: () #[[ATTR5:[0-9]+]] {
10806 // CHECK19-NEXT:  entry:
10807 // CHECK19-NEXT:    call void @__tgt_register_requires(i64 1)
10808 // CHECK19-NEXT:    ret void
10809 //
10810 //
10811 // CHECK20-LABEL: define {{[^@]+}}@_Z3fooi
10812 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
10813 // CHECK20-NEXT:  entry:
10814 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
10815 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
10816 // CHECK20-NEXT:    [[AA:%.*]] = alloca i16, align 2
10817 // CHECK20-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
10818 // CHECK20-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
10819 // CHECK20-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
10820 // CHECK20-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
10821 // CHECK20-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
10822 // CHECK20-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
10823 // CHECK20-NEXT:    [[AGG_CAPTURED:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1
10824 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
10825 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
10826 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [1 x i8*], align 4
10827 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [1 x i8*], align 4
10828 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [1 x i8*], align 4
10829 // CHECK20-NEXT:    [[A_CASTED2:%.*]] = alloca i32, align 4
10830 // CHECK20-NEXT:    [[AA_CASTED3:%.*]] = alloca i32, align 4
10831 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS5:%.*]] = alloca [2 x i8*], align 4
10832 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS6:%.*]] = alloca [2 x i8*], align 4
10833 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS7:%.*]] = alloca [2 x i8*], align 4
10834 // CHECK20-NEXT:    [[A_CASTED10:%.*]] = alloca i32, align 4
10835 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS13:%.*]] = alloca [9 x i8*], align 4
10836 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS14:%.*]] = alloca [9 x i8*], align 4
10837 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS15:%.*]] = alloca [9 x i8*], align 4
10838 // CHECK20-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [9 x i64], align 4
10839 // CHECK20-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
10840 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
10841 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
10842 // CHECK20-NEXT:    store i16 0, i16* [[AA]], align 2
10843 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
10844 // CHECK20-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
10845 // CHECK20-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
10846 // CHECK20-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP1]], align 4
10847 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
10848 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
10849 // CHECK20-NEXT:    [[TMP4:%.*]] = mul nuw i32 5, [[TMP3]]
10850 // CHECK20-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP4]], align 8
10851 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[__VLA_EXPR1]], align 4
10852 // CHECK20-NEXT:    [[TMP5:%.*]] = call i8* @__kmpc_omp_target_task_alloc(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 1, i32 20, i32 1, i32 (i32, i8*)* bitcast (i32 (i32, %struct.kmp_task_t_with_privates*)* @.omp_task_entry. to i32 (i32, i8*)*), i64 -1)
10853 // CHECK20-NEXT:    [[TMP6:%.*]] = bitcast i8* [[TMP5]] to %struct.kmp_task_t_with_privates*
10854 // CHECK20-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP6]], i32 0, i32 0
10855 // CHECK20-NEXT:    [[TMP8:%.*]] = call i32 @__kmpc_omp_task(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* [[TMP5]])
10856 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A]], align 4
10857 // CHECK20-NEXT:    store i32 [[TMP9]], i32* [[A_CASTED]], align 4
10858 // CHECK20-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A_CASTED]], align 4
10859 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104(i32 [[TMP10]]) #[[ATTR3:[0-9]+]]
10860 // CHECK20-NEXT:    [[TMP11:%.*]] = load i16, i16* [[AA]], align 2
10861 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
10862 // CHECK20-NEXT:    store i16 [[TMP11]], i16* [[CONV]], align 2
10863 // CHECK20-NEXT:    [[TMP12:%.*]] = load i32, i32* [[AA_CASTED]], align 4
10864 // CHECK20-NEXT:    [[TMP13:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10865 // CHECK20-NEXT:    [[TMP14:%.*]] = bitcast i8** [[TMP13]] to i32*
10866 // CHECK20-NEXT:    store i32 [[TMP12]], i32* [[TMP14]], align 4
10867 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10868 // CHECK20-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to i32*
10869 // CHECK20-NEXT:    store i32 [[TMP12]], i32* [[TMP16]], align 4
10870 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
10871 // CHECK20-NEXT:    store i8* null, i8** [[TMP17]], align 4
10872 // CHECK20-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
10873 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
10874 // CHECK20-NEXT:    [[TMP20:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110.region_id, i32 1, i8** [[TMP18]], i8** [[TMP19]], i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([1 x i64], [1 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
10875 // CHECK20-NEXT:    [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0
10876 // CHECK20-NEXT:    br i1 [[TMP21]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
10877 // CHECK20:       omp_offload.failed:
10878 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110(i32 [[TMP12]]) #[[ATTR3]]
10879 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
10880 // CHECK20:       omp_offload.cont:
10881 // CHECK20-NEXT:    [[TMP22:%.*]] = load i32, i32* [[A]], align 4
10882 // CHECK20-NEXT:    store i32 [[TMP22]], i32* [[A_CASTED2]], align 4
10883 // CHECK20-NEXT:    [[TMP23:%.*]] = load i32, i32* [[A_CASTED2]], align 4
10884 // CHECK20-NEXT:    [[TMP24:%.*]] = load i16, i16* [[AA]], align 2
10885 // CHECK20-NEXT:    [[CONV4:%.*]] = bitcast i32* [[AA_CASTED3]] to i16*
10886 // CHECK20-NEXT:    store i16 [[TMP24]], i16* [[CONV4]], align 2
10887 // CHECK20-NEXT:    [[TMP25:%.*]] = load i32, i32* [[AA_CASTED3]], align 4
10888 // CHECK20-NEXT:    [[TMP26:%.*]] = load i32, i32* [[N_ADDR]], align 4
10889 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP26]], 10
10890 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
10891 // CHECK20:       omp_if.then:
10892 // CHECK20-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
10893 // CHECK20-NEXT:    [[TMP28:%.*]] = bitcast i8** [[TMP27]] to i32*
10894 // CHECK20-NEXT:    store i32 [[TMP23]], i32* [[TMP28]], align 4
10895 // CHECK20-NEXT:    [[TMP29:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
10896 // CHECK20-NEXT:    [[TMP30:%.*]] = bitcast i8** [[TMP29]] to i32*
10897 // CHECK20-NEXT:    store i32 [[TMP23]], i32* [[TMP30]], align 4
10898 // CHECK20-NEXT:    [[TMP31:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 0
10899 // CHECK20-NEXT:    store i8* null, i8** [[TMP31]], align 4
10900 // CHECK20-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 1
10901 // CHECK20-NEXT:    [[TMP33:%.*]] = bitcast i8** [[TMP32]] to i32*
10902 // CHECK20-NEXT:    store i32 [[TMP25]], i32* [[TMP33]], align 4
10903 // CHECK20-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 1
10904 // CHECK20-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i32*
10905 // CHECK20-NEXT:    store i32 [[TMP25]], i32* [[TMP35]], align 4
10906 // CHECK20-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_MAPPERS7]], i32 0, i32 1
10907 // CHECK20-NEXT:    store i8* null, i8** [[TMP36]], align 4
10908 // CHECK20-NEXT:    [[TMP37:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_BASEPTRS5]], i32 0, i32 0
10909 // CHECK20-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[DOTOFFLOAD_PTRS6]], i32 0, i32 0
10910 // CHECK20-NEXT:    [[TMP39:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119.region_id, i32 2, i8** [[TMP37]], i8** [[TMP38]], i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_sizes.5, i32 0, i32 0), i64* getelementptr inbounds ([2 x i64], [2 x i64]* @.offload_maptypes.6, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
10911 // CHECK20-NEXT:    [[TMP40:%.*]] = icmp ne i32 [[TMP39]], 0
10912 // CHECK20-NEXT:    br i1 [[TMP40]], label [[OMP_OFFLOAD_FAILED8:%.*]], label [[OMP_OFFLOAD_CONT9:%.*]]
10913 // CHECK20:       omp_offload.failed8:
10914 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]]
10915 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT9]]
10916 // CHECK20:       omp_offload.cont9:
10917 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
10918 // CHECK20:       omp_if.else:
10919 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119(i32 [[TMP23]], i32 [[TMP25]]) #[[ATTR3]]
10920 // CHECK20-NEXT:    br label [[OMP_IF_END]]
10921 // CHECK20:       omp_if.end:
10922 // CHECK20-NEXT:    [[TMP41:%.*]] = load i32, i32* [[A]], align 4
10923 // CHECK20-NEXT:    store i32 [[TMP41]], i32* [[A_CASTED10]], align 4
10924 // CHECK20-NEXT:    [[TMP42:%.*]] = load i32, i32* [[A_CASTED10]], align 4
10925 // CHECK20-NEXT:    [[TMP43:%.*]] = load i32, i32* [[N_ADDR]], align 4
10926 // CHECK20-NEXT:    [[CMP11:%.*]] = icmp sgt i32 [[TMP43]], 20
10927 // CHECK20-NEXT:    br i1 [[CMP11]], label [[OMP_IF_THEN12:%.*]], label [[OMP_IF_ELSE18:%.*]]
10928 // CHECK20:       omp_if.then12:
10929 // CHECK20-NEXT:    [[TMP44:%.*]] = mul nuw i32 [[TMP1]], 4
10930 // CHECK20-NEXT:    [[TMP45:%.*]] = sext i32 [[TMP44]] to i64
10931 // CHECK20-NEXT:    [[TMP46:%.*]] = mul nuw i32 5, [[TMP3]]
10932 // CHECK20-NEXT:    [[TMP47:%.*]] = mul nuw i32 [[TMP46]], 8
10933 // CHECK20-NEXT:    [[TMP48:%.*]] = sext i32 [[TMP47]] to i64
10934 // CHECK20-NEXT:    [[TMP49:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
10935 // CHECK20-NEXT:    [[TMP50:%.*]] = bitcast i8** [[TMP49]] to i32*
10936 // CHECK20-NEXT:    store i32 [[TMP42]], i32* [[TMP50]], align 4
10937 // CHECK20-NEXT:    [[TMP51:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
10938 // CHECK20-NEXT:    [[TMP52:%.*]] = bitcast i8** [[TMP51]] to i32*
10939 // CHECK20-NEXT:    store i32 [[TMP42]], i32* [[TMP52]], align 4
10940 // CHECK20-NEXT:    [[TMP53:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
10941 // CHECK20-NEXT:    store i64 4, i64* [[TMP53]], align 4
10942 // CHECK20-NEXT:    [[TMP54:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 0
10943 // CHECK20-NEXT:    store i8* null, i8** [[TMP54]], align 4
10944 // CHECK20-NEXT:    [[TMP55:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 1
10945 // CHECK20-NEXT:    [[TMP56:%.*]] = bitcast i8** [[TMP55]] to [10 x float]**
10946 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP56]], align 4
10947 // CHECK20-NEXT:    [[TMP57:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 1
10948 // CHECK20-NEXT:    [[TMP58:%.*]] = bitcast i8** [[TMP57]] to [10 x float]**
10949 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[TMP58]], align 4
10950 // CHECK20-NEXT:    [[TMP59:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
10951 // CHECK20-NEXT:    store i64 40, i64* [[TMP59]], align 4
10952 // CHECK20-NEXT:    [[TMP60:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 1
10953 // CHECK20-NEXT:    store i8* null, i8** [[TMP60]], align 4
10954 // CHECK20-NEXT:    [[TMP61:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 2
10955 // CHECK20-NEXT:    [[TMP62:%.*]] = bitcast i8** [[TMP61]] to i32*
10956 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP62]], align 4
10957 // CHECK20-NEXT:    [[TMP63:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 2
10958 // CHECK20-NEXT:    [[TMP64:%.*]] = bitcast i8** [[TMP63]] to i32*
10959 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP64]], align 4
10960 // CHECK20-NEXT:    [[TMP65:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
10961 // CHECK20-NEXT:    store i64 4, i64* [[TMP65]], align 4
10962 // CHECK20-NEXT:    [[TMP66:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 2
10963 // CHECK20-NEXT:    store i8* null, i8** [[TMP66]], align 4
10964 // CHECK20-NEXT:    [[TMP67:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 3
10965 // CHECK20-NEXT:    [[TMP68:%.*]] = bitcast i8** [[TMP67]] to float**
10966 // CHECK20-NEXT:    store float* [[VLA]], float** [[TMP68]], align 4
10967 // CHECK20-NEXT:    [[TMP69:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 3
10968 // CHECK20-NEXT:    [[TMP70:%.*]] = bitcast i8** [[TMP69]] to float**
10969 // CHECK20-NEXT:    store float* [[VLA]], float** [[TMP70]], align 4
10970 // CHECK20-NEXT:    [[TMP71:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
10971 // CHECK20-NEXT:    store i64 [[TMP45]], i64* [[TMP71]], align 4
10972 // CHECK20-NEXT:    [[TMP72:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 3
10973 // CHECK20-NEXT:    store i8* null, i8** [[TMP72]], align 4
10974 // CHECK20-NEXT:    [[TMP73:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 4
10975 // CHECK20-NEXT:    [[TMP74:%.*]] = bitcast i8** [[TMP73]] to [5 x [10 x double]]**
10976 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP74]], align 4
10977 // CHECK20-NEXT:    [[TMP75:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 4
10978 // CHECK20-NEXT:    [[TMP76:%.*]] = bitcast i8** [[TMP75]] to [5 x [10 x double]]**
10979 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[TMP76]], align 4
10980 // CHECK20-NEXT:    [[TMP77:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
10981 // CHECK20-NEXT:    store i64 400, i64* [[TMP77]], align 4
10982 // CHECK20-NEXT:    [[TMP78:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 4
10983 // CHECK20-NEXT:    store i8* null, i8** [[TMP78]], align 4
10984 // CHECK20-NEXT:    [[TMP79:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 5
10985 // CHECK20-NEXT:    [[TMP80:%.*]] = bitcast i8** [[TMP79]] to i32*
10986 // CHECK20-NEXT:    store i32 5, i32* [[TMP80]], align 4
10987 // CHECK20-NEXT:    [[TMP81:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 5
10988 // CHECK20-NEXT:    [[TMP82:%.*]] = bitcast i8** [[TMP81]] to i32*
10989 // CHECK20-NEXT:    store i32 5, i32* [[TMP82]], align 4
10990 // CHECK20-NEXT:    [[TMP83:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 5
10991 // CHECK20-NEXT:    store i64 4, i64* [[TMP83]], align 4
10992 // CHECK20-NEXT:    [[TMP84:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 5
10993 // CHECK20-NEXT:    store i8* null, i8** [[TMP84]], align 4
10994 // CHECK20-NEXT:    [[TMP85:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 6
10995 // CHECK20-NEXT:    [[TMP86:%.*]] = bitcast i8** [[TMP85]] to i32*
10996 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP86]], align 4
10997 // CHECK20-NEXT:    [[TMP87:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 6
10998 // CHECK20-NEXT:    [[TMP88:%.*]] = bitcast i8** [[TMP87]] to i32*
10999 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP88]], align 4
11000 // CHECK20-NEXT:    [[TMP89:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 6
11001 // CHECK20-NEXT:    store i64 4, i64* [[TMP89]], align 4
11002 // CHECK20-NEXT:    [[TMP90:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 6
11003 // CHECK20-NEXT:    store i8* null, i8** [[TMP90]], align 4
11004 // CHECK20-NEXT:    [[TMP91:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 7
11005 // CHECK20-NEXT:    [[TMP92:%.*]] = bitcast i8** [[TMP91]] to double**
11006 // CHECK20-NEXT:    store double* [[VLA1]], double** [[TMP92]], align 4
11007 // CHECK20-NEXT:    [[TMP93:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 7
11008 // CHECK20-NEXT:    [[TMP94:%.*]] = bitcast i8** [[TMP93]] to double**
11009 // CHECK20-NEXT:    store double* [[VLA1]], double** [[TMP94]], align 4
11010 // CHECK20-NEXT:    [[TMP95:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 7
11011 // CHECK20-NEXT:    store i64 [[TMP48]], i64* [[TMP95]], align 4
11012 // CHECK20-NEXT:    [[TMP96:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 7
11013 // CHECK20-NEXT:    store i8* null, i8** [[TMP96]], align 4
11014 // CHECK20-NEXT:    [[TMP97:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 8
11015 // CHECK20-NEXT:    [[TMP98:%.*]] = bitcast i8** [[TMP97]] to %struct.TT**
11016 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP98]], align 4
11017 // CHECK20-NEXT:    [[TMP99:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 8
11018 // CHECK20-NEXT:    [[TMP100:%.*]] = bitcast i8** [[TMP99]] to %struct.TT**
11019 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[TMP100]], align 4
11020 // CHECK20-NEXT:    [[TMP101:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 8
11021 // CHECK20-NEXT:    store i64 12, i64* [[TMP101]], align 4
11022 // CHECK20-NEXT:    [[TMP102:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_MAPPERS15]], i32 0, i32 8
11023 // CHECK20-NEXT:    store i8* null, i8** [[TMP102]], align 4
11024 // CHECK20-NEXT:    [[TMP103:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_BASEPTRS13]], i32 0, i32 0
11025 // CHECK20-NEXT:    [[TMP104:%.*]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[DOTOFFLOAD_PTRS14]], i32 0, i32 0
11026 // CHECK20-NEXT:    [[TMP105:%.*]] = getelementptr inbounds [9 x i64], [9 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11027 // CHECK20-NEXT:    [[TMP106:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144.region_id, i32 9, i8** [[TMP103]], i8** [[TMP104]], i64* [[TMP105]], i64* getelementptr inbounds ([9 x i64], [9 x i64]* @.offload_maptypes.8, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
11028 // CHECK20-NEXT:    [[TMP107:%.*]] = icmp ne i32 [[TMP106]], 0
11029 // CHECK20-NEXT:    br i1 [[TMP107]], label [[OMP_OFFLOAD_FAILED16:%.*]], label [[OMP_OFFLOAD_CONT17:%.*]]
11030 // CHECK20:       omp_offload.failed16:
11031 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
11032 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT17]]
11033 // CHECK20:       omp_offload.cont17:
11034 // CHECK20-NEXT:    br label [[OMP_IF_END19:%.*]]
11035 // CHECK20:       omp_if.else18:
11036 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144(i32 [[TMP42]], [10 x float]* [[B]], i32 [[TMP1]], float* [[VLA]], [5 x [10 x double]]* [[C]], i32 5, i32 [[TMP3]], double* [[VLA1]], %struct.TT* [[D]]) #[[ATTR3]]
11037 // CHECK20-NEXT:    br label [[OMP_IF_END19]]
11038 // CHECK20:       omp_if.end19:
11039 // CHECK20-NEXT:    [[TMP108:%.*]] = load i32, i32* [[A]], align 4
11040 // CHECK20-NEXT:    [[TMP109:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
11041 // CHECK20-NEXT:    call void @llvm.stackrestore(i8* [[TMP109]])
11042 // CHECK20-NEXT:    ret i32 [[TMP108]]
11043 //
11044 //
11045 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
11046 // CHECK20-SAME: () #[[ATTR2:[0-9]+]] {
11047 // CHECK20-NEXT:  entry:
11048 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
11049 // CHECK20-NEXT:    ret void
11050 //
11051 //
11052 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined.
11053 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2]] {
11054 // CHECK20-NEXT:  entry:
11055 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11056 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11057 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11058 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11059 // CHECK20-NEXT:    ret void
11060 //
11061 //
11062 // CHECK20-LABEL: define {{[^@]+}}@.omp_task_entry.
11063 // CHECK20-SAME: (i32 [[TMP0:%.*]], %struct.kmp_task_t_with_privates* noalias [[TMP1:%.*]]) #[[ATTR4:[0-9]+]] {
11064 // CHECK20-NEXT:  entry:
11065 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR_I:%.*]] = alloca i32, align 4
11066 // CHECK20-NEXT:    [[DOTPART_ID__ADDR_I:%.*]] = alloca i32*, align 4
11067 // CHECK20-NEXT:    [[DOTPRIVATES__ADDR_I:%.*]] = alloca i8*, align 4
11068 // CHECK20-NEXT:    [[DOTCOPY_FN__ADDR_I:%.*]] = alloca void (i8*, ...)*, align 4
11069 // CHECK20-NEXT:    [[DOTTASK_T__ADDR_I:%.*]] = alloca i8*, align 4
11070 // CHECK20-NEXT:    [[__CONTEXT_ADDR_I:%.*]] = alloca %struct.anon*, align 4
11071 // CHECK20-NEXT:    [[DOTADDR:%.*]] = alloca i32, align 4
11072 // CHECK20-NEXT:    [[DOTADDR1:%.*]] = alloca %struct.kmp_task_t_with_privates*, align 4
11073 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[DOTADDR]], align 4
11074 // CHECK20-NEXT:    store %struct.kmp_task_t_with_privates* [[TMP1]], %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
11075 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[DOTADDR]], align 4
11076 // CHECK20-NEXT:    [[TMP3:%.*]] = load %struct.kmp_task_t_with_privates*, %struct.kmp_task_t_with_privates** [[DOTADDR1]], align 4
11077 // CHECK20-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T_WITH_PRIVATES:%.*]], %struct.kmp_task_t_with_privates* [[TMP3]], i32 0, i32 0
11078 // CHECK20-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T:%.*]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 2
11079 // CHECK20-NEXT:    [[TMP6:%.*]] = getelementptr inbounds [[STRUCT_KMP_TASK_T]], %struct.kmp_task_t* [[TMP4]], i32 0, i32 0
11080 // CHECK20-NEXT:    [[TMP7:%.*]] = load i8*, i8** [[TMP6]], align 4
11081 // CHECK20-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to %struct.anon*
11082 // CHECK20-NEXT:    [[TMP9:%.*]] = bitcast %struct.kmp_task_t_with_privates* [[TMP3]] to i8*
11083 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META12:![0-9]+]])
11084 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META15:![0-9]+]])
11085 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META17:![0-9]+]])
11086 // CHECK20-NEXT:    call void @llvm.experimental.noalias.scope.decl(metadata [[META19:![0-9]+]])
11087 // CHECK20-NEXT:    store i32 [[TMP2]], i32* [[DOTGLOBAL_TID__ADDR_I]], align 4, !noalias !21
11088 // CHECK20-NEXT:    store i32* [[TMP5]], i32** [[DOTPART_ID__ADDR_I]], align 4, !noalias !21
11089 // CHECK20-NEXT:    store i8* null, i8** [[DOTPRIVATES__ADDR_I]], align 4, !noalias !21
11090 // CHECK20-NEXT:    store void (i8*, ...)* null, void (i8*, ...)** [[DOTCOPY_FN__ADDR_I]], align 4, !noalias !21
11091 // CHECK20-NEXT:    store i8* [[TMP9]], i8** [[DOTTASK_T__ADDR_I]], align 4, !noalias !21
11092 // CHECK20-NEXT:    store %struct.anon* [[TMP8]], %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
11093 // CHECK20-NEXT:    [[TMP10:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR_I]], align 4, !noalias !21
11094 // CHECK20-NEXT:    [[TMP11:%.*]] = call i32 @__tgt_target_teams_nowait_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100.region_id, i32 0, i8** null, i8** null, i64* null, i64* null, i8** null, i8** null, i32 1, i32 0) #[[ATTR3]]
11095 // CHECK20-NEXT:    [[TMP12:%.*]] = icmp ne i32 [[TMP11]], 0
11096 // CHECK20-NEXT:    br i1 [[TMP12]], label [[OMP_OFFLOAD_FAILED_I:%.*]], label [[DOTOMP_OUTLINED__1_EXIT:%.*]]
11097 // CHECK20:       omp_offload.failed.i:
11098 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100() #[[ATTR3]]
11099 // CHECK20-NEXT:    br label [[DOTOMP_OUTLINED__1_EXIT]]
11100 // CHECK20:       .omp_outlined..1.exit:
11101 // CHECK20-NEXT:    ret i32 0
11102 //
11103 //
11104 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l104
11105 // CHECK20-SAME: (i32 [[A:%.*]]) #[[ATTR2]] {
11106 // CHECK20-NEXT:  entry:
11107 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11108 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11109 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11110 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11111 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11112 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11113 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11114 // CHECK20-NEXT:    ret void
11115 //
11116 //
11117 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..2
11118 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]]) #[[ATTR2]] {
11119 // CHECK20-NEXT:  entry:
11120 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11121 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11122 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11123 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11124 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11125 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11126 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11127 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11128 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
11129 // CHECK20-NEXT:    ret void
11130 //
11131 //
11132 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
11133 // CHECK20-SAME: (i32 [[AA:%.*]]) #[[ATTR2]] {
11134 // CHECK20-NEXT:  entry:
11135 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11136 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11137 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11138 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11139 // CHECK20-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
11140 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11141 // CHECK20-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
11142 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11143 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP1]])
11144 // CHECK20-NEXT:    ret void
11145 //
11146 //
11147 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..3
11148 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
11149 // CHECK20-NEXT:  entry:
11150 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11151 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11152 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11153 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11154 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11155 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11156 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11157 // CHECK20-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
11158 // CHECK20-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
11159 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
11160 // CHECK20-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
11161 // CHECK20-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 4
11162 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
11163 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
11164 // CHECK20-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
11165 // CHECK20-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
11166 // CHECK20-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
11167 // CHECK20:       .cancel.exit:
11168 // CHECK20-NEXT:    br label [[DOTCANCEL_CONTINUE]]
11169 // CHECK20:       .cancel.continue:
11170 // CHECK20-NEXT:    ret void
11171 //
11172 //
11173 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
11174 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
11175 // CHECK20-NEXT:  entry:
11176 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11177 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11178 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11179 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11180 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11181 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11182 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11183 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11184 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11185 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11186 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
11187 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11188 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
11189 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11190 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
11191 // CHECK20-NEXT:    ret void
11192 //
11193 //
11194 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..4
11195 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR2]] {
11196 // CHECK20-NEXT:  entry:
11197 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11198 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11199 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11200 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11201 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11202 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11203 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11204 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11205 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11206 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
11207 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11208 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
11209 // CHECK20-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
11210 // CHECK20-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
11211 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
11212 // CHECK20-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
11213 // CHECK20-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
11214 // CHECK20-NEXT:    ret void
11215 //
11216 //
11217 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
11218 // CHECK20-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
11219 // CHECK20-NEXT:  entry:
11220 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11221 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11222 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11223 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11224 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11225 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11226 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11227 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11228 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11229 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11230 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11231 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11232 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11233 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11234 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11235 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11236 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11237 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11238 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11239 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11240 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11241 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11242 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11243 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11244 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11245 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11246 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11247 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
11248 // CHECK20-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
11249 // CHECK20-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
11250 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
11251 // CHECK20-NEXT:    ret void
11252 //
11253 //
11254 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..7
11255 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR2]] {
11256 // CHECK20-NEXT:  entry:
11257 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11258 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11259 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11260 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
11261 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11262 // CHECK20-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
11263 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
11264 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11265 // CHECK20-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
11266 // CHECK20-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
11267 // CHECK20-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
11268 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11269 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11270 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11271 // CHECK20-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
11272 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11273 // CHECK20-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
11274 // CHECK20-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
11275 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11276 // CHECK20-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
11277 // CHECK20-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
11278 // CHECK20-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
11279 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
11280 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11281 // CHECK20-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
11282 // CHECK20-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
11283 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11284 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
11285 // CHECK20-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
11286 // CHECK20-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
11287 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
11288 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
11289 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
11290 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
11291 // CHECK20-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
11292 // CHECK20-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
11293 // CHECK20-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
11294 // CHECK20-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
11295 // CHECK20-NEXT:    store float [[CONV6]], float* [[ARRAYIDX]], align 4
11296 // CHECK20-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
11297 // CHECK20-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
11298 // CHECK20-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
11299 // CHECK20-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
11300 // CHECK20-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
11301 // CHECK20-NEXT:    store float [[CONV10]], float* [[ARRAYIDX7]], align 4
11302 // CHECK20-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
11303 // CHECK20-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
11304 // CHECK20-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
11305 // CHECK20-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
11306 // CHECK20-NEXT:    store double [[ADD13]], double* [[ARRAYIDX12]], align 8
11307 // CHECK20-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
11308 // CHECK20-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
11309 // CHECK20-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
11310 // CHECK20-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
11311 // CHECK20-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
11312 // CHECK20-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
11313 // CHECK20-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
11314 // CHECK20-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
11315 // CHECK20-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
11316 // CHECK20-NEXT:    store i64 [[ADD17]], i64* [[X]], align 4
11317 // CHECK20-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
11318 // CHECK20-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
11319 // CHECK20-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
11320 // CHECK20-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
11321 // CHECK20-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
11322 // CHECK20-NEXT:    store i8 [[CONV20]], i8* [[Y]], align 4
11323 // CHECK20-NEXT:    ret void
11324 //
11325 //
11326 // CHECK20-LABEL: define {{[^@]+}}@_Z3bari
11327 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
11328 // CHECK20-NEXT:  entry:
11329 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11330 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
11331 // CHECK20-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
11332 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11333 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
11334 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11335 // CHECK20-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
11336 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
11337 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
11338 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
11339 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
11340 // CHECK20-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
11341 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
11342 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
11343 // CHECK20-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
11344 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11345 // CHECK20-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
11346 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
11347 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
11348 // CHECK20-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
11349 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11350 // CHECK20-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
11351 // CHECK20-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
11352 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
11353 // CHECK20-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
11354 // CHECK20-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
11355 // CHECK20-NEXT:    ret i32 [[TMP8]]
11356 //
11357 //
11358 // CHECK20-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
11359 // CHECK20-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
11360 // CHECK20-NEXT:  entry:
11361 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11362 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11363 // CHECK20-NEXT:    [[B:%.*]] = alloca i32, align 4
11364 // CHECK20-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
11365 // CHECK20-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
11366 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
11367 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [5 x i8*], align 4
11368 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [5 x i8*], align 4
11369 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [5 x i8*], align 4
11370 // CHECK20-NEXT:    [[DOTOFFLOAD_SIZES:%.*]] = alloca [5 x i64], align 4
11371 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11372 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11373 // CHECK20-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11374 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11375 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11376 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
11377 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
11378 // CHECK20-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
11379 // CHECK20-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
11380 // CHECK20-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
11381 // CHECK20-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
11382 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
11383 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
11384 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
11385 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
11386 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11387 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 60
11388 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11389 // CHECK20:       omp_if.then:
11390 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
11391 // CHECK20-NEXT:    [[TMP7:%.*]] = mul nuw i32 2, [[TMP1]]
11392 // CHECK20-NEXT:    [[TMP8:%.*]] = mul nuw i32 [[TMP7]], 2
11393 // CHECK20-NEXT:    [[TMP9:%.*]] = sext i32 [[TMP8]] to i64
11394 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11395 // CHECK20-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to %struct.S1**
11396 // CHECK20-NEXT:    store %struct.S1* [[THIS1]], %struct.S1** [[TMP11]], align 4
11397 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11398 // CHECK20-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to double**
11399 // CHECK20-NEXT:    store double* [[A]], double** [[TMP13]], align 4
11400 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11401 // CHECK20-NEXT:    store i64 8, i64* [[TMP14]], align 4
11402 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11403 // CHECK20-NEXT:    store i8* null, i8** [[TMP15]], align 4
11404 // CHECK20-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11405 // CHECK20-NEXT:    [[TMP17:%.*]] = bitcast i8** [[TMP16]] to i32*
11406 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP17]], align 4
11407 // CHECK20-NEXT:    [[TMP18:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11408 // CHECK20-NEXT:    [[TMP19:%.*]] = bitcast i8** [[TMP18]] to i32*
11409 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP19]], align 4
11410 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 1
11411 // CHECK20-NEXT:    store i64 4, i64* [[TMP20]], align 4
11412 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11413 // CHECK20-NEXT:    store i8* null, i8** [[TMP21]], align 4
11414 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11415 // CHECK20-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to i32*
11416 // CHECK20-NEXT:    store i32 2, i32* [[TMP23]], align 4
11417 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11418 // CHECK20-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32*
11419 // CHECK20-NEXT:    store i32 2, i32* [[TMP25]], align 4
11420 // CHECK20-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 2
11421 // CHECK20-NEXT:    store i64 4, i64* [[TMP26]], align 4
11422 // CHECK20-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11423 // CHECK20-NEXT:    store i8* null, i8** [[TMP27]], align 4
11424 // CHECK20-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
11425 // CHECK20-NEXT:    [[TMP29:%.*]] = bitcast i8** [[TMP28]] to i32*
11426 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP29]], align 4
11427 // CHECK20-NEXT:    [[TMP30:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
11428 // CHECK20-NEXT:    [[TMP31:%.*]] = bitcast i8** [[TMP30]] to i32*
11429 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP31]], align 4
11430 // CHECK20-NEXT:    [[TMP32:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 3
11431 // CHECK20-NEXT:    store i64 4, i64* [[TMP32]], align 4
11432 // CHECK20-NEXT:    [[TMP33:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
11433 // CHECK20-NEXT:    store i8* null, i8** [[TMP33]], align 4
11434 // CHECK20-NEXT:    [[TMP34:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 4
11435 // CHECK20-NEXT:    [[TMP35:%.*]] = bitcast i8** [[TMP34]] to i16**
11436 // CHECK20-NEXT:    store i16* [[VLA]], i16** [[TMP35]], align 4
11437 // CHECK20-NEXT:    [[TMP36:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 4
11438 // CHECK20-NEXT:    [[TMP37:%.*]] = bitcast i8** [[TMP36]] to i16**
11439 // CHECK20-NEXT:    store i16* [[VLA]], i16** [[TMP37]], align 4
11440 // CHECK20-NEXT:    [[TMP38:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 4
11441 // CHECK20-NEXT:    store i64 [[TMP9]], i64* [[TMP38]], align 4
11442 // CHECK20-NEXT:    [[TMP39:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 4
11443 // CHECK20-NEXT:    store i8* null, i8** [[TMP39]], align 4
11444 // CHECK20-NEXT:    [[TMP40:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11445 // CHECK20-NEXT:    [[TMP41:%.*]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11446 // CHECK20-NEXT:    [[TMP42:%.*]] = getelementptr inbounds [5 x i64], [5 x i64]* [[DOTOFFLOAD_SIZES]], i32 0, i32 0
11447 // CHECK20-NEXT:    [[TMP43:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216.region_id, i32 5, i8** [[TMP40]], i8** [[TMP41]], i64* [[TMP42]], i64* getelementptr inbounds ([5 x i64], [5 x i64]* @.offload_maptypes.10, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
11448 // CHECK20-NEXT:    [[TMP44:%.*]] = icmp ne i32 [[TMP43]], 0
11449 // CHECK20-NEXT:    br i1 [[TMP44]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11450 // CHECK20:       omp_offload.failed:
11451 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
11452 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11453 // CHECK20:       omp_offload.cont:
11454 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
11455 // CHECK20:       omp_if.else:
11456 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216(%struct.S1* [[THIS1]], i32 [[TMP5]], i32 2, i32 [[TMP1]], i16* [[VLA]]) #[[ATTR3]]
11457 // CHECK20-NEXT:    br label [[OMP_IF_END]]
11458 // CHECK20:       omp_if.end:
11459 // CHECK20-NEXT:    [[TMP45:%.*]] = mul nsw i32 1, [[TMP1]]
11460 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP45]]
11461 // CHECK20-NEXT:    [[ARRAYIDX2:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11462 // CHECK20-NEXT:    [[TMP46:%.*]] = load i16, i16* [[ARRAYIDX2]], align 2
11463 // CHECK20-NEXT:    [[CONV:%.*]] = sext i16 [[TMP46]] to i32
11464 // CHECK20-NEXT:    [[TMP47:%.*]] = load i32, i32* [[B]], align 4
11465 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV]], [[TMP47]]
11466 // CHECK20-NEXT:    [[TMP48:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
11467 // CHECK20-NEXT:    call void @llvm.stackrestore(i8* [[TMP48]])
11468 // CHECK20-NEXT:    ret i32 [[ADD3]]
11469 //
11470 //
11471 // CHECK20-LABEL: define {{[^@]+}}@_ZL7fstatici
11472 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
11473 // CHECK20-NEXT:  entry:
11474 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11475 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
11476 // CHECK20-NEXT:    [[AA:%.*]] = alloca i16, align 2
11477 // CHECK20-NEXT:    [[AAA:%.*]] = alloca i8, align 1
11478 // CHECK20-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
11479 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11480 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11481 // CHECK20-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
11482 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4
11483 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4
11484 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4
11485 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11486 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
11487 // CHECK20-NEXT:    store i16 0, i16* [[AA]], align 2
11488 // CHECK20-NEXT:    store i8 0, i8* [[AAA]], align 1
11489 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
11490 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11491 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11492 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
11493 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11494 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
11495 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11496 // CHECK20-NEXT:    [[TMP4:%.*]] = load i8, i8* [[AAA]], align 1
11497 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11498 // CHECK20-NEXT:    store i8 [[TMP4]], i8* [[CONV1]], align 1
11499 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11500 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11501 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 50
11502 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11503 // CHECK20:       omp_if.then:
11504 // CHECK20-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11505 // CHECK20-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
11506 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
11507 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11508 // CHECK20-NEXT:    [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32*
11509 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP10]], align 4
11510 // CHECK20-NEXT:    [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11511 // CHECK20-NEXT:    store i8* null, i8** [[TMP11]], align 4
11512 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11513 // CHECK20-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
11514 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
11515 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11516 // CHECK20-NEXT:    [[TMP15:%.*]] = bitcast i8** [[TMP14]] to i32*
11517 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP15]], align 4
11518 // CHECK20-NEXT:    [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11519 // CHECK20-NEXT:    store i8* null, i8** [[TMP16]], align 4
11520 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11521 // CHECK20-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to i32*
11522 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP18]], align 4
11523 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11524 // CHECK20-NEXT:    [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32*
11525 // CHECK20-NEXT:    store i32 [[TMP5]], i32* [[TMP20]], align 4
11526 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11527 // CHECK20-NEXT:    store i8* null, i8** [[TMP21]], align 4
11528 // CHECK20-NEXT:    [[TMP22:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3
11529 // CHECK20-NEXT:    [[TMP23:%.*]] = bitcast i8** [[TMP22]] to [10 x i32]**
11530 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP23]], align 4
11531 // CHECK20-NEXT:    [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3
11532 // CHECK20-NEXT:    [[TMP25:%.*]] = bitcast i8** [[TMP24]] to [10 x i32]**
11533 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP25]], align 4
11534 // CHECK20-NEXT:    [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3
11535 // CHECK20-NEXT:    store i8* null, i8** [[TMP26]], align 4
11536 // CHECK20-NEXT:    [[TMP27:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11537 // CHECK20-NEXT:    [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11538 // CHECK20-NEXT:    [[TMP29:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198.region_id, i32 4, i8** [[TMP27]], i8** [[TMP28]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes.12, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes.13, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
11539 // CHECK20-NEXT:    [[TMP30:%.*]] = icmp ne i32 [[TMP29]], 0
11540 // CHECK20-NEXT:    br i1 [[TMP30]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11541 // CHECK20:       omp_offload.failed:
11542 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
11543 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11544 // CHECK20:       omp_offload.cont:
11545 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
11546 // CHECK20:       omp_if.else:
11547 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198(i32 [[TMP1]], i32 [[TMP3]], i32 [[TMP5]], [10 x i32]* [[B]]) #[[ATTR3]]
11548 // CHECK20-NEXT:    br label [[OMP_IF_END]]
11549 // CHECK20:       omp_if.end:
11550 // CHECK20-NEXT:    [[TMP31:%.*]] = load i32, i32* [[A]], align 4
11551 // CHECK20-NEXT:    ret i32 [[TMP31]]
11552 //
11553 //
11554 // CHECK20-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
11555 // CHECK20-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
11556 // CHECK20-NEXT:  entry:
11557 // CHECK20-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11558 // CHECK20-NEXT:    [[A:%.*]] = alloca i32, align 4
11559 // CHECK20-NEXT:    [[AA:%.*]] = alloca i16, align 2
11560 // CHECK20-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
11561 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11562 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11563 // CHECK20-NEXT:    [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [3 x i8*], align 4
11564 // CHECK20-NEXT:    [[DOTOFFLOAD_PTRS:%.*]] = alloca [3 x i8*], align 4
11565 // CHECK20-NEXT:    [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [3 x i8*], align 4
11566 // CHECK20-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11567 // CHECK20-NEXT:    store i32 0, i32* [[A]], align 4
11568 // CHECK20-NEXT:    store i16 0, i16* [[AA]], align 2
11569 // CHECK20-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
11570 // CHECK20-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
11571 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
11572 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[AA]], align 2
11573 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11574 // CHECK20-NEXT:    store i16 [[TMP2]], i16* [[CONV]], align 2
11575 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11576 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11577 // CHECK20-NEXT:    [[CMP:%.*]] = icmp sgt i32 [[TMP4]], 40
11578 // CHECK20-NEXT:    br i1 [[CMP]], label [[OMP_IF_THEN:%.*]], label [[OMP_IF_ELSE:%.*]]
11579 // CHECK20:       omp_if.then:
11580 // CHECK20-NEXT:    [[TMP5:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11581 // CHECK20-NEXT:    [[TMP6:%.*]] = bitcast i8** [[TMP5]] to i32*
11582 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP6]], align 4
11583 // CHECK20-NEXT:    [[TMP7:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11584 // CHECK20-NEXT:    [[TMP8:%.*]] = bitcast i8** [[TMP7]] to i32*
11585 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[TMP8]], align 4
11586 // CHECK20-NEXT:    [[TMP9:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0
11587 // CHECK20-NEXT:    store i8* null, i8** [[TMP9]], align 4
11588 // CHECK20-NEXT:    [[TMP10:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1
11589 // CHECK20-NEXT:    [[TMP11:%.*]] = bitcast i8** [[TMP10]] to i32*
11590 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP11]], align 4
11591 // CHECK20-NEXT:    [[TMP12:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1
11592 // CHECK20-NEXT:    [[TMP13:%.*]] = bitcast i8** [[TMP12]] to i32*
11593 // CHECK20-NEXT:    store i32 [[TMP3]], i32* [[TMP13]], align 4
11594 // CHECK20-NEXT:    [[TMP14:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1
11595 // CHECK20-NEXT:    store i8* null, i8** [[TMP14]], align 4
11596 // CHECK20-NEXT:    [[TMP15:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2
11597 // CHECK20-NEXT:    [[TMP16:%.*]] = bitcast i8** [[TMP15]] to [10 x i32]**
11598 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP16]], align 4
11599 // CHECK20-NEXT:    [[TMP17:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2
11600 // CHECK20-NEXT:    [[TMP18:%.*]] = bitcast i8** [[TMP17]] to [10 x i32]**
11601 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[TMP18]], align 4
11602 // CHECK20-NEXT:    [[TMP19:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2
11603 // CHECK20-NEXT:    store i8* null, i8** [[TMP19]], align 4
11604 // CHECK20-NEXT:    [[TMP20:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0
11605 // CHECK20-NEXT:    [[TMP21:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0
11606 // CHECK20-NEXT:    [[TMP22:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB1]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181.region_id, i32 3, i8** [[TMP20]], i8** [[TMP21]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.15, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.16, i32 0, i32 0), i8** null, i8** null, i32 1, i32 0)
11607 // CHECK20-NEXT:    [[TMP23:%.*]] = icmp ne i32 [[TMP22]], 0
11608 // CHECK20-NEXT:    br i1 [[TMP23]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]]
11609 // CHECK20:       omp_offload.failed:
11610 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
11611 // CHECK20-NEXT:    br label [[OMP_OFFLOAD_CONT]]
11612 // CHECK20:       omp_offload.cont:
11613 // CHECK20-NEXT:    br label [[OMP_IF_END:%.*]]
11614 // CHECK20:       omp_if.else:
11615 // CHECK20-NEXT:    call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181(i32 [[TMP1]], i32 [[TMP3]], [10 x i32]* [[B]]) #[[ATTR3]]
11616 // CHECK20-NEXT:    br label [[OMP_IF_END]]
11617 // CHECK20:       omp_if.end:
11618 // CHECK20-NEXT:    [[TMP24:%.*]] = load i32, i32* [[A]], align 4
11619 // CHECK20-NEXT:    ret i32 [[TMP24]]
11620 //
11621 //
11622 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
11623 // CHECK20-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
11624 // CHECK20-NEXT:  entry:
11625 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11626 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11627 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11628 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11629 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11630 // CHECK20-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
11631 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11632 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11633 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11634 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11635 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11636 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11637 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11638 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11639 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11640 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
11641 // CHECK20-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
11642 // CHECK20-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
11643 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..9 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
11644 // CHECK20-NEXT:    ret void
11645 //
11646 //
11647 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..9
11648 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR2]] {
11649 // CHECK20-NEXT:  entry:
11650 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11651 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11652 // CHECK20-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
11653 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
11654 // CHECK20-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
11655 // CHECK20-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
11656 // CHECK20-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
11657 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11658 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11659 // CHECK20-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
11660 // CHECK20-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
11661 // CHECK20-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
11662 // CHECK20-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
11663 // CHECK20-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
11664 // CHECK20-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
11665 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
11666 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
11667 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
11668 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
11669 // CHECK20-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
11670 // CHECK20-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
11671 // CHECK20-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
11672 // CHECK20-NEXT:    store double [[ADD]], double* [[A]], align 4
11673 // CHECK20-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
11674 // CHECK20-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
11675 // CHECK20-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
11676 // CHECK20-NEXT:    store double [[INC]], double* [[A3]], align 4
11677 // CHECK20-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
11678 // CHECK20-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
11679 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
11680 // CHECK20-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
11681 // CHECK20-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
11682 // CHECK20-NEXT:    ret void
11683 //
11684 //
11685 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
11686 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11687 // CHECK20-NEXT:  entry:
11688 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11689 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11690 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11691 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11692 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11693 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11694 // CHECK20-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
11695 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11696 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11697 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11698 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11699 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11700 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11701 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11702 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11703 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11704 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11705 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11706 // CHECK20-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11707 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
11708 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11709 // CHECK20-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
11710 // CHECK20-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
11711 // CHECK20-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
11712 // CHECK20-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
11713 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..11 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
11714 // CHECK20-NEXT:    ret void
11715 //
11716 //
11717 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..11
11718 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11719 // CHECK20-NEXT:  entry:
11720 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11721 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11722 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11723 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11724 // CHECK20-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
11725 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11726 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11727 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11728 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11729 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11730 // CHECK20-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
11731 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11732 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11733 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
11734 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11735 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11736 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
11737 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
11738 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
11739 // CHECK20-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
11740 // CHECK20-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
11741 // CHECK20-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
11742 // CHECK20-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
11743 // CHECK20-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
11744 // CHECK20-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
11745 // CHECK20-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
11746 // CHECK20-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
11747 // CHECK20-NEXT:    store i8 [[CONV7]], i8* [[CONV1]], align 4
11748 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11749 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11750 // CHECK20-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
11751 // CHECK20-NEXT:    store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
11752 // CHECK20-NEXT:    ret void
11753 //
11754 //
11755 // CHECK20-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
11756 // CHECK20-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11757 // CHECK20-NEXT:  entry:
11758 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11759 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11760 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11761 // CHECK20-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
11762 // CHECK20-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
11763 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11764 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11765 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11766 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11767 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11768 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11769 // CHECK20-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
11770 // CHECK20-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
11771 // CHECK20-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
11772 // CHECK20-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
11773 // CHECK20-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
11774 // CHECK20-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
11775 // CHECK20-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..14 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
11776 // CHECK20-NEXT:    ret void
11777 //
11778 //
11779 // CHECK20-LABEL: define {{[^@]+}}@.omp_outlined..14
11780 // CHECK20-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR2]] {
11781 // CHECK20-NEXT:  entry:
11782 // CHECK20-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
11783 // CHECK20-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
11784 // CHECK20-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
11785 // CHECK20-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
11786 // CHECK20-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
11787 // CHECK20-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
11788 // CHECK20-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
11789 // CHECK20-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
11790 // CHECK20-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
11791 // CHECK20-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
11792 // CHECK20-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
11793 // CHECK20-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
11794 // CHECK20-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
11795 // CHECK20-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
11796 // CHECK20-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
11797 // CHECK20-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
11798 // CHECK20-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
11799 // CHECK20-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
11800 // CHECK20-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
11801 // CHECK20-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
11802 // CHECK20-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
11803 // CHECK20-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
11804 // CHECK20-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
11805 // CHECK20-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
11806 // CHECK20-NEXT:    ret void
11807 //
11808 //
11809 // CHECK20-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg
11810 // CHECK20-SAME: () #[[ATTR5:[0-9]+]] {
11811 // CHECK20-NEXT:  entry:
11812 // CHECK20-NEXT:    call void @__tgt_register_requires(i64 1)
11813 // CHECK20-NEXT:    ret void
11814 //
11815 //
11816 // CHECK21-LABEL: define {{[^@]+}}@_Z3fooi
11817 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
11818 // CHECK21-NEXT:  entry:
11819 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11820 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
11821 // CHECK21-NEXT:    [[AA:%.*]] = alloca i16, align 2
11822 // CHECK21-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
11823 // CHECK21-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
11824 // CHECK21-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
11825 // CHECK21-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
11826 // CHECK21-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
11827 // CHECK21-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
11828 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11829 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
11830 // CHECK21-NEXT:    store i16 0, i16* [[AA]], align 2
11831 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11832 // CHECK21-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
11833 // CHECK21-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
11834 // CHECK21-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
11835 // CHECK21-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
11836 // CHECK21-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
11837 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
11838 // CHECK21-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
11839 // CHECK21-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
11840 // CHECK21-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
11841 // CHECK21-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
11842 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
11843 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
11844 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
11845 // CHECK21-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
11846 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
11847 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
11848 // CHECK21-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
11849 // CHECK21-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
11850 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
11851 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
11852 // CHECK21-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
11853 // CHECK21-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
11854 // CHECK21-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
11855 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
11856 // CHECK21-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
11857 // CHECK21-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
11858 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A]], align 4
11859 // CHECK21-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
11860 // CHECK21-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
11861 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
11862 // CHECK21-NEXT:    [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4
11863 // CHECK21-NEXT:    [[CONV9:%.*]] = fpext float [[TMP11]] to double
11864 // CHECK21-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
11865 // CHECK21-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
11866 // CHECK21-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
11867 // CHECK21-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
11868 // CHECK21-NEXT:    [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4
11869 // CHECK21-NEXT:    [[CONV13:%.*]] = fpext float [[TMP12]] to double
11870 // CHECK21-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
11871 // CHECK21-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
11872 // CHECK21-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
11873 // CHECK21-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
11874 // CHECK21-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
11875 // CHECK21-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8
11876 // CHECK21-NEXT:    [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00
11877 // CHECK21-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
11878 // CHECK21-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]]
11879 // CHECK21-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]]
11880 // CHECK21-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
11881 // CHECK21-NEXT:    [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8
11882 // CHECK21-NEXT:    [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00
11883 // CHECK21-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
11884 // CHECK21-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
11885 // CHECK21-NEXT:    [[TMP16:%.*]] = load i64, i64* [[X]], align 8
11886 // CHECK21-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1
11887 // CHECK21-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
11888 // CHECK21-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
11889 // CHECK21-NEXT:    [[TMP17:%.*]] = load i8, i8* [[Y]], align 8
11890 // CHECK21-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP17]] to i32
11891 // CHECK21-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
11892 // CHECK21-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
11893 // CHECK21-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
11894 // CHECK21-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
11895 // CHECK21-NEXT:    [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
11896 // CHECK21-NEXT:    call void @llvm.stackrestore(i8* [[TMP19]])
11897 // CHECK21-NEXT:    ret i32 [[TMP18]]
11898 //
11899 //
11900 // CHECK21-LABEL: define {{[^@]+}}@_Z3bari
11901 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
11902 // CHECK21-NEXT:  entry:
11903 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11904 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
11905 // CHECK21-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
11906 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11907 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
11908 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11909 // CHECK21-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
11910 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
11911 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
11912 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
11913 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
11914 // CHECK21-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
11915 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
11916 // CHECK21-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
11917 // CHECK21-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
11918 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
11919 // CHECK21-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
11920 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
11921 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
11922 // CHECK21-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
11923 // CHECK21-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
11924 // CHECK21-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
11925 // CHECK21-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
11926 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
11927 // CHECK21-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
11928 // CHECK21-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
11929 // CHECK21-NEXT:    ret i32 [[TMP8]]
11930 //
11931 //
11932 // CHECK21-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
11933 // CHECK21-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
11934 // CHECK21-NEXT:  entry:
11935 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
11936 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11937 // CHECK21-NEXT:    [[B:%.*]] = alloca i32, align 4
11938 // CHECK21-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
11939 // CHECK21-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
11940 // CHECK21-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
11941 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11942 // CHECK21-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
11943 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
11944 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11945 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
11946 // CHECK21-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
11947 // CHECK21-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
11948 // CHECK21-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
11949 // CHECK21-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
11950 // CHECK21-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
11951 // CHECK21-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
11952 // CHECK21-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
11953 // CHECK21-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
11954 // CHECK21-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
11955 // CHECK21-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
11956 // CHECK21-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
11957 // CHECK21-NEXT:    store double [[ADD2]], double* [[A]], align 8
11958 // CHECK21-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
11959 // CHECK21-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 8
11960 // CHECK21-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
11961 // CHECK21-NEXT:    store double [[INC]], double* [[A3]], align 8
11962 // CHECK21-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
11963 // CHECK21-NEXT:    [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
11964 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
11965 // CHECK21-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
11966 // CHECK21-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
11967 // CHECK21-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
11968 // CHECK21-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
11969 // CHECK21-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
11970 // CHECK21-NEXT:    [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
11971 // CHECK21-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
11972 // CHECK21-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4
11973 // CHECK21-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
11974 // CHECK21-NEXT:    [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
11975 // CHECK21-NEXT:    call void @llvm.stackrestore(i8* [[TMP11]])
11976 // CHECK21-NEXT:    ret i32 [[ADD9]]
11977 //
11978 //
11979 // CHECK21-LABEL: define {{[^@]+}}@_ZL7fstatici
11980 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
11981 // CHECK21-NEXT:  entry:
11982 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
11983 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
11984 // CHECK21-NEXT:    [[AA:%.*]] = alloca i16, align 2
11985 // CHECK21-NEXT:    [[AAA:%.*]] = alloca i8, align 1
11986 // CHECK21-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
11987 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
11988 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
11989 // CHECK21-NEXT:    store i16 0, i16* [[AA]], align 2
11990 // CHECK21-NEXT:    store i8 0, i8* [[AAA]], align 1
11991 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
11992 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
11993 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
11994 // CHECK21-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
11995 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
11996 // CHECK21-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
11997 // CHECK21-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
11998 // CHECK21-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
11999 // CHECK21-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
12000 // CHECK21-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
12001 // CHECK21-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12002 // CHECK21-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12003 // CHECK21-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12004 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12005 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12006 // CHECK21-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
12007 // CHECK21-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12008 // CHECK21-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
12009 // CHECK21-NEXT:    ret i32 [[TMP4]]
12010 //
12011 //
12012 // CHECK21-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12013 // CHECK21-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
12014 // CHECK21-NEXT:  entry:
12015 // CHECK21-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12016 // CHECK21-NEXT:    [[A:%.*]] = alloca i32, align 4
12017 // CHECK21-NEXT:    [[AA:%.*]] = alloca i16, align 2
12018 // CHECK21-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12019 // CHECK21-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12020 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
12021 // CHECK21-NEXT:    store i16 0, i16* [[AA]], align 2
12022 // CHECK21-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12023 // CHECK21-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12024 // CHECK21-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12025 // CHECK21-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
12026 // CHECK21-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
12027 // CHECK21-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12028 // CHECK21-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12029 // CHECK21-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12030 // CHECK21-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12031 // CHECK21-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12032 // CHECK21-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
12033 // CHECK21-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12034 // CHECK21-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12035 // CHECK21-NEXT:    ret i32 [[TMP3]]
12036 //
12037 //
12038 // CHECK22-LABEL: define {{[^@]+}}@_Z3fooi
12039 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
12040 // CHECK22-NEXT:  entry:
12041 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12042 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
12043 // CHECK22-NEXT:    [[AA:%.*]] = alloca i16, align 2
12044 // CHECK22-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12045 // CHECK22-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
12046 // CHECK22-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
12047 // CHECK22-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12048 // CHECK22-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
12049 // CHECK22-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
12050 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12051 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
12052 // CHECK22-NEXT:    store i16 0, i16* [[AA]], align 2
12053 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12054 // CHECK22-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
12055 // CHECK22-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
12056 // CHECK22-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
12057 // CHECK22-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
12058 // CHECK22-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
12059 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
12060 // CHECK22-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
12061 // CHECK22-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
12062 // CHECK22-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
12063 // CHECK22-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
12064 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
12065 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
12066 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12067 // CHECK22-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
12068 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
12069 // CHECK22-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
12070 // CHECK22-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
12071 // CHECK22-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
12072 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12073 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
12074 // CHECK22-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12075 // CHECK22-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
12076 // CHECK22-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
12077 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
12078 // CHECK22-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
12079 // CHECK22-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
12080 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A]], align 4
12081 // CHECK22-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
12082 // CHECK22-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
12083 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
12084 // CHECK22-NEXT:    [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4
12085 // CHECK22-NEXT:    [[CONV9:%.*]] = fpext float [[TMP11]] to double
12086 // CHECK22-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
12087 // CHECK22-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
12088 // CHECK22-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
12089 // CHECK22-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
12090 // CHECK22-NEXT:    [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4
12091 // CHECK22-NEXT:    [[CONV13:%.*]] = fpext float [[TMP12]] to double
12092 // CHECK22-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
12093 // CHECK22-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
12094 // CHECK22-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
12095 // CHECK22-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
12096 // CHECK22-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
12097 // CHECK22-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8
12098 // CHECK22-NEXT:    [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00
12099 // CHECK22-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
12100 // CHECK22-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]]
12101 // CHECK22-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]]
12102 // CHECK22-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
12103 // CHECK22-NEXT:    [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8
12104 // CHECK22-NEXT:    [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00
12105 // CHECK22-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
12106 // CHECK22-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
12107 // CHECK22-NEXT:    [[TMP16:%.*]] = load i64, i64* [[X]], align 8
12108 // CHECK22-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1
12109 // CHECK22-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
12110 // CHECK22-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
12111 // CHECK22-NEXT:    [[TMP17:%.*]] = load i8, i8* [[Y]], align 8
12112 // CHECK22-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP17]] to i32
12113 // CHECK22-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
12114 // CHECK22-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
12115 // CHECK22-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
12116 // CHECK22-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
12117 // CHECK22-NEXT:    [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
12118 // CHECK22-NEXT:    call void @llvm.stackrestore(i8* [[TMP19]])
12119 // CHECK22-NEXT:    ret i32 [[TMP18]]
12120 //
12121 //
12122 // CHECK22-LABEL: define {{[^@]+}}@_Z3bari
12123 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
12124 // CHECK22-NEXT:  entry:
12125 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12126 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
12127 // CHECK22-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
12128 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12129 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
12130 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12131 // CHECK22-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
12132 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12133 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12134 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12135 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12136 // CHECK22-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
12137 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12138 // CHECK22-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12139 // CHECK22-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12140 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12141 // CHECK22-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
12142 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12143 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12144 // CHECK22-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12145 // CHECK22-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12146 // CHECK22-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
12147 // CHECK22-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12148 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12149 // CHECK22-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12150 // CHECK22-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12151 // CHECK22-NEXT:    ret i32 [[TMP8]]
12152 //
12153 //
12154 // CHECK22-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12155 // CHECK22-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12156 // CHECK22-NEXT:  entry:
12157 // CHECK22-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
12158 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12159 // CHECK22-NEXT:    [[B:%.*]] = alloca i32, align 4
12160 // CHECK22-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
12161 // CHECK22-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
12162 // CHECK22-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
12163 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12164 // CHECK22-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
12165 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12166 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12167 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12168 // CHECK22-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12169 // CHECK22-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
12170 // CHECK22-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
12171 // CHECK22-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
12172 // CHECK22-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
12173 // CHECK22-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
12174 // CHECK22-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
12175 // CHECK22-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
12176 // CHECK22-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
12177 // CHECK22-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
12178 // CHECK22-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12179 // CHECK22-NEXT:    store double [[ADD2]], double* [[A]], align 8
12180 // CHECK22-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
12181 // CHECK22-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 8
12182 // CHECK22-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
12183 // CHECK22-NEXT:    store double [[INC]], double* [[A3]], align 8
12184 // CHECK22-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
12185 // CHECK22-NEXT:    [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
12186 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
12187 // CHECK22-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
12188 // CHECK22-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
12189 // CHECK22-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
12190 // CHECK22-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
12191 // CHECK22-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
12192 // CHECK22-NEXT:    [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
12193 // CHECK22-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
12194 // CHECK22-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4
12195 // CHECK22-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
12196 // CHECK22-NEXT:    [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
12197 // CHECK22-NEXT:    call void @llvm.stackrestore(i8* [[TMP11]])
12198 // CHECK22-NEXT:    ret i32 [[ADD9]]
12199 //
12200 //
12201 // CHECK22-LABEL: define {{[^@]+}}@_ZL7fstatici
12202 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
12203 // CHECK22-NEXT:  entry:
12204 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12205 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
12206 // CHECK22-NEXT:    [[AA:%.*]] = alloca i16, align 2
12207 // CHECK22-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12208 // CHECK22-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12209 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12210 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
12211 // CHECK22-NEXT:    store i16 0, i16* [[AA]], align 2
12212 // CHECK22-NEXT:    store i8 0, i8* [[AAA]], align 1
12213 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12214 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12215 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12216 // CHECK22-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
12217 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
12218 // CHECK22-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12219 // CHECK22-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12220 // CHECK22-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12221 // CHECK22-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
12222 // CHECK22-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
12223 // CHECK22-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12224 // CHECK22-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12225 // CHECK22-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12226 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12227 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12228 // CHECK22-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
12229 // CHECK22-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12230 // CHECK22-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
12231 // CHECK22-NEXT:    ret i32 [[TMP4]]
12232 //
12233 //
12234 // CHECK22-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12235 // CHECK22-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
12236 // CHECK22-NEXT:  entry:
12237 // CHECK22-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12238 // CHECK22-NEXT:    [[A:%.*]] = alloca i32, align 4
12239 // CHECK22-NEXT:    [[AA:%.*]] = alloca i16, align 2
12240 // CHECK22-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12241 // CHECK22-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12242 // CHECK22-NEXT:    store i32 0, i32* [[A]], align 4
12243 // CHECK22-NEXT:    store i16 0, i16* [[AA]], align 2
12244 // CHECK22-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12245 // CHECK22-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12246 // CHECK22-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12247 // CHECK22-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
12248 // CHECK22-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
12249 // CHECK22-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12250 // CHECK22-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12251 // CHECK22-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12252 // CHECK22-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
12253 // CHECK22-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12254 // CHECK22-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
12255 // CHECK22-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12256 // CHECK22-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12257 // CHECK22-NEXT:    ret i32 [[TMP3]]
12258 //
12259 //
12260 // CHECK23-LABEL: define {{[^@]+}}@_Z3fooi
12261 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
12262 // CHECK23-NEXT:  entry:
12263 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12264 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
12265 // CHECK23-NEXT:    [[AA:%.*]] = alloca i16, align 2
12266 // CHECK23-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12267 // CHECK23-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12268 // CHECK23-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12269 // CHECK23-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12270 // CHECK23-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
12271 // CHECK23-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
12272 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12273 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
12274 // CHECK23-NEXT:    store i16 0, i16* [[AA]], align 2
12275 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12276 // CHECK23-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
12277 // CHECK23-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
12278 // CHECK23-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
12279 // CHECK23-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
12280 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12281 // CHECK23-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
12282 // CHECK23-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
12283 // CHECK23-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
12284 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
12285 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
12286 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12287 // CHECK23-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2
12288 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
12289 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
12290 // CHECK23-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
12291 // CHECK23-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
12292 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
12293 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
12294 // CHECK23-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12295 // CHECK23-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
12296 // CHECK23-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP7]] to i32
12297 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
12298 // CHECK23-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
12299 // CHECK23-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
12300 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12301 // CHECK23-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
12302 // CHECK23-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
12303 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
12304 // CHECK23-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
12305 // CHECK23-NEXT:    [[CONV9:%.*]] = fpext float [[TMP9]] to double
12306 // CHECK23-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
12307 // CHECK23-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
12308 // CHECK23-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
12309 // CHECK23-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
12310 // CHECK23-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4
12311 // CHECK23-NEXT:    [[CONV13:%.*]] = fpext float [[TMP10]] to double
12312 // CHECK23-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
12313 // CHECK23-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
12314 // CHECK23-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
12315 // CHECK23-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
12316 // CHECK23-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2
12317 // CHECK23-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8
12318 // CHECK23-NEXT:    [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00
12319 // CHECK23-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
12320 // CHECK23-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
12321 // CHECK23-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]]
12322 // CHECK23-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3
12323 // CHECK23-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8
12324 // CHECK23-NEXT:    [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00
12325 // CHECK23-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
12326 // CHECK23-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
12327 // CHECK23-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
12328 // CHECK23-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1
12329 // CHECK23-NEXT:    store i64 [[ADD22]], i64* [[X]], align 4
12330 // CHECK23-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
12331 // CHECK23-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
12332 // CHECK23-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP15]] to i32
12333 // CHECK23-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
12334 // CHECK23-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
12335 // CHECK23-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 4
12336 // CHECK23-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
12337 // CHECK23-NEXT:    [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12338 // CHECK23-NEXT:    call void @llvm.stackrestore(i8* [[TMP17]])
12339 // CHECK23-NEXT:    ret i32 [[TMP16]]
12340 //
12341 //
12342 // CHECK23-LABEL: define {{[^@]+}}@_Z3bari
12343 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12344 // CHECK23-NEXT:  entry:
12345 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12346 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
12347 // CHECK23-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
12348 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12349 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
12350 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12351 // CHECK23-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
12352 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12353 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12354 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12355 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12356 // CHECK23-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
12357 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12358 // CHECK23-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12359 // CHECK23-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12360 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12361 // CHECK23-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
12362 // CHECK23-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12363 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12364 // CHECK23-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12365 // CHECK23-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12366 // CHECK23-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
12367 // CHECK23-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12368 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12369 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12370 // CHECK23-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12371 // CHECK23-NEXT:    ret i32 [[TMP8]]
12372 //
12373 //
12374 // CHECK23-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12375 // CHECK23-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12376 // CHECK23-NEXT:  entry:
12377 // CHECK23-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12378 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12379 // CHECK23-NEXT:    [[B:%.*]] = alloca i32, align 4
12380 // CHECK23-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12381 // CHECK23-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12382 // CHECK23-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12383 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12384 // CHECK23-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12385 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12386 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12387 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12388 // CHECK23-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12389 // CHECK23-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
12390 // CHECK23-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
12391 // CHECK23-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
12392 // CHECK23-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
12393 // CHECK23-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
12394 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
12395 // CHECK23-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
12396 // CHECK23-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
12397 // CHECK23-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12398 // CHECK23-NEXT:    store double [[ADD2]], double* [[A]], align 4
12399 // CHECK23-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
12400 // CHECK23-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
12401 // CHECK23-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
12402 // CHECK23-NEXT:    store double [[INC]], double* [[A3]], align 4
12403 // CHECK23-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
12404 // CHECK23-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
12405 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
12406 // CHECK23-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
12407 // CHECK23-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
12408 // CHECK23-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
12409 // CHECK23-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
12410 // CHECK23-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
12411 // CHECK23-NEXT:    [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
12412 // CHECK23-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
12413 // CHECK23-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4
12414 // CHECK23-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
12415 // CHECK23-NEXT:    [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12416 // CHECK23-NEXT:    call void @llvm.stackrestore(i8* [[TMP10]])
12417 // CHECK23-NEXT:    ret i32 [[ADD9]]
12418 //
12419 //
12420 // CHECK23-LABEL: define {{[^@]+}}@_ZL7fstatici
12421 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12422 // CHECK23-NEXT:  entry:
12423 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12424 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
12425 // CHECK23-NEXT:    [[AA:%.*]] = alloca i16, align 2
12426 // CHECK23-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12427 // CHECK23-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12428 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12429 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
12430 // CHECK23-NEXT:    store i16 0, i16* [[AA]], align 2
12431 // CHECK23-NEXT:    store i8 0, i8* [[AAA]], align 1
12432 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12433 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12434 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12435 // CHECK23-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
12436 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
12437 // CHECK23-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12438 // CHECK23-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12439 // CHECK23-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12440 // CHECK23-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
12441 // CHECK23-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
12442 // CHECK23-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12443 // CHECK23-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12444 // CHECK23-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12445 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12446 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12447 // CHECK23-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
12448 // CHECK23-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12449 // CHECK23-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
12450 // CHECK23-NEXT:    ret i32 [[TMP4]]
12451 //
12452 //
12453 // CHECK23-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12454 // CHECK23-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
12455 // CHECK23-NEXT:  entry:
12456 // CHECK23-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12457 // CHECK23-NEXT:    [[A:%.*]] = alloca i32, align 4
12458 // CHECK23-NEXT:    [[AA:%.*]] = alloca i16, align 2
12459 // CHECK23-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12460 // CHECK23-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12461 // CHECK23-NEXT:    store i32 0, i32* [[A]], align 4
12462 // CHECK23-NEXT:    store i16 0, i16* [[AA]], align 2
12463 // CHECK23-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12464 // CHECK23-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12465 // CHECK23-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12466 // CHECK23-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
12467 // CHECK23-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
12468 // CHECK23-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12469 // CHECK23-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12470 // CHECK23-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12471 // CHECK23-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12472 // CHECK23-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12473 // CHECK23-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
12474 // CHECK23-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12475 // CHECK23-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12476 // CHECK23-NEXT:    ret i32 [[TMP3]]
12477 //
12478 //
12479 // CHECK24-LABEL: define {{[^@]+}}@_Z3fooi
12480 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
12481 // CHECK24-NEXT:  entry:
12482 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12483 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
12484 // CHECK24-NEXT:    [[AA:%.*]] = alloca i16, align 2
12485 // CHECK24-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
12486 // CHECK24-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12487 // CHECK24-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12488 // CHECK24-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
12489 // CHECK24-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
12490 // CHECK24-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
12491 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12492 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
12493 // CHECK24-NEXT:    store i16 0, i16* [[AA]], align 2
12494 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12495 // CHECK24-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
12496 // CHECK24-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
12497 // CHECK24-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
12498 // CHECK24-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
12499 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12500 // CHECK24-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
12501 // CHECK24-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
12502 // CHECK24-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
12503 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
12504 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
12505 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12506 // CHECK24-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2
12507 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
12508 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
12509 // CHECK24-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
12510 // CHECK24-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
12511 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
12512 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
12513 // CHECK24-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12514 // CHECK24-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
12515 // CHECK24-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP7]] to i32
12516 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
12517 // CHECK24-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
12518 // CHECK24-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
12519 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12520 // CHECK24-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
12521 // CHECK24-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
12522 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
12523 // CHECK24-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
12524 // CHECK24-NEXT:    [[CONV9:%.*]] = fpext float [[TMP9]] to double
12525 // CHECK24-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
12526 // CHECK24-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
12527 // CHECK24-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
12528 // CHECK24-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
12529 // CHECK24-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4
12530 // CHECK24-NEXT:    [[CONV13:%.*]] = fpext float [[TMP10]] to double
12531 // CHECK24-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
12532 // CHECK24-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
12533 // CHECK24-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
12534 // CHECK24-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
12535 // CHECK24-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2
12536 // CHECK24-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8
12537 // CHECK24-NEXT:    [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00
12538 // CHECK24-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
12539 // CHECK24-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
12540 // CHECK24-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]]
12541 // CHECK24-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3
12542 // CHECK24-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8
12543 // CHECK24-NEXT:    [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00
12544 // CHECK24-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
12545 // CHECK24-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
12546 // CHECK24-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
12547 // CHECK24-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1
12548 // CHECK24-NEXT:    store i64 [[ADD22]], i64* [[X]], align 4
12549 // CHECK24-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
12550 // CHECK24-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
12551 // CHECK24-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP15]] to i32
12552 // CHECK24-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
12553 // CHECK24-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
12554 // CHECK24-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 4
12555 // CHECK24-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
12556 // CHECK24-NEXT:    [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12557 // CHECK24-NEXT:    call void @llvm.stackrestore(i8* [[TMP17]])
12558 // CHECK24-NEXT:    ret i32 [[TMP16]]
12559 //
12560 //
12561 // CHECK24-LABEL: define {{[^@]+}}@_Z3bari
12562 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12563 // CHECK24-NEXT:  entry:
12564 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12565 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
12566 // CHECK24-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
12567 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12568 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
12569 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12570 // CHECK24-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
12571 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
12572 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
12573 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12574 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
12575 // CHECK24-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
12576 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12577 // CHECK24-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
12578 // CHECK24-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
12579 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
12580 // CHECK24-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
12581 // CHECK24-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
12582 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
12583 // CHECK24-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
12584 // CHECK24-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
12585 // CHECK24-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
12586 // CHECK24-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
12587 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
12588 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
12589 // CHECK24-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
12590 // CHECK24-NEXT:    ret i32 [[TMP8]]
12591 //
12592 //
12593 // CHECK24-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
12594 // CHECK24-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
12595 // CHECK24-NEXT:  entry:
12596 // CHECK24-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
12597 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12598 // CHECK24-NEXT:    [[B:%.*]] = alloca i32, align 4
12599 // CHECK24-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
12600 // CHECK24-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
12601 // CHECK24-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
12602 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12603 // CHECK24-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
12604 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
12605 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12606 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
12607 // CHECK24-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
12608 // CHECK24-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
12609 // CHECK24-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
12610 // CHECK24-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
12611 // CHECK24-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
12612 // CHECK24-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
12613 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
12614 // CHECK24-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
12615 // CHECK24-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
12616 // CHECK24-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
12617 // CHECK24-NEXT:    store double [[ADD2]], double* [[A]], align 4
12618 // CHECK24-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
12619 // CHECK24-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
12620 // CHECK24-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
12621 // CHECK24-NEXT:    store double [[INC]], double* [[A3]], align 4
12622 // CHECK24-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
12623 // CHECK24-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
12624 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
12625 // CHECK24-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
12626 // CHECK24-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
12627 // CHECK24-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
12628 // CHECK24-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
12629 // CHECK24-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
12630 // CHECK24-NEXT:    [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
12631 // CHECK24-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
12632 // CHECK24-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4
12633 // CHECK24-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
12634 // CHECK24-NEXT:    [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
12635 // CHECK24-NEXT:    call void @llvm.stackrestore(i8* [[TMP10]])
12636 // CHECK24-NEXT:    ret i32 [[ADD9]]
12637 //
12638 //
12639 // CHECK24-LABEL: define {{[^@]+}}@_ZL7fstatici
12640 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
12641 // CHECK24-NEXT:  entry:
12642 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12643 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
12644 // CHECK24-NEXT:    [[AA:%.*]] = alloca i16, align 2
12645 // CHECK24-NEXT:    [[AAA:%.*]] = alloca i8, align 1
12646 // CHECK24-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12647 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12648 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
12649 // CHECK24-NEXT:    store i16 0, i16* [[AA]], align 2
12650 // CHECK24-NEXT:    store i8 0, i8* [[AAA]], align 1
12651 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12652 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12653 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12654 // CHECK24-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
12655 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
12656 // CHECK24-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12657 // CHECK24-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12658 // CHECK24-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12659 // CHECK24-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
12660 // CHECK24-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
12661 // CHECK24-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12662 // CHECK24-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
12663 // CHECK24-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
12664 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12665 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12666 // CHECK24-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
12667 // CHECK24-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
12668 // CHECK24-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
12669 // CHECK24-NEXT:    ret i32 [[TMP4]]
12670 //
12671 //
12672 // CHECK24-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
12673 // CHECK24-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
12674 // CHECK24-NEXT:  entry:
12675 // CHECK24-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
12676 // CHECK24-NEXT:    [[A:%.*]] = alloca i32, align 4
12677 // CHECK24-NEXT:    [[AA:%.*]] = alloca i16, align 2
12678 // CHECK24-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
12679 // CHECK24-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
12680 // CHECK24-NEXT:    store i32 0, i32* [[A]], align 4
12681 // CHECK24-NEXT:    store i16 0, i16* [[AA]], align 2
12682 // CHECK24-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
12683 // CHECK24-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12684 // CHECK24-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
12685 // CHECK24-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
12686 // CHECK24-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
12687 // CHECK24-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
12688 // CHECK24-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
12689 // CHECK24-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
12690 // CHECK24-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
12691 // CHECK24-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12692 // CHECK24-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
12693 // CHECK24-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
12694 // CHECK24-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
12695 // CHECK24-NEXT:    ret i32 [[TMP3]]
12696 //
12697 //
12698 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
12699 // CHECK25-SAME: () #[[ATTR0:[0-9]+]] {
12700 // CHECK25-NEXT:  entry:
12701 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
12702 // CHECK25-NEXT:    ret void
12703 //
12704 //
12705 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined.
12706 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
12707 // CHECK25-NEXT:  entry:
12708 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12709 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12710 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12711 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12712 // CHECK25-NEXT:    ret void
12713 //
12714 //
12715 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
12716 // CHECK25-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
12717 // CHECK25-NEXT:  entry:
12718 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12719 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
12720 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12721 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12722 // CHECK25-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
12723 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
12724 // CHECK25-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
12725 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
12726 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
12727 // CHECK25-NEXT:    ret void
12728 //
12729 //
12730 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..1
12731 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
12732 // CHECK25-NEXT:  entry:
12733 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12734 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12735 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12736 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12737 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12738 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12739 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12740 // CHECK25-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
12741 // CHECK25-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
12742 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
12743 // CHECK25-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
12744 // CHECK25-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 8
12745 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
12746 // CHECK25-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
12747 // CHECK25-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
12748 // CHECK25-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
12749 // CHECK25-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
12750 // CHECK25:       .cancel.exit:
12751 // CHECK25-NEXT:    br label [[DOTCANCEL_CONTINUE]]
12752 // CHECK25:       .cancel.continue:
12753 // CHECK25-NEXT:    ret void
12754 //
12755 //
12756 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
12757 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
12758 // CHECK25-NEXT:  entry:
12759 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12760 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12761 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
12762 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
12763 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12764 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12765 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12766 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12767 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
12768 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
12769 // CHECK25-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
12770 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
12771 // CHECK25-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
12772 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
12773 // CHECK25-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
12774 // CHECK25-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
12775 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
12776 // CHECK25-NEXT:    ret void
12777 //
12778 //
12779 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..2
12780 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
12781 // CHECK25-NEXT:  entry:
12782 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12783 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12784 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12785 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12786 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12787 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12788 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12789 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12790 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12791 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12792 // CHECK25-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
12793 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
12794 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
12795 // CHECK25-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
12796 // CHECK25-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
12797 // CHECK25-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
12798 // CHECK25-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
12799 // CHECK25-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
12800 // CHECK25-NEXT:    ret void
12801 //
12802 //
12803 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
12804 // CHECK25-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
12805 // CHECK25-NEXT:  entry:
12806 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12807 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
12808 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
12809 // CHECK25-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
12810 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
12811 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
12812 // CHECK25-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
12813 // CHECK25-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
12814 // CHECK25-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
12815 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
12816 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12817 // CHECK25-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
12818 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
12819 // CHECK25-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
12820 // CHECK25-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
12821 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
12822 // CHECK25-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
12823 // CHECK25-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
12824 // CHECK25-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
12825 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12826 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
12827 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
12828 // CHECK25-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
12829 // CHECK25-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
12830 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
12831 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
12832 // CHECK25-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
12833 // CHECK25-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
12834 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
12835 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
12836 // CHECK25-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
12837 // CHECK25-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
12838 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
12839 // CHECK25-NEXT:    ret void
12840 //
12841 //
12842 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..3
12843 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
12844 // CHECK25-NEXT:  entry:
12845 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12846 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12847 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12848 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
12849 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
12850 // CHECK25-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
12851 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
12852 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
12853 // CHECK25-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
12854 // CHECK25-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
12855 // CHECK25-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
12856 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12857 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12858 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12859 // CHECK25-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
12860 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
12861 // CHECK25-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
12862 // CHECK25-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
12863 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
12864 // CHECK25-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
12865 // CHECK25-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
12866 // CHECK25-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
12867 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12868 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
12869 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
12870 // CHECK25-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
12871 // CHECK25-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
12872 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
12873 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
12874 // CHECK25-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
12875 // CHECK25-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
12876 // CHECK25-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
12877 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
12878 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
12879 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
12880 // CHECK25-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
12881 // CHECK25-NEXT:    [[CONV5:%.*]] = fpext float [[TMP9]] to double
12882 // CHECK25-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
12883 // CHECK25-NEXT:    [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
12884 // CHECK25-NEXT:    store float [[CONV7]], float* [[ARRAYIDX]], align 4
12885 // CHECK25-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
12886 // CHECK25-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
12887 // CHECK25-NEXT:    [[CONV9:%.*]] = fpext float [[TMP10]] to double
12888 // CHECK25-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
12889 // CHECK25-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
12890 // CHECK25-NEXT:    store float [[CONV11]], float* [[ARRAYIDX8]], align 4
12891 // CHECK25-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
12892 // CHECK25-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
12893 // CHECK25-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
12894 // CHECK25-NEXT:    [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
12895 // CHECK25-NEXT:    store double [[ADD14]], double* [[ARRAYIDX13]], align 8
12896 // CHECK25-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
12897 // CHECK25-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
12898 // CHECK25-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
12899 // CHECK25-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
12900 // CHECK25-NEXT:    [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
12901 // CHECK25-NEXT:    store double [[ADD17]], double* [[ARRAYIDX16]], align 8
12902 // CHECK25-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
12903 // CHECK25-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 8
12904 // CHECK25-NEXT:    [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
12905 // CHECK25-NEXT:    store i64 [[ADD18]], i64* [[X]], align 8
12906 // CHECK25-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
12907 // CHECK25-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
12908 // CHECK25-NEXT:    [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
12909 // CHECK25-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
12910 // CHECK25-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
12911 // CHECK25-NEXT:    store i8 [[CONV21]], i8* [[Y]], align 8
12912 // CHECK25-NEXT:    ret void
12913 //
12914 //
12915 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
12916 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
12917 // CHECK25-NEXT:  entry:
12918 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12919 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12920 // CHECK25-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
12921 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
12922 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
12923 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
12924 // CHECK25-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
12925 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12926 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12927 // CHECK25-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
12928 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
12929 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12930 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12931 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
12932 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
12933 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
12934 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
12935 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
12936 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
12937 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
12938 // CHECK25-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
12939 // CHECK25-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
12940 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
12941 // CHECK25-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
12942 // CHECK25-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
12943 // CHECK25-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
12944 // CHECK25-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
12945 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
12946 // CHECK25-NEXT:    ret void
12947 //
12948 //
12949 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..4
12950 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
12951 // CHECK25-NEXT:  entry:
12952 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
12953 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
12954 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
12955 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
12956 // CHECK25-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
12957 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
12958 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
12959 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
12960 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
12961 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
12962 // CHECK25-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
12963 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
12964 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
12965 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
12966 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
12967 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
12968 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
12969 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
12970 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
12971 // CHECK25-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
12972 // CHECK25-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
12973 // CHECK25-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
12974 // CHECK25-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
12975 // CHECK25-NEXT:    store i16 [[CONV5]], i16* [[CONV1]], align 8
12976 // CHECK25-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
12977 // CHECK25-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
12978 // CHECK25-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
12979 // CHECK25-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
12980 // CHECK25-NEXT:    store i8 [[CONV8]], i8* [[CONV2]], align 8
12981 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
12982 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
12983 // CHECK25-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
12984 // CHECK25-NEXT:    store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
12985 // CHECK25-NEXT:    ret void
12986 //
12987 //
12988 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
12989 // CHECK25-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
12990 // CHECK25-NEXT:  entry:
12991 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
12992 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
12993 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
12994 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
12995 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
12996 // CHECK25-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
12997 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
12998 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
12999 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13000 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13001 // CHECK25-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
13002 // CHECK25-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
13003 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
13004 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13005 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13006 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
13007 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
13008 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
13009 // CHECK25-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
13010 // CHECK25-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
13011 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
13012 // CHECK25-NEXT:    ret void
13013 //
13014 //
13015 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..5
13016 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
13017 // CHECK25-NEXT:  entry:
13018 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13019 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13020 // CHECK25-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
13021 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
13022 // CHECK25-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
13023 // CHECK25-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
13024 // CHECK25-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
13025 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13026 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13027 // CHECK25-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
13028 // CHECK25-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
13029 // CHECK25-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13030 // CHECK25-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13031 // CHECK25-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
13032 // CHECK25-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
13033 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
13034 // CHECK25-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13035 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13036 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
13037 // CHECK25-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
13038 // CHECK25-NEXT:    [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
13039 // CHECK25-NEXT:    [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
13040 // CHECK25-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
13041 // CHECK25-NEXT:    store double [[ADD]], double* [[A]], align 8
13042 // CHECK25-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13043 // CHECK25-NEXT:    [[TMP5:%.*]] = load double, double* [[A4]], align 8
13044 // CHECK25-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
13045 // CHECK25-NEXT:    store double [[INC]], double* [[A4]], align 8
13046 // CHECK25-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
13047 // CHECK25-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
13048 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
13049 // CHECK25-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
13050 // CHECK25-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
13051 // CHECK25-NEXT:    ret void
13052 //
13053 //
13054 // CHECK25-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
13055 // CHECK25-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13056 // CHECK25-NEXT:  entry:
13057 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13058 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13059 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13060 // CHECK25-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13061 // CHECK25-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13062 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13063 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13064 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13065 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13066 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13067 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13068 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13069 // CHECK25-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13070 // CHECK25-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
13071 // CHECK25-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
13072 // CHECK25-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
13073 // CHECK25-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13074 // CHECK25-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
13075 // CHECK25-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13076 // CHECK25-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
13077 // CHECK25-NEXT:    ret void
13078 //
13079 //
13080 // CHECK25-LABEL: define {{[^@]+}}@.omp_outlined..6
13081 // CHECK25-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13082 // CHECK25-NEXT:  entry:
13083 // CHECK25-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13084 // CHECK25-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13085 // CHECK25-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13086 // CHECK25-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13087 // CHECK25-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13088 // CHECK25-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13089 // CHECK25-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13090 // CHECK25-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13091 // CHECK25-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13092 // CHECK25-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13093 // CHECK25-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13094 // CHECK25-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13095 // CHECK25-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13096 // CHECK25-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13097 // CHECK25-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13098 // CHECK25-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
13099 // CHECK25-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13100 // CHECK25-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
13101 // CHECK25-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13102 // CHECK25-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13103 // CHECK25-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
13104 // CHECK25-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
13105 // CHECK25-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13106 // CHECK25-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
13107 // CHECK25-NEXT:    store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
13108 // CHECK25-NEXT:    ret void
13109 //
13110 //
13111 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
13112 // CHECK26-SAME: () #[[ATTR0:[0-9]+]] {
13113 // CHECK26-NEXT:  entry:
13114 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
13115 // CHECK26-NEXT:    ret void
13116 //
13117 //
13118 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined.
13119 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
13120 // CHECK26-NEXT:  entry:
13121 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13122 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13123 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13124 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13125 // CHECK26-NEXT:    ret void
13126 //
13127 //
13128 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
13129 // CHECK26-SAME: (i64 [[AA:%.*]]) #[[ATTR0]] {
13130 // CHECK26-NEXT:  entry:
13131 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13132 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13133 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13134 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13135 // CHECK26-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
13136 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13137 // CHECK26-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
13138 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13139 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP1]])
13140 // CHECK26-NEXT:    ret void
13141 //
13142 //
13143 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..1
13144 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13145 // CHECK26-NEXT:  entry:
13146 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13147 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13148 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13149 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13150 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13151 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13152 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13153 // CHECK26-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 8
13154 // CHECK26-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
13155 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
13156 // CHECK26-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
13157 // CHECK26-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 8
13158 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
13159 // CHECK26-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
13160 // CHECK26-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
13161 // CHECK26-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
13162 // CHECK26-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
13163 // CHECK26:       .cancel.exit:
13164 // CHECK26-NEXT:    br label [[DOTCANCEL_CONTINUE]]
13165 // CHECK26:       .cancel.continue:
13166 // CHECK26-NEXT:    ret void
13167 //
13168 //
13169 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
13170 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13171 // CHECK26-NEXT:  entry:
13172 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13173 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13174 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13175 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13176 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13177 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13178 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13179 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13180 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13181 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13182 // CHECK26-NEXT:    store i32 [[TMP0]], i32* [[CONV2]], align 4
13183 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[A_CASTED]], align 8
13184 // CHECK26-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13185 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13186 // CHECK26-NEXT:    store i16 [[TMP2]], i16* [[CONV3]], align 2
13187 // CHECK26-NEXT:    [[TMP3:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13188 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP1]], i64 [[TMP3]])
13189 // CHECK26-NEXT:    ret void
13190 //
13191 //
13192 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..2
13193 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]]) #[[ATTR0]] {
13194 // CHECK26-NEXT:  entry:
13195 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13196 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13197 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13198 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13199 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13200 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13201 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13202 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13203 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13204 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13205 // CHECK26-NEXT:    [[TMP0:%.*]] = load i32, i32* [[CONV]], align 8
13206 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
13207 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
13208 // CHECK26-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV1]], align 8
13209 // CHECK26-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP1]] to i32
13210 // CHECK26-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13211 // CHECK26-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13212 // CHECK26-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
13213 // CHECK26-NEXT:    ret void
13214 //
13215 //
13216 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
13217 // CHECK26-SAME: (i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
13218 // CHECK26-NEXT:  entry:
13219 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13220 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
13221 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
13222 // CHECK26-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
13223 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
13224 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
13225 // CHECK26-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
13226 // CHECK26-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
13227 // CHECK26-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
13228 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13229 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13230 // CHECK26-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
13231 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13232 // CHECK26-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
13233 // CHECK26-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
13234 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13235 // CHECK26-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
13236 // CHECK26-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
13237 // CHECK26-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
13238 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13239 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
13240 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13241 // CHECK26-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
13242 // CHECK26-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
13243 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13244 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
13245 // CHECK26-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
13246 // CHECK26-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
13247 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
13248 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13249 // CHECK26-NEXT:    store i32 [[TMP8]], i32* [[CONV5]], align 4
13250 // CHECK26-NEXT:    [[TMP9:%.*]] = load i64, i64* [[A_CASTED]], align 8
13251 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [10 x float]*, i64, float*, [5 x [10 x double]]*, i64, i64, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP9]], [10 x float]* [[TMP0]], i64 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i64 [[TMP4]], i64 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
13252 // CHECK26-NEXT:    ret void
13253 //
13254 //
13255 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..3
13256 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i64 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 8 dereferenceable(400) [[C:%.*]], i64 [[VLA1:%.*]], i64 [[VLA3:%.*]], double* nonnull align 8 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 8 dereferenceable(16) [[D:%.*]]) #[[ATTR0]] {
13257 // CHECK26-NEXT:  entry:
13258 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13259 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13260 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13261 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 8
13262 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
13263 // CHECK26-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 8
13264 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 8
13265 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
13266 // CHECK26-NEXT:    [[VLA_ADDR4:%.*]] = alloca i64, align 8
13267 // CHECK26-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 8
13268 // CHECK26-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 8
13269 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13270 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13271 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13272 // CHECK26-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 8
13273 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13274 // CHECK26-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 8
13275 // CHECK26-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 8
13276 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13277 // CHECK26-NEXT:    store i64 [[VLA3]], i64* [[VLA_ADDR4]], align 8
13278 // CHECK26-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 8
13279 // CHECK26-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 8
13280 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13281 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 8
13282 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13283 // CHECK26-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 8
13284 // CHECK26-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 8
13285 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13286 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[VLA_ADDR4]], align 8
13287 // CHECK26-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 8
13288 // CHECK26-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 8
13289 // CHECK26-NEXT:    [[TMP8:%.*]] = load i32, i32* [[CONV]], align 8
13290 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
13291 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
13292 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i64 0, i64 2
13293 // CHECK26-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
13294 // CHECK26-NEXT:    [[CONV5:%.*]] = fpext float [[TMP9]] to double
13295 // CHECK26-NEXT:    [[ADD6:%.*]] = fadd double [[CONV5]], 1.000000e+00
13296 // CHECK26-NEXT:    [[CONV7:%.*]] = fptrunc double [[ADD6]] to float
13297 // CHECK26-NEXT:    store float [[CONV7]], float* [[ARRAYIDX]], align 4
13298 // CHECK26-NEXT:    [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 3
13299 // CHECK26-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX8]], align 4
13300 // CHECK26-NEXT:    [[CONV9:%.*]] = fpext float [[TMP10]] to double
13301 // CHECK26-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
13302 // CHECK26-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
13303 // CHECK26-NEXT:    store float [[CONV11]], float* [[ARRAYIDX8]], align 4
13304 // CHECK26-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i64 0, i64 1
13305 // CHECK26-NEXT:    [[ARRAYIDX13:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX12]], i64 0, i64 2
13306 // CHECK26-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX13]], align 8
13307 // CHECK26-NEXT:    [[ADD14:%.*]] = fadd double [[TMP11]], 1.000000e+00
13308 // CHECK26-NEXT:    store double [[ADD14]], double* [[ARRAYIDX13]], align 8
13309 // CHECK26-NEXT:    [[TMP12:%.*]] = mul nsw i64 1, [[TMP5]]
13310 // CHECK26-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[TMP6]], i64 [[TMP12]]
13311 // CHECK26-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX15]], i64 3
13312 // CHECK26-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX16]], align 8
13313 // CHECK26-NEXT:    [[ADD17:%.*]] = fadd double [[TMP13]], 1.000000e+00
13314 // CHECK26-NEXT:    store double [[ADD17]], double* [[ARRAYIDX16]], align 8
13315 // CHECK26-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
13316 // CHECK26-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 8
13317 // CHECK26-NEXT:    [[ADD18:%.*]] = add nsw i64 [[TMP14]], 1
13318 // CHECK26-NEXT:    store i64 [[ADD18]], i64* [[X]], align 8
13319 // CHECK26-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
13320 // CHECK26-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 8
13321 // CHECK26-NEXT:    [[CONV19:%.*]] = sext i8 [[TMP15]] to i32
13322 // CHECK26-NEXT:    [[ADD20:%.*]] = add nsw i32 [[CONV19]], 1
13323 // CHECK26-NEXT:    [[CONV21:%.*]] = trunc i32 [[ADD20]] to i8
13324 // CHECK26-NEXT:    store i8 [[CONV21]], i8* [[Y]], align 8
13325 // CHECK26-NEXT:    ret void
13326 //
13327 //
13328 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
13329 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13330 // CHECK26-NEXT:  entry:
13331 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13332 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13333 // CHECK26-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
13334 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13335 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13336 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13337 // CHECK26-NEXT:    [[AAA_CASTED:%.*]] = alloca i64, align 8
13338 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13339 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13340 // CHECK26-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
13341 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13342 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13343 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13344 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
13345 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13346 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13347 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13348 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[CONV3]], align 4
13349 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
13350 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
13351 // CHECK26-NEXT:    [[CONV4:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13352 // CHECK26-NEXT:    store i16 [[TMP3]], i16* [[CONV4]], align 2
13353 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13354 // CHECK26-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV2]], align 8
13355 // CHECK26-NEXT:    [[CONV5:%.*]] = bitcast i64* [[AAA_CASTED]] to i8*
13356 // CHECK26-NEXT:    store i8 [[TMP5]], i8* [[CONV5]], align 1
13357 // CHECK26-NEXT:    [[TMP6:%.*]] = load i64, i64* [[AAA_CASTED]], align 8
13358 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], i64 [[TMP6]], [10 x i32]* [[TMP0]])
13359 // CHECK26-NEXT:    ret void
13360 //
13361 //
13362 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..4
13363 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], i64 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13364 // CHECK26-NEXT:  entry:
13365 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13366 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13367 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13368 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13369 // CHECK26-NEXT:    [[AAA_ADDR:%.*]] = alloca i64, align 8
13370 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13371 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13372 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13373 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13374 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13375 // CHECK26-NEXT:    store i64 [[AAA]], i64* [[AAA_ADDR]], align 8
13376 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13377 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13378 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13379 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[AAA_ADDR]] to i8*
13380 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13381 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13382 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13383 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
13384 // CHECK26-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13385 // CHECK26-NEXT:    [[CONV3:%.*]] = sext i16 [[TMP2]] to i32
13386 // CHECK26-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
13387 // CHECK26-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i16
13388 // CHECK26-NEXT:    store i16 [[CONV5]], i16* [[CONV1]], align 8
13389 // CHECK26-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV2]], align 8
13390 // CHECK26-NEXT:    [[CONV6:%.*]] = sext i8 [[TMP3]] to i32
13391 // CHECK26-NEXT:    [[ADD7:%.*]] = add nsw i32 [[CONV6]], 1
13392 // CHECK26-NEXT:    [[CONV8:%.*]] = trunc i32 [[ADD7]] to i8
13393 // CHECK26-NEXT:    store i8 [[CONV8]], i8* [[CONV2]], align 8
13394 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
13395 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13396 // CHECK26-NEXT:    [[ADD9:%.*]] = add nsw i32 [[TMP4]], 1
13397 // CHECK26-NEXT:    store i32 [[ADD9]], i32* [[ARRAYIDX]], align 4
13398 // CHECK26-NEXT:    ret void
13399 //
13400 //
13401 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
13402 // CHECK26-SAME: (%struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
13403 // CHECK26-NEXT:  entry:
13404 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
13405 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
13406 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
13407 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
13408 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
13409 // CHECK26-NEXT:    [[B_CASTED:%.*]] = alloca i64, align 8
13410 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
13411 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
13412 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13413 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13414 // CHECK26-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
13415 // CHECK26-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
13416 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
13417 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13418 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13419 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
13420 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
13421 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[B_CASTED]] to i32*
13422 // CHECK26-NEXT:    store i32 [[TMP4]], i32* [[CONV3]], align 4
13423 // CHECK26-NEXT:    [[TMP5:%.*]] = load i64, i64* [[B_CASTED]], align 8
13424 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i64, i64, i64, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i64 [[TMP5]], i64 [[TMP1]], i64 [[TMP2]], i16* [[TMP3]])
13425 // CHECK26-NEXT:    ret void
13426 //
13427 //
13428 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..5
13429 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i64 [[B:%.*]], i64 [[VLA:%.*]], i64 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
13430 // CHECK26-NEXT:  entry:
13431 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13432 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13433 // CHECK26-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
13434 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca i64, align 8
13435 // CHECK26-NEXT:    [[VLA_ADDR:%.*]] = alloca i64, align 8
13436 // CHECK26-NEXT:    [[VLA_ADDR2:%.*]] = alloca i64, align 8
13437 // CHECK26-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 8
13438 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13439 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13440 // CHECK26-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
13441 // CHECK26-NEXT:    store i64 [[B]], i64* [[B_ADDR]], align 8
13442 // CHECK26-NEXT:    store i64 [[VLA]], i64* [[VLA_ADDR]], align 8
13443 // CHECK26-NEXT:    store i64 [[VLA1]], i64* [[VLA_ADDR2]], align 8
13444 // CHECK26-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 8
13445 // CHECK26-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
13446 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[B_ADDR]] to i32*
13447 // CHECK26-NEXT:    [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8
13448 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[VLA_ADDR2]], align 8
13449 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 8
13450 // CHECK26-NEXT:    [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8
13451 // CHECK26-NEXT:    [[CONV3:%.*]] = sitofp i32 [[TMP4]] to double
13452 // CHECK26-NEXT:    [[ADD:%.*]] = fadd double [[CONV3]], 1.500000e+00
13453 // CHECK26-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
13454 // CHECK26-NEXT:    store double [[ADD]], double* [[A]], align 8
13455 // CHECK26-NEXT:    [[A4:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13456 // CHECK26-NEXT:    [[TMP5:%.*]] = load double, double* [[A4]], align 8
13457 // CHECK26-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
13458 // CHECK26-NEXT:    store double [[INC]], double* [[A4]], align 8
13459 // CHECK26-NEXT:    [[CONV5:%.*]] = fptosi double [[INC]] to i16
13460 // CHECK26-NEXT:    [[TMP6:%.*]] = mul nsw i64 1, [[TMP2]]
13461 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i64 [[TMP6]]
13462 // CHECK26-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
13463 // CHECK26-NEXT:    store i16 [[CONV5]], i16* [[ARRAYIDX6]], align 2
13464 // CHECK26-NEXT:    ret void
13465 //
13466 //
13467 // CHECK26-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
13468 // CHECK26-SAME: (i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13469 // CHECK26-NEXT:  entry:
13470 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13471 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13472 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13473 // CHECK26-NEXT:    [[A_CASTED:%.*]] = alloca i64, align 8
13474 // CHECK26-NEXT:    [[AA_CASTED:%.*]] = alloca i64, align 8
13475 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13476 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13477 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13478 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13479 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13480 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13481 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13482 // CHECK26-NEXT:    [[CONV2:%.*]] = bitcast i64* [[A_CASTED]] to i32*
13483 // CHECK26-NEXT:    store i32 [[TMP1]], i32* [[CONV2]], align 4
13484 // CHECK26-NEXT:    [[TMP2:%.*]] = load i64, i64* [[A_CASTED]], align 8
13485 // CHECK26-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV1]], align 8
13486 // CHECK26-NEXT:    [[CONV3:%.*]] = bitcast i64* [[AA_CASTED]] to i16*
13487 // CHECK26-NEXT:    store i16 [[TMP3]], i16* [[CONV3]], align 2
13488 // CHECK26-NEXT:    [[TMP4:%.*]] = load i64, i64* [[AA_CASTED]], align 8
13489 // CHECK26-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i64 [[TMP2]], i64 [[TMP4]], [10 x i32]* [[TMP0]])
13490 // CHECK26-NEXT:    ret void
13491 //
13492 //
13493 // CHECK26-LABEL: define {{[^@]+}}@.omp_outlined..6
13494 // CHECK26-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[A:%.*]], i64 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13495 // CHECK26-NEXT:  entry:
13496 // CHECK26-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
13497 // CHECK26-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
13498 // CHECK26-NEXT:    [[A_ADDR:%.*]] = alloca i64, align 8
13499 // CHECK26-NEXT:    [[AA_ADDR:%.*]] = alloca i64, align 8
13500 // CHECK26-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 8
13501 // CHECK26-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
13502 // CHECK26-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
13503 // CHECK26-NEXT:    store i64 [[A]], i64* [[A_ADDR]], align 8
13504 // CHECK26-NEXT:    store i64 [[AA]], i64* [[AA_ADDR]], align 8
13505 // CHECK26-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 8
13506 // CHECK26-NEXT:    [[CONV:%.*]] = bitcast i64* [[A_ADDR]] to i32*
13507 // CHECK26-NEXT:    [[CONV1:%.*]] = bitcast i64* [[AA_ADDR]] to i16*
13508 // CHECK26-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 8
13509 // CHECK26-NEXT:    [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8
13510 // CHECK26-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13511 // CHECK26-NEXT:    store i32 [[ADD]], i32* [[CONV]], align 8
13512 // CHECK26-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV1]], align 8
13513 // CHECK26-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
13514 // CHECK26-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13515 // CHECK26-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13516 // CHECK26-NEXT:    store i16 [[CONV4]], i16* [[CONV1]], align 8
13517 // CHECK26-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i64 0, i64 2
13518 // CHECK26-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13519 // CHECK26-NEXT:    [[ADD5:%.*]] = add nsw i32 [[TMP3]], 1
13520 // CHECK26-NEXT:    store i32 [[ADD5]], i32* [[ARRAYIDX]], align 4
13521 // CHECK26-NEXT:    ret void
13522 //
13523 //
13524 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
13525 // CHECK27-SAME: () #[[ATTR0:[0-9]+]] {
13526 // CHECK27-NEXT:  entry:
13527 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
13528 // CHECK27-NEXT:    ret void
13529 //
13530 //
13531 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined.
13532 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
13533 // CHECK27-NEXT:  entry:
13534 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13535 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13536 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13537 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13538 // CHECK27-NEXT:    ret void
13539 //
13540 //
13541 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
13542 // CHECK27-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
13543 // CHECK27-NEXT:  entry:
13544 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13545 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13546 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13547 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13548 // CHECK27-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
13549 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13550 // CHECK27-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
13551 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13552 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
13553 // CHECK27-NEXT:    ret void
13554 //
13555 //
13556 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..1
13557 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
13558 // CHECK27-NEXT:  entry:
13559 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13560 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13561 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13562 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13563 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13564 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13565 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13566 // CHECK27-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
13567 // CHECK27-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
13568 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
13569 // CHECK27-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
13570 // CHECK27-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 4
13571 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13572 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
13573 // CHECK27-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
13574 // CHECK27-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
13575 // CHECK27-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
13576 // CHECK27:       .cancel.exit:
13577 // CHECK27-NEXT:    br label [[DOTCANCEL_CONTINUE]]
13578 // CHECK27:       .cancel.continue:
13579 // CHECK27-NEXT:    ret void
13580 //
13581 //
13582 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
13583 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
13584 // CHECK27-NEXT:  entry:
13585 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13586 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13587 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13588 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13589 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13590 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13591 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13592 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
13593 // CHECK27-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
13594 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
13595 // CHECK27-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
13596 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13597 // CHECK27-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
13598 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13599 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
13600 // CHECK27-NEXT:    ret void
13601 //
13602 //
13603 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..2
13604 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
13605 // CHECK27-NEXT:  entry:
13606 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13607 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13608 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13609 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13610 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13611 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13612 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13613 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13614 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13615 // CHECK27-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
13616 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
13617 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
13618 // CHECK27-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
13619 // CHECK27-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
13620 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
13621 // CHECK27-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
13622 // CHECK27-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
13623 // CHECK27-NEXT:    ret void
13624 //
13625 //
13626 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
13627 // CHECK27-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
13628 // CHECK27-NEXT:  entry:
13629 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13630 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
13631 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13632 // CHECK27-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
13633 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
13634 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13635 // CHECK27-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
13636 // CHECK27-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
13637 // CHECK27-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
13638 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13639 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13640 // CHECK27-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
13641 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13642 // CHECK27-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
13643 // CHECK27-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
13644 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13645 // CHECK27-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
13646 // CHECK27-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
13647 // CHECK27-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
13648 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
13649 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13650 // CHECK27-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
13651 // CHECK27-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
13652 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13653 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
13654 // CHECK27-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
13655 // CHECK27-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
13656 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
13657 // CHECK27-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
13658 // CHECK27-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
13659 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
13660 // CHECK27-NEXT:    ret void
13661 //
13662 //
13663 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..3
13664 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
13665 // CHECK27-NEXT:  entry:
13666 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13667 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13668 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13669 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
13670 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13671 // CHECK27-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
13672 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
13673 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13674 // CHECK27-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
13675 // CHECK27-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
13676 // CHECK27-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
13677 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13678 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13679 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13680 // CHECK27-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
13681 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13682 // CHECK27-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
13683 // CHECK27-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
13684 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13685 // CHECK27-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
13686 // CHECK27-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
13687 // CHECK27-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
13688 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
13689 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13690 // CHECK27-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
13691 // CHECK27-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
13692 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13693 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
13694 // CHECK27-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
13695 // CHECK27-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
13696 // CHECK27-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
13697 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
13698 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
13699 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
13700 // CHECK27-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
13701 // CHECK27-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
13702 // CHECK27-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
13703 // CHECK27-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
13704 // CHECK27-NEXT:    store float [[CONV6]], float* [[ARRAYIDX]], align 4
13705 // CHECK27-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
13706 // CHECK27-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
13707 // CHECK27-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
13708 // CHECK27-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
13709 // CHECK27-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
13710 // CHECK27-NEXT:    store float [[CONV10]], float* [[ARRAYIDX7]], align 4
13711 // CHECK27-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
13712 // CHECK27-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
13713 // CHECK27-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
13714 // CHECK27-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
13715 // CHECK27-NEXT:    store double [[ADD13]], double* [[ARRAYIDX12]], align 8
13716 // CHECK27-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
13717 // CHECK27-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
13718 // CHECK27-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
13719 // CHECK27-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
13720 // CHECK27-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
13721 // CHECK27-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
13722 // CHECK27-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
13723 // CHECK27-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
13724 // CHECK27-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
13725 // CHECK27-NEXT:    store i64 [[ADD17]], i64* [[X]], align 4
13726 // CHECK27-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
13727 // CHECK27-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
13728 // CHECK27-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
13729 // CHECK27-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
13730 // CHECK27-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
13731 // CHECK27-NEXT:    store i8 [[CONV20]], i8* [[Y]], align 4
13732 // CHECK27-NEXT:    ret void
13733 //
13734 //
13735 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
13736 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13737 // CHECK27-NEXT:  entry:
13738 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13739 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13740 // CHECK27-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
13741 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13742 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13743 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13744 // CHECK27-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
13745 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13746 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13747 // CHECK27-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13748 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13749 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13750 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
13751 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13752 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13753 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
13754 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
13755 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
13756 // CHECK27-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13757 // CHECK27-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
13758 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13759 // CHECK27-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
13760 // CHECK27-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
13761 // CHECK27-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
13762 // CHECK27-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
13763 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
13764 // CHECK27-NEXT:    ret void
13765 //
13766 //
13767 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..4
13768 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13769 // CHECK27-NEXT:  entry:
13770 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13771 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13772 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13773 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13774 // CHECK27-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
13775 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13776 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13777 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13778 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13779 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13780 // CHECK27-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
13781 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13782 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13783 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
13784 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13785 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13786 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13787 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
13788 // CHECK27-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
13789 // CHECK27-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
13790 // CHECK27-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
13791 // CHECK27-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
13792 // CHECK27-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
13793 // CHECK27-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
13794 // CHECK27-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
13795 // CHECK27-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
13796 // CHECK27-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
13797 // CHECK27-NEXT:    store i8 [[CONV7]], i8* [[CONV1]], align 4
13798 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
13799 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13800 // CHECK27-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
13801 // CHECK27-NEXT:    store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
13802 // CHECK27-NEXT:    ret void
13803 //
13804 //
13805 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
13806 // CHECK27-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
13807 // CHECK27-NEXT:  entry:
13808 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13809 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
13810 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13811 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13812 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
13813 // CHECK27-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
13814 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13815 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
13816 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13817 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13818 // CHECK27-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
13819 // CHECK27-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13820 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13821 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13822 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
13823 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
13824 // CHECK27-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
13825 // CHECK27-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
13826 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
13827 // CHECK27-NEXT:    ret void
13828 //
13829 //
13830 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..5
13831 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
13832 // CHECK27-NEXT:  entry:
13833 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13834 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13835 // CHECK27-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
13836 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
13837 // CHECK27-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
13838 // CHECK27-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
13839 // CHECK27-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
13840 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13841 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13842 // CHECK27-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
13843 // CHECK27-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
13844 // CHECK27-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
13845 // CHECK27-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
13846 // CHECK27-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
13847 // CHECK27-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
13848 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
13849 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
13850 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
13851 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
13852 // CHECK27-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
13853 // CHECK27-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
13854 // CHECK27-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
13855 // CHECK27-NEXT:    store double [[ADD]], double* [[A]], align 4
13856 // CHECK27-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
13857 // CHECK27-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
13858 // CHECK27-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
13859 // CHECK27-NEXT:    store double [[INC]], double* [[A3]], align 4
13860 // CHECK27-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
13861 // CHECK27-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
13862 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
13863 // CHECK27-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
13864 // CHECK27-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
13865 // CHECK27-NEXT:    ret void
13866 //
13867 //
13868 // CHECK27-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
13869 // CHECK27-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13870 // CHECK27-NEXT:  entry:
13871 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13872 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13873 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13874 // CHECK27-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13875 // CHECK27-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13876 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13877 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13878 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13879 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13880 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13881 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13882 // CHECK27-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
13883 // CHECK27-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
13884 // CHECK27-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
13885 // CHECK27-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13886 // CHECK27-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
13887 // CHECK27-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13888 // CHECK27-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
13889 // CHECK27-NEXT:    ret void
13890 //
13891 //
13892 // CHECK27-LABEL: define {{[^@]+}}@.omp_outlined..6
13893 // CHECK27-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
13894 // CHECK27-NEXT:  entry:
13895 // CHECK27-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13896 // CHECK27-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13897 // CHECK27-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13898 // CHECK27-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13899 // CHECK27-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
13900 // CHECK27-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13901 // CHECK27-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13902 // CHECK27-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13903 // CHECK27-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13904 // CHECK27-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
13905 // CHECK27-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13906 // CHECK27-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
13907 // CHECK27-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
13908 // CHECK27-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
13909 // CHECK27-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
13910 // CHECK27-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
13911 // CHECK27-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
13912 // CHECK27-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
13913 // CHECK27-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
13914 // CHECK27-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
13915 // CHECK27-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
13916 // CHECK27-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
13917 // CHECK27-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
13918 // CHECK27-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
13919 // CHECK27-NEXT:    ret void
13920 //
13921 //
13922 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l100
13923 // CHECK28-SAME: () #[[ATTR0:[0-9]+]] {
13924 // CHECK28-NEXT:  entry:
13925 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
13926 // CHECK28-NEXT:    ret void
13927 //
13928 //
13929 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined.
13930 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR0]] {
13931 // CHECK28-NEXT:  entry:
13932 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13933 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13934 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13935 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13936 // CHECK28-NEXT:    ret void
13937 //
13938 //
13939 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l110
13940 // CHECK28-SAME: (i32 [[AA:%.*]]) #[[ATTR0]] {
13941 // CHECK28-NEXT:  entry:
13942 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13943 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13944 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13945 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13946 // CHECK28-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
13947 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13948 // CHECK28-NEXT:    store i16 [[TMP0]], i16* [[CONV1]], align 2
13949 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13950 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP1]])
13951 // CHECK28-NEXT:    ret void
13952 //
13953 //
13954 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..1
13955 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
13956 // CHECK28-NEXT:  entry:
13957 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
13958 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
13959 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13960 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
13961 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
13962 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13963 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13964 // CHECK28-NEXT:    [[TMP0:%.*]] = load i16, i16* [[CONV]], align 4
13965 // CHECK28-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP0]] to i32
13966 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[CONV1]], 1
13967 // CHECK28-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD]] to i16
13968 // CHECK28-NEXT:    store i16 [[CONV2]], i16* [[CONV]], align 4
13969 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4
13970 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[TMP1]], align 4
13971 // CHECK28-NEXT:    [[TMP3:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB1]], i32 [[TMP2]], i32 1)
13972 // CHECK28-NEXT:    [[TMP4:%.*]] = icmp ne i32 [[TMP3]], 0
13973 // CHECK28-NEXT:    br i1 [[TMP4]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]]
13974 // CHECK28:       .cancel.exit:
13975 // CHECK28-NEXT:    br label [[DOTCANCEL_CONTINUE]]
13976 // CHECK28:       .cancel.continue:
13977 // CHECK28-NEXT:    ret void
13978 //
13979 //
13980 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l119
13981 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
13982 // CHECK28-NEXT:  entry:
13983 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
13984 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
13985 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
13986 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
13987 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
13988 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
13989 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
13990 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
13991 // CHECK28-NEXT:    store i32 [[TMP0]], i32* [[A_CASTED]], align 4
13992 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_CASTED]], align 4
13993 // CHECK28-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
13994 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
13995 // CHECK28-NEXT:    store i16 [[TMP2]], i16* [[CONV1]], align 2
13996 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[AA_CASTED]], align 4
13997 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP1]], i32 [[TMP3]])
13998 // CHECK28-NEXT:    ret void
13999 //
14000 //
14001 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..2
14002 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]]) #[[ATTR0]] {
14003 // CHECK28-NEXT:  entry:
14004 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14005 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14006 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
14007 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
14008 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14009 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14010 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
14011 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
14012 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14013 // CHECK28-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
14014 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14015 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
14016 // CHECK28-NEXT:    [[TMP1:%.*]] = load i16, i16* [[CONV]], align 4
14017 // CHECK28-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP1]] to i32
14018 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
14019 // CHECK28-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14020 // CHECK28-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
14021 // CHECK28-NEXT:    ret void
14022 //
14023 //
14024 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z3fooi_l144
14025 // CHECK28-SAME: (i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
14026 // CHECK28-NEXT:  entry:
14027 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
14028 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
14029 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
14030 // CHECK28-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
14031 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
14032 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
14033 // CHECK28-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
14034 // CHECK28-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
14035 // CHECK28-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
14036 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
14037 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
14038 // CHECK28-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
14039 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14040 // CHECK28-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
14041 // CHECK28-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
14042 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
14043 // CHECK28-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
14044 // CHECK28-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
14045 // CHECK28-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
14046 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
14047 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14048 // CHECK28-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
14049 // CHECK28-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
14050 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
14051 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
14052 // CHECK28-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
14053 // CHECK28-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
14054 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
14055 // CHECK28-NEXT:    store i32 [[TMP8]], i32* [[A_CASTED]], align 4
14056 // CHECK28-NEXT:    [[TMP9:%.*]] = load i32, i32* [[A_CASTED]], align 4
14057 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 9, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [10 x float]*, i32, float*, [5 x [10 x double]]*, i32, i32, double*, %struct.TT*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP9]], [10 x float]* [[TMP0]], i32 [[TMP1]], float* [[TMP2]], [5 x [10 x double]]* [[TMP3]], i32 [[TMP4]], i32 [[TMP5]], double* [[TMP6]], %struct.TT* [[TMP7]])
14058 // CHECK28-NEXT:    ret void
14059 //
14060 //
14061 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..3
14062 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], [10 x float]* nonnull align 4 dereferenceable(40) [[B:%.*]], i32 [[VLA:%.*]], float* nonnull align 4 dereferenceable(4) [[BN:%.*]], [5 x [10 x double]]* nonnull align 4 dereferenceable(400) [[C:%.*]], i32 [[VLA1:%.*]], i32 [[VLA3:%.*]], double* nonnull align 4 dereferenceable(8) [[CN:%.*]], %struct.TT* nonnull align 4 dereferenceable(12) [[D:%.*]]) #[[ATTR0]] {
14063 // CHECK28-NEXT:  entry:
14064 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14065 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14066 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
14067 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x float]*, align 4
14068 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
14069 // CHECK28-NEXT:    [[BN_ADDR:%.*]] = alloca float*, align 4
14070 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca [5 x [10 x double]]*, align 4
14071 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
14072 // CHECK28-NEXT:    [[VLA_ADDR4:%.*]] = alloca i32, align 4
14073 // CHECK28-NEXT:    [[CN_ADDR:%.*]] = alloca double*, align 4
14074 // CHECK28-NEXT:    [[D_ADDR:%.*]] = alloca %struct.TT*, align 4
14075 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14076 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14077 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
14078 // CHECK28-NEXT:    store [10 x float]* [[B]], [10 x float]** [[B_ADDR]], align 4
14079 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14080 // CHECK28-NEXT:    store float* [[BN]], float** [[BN_ADDR]], align 4
14081 // CHECK28-NEXT:    store [5 x [10 x double]]* [[C]], [5 x [10 x double]]** [[C_ADDR]], align 4
14082 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
14083 // CHECK28-NEXT:    store i32 [[VLA3]], i32* [[VLA_ADDR4]], align 4
14084 // CHECK28-NEXT:    store double* [[CN]], double** [[CN_ADDR]], align 4
14085 // CHECK28-NEXT:    store %struct.TT* [[D]], %struct.TT** [[D_ADDR]], align 4
14086 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x float]*, [10 x float]** [[B_ADDR]], align 4
14087 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14088 // CHECK28-NEXT:    [[TMP2:%.*]] = load float*, float** [[BN_ADDR]], align 4
14089 // CHECK28-NEXT:    [[TMP3:%.*]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[C_ADDR]], align 4
14090 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
14091 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[VLA_ADDR4]], align 4
14092 // CHECK28-NEXT:    [[TMP6:%.*]] = load double*, double** [[CN_ADDR]], align 4
14093 // CHECK28-NEXT:    [[TMP7:%.*]] = load %struct.TT*, %struct.TT** [[D_ADDR]], align 4
14094 // CHECK28-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A_ADDR]], align 4
14095 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP8]], 1
14096 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
14097 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[TMP0]], i32 0, i32 2
14098 // CHECK28-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
14099 // CHECK28-NEXT:    [[CONV:%.*]] = fpext float [[TMP9]] to double
14100 // CHECK28-NEXT:    [[ADD5:%.*]] = fadd double [[CONV]], 1.000000e+00
14101 // CHECK28-NEXT:    [[CONV6:%.*]] = fptrunc double [[ADD5]] to float
14102 // CHECK28-NEXT:    store float [[CONV6]], float* [[ARRAYIDX]], align 4
14103 // CHECK28-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP2]], i32 3
14104 // CHECK28-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4
14105 // CHECK28-NEXT:    [[CONV8:%.*]] = fpext float [[TMP10]] to double
14106 // CHECK28-NEXT:    [[ADD9:%.*]] = fadd double [[CONV8]], 1.000000e+00
14107 // CHECK28-NEXT:    [[CONV10:%.*]] = fptrunc double [[ADD9]] to float
14108 // CHECK28-NEXT:    store float [[CONV10]], float* [[ARRAYIDX7]], align 4
14109 // CHECK28-NEXT:    [[ARRAYIDX11:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[TMP3]], i32 0, i32 1
14110 // CHECK28-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX11]], i32 0, i32 2
14111 // CHECK28-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX12]], align 8
14112 // CHECK28-NEXT:    [[ADD13:%.*]] = fadd double [[TMP11]], 1.000000e+00
14113 // CHECK28-NEXT:    store double [[ADD13]], double* [[ARRAYIDX12]], align 8
14114 // CHECK28-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP5]]
14115 // CHECK28-NEXT:    [[ARRAYIDX14:%.*]] = getelementptr inbounds double, double* [[TMP6]], i32 [[TMP12]]
14116 // CHECK28-NEXT:    [[ARRAYIDX15:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX14]], i32 3
14117 // CHECK28-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX15]], align 8
14118 // CHECK28-NEXT:    [[ADD16:%.*]] = fadd double [[TMP13]], 1.000000e+00
14119 // CHECK28-NEXT:    store double [[ADD16]], double* [[ARRAYIDX15]], align 8
14120 // CHECK28-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT:%.*]], %struct.TT* [[TMP7]], i32 0, i32 0
14121 // CHECK28-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
14122 // CHECK28-NEXT:    [[ADD17:%.*]] = add nsw i64 [[TMP14]], 1
14123 // CHECK28-NEXT:    store i64 [[ADD17]], i64* [[X]], align 4
14124 // CHECK28-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[TMP7]], i32 0, i32 1
14125 // CHECK28-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
14126 // CHECK28-NEXT:    [[CONV18:%.*]] = sext i8 [[TMP15]] to i32
14127 // CHECK28-NEXT:    [[ADD19:%.*]] = add nsw i32 [[CONV18]], 1
14128 // CHECK28-NEXT:    [[CONV20:%.*]] = trunc i32 [[ADD19]] to i8
14129 // CHECK28-NEXT:    store i8 [[CONV20]], i8* [[Y]], align 4
14130 // CHECK28-NEXT:    ret void
14131 //
14132 //
14133 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZL7fstatici_l198
14134 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14135 // CHECK28-NEXT:  entry:
14136 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
14137 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
14138 // CHECK28-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
14139 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14140 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
14141 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
14142 // CHECK28-NEXT:    [[AAA_CASTED:%.*]] = alloca i32, align 4
14143 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
14144 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
14145 // CHECK28-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
14146 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14147 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14148 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
14149 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14150 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14151 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
14152 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
14153 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
14154 // CHECK28-NEXT:    [[CONV2:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14155 // CHECK28-NEXT:    store i16 [[TMP3]], i16* [[CONV2]], align 2
14156 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14157 // CHECK28-NEXT:    [[TMP5:%.*]] = load i8, i8* [[CONV1]], align 4
14158 // CHECK28-NEXT:    [[CONV3:%.*]] = bitcast i32* [[AAA_CASTED]] to i8*
14159 // CHECK28-NEXT:    store i8 [[TMP5]], i8* [[CONV3]], align 1
14160 // CHECK28-NEXT:    [[TMP6:%.*]] = load i32, i32* [[AAA_CASTED]], align 4
14161 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [10 x i32]*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], i32 [[TMP6]], [10 x i32]* [[TMP0]])
14162 // CHECK28-NEXT:    ret void
14163 //
14164 //
14165 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..4
14166 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], i32 [[AAA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14167 // CHECK28-NEXT:  entry:
14168 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14169 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14170 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
14171 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
14172 // CHECK28-NEXT:    [[AAA_ADDR:%.*]] = alloca i32, align 4
14173 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14174 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14175 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14176 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
14177 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
14178 // CHECK28-NEXT:    store i32 [[AAA]], i32* [[AAA_ADDR]], align 4
14179 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14180 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14181 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AAA_ADDR]] to i8*
14182 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14183 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14184 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
14185 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
14186 // CHECK28-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
14187 // CHECK28-NEXT:    [[CONV2:%.*]] = sext i16 [[TMP2]] to i32
14188 // CHECK28-NEXT:    [[ADD3:%.*]] = add nsw i32 [[CONV2]], 1
14189 // CHECK28-NEXT:    [[CONV4:%.*]] = trunc i32 [[ADD3]] to i16
14190 // CHECK28-NEXT:    store i16 [[CONV4]], i16* [[CONV]], align 4
14191 // CHECK28-NEXT:    [[TMP3:%.*]] = load i8, i8* [[CONV1]], align 4
14192 // CHECK28-NEXT:    [[CONV5:%.*]] = sext i8 [[TMP3]] to i32
14193 // CHECK28-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
14194 // CHECK28-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i8
14195 // CHECK28-NEXT:    store i8 [[CONV7]], i8* [[CONV1]], align 4
14196 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
14197 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14198 // CHECK28-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP4]], 1
14199 // CHECK28-NEXT:    store i32 [[ADD8]], i32* [[ARRAYIDX]], align 4
14200 // CHECK28-NEXT:    ret void
14201 //
14202 //
14203 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__ZN2S12r1Ei_l216
14204 // CHECK28-SAME: (%struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
14205 // CHECK28-NEXT:  entry:
14206 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
14207 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
14208 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
14209 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
14210 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
14211 // CHECK28-NEXT:    [[B_CASTED:%.*]] = alloca i32, align 4
14212 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
14213 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
14214 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14215 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
14216 // CHECK28-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
14217 // CHECK28-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
14218 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14219 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
14220 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
14221 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
14222 // CHECK28-NEXT:    store i32 [[TMP4]], i32* [[B_CASTED]], align 4
14223 // CHECK28-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B_CASTED]], align 4
14224 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.S1*, i32, i32, i32, i16*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.S1* [[TMP0]], i32 [[TMP5]], i32 [[TMP1]], i32 [[TMP2]], i16* [[TMP3]])
14225 // CHECK28-NEXT:    ret void
14226 //
14227 //
14228 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..5
14229 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.S1* [[THIS:%.*]], i32 [[B:%.*]], i32 [[VLA:%.*]], i32 [[VLA1:%.*]], i16* nonnull align 2 dereferenceable(2) [[C:%.*]]) #[[ATTR0]] {
14230 // CHECK28-NEXT:  entry:
14231 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14232 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14233 // CHECK28-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
14234 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca i32, align 4
14235 // CHECK28-NEXT:    [[VLA_ADDR:%.*]] = alloca i32, align 4
14236 // CHECK28-NEXT:    [[VLA_ADDR2:%.*]] = alloca i32, align 4
14237 // CHECK28-NEXT:    [[C_ADDR:%.*]] = alloca i16*, align 4
14238 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14239 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14240 // CHECK28-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
14241 // CHECK28-NEXT:    store i32 [[B]], i32* [[B_ADDR]], align 4
14242 // CHECK28-NEXT:    store i32 [[VLA]], i32* [[VLA_ADDR]], align 4
14243 // CHECK28-NEXT:    store i32 [[VLA1]], i32* [[VLA_ADDR2]], align 4
14244 // CHECK28-NEXT:    store i16* [[C]], i16** [[C_ADDR]], align 4
14245 // CHECK28-NEXT:    [[TMP0:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
14246 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[VLA_ADDR]], align 4
14247 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[VLA_ADDR2]], align 4
14248 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16*, i16** [[C_ADDR]], align 4
14249 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B_ADDR]], align 4
14250 // CHECK28-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
14251 // CHECK28-NEXT:    [[ADD:%.*]] = fadd double [[CONV]], 1.500000e+00
14252 // CHECK28-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[TMP0]], i32 0, i32 0
14253 // CHECK28-NEXT:    store double [[ADD]], double* [[A]], align 4
14254 // CHECK28-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[TMP0]], i32 0, i32 0
14255 // CHECK28-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
14256 // CHECK28-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
14257 // CHECK28-NEXT:    store double [[INC]], double* [[A3]], align 4
14258 // CHECK28-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
14259 // CHECK28-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP2]]
14260 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[TMP3]], i32 [[TMP6]]
14261 // CHECK28-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
14262 // CHECK28-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
14263 // CHECK28-NEXT:    ret void
14264 //
14265 //
14266 // CHECK28-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z9ftemplateIiET_i_l181
14267 // CHECK28-SAME: (i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14268 // CHECK28-NEXT:  entry:
14269 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
14270 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
14271 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14272 // CHECK28-NEXT:    [[A_CASTED:%.*]] = alloca i32, align 4
14273 // CHECK28-NEXT:    [[AA_CASTED:%.*]] = alloca i32, align 4
14274 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
14275 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
14276 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14277 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14278 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14279 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14280 // CHECK28-NEXT:    store i32 [[TMP1]], i32* [[A_CASTED]], align 4
14281 // CHECK28-NEXT:    [[TMP2:%.*]] = load i32, i32* [[A_CASTED]], align 4
14282 // CHECK28-NEXT:    [[TMP3:%.*]] = load i16, i16* [[CONV]], align 4
14283 // CHECK28-NEXT:    [[CONV1:%.*]] = bitcast i32* [[AA_CASTED]] to i16*
14284 // CHECK28-NEXT:    store i16 [[TMP3]], i16* [[CONV1]], align 2
14285 // CHECK28-NEXT:    [[TMP4:%.*]] = load i32, i32* [[AA_CASTED]], align 4
14286 // CHECK28-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, [10 x i32]*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32 [[TMP2]], i32 [[TMP4]], [10 x i32]* [[TMP0]])
14287 // CHECK28-NEXT:    ret void
14288 //
14289 //
14290 // CHECK28-LABEL: define {{[^@]+}}@.omp_outlined..6
14291 // CHECK28-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[A:%.*]], i32 [[AA:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[B:%.*]]) #[[ATTR0]] {
14292 // CHECK28-NEXT:  entry:
14293 // CHECK28-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4
14294 // CHECK28-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4
14295 // CHECK28-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
14296 // CHECK28-NEXT:    [[AA_ADDR:%.*]] = alloca i32, align 4
14297 // CHECK28-NEXT:    [[B_ADDR:%.*]] = alloca [10 x i32]*, align 4
14298 // CHECK28-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4
14299 // CHECK28-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4
14300 // CHECK28-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
14301 // CHECK28-NEXT:    store i32 [[AA]], i32* [[AA_ADDR]], align 4
14302 // CHECK28-NEXT:    store [10 x i32]* [[B]], [10 x i32]** [[B_ADDR]], align 4
14303 // CHECK28-NEXT:    [[CONV:%.*]] = bitcast i32* [[AA_ADDR]] to i16*
14304 // CHECK28-NEXT:    [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[B_ADDR]], align 4
14305 // CHECK28-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
14306 // CHECK28-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], 1
14307 // CHECK28-NEXT:    store i32 [[ADD]], i32* [[A_ADDR]], align 4
14308 // CHECK28-NEXT:    [[TMP2:%.*]] = load i16, i16* [[CONV]], align 4
14309 // CHECK28-NEXT:    [[CONV1:%.*]] = sext i16 [[TMP2]] to i32
14310 // CHECK28-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV1]], 1
14311 // CHECK28-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14312 // CHECK28-NEXT:    store i16 [[CONV3]], i16* [[CONV]], align 4
14313 // CHECK28-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP0]], i32 0, i32 2
14314 // CHECK28-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14315 // CHECK28-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP3]], 1
14316 // CHECK28-NEXT:    store i32 [[ADD4]], i32* [[ARRAYIDX]], align 4
14317 // CHECK28-NEXT:    ret void
14318 //
14319 //
14320 // CHECK29-LABEL: define {{[^@]+}}@_Z3fooi
14321 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
14322 // CHECK29-NEXT:  entry:
14323 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14324 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
14325 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
14326 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14327 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14328 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14329 // CHECK29-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14330 // CHECK29-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
14331 // CHECK29-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
14332 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14333 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
14334 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
14335 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14336 // CHECK29-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
14337 // CHECK29-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
14338 // CHECK29-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
14339 // CHECK29-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
14340 // CHECK29-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
14341 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
14342 // CHECK29-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
14343 // CHECK29-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
14344 // CHECK29-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
14345 // CHECK29-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
14346 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
14347 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
14348 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14349 // CHECK29-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
14350 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
14351 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
14352 // CHECK29-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14353 // CHECK29-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
14354 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14355 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
14356 // CHECK29-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14357 // CHECK29-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
14358 // CHECK29-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
14359 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
14360 // CHECK29-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
14361 // CHECK29-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
14362 // CHECK29-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A]], align 4
14363 // CHECK29-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
14364 // CHECK29-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
14365 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
14366 // CHECK29-NEXT:    [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4
14367 // CHECK29-NEXT:    [[CONV9:%.*]] = fpext float [[TMP11]] to double
14368 // CHECK29-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
14369 // CHECK29-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
14370 // CHECK29-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
14371 // CHECK29-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
14372 // CHECK29-NEXT:    [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4
14373 // CHECK29-NEXT:    [[CONV13:%.*]] = fpext float [[TMP12]] to double
14374 // CHECK29-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
14375 // CHECK29-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
14376 // CHECK29-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
14377 // CHECK29-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
14378 // CHECK29-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
14379 // CHECK29-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8
14380 // CHECK29-NEXT:    [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00
14381 // CHECK29-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
14382 // CHECK29-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]]
14383 // CHECK29-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]]
14384 // CHECK29-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
14385 // CHECK29-NEXT:    [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8
14386 // CHECK29-NEXT:    [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00
14387 // CHECK29-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
14388 // CHECK29-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
14389 // CHECK29-NEXT:    [[TMP16:%.*]] = load i64, i64* [[X]], align 8
14390 // CHECK29-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1
14391 // CHECK29-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
14392 // CHECK29-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
14393 // CHECK29-NEXT:    [[TMP17:%.*]] = load i8, i8* [[Y]], align 8
14394 // CHECK29-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP17]] to i32
14395 // CHECK29-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
14396 // CHECK29-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
14397 // CHECK29-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
14398 // CHECK29-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
14399 // CHECK29-NEXT:    [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14400 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP19]])
14401 // CHECK29-NEXT:    ret i32 [[TMP18]]
14402 //
14403 //
14404 // CHECK29-LABEL: define {{[^@]+}}@_Z3bari
14405 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14406 // CHECK29-NEXT:  entry:
14407 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14408 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
14409 // CHECK29-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
14410 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14411 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
14412 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14413 // CHECK29-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
14414 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
14415 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
14416 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14417 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14418 // CHECK29-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
14419 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14420 // CHECK29-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
14421 // CHECK29-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
14422 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14423 // CHECK29-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
14424 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
14425 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
14426 // CHECK29-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14427 // CHECK29-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
14428 // CHECK29-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
14429 // CHECK29-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14430 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
14431 // CHECK29-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
14432 // CHECK29-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14433 // CHECK29-NEXT:    ret i32 [[TMP8]]
14434 //
14435 //
14436 // CHECK29-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
14437 // CHECK29-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
14438 // CHECK29-NEXT:  entry:
14439 // CHECK29-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14440 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14441 // CHECK29-NEXT:    [[B:%.*]] = alloca i32, align 4
14442 // CHECK29-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14443 // CHECK29-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14444 // CHECK29-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14445 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14446 // CHECK29-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14447 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14448 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14449 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
14450 // CHECK29-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14451 // CHECK29-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
14452 // CHECK29-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
14453 // CHECK29-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
14454 // CHECK29-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
14455 // CHECK29-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
14456 // CHECK29-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
14457 // CHECK29-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
14458 // CHECK29-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
14459 // CHECK29-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
14460 // CHECK29-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
14461 // CHECK29-NEXT:    store double [[ADD2]], double* [[A]], align 8
14462 // CHECK29-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
14463 // CHECK29-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 8
14464 // CHECK29-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
14465 // CHECK29-NEXT:    store double [[INC]], double* [[A3]], align 8
14466 // CHECK29-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
14467 // CHECK29-NEXT:    [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
14468 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
14469 // CHECK29-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
14470 // CHECK29-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
14471 // CHECK29-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
14472 // CHECK29-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
14473 // CHECK29-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
14474 // CHECK29-NEXT:    [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
14475 // CHECK29-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
14476 // CHECK29-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4
14477 // CHECK29-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
14478 // CHECK29-NEXT:    [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14479 // CHECK29-NEXT:    call void @llvm.stackrestore(i8* [[TMP11]])
14480 // CHECK29-NEXT:    ret i32 [[ADD9]]
14481 //
14482 //
14483 // CHECK29-LABEL: define {{[^@]+}}@_ZL7fstatici
14484 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14485 // CHECK29-NEXT:  entry:
14486 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14487 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
14488 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
14489 // CHECK29-NEXT:    [[AAA:%.*]] = alloca i8, align 1
14490 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14491 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14492 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
14493 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
14494 // CHECK29-NEXT:    store i8 0, i8* [[AAA]], align 1
14495 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14496 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14497 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14498 // CHECK29-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
14499 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
14500 // CHECK29-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
14501 // CHECK29-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
14502 // CHECK29-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
14503 // CHECK29-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
14504 // CHECK29-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
14505 // CHECK29-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
14506 // CHECK29-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
14507 // CHECK29-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
14508 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
14509 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14510 // CHECK29-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
14511 // CHECK29-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
14512 // CHECK29-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
14513 // CHECK29-NEXT:    ret i32 [[TMP4]]
14514 //
14515 //
14516 // CHECK29-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
14517 // CHECK29-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
14518 // CHECK29-NEXT:  entry:
14519 // CHECK29-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14520 // CHECK29-NEXT:    [[A:%.*]] = alloca i32, align 4
14521 // CHECK29-NEXT:    [[AA:%.*]] = alloca i16, align 2
14522 // CHECK29-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14523 // CHECK29-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14524 // CHECK29-NEXT:    store i32 0, i32* [[A]], align 4
14525 // CHECK29-NEXT:    store i16 0, i16* [[AA]], align 2
14526 // CHECK29-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14527 // CHECK29-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14528 // CHECK29-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14529 // CHECK29-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
14530 // CHECK29-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
14531 // CHECK29-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
14532 // CHECK29-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
14533 // CHECK29-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
14534 // CHECK29-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
14535 // CHECK29-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14536 // CHECK29-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
14537 // CHECK29-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
14538 // CHECK29-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14539 // CHECK29-NEXT:    ret i32 [[TMP3]]
14540 //
14541 //
14542 // CHECK30-LABEL: define {{[^@]+}}@_Z3fooi
14543 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0:[0-9]+]] {
14544 // CHECK30-NEXT:  entry:
14545 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14546 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
14547 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
14548 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14549 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14550 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14551 // CHECK30-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14552 // CHECK30-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i64, align 8
14553 // CHECK30-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 8
14554 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14555 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
14556 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
14557 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14558 // CHECK30-NEXT:    [[TMP1:%.*]] = zext i32 [[TMP0]] to i64
14559 // CHECK30-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
14560 // CHECK30-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8
14561 // CHECK30-NEXT:    [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 4
14562 // CHECK30-NEXT:    store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8
14563 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4
14564 // CHECK30-NEXT:    [[TMP4:%.*]] = zext i32 [[TMP3]] to i64
14565 // CHECK30-NEXT:    [[TMP5:%.*]] = mul nuw i64 5, [[TMP4]]
14566 // CHECK30-NEXT:    [[VLA1:%.*]] = alloca double, i64 [[TMP5]], align 8
14567 // CHECK30-NEXT:    store i64 [[TMP4]], i64* [[__VLA_EXPR1]], align 8
14568 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
14569 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP6]], 1
14570 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14571 // CHECK30-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
14572 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP7]] to i32
14573 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
14574 // CHECK30-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14575 // CHECK30-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
14576 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14577 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP8]], 1
14578 // CHECK30-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14579 // CHECK30-NEXT:    [[TMP9:%.*]] = load i16, i16* [[AA]], align 2
14580 // CHECK30-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP9]] to i32
14581 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
14582 // CHECK30-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
14583 // CHECK30-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
14584 // CHECK30-NEXT:    [[TMP10:%.*]] = load i32, i32* [[A]], align 4
14585 // CHECK30-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP10]], 1
14586 // CHECK30-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
14587 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i64 0, i64 2
14588 // CHECK30-NEXT:    [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4
14589 // CHECK30-NEXT:    [[CONV9:%.*]] = fpext float [[TMP11]] to double
14590 // CHECK30-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
14591 // CHECK30-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
14592 // CHECK30-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
14593 // CHECK30-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 3
14594 // CHECK30-NEXT:    [[TMP12:%.*]] = load float, float* [[ARRAYIDX12]], align 4
14595 // CHECK30-NEXT:    [[CONV13:%.*]] = fpext float [[TMP12]] to double
14596 // CHECK30-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
14597 // CHECK30-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
14598 // CHECK30-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
14599 // CHECK30-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i64 0, i64 1
14600 // CHECK30-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i64 0, i64 2
14601 // CHECK30-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX17]], align 8
14602 // CHECK30-NEXT:    [[ADD18:%.*]] = fadd double [[TMP13]], 1.000000e+00
14603 // CHECK30-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
14604 // CHECK30-NEXT:    [[TMP14:%.*]] = mul nsw i64 1, [[TMP4]]
14605 // CHECK30-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i64 [[TMP14]]
14606 // CHECK30-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i64 3
14607 // CHECK30-NEXT:    [[TMP15:%.*]] = load double, double* [[ARRAYIDX20]], align 8
14608 // CHECK30-NEXT:    [[ADD21:%.*]] = fadd double [[TMP15]], 1.000000e+00
14609 // CHECK30-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
14610 // CHECK30-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
14611 // CHECK30-NEXT:    [[TMP16:%.*]] = load i64, i64* [[X]], align 8
14612 // CHECK30-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP16]], 1
14613 // CHECK30-NEXT:    store i64 [[ADD22]], i64* [[X]], align 8
14614 // CHECK30-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
14615 // CHECK30-NEXT:    [[TMP17:%.*]] = load i8, i8* [[Y]], align 8
14616 // CHECK30-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP17]] to i32
14617 // CHECK30-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
14618 // CHECK30-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
14619 // CHECK30-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 8
14620 // CHECK30-NEXT:    [[TMP18:%.*]] = load i32, i32* [[A]], align 4
14621 // CHECK30-NEXT:    [[TMP19:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14622 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP19]])
14623 // CHECK30-NEXT:    ret i32 [[TMP18]]
14624 //
14625 //
14626 // CHECK30-LABEL: define {{[^@]+}}@_Z3bari
14627 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14628 // CHECK30-NEXT:  entry:
14629 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14630 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
14631 // CHECK30-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 8
14632 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14633 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
14634 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14635 // CHECK30-NEXT:    [[CALL:%.*]] = call signext i32 @_Z3fooi(i32 signext [[TMP0]])
14636 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
14637 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
14638 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14639 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14640 // CHECK30-NEXT:    [[CALL1:%.*]] = call signext i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 8 dereferenceable(8) [[S]], i32 signext [[TMP2]])
14641 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14642 // CHECK30-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
14643 // CHECK30-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
14644 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14645 // CHECK30-NEXT:    [[CALL3:%.*]] = call signext i32 @_ZL7fstatici(i32 signext [[TMP4]])
14646 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
14647 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
14648 // CHECK30-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14649 // CHECK30-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
14650 // CHECK30-NEXT:    [[CALL5:%.*]] = call signext i32 @_Z9ftemplateIiET_i(i32 signext [[TMP6]])
14651 // CHECK30-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14652 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
14653 // CHECK30-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
14654 // CHECK30-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14655 // CHECK30-NEXT:    ret i32 [[TMP8]]
14656 //
14657 //
14658 // CHECK30-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
14659 // CHECK30-SAME: (%struct.S1* nonnull align 8 dereferenceable(8) [[THIS:%.*]], i32 signext [[N:%.*]]) #[[ATTR0]] comdat align 2 {
14660 // CHECK30-NEXT:  entry:
14661 // CHECK30-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 8
14662 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14663 // CHECK30-NEXT:    [[B:%.*]] = alloca i32, align 4
14664 // CHECK30-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 8
14665 // CHECK30-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i64, align 8
14666 // CHECK30-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 8
14667 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14668 // CHECK30-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 8
14669 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14670 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14671 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
14672 // CHECK30-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14673 // CHECK30-NEXT:    [[TMP2:%.*]] = zext i32 [[TMP1]] to i64
14674 // CHECK30-NEXT:    [[TMP3:%.*]] = call i8* @llvm.stacksave()
14675 // CHECK30-NEXT:    store i8* [[TMP3]], i8** [[SAVED_STACK]], align 8
14676 // CHECK30-NEXT:    [[TMP4:%.*]] = mul nuw i64 2, [[TMP2]]
14677 // CHECK30-NEXT:    [[VLA:%.*]] = alloca i16, i64 [[TMP4]], align 2
14678 // CHECK30-NEXT:    store i64 [[TMP2]], i64* [[__VLA_EXPR0]], align 8
14679 // CHECK30-NEXT:    [[TMP5:%.*]] = load i32, i32* [[B]], align 4
14680 // CHECK30-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP5]] to double
14681 // CHECK30-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
14682 // CHECK30-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
14683 // CHECK30-NEXT:    store double [[ADD2]], double* [[A]], align 8
14684 // CHECK30-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
14685 // CHECK30-NEXT:    [[TMP6:%.*]] = load double, double* [[A3]], align 8
14686 // CHECK30-NEXT:    [[INC:%.*]] = fadd double [[TMP6]], 1.000000e+00
14687 // CHECK30-NEXT:    store double [[INC]], double* [[A3]], align 8
14688 // CHECK30-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
14689 // CHECK30-NEXT:    [[TMP7:%.*]] = mul nsw i64 1, [[TMP2]]
14690 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP7]]
14691 // CHECK30-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i64 1
14692 // CHECK30-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
14693 // CHECK30-NEXT:    [[TMP8:%.*]] = mul nsw i64 1, [[TMP2]]
14694 // CHECK30-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i64 [[TMP8]]
14695 // CHECK30-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i64 1
14696 // CHECK30-NEXT:    [[TMP9:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
14697 // CHECK30-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP9]] to i32
14698 // CHECK30-NEXT:    [[TMP10:%.*]] = load i32, i32* [[B]], align 4
14699 // CHECK30-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP10]]
14700 // CHECK30-NEXT:    [[TMP11:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8
14701 // CHECK30-NEXT:    call void @llvm.stackrestore(i8* [[TMP11]])
14702 // CHECK30-NEXT:    ret i32 [[ADD9]]
14703 //
14704 //
14705 // CHECK30-LABEL: define {{[^@]+}}@_ZL7fstatici
14706 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] {
14707 // CHECK30-NEXT:  entry:
14708 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14709 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
14710 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
14711 // CHECK30-NEXT:    [[AAA:%.*]] = alloca i8, align 1
14712 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14713 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14714 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
14715 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
14716 // CHECK30-NEXT:    store i8 0, i8* [[AAA]], align 1
14717 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14718 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14719 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14720 // CHECK30-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
14721 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
14722 // CHECK30-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
14723 // CHECK30-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
14724 // CHECK30-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
14725 // CHECK30-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
14726 // CHECK30-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
14727 // CHECK30-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
14728 // CHECK30-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
14729 // CHECK30-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
14730 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
14731 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14732 // CHECK30-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
14733 // CHECK30-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
14734 // CHECK30-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
14735 // CHECK30-NEXT:    ret i32 [[TMP4]]
14736 //
14737 //
14738 // CHECK30-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
14739 // CHECK30-SAME: (i32 signext [[N:%.*]]) #[[ATTR0]] comdat {
14740 // CHECK30-NEXT:  entry:
14741 // CHECK30-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14742 // CHECK30-NEXT:    [[A:%.*]] = alloca i32, align 4
14743 // CHECK30-NEXT:    [[AA:%.*]] = alloca i16, align 2
14744 // CHECK30-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14745 // CHECK30-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14746 // CHECK30-NEXT:    store i32 0, i32* [[A]], align 4
14747 // CHECK30-NEXT:    store i16 0, i16* [[AA]], align 2
14748 // CHECK30-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14749 // CHECK30-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14750 // CHECK30-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14751 // CHECK30-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
14752 // CHECK30-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
14753 // CHECK30-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
14754 // CHECK30-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
14755 // CHECK30-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
14756 // CHECK30-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i64 0, i64 2
14757 // CHECK30-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14758 // CHECK30-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
14759 // CHECK30-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
14760 // CHECK30-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14761 // CHECK30-NEXT:    ret i32 [[TMP3]]
14762 //
14763 //
14764 // CHECK31-LABEL: define {{[^@]+}}@_Z3fooi
14765 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
14766 // CHECK31-NEXT:  entry:
14767 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14768 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
14769 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
14770 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14771 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
14772 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
14773 // CHECK31-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14774 // CHECK31-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
14775 // CHECK31-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
14776 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14777 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
14778 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
14779 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14780 // CHECK31-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
14781 // CHECK31-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
14782 // CHECK31-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
14783 // CHECK31-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
14784 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14785 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
14786 // CHECK31-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
14787 // CHECK31-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
14788 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
14789 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
14790 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14791 // CHECK31-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2
14792 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
14793 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
14794 // CHECK31-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
14795 // CHECK31-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
14796 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
14797 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
14798 // CHECK31-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14799 // CHECK31-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
14800 // CHECK31-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP7]] to i32
14801 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
14802 // CHECK31-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
14803 // CHECK31-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
14804 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14805 // CHECK31-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
14806 // CHECK31-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
14807 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
14808 // CHECK31-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
14809 // CHECK31-NEXT:    [[CONV9:%.*]] = fpext float [[TMP9]] to double
14810 // CHECK31-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
14811 // CHECK31-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
14812 // CHECK31-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
14813 // CHECK31-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
14814 // CHECK31-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4
14815 // CHECK31-NEXT:    [[CONV13:%.*]] = fpext float [[TMP10]] to double
14816 // CHECK31-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
14817 // CHECK31-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
14818 // CHECK31-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
14819 // CHECK31-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
14820 // CHECK31-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2
14821 // CHECK31-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8
14822 // CHECK31-NEXT:    [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00
14823 // CHECK31-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
14824 // CHECK31-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
14825 // CHECK31-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]]
14826 // CHECK31-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3
14827 // CHECK31-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8
14828 // CHECK31-NEXT:    [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00
14829 // CHECK31-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
14830 // CHECK31-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
14831 // CHECK31-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
14832 // CHECK31-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1
14833 // CHECK31-NEXT:    store i64 [[ADD22]], i64* [[X]], align 4
14834 // CHECK31-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
14835 // CHECK31-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
14836 // CHECK31-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP15]] to i32
14837 // CHECK31-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
14838 // CHECK31-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
14839 // CHECK31-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 4
14840 // CHECK31-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
14841 // CHECK31-NEXT:    [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
14842 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP17]])
14843 // CHECK31-NEXT:    ret i32 [[TMP16]]
14844 //
14845 //
14846 // CHECK31-LABEL: define {{[^@]+}}@_Z3bari
14847 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
14848 // CHECK31-NEXT:  entry:
14849 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14850 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
14851 // CHECK31-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
14852 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14853 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
14854 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14855 // CHECK31-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
14856 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
14857 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
14858 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14859 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
14860 // CHECK31-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
14861 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14862 // CHECK31-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
14863 // CHECK31-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
14864 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
14865 // CHECK31-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
14866 // CHECK31-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
14867 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
14868 // CHECK31-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
14869 // CHECK31-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
14870 // CHECK31-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
14871 // CHECK31-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
14872 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
14873 // CHECK31-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
14874 // CHECK31-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
14875 // CHECK31-NEXT:    ret i32 [[TMP8]]
14876 //
14877 //
14878 // CHECK31-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
14879 // CHECK31-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
14880 // CHECK31-NEXT:  entry:
14881 // CHECK31-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
14882 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14883 // CHECK31-NEXT:    [[B:%.*]] = alloca i32, align 4
14884 // CHECK31-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
14885 // CHECK31-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
14886 // CHECK31-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
14887 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14888 // CHECK31-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
14889 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14890 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14891 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
14892 // CHECK31-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
14893 // CHECK31-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
14894 // CHECK31-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
14895 // CHECK31-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
14896 // CHECK31-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
14897 // CHECK31-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
14898 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
14899 // CHECK31-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
14900 // CHECK31-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
14901 // CHECK31-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
14902 // CHECK31-NEXT:    store double [[ADD2]], double* [[A]], align 4
14903 // CHECK31-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
14904 // CHECK31-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
14905 // CHECK31-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
14906 // CHECK31-NEXT:    store double [[INC]], double* [[A3]], align 4
14907 // CHECK31-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
14908 // CHECK31-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
14909 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
14910 // CHECK31-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
14911 // CHECK31-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
14912 // CHECK31-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
14913 // CHECK31-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
14914 // CHECK31-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
14915 // CHECK31-NEXT:    [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
14916 // CHECK31-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
14917 // CHECK31-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4
14918 // CHECK31-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
14919 // CHECK31-NEXT:    [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
14920 // CHECK31-NEXT:    call void @llvm.stackrestore(i8* [[TMP10]])
14921 // CHECK31-NEXT:    ret i32 [[ADD9]]
14922 //
14923 //
14924 // CHECK31-LABEL: define {{[^@]+}}@_ZL7fstatici
14925 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
14926 // CHECK31-NEXT:  entry:
14927 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14928 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
14929 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
14930 // CHECK31-NEXT:    [[AAA:%.*]] = alloca i8, align 1
14931 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14932 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14933 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
14934 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
14935 // CHECK31-NEXT:    store i8 0, i8* [[AAA]], align 1
14936 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14937 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14938 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14939 // CHECK31-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
14940 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
14941 // CHECK31-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
14942 // CHECK31-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
14943 // CHECK31-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
14944 // CHECK31-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
14945 // CHECK31-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
14946 // CHECK31-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
14947 // CHECK31-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
14948 // CHECK31-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
14949 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
14950 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14951 // CHECK31-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
14952 // CHECK31-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
14953 // CHECK31-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
14954 // CHECK31-NEXT:    ret i32 [[TMP4]]
14955 //
14956 //
14957 // CHECK31-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
14958 // CHECK31-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
14959 // CHECK31-NEXT:  entry:
14960 // CHECK31-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14961 // CHECK31-NEXT:    [[A:%.*]] = alloca i32, align 4
14962 // CHECK31-NEXT:    [[AA:%.*]] = alloca i16, align 2
14963 // CHECK31-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
14964 // CHECK31-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14965 // CHECK31-NEXT:    store i32 0, i32* [[A]], align 4
14966 // CHECK31-NEXT:    store i16 0, i16* [[AA]], align 2
14967 // CHECK31-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
14968 // CHECK31-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
14969 // CHECK31-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
14970 // CHECK31-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
14971 // CHECK31-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
14972 // CHECK31-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
14973 // CHECK31-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
14974 // CHECK31-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
14975 // CHECK31-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
14976 // CHECK31-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
14977 // CHECK31-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
14978 // CHECK31-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
14979 // CHECK31-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
14980 // CHECK31-NEXT:    ret i32 [[TMP3]]
14981 //
14982 //
14983 // CHECK32-LABEL: define {{[^@]+}}@_Z3fooi
14984 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0:[0-9]+]] {
14985 // CHECK32-NEXT:  entry:
14986 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
14987 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
14988 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
14989 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x float], align 4
14990 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
14991 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
14992 // CHECK32-NEXT:    [[C:%.*]] = alloca [5 x [10 x double]], align 8
14993 // CHECK32-NEXT:    [[__VLA_EXPR1:%.*]] = alloca i32, align 4
14994 // CHECK32-NEXT:    [[D:%.*]] = alloca [[STRUCT_TT:%.*]], align 4
14995 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
14996 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
14997 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
14998 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
14999 // CHECK32-NEXT:    [[TMP1:%.*]] = call i8* @llvm.stacksave()
15000 // CHECK32-NEXT:    store i8* [[TMP1]], i8** [[SAVED_STACK]], align 4
15001 // CHECK32-NEXT:    [[VLA:%.*]] = alloca float, i32 [[TMP0]], align 4
15002 // CHECK32-NEXT:    store i32 [[TMP0]], i32* [[__VLA_EXPR0]], align 4
15003 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
15004 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 5, [[TMP2]]
15005 // CHECK32-NEXT:    [[VLA1:%.*]] = alloca double, i32 [[TMP3]], align 8
15006 // CHECK32-NEXT:    store i32 [[TMP2]], i32* [[__VLA_EXPR1]], align 4
15007 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
15008 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP4]], 1
15009 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
15010 // CHECK32-NEXT:    [[TMP5:%.*]] = load i16, i16* [[AA]], align 2
15011 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP5]] to i32
15012 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[CONV]], 1
15013 // CHECK32-NEXT:    [[CONV3:%.*]] = trunc i32 [[ADD2]] to i16
15014 // CHECK32-NEXT:    store i16 [[CONV3]], i16* [[AA]], align 2
15015 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[A]], align 4
15016 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP6]], 1
15017 // CHECK32-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
15018 // CHECK32-NEXT:    [[TMP7:%.*]] = load i16, i16* [[AA]], align 2
15019 // CHECK32-NEXT:    [[CONV5:%.*]] = sext i16 [[TMP7]] to i32
15020 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[CONV5]], 1
15021 // CHECK32-NEXT:    [[CONV7:%.*]] = trunc i32 [[ADD6]] to i16
15022 // CHECK32-NEXT:    store i16 [[CONV7]], i16* [[AA]], align 2
15023 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15024 // CHECK32-NEXT:    [[ADD8:%.*]] = add nsw i32 [[TMP8]], 1
15025 // CHECK32-NEXT:    store i32 [[ADD8]], i32* [[A]], align 4
15026 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x float], [10 x float]* [[B]], i32 0, i32 2
15027 // CHECK32-NEXT:    [[TMP9:%.*]] = load float, float* [[ARRAYIDX]], align 4
15028 // CHECK32-NEXT:    [[CONV9:%.*]] = fpext float [[TMP9]] to double
15029 // CHECK32-NEXT:    [[ADD10:%.*]] = fadd double [[CONV9]], 1.000000e+00
15030 // CHECK32-NEXT:    [[CONV11:%.*]] = fptrunc double [[ADD10]] to float
15031 // CHECK32-NEXT:    store float [[CONV11]], float* [[ARRAYIDX]], align 4
15032 // CHECK32-NEXT:    [[ARRAYIDX12:%.*]] = getelementptr inbounds float, float* [[VLA]], i32 3
15033 // CHECK32-NEXT:    [[TMP10:%.*]] = load float, float* [[ARRAYIDX12]], align 4
15034 // CHECK32-NEXT:    [[CONV13:%.*]] = fpext float [[TMP10]] to double
15035 // CHECK32-NEXT:    [[ADD14:%.*]] = fadd double [[CONV13]], 1.000000e+00
15036 // CHECK32-NEXT:    [[CONV15:%.*]] = fptrunc double [[ADD14]] to float
15037 // CHECK32-NEXT:    store float [[CONV15]], float* [[ARRAYIDX12]], align 4
15038 // CHECK32-NEXT:    [[ARRAYIDX16:%.*]] = getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[C]], i32 0, i32 1
15039 // CHECK32-NEXT:    [[ARRAYIDX17:%.*]] = getelementptr inbounds [10 x double], [10 x double]* [[ARRAYIDX16]], i32 0, i32 2
15040 // CHECK32-NEXT:    [[TMP11:%.*]] = load double, double* [[ARRAYIDX17]], align 8
15041 // CHECK32-NEXT:    [[ADD18:%.*]] = fadd double [[TMP11]], 1.000000e+00
15042 // CHECK32-NEXT:    store double [[ADD18]], double* [[ARRAYIDX17]], align 8
15043 // CHECK32-NEXT:    [[TMP12:%.*]] = mul nsw i32 1, [[TMP2]]
15044 // CHECK32-NEXT:    [[ARRAYIDX19:%.*]] = getelementptr inbounds double, double* [[VLA1]], i32 [[TMP12]]
15045 // CHECK32-NEXT:    [[ARRAYIDX20:%.*]] = getelementptr inbounds double, double* [[ARRAYIDX19]], i32 3
15046 // CHECK32-NEXT:    [[TMP13:%.*]] = load double, double* [[ARRAYIDX20]], align 8
15047 // CHECK32-NEXT:    [[ADD21:%.*]] = fadd double [[TMP13]], 1.000000e+00
15048 // CHECK32-NEXT:    store double [[ADD21]], double* [[ARRAYIDX20]], align 8
15049 // CHECK32-NEXT:    [[X:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 0
15050 // CHECK32-NEXT:    [[TMP14:%.*]] = load i64, i64* [[X]], align 4
15051 // CHECK32-NEXT:    [[ADD22:%.*]] = add nsw i64 [[TMP14]], 1
15052 // CHECK32-NEXT:    store i64 [[ADD22]], i64* [[X]], align 4
15053 // CHECK32-NEXT:    [[Y:%.*]] = getelementptr inbounds [[STRUCT_TT]], %struct.TT* [[D]], i32 0, i32 1
15054 // CHECK32-NEXT:    [[TMP15:%.*]] = load i8, i8* [[Y]], align 4
15055 // CHECK32-NEXT:    [[CONV23:%.*]] = sext i8 [[TMP15]] to i32
15056 // CHECK32-NEXT:    [[ADD24:%.*]] = add nsw i32 [[CONV23]], 1
15057 // CHECK32-NEXT:    [[CONV25:%.*]] = trunc i32 [[ADD24]] to i8
15058 // CHECK32-NEXT:    store i8 [[CONV25]], i8* [[Y]], align 4
15059 // CHECK32-NEXT:    [[TMP16:%.*]] = load i32, i32* [[A]], align 4
15060 // CHECK32-NEXT:    [[TMP17:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
15061 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP17]])
15062 // CHECK32-NEXT:    ret i32 [[TMP16]]
15063 //
15064 //
15065 // CHECK32-LABEL: define {{[^@]+}}@_Z3bari
15066 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
15067 // CHECK32-NEXT:  entry:
15068 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15069 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
15070 // CHECK32-NEXT:    [[S:%.*]] = alloca [[STRUCT_S1:%.*]], align 4
15071 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15072 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
15073 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15074 // CHECK32-NEXT:    [[CALL:%.*]] = call i32 @_Z3fooi(i32 [[TMP0]])
15075 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A]], align 4
15076 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[CALL]]
15077 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
15078 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[N_ADDR]], align 4
15079 // CHECK32-NEXT:    [[CALL1:%.*]] = call i32 @_ZN2S12r1Ei(%struct.S1* nonnull align 4 dereferenceable(8) [[S]], i32 [[TMP2]])
15080 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
15081 // CHECK32-NEXT:    [[ADD2:%.*]] = add nsw i32 [[TMP3]], [[CALL1]]
15082 // CHECK32-NEXT:    store i32 [[ADD2]], i32* [[A]], align 4
15083 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4
15084 // CHECK32-NEXT:    [[CALL3:%.*]] = call i32 @_ZL7fstatici(i32 [[TMP4]])
15085 // CHECK32-NEXT:    [[TMP5:%.*]] = load i32, i32* [[A]], align 4
15086 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[TMP5]], [[CALL3]]
15087 // CHECK32-NEXT:    store i32 [[ADD4]], i32* [[A]], align 4
15088 // CHECK32-NEXT:    [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4
15089 // CHECK32-NEXT:    [[CALL5:%.*]] = call i32 @_Z9ftemplateIiET_i(i32 [[TMP6]])
15090 // CHECK32-NEXT:    [[TMP7:%.*]] = load i32, i32* [[A]], align 4
15091 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP7]], [[CALL5]]
15092 // CHECK32-NEXT:    store i32 [[ADD6]], i32* [[A]], align 4
15093 // CHECK32-NEXT:    [[TMP8:%.*]] = load i32, i32* [[A]], align 4
15094 // CHECK32-NEXT:    ret i32 [[TMP8]]
15095 //
15096 //
15097 // CHECK32-LABEL: define {{[^@]+}}@_ZN2S12r1Ei
15098 // CHECK32-SAME: (%struct.S1* nonnull align 4 dereferenceable(8) [[THIS:%.*]], i32 [[N:%.*]]) #[[ATTR0]] comdat align 2 {
15099 // CHECK32-NEXT:  entry:
15100 // CHECK32-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S1*, align 4
15101 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15102 // CHECK32-NEXT:    [[B:%.*]] = alloca i32, align 4
15103 // CHECK32-NEXT:    [[SAVED_STACK:%.*]] = alloca i8*, align 4
15104 // CHECK32-NEXT:    [[__VLA_EXPR0:%.*]] = alloca i32, align 4
15105 // CHECK32-NEXT:    store %struct.S1* [[THIS]], %struct.S1** [[THIS_ADDR]], align 4
15106 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15107 // CHECK32-NEXT:    [[THIS1:%.*]] = load %struct.S1*, %struct.S1** [[THIS_ADDR]], align 4
15108 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4
15109 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
15110 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[B]], align 4
15111 // CHECK32-NEXT:    [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4
15112 // CHECK32-NEXT:    [[TMP2:%.*]] = call i8* @llvm.stacksave()
15113 // CHECK32-NEXT:    store i8* [[TMP2]], i8** [[SAVED_STACK]], align 4
15114 // CHECK32-NEXT:    [[TMP3:%.*]] = mul nuw i32 2, [[TMP1]]
15115 // CHECK32-NEXT:    [[VLA:%.*]] = alloca i16, i32 [[TMP3]], align 2
15116 // CHECK32-NEXT:    store i32 [[TMP1]], i32* [[__VLA_EXPR0]], align 4
15117 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[B]], align 4
15118 // CHECK32-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to double
15119 // CHECK32-NEXT:    [[ADD2:%.*]] = fadd double [[CONV]], 1.500000e+00
15120 // CHECK32-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_S1:%.*]], %struct.S1* [[THIS1]], i32 0, i32 0
15121 // CHECK32-NEXT:    store double [[ADD2]], double* [[A]], align 4
15122 // CHECK32-NEXT:    [[A3:%.*]] = getelementptr inbounds [[STRUCT_S1]], %struct.S1* [[THIS1]], i32 0, i32 0
15123 // CHECK32-NEXT:    [[TMP5:%.*]] = load double, double* [[A3]], align 4
15124 // CHECK32-NEXT:    [[INC:%.*]] = fadd double [[TMP5]], 1.000000e+00
15125 // CHECK32-NEXT:    store double [[INC]], double* [[A3]], align 4
15126 // CHECK32-NEXT:    [[CONV4:%.*]] = fptosi double [[INC]] to i16
15127 // CHECK32-NEXT:    [[TMP6:%.*]] = mul nsw i32 1, [[TMP1]]
15128 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP6]]
15129 // CHECK32-NEXT:    [[ARRAYIDX5:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX]], i32 1
15130 // CHECK32-NEXT:    store i16 [[CONV4]], i16* [[ARRAYIDX5]], align 2
15131 // CHECK32-NEXT:    [[TMP7:%.*]] = mul nsw i32 1, [[TMP1]]
15132 // CHECK32-NEXT:    [[ARRAYIDX6:%.*]] = getelementptr inbounds i16, i16* [[VLA]], i32 [[TMP7]]
15133 // CHECK32-NEXT:    [[ARRAYIDX7:%.*]] = getelementptr inbounds i16, i16* [[ARRAYIDX6]], i32 1
15134 // CHECK32-NEXT:    [[TMP8:%.*]] = load i16, i16* [[ARRAYIDX7]], align 2
15135 // CHECK32-NEXT:    [[CONV8:%.*]] = sext i16 [[TMP8]] to i32
15136 // CHECK32-NEXT:    [[TMP9:%.*]] = load i32, i32* [[B]], align 4
15137 // CHECK32-NEXT:    [[ADD9:%.*]] = add nsw i32 [[CONV8]], [[TMP9]]
15138 // CHECK32-NEXT:    [[TMP10:%.*]] = load i8*, i8** [[SAVED_STACK]], align 4
15139 // CHECK32-NEXT:    call void @llvm.stackrestore(i8* [[TMP10]])
15140 // CHECK32-NEXT:    ret i32 [[ADD9]]
15141 //
15142 //
15143 // CHECK32-LABEL: define {{[^@]+}}@_ZL7fstatici
15144 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] {
15145 // CHECK32-NEXT:  entry:
15146 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15147 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
15148 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
15149 // CHECK32-NEXT:    [[AAA:%.*]] = alloca i8, align 1
15150 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15151 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15152 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
15153 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
15154 // CHECK32-NEXT:    store i8 0, i8* [[AAA]], align 1
15155 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
15156 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
15157 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
15158 // CHECK32-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
15159 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
15160 // CHECK32-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
15161 // CHECK32-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
15162 // CHECK32-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
15163 // CHECK32-NEXT:    [[TMP2:%.*]] = load i8, i8* [[AAA]], align 1
15164 // CHECK32-NEXT:    [[CONV3:%.*]] = sext i8 [[TMP2]] to i32
15165 // CHECK32-NEXT:    [[ADD4:%.*]] = add nsw i32 [[CONV3]], 1
15166 // CHECK32-NEXT:    [[CONV5:%.*]] = trunc i32 [[ADD4]] to i8
15167 // CHECK32-NEXT:    store i8 [[CONV5]], i8* [[AAA]], align 1
15168 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
15169 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
15170 // CHECK32-NEXT:    [[ADD6:%.*]] = add nsw i32 [[TMP3]], 1
15171 // CHECK32-NEXT:    store i32 [[ADD6]], i32* [[ARRAYIDX]], align 4
15172 // CHECK32-NEXT:    [[TMP4:%.*]] = load i32, i32* [[A]], align 4
15173 // CHECK32-NEXT:    ret i32 [[TMP4]]
15174 //
15175 //
15176 // CHECK32-LABEL: define {{[^@]+}}@_Z9ftemplateIiET_i
15177 // CHECK32-SAME: (i32 [[N:%.*]]) #[[ATTR0]] comdat {
15178 // CHECK32-NEXT:  entry:
15179 // CHECK32-NEXT:    [[N_ADDR:%.*]] = alloca i32, align 4
15180 // CHECK32-NEXT:    [[A:%.*]] = alloca i32, align 4
15181 // CHECK32-NEXT:    [[AA:%.*]] = alloca i16, align 2
15182 // CHECK32-NEXT:    [[B:%.*]] = alloca [10 x i32], align 4
15183 // CHECK32-NEXT:    store i32 [[N]], i32* [[N_ADDR]], align 4
15184 // CHECK32-NEXT:    store i32 0, i32* [[A]], align 4
15185 // CHECK32-NEXT:    store i16 0, i16* [[AA]], align 2
15186 // CHECK32-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A]], align 4
15187 // CHECK32-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], 1
15188 // CHECK32-NEXT:    store i32 [[ADD]], i32* [[A]], align 4
15189 // CHECK32-NEXT:    [[TMP1:%.*]] = load i16, i16* [[AA]], align 2
15190 // CHECK32-NEXT:    [[CONV:%.*]] = sext i16 [[TMP1]] to i32
15191 // CHECK32-NEXT:    [[ADD1:%.*]] = add nsw i32 [[CONV]], 1
15192 // CHECK32-NEXT:    [[CONV2:%.*]] = trunc i32 [[ADD1]] to i16
15193 // CHECK32-NEXT:    store i16 [[CONV2]], i16* [[AA]], align 2
15194 // CHECK32-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[B]], i32 0, i32 2
15195 // CHECK32-NEXT:    [[TMP2:%.*]] = load i32, i32* [[ARRAYIDX]], align 4
15196 // CHECK32-NEXT:    [[ADD3:%.*]] = add nsw i32 [[TMP2]], 1
15197 // CHECK32-NEXT:    store i32 [[ADD3]], i32* [[ARRAYIDX]], align 4
15198 // CHECK32-NEXT:    [[TMP3:%.*]] = load i32, i32* [[A]], align 4
15199 // CHECK32-NEXT:    ret i32 [[TMP3]]
15200 //
15201