1 // Test host codegen. 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 8 9 // Test target codegen - host bc file has to be created first. 10 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 11 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 12 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 13 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 15 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 16 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 17 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 18 19 // expected-no-diagnostics 20 #ifndef HEADER 21 #define HEADER 22 23 // CHECK-DAG: [[TT:%.+]] = type { i64, i8 } 24 // CHECK-DAG: [[S1:%.+]] = type { double } 25 // CHECK-DAG: [[ENTTY:%.+]] = type { i8*, i8*, i[[SZ:32|64]], i32, i32 } 26 // CHECK-DAG: [[DEVTY:%.+]] = type { i8*, i8*, [[ENTTY]]*, [[ENTTY]]* } 27 // CHECK-DAG: [[DSCTY:%.+]] = type { i32, [[DEVTY]]*, [[ENTTY]]*, [[ENTTY]]* } 28 29 // TCHECK: [[ENTTY:%.+]] = type { i8*, i8*, i{{32|64}}, i32, i32 } 30 31 // CHECK-DAG: $[[REGFN:\.omp_offloading\..+]] = comdat 32 33 // We have 8 target regions, but only 7 that actually will generate offloading 34 // code, only 6 will have mapped arguments, and only 4 have all-constant map 35 // sizes. 36 37 // CHECK-DAG: [[SIZET2:@.+]] = private unnamed_addr constant [1 x i{{32|64}}] [i[[SZ:32|64]] 2] 38 // CHECK-DAG: [[MAPT2:@.+]] = private unnamed_addr constant [1 x i32] [i32 288] 39 // CHECK-DAG: [[SIZET3:@.+]] = private unnamed_addr constant [2 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2] 40 // CHECK-DAG: [[MAPT3:@.+]] = private unnamed_addr constant [2 x i32] [i32 288, i32 288] 41 // CHECK-DAG: [[MAPT4:@.+]] = private unnamed_addr constant [9 x i32] [i32 288, i32 547, i32 288, i32 547, i32 547, i32 288, i32 288, i32 547, i32 547] 42 // CHECK-DAG: [[SIZET5:@.+]] = private unnamed_addr constant [3 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 40] 43 // CHECK-DAG: [[MAPT5:@.+]] = private unnamed_addr constant [3 x i32] [i32 288, i32 288, i32 547] 44 // CHECK-DAG: [[SIZET6:@.+]] = private unnamed_addr constant [4 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 1, i[[SZ]] 40] 45 // CHECK-DAG: [[MAPT6:@.+]] = private unnamed_addr constant [4 x i32] [i32 288, i32 288, i32 288, i32 547] 46 // CHECK-DAG: [[MAPT7:@.+]] = private unnamed_addr constant [5 x i32] [i32 547, i32 288, i32 288, i32 288, i32 547] 47 // CHECK-DAG: @{{.*}} = private constant i8 0 48 // CHECK-DAG: @{{.*}} = private constant i8 0 49 // CHECK-DAG: @{{.*}} = private constant i8 0 50 // CHECK-DAG: @{{.*}} = private constant i8 0 51 // CHECK-DAG: @{{.*}} = private constant i8 0 52 // CHECK-DAG: @{{.*}} = private constant i8 0 53 // CHECK-DAG: @{{.*}} = private constant i8 0 54 55 // TCHECK: @{{.+}} = constant [[ENTTY]] 56 // TCHECK: @{{.+}} = constant [[ENTTY]] 57 // TCHECK: @{{.+}} = constant [[ENTTY]] 58 // TCHECK: @{{.+}} = constant [[ENTTY]] 59 // TCHECK: @{{.+}} = constant [[ENTTY]] 60 // TCHECK: @{{.+}} = constant [[ENTTY]] 61 // TCHECK: @{{.+}} = constant [[ENTTY]] 62 // TCHECK-NOT: @{{.+}} = constant [[ENTTY]] 63 64 // Check if offloading descriptor is created. 65 // CHECK: [[ENTBEGIN:@.+]] = external constant [[ENTTY]] 66 // CHECK: [[ENTEND:@.+]] = external constant [[ENTTY]] 67 // CHECK: [[DEVBEGIN:@.+]] = external constant i8 68 // CHECK: [[DEVEND:@.+]] = external constant i8 69 // CHECK: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x [[DEVTY]]] [{{.+}} { i8* [[DEVBEGIN]], i8* [[DEVEND]], [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }], comdat($[[REGFN]]) 70 // CHECK: [[DESC:@.+]] = internal constant [[DSCTY]] { i32 1, [[DEVTY]]* getelementptr inbounds ([1 x [[DEVTY]]], [1 x [[DEVTY]]]* [[IMAGES]], i32 0, i32 0), [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }, comdat($[[REGFN]]) 71 72 // Check target registration is registered as a Ctor. 73 // CHECK: appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* bitcast (void (i8*)* @[[REGFN]] to void ()*), i8* bitcast (void (i8*)* @[[REGFN]] to i8*) }] 74 75 76 template<typename tx, typename ty> 77 struct TT{ 78 tx X; 79 ty Y; 80 }; 81 82 int global; 83 extern int global; 84 85 // CHECK: define {{.*}}[[FOO:@.+]]( 86 int foo(int n) { 87 int a = 0; 88 short aa = 0; 89 float b[10]; 90 float bn[n]; 91 double c[5][10]; 92 double cn[5][n]; 93 TT<long long, char> d; 94 95 // CHECK: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i32* null) 96 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 97 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 98 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 99 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 100 // CHECK: [[FAIL]] 101 // CHECK: call void [[HVT0:@.+]]() 102 // CHECK-NEXT: br label %[[END]] 103 // CHECK: [[END]] 104 #pragma omp target 105 { 106 } 107 108 // CHECK: store i32 0, i32* [[RHV:%.+]], align 4 109 // CHECK: store i32 -1, i32* [[RHV]], align 4 110 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 111 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 112 // CHECK: call void [[HVT1:@.+]](i[[SZ]] {{[^,]+}}) 113 #pragma omp target if(0) firstprivate(global) 114 { 115 global += 1; 116 } 117 118 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 1, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i[[SZ]]* getelementptr inbounds ([1 x i[[SZ]]], [1 x i[[SZ]]]* [[SIZET2]], i32 0, i32 0), i32* getelementptr inbounds ([1 x i32], [1 x i32]* [[MAPT2]], i32 0, i32 0)) 119 // CHECK-DAG: [[BP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPR:%[^,]+]], i32 0, i32 0 120 // CHECK-DAG: [[P]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PR:%[^,]+]], i32 0, i32 0 121 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPR]], i32 0, i32 [[IDX0:[0-9]+]] 122 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PR]], i32 0, i32 [[IDX0]] 123 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 124 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 125 // CHECK-DAG: store i[[SZ]] [[BP0:%[^,]+]], i[[SZ]]* [[CBPADDR0]] 126 // CHECK-DAG: store i[[SZ]] [[P0:%[^,]+]], i[[SZ]]* [[CPADDR0]] 127 128 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 129 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 130 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 131 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 132 // CHECK: [[FAIL]] 133 // CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}}) 134 // CHECK-NEXT: br label %[[END]] 135 // CHECK: [[END]] 136 #pragma omp target if(1) 137 { 138 aa += 1; 139 } 140 141 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 10 142 // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]] 143 // CHECK: [[IFTHEN]] 144 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([2 x i[[SZ]]], [2 x i[[SZ]]]* [[SIZET3]], i32 0, i32 0), i32* getelementptr inbounds ([2 x i32], [2 x i32]* [[MAPT3]], i32 0, i32 0)) 145 // CHECK-DAG: [[BPR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP:%[^,]+]], i32 0, i32 0 146 // CHECK-DAG: [[PR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P:%[^,]+]], i32 0, i32 0 147 148 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 0 149 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 0 150 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 151 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 152 // CHECK-DAG: store i[[SZ]] [[BP0:%[^,]+]], i[[SZ]]* [[CBPADDR0]] 153 // CHECK-DAG: store i[[SZ]] [[P0:%[^,]+]], i[[SZ]]* [[CPADDR0]] 154 155 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 1 156 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 1 157 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* 158 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* 159 // CHECK-DAG: store i[[SZ]] [[BP1:%[^,]+]], i[[SZ]]* [[CBPADDR1]] 160 // CHECK-DAG: store i[[SZ]] [[P1:%[^,]+]], i[[SZ]]* [[CPADDR1]] 161 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 162 // CHECK-NEXT: br label %[[IFEND:.+]] 163 164 // CHECK: [[IFELSE]] 165 // CHECK: store i32 -1, i32* [[RHV]], align 4 166 // CHECK-NEXT: br label %[[IFEND:.+]] 167 168 // CHECK: [[IFEND]] 169 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 170 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 171 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 172 // CHECK: [[FAIL]] 173 // CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}}) 174 // CHECK-NEXT: br label %[[END]] 175 // CHECK: [[END]] 176 #pragma omp target if(n>10) 177 { 178 a += 1; 179 aa += 1; 180 } 181 182 // We capture 3 VLA sizes in this target region 183 // CHECK-64: [[A_VAL:%.+]] = load i32, i32* %{{.+}}, 184 // CHECK-64: [[A_ADDR:%.+]] = bitcast i[[SZ]]* [[A_CADDR:%.+]] to i32* 185 // CHECK-64: store i32 [[A_VAL]], i32* [[A_ADDR]], 186 // CHECK-64: [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]], 187 188 // CHECK-32: [[A_VAL:%.+]] = load i32, i32* %{{.+}}, 189 // CHECK-32: store i32 [[A_VAL]], i32* [[A_CADDR:%.+]], 190 // CHECK-32: [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]], 191 192 // CHECK: [[BNSIZE:%.+]] = mul nuw i[[SZ]] [[VLA0:%.+]], 4 193 // CHECK: [[CNELEMSIZE2:%.+]] = mul nuw i[[SZ]] 5, [[VLA1:%.+]] 194 // CHECK: [[CNSIZE:%.+]] = mul nuw i[[SZ]] [[CNELEMSIZE2]], 8 195 196 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 20 197 // CHECK: br i1 [[IF]], label %[[TRY:[^,]+]], label %[[FAIL:[^,]+]] 198 // CHECK: [[TRY]] 199 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 9, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SR:%[^,]+]], i32* getelementptr inbounds ([9 x i32], [9 x i32]* [[MAPT4]], i32 0, i32 0)) 200 // CHECK-DAG: [[BPR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP:%[^,]+]], i32 0, i32 0 201 // CHECK-DAG: [[PR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P:%[^,]+]], i32 0, i32 0 202 // CHECK-DAG: [[SR]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S:%[^,]+]], i32 0, i32 0 203 204 // CHECK-DAG: [[SADDR0:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX0:0]] 205 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX0]] 206 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX0]] 207 // CHECK-DAG: [[SADDR1:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX1:1]] 208 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX1]] 209 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX1]] 210 // CHECK-DAG: [[SADDR2:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX2:2]] 211 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX2]] 212 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX2]] 213 // CHECK-DAG: [[SADDR3:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX3:3]] 214 // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX3]] 215 // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX3]] 216 // CHECK-DAG: [[SADDR4:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX4:4]] 217 // CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX4]] 218 // CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX4]] 219 // CHECK-DAG: [[SADDR5:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX5:5]] 220 // CHECK-DAG: [[BPADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX5]] 221 // CHECK-DAG: [[PADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX5]] 222 // CHECK-DAG: [[SADDR6:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX6:6]] 223 // CHECK-DAG: [[BPADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX6]] 224 // CHECK-DAG: [[PADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX6]] 225 // CHECK-DAG: [[SADDR7:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX7:7]] 226 // CHECK-DAG: [[BPADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX7]] 227 // CHECK-DAG: [[PADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX7]] 228 // CHECK-DAG: [[SADDR8:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX8:8]] 229 // CHECK-DAG: [[BPADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX8]] 230 // CHECK-DAG: [[PADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX8]] 231 232 // The names below are not necessarily consistent with the names used for the 233 // addresses above as some are repeated. 234 // CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to i[[SZ]]* 235 // CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to i[[SZ]]* 236 // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CBPADDR2]] 237 // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CPADDR2]] 238 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR2]] 239 240 // CHECK-DAG: [[CBPADDR6:%.+]] = bitcast i8** [[BPADDR6]] to i[[SZ]]* 241 // CHECK-DAG: [[CPADDR6:%.+]] = bitcast i8** [[PADDR6]] to i[[SZ]]* 242 // CHECK-DAG: store i[[SZ]] [[VLA1]], i[[SZ]]* [[CBPADDR6]] 243 // CHECK-DAG: store i[[SZ]] [[VLA1]], i[[SZ]]* [[CPADDR6]] 244 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR6]] 245 246 // CHECK-DAG: [[CBPADDR5:%.+]] = bitcast i8** [[BPADDR5]] to i[[SZ]]* 247 // CHECK-DAG: [[CPADDR5:%.+]] = bitcast i8** [[PADDR5]] to i[[SZ]]* 248 // CHECK-DAG: store i[[SZ]] 5, i[[SZ]]* [[CBPADDR5]] 249 // CHECK-DAG: store i[[SZ]] 5, i[[SZ]]* [[CPADDR5]] 250 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR5]] 251 252 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 253 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 254 // CHECK-DAG: store i[[SZ]] [[A_CVAL]], i[[SZ]]* [[CBPADDR0]] 255 // CHECK-DAG: store i[[SZ]] [[A_CVAL]], i[[SZ]]* [[CPADDR0]] 256 // CHECK-DAG: store i[[SZ]] 4, i[[SZ]]* [[SADDR0]] 257 258 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to [10 x float]** 259 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to [10 x float]** 260 // CHECK-DAG: store [10 x float]* %{{.+}}, [10 x float]** [[CBPADDR1]] 261 // CHECK-DAG: store [10 x float]* %{{.+}}, [10 x float]** [[CPADDR1]] 262 // CHECK-DAG: store i[[SZ]] 40, i[[SZ]]* [[SADDR1]] 263 264 // CHECK-DAG: [[CBPADDR3:%.+]] = bitcast i8** [[BPADDR3]] to float** 265 // CHECK-DAG: [[CPADDR3:%.+]] = bitcast i8** [[PADDR3]] to float** 266 // CHECK-DAG: store float* %{{.+}}, float** [[CBPADDR3]] 267 // CHECK-DAG: store float* %{{.+}}, float** [[CPADDR3]] 268 // CHECK-DAG: store i[[SZ]] [[BNSIZE]], i[[SZ]]* [[SADDR3]] 269 270 // CHECK-DAG: [[CBPADDR4:%.+]] = bitcast i8** [[BPADDR4]] to [5 x [10 x double]]** 271 // CHECK-DAG: [[CPADDR4:%.+]] = bitcast i8** [[PADDR4]] to [5 x [10 x double]]** 272 // CHECK-DAG: store [5 x [10 x double]]* %{{.+}}, [5 x [10 x double]]** [[CBPADDR4]] 273 // CHECK-DAG: store [5 x [10 x double]]* %{{.+}}, [5 x [10 x double]]** [[CPADDR4]] 274 // CHECK-DAG: store i[[SZ]] 400, i[[SZ]]* [[SADDR4]] 275 276 // CHECK-DAG: [[CBPADDR7:%.+]] = bitcast i8** [[BPADDR7]] to double** 277 // CHECK-DAG: [[CPADDR7:%.+]] = bitcast i8** [[PADDR7]] to double** 278 // CHECK-DAG: store double* %{{.+}}, double** [[CBPADDR7]] 279 // CHECK-DAG: store double* %{{.+}}, double** [[CPADDR7]] 280 // CHECK-DAG: store i[[SZ]] [[CNSIZE]], i[[SZ]]* [[SADDR7]] 281 282 // CHECK-DAG: [[CBPADDR8:%.+]] = bitcast i8** [[BPADDR8]] to [[TT]]** 283 // CHECK-DAG: [[CPADDR8:%.+]] = bitcast i8** [[PADDR8]] to [[TT]]** 284 // CHECK-DAG: store [[TT]]* %{{.+}}, [[TT]]** [[CBPADDR8]] 285 // CHECK-DAG: store [[TT]]* %{{.+}}, [[TT]]** [[CPADDR8]] 286 // CHECK-DAG: store i[[SZ]] {{12|16}}, i[[SZ]]* [[SADDR8]] 287 288 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 289 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 290 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 291 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 292 293 // CHECK: [[FAIL]] 294 // CHECK: call void [[HVT4:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 295 // CHECK-NEXT: br label %[[END]] 296 // CHECK: [[END]] 297 #pragma omp target if(n>20) 298 { 299 a += 1; 300 b[2] += 1.0; 301 bn[3] += 1.0; 302 c[1][2] += 1.0; 303 cn[1][3] += 1.0; 304 d.X += 1; 305 d.Y += 1; 306 } 307 308 return a; 309 } 310 311 // Check that the offloading functions are emitted and that the arguments are 312 // correct and loaded correctly for the target regions in foo(). 313 314 // CHECK: define internal void [[HVT0]]() 315 316 // CHECK: define internal void [[HVT1]](i[[SZ]] %{{.+}}) 317 // Create stack storage and store argument in there. 318 // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align 319 // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align 320 // CHECK-64: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i32* 321 // CHECK-64: load i32, i32* [[AA_CADDR]], align 322 // CHECK-32: load i32, i32* [[AA_ADDR]], align 323 324 // CHECK: define internal void [[HVT2]](i[[SZ]] %{{.+}}) 325 // Create stack storage and store argument in there. 326 // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align 327 // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align 328 // CHECK: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* 329 // CHECK: load i16, i16* [[AA_CADDR]], align 330 331 // CHECK: define internal void [[HVT3]] 332 // Create stack storage and store argument in there. 333 // CHECK: [[A_ADDR:%.+]] = alloca i[[SZ]], align 334 // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align 335 // CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[A_ADDR]], align 336 // CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align 337 // CHECK-64-DAG:[[A_CADDR:%.+]] = bitcast i[[SZ]]* [[A_ADDR]] to i32* 338 // CHECK-DAG: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* 339 // CHECK-64-DAG:load i32, i32* [[A_CADDR]], align 340 // CHECK-32-DAG:load i32, i32* [[A_ADDR]], align 341 // CHECK-DAG: load i16, i16* [[AA_CADDR]], align 342 343 // CHECK: define internal void [[HVT4]] 344 // Create local storage for each capture. 345 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] 346 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x float]* 347 // CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]] 348 // CHECK: [[LOCAL_BN:%.+]] = alloca float* 349 // CHECK: [[LOCAL_C:%.+]] = alloca [5 x [10 x double]]* 350 // CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]] 351 // CHECK: [[LOCAL_VLA3:%.+]] = alloca i[[SZ]] 352 // CHECK: [[LOCAL_CN:%.+]] = alloca double* 353 // CHECK: [[LOCAL_D:%.+]] = alloca [[TT]]* 354 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 355 // CHECK-DAG: store [10 x float]* [[ARG_B:%.+]], [10 x float]** [[LOCAL_B]] 356 // CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]] 357 // CHECK-DAG: store float* [[ARG_BN:%.+]], float** [[LOCAL_BN]] 358 // CHECK-DAG: store [5 x [10 x double]]* [[ARG_C:%.+]], [5 x [10 x double]]** [[LOCAL_C]] 359 // CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]] 360 // CHECK-DAG: store i[[SZ]] [[ARG_VLA3:%.+]], i[[SZ]]* [[LOCAL_VLA3]] 361 // CHECK-DAG: store double* [[ARG_CN:%.+]], double** [[LOCAL_CN]] 362 // CHECK-DAG: store [[TT]]* [[ARG_D:%.+]], [[TT]]** [[LOCAL_D]] 363 364 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 365 // CHECK-DAG: [[REF_B:%.+]] = load [10 x float]*, [10 x float]** [[LOCAL_B]], 366 // CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]], 367 // CHECK-DAG: [[REF_BN:%.+]] = load float*, float** [[LOCAL_BN]], 368 // CHECK-DAG: [[REF_C:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[LOCAL_C]], 369 // CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]], 370 // CHECK-DAG: [[VAL_VLA3:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA3]], 371 // CHECK-DAG: [[REF_CN:%.+]] = load double*, double** [[LOCAL_CN]], 372 // CHECK-DAG: [[REF_D:%.+]] = load [[TT]]*, [[TT]]** [[LOCAL_D]], 373 374 // Use captures. 375 // CHECK-64-DAG: load i32, i32* [[REF_A]] 376 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 377 // CHECK-DAG: getelementptr inbounds [10 x float], [10 x float]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 378 // CHECK-DAG: getelementptr inbounds float, float* [[REF_BN]], i[[SZ]] 3 379 // CHECK-DAG: getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[REF_C]], i[[SZ]] 0, i[[SZ]] 1 380 // CHECK-DAG: getelementptr inbounds double, double* [[REF_CN]], i[[SZ]] %{{.+}} 381 // CHECK-DAG: getelementptr inbounds [[TT]], [[TT]]* [[REF_D]], i32 0, i32 0 382 383 template<typename tx> 384 tx ftemplate(int n) { 385 tx a = 0; 386 short aa = 0; 387 tx b[10]; 388 389 #pragma omp target if(n>40) 390 { 391 a += 1; 392 aa += 1; 393 b[2] += 1; 394 } 395 396 return a; 397 } 398 399 static 400 int fstatic(int n) { 401 int a = 0; 402 short aa = 0; 403 char aaa = 0; 404 int b[10]; 405 406 #pragma omp target if(n>50) 407 { 408 a += 1; 409 aa += 1; 410 aaa += 1; 411 b[2] += 1; 412 } 413 414 return a; 415 } 416 417 struct S1 { 418 double a; 419 420 int r1(int n){ 421 int b = n+1; 422 short int c[2][n]; 423 424 #pragma omp target if(n>60) 425 { 426 this->a = (double)b + 1.5; 427 c[1][1] = ++a; 428 } 429 430 return c[1][1] + (int)b; 431 } 432 }; 433 434 // CHECK: define {{.*}}@{{.*}}bar{{.*}} 435 int bar(int n){ 436 int a = 0; 437 438 // CHECK: call {{.*}}i32 [[FOO]](i32 {{.*}}) 439 a += foo(n); 440 441 S1 S; 442 // CHECK: call {{.*}}i32 [[FS1:@.+]]([[S1]]* {{.*}}, i32 {{.*}}) 443 a += S.r1(n); 444 445 // CHECK: call {{.*}}i32 [[FSTATIC:@.+]](i32 {{.*}}) 446 a += fstatic(n); 447 448 // CHECK: call {{.*}}i32 [[FTEMPLATE:@.+]](i32 {{.*}}) 449 a += ftemplate<int>(n); 450 451 return a; 452 } 453 454 // 455 // CHECK: define {{.*}}[[FS1]] 456 // 457 // CHECK: i8* @llvm.stacksave() 458 // CHECK-64: [[B_ADDR:%.+]] = bitcast i[[SZ]]* [[B_CADDR:%.+]] to i32* 459 // CHECK-64: store i32 %{{.+}}, i32* [[B_ADDR]], 460 // CHECK-64: [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]], 461 462 // CHECK-32: store i32 %{{.+}}, i32* [[B_ADDR:%.+]], 463 // CHECK-32: [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]], 464 465 // We capture 2 VLA sizes in this target region 466 // CHECK: [[CELEMSIZE2:%.+]] = mul nuw i[[SZ]] 2, [[VLA0:%.+]] 467 // CHECK: [[CSIZE:%.+]] = mul nuw i[[SZ]] [[CELEMSIZE2]], 2 468 469 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 60 470 // CHECK: br i1 [[IF]], label %[[TRY:[^,]+]], label %[[FAIL:[^,]+]] 471 // CHECK: [[TRY]] 472 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 5, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SR:%[^,]+]], i32* getelementptr inbounds ([5 x i32], [5 x i32]* [[MAPT7]], i32 0, i32 0)) 473 // CHECK-DAG: [[BPR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP:%.+]], i32 0, i32 0 474 // CHECK-DAG: [[PR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P:%.+]], i32 0, i32 0 475 // CHECK-DAG: [[SR]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S:%.+]], i32 0, i32 0 476 // CHECK-DAG: [[SADDR0:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX0:0]] 477 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX0]] 478 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX0]] 479 // CHECK-DAG: [[SADDR1:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX1:1]] 480 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX1]] 481 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX1]] 482 // CHECK-DAG: [[SADDR2:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX2:2]] 483 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX2]] 484 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX2]] 485 // CHECK-DAG: [[SADDR3:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX3:3]] 486 // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX3]] 487 // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX3]] 488 // CHECK-DAG: [[SADDR4:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX4:4]] 489 // CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX4]] 490 // CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX4]] 491 492 // The names below are not necessarily consistent with the names used for the 493 // addresses above as some are repeated. 494 // CHECK-DAG: [[CBPADDR3:%.+]] = bitcast i8** [[BPADDR3]] to i[[SZ]]* 495 // CHECK-DAG: [[CPADDR3:%.+]] = bitcast i8** [[PADDR3]] to i[[SZ]]* 496 // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CBPADDR3]] 497 // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CPADDR3]] 498 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR3]] 499 500 // CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to i[[SZ]]* 501 // CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to i[[SZ]]* 502 // CHECK-DAG: store i[[SZ]] 2, i[[SZ]]* [[CBPADDR2]] 503 // CHECK-DAG: store i[[SZ]] 2, i[[SZ]]* [[CPADDR2]] 504 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR2]] 505 506 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* 507 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* 508 // CHECK-DAG: store i[[SZ]] [[B_CVAL]], i[[SZ]]* [[CBPADDR1]] 509 // CHECK-DAG: store i[[SZ]] [[B_CVAL]], i[[SZ]]* [[CPADDR1]] 510 // CHECK-DAG: store i[[SZ]] 4, i[[SZ]]* [[SADDR1]] 511 512 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to [[S1]]** 513 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to double** 514 // CHECK-DAG: store [[S1]]* %{{.+}}, [[S1]]** [[CBPADDR0]] 515 // CHECK-DAG: store double* %{{.+}}, double** [[CPADDR0]] 516 // CHECK-DAG: store i[[SZ]] 8, i[[SZ]]* [[SADDR0]] 517 518 // CHECK-DAG: [[CBPADDR4:%.+]] = bitcast i8** [[BPADDR4]] to i16** 519 // CHECK-DAG: [[CPADDR4:%.+]] = bitcast i8** [[PADDR4]] to i16** 520 // CHECK-DAG: store i16* %{{.+}}, i16** [[CBPADDR4]] 521 // CHECK-DAG: store i16* %{{.+}}, i16** [[CPADDR4]] 522 // CHECK-DAG: store i[[SZ]] [[CSIZE]], i[[SZ]]* [[SADDR4]] 523 524 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 525 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 526 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 527 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 528 529 // CHECK: [[FAIL]] 530 // CHECK: call void [[HVT7:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 531 // CHECK-NEXT: br label %[[END]] 532 // CHECK: [[END]] 533 534 // 535 // CHECK: define {{.*}}[[FSTATIC]] 536 // 537 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 50 538 // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]] 539 // CHECK: [[IFTHEN]] 540 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 4, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([4 x i[[SZ]]], [4 x i[[SZ]]]* [[SIZET6]], i32 0, i32 0), i32* getelementptr inbounds ([4 x i32], [4 x i32]* [[MAPT6]], i32 0, i32 0)) 541 // CHECK-DAG: [[BPR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP:%.+]], i32 0, i32 0 542 // CHECK-DAG: [[PR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P:%.+]], i32 0, i32 0 543 544 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 0 545 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 0 546 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 547 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 548 // CHECK-DAG: store i[[SZ]] [[VAL0:%[^,]+]], i[[SZ]]* [[CBPADDR0]] 549 // CHECK-DAG: store i[[SZ]] [[VAL0]], i[[SZ]]* [[CPADDR0]] 550 551 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 1 552 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 1 553 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* 554 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* 555 // CHECK-DAG: store i[[SZ]] [[VAL1:%[^,]+]], i[[SZ]]* [[CBPADDR1]] 556 // CHECK-DAG: store i[[SZ]] [[VAL1]], i[[SZ]]* [[CPADDR1]] 557 558 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 2 559 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 2 560 // CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to i[[SZ]]* 561 // CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to i[[SZ]]* 562 // CHECK-DAG: store i[[SZ]] [[VAL2:%[^,]+]], i[[SZ]]* [[CBPADDR2]] 563 // CHECK-DAG: store i[[SZ]] [[VAL2]], i[[SZ]]* [[CPADDR2]] 564 565 // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 3 566 // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 3 567 // CHECK-DAG: [[CBPADDR3:%.+]] = bitcast i8** [[BPADDR3]] to [10 x i32]** 568 // CHECK-DAG: [[CPADDR3:%.+]] = bitcast i8** [[PADDR3]] to [10 x i32]** 569 // CHECK-DAG: store [10 x i32]* [[VAL3:%[^,]+]], [10 x i32]** [[CBPADDR3]] 570 // CHECK-DAG: store [10 x i32]* [[VAL3]], [10 x i32]** [[CPADDR3]] 571 572 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 573 // CHECK-NEXT: br label %[[IFEND:.+]] 574 575 // CHECK: [[IFELSE]] 576 // CHECK: store i32 -1, i32* [[RHV]], align 4 577 // CHECK-NEXT: br label %[[IFEND:.+]] 578 579 // CHECK: [[IFEND]] 580 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 581 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 582 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 583 // CHECK: [[FAIL]] 584 // CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 585 // CHECK-NEXT: br label %[[END]] 586 // CHECK: [[END]] 587 588 // 589 // CHECK: define {{.*}}[[FTEMPLATE]] 590 // 591 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 40 592 // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]] 593 // CHECK: [[IFTHEN]] 594 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 3, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([3 x i[[SZ]]], [3 x i[[SZ]]]* [[SIZET5]], i32 0, i32 0), i32* getelementptr inbounds ([3 x i32], [3 x i32]* [[MAPT5]], i32 0, i32 0)) 595 // CHECK-DAG: [[BPR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP:%.+]], i32 0, i32 0 596 // CHECK-DAG: [[PR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P:%.+]], i32 0, i32 0 597 598 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 0 599 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 0 600 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 601 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 602 // CHECK-DAG: store i[[SZ]] [[VAL0:%[^,]+]], i[[SZ]]* [[CBPADDR0]] 603 // CHECK-DAG: store i[[SZ]] [[VAL0]], i[[SZ]]* [[CPADDR0]] 604 605 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 1 606 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 1 607 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* 608 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* 609 // CHECK-DAG: store i[[SZ]] [[VAL1:%[^,]+]], i[[SZ]]* [[CBPADDR1]] 610 // CHECK-DAG: store i[[SZ]] [[VAL1]], i[[SZ]]* [[CPADDR1]] 611 612 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 2 613 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 2 614 // CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to [10 x i32]** 615 // CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to [10 x i32]** 616 // CHECK-DAG: store [10 x i32]* [[VAL2:%[^,]+]], [10 x i32]** [[CBPADDR2]] 617 // CHECK-DAG: store [10 x i32]* [[VAL2]], [10 x i32]** [[CPADDR2]] 618 619 // CHECK: store i32 [[RET]], i32* [[RHV:%.+]], align 4 620 // CHECK-NEXT: br label %[[IFEND:.+]] 621 622 // CHECK: [[IFELSE]] 623 // CHECK: store i32 -1, i32* [[RHV]], align 4 624 // CHECK-NEXT: br label %[[IFEND:.+]] 625 626 // CHECK: [[IFEND]] 627 // CHECK: [[RET2:%.+]] = load i32, i32* [[RHV]], align 4 628 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0 629 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 630 // CHECK: [[FAIL]] 631 // CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 632 // CHECK-NEXT: br label %[[END]] 633 // CHECK: [[END]] 634 635 636 637 // Check that the offloading functions are emitted and that the arguments are 638 // correct and loaded correctly for the target regions of the callees of bar(). 639 640 // CHECK: define internal void [[HVT7]] 641 // Create local storage for each capture. 642 // CHECK: [[LOCAL_THIS:%.+]] = alloca [[S1]]* 643 // CHECK: [[LOCAL_B:%.+]] = alloca i[[SZ]] 644 // CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]] 645 // CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]] 646 // CHECK: [[LOCAL_C:%.+]] = alloca i16* 647 // CHECK-DAG: store [[S1]]* [[ARG_THIS:%.+]], [[S1]]** [[LOCAL_THIS]] 648 // CHECK-DAG: store i[[SZ]] [[ARG_B:%.+]], i[[SZ]]* [[LOCAL_B]] 649 // CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]] 650 // CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]] 651 // CHECK-DAG: store i16* [[ARG_C:%.+]], i16** [[LOCAL_C]] 652 // Store captures in the context. 653 // CHECK-DAG: [[REF_THIS:%.+]] = load [[S1]]*, [[S1]]** [[LOCAL_THIS]], 654 // CHECK-64-DAG:[[REF_B:%.+]] = bitcast i[[SZ]]* [[LOCAL_B]] to i32* 655 // CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]], 656 // CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]], 657 // CHECK-DAG: [[REF_C:%.+]] = load i16*, i16** [[LOCAL_C]], 658 // Use captures. 659 // CHECK-DAG: getelementptr inbounds [[S1]], [[S1]]* [[REF_THIS]], i32 0, i32 0 660 // CHECK-64-DAG:load i32, i32* [[REF_B]] 661 // CHECK-32-DAG:load i32, i32* [[LOCAL_B]] 662 // CHECK-DAG: getelementptr inbounds i16, i16* [[REF_C]], i[[SZ]] %{{.+}} 663 664 665 // CHECK: define internal void [[HVT6]] 666 // Create local storage for each capture. 667 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] 668 // CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]] 669 // CHECK: [[LOCAL_AAA:%.+]] = alloca i[[SZ]] 670 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* 671 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 672 // CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] 673 // CHECK-DAG: store i[[SZ]] [[ARG_AAA:%.+]], i[[SZ]]* [[LOCAL_AAA]] 674 // CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] 675 // Store captures in the context. 676 // CHECK-64-DAG: [[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 677 // CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* 678 // CHECK-DAG: [[REF_AAA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AAA]] to i8* 679 // CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], 680 // Use captures. 681 // CHECK-64-DAG: load i32, i32* [[REF_A]] 682 // CHECK-DAG: load i16, i16* [[REF_AA]] 683 // CHECK-DAG: load i8, i8* [[REF_AAA]] 684 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 685 // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 686 687 // CHECK: define internal void [[HVT5]] 688 // Create local storage for each capture. 689 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] 690 // CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]] 691 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* 692 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 693 // CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] 694 // CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] 695 // Store captures in the context. 696 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 697 // CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* 698 // CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], 699 // Use captures. 700 // CHECK-64-DAG: load i32, i32* [[REF_A]] 701 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 702 // CHECK-DAG: load i16, i16* [[REF_AA]] 703 // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 704 #endif 705