1 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
2 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -emit-pch -o %t %s
3 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64
4 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -emit-pch -o %t %s
6 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32
7 // expected-no-diagnostics
8 #ifndef HEADER
9 #define HEADER
10 
11 // CHECK-DAG: [[TT:%.+]] = type { i64, i8 }
12 // CHECK-DAG: [[S1:%.+]] = type { double }
13 
14 // We have 8 target regions, but only 7 that actually will generate offloading
15 // code, only 6 will have mapped arguments, and only 4 have all-constant map
16 // sizes.
17 
18 // CHECK-DAG: [[SIZET2:@.+]] = private unnamed_addr constant [1 x i{{32|64}}] [i[[SZ:32|64]] 2]
19 // CHECK-DAG: [[MAPT2:@.+]] = private unnamed_addr constant [1 x i32] [i32 128]
20 // CHECK-DAG: [[SIZET3:@.+]] = private unnamed_addr constant [2 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2]
21 // CHECK-DAG: [[MAPT3:@.+]] = private unnamed_addr constant [2 x i32] [i32 128, i32 128]
22 // CHECK-DAG: [[MAPT4:@.+]] = private unnamed_addr constant [9 x i32] [i32 128, i32 3, i32 128, i32 3, i32 3, i32 128, i32 128, i32 3, i32 3]
23 // CHECK-DAG: [[SIZET5:@.+]] = private unnamed_addr constant [3 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 40]
24 // CHECK-DAG: [[MAPT5:@.+]] = private unnamed_addr constant [3 x i32] [i32 128, i32 128, i32 3]
25 // CHECK-DAG: [[SIZET6:@.+]] = private unnamed_addr constant [4 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 1, i[[SZ]] 40]
26 // CHECK-DAG: [[MAPT6:@.+]] = private unnamed_addr constant [4 x i32] [i32 128, i32 128, i32 128, i32 3]
27 // CHECK-DAG: [[MAPT7:@.+]] = private unnamed_addr constant [5 x i32] [i32 3, i32 128, i32 128, i32 128, i32 3]
28 // CHECK-DAG: @{{.*}} = private constant i8 0
29 // CHECK-DAG: @{{.*}} = private constant i8 0
30 // CHECK-DAG: @{{.*}} = private constant i8 0
31 // CHECK-DAG: @{{.*}} = private constant i8 0
32 // CHECK-DAG: @{{.*}} = private constant i8 0
33 // CHECK-DAG: @{{.*}} = private constant i8 0
34 // CHECK-DAG: @{{.*}} = private constant i8 0
35 
36 template<typename tx, typename ty>
37 struct TT{
38   tx X;
39   ty Y;
40 };
41 
42 // CHECK: define {{.*}}[[FOO:@.+]](
43 int foo(int n) {
44   int a = 0;
45   short aa = 0;
46   float b[10];
47   float bn[n];
48   double c[5][10];
49   double cn[5][n];
50   TT<long long, char> d;
51 
52   // CHECK:       [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i32* null)
53   // CHECK:       store i32 [[RET]], i32* [[RHV:%.+]], align 4
54   // CHECK:       [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
55   // CHECK-NEXT:  [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
56   // CHECK-NEXT:  br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
57   // CHECK:       [[FAIL]]
58   // CHECK:       call void [[HVT0:@.+]]()
59   // CHECK-NEXT:  br label %[[END]]
60   // CHECK:       [[END]]
61   #pragma omp target
62   {
63   }
64 
65   // CHECK:       store i32 0, i32* [[RHV:%.+]], align 4
66   // CHECK:       store i32 -1, i32* [[RHV]], align 4
67   // CHECK:       [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
68   // CHECK-NEXT:  [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
69   // CHECK:       call void [[HVT1:@.+]](i[[SZ]] {{[^,]+}})
70   #pragma omp target if(0)
71   {
72     a += 1;
73   }
74 
75   // CHECK-DAG:   [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 1, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i[[SZ]]* getelementptr inbounds ([1 x i[[SZ]]], [1 x i[[SZ]]]* [[SIZET2]], i32 0, i32 0), i32* getelementptr inbounds ([1 x i32], [1 x i32]* [[MAPT2]], i32 0, i32 0))
76   // CHECK-DAG:   [[BP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPR:%[^,]+]], i32 0, i32 0
77   // CHECK-DAG:   [[P]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PR:%[^,]+]], i32 0, i32 0
78   // CHECK-DAG:   [[BPADDR0:%.+]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPR]], i32 0, i32 [[IDX0:[0-9]+]]
79   // CHECK-DAG:   [[PADDR0:%.+]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PR]], i32 0, i32 [[IDX0]]
80   // CHECK-DAG:   store i8* [[BP0:%[^,]+]], i8** [[BPADDR0]]
81   // CHECK-DAG:   store i8* [[P0:%[^,]+]], i8** [[PADDR0]]
82   // CHECK-DAG:   [[BP0]] = inttoptr i[[SZ]] %{{.+}} to i8*
83   // CHECK-DAG:   [[P0]] = inttoptr i[[SZ]] %{{.+}} to i8*
84 
85   // CHECK:       store i32 [[RET]], i32* [[RHV:%.+]], align 4
86   // CHECK:       [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
87   // CHECK-NEXT:  [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
88   // CHECK-NEXT:  br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
89   // CHECK:       [[FAIL]]
90   // CHECK:       call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}})
91   // CHECK-NEXT:  br label %[[END]]
92   // CHECK:       [[END]]
93   #pragma omp target if(1)
94   {
95     aa += 1;
96   }
97 
98   // CHECK:       [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 10
99   // CHECK:       br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]]
100   // CHECK:       [[IFTHEN]]
101   // CHECK-DAG:   [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([2 x i[[SZ]]], [2 x i[[SZ]]]* [[SIZET3]], i32 0, i32 0), i32* getelementptr inbounds ([2 x i32], [2 x i32]* [[MAPT3]], i32 0, i32 0))
102   // CHECK-DAG:   [[BPR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP:%[^,]+]], i32 0, i32 0
103   // CHECK-DAG:   [[PR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P:%[^,]+]], i32 0, i32 0
104 
105   // CHECK-DAG:   [[BPADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 0
106   // CHECK-DAG:   [[PADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 0
107   // CHECK-DAG:   store i8* [[BP0:%[^,]+]], i8** [[BPADDR0]]
108   // CHECK-DAG:   store i8* [[P0:%[^,]+]], i8** [[PADDR0]]
109   // CHECK-DAG:   [[BP0]] = inttoptr i[[SZ]] %{{.+}} to i8*
110   // CHECK-DAG:   [[P0]] = inttoptr i[[SZ]] %{{.+}} to i8*
111 
112   // CHECK-DAG:   [[BPADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 1
113   // CHECK-DAG:   [[PADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 1
114   // CHECK-DAG:   store i8* [[BP1:%[^,]+]], i8** [[BPADDR1]]
115   // CHECK-DAG:   store i8* [[P1:%[^,]+]], i8** [[PADDR1]]
116   // CHECK-DAG:   [[BP1]] = inttoptr i[[SZ]] %{{.+}} to i8*
117   // CHECK-DAG:   [[P1]] = inttoptr i[[SZ]] %{{.+}} to i8*
118   // CHECK:       store i32 [[RET]], i32* [[RHV:%.+]], align 4
119   // CHECK-NEXT:  br label %[[IFEND:.+]]
120 
121   // CHECK:       [[IFELSE]]
122   // CHECK:       store i32 -1, i32* [[RHV]], align 4
123   // CHECK-NEXT:  br label %[[IFEND:.+]]
124 
125   // CHECK:       [[IFEND]]
126   // CHECK:       [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
127   // CHECK:       [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
128   // CHECK-NEXT:  br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
129   // CHECK:       [[FAIL]]
130   // CHECK:       call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}})
131   // CHECK-NEXT:  br label %[[END]]
132   // CHECK:       [[END]]
133   #pragma omp target if(n>10)
134   {
135     a += 1;
136     aa += 1;
137   }
138 
139   // We capture 3 VLA sizes in this target region
140   // CHECK-64:       [[A_VAL:%.+]] = load i32, i32* %{{.+}},
141   // CHECK-64:       [[A_ADDR:%.+]] = bitcast i[[SZ]]* [[A_CADDR:%.+]] to i32*
142   // CHECK-64:       store i32 [[A_VAL]], i32* [[A_ADDR]],
143   // CHECK-64:       [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]],
144 
145   // CHECK-32:       [[A_VAL:%.+]] = load i32, i32* %{{.+}},
146   // CHECK-32:       store i32 [[A_VAL]], i32* [[A_CADDR:%.+]],
147   // CHECK-32:       [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]],
148 
149   // CHECK:       [[BNSIZE:%.+]] = mul nuw i[[SZ]] [[VLA0:%.+]], 4
150   // CHECK:       [[CNELEMSIZE2:%.+]] = mul nuw i[[SZ]] 5, [[VLA1:%.+]]
151   // CHECK:       [[CNSIZE:%.+]] = mul nuw i[[SZ]] [[CNELEMSIZE2]], 8
152 
153   // CHECK:       [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 20
154   // CHECK:       br i1 [[IF]], label %[[TRY:[^,]+]], label %[[FAIL:[^,]+]]
155   // CHECK:       [[TRY]]
156   // CHECK-DAG:   [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 9, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SR:%[^,]+]], i32* getelementptr inbounds ([9 x i32], [9 x i32]* [[MAPT4]], i32 0, i32 0))
157   // CHECK-DAG:   [[BPR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP:%[^,]+]], i32 0, i32 0
158   // CHECK-DAG:   [[PR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P:%[^,]+]], i32 0, i32 0
159   // CHECK-DAG:   [[SR]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S:%[^,]+]], i32 0, i32 0
160 
161   // CHECK-DAG:   [[SADDR0:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX0:[0-9]+]]
162   // CHECK-DAG:   [[BPADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX0]]
163   // CHECK-DAG:   [[PADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX0]]
164   // CHECK-DAG:   [[SADDR1:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX1:[0-9]+]]
165   // CHECK-DAG:   [[BPADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX1]]
166   // CHECK-DAG:   [[PADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX1]]
167   // CHECK-DAG:   [[SADDR2:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX2:[0-9]+]]
168   // CHECK-DAG:   [[BPADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX2]]
169   // CHECK-DAG:   [[PADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX2]]
170   // CHECK-DAG:   [[SADDR3:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX3:[0-9]+]]
171   // CHECK-DAG:   [[BPADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX3]]
172   // CHECK-DAG:   [[PADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX3]]
173   // CHECK-DAG:   [[SADDR4:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX4:[0-9]+]]
174   // CHECK-DAG:   [[BPADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX4]]
175   // CHECK-DAG:   [[PADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX4]]
176   // CHECK-DAG:   [[SADDR5:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX5:[0-9]+]]
177   // CHECK-DAG:   [[BPADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX5]]
178   // CHECK-DAG:   [[PADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX5]]
179   // CHECK-DAG:   [[SADDR6:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX6:[0-9]+]]
180   // CHECK-DAG:   [[BPADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX6]]
181   // CHECK-DAG:   [[PADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX6]]
182   // CHECK-DAG:   [[SADDR7:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX7:[0-9]+]]
183   // CHECK-DAG:   [[BPADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX7]]
184   // CHECK-DAG:   [[PADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX7]]
185   // CHECK-DAG:   [[SADDR8:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX8:[0-9]+]]
186   // CHECK-DAG:   [[BPADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX8]]
187   // CHECK-DAG:   [[PADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX8]]
188 
189   // The names below are not necessarily consistent with the names used for the
190   // addresses above as some are repeated.
191   // CHECK-DAG:   [[BP0:%[^,]+]] = inttoptr i[[SZ]] [[VLA0]] to i8*
192   // CHECK-DAG:   [[P0:%[^,]+]] = inttoptr i[[SZ]] [[VLA0]] to i8*
193   // CHECK-DAG:   store i8* [[BP0]], i8** {{%[^,]+}}
194   // CHECK-DAG:   store i8* [[P0]], i8** {{%[^,]+}}
195   // CHECK-DAG:   store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}}
196 
197   // CHECK-DAG:   [[BP1:%[^,]+]] = inttoptr i[[SZ]] [[VLA1]] to i8*
198   // CHECK-DAG:   [[P1:%[^,]+]] = inttoptr i[[SZ]] [[VLA1]] to i8*
199   // CHECK-DAG:   store i8* [[BP1]], i8** {{%[^,]+}}
200   // CHECK-DAG:   store i8* [[P1]], i8** {{%[^,]+}}
201   // CHECK-DAG:   store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}}
202 
203   // CHECK-DAG:   store i8* inttoptr (i[[SZ]] 5 to i8*), i8** {{%[^,]+}}
204   // CHECK-DAG:   store i8* inttoptr (i[[SZ]] 5 to i8*), i8** {{%[^,]+}}
205   // CHECK-DAG:   store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}}
206 
207   // CHECK-DAG:   [[BP3:%[^,]+]] = inttoptr i[[SZ]] [[A_CVAL]] to i8*
208   // CHECK-DAG:   [[P3:%[^,]+]] = inttoptr i[[SZ]] [[A_CVAL]] to i8*
209   // CHECK-DAG:   store i8* [[BP3]], i8** {{%[^,]+}}
210   // CHECK-DAG:   store i8* [[P3]], i8** {{%[^,]+}}
211   // CHECK-DAG:   store i[[SZ]] 4, i[[SZ]]* {{%[^,]+}}
212 
213   // CHECK-DAG:   [[BP4:%[^,]+]] = bitcast [10 x float]* %{{.+}} to i8*
214   // CHECK-DAG:   [[P4:%[^,]+]] = bitcast [10 x float]* %{{.+}} to i8*
215   // CHECK-DAG:   store i8* [[BP4]], i8** {{%[^,]+}}
216   // CHECK-DAG:   store i8* [[P4]], i8** {{%[^,]+}}
217   // CHECK-DAG:   store i[[SZ]] 40, i[[SZ]]* {{%[^,]+}}
218 
219   // CHECK-DAG:   [[BP5:%[^,]+]] = bitcast float* %{{.+}} to i8*
220   // CHECK-DAG:   [[P5:%[^,]+]] = bitcast float* %{{.+}} to i8*
221   // CHECK-DAG:   store i8* [[BP5]], i8** {{%[^,]+}}
222   // CHECK-DAG:   store i8* [[P5]], i8** {{%[^,]+}}
223   // CHECK-DAG:   store i[[SZ]] [[BNSIZE]], i[[SZ]]* {{%[^,]+}}
224 
225   // CHECK-DAG:   [[BP6:%[^,]+]] = bitcast [5 x [10 x double]]* %{{.+}} to i8*
226   // CHECK-DAG:   [[P6:%[^,]+]] = bitcast [5 x [10 x double]]* %{{.+}} to i8*
227   // CHECK-DAG:   store i8* [[BP6]], i8** {{%[^,]+}}
228   // CHECK-DAG:   store i8* [[P6]], i8** {{%[^,]+}}
229   // CHECK-DAG:   store i[[SZ]] 400, i[[SZ]]* {{%[^,]+}}
230 
231   // CHECK-DAG:   [[BP7:%[^,]+]] = bitcast double* %{{.+}} to i8*
232   // CHECK-DAG:   [[P7:%[^,]+]] = bitcast double* %{{.+}} to i8*
233   // CHECK-DAG:   store i8* [[BP7]], i8** {{%[^,]+}}
234   // CHECK-DAG:   store i8* [[P7]], i8** {{%[^,]+}}
235   // CHECK-DAG:   store i[[SZ]] [[CNSIZE]], i[[SZ]]* {{%[^,]+}}
236 
237   // CHECK-DAG:   [[BP8:%[^,]+]] = bitcast [[TT]]* %{{.+}} to i8*
238   // CHECK-DAG:   [[P8:%[^,]+]] = bitcast [[TT]]* %{{.+}} to i8*
239   // CHECK-DAG:   store i8* [[BP8]], i8** {{%[^,]+}}
240   // CHECK-DAG:   store i8* [[P8]], i8** {{%[^,]+}}
241   // CHECK-DAG:   store i[[SZ]] {{12|16}}, i[[SZ]]* {{%[^,]+}}
242 
243   // CHECK:       store i32 [[RET]], i32* [[RHV:%.+]], align 4
244   // CHECK:       [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
245   // CHECK-NEXT:  [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
246   // CHECK-NEXT:  br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
247 
248   // CHECK:       [[FAIL]]
249   // CHECK:       call void [[HVT4:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
250   // CHECK-NEXT:  br label %[[END]]
251   // CHECK:       [[END]]
252   #pragma omp target if(n>20)
253   {
254     a += 1;
255     b[2] += 1.0;
256     bn[3] += 1.0;
257     c[1][2] += 1.0;
258     cn[1][3] += 1.0;
259     d.X += 1;
260     d.Y += 1;
261   }
262 
263   return a;
264 }
265 
266 // Check that the offloading functions are emitted and that the arguments are
267 // correct and loaded correctly for the target regions in foo().
268 
269 // CHECK:       define internal void [[HVT0]]()
270 
271 // CHECK:       define internal void [[HVT1]](i[[SZ]] %{{.+}})
272 // Create stack storage and store argument in there.
273 // CHECK:       [[AA_ADDR:%.+]] = alloca i[[SZ]], align
274 // CHECK:       store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align
275 // CHECK-64:    [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i32*
276 // CHECK-64:    load i32, i32* [[AA_CADDR]], align
277 // CHECK-32:    load i32, i32* [[AA_ADDR]], align
278 
279 // CHECK:       define internal void [[HVT2]](i[[SZ]] %{{.+}})
280 // Create stack storage and store argument in there.
281 // CHECK:       [[AA_ADDR:%.+]] = alloca i[[SZ]], align
282 // CHECK:       store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align
283 // CHECK:       [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16*
284 // CHECK:       load i16, i16* [[AA_CADDR]], align
285 
286 // CHECK:       define internal void [[HVT3]]
287 // Create stack storage and store argument in there.
288 // CHECK:       [[A_ADDR:%.+]] = alloca i[[SZ]], align
289 // CHECK:       [[AA_ADDR:%.+]] = alloca i[[SZ]], align
290 // CHECK-DAG:   store i[[SZ]] %{{.+}}, i[[SZ]]* [[A_ADDR]], align
291 // CHECK-DAG:   store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align
292 // CHECK-64-DAG:[[A_CADDR:%.+]] = bitcast i[[SZ]]* [[A_ADDR]] to i32*
293 // CHECK-DAG:   [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16*
294 // CHECK-64-DAG:load i32, i32* [[A_CADDR]], align
295 // CHECK-32-DAG:load i32, i32* [[A_ADDR]], align
296 // CHECK-DAG:   load i16, i16* [[AA_CADDR]], align
297 
298 // CHECK:       define internal void [[HVT4]]
299 // Create local storage for each capture.
300 // CHECK:       [[LOCAL_A:%.+]] = alloca i[[SZ]]
301 // CHECK:       [[LOCAL_B:%.+]] = alloca [10 x float]*
302 // CHECK:       [[LOCAL_VLA1:%.+]] = alloca i[[SZ]]
303 // CHECK:       [[LOCAL_BN:%.+]] = alloca float*
304 // CHECK:       [[LOCAL_C:%.+]] = alloca [5 x [10 x double]]*
305 // CHECK:       [[LOCAL_VLA2:%.+]] = alloca i[[SZ]]
306 // CHECK:       [[LOCAL_VLA3:%.+]] = alloca i[[SZ]]
307 // CHECK:       [[LOCAL_CN:%.+]] = alloca double*
308 // CHECK:       [[LOCAL_D:%.+]] = alloca [[TT]]*
309 // CHECK-DAG:   store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]]
310 // CHECK-DAG:   store [10 x float]* [[ARG_B:%.+]], [10 x float]** [[LOCAL_B]]
311 // CHECK-DAG:   store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]]
312 // CHECK-DAG:   store float* [[ARG_BN:%.+]], float** [[LOCAL_BN]]
313 // CHECK-DAG:   store [5 x [10 x double]]* [[ARG_C:%.+]], [5 x [10 x double]]** [[LOCAL_C]]
314 // CHECK-DAG:   store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]]
315 // CHECK-DAG:   store i[[SZ]] [[ARG_VLA3:%.+]], i[[SZ]]* [[LOCAL_VLA3]]
316 // CHECK-DAG:   store double* [[ARG_CN:%.+]], double** [[LOCAL_CN]]
317 // CHECK-DAG:   store [[TT]]* [[ARG_D:%.+]], [[TT]]** [[LOCAL_D]]
318 
319 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32*
320 // CHECK-DAG:   [[REF_B:%.+]] = load [10 x float]*, [10 x float]** [[LOCAL_B]],
321 // CHECK-DAG:   [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]],
322 // CHECK-DAG:   [[REF_BN:%.+]] = load float*, float** [[LOCAL_BN]],
323 // CHECK-DAG:   [[REF_C:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[LOCAL_C]],
324 // CHECK-DAG:   [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]],
325 // CHECK-DAG:   [[VAL_VLA3:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA3]],
326 // CHECK-DAG:   [[REF_CN:%.+]] = load double*, double** [[LOCAL_CN]],
327 // CHECK-DAG:   [[REF_D:%.+]] = load [[TT]]*, [[TT]]** [[LOCAL_D]],
328 
329 // Use captures.
330 // CHECK-64-DAG:   load i32, i32* [[REF_A]]
331 // CHECK-32-DAG:   load i32, i32* [[LOCAL_A]]
332 // CHECK-DAG:   getelementptr inbounds [10 x float], [10 x float]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2
333 // CHECK-DAG:   getelementptr inbounds float, float* [[REF_BN]], i[[SZ]] 3
334 // CHECK-DAG:   getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[REF_C]], i[[SZ]] 0, i[[SZ]] 1
335 // CHECK-DAG:   getelementptr inbounds double, double* [[REF_CN]], i[[SZ]] %{{.+}}
336 // CHECK-DAG:   getelementptr inbounds [[TT]], [[TT]]* [[REF_D]], i32 0, i32 0
337 
338 template<typename tx>
339 tx ftemplate(int n) {
340   tx a = 0;
341   short aa = 0;
342   tx b[10];
343 
344   #pragma omp target if(n>40)
345   {
346     a += 1;
347     aa += 1;
348     b[2] += 1;
349   }
350 
351   return a;
352 }
353 
354 static
355 int fstatic(int n) {
356   int a = 0;
357   short aa = 0;
358   char aaa = 0;
359   int b[10];
360 
361   #pragma omp target if(n>50)
362   {
363     a += 1;
364     aa += 1;
365     aaa += 1;
366     b[2] += 1;
367   }
368 
369   return a;
370 }
371 
372 struct S1 {
373   double a;
374 
375   int r1(int n){
376     int b = n+1;
377     short int c[2][n];
378 
379     #pragma omp target if(n>60)
380     {
381       this->a = (double)b + 1.5;
382       c[1][1] = ++a;
383     }
384 
385     return c[1][1] + (int)b;
386   }
387 };
388 
389 // CHECK: define {{.*}}@{{.*}}bar{{.*}}
390 int bar(int n){
391   int a = 0;
392 
393   // CHECK: call {{.*}}i32 [[FOO]](i32 {{.*}})
394   a += foo(n);
395 
396   S1 S;
397   // CHECK: call {{.*}}i32 [[FS1:@.+]]([[S1]]* {{.*}}, i32 {{.*}})
398   a += S.r1(n);
399 
400   // CHECK: call {{.*}}i32 [[FSTATIC:@.+]](i32 {{.*}})
401   a += fstatic(n);
402 
403   // CHECK: call {{.*}}i32 [[FTEMPLATE:@.+]](i32 {{.*}})
404   a += ftemplate<int>(n);
405 
406   return a;
407 }
408 
409 //
410 // CHECK: define {{.*}}[[FS1]]
411 //
412 // CHECK:          i8* @llvm.stacksave()
413 // CHECK-64:       [[B_ADDR:%.+]] = bitcast i[[SZ]]* [[B_CADDR:%.+]] to i32*
414 // CHECK-64:       store i32 %{{.+}}, i32* [[B_ADDR]],
415 // CHECK-64:       [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]],
416 
417 // CHECK-32:       store i32 %{{.+}}, i32* [[B_ADDR:%.+]],
418 // CHECK-32:       [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]],
419 
420 // We capture 2 VLA sizes in this target region
421 // CHECK:       [[CELEMSIZE2:%.+]] = mul nuw i[[SZ]] 2, [[VLA0:%.+]]
422 // CHECK:       [[CSIZE:%.+]] = mul nuw i[[SZ]] [[CELEMSIZE2]], 2
423 
424 // CHECK:       [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 60
425 // CHECK:       br i1 [[IF]], label %[[TRY:[^,]+]], label %[[FAIL:[^,]+]]
426 // CHECK:       [[TRY]]
427 // CHECK-DAG:   [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 5, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SR:%[^,]+]], i32* getelementptr inbounds ([5 x i32], [5 x i32]* [[MAPT7]], i32 0, i32 0))
428 // CHECK-DAG:   [[BPR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP:%.+]], i32 0, i32 0
429 // CHECK-DAG:   [[PR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P:%.+]], i32 0, i32 0
430 // CHECK-DAG:   [[SR]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S:%.+]], i32 0, i32 0
431 // CHECK-DAG:   [[SADDR0:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 [[IDX0:[0-9]+]]
432 // CHECK-DAG:   [[BPADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 [[IDX0]]
433 // CHECK-DAG:   [[PADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 [[IDX0]]
434 // CHECK-DAG:   [[SADDR1:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 [[IDX1:[0-9]+]]
435 // CHECK-DAG:   [[BPADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 [[IDX1]]
436 // CHECK-DAG:   [[PADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 [[IDX1]]
437 // CHECK-DAG:   [[SADDR2:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 [[IDX2:[0-9]+]]
438 // CHECK-DAG:   [[BPADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 [[IDX2]]
439 // CHECK-DAG:   [[PADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 [[IDX2]]
440 // CHECK-DAG:   [[SADDR3:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 [[IDX3:[0-9]+]]
441 // CHECK-DAG:   [[BPADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 [[IDX3]]
442 // CHECK-DAG:   [[PADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 [[IDX3]]
443 
444 // The names below are not necessarily consistent with the names used for the
445 // addresses above as some are repeated.
446 // CHECK-DAG:   [[BP0:%[^,]+]] = inttoptr i[[SZ]] [[VLA0]] to i8*
447 // CHECK-DAG:   [[P0:%[^,]+]] = inttoptr i[[SZ]] [[VLA0]] to i8*
448 // CHECK-DAG:   store i8* [[BP0]], i8** {{%[^,]+}}
449 // CHECK-DAG:   store i8* [[P0]], i8** {{%[^,]+}}
450 // CHECK-DAG:   store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}}
451 
452 // CHECK-DAG:   store i8* inttoptr (i[[SZ]] 2 to i8*), i8** {{%[^,]+}}
453 // CHECK-DAG:   store i8* inttoptr (i[[SZ]] 2 to i8*), i8** {{%[^,]+}}
454 // CHECK-DAG:   store i[[SZ]] {{4|8}}, i[[SZ]]* {{%[^,]+}}
455 
456 // CHECK-DAG:   [[BP2:%[^,]+]] = inttoptr i[[SZ]] [[B_CVAL]] to i8*
457 // CHECK-DAG:   [[P2:%[^,]+]] = inttoptr i[[SZ]] [[B_CVAL]] to i8*
458 // CHECK-DAG:   store i8* [[BP2]], i8** {{%[^,]+}}
459 // CHECK-DAG:   store i8* [[P2]], i8** {{%[^,]+}}
460 // CHECK-DAG:   store i[[SZ]] 4, i[[SZ]]* {{%[^,]+}}
461 
462 // CHECK-DAG:   [[BP3:%[^,]+]] = bitcast [[S1]]* %{{.+}} to i8*
463 // CHECK-DAG:   [[P3:%[^,]+]] = bitcast [[S1]]* %{{.+}} to i8*
464 // CHECK-DAG:   store i8* [[BP3]], i8** {{%[^,]+}}
465 // CHECK-DAG:   store i8* [[P3]], i8** {{%[^,]+}}
466 // CHECK-DAG:   store i[[SZ]] 8, i[[SZ]]* {{%[^,]+}}
467 
468 // CHECK-DAG:   [[BP4:%[^,]+]] = bitcast i16* %{{.+}} to i8*
469 // CHECK-DAG:   [[P4:%[^,]+]] = bitcast i16* %{{.+}} to i8*
470 // CHECK-DAG:   store i8* [[BP4]], i8** {{%[^,]+}}
471 // CHECK-DAG:   store i8* [[P4]], i8** {{%[^,]+}}
472 // CHECK-DAG:   store i[[SZ]] [[CSIZE]], i[[SZ]]* {{%[^,]+}}
473 
474 // CHECK:       store i32 [[RET]], i32* [[RHV:%.+]], align 4
475 // CHECK:       [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
476 // CHECK-NEXT:  [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
477 // CHECK-NEXT:  br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]]
478 
479 // CHECK:       [[FAIL]]
480 // CHECK:       call void [[HVT7:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
481 // CHECK-NEXT:  br label %[[END]]
482 // CHECK:       [[END]]
483 
484 //
485 // CHECK: define {{.*}}[[FSTATIC]]
486 //
487 // CHECK:       [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 50
488 // CHECK:       br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]]
489 // CHECK:       [[IFTHEN]]
490 // CHECK-DAG:   [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 4, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([4 x i[[SZ]]], [4 x i[[SZ]]]* [[SIZET6]], i32 0, i32 0), i32* getelementptr inbounds ([4 x i32], [4 x i32]* [[MAPT6]], i32 0, i32 0))
491 // CHECK-DAG:   [[BPR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP:%.+]], i32 0, i32 0
492 // CHECK-DAG:   [[PR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P:%.+]], i32 0, i32 0
493 
494 // CHECK-DAG:   [[BPADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 0
495 // CHECK-DAG:   [[PADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 0
496 // CHECK-DAG:   store i8* [[BP0:%[^,]+]], i8** [[BPADDR0]]
497 // CHECK-DAG:   store i8* [[P0:%[^,]+]], i8** [[PADDR0]]
498 // CHECK-DAG:   [[BP0]] = inttoptr i[[SZ]] [[VAL0:%.+]] to i8*
499 // CHECK-DAG:   [[P0]] = inttoptr i[[SZ]] [[VAL0]] to i8*
500 
501 // CHECK-DAG:   [[BPADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 1
502 // CHECK-DAG:   [[PADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 1
503 // CHECK-DAG:   store i8* [[BP1:%[^,]+]], i8** [[BPADDR1]]
504 // CHECK-DAG:   store i8* [[P1:%[^,]+]], i8** [[PADDR1]]
505 // CHECK-DAG:   [[BP1]] = inttoptr i[[SZ]] [[VAL1:%.+]] to i8*
506 // CHECK-DAG:   [[P1]] = inttoptr i[[SZ]] [[VAL1]] to i8*
507 
508 // CHECK-DAG:   [[BPADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 2
509 // CHECK-DAG:   [[PADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 2
510 // CHECK-DAG:   store i8* [[BP2:%[^,]+]], i8** [[BPADDR2]]
511 // CHECK-DAG:   store i8* [[P2:%[^,]+]], i8** [[PADDR2]]
512 
513 // CHECK-DAG:   [[BPADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 3
514 // CHECK-DAG:   [[PADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 3
515 // CHECK-DAG:   store i8* [[BP3:%[^,]+]], i8** [[BPADDR3]]
516 // CHECK-DAG:   store i8* [[P3:%[^,]+]], i8** [[PADDR3]]
517 // CHECK-DAG:   [[BP3]] = bitcast [10 x i32]* %{{.+}} to i8*
518 // CHECK-DAG:   [[P3]] = bitcast [10 x i32]* %{{.+}} to i8*
519 
520 // CHECK:       store i32 [[RET]], i32* [[RHV:%.+]], align 4
521 // CHECK-NEXT:  br label %[[IFEND:.+]]
522 
523 // CHECK:       [[IFELSE]]
524 // CHECK:       store i32 -1, i32* [[RHV]], align 4
525 // CHECK-NEXT:  br label %[[IFEND:.+]]
526 
527 // CHECK:       [[IFEND]]
528 // CHECK:       [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
529 // CHECK:       [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
530 // CHECK-NEXT:  br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
531 // CHECK:       [[FAIL]]
532 // CHECK:       call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}})
533 // CHECK-NEXT:  br label %[[END]]
534 // CHECK:       [[END]]
535 
536 //
537 // CHECK: define {{.*}}[[FTEMPLATE]]
538 //
539 // CHECK:       [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 40
540 // CHECK:       br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]]
541 // CHECK:       [[IFTHEN]]
542 // CHECK-DAG:   [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 3, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([3 x i[[SZ]]], [3 x i[[SZ]]]* [[SIZET5]], i32 0, i32 0), i32* getelementptr inbounds ([3 x i32], [3 x i32]* [[MAPT5]], i32 0, i32 0))
543 // CHECK-DAG:   [[BPR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP:%.+]], i32 0, i32 0
544 // CHECK-DAG:   [[PR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P:%.+]], i32 0, i32 0
545 
546 // CHECK-DAG:   [[BPADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 0
547 // CHECK-DAG:   [[PADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 0
548 // CHECK-DAG:   store i8* [[BP0:%[^,]+]], i8** [[BPADDR0]]
549 // CHECK-DAG:   store i8* [[P0:%[^,]+]], i8** [[PADDR0]]
550 // CHECK-DAG:   [[BP0]] = inttoptr i[[SZ]] [[VAL0:%.+]] to i8*
551 // CHECK-DAG:   [[P0]] = inttoptr i[[SZ]] [[VAL0]] to i8*
552 
553 // CHECK-DAG:   [[BPADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 1
554 // CHECK-DAG:   [[PADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 1
555 // CHECK-DAG:   store i8* [[BP1:%[^,]+]], i8** [[BPADDR1]]
556 // CHECK-DAG:   store i8* [[P1:%[^,]+]], i8** [[PADDR1]]
557 // CHECK-DAG:   [[BP1]] = inttoptr i[[SZ]] [[VAL1:%.+]] to i8*
558 // CHECK-DAG:   [[P1]] = inttoptr i[[SZ]] [[VAL1]] to i8*
559 
560 // CHECK-DAG:   [[BPADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 2
561 // CHECK-DAG:   [[PADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 2
562 // CHECK-DAG:   store i8* [[BP2:%[^,]+]], i8** [[BPADDR2]]
563 // CHECK-DAG:   store i8* [[P2:%[^,]+]], i8** [[PADDR2]]
564 // CHECK-DAG:   [[BP2]] = bitcast [10 x i32]* %{{.+}} to i8*
565 // CHECK-DAG:   [[P2]] = bitcast [10 x i32]* %{{.+}} to i8*
566 
567 // CHECK:       store i32 [[RET]], i32* [[RHV:%.+]], align 4
568 // CHECK-NEXT:  br label %[[IFEND:.+]]
569 
570 // CHECK:       [[IFELSE]]
571 // CHECK:       store i32 -1, i32* [[RHV]], align 4
572 // CHECK-NEXT:  br label %[[IFEND:.+]]
573 
574 // CHECK:       [[IFEND]]
575 // CHECK:       [[RET2:%.+]] = load i32, i32* [[RHV]], align 4
576 // CHECK:       [[ERROR:%.+]] = icmp ne i32 [[RET2]], 0
577 // CHECK-NEXT:  br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]]
578 // CHECK:       [[FAIL]]
579 // CHECK:       call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}})
580 // CHECK-NEXT:  br label %[[END]]
581 // CHECK:       [[END]]
582 
583 
584 
585 // Check that the offloading functions are emitted and that the arguments are
586 // correct and loaded correctly for the target regions of the callees of bar().
587 
588 // CHECK:       define internal void [[HVT7]]
589 // Create local storage for each capture.
590 // CHECK:       [[LOCAL_THIS:%.+]] = alloca [[S1]]*
591 // CHECK:       [[LOCAL_B:%.+]] = alloca i[[SZ]]
592 // CHECK:       [[LOCAL_VLA1:%.+]] = alloca i[[SZ]]
593 // CHECK:       [[LOCAL_VLA2:%.+]] = alloca i[[SZ]]
594 // CHECK:       [[LOCAL_C:%.+]] = alloca i16*
595 // CHECK-DAG:   store [[S1]]* [[ARG_THIS:%.+]], [[S1]]** [[LOCAL_THIS]]
596 // CHECK-DAG:   store i[[SZ]] [[ARG_B:%.+]], i[[SZ]]* [[LOCAL_B]]
597 // CHECK-DAG:   store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]]
598 // CHECK-DAG:   store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]]
599 // CHECK-DAG:   store i16* [[ARG_C:%.+]], i16** [[LOCAL_C]]
600 // Store captures in the context.
601 // CHECK-DAG:   [[REF_THIS:%.+]] = load [[S1]]*, [[S1]]** [[LOCAL_THIS]],
602 // CHECK-64-DAG:[[REF_B:%.+]] = bitcast i[[SZ]]* [[LOCAL_B]] to i32*
603 // CHECK-DAG:   [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]],
604 // CHECK-DAG:   [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]],
605 // CHECK-DAG:   [[REF_C:%.+]] = load i16*, i16** [[LOCAL_C]],
606 // Use captures.
607 // CHECK-DAG:   getelementptr inbounds [[S1]], [[S1]]* [[REF_THIS]], i32 0, i32 0
608 // CHECK-64-DAG:load i32, i32* [[REF_B]]
609 // CHECK-32-DAG:load i32, i32* [[LOCAL_B]]
610 // CHECK-DAG:   getelementptr inbounds i16, i16* [[REF_C]], i[[SZ]] %{{.+}}
611 
612 
613 // CHECK:       define internal void [[HVT6]]
614 // Create local storage for each capture.
615 // CHECK:       [[LOCAL_A:%.+]] = alloca i[[SZ]]
616 // CHECK:       [[LOCAL_AA:%.+]] = alloca i[[SZ]]
617 // CHECK:       [[LOCAL_AAA:%.+]] = alloca i[[SZ]]
618 // CHECK:       [[LOCAL_B:%.+]] = alloca [10 x i32]*
619 // CHECK-DAG:   store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]]
620 // CHECK-DAG:   store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]]
621 // CHECK-DAG:   store i[[SZ]] [[ARG_AAA:%.+]], i[[SZ]]* [[LOCAL_AAA]]
622 // CHECK-DAG:   store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]]
623 // Store captures in the context.
624 // CHECK-64-DAG:   [[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32*
625 // CHECK-DAG:      [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16*
626 // CHECK-DAG:      [[REF_AAA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AAA]] to i8*
627 // CHECK-DAG:      [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]],
628 // Use captures.
629 // CHECK-64-DAG:   load i32, i32* [[REF_A]]
630 // CHECK-DAG:      load i16, i16* [[REF_AA]]
631 // CHECK-DAG:      load i8, i8* [[REF_AAA]]
632 // CHECK-32-DAG:   load i32, i32* [[LOCAL_A]]
633 // CHECK-DAG:      getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2
634 
635 // CHECK:       define internal void [[HVT5]]
636 // Create local storage for each capture.
637 // CHECK:       [[LOCAL_A:%.+]] = alloca i[[SZ]]
638 // CHECK:       [[LOCAL_AA:%.+]] = alloca i[[SZ]]
639 // CHECK:       [[LOCAL_B:%.+]] = alloca [10 x i32]*
640 // CHECK-DAG:   store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]]
641 // CHECK-DAG:   store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]]
642 // CHECK-DAG:   store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]]
643 // Store captures in the context.
644 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32*
645 // CHECK-DAG:   [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16*
646 // CHECK-DAG:   [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]],
647 // Use captures.
648 // CHECK-64-DAG:   load i32, i32* [[REF_A]]
649 // CHECK-32-DAG:   load i32, i32* [[LOCAL_A]]
650 // CHECK-DAG:   load i16, i16* [[REF_AA]]
651 // CHECK-DAG:   getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2
652 #endif
653