1 // Test host codegen. 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 3 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s 4 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-64 5 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 6 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s 7 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix CHECK --check-prefix CHECK-32 8 9 // Test target codegen - host bc file has to be created first. 10 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc 11 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 12 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s 13 // RUN: %clang_cc1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-64 14 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc 15 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 16 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s 17 // RUN: %clang_cc1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix TCHECK --check-prefix TCHECK-32 18 19 // expected-no-diagnostics 20 #ifndef HEADER 21 #define HEADER 22 23 // CHECK-DAG: [[TT:%.+]] = type { i64, i8 } 24 // CHECK-DAG: [[S1:%.+]] = type { double } 25 // CHECK-DAG: [[ENTTY:%.+]] = type { i8*, i8*, i[[SZ:32|64]], i32, i32 } 26 // CHECK-DAG: [[DEVTY:%.+]] = type { i8*, i8*, [[ENTTY]]*, [[ENTTY]]* } 27 // CHECK-DAG: [[DSCTY:%.+]] = type { i32, [[DEVTY]]*, [[ENTTY]]*, [[ENTTY]]* } 28 29 // TCHECK: [[ENTTY:%.+]] = type { i8*, i8*, i{{32|64}}, i32, i32 } 30 31 // CHECK-DAG: $[[REGFN:\.omp_offloading\..+]] = comdat 32 33 // We have 8 target regions, but only 7 that actually will generate offloading 34 // code, only 6 will have mapped arguments, and only 4 have all-constant map 35 // sizes. 36 37 // CHECK-DAG: [[SIZET:@.+]] = private unnamed_addr constant [2 x i[[SZ]]] [i[[SZ]] 0, i[[SZ]] 4] 38 // CHECK-DAG: [[MAPT:@.+]] = private unnamed_addr constant [2 x i32] [i32 32, i32 288] 39 // CHECK-DAG: [[SIZET2:@.+]] = private unnamed_addr constant [1 x i{{32|64}}] [i[[SZ]] 2] 40 // CHECK-DAG: [[MAPT2:@.+]] = private unnamed_addr constant [1 x i32] [i32 288] 41 // CHECK-DAG: [[SIZET3:@.+]] = private unnamed_addr constant [2 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2] 42 // CHECK-DAG: [[MAPT3:@.+]] = private unnamed_addr constant [2 x i32] [i32 288, i32 288] 43 // CHECK-DAG: [[MAPT4:@.+]] = private unnamed_addr constant [9 x i32] [i32 288, i32 547, i32 288, i32 547, i32 547, i32 288, i32 288, i32 547, i32 547] 44 // CHECK-DAG: [[SIZET5:@.+]] = private unnamed_addr constant [3 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 40] 45 // CHECK-DAG: [[MAPT5:@.+]] = private unnamed_addr constant [3 x i32] [i32 288, i32 288, i32 547] 46 // CHECK-DAG: [[SIZET6:@.+]] = private unnamed_addr constant [4 x i[[SZ]]] [i[[SZ]] 4, i[[SZ]] 2, i[[SZ]] 1, i[[SZ]] 40] 47 // CHECK-DAG: [[MAPT6:@.+]] = private unnamed_addr constant [4 x i32] [i32 288, i32 288, i32 288, i32 547] 48 // CHECK-DAG: [[MAPT7:@.+]] = private unnamed_addr constant [5 x i32] [i32 547, i32 288, i32 288, i32 288, i32 547] 49 // CHECK-DAG: @{{.*}} = private constant i8 0 50 // CHECK-DAG: @{{.*}} = private constant i8 0 51 // CHECK-DAG: @{{.*}} = private constant i8 0 52 // CHECK-DAG: @{{.*}} = private constant i8 0 53 // CHECK-DAG: @{{.*}} = private constant i8 0 54 // CHECK-DAG: @{{.*}} = private constant i8 0 55 // CHECK-DAG: @{{.*}} = private constant i8 0 56 57 // TCHECK: @{{.+}} = constant [[ENTTY]] 58 // TCHECK: @{{.+}} = constant [[ENTTY]] 59 // TCHECK: @{{.+}} = constant [[ENTTY]] 60 // TCHECK: @{{.+}} = constant [[ENTTY]] 61 // TCHECK: @{{.+}} = constant [[ENTTY]] 62 // TCHECK: @{{.+}} = constant [[ENTTY]] 63 // TCHECK: @{{.+}} = constant [[ENTTY]] 64 // TCHECK: @{{.+}} = {{.*}}constant [[ENTTY]] 65 // TCHECK-NOT: @{{.+}} = constant [[ENTTY]] 66 67 // Check if offloading descriptor is created. 68 // CHECK: [[ENTBEGIN:@.+]] = external constant [[ENTTY]] 69 // CHECK: [[ENTEND:@.+]] = external constant [[ENTTY]] 70 // CHECK: [[DEVBEGIN:@.+]] = external constant i8 71 // CHECK: [[DEVEND:@.+]] = external constant i8 72 // CHECK: [[IMAGES:@.+]] = internal unnamed_addr constant [1 x [[DEVTY]]] [{{.+}} { i8* [[DEVBEGIN]], i8* [[DEVEND]], [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }], comdat($[[REGFN]]) 73 // CHECK: [[DESC:@.+]] = internal constant [[DSCTY]] { i32 1, [[DEVTY]]* getelementptr inbounds ([1 x [[DEVTY]]], [1 x [[DEVTY]]]* [[IMAGES]], i32 0, i32 0), [[ENTTY]]* [[ENTBEGIN]], [[ENTTY]]* [[ENTEND]] }, comdat($[[REGFN]]) 74 75 // Check target registration is registered as a Ctor. 76 // CHECK: appending global [1 x { i32, void ()*, i8* }] [{ i32, void ()*, i8* } { i32 0, void ()* bitcast (void (i8*)* @[[REGFN]] to void ()*), i8* bitcast (void (i8*)* @[[REGFN]] to i8*) }] 77 78 79 template<typename tx, typename ty> 80 struct TT{ 81 tx X; 82 ty Y; 83 }; 84 85 int global; 86 extern int global; 87 88 // CHECK: define {{.*}}[[FOO:@.+]]( 89 int foo(int n) { 90 int a = 0; 91 short aa = 0; 92 float b[10]; 93 float bn[n]; 94 double c[5][10]; 95 double cn[5][n]; 96 TT<long long, char> d; 97 static long *plocal; 98 99 // CHECK: [[ADD:%.+]] = add nsw i32 100 // CHECK: store i32 [[ADD]], i32* [[CAPTURE:%.+]], 101 // CHECK: [[LD:%.+]] = load i32, i32* [[CAPTURE]], 102 // CHECK: [[RET:%.+]] = call i32 @__tgt_target(i32 [[LD]], i8* @{{[^,]+}}, i32 0, i8** null, i8** null, i[[SZ]]* null, i32* null) 103 // CHECK-NEXT: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 104 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 105 // CHECK: [[FAIL]] 106 // CHECK: call void [[HVT0:@.+]]() 107 // CHECK-NEXT: br label %[[END]] 108 // CHECK: [[END]] 109 #pragma omp target device(global + a) 110 { 111 } 112 113 // CHECK: [[ADD:%.+]] = add nsw i32 114 // CHECK: store i32 [[ADD]], i32* [[CAPTURE:%.+]], 115 // CHECK-DAG: [[LD:%.+]] = load i32, i32* [[CAPTURE]], 116 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 [[LD]], i8* @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([2 x i[[SZ]]], [2 x i[[SZ]]]* [[SIZET]], i32 0, i32 0), i32* getelementptr inbounds ([2 x i32], [2 x i32]* [[MAPT]], i32 0, i32 0) 117 // CHECK-DAG: [[BPR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP:%[^,]+]], i32 0, i32 0 118 // CHECK-DAG: [[PR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P:%[^,]+]], i32 0, i32 0 119 120 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 0 121 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 0 122 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]** 123 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]** 124 // CHECK-DAG: store i[[SZ]]* [[BP0:%[^,]+]], i[[SZ]]** [[CBPADDR0]] 125 // CHECK-DAG: store i[[SZ]]* [[BP0]], i[[SZ]]** [[CPADDR0]] 126 127 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 1 128 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 1 129 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* 130 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* 131 // CHECK-DAG: store i[[SZ]] [[BP1:%[^,]+]], i[[SZ]]* [[CBPADDR1]] 132 // CHECK-DAG: store i[[SZ]] [[BP1]], i[[SZ]]* [[CPADDR1]] 133 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 134 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 135 // CHECK: [[FAIL]] 136 // CHECK: call void [[HVT0_:@.+]](i[[SZ]]* [[BP0]], i[[SZ]] [[BP1]]) 137 // CHECK-NEXT: br label %[[END]] 138 // CHECK: [[END]] 139 #pragma omp target device(global + a) 140 { 141 static int local1; 142 *plocal = global; 143 local1 = global; 144 } 145 146 // CHECK: call void [[HVT1:@.+]](i[[SZ]] {{[^,]+}}) 147 #pragma omp target if(0) firstprivate(global) 148 { 149 global += 1; 150 } 151 152 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 1, i8** [[BP:%[^,]+]], i8** [[P:%[^,]+]], i[[SZ]]* getelementptr inbounds ([1 x i[[SZ]]], [1 x i[[SZ]]]* [[SIZET2]], i32 0, i32 0), i32* getelementptr inbounds ([1 x i32], [1 x i32]* [[MAPT2]], i32 0, i32 0)) 153 // CHECK-DAG: [[BP]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPR:%[^,]+]], i32 0, i32 0 154 // CHECK-DAG: [[P]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PR:%[^,]+]], i32 0, i32 0 155 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[BPR]], i32 0, i32 [[IDX0:[0-9]+]] 156 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [1 x i8*], [1 x i8*]* [[PR]], i32 0, i32 [[IDX0]] 157 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 158 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 159 // CHECK-DAG: store i[[SZ]] [[BP0:%[^,]+]], i[[SZ]]* [[CBPADDR0]] 160 // CHECK-DAG: store i[[SZ]] [[P0:%[^,]+]], i[[SZ]]* [[CPADDR0]] 161 162 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 163 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:[^,]+]], label %[[END:[^,]+]] 164 // CHECK: [[FAIL]] 165 // CHECK: call void [[HVT2:@.+]](i[[SZ]] {{[^,]+}}) 166 // CHECK-NEXT: br label %[[END]] 167 // CHECK: [[END]] 168 #pragma omp target if(1) 169 { 170 aa += 1; 171 } 172 173 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 10 174 // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]] 175 // CHECK: [[IFTHEN]] 176 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 2, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([2 x i[[SZ]]], [2 x i[[SZ]]]* [[SIZET3]], i32 0, i32 0), i32* getelementptr inbounds ([2 x i32], [2 x i32]* [[MAPT3]], i32 0, i32 0)) 177 // CHECK-DAG: [[BPR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP:%[^,]+]], i32 0, i32 0 178 // CHECK-DAG: [[PR]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P:%[^,]+]], i32 0, i32 0 179 180 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 0 181 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 0 182 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 183 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 184 // CHECK-DAG: store i[[SZ]] [[BP0:%[^,]+]], i[[SZ]]* [[CBPADDR0]] 185 // CHECK-DAG: store i[[SZ]] [[P0:%[^,]+]], i[[SZ]]* [[CPADDR0]] 186 187 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[BP]], i32 0, i32 1 188 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [2 x i8*], [2 x i8*]* [[P]], i32 0, i32 1 189 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* 190 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* 191 // CHECK-DAG: store i[[SZ]] [[BP1:%[^,]+]], i[[SZ]]* [[CBPADDR1]] 192 // CHECK-DAG: store i[[SZ]] [[P1:%[^,]+]], i[[SZ]]* [[CPADDR1]] 193 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 194 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 195 // CHECK: [[FAIL]] 196 // CHECK: call void [[HVT3:@.+]]({{[^,]+}}, {{[^,]+}}) 197 // CHECK-NEXT: br label %[[END]] 198 // CHECK: [[END]] 199 // CHECK-NEXT: br label %[[IFEND:.+]] 200 // CHECK: [[IFELSE]] 201 // CHECK: call void [[HVT3]]({{[^,]+}}, {{[^,]+}}) 202 // CHECK-NEXT: br label %[[IFEND]] 203 204 // CHECK: [[IFEND]] 205 #pragma omp target if(n>10) 206 { 207 a += 1; 208 aa += 1; 209 } 210 211 // We capture 3 VLA sizes in this target region 212 // CHECK-64: [[A_VAL:%.+]] = load i32, i32* %{{.+}}, 213 // CHECK-64: [[A_ADDR:%.+]] = bitcast i[[SZ]]* [[A_CADDR:%.+]] to i32* 214 // CHECK-64: store i32 [[A_VAL]], i32* [[A_ADDR]], 215 // CHECK-64: [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]], 216 217 // CHECK-32: [[A_VAL:%.+]] = load i32, i32* %{{.+}}, 218 // CHECK-32: store i32 [[A_VAL]], i32* [[A_CADDR:%.+]], 219 // CHECK-32: [[A_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[A_CADDR]], 220 221 // CHECK: [[BNSIZE:%.+]] = mul nuw i[[SZ]] [[VLA0:%.+]], 4 222 // CHECK: [[CNELEMSIZE2:%.+]] = mul nuw i[[SZ]] 5, [[VLA1:%.+]] 223 // CHECK: [[CNSIZE:%.+]] = mul nuw i[[SZ]] [[CNELEMSIZE2]], 8 224 225 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 20 226 // CHECK: br i1 [[IF]], label %[[TRY:[^,]+]], label %[[IFELSE:[^,]+]] 227 // CHECK: [[TRY]] 228 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 9, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SR:%[^,]+]], i32* getelementptr inbounds ([9 x i32], [9 x i32]* [[MAPT4]], i32 0, i32 0)) 229 // CHECK-DAG: [[BPR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP:%[^,]+]], i32 0, i32 0 230 // CHECK-DAG: [[PR]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P:%[^,]+]], i32 0, i32 0 231 // CHECK-DAG: [[SR]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S:%[^,]+]], i32 0, i32 0 232 233 // CHECK-DAG: [[SADDR0:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX0:0]] 234 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX0]] 235 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX0]] 236 // CHECK-DAG: [[SADDR1:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX1:1]] 237 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX1]] 238 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX1]] 239 // CHECK-DAG: [[SADDR2:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX2:2]] 240 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX2]] 241 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX2]] 242 // CHECK-DAG: [[SADDR3:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX3:3]] 243 // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX3]] 244 // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX3]] 245 // CHECK-DAG: [[SADDR4:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX4:4]] 246 // CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX4]] 247 // CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX4]] 248 // CHECK-DAG: [[SADDR5:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX5:5]] 249 // CHECK-DAG: [[BPADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX5]] 250 // CHECK-DAG: [[PADDR5:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX5]] 251 // CHECK-DAG: [[SADDR6:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX6:6]] 252 // CHECK-DAG: [[BPADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX6]] 253 // CHECK-DAG: [[PADDR6:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX6]] 254 // CHECK-DAG: [[SADDR7:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX7:7]] 255 // CHECK-DAG: [[BPADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX7]] 256 // CHECK-DAG: [[PADDR7:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX7]] 257 // CHECK-DAG: [[SADDR8:%.+]] = getelementptr inbounds [9 x i[[SZ]]], [9 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX8:8]] 258 // CHECK-DAG: [[BPADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[BP]], i32 0, i32 [[IDX8]] 259 // CHECK-DAG: [[PADDR8:%.+]] = getelementptr inbounds [9 x i8*], [9 x i8*]* [[P]], i32 0, i32 [[IDX8]] 260 261 // The names below are not necessarily consistent with the names used for the 262 // addresses above as some are repeated. 263 // CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to i[[SZ]]* 264 // CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to i[[SZ]]* 265 // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CBPADDR2]] 266 // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CPADDR2]] 267 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR2]] 268 269 // CHECK-DAG: [[CBPADDR6:%.+]] = bitcast i8** [[BPADDR6]] to i[[SZ]]* 270 // CHECK-DAG: [[CPADDR6:%.+]] = bitcast i8** [[PADDR6]] to i[[SZ]]* 271 // CHECK-DAG: store i[[SZ]] [[VLA1]], i[[SZ]]* [[CBPADDR6]] 272 // CHECK-DAG: store i[[SZ]] [[VLA1]], i[[SZ]]* [[CPADDR6]] 273 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR6]] 274 275 // CHECK-DAG: [[CBPADDR5:%.+]] = bitcast i8** [[BPADDR5]] to i[[SZ]]* 276 // CHECK-DAG: [[CPADDR5:%.+]] = bitcast i8** [[PADDR5]] to i[[SZ]]* 277 // CHECK-DAG: store i[[SZ]] 5, i[[SZ]]* [[CBPADDR5]] 278 // CHECK-DAG: store i[[SZ]] 5, i[[SZ]]* [[CPADDR5]] 279 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR5]] 280 281 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 282 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 283 // CHECK-DAG: store i[[SZ]] [[A_CVAL]], i[[SZ]]* [[CBPADDR0]] 284 // CHECK-DAG: store i[[SZ]] [[A_CVAL]], i[[SZ]]* [[CPADDR0]] 285 // CHECK-DAG: store i[[SZ]] 4, i[[SZ]]* [[SADDR0]] 286 287 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to [10 x float]** 288 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to [10 x float]** 289 // CHECK-DAG: store [10 x float]* %{{.+}}, [10 x float]** [[CBPADDR1]] 290 // CHECK-DAG: store [10 x float]* %{{.+}}, [10 x float]** [[CPADDR1]] 291 // CHECK-DAG: store i[[SZ]] 40, i[[SZ]]* [[SADDR1]] 292 293 // CHECK-DAG: [[CBPADDR3:%.+]] = bitcast i8** [[BPADDR3]] to float** 294 // CHECK-DAG: [[CPADDR3:%.+]] = bitcast i8** [[PADDR3]] to float** 295 // CHECK-DAG: store float* %{{.+}}, float** [[CBPADDR3]] 296 // CHECK-DAG: store float* %{{.+}}, float** [[CPADDR3]] 297 // CHECK-DAG: store i[[SZ]] [[BNSIZE]], i[[SZ]]* [[SADDR3]] 298 299 // CHECK-DAG: [[CBPADDR4:%.+]] = bitcast i8** [[BPADDR4]] to [5 x [10 x double]]** 300 // CHECK-DAG: [[CPADDR4:%.+]] = bitcast i8** [[PADDR4]] to [5 x [10 x double]]** 301 // CHECK-DAG: store [5 x [10 x double]]* %{{.+}}, [5 x [10 x double]]** [[CBPADDR4]] 302 // CHECK-DAG: store [5 x [10 x double]]* %{{.+}}, [5 x [10 x double]]** [[CPADDR4]] 303 // CHECK-DAG: store i[[SZ]] 400, i[[SZ]]* [[SADDR4]] 304 305 // CHECK-DAG: [[CBPADDR7:%.+]] = bitcast i8** [[BPADDR7]] to double** 306 // CHECK-DAG: [[CPADDR7:%.+]] = bitcast i8** [[PADDR7]] to double** 307 // CHECK-DAG: store double* %{{.+}}, double** [[CBPADDR7]] 308 // CHECK-DAG: store double* %{{.+}}, double** [[CPADDR7]] 309 // CHECK-DAG: store i[[SZ]] [[CNSIZE]], i[[SZ]]* [[SADDR7]] 310 311 // CHECK-DAG: [[CBPADDR8:%.+]] = bitcast i8** [[BPADDR8]] to [[TT]]** 312 // CHECK-DAG: [[CPADDR8:%.+]] = bitcast i8** [[PADDR8]] to [[TT]]** 313 // CHECK-DAG: store [[TT]]* %{{.+}}, [[TT]]** [[CBPADDR8]] 314 // CHECK-DAG: store [[TT]]* %{{.+}}, [[TT]]** [[CPADDR8]] 315 // CHECK-DAG: store i[[SZ]] {{12|16}}, i[[SZ]]* [[SADDR8]] 316 317 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 318 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 319 // CHECK: [[FAIL]] 320 // CHECK: call void [[HVT4:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 321 // CHECK-NEXT: br label %[[END]] 322 // CHECK: [[END]] 323 // CHECK-NEXT: br label %[[IFEND:.+]] 324 // CHECK: [[IFELSE]] 325 // CHECK: call void [[HVT4]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 326 // CHECK-NEXT: br label %[[IFEND]] 327 328 // CHECK: [[IFEND]] 329 #pragma omp target if(n>20) 330 { 331 a += 1; 332 b[2] += 1.0; 333 bn[3] += 1.0; 334 c[1][2] += 1.0; 335 cn[1][3] += 1.0; 336 d.X += 1; 337 d.Y += 1; 338 } 339 340 return a; 341 } 342 343 // Check that the offloading functions are emitted and that the arguments are 344 // correct and loaded correctly for the target regions in foo(). 345 346 // CHECK: define internal void [[HVT0]]() 347 348 // CHECK: define internal void [[HVT1]](i[[SZ]] %{{.+}}) 349 // Create stack storage and store argument in there. 350 // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align 351 // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align 352 // CHECK-64: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i32* 353 // CHECK-64: load i32, i32* [[AA_CADDR]], align 354 // CHECK-32: load i32, i32* [[AA_ADDR]], align 355 356 // CHECK: define internal void [[HVT2]](i[[SZ]] %{{.+}}) 357 // Create stack storage and store argument in there. 358 // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align 359 // CHECK: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align 360 // CHECK: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* 361 // CHECK: load i16, i16* [[AA_CADDR]], align 362 363 // CHECK: define internal void [[HVT3]] 364 // Create stack storage and store argument in there. 365 // CHECK: [[A_ADDR:%.+]] = alloca i[[SZ]], align 366 // CHECK: [[AA_ADDR:%.+]] = alloca i[[SZ]], align 367 // CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[A_ADDR]], align 368 // CHECK-DAG: store i[[SZ]] %{{.+}}, i[[SZ]]* [[AA_ADDR]], align 369 // CHECK-64-DAG:[[A_CADDR:%.+]] = bitcast i[[SZ]]* [[A_ADDR]] to i32* 370 // CHECK-DAG: [[AA_CADDR:%.+]] = bitcast i[[SZ]]* [[AA_ADDR]] to i16* 371 // CHECK-64-DAG:load i32, i32* [[A_CADDR]], align 372 // CHECK-32-DAG:load i32, i32* [[A_ADDR]], align 373 // CHECK-DAG: load i16, i16* [[AA_CADDR]], align 374 375 // CHECK: define internal void [[HVT4]] 376 // Create local storage for each capture. 377 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] 378 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x float]* 379 // CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]] 380 // CHECK: [[LOCAL_BN:%.+]] = alloca float* 381 // CHECK: [[LOCAL_C:%.+]] = alloca [5 x [10 x double]]* 382 // CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]] 383 // CHECK: [[LOCAL_VLA3:%.+]] = alloca i[[SZ]] 384 // CHECK: [[LOCAL_CN:%.+]] = alloca double* 385 // CHECK: [[LOCAL_D:%.+]] = alloca [[TT]]* 386 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 387 // CHECK-DAG: store [10 x float]* [[ARG_B:%.+]], [10 x float]** [[LOCAL_B]] 388 // CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]] 389 // CHECK-DAG: store float* [[ARG_BN:%.+]], float** [[LOCAL_BN]] 390 // CHECK-DAG: store [5 x [10 x double]]* [[ARG_C:%.+]], [5 x [10 x double]]** [[LOCAL_C]] 391 // CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]] 392 // CHECK-DAG: store i[[SZ]] [[ARG_VLA3:%.+]], i[[SZ]]* [[LOCAL_VLA3]] 393 // CHECK-DAG: store double* [[ARG_CN:%.+]], double** [[LOCAL_CN]] 394 // CHECK-DAG: store [[TT]]* [[ARG_D:%.+]], [[TT]]** [[LOCAL_D]] 395 396 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 397 // CHECK-DAG: [[REF_B:%.+]] = load [10 x float]*, [10 x float]** [[LOCAL_B]], 398 // CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]], 399 // CHECK-DAG: [[REF_BN:%.+]] = load float*, float** [[LOCAL_BN]], 400 // CHECK-DAG: [[REF_C:%.+]] = load [5 x [10 x double]]*, [5 x [10 x double]]** [[LOCAL_C]], 401 // CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]], 402 // CHECK-DAG: [[VAL_VLA3:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA3]], 403 // CHECK-DAG: [[REF_CN:%.+]] = load double*, double** [[LOCAL_CN]], 404 // CHECK-DAG: [[REF_D:%.+]] = load [[TT]]*, [[TT]]** [[LOCAL_D]], 405 406 // Use captures. 407 // CHECK-64-DAG: load i32, i32* [[REF_A]] 408 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 409 // CHECK-DAG: getelementptr inbounds [10 x float], [10 x float]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 410 // CHECK-DAG: getelementptr inbounds float, float* [[REF_BN]], i[[SZ]] 3 411 // CHECK-DAG: getelementptr inbounds [5 x [10 x double]], [5 x [10 x double]]* [[REF_C]], i[[SZ]] 0, i[[SZ]] 1 412 // CHECK-DAG: getelementptr inbounds double, double* [[REF_CN]], i[[SZ]] %{{.+}} 413 // CHECK-DAG: getelementptr inbounds [[TT]], [[TT]]* [[REF_D]], i32 0, i32 0 414 415 template<typename tx> 416 tx ftemplate(int n) { 417 tx a = 0; 418 short aa = 0; 419 tx b[10]; 420 421 #pragma omp target if(n>40) 422 { 423 a += 1; 424 aa += 1; 425 b[2] += 1; 426 } 427 428 return a; 429 } 430 431 static 432 int fstatic(int n) { 433 int a = 0; 434 short aa = 0; 435 char aaa = 0; 436 int b[10]; 437 438 #pragma omp target if(n>50) 439 { 440 a += 1; 441 aa += 1; 442 aaa += 1; 443 b[2] += 1; 444 } 445 446 return a; 447 } 448 449 struct S1 { 450 double a; 451 452 int r1(int n){ 453 int b = n+1; 454 short int c[2][n]; 455 456 #pragma omp target if(n>60) 457 { 458 this->a = (double)b + 1.5; 459 c[1][1] = ++a; 460 } 461 462 return c[1][1] + (int)b; 463 } 464 }; 465 466 // CHECK: define {{.*}}@{{.*}}bar{{.*}} 467 int bar(int n){ 468 int a = 0; 469 470 // CHECK: call {{.*}}i32 [[FOO]](i32 {{.*}}) 471 a += foo(n); 472 473 S1 S; 474 // CHECK: call {{.*}}i32 [[FS1:@.+]]([[S1]]* {{.*}}, i32 {{.*}}) 475 a += S.r1(n); 476 477 // CHECK: call {{.*}}i32 [[FSTATIC:@.+]](i32 {{.*}}) 478 a += fstatic(n); 479 480 // CHECK: call {{.*}}i32 [[FTEMPLATE:@.+]](i32 {{.*}}) 481 a += ftemplate<int>(n); 482 483 return a; 484 } 485 486 // 487 // CHECK: define {{.*}}[[FS1]] 488 // 489 // CHECK: i8* @llvm.stacksave() 490 // CHECK-64: [[B_ADDR:%.+]] = bitcast i[[SZ]]* [[B_CADDR:%.+]] to i32* 491 // CHECK-64: store i32 %{{.+}}, i32* [[B_ADDR]], 492 // CHECK-64: [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_CADDR]], 493 494 // CHECK-32: store i32 %{{.+}}, i32* [[B_ADDR:%.+]], 495 // CHECK-32: [[B_CVAL:%.+]] = load i[[SZ]], i[[SZ]]* [[B_ADDR]], 496 497 // We capture 2 VLA sizes in this target region 498 // CHECK: [[CELEMSIZE2:%.+]] = mul nuw i[[SZ]] 2, [[VLA0:%.+]] 499 // CHECK: [[CSIZE:%.+]] = mul nuw i[[SZ]] [[CELEMSIZE2]], 2 500 501 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 60 502 // CHECK: br i1 [[IF]], label %[[TRY:[^,]+]], label %[[IFELSE:[^,]+]] 503 // CHECK: [[TRY]] 504 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 5, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* [[SR:%[^,]+]], i32* getelementptr inbounds ([5 x i32], [5 x i32]* [[MAPT7]], i32 0, i32 0)) 505 // CHECK-DAG: [[BPR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP:%.+]], i32 0, i32 0 506 // CHECK-DAG: [[PR]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P:%.+]], i32 0, i32 0 507 // CHECK-DAG: [[SR]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S:%.+]], i32 0, i32 0 508 // CHECK-DAG: [[SADDR0:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX0:0]] 509 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX0]] 510 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX0]] 511 // CHECK-DAG: [[SADDR1:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX1:1]] 512 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX1]] 513 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX1]] 514 // CHECK-DAG: [[SADDR2:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX2:2]] 515 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX2]] 516 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX2]] 517 // CHECK-DAG: [[SADDR3:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX3:3]] 518 // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX3]] 519 // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX3]] 520 // CHECK-DAG: [[SADDR4:%.+]] = getelementptr inbounds [5 x i[[SZ]]], [5 x i[[SZ]]]* [[S]], i32 0, i32 [[IDX4:4]] 521 // CHECK-DAG: [[BPADDR4:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[BP]], i32 0, i32 [[IDX4]] 522 // CHECK-DAG: [[PADDR4:%.+]] = getelementptr inbounds [5 x i8*], [5 x i8*]* [[P]], i32 0, i32 [[IDX4]] 523 524 // The names below are not necessarily consistent with the names used for the 525 // addresses above as some are repeated. 526 // CHECK-DAG: [[CBPADDR3:%.+]] = bitcast i8** [[BPADDR3]] to i[[SZ]]* 527 // CHECK-DAG: [[CPADDR3:%.+]] = bitcast i8** [[PADDR3]] to i[[SZ]]* 528 // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CBPADDR3]] 529 // CHECK-DAG: store i[[SZ]] [[VLA0]], i[[SZ]]* [[CPADDR3]] 530 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR3]] 531 532 // CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to i[[SZ]]* 533 // CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to i[[SZ]]* 534 // CHECK-DAG: store i[[SZ]] 2, i[[SZ]]* [[CBPADDR2]] 535 // CHECK-DAG: store i[[SZ]] 2, i[[SZ]]* [[CPADDR2]] 536 // CHECK-DAG: store i[[SZ]] {{4|8}}, i[[SZ]]* [[SADDR2]] 537 538 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* 539 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* 540 // CHECK-DAG: store i[[SZ]] [[B_CVAL]], i[[SZ]]* [[CBPADDR1]] 541 // CHECK-DAG: store i[[SZ]] [[B_CVAL]], i[[SZ]]* [[CPADDR1]] 542 // CHECK-DAG: store i[[SZ]] 4, i[[SZ]]* [[SADDR1]] 543 544 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to [[S1]]** 545 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to double** 546 // CHECK-DAG: store [[S1]]* %{{.+}}, [[S1]]** [[CBPADDR0]] 547 // CHECK-DAG: store double* %{{.+}}, double** [[CPADDR0]] 548 // CHECK-DAG: store i[[SZ]] 8, i[[SZ]]* [[SADDR0]] 549 550 // CHECK-DAG: [[CBPADDR4:%.+]] = bitcast i8** [[BPADDR4]] to i16** 551 // CHECK-DAG: [[CPADDR4:%.+]] = bitcast i8** [[PADDR4]] to i16** 552 // CHECK-DAG: store i16* %{{.+}}, i16** [[CBPADDR4]] 553 // CHECK-DAG: store i16* %{{.+}}, i16** [[CPADDR4]] 554 // CHECK-DAG: store i[[SZ]] [[CSIZE]], i[[SZ]]* [[SADDR4]] 555 556 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 557 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 558 // CHECK: [[FAIL]] 559 // CHECK: call void [[HVT7:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 560 // CHECK-NEXT: br label %[[END]] 561 // CHECK: [[END]] 562 // CHECK-NEXT: br label %[[IFEND:.+]] 563 // CHECK: [[IFELSE]] 564 // CHECK: call void [[HVT7]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 565 // CHECK-NEXT: br label %[[IFEND]] 566 567 // CHECK: [[IFEND]] 568 569 // 570 // CHECK: define {{.*}}[[FSTATIC]] 571 // 572 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 50 573 // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]] 574 // CHECK: [[IFTHEN]] 575 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 4, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([4 x i[[SZ]]], [4 x i[[SZ]]]* [[SIZET6]], i32 0, i32 0), i32* getelementptr inbounds ([4 x i32], [4 x i32]* [[MAPT6]], i32 0, i32 0)) 576 // CHECK-DAG: [[BPR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP:%.+]], i32 0, i32 0 577 // CHECK-DAG: [[PR]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P:%.+]], i32 0, i32 0 578 579 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 0 580 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 0 581 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 582 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 583 // CHECK-DAG: store i[[SZ]] [[VAL0:%[^,]+]], i[[SZ]]* [[CBPADDR0]] 584 // CHECK-DAG: store i[[SZ]] [[VAL0]], i[[SZ]]* [[CPADDR0]] 585 586 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 1 587 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 1 588 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* 589 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* 590 // CHECK-DAG: store i[[SZ]] [[VAL1:%[^,]+]], i[[SZ]]* [[CBPADDR1]] 591 // CHECK-DAG: store i[[SZ]] [[VAL1]], i[[SZ]]* [[CPADDR1]] 592 593 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 2 594 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 2 595 // CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to i[[SZ]]* 596 // CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to i[[SZ]]* 597 // CHECK-DAG: store i[[SZ]] [[VAL2:%[^,]+]], i[[SZ]]* [[CBPADDR2]] 598 // CHECK-DAG: store i[[SZ]] [[VAL2]], i[[SZ]]* [[CPADDR2]] 599 600 // CHECK-DAG: [[BPADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[BP]], i32 0, i32 3 601 // CHECK-DAG: [[PADDR3:%.+]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[P]], i32 0, i32 3 602 // CHECK-DAG: [[CBPADDR3:%.+]] = bitcast i8** [[BPADDR3]] to [10 x i32]** 603 // CHECK-DAG: [[CPADDR3:%.+]] = bitcast i8** [[PADDR3]] to [10 x i32]** 604 // CHECK-DAG: store [10 x i32]* [[VAL3:%[^,]+]], [10 x i32]** [[CBPADDR3]] 605 // CHECK-DAG: store [10 x i32]* [[VAL3]], [10 x i32]** [[CPADDR3]] 606 607 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 608 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 609 // CHECK: [[FAIL]] 610 // CHECK: call void [[HVT6:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 611 // CHECK-NEXT: br label %[[END]] 612 // CHECK: [[END]] 613 // CHECK-NEXT: br label %[[IFEND:.+]] 614 // CHECK: [[IFELSE]] 615 // CHECK: call void [[HVT6]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 616 // CHECK-NEXT: br label %[[IFEND]] 617 618 // CHECK: [[IFEND]] 619 620 // 621 // CHECK: define {{.*}}[[FTEMPLATE]] 622 // 623 // CHECK: [[IF:%.+]] = icmp sgt i32 {{[^,]+}}, 40 624 // CHECK: br i1 [[IF]], label %[[IFTHEN:[^,]+]], label %[[IFELSE:[^,]+]] 625 // CHECK: [[IFTHEN]] 626 // CHECK-DAG: [[RET:%.+]] = call i32 @__tgt_target(i32 -1, i8* @{{[^,]+}}, i32 3, i8** [[BPR:%[^,]+]], i8** [[PR:%[^,]+]], i[[SZ]]* getelementptr inbounds ([3 x i[[SZ]]], [3 x i[[SZ]]]* [[SIZET5]], i32 0, i32 0), i32* getelementptr inbounds ([3 x i32], [3 x i32]* [[MAPT5]], i32 0, i32 0)) 627 // CHECK-DAG: [[BPR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP:%.+]], i32 0, i32 0 628 // CHECK-DAG: [[PR]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P:%.+]], i32 0, i32 0 629 630 // CHECK-DAG: [[BPADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 0 631 // CHECK-DAG: [[PADDR0:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 0 632 // CHECK-DAG: [[CBPADDR0:%.+]] = bitcast i8** [[BPADDR0]] to i[[SZ]]* 633 // CHECK-DAG: [[CPADDR0:%.+]] = bitcast i8** [[PADDR0]] to i[[SZ]]* 634 // CHECK-DAG: store i[[SZ]] [[VAL0:%[^,]+]], i[[SZ]]* [[CBPADDR0]] 635 // CHECK-DAG: store i[[SZ]] [[VAL0]], i[[SZ]]* [[CPADDR0]] 636 637 // CHECK-DAG: [[BPADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 1 638 // CHECK-DAG: [[PADDR1:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 1 639 // CHECK-DAG: [[CBPADDR1:%.+]] = bitcast i8** [[BPADDR1]] to i[[SZ]]* 640 // CHECK-DAG: [[CPADDR1:%.+]] = bitcast i8** [[PADDR1]] to i[[SZ]]* 641 // CHECK-DAG: store i[[SZ]] [[VAL1:%[^,]+]], i[[SZ]]* [[CBPADDR1]] 642 // CHECK-DAG: store i[[SZ]] [[VAL1]], i[[SZ]]* [[CPADDR1]] 643 644 // CHECK-DAG: [[BPADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[BP]], i32 0, i32 2 645 // CHECK-DAG: [[PADDR2:%.+]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[P]], i32 0, i32 2 646 // CHECK-DAG: [[CBPADDR2:%.+]] = bitcast i8** [[BPADDR2]] to [10 x i32]** 647 // CHECK-DAG: [[CPADDR2:%.+]] = bitcast i8** [[PADDR2]] to [10 x i32]** 648 // CHECK-DAG: store [10 x i32]* [[VAL2:%[^,]+]], [10 x i32]** [[CBPADDR2]] 649 // CHECK-DAG: store [10 x i32]* [[VAL2]], [10 x i32]** [[CPADDR2]] 650 651 // CHECK: [[ERROR:%.+]] = icmp ne i32 [[RET]], 0 652 // CHECK-NEXT: br i1 [[ERROR]], label %[[FAIL:.+]], label %[[END:[^,]+]] 653 // CHECK: [[FAIL]] 654 // CHECK: call void [[HVT5:@.+]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 655 // CHECK-NEXT: br label %[[END]] 656 // CHECK: [[END]] 657 // CHECK-NEXT: br label %[[IFEND:.+]] 658 // CHECK: [[IFELSE]] 659 // CHECK: call void [[HVT5]]({{[^,]+}}, {{[^,]+}}, {{[^,]+}}) 660 // CHECK-NEXT: br label %[[IFEND]] 661 662 // CHECK: [[IFEND]] 663 664 665 // Check that the offloading functions are emitted and that the arguments are 666 // correct and loaded correctly for the target regions of the callees of bar(). 667 668 // CHECK: define internal void [[HVT7]] 669 // Create local storage for each capture. 670 // CHECK: [[LOCAL_THIS:%.+]] = alloca [[S1]]* 671 // CHECK: [[LOCAL_B:%.+]] = alloca i[[SZ]] 672 // CHECK: [[LOCAL_VLA1:%.+]] = alloca i[[SZ]] 673 // CHECK: [[LOCAL_VLA2:%.+]] = alloca i[[SZ]] 674 // CHECK: [[LOCAL_C:%.+]] = alloca i16* 675 // CHECK-DAG: store [[S1]]* [[ARG_THIS:%.+]], [[S1]]** [[LOCAL_THIS]] 676 // CHECK-DAG: store i[[SZ]] [[ARG_B:%.+]], i[[SZ]]* [[LOCAL_B]] 677 // CHECK-DAG: store i[[SZ]] [[ARG_VLA1:%.+]], i[[SZ]]* [[LOCAL_VLA1]] 678 // CHECK-DAG: store i[[SZ]] [[ARG_VLA2:%.+]], i[[SZ]]* [[LOCAL_VLA2]] 679 // CHECK-DAG: store i16* [[ARG_C:%.+]], i16** [[LOCAL_C]] 680 // Store captures in the context. 681 // CHECK-DAG: [[REF_THIS:%.+]] = load [[S1]]*, [[S1]]** [[LOCAL_THIS]], 682 // CHECK-64-DAG:[[REF_B:%.+]] = bitcast i[[SZ]]* [[LOCAL_B]] to i32* 683 // CHECK-DAG: [[VAL_VLA1:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA1]], 684 // CHECK-DAG: [[VAL_VLA2:%.+]] = load i[[SZ]], i[[SZ]]* [[LOCAL_VLA2]], 685 // CHECK-DAG: [[REF_C:%.+]] = load i16*, i16** [[LOCAL_C]], 686 // Use captures. 687 // CHECK-DAG: getelementptr inbounds [[S1]], [[S1]]* [[REF_THIS]], i32 0, i32 0 688 // CHECK-64-DAG:load i32, i32* [[REF_B]] 689 // CHECK-32-DAG:load i32, i32* [[LOCAL_B]] 690 // CHECK-DAG: getelementptr inbounds i16, i16* [[REF_C]], i[[SZ]] %{{.+}} 691 692 693 // CHECK: define internal void [[HVT6]] 694 // Create local storage for each capture. 695 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] 696 // CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]] 697 // CHECK: [[LOCAL_AAA:%.+]] = alloca i[[SZ]] 698 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* 699 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 700 // CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] 701 // CHECK-DAG: store i[[SZ]] [[ARG_AAA:%.+]], i[[SZ]]* [[LOCAL_AAA]] 702 // CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] 703 // Store captures in the context. 704 // CHECK-64-DAG: [[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 705 // CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* 706 // CHECK-DAG: [[REF_AAA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AAA]] to i8* 707 // CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], 708 // Use captures. 709 // CHECK-64-DAG: load i32, i32* [[REF_A]] 710 // CHECK-DAG: load i16, i16* [[REF_AA]] 711 // CHECK-DAG: load i8, i8* [[REF_AAA]] 712 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 713 // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 714 715 // CHECK: define internal void [[HVT5]] 716 // Create local storage for each capture. 717 // CHECK: [[LOCAL_A:%.+]] = alloca i[[SZ]] 718 // CHECK: [[LOCAL_AA:%.+]] = alloca i[[SZ]] 719 // CHECK: [[LOCAL_B:%.+]] = alloca [10 x i32]* 720 // CHECK-DAG: store i[[SZ]] [[ARG_A:%.+]], i[[SZ]]* [[LOCAL_A]] 721 // CHECK-DAG: store i[[SZ]] [[ARG_AA:%.+]], i[[SZ]]* [[LOCAL_AA]] 722 // CHECK-DAG: store [10 x i32]* [[ARG_B:%.+]], [10 x i32]** [[LOCAL_B]] 723 // Store captures in the context. 724 // CHECK-64-DAG:[[REF_A:%.+]] = bitcast i[[SZ]]* [[LOCAL_A]] to i32* 725 // CHECK-DAG: [[REF_AA:%.+]] = bitcast i[[SZ]]* [[LOCAL_AA]] to i16* 726 // CHECK-DAG: [[REF_B:%.+]] = load [10 x i32]*, [10 x i32]** [[LOCAL_B]], 727 // Use captures. 728 // CHECK-64-DAG: load i32, i32* [[REF_A]] 729 // CHECK-32-DAG: load i32, i32* [[LOCAL_A]] 730 // CHECK-DAG: load i16, i16* [[REF_AA]] 731 // CHECK-DAG: getelementptr inbounds [10 x i32], [10 x i32]* [[REF_B]], i[[SZ]] 0, i[[SZ]] 2 732 #endif 733