1 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s 2 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 3 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -g -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s 4 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -gline-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=TERM_DEBUG 5 // REQUIRES: x86-registered-target 6 // expected-no-diagnostics 7 #ifndef HEADER 8 #define HEADER 9 10 long long get_val() { return 0; } 11 double *g_ptr; 12 13 // CHECK-LABEL: define {{.*void}} @{{.*}}simple{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) 14 void simple(float *a, float *b, float *c, float *d) { 15 // CHECK: call void (%ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( 16 // CHECK: [[K0:%.+]] = call {{.*}}i64 @{{.*}}get_val 17 // CHECK-NEXT: store i64 [[K0]], i64* [[K_VAR:%[^,]+]] 18 // CHECK: call void (%ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( 19 // CHECK: store i32 12, i32* [[LIN_VAR:%[^,]+]] 20 // CHECK: call void (%ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( 21 // CHECK: call void (%ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( 22 // CHECK: call void (%ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( 23 // CHECK: call void (%ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( 24 // CHECK: store i32 -1, i32* [[A:%.+]], 25 // CHECK: call void (%ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( 26 // CHECK: store i32 -1, i32* [[R:%[^,]+]], 27 // CHECK: call void (%ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( 28 #pragma omp parallel for simd 29 // CHECK: call void @__kmpc_for_static_init_4(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i32* [[LB:%[^,]+]], i32* [[UB:%[^,]+]], i32* [[STRIDE:%[^,]+]], i32 1, i32 1) 30 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 31 // CHECK: [[CMP:%.+]] = icmp sgt i32 [[UB_VAL]], 5 32 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 33 // CHECK: [[TRUE]] 34 // CHECK: br label %[[SWITCH:[^,]+]] 35 // CHECK: [[FALSE]] 36 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 37 // CHECK: br label %[[SWITCH]] 38 // CHECK: [[SWITCH]] 39 // CHECK: [[UP:%.+]] = phi i32 [ 5, %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 40 // CHECK: store i32 [[UP]], i32* [[UB]], 41 // CHECK: [[LB_VAL:%.+]] = load i32, i32* [[LB]], 42 // CHECK: store i32 [[LB_VAL]], i32* [[OMP_IV:%[^,]+]], 43 44 // CHECK: [[IV:%.+]] = load i32, i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID:[0-9]+]] 45 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 46 // CHECK-NEXT: [[CMP:%.+]] = icmp sle i32 [[IV]], [[UB_VAL]] 47 // CHECK-NEXT: br i1 [[CMP]], label %[[SIMPLE_LOOP1_BODY:.+]], label %[[SIMPLE_LOOP1_END:[^,]+]] 48 for (int i = 3; i < 32; i += 5) { 49 // CHECK: [[SIMPLE_LOOP1_BODY]] 50 // Start of body: calculate i from IV: 51 // CHECK: [[IV1_1:%.+]] = load i32, i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 52 // CHECK: [[CALC_I_1:%.+]] = mul nsw i32 [[IV1_1]], 5 53 // CHECK-NEXT: [[CALC_I_2:%.+]] = add nsw i32 3, [[CALC_I_1]] 54 // CHECK-NEXT: store i32 [[CALC_I_2]], i32* [[LC_I:.+]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 55 // ... loop body ... 56 // End of body: store into a[i]: 57 // CHECK: store float [[RESULT:%.+]], float* {{%.+}}{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 58 a[i] = b[i] * c[i] * d[i]; 59 // CHECK: [[IV1_2:%.+]] = load i32, i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 60 // CHECK-NEXT: [[ADD1_2:%.+]] = add nsw i32 [[IV1_2]], 1 61 // CHECK-NEXT: store i32 [[ADD1_2]], i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP1_ID]] 62 // br label %{{.+}}, !llvm.loop !{{.+}} 63 } 64 // CHECK: [[SIMPLE_LOOP1_END]] 65 // CHECK: call void @__kmpc_for_static_fini(%ident_t* {{.+}}, i32 %{{.+}}) 66 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 67 68 long long k = get_val(); 69 70 #pragma omp parallel for simd linear(k : 3) schedule(dynamic) 71 // CHECK: [[K0LOAD:%.+]] = load i64, i64* [[K_VAR:%[^,]+]] 72 // CHECK-NEXT: store i64 [[K0LOAD]], i64* [[LIN0:%[^,]+]] 73 74 // CHECK: call void @__kmpc_dispatch_init_4(%ident_t* {{.+}}, i32 %{{.+}}, i32 35, i32 0, i32 8, i32 1, i32 1) 75 // CHECK: [[NEXT:%.+]] = call i32 @__kmpc_dispatch_next_4(%ident_t* {{.+}}, i32 %{{.+}}, i32* %{{.+}}, i32* [[LB:%.+]], i32* [[UB:%.+]], i32* %{{.+}}) 76 // CHECK: [[COND:%.+]] = icmp ne i32 [[NEXT]], 0 77 // CHECK: br i1 [[COND]], label %[[CONT:.+]], label %[[END:.+]] 78 // CHECK: [[CONT]] 79 // CHECK: [[LB_VAL:%.+]] = load i32, i32* [[LB]], 80 // CHECK: store i32 [[LB_VAL]], i32* [[OMP_IV2:%[^,]+]], 81 82 // CHECK: [[IV2:%.+]] = load i32, i32* [[OMP_IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID:[0-9]+]] 83 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 84 // CHECK-NEXT: [[CMP2:%.+]] = icmp sle i32 [[IV2]], [[UB_VAL]] 85 // CHECK-NEXT: br i1 [[CMP2]], label %[[SIMPLE_LOOP2_BODY:.+]], label %[[SIMPLE_LOOP2_END:[^,]+]] 86 for (int i = 10; i > 1; i--) { 87 // CHECK: [[SIMPLE_LOOP2_BODY]] 88 // Start of body: calculate i from IV: 89 // CHECK: [[IV2_0:%.+]] = load i32, i32* [[OMP_IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 90 // FIXME: It is interesting, why the following "mul 1" was not constant folded? 91 // CHECK-NEXT: [[IV2_1:%.+]] = mul nsw i32 [[IV2_0]], 1 92 // CHECK-NEXT: [[LC_I_1:%.+]] = sub nsw i32 10, [[IV2_1]] 93 // CHECK-NEXT: store i32 [[LC_I_1]], i32* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 94 // 95 // CHECK-NEXT: [[LIN0_1:%.+]] = load i64, i64* [[LIN0]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 96 // CHECK-NEXT: [[IV2_2:%.+]] = load i32, i32* [[OMP_IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 97 // CHECK-NEXT: [[LIN_MUL1:%.+]] = mul nsw i32 [[IV2_2]], 3 98 // CHECK-NEXT: [[LIN_EXT1:%.+]] = sext i32 [[LIN_MUL1]] to i64 99 // CHECK-NEXT: [[LIN_ADD1:%.+]] = add nsw i64 [[LIN0_1]], [[LIN_EXT1]] 100 // Update of the privatized version of linear variable! 101 // CHECK-NEXT: store i64 [[LIN_ADD1]], i64* [[K_PRIVATIZED:%[^,]+]] 102 a[k]++; 103 k = k + 3; 104 // CHECK: [[IV2_2:%.+]] = load i32, i32* [[OMP_IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 105 // CHECK-NEXT: [[ADD2_2:%.+]] = add nsw i32 [[IV2_2]], 1 106 // CHECK-NEXT: store i32 [[ADD2_2]], i32* [[OMP_IV2]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP2_ID]] 107 // br label {{.+}}, !llvm.loop ![[SIMPLE_LOOP2_ID]] 108 } 109 // CHECK: [[SIMPLE_LOOP2_END]] 110 // 111 // Update linear vars after loop, as the loop was operating on a private version. 112 // CHECK: [[LIN0_2:%.+]] = load i64, i64* [[LIN0]] 113 // CHECK-NEXT: [[LIN_ADD2:%.+]] = add nsw i64 [[LIN0_2]], 27 114 // CHECK-NEXT: store i64 [[LIN_ADD2]], i64* %{{.+}} 115 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 116 117 int lin = 12; 118 #pragma omp parallel for simd linear(lin : get_val()), linear(g_ptr) 119 120 // Init linear private var. 121 // CHECK: [[LIN_VAR:%.+]] = load i32*, i32** % 122 // CHECK: [[LIN_LOAD:%.+]] = load i32, i32* [[LIN_VAR]] 123 // CHECK-NEXT: store i32 [[LIN_LOAD]], i32* [[LIN_START:%[^,]+]] 124 // Remember linear step. 125 // CHECK: [[CALL_VAL:%.+]] = invoke 126 // CHECK: store i64 [[CALL_VAL]], i64* [[LIN_STEP:%[^,]+]] 127 128 // CHECK: [[GLIN_LOAD:%.+]] = load double*, double** [[GLIN_VAR:%.+]], 129 // CHECK-NEXT: store double* [[GLIN_LOAD]], double** [[GLIN_START:%[^,]+]] 130 131 // CHECK: call void @__kmpc_for_static_init_8u(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i64* [[LB:%[^,]+]], i64* [[UB:%[^,]+]], i64* [[STRIDE:%[^,]+]], i64 1, i64 1) 132 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 133 // CHECK: [[CMP:%.+]] = icmp ugt i64 [[UB_VAL]], 3 134 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 135 // CHECK: [[TRUE]] 136 // CHECK: br label %[[SWITCH:[^,]+]] 137 // CHECK: [[FALSE]] 138 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 139 // CHECK: br label %[[SWITCH]] 140 // CHECK: [[SWITCH]] 141 // CHECK: [[UP:%.+]] = phi i64 [ 3, %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 142 // CHECK: store i64 [[UP]], i64* [[UB]], 143 // CHECK: [[LB_VAL:%.+]] = load i64, i64* [[LB]], 144 // CHECK: store i64 [[LB_VAL]], i64* [[OMP_IV3:%[^,]+]], 145 146 // CHECK: [[IV3:%.+]] = load i64, i64* [[OMP_IV3]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID:[0-9]+]] 147 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 148 // CHECK-NEXT: [[CMP3:%.+]] = icmp ule i64 [[IV3]], [[UB_VAL]] 149 // CHECK-NEXT: br i1 [[CMP3]], label %[[SIMPLE_LOOP3_BODY:.+]], label %[[SIMPLE_LOOP3_END:[^,]+]] 150 for (unsigned long long it = 2000; it >= 600; it-=400) { 151 // CHECK: [[SIMPLE_LOOP3_BODY]] 152 // Start of body: calculate it from IV: 153 // CHECK: [[IV3_0:%.+]] = load i64, i64* [[OMP_IV3]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 154 // CHECK-NEXT: [[LC_IT_1:%.+]] = mul i64 [[IV3_0]], 400 155 // CHECK-NEXT: [[LC_IT_2:%.+]] = sub i64 2000, [[LC_IT_1]] 156 // CHECK-NEXT: store i64 [[LC_IT_2]], i64* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 157 // 158 // Linear start and step are used to calculate current value of the linear variable. 159 // CHECK: [[LINSTART:.+]] = load i32, i32* [[LIN_START]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 160 // CHECK: [[LINSTEP:.+]] = load i64, i64* [[LIN_STEP]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 161 // CHECK-NOT: store i32 {{.+}}, i32* [[LIN_VAR]],{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 162 // CHECK: [[GLINSTART:.+]] = load double*, double** [[GLIN_START]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 163 // CHECK-NEXT: [[IV3_1:%.+]] = load i64, i64* [[OMP_IV3]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 164 // CHECK-NEXT: [[MUL:%.+]] = mul i64 [[IV3_1]], 1 165 // CHECK: [[GEP:%.+]] = getelementptr{{.*}}[[GLINSTART]] 166 // CHECK-NEXT: store double* [[GEP]], double** [[G_PTR_CUR:%[^,]+]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 167 *g_ptr++ = 0.0; 168 // CHECK: [[GEP_VAL:%.+]] = load double{{.*}}[[G_PTR_CUR]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 169 // CHECK: store double{{.*}}[[GEP_VAL]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 170 a[it + lin]++; 171 // CHECK: [[FLT_INC:%.+]] = fadd float 172 // CHECK-NEXT: store float [[FLT_INC]],{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 173 // CHECK: [[IV3_2:%.+]] = load i64, i64* [[OMP_IV3]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 174 // CHECK-NEXT: [[ADD3_2:%.+]] = add i64 [[IV3_2]], 1 175 // CHECK-NEXT: store i64 [[ADD3_2]], i64* [[OMP_IV3]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP3_ID]] 176 } 177 // CHECK: [[SIMPLE_LOOP3_END]] 178 // CHECK: call void @__kmpc_for_static_fini(%ident_t* {{.+}}, i32 %{{.+}}) 179 // 180 // Linear start and step are used to calculate final value of the linear variables. 181 // CHECK: [[LINSTART:.+]] = load i32, i32* [[LIN_START]] 182 // CHECK: [[LINSTEP:.+]] = load i64, i64* [[LIN_STEP]] 183 // CHECK: store i32 {{.+}}, i32* [[LIN_VAR]], 184 // CHECK: [[GLINSTART:.+]] = load double*, double** [[GLIN_START]] 185 // CHECK: store double* {{.*}}[[GLIN_VAR]] 186 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 187 188 #pragma omp parallel for simd 189 // CHECK: call void @__kmpc_for_static_init_4(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i32* [[LB:%[^,]+]], i32* [[UB:%[^,]+]], i32* [[STRIDE:%[^,]+]], i32 1, i32 1) 190 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 191 // CHECK: [[CMP:%.+]] = icmp sgt i32 [[UB_VAL]], 3 192 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 193 // CHECK: [[TRUE]] 194 // CHECK: br label %[[SWITCH:[^,]+]] 195 // CHECK: [[FALSE]] 196 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 197 // CHECK: br label %[[SWITCH]] 198 // CHECK: [[SWITCH]] 199 // CHECK: [[UP:%.+]] = phi i32 [ 3, %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 200 // CHECK: store i32 [[UP]], i32* [[UB]], 201 // CHECK: [[LB_VAL:%.+]] = load i32, i32* [[LB]], 202 // CHECK: store i32 [[LB_VAL]], i32* [[OMP_IV4:%[^,]+]], 203 204 // CHECK: [[IV4:%.+]] = load i32, i32* [[OMP_IV4]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID:[0-9]+]] 205 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID]] 206 // CHECK-NEXT: [[CMP4:%.+]] = icmp sle i32 [[IV4]], [[UB_VAL]] 207 // CHECK-NEXT: br i1 [[CMP4]], label %[[SIMPLE_LOOP4_BODY:.+]], label %[[SIMPLE_LOOP4_END:[^,]+]] 208 for (short it = 6; it <= 20; it-=-4) { 209 // CHECK: [[SIMPLE_LOOP4_BODY]] 210 // Start of body: calculate it from IV: 211 // CHECK: [[IV4_0:%.+]] = load i32, i32* [[OMP_IV4]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID]] 212 // CHECK-NEXT: [[LC_IT_1:%.+]] = mul nsw i32 [[IV4_0]], 4 213 // CHECK-NEXT: [[LC_IT_2:%.+]] = add nsw i32 6, [[LC_IT_1]] 214 // CHECK-NEXT: [[LC_IT_3:%.+]] = trunc i32 [[LC_IT_2]] to i16 215 // CHECK-NEXT: store i16 [[LC_IT_3]], i16* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID]] 216 217 // CHECK: [[IV4_2:%.+]] = load i32, i32* [[OMP_IV4]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID]] 218 // CHECK-NEXT: [[ADD4_2:%.+]] = add nsw i32 [[IV4_2]], 1 219 // CHECK-NEXT: store i32 [[ADD4_2]], i32* [[OMP_IV4]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP4_ID]] 220 } 221 // CHECK: [[SIMPLE_LOOP4_END]] 222 // CHECK: call void @__kmpc_for_static_fini(%ident_t* {{.+}}, i32 %{{.+}}) 223 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 224 225 #pragma omp parallel for simd 226 // CHECK: call void @__kmpc_for_static_init_4(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i32* [[LB:%[^,]+]], i32* [[UB:%[^,]+]], i32* [[STRIDE:%[^,]+]], i32 1, i32 1) 227 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 228 // CHECK: [[CMP:%.+]] = icmp sgt i32 [[UB_VAL]], 25 229 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 230 // CHECK: [[TRUE]] 231 // CHECK: br label %[[SWITCH:[^,]+]] 232 // CHECK: [[FALSE]] 233 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 234 // CHECK: br label %[[SWITCH]] 235 // CHECK: [[SWITCH]] 236 // CHECK: [[UP:%.+]] = phi i32 [ 25, %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 237 // CHECK: store i32 [[UP]], i32* [[UB]], 238 // CHECK: [[LB_VAL:%.+]] = load i32, i32* [[LB]], 239 // CHECK: store i32 [[LB_VAL]], i32* [[OMP_IV5:%[^,]+]], 240 241 // CHECK: [[IV5:%.+]] = load i32, i32* [[OMP_IV5]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID:[0-9]+]] 242 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID]] 243 // CHECK-NEXT: [[CMP5:%.+]] = icmp sle i32 [[IV5]], [[UB_VAL]] 244 // CHECK-NEXT: br i1 [[CMP5]], label %[[SIMPLE_LOOP5_BODY:.+]], label %[[SIMPLE_LOOP5_END:[^,]+]] 245 for (unsigned char it = 'z'; it >= 'a'; it+=-1) { 246 // CHECK: [[SIMPLE_LOOP5_BODY]] 247 // Start of body: calculate it from IV: 248 // CHECK: [[IV5_0:%.+]] = load i32, i32* [[OMP_IV5]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID]] 249 // CHECK-NEXT: [[IV5_1:%.+]] = mul nsw i32 [[IV5_0]], 1 250 // CHECK-NEXT: [[LC_IT_1:%.+]] = sub nsw i32 122, [[IV5_1]] 251 // CHECK-NEXT: [[LC_IT_2:%.+]] = trunc i32 [[LC_IT_1]] to i8 252 // CHECK-NEXT: store i8 [[LC_IT_2]], i8* {{.+}}, !llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID]] 253 254 // CHECK: [[IV5_2:%.+]] = load i32, i32* [[OMP_IV5]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID]] 255 // CHECK-NEXT: [[ADD5_2:%.+]] = add nsw i32 [[IV5_2]], 1 256 // CHECK-NEXT: store i32 [[ADD5_2]], i32* [[OMP_IV5]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP5_ID]] 257 } 258 // CHECK: [[SIMPLE_LOOP5_END]] 259 // CHECK: call void @__kmpc_for_static_fini(%ident_t* {{.+}}, i32 %{{.+}}) 260 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 261 262 // CHECK-NOT: mul i32 %{{.+}}, 10 263 #pragma omp parallel for simd 264 for (unsigned i=100; i<10; i+=10) { 265 } 266 267 int A; 268 { 269 A = -1; 270 #pragma omp parallel for simd lastprivate(A) 271 // CHECK: call void @__kmpc_for_static_init_8(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i64* [[LB:%[^,]+]], i64* [[UB:%[^,]+]], i64* [[STRIDE:%[^,]+]], i64 1, i64 1) 272 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 273 // CHECK: [[CMP:%.+]] = icmp sgt i64 [[UB_VAL]], 6 274 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 275 // CHECK: [[TRUE]] 276 // CHECK: br label %[[SWITCH:[^,]+]] 277 // CHECK: [[FALSE]] 278 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 279 // CHECK: br label %[[SWITCH]] 280 // CHECK: [[SWITCH]] 281 // CHECK: [[UP:%.+]] = phi i64 [ 6, %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 282 // CHECK: store i64 [[UP]], i64* [[UB]], 283 // CHECK: [[LB_VAL:%.+]] = load i64, i64* [[LB]], 284 // CHECK: store i64 [[LB_VAL]], i64* [[OMP_IV7:%[^,]+]], 285 286 // CHECK: br label %[[SIMD_LOOP7_COND:[^,]+]] 287 // CHECK: [[SIMD_LOOP7_COND]] 288 // CHECK-NEXT: [[IV7:%.+]] = load i64, i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID:[0-9]+]] 289 // CHECK-NEXT: [[UB_VAL:%.+]] = load i64, i64* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 290 // CHECK-NEXT: [[CMP7:%.+]] = icmp sle i64 [[IV7]], [[UB_VAL]] 291 // CHECK-NEXT: br i1 [[CMP7]], label %[[SIMPLE_LOOP7_BODY:.+]], label %[[SIMPLE_LOOP7_END:[^,]+]] 292 for (long long i = -10; i < 10; i += 3) { 293 // CHECK: [[SIMPLE_LOOP7_BODY]] 294 // Start of body: calculate i from IV: 295 // CHECK: [[IV7_0:%.+]] = load i64, i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 296 // CHECK-NEXT: [[LC_IT_1:%.+]] = mul nsw i64 [[IV7_0]], 3 297 // CHECK-NEXT: [[LC_IT_2:%.+]] = add nsw i64 -10, [[LC_IT_1]] 298 // CHECK-NEXT: store i64 [[LC_IT_2]], i64* [[LC:%[^,]+]],{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 299 // CHECK-NEXT: [[LC_VAL:%.+]] = load i64, i64* [[LC]]{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 300 // CHECK-NEXT: [[CONV:%.+]] = trunc i64 [[LC_VAL]] to i32 301 // CHECK-NEXT: store i32 [[CONV]], i32* [[A_PRIV:%[^,]+]],{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 302 A = i; 303 // CHECK: [[IV7_2:%.+]] = load i64, i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 304 // CHECK-NEXT: [[ADD7_2:%.+]] = add nsw i64 [[IV7_2]], 1 305 // CHECK-NEXT: store i64 [[ADD7_2]], i64* [[OMP_IV7]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP7_ID]] 306 } 307 // CHECK: [[SIMPLE_LOOP7_END]] 308 // CHECK: call void @__kmpc_for_static_fini(%ident_t* {{.+}}, i32 %{{.+}}) 309 // CHECK: load i32, i32* 310 // CHECK: icmp ne i32 %{{.+}}, 0 311 // CHECK: br i1 %{{.+}}, label 312 // CHECK: [[A_PRIV_VAL:%.+]] = load i32, i32* [[A_PRIV]], 313 // CHECK-NEXT: store i32 [[A_PRIV_VAL]], i32* %{{.+}}, 314 // CHECK-NEXT: br label 315 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 316 } 317 int R; 318 { 319 R = -1; 320 // CHECK: store i32 1, i32* [[R_PRIV:%[^,]+]], 321 #pragma omp parallel for simd reduction(*:R) 322 // CHECK: call void @__kmpc_for_static_init_8(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i64* [[LB:%[^,]+]], i64* [[UB:%[^,]+]], i64* [[STRIDE:%[^,]+]], i64 1, i64 1) 323 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 324 // CHECK: [[CMP:%.+]] = icmp sgt i64 [[UB_VAL]], 6 325 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 326 // CHECK: [[TRUE]] 327 // CHECK: br label %[[SWITCH:[^,]+]] 328 // CHECK: [[FALSE]] 329 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 330 // CHECK: br label %[[SWITCH]] 331 // CHECK: [[SWITCH]] 332 // CHECK: [[UP:%.+]] = phi i64 [ 6, %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 333 // CHECK: store i64 [[UP]], i64* [[UB]], 334 // CHECK: [[LB_VAL:%.+]] = load i64, i64* [[LB]], 335 // CHECK: store i64 [[LB_VAL]], i64* [[OMP_IV8:%[^,]+]], 336 337 // CHECK: br label %[[SIMD_LOOP8_COND:[^,]+]] 338 // CHECK: [[SIMD_LOOP8_COND]] 339 // CHECK-NEXT: [[IV8:%.+]] = load i64, i64* [[OMP_IV8]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID:[0-9]+]] 340 // CHECK-NEXT: [[UB_VAL:%.+]] = load i64, i64* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] 341 // CHECK-NEXT: [[CMP8:%.+]] = icmp sle i64 [[IV8]], [[UB_VAL]] 342 // CHECK-NEXT: br i1 [[CMP8]], label %[[SIMPLE_LOOP8_BODY:.+]], label %[[SIMPLE_LOOP8_END:[^,]+]] 343 for (long long i = -10; i < 10; i += 3) { 344 // CHECK: [[SIMPLE_LOOP8_BODY]] 345 // Start of body: calculate i from IV: 346 // CHECK: [[IV8_0:%.+]] = load i64, i64* [[OMP_IV8]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] 347 // CHECK-NEXT: [[LC_IT_1:%.+]] = mul nsw i64 [[IV8_0]], 3 348 // CHECK-NEXT: [[LC_IT_2:%.+]] = add nsw i64 -10, [[LC_IT_1]] 349 // CHECK-NEXT: store i64 [[LC_IT_2]], i64* [[LC:%[^,]+]],{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] 350 // CHECK-NEXT: [[LC_VAL:%.+]] = load i64, i64* [[LC]]{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] 351 // CHECK: store i32 %{{.+}}, i32* [[R_PRIV]],{{.+}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] 352 R *= i; 353 // CHECK: [[IV8_2:%.+]] = load i64, i64* [[OMP_IV8]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] 354 // CHECK-NEXT: [[ADD8_2:%.+]] = add nsw i64 [[IV8_2]], 1 355 // CHECK-NEXT: store i64 [[ADD8_2]], i64* [[OMP_IV8]]{{.*}}!llvm.mem.parallel_loop_access ![[SIMPLE_LOOP8_ID]] 356 } 357 // CHECK: [[SIMPLE_LOOP8_END]] 358 // CHECK: call void @__kmpc_for_static_fini(%ident_t* {{.+}}, i32 %{{.+}}) 359 // CHECK: call i32 @__kmpc_reduce_nowait( 360 // CHECK: [[R_PRIV_VAL:%.+]] = load i32, i32* [[R_PRIV]], 361 // CHECK: [[RED:%.+]] = mul nsw i32 %{{.+}}, [[R_PRIV_VAL]] 362 // CHECK-NEXT: store i32 [[RED]], i32* %{{.+}}, 363 // CHECK-NEXT: call void @__kmpc_end_reduce_nowait( 364 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 365 } 366 } 367 368 template <class T, unsigned K> T tfoo(T a) { return a + K; } 369 370 template <typename T, unsigned N> 371 int templ1(T a, T *z) { 372 #pragma omp parallel for simd collapse(N) 373 for (int i = 0; i < N * 2; i++) { 374 for (long long j = 0; j < (N + N + N + N); j += 2) { 375 z[i + j] = a + tfoo<T, N>(i + j); 376 } 377 } 378 return 0; 379 } 380 381 // Instatiation templ1<float,2> 382 // CHECK-LABEL: define {{.*i32}} @{{.*}}templ1{{.*}}(float {{.+}}, float* {{.+}}) 383 // CHECK: call void (%ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call( 384 void inst_templ1() { 385 float a; 386 float z[100]; 387 templ1<float,2> (a, z); 388 } 389 390 391 typedef int MyIdx; 392 393 class IterDouble { 394 double *Ptr; 395 public: 396 IterDouble operator++ () const { 397 IterDouble n; 398 n.Ptr = Ptr + 1; 399 return n; 400 } 401 bool operator < (const IterDouble &that) const { 402 return Ptr < that.Ptr; 403 } 404 double & operator *() const { 405 return *Ptr; 406 } 407 MyIdx operator - (const IterDouble &that) const { 408 return (MyIdx) (Ptr - that.Ptr); 409 } 410 IterDouble operator + (int Delta) { 411 IterDouble re; 412 re.Ptr = Ptr + Delta; 413 return re; 414 } 415 416 ///~IterDouble() {} 417 }; 418 419 // CHECK-LABEL: define {{.*void}} @{{.*}}iter_simple{{.*}} 420 void iter_simple(IterDouble ia, IterDouble ib, IterDouble ic) { 421 // 422 // Calculate number of iterations before the loop body. 423 // CHECK: [[DIFF1:%.+]] = invoke {{.*}}i32 @{{.*}}IterDouble{{.*}} 424 // CHECK: [[DIFF2:%.+]] = sub nsw i32 [[DIFF1]], 1 425 // CHECK-NEXT: [[DIFF3:%.+]] = add nsw i32 [[DIFF2]], 1 426 // CHECK-NEXT: [[DIFF4:%.+]] = sdiv i32 [[DIFF3]], 1 427 // CHECK-NEXT: [[DIFF5:%.+]] = sub nsw i32 [[DIFF4]], 1 428 // CHECK-NEXT: store i32 [[DIFF5]], i32* [[OMP_LAST_IT:%[^,]+]]{{.+}} 429 #pragma omp parallel for simd 430 431 // CHECK: call void @__kmpc_for_static_init_4(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i32* [[LB:%[^,]+]], i32* [[UB:%[^,]+]], i32* [[STRIDE:%[^,]+]], i32 1, i32 1) 432 // CHECK-DAG: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 433 // CHECK-DAG: [[OMP_LAST_IT_VAL:%.+]] = load i32, i32* [[OMP_LAST_IT]], 434 // CHECK: [[CMP:%.+]] = icmp sgt i32 [[UB_VAL]], [[OMP_LAST_IT_VAL]] 435 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 436 // CHECK: [[TRUE]] 437 // CHECK: [[OMP_LAST_IT_VAL:%.+]] = load i32, i32* [[OMP_LAST_IT]], 438 // CHECK: br label %[[SWITCH:[^,]+]] 439 // CHECK: [[FALSE]] 440 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 441 // CHECK: br label %[[SWITCH]] 442 // CHECK: [[SWITCH]] 443 // CHECK: [[UP:%.+]] = phi i32 [ [[OMP_LAST_IT_VAL]], %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 444 // CHECK: store i32 [[UP]], i32* [[UB]], 445 // CHECK: [[LB_VAL:%.+]] = load i32, i32* [[LB]], 446 // CHECK: store i32 [[LB_VAL]], i32* [[IT_OMP_IV:%[^,]+]], 447 448 // CHECK: [[IV:%.+]] = load i32, i32* [[IT_OMP_IV]]{{.+}} !llvm.mem.parallel_loop_access ![[ITER_LOOP_ID:[0-9]+]] 449 // CHECK-NEXT: [[UB_VAL:%.+]] = load i32, i32* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 450 // CHECK-NEXT: [[CMP:%.+]] = icmp sle i32 [[IV]], [[UB_VAL]] 451 // CHECK-NEXT: br i1 [[CMP]], label %[[IT_BODY:[^,]+]], label %[[IT_END:[^,]+]] 452 for (IterDouble i = ia; i < ib; ++i) { 453 // CHECK: [[IT_BODY]] 454 // Start of body: calculate i from index: 455 // CHECK: [[IV1:%.+]] = load i32, i32* [[IT_OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 456 // Call of operator+ (i, IV). 457 // CHECK: {{%.+}} = invoke {{.+}} @{{.*}}IterDouble{{.*}} 458 // ... loop body ... 459 *i = *ic * 0.5; 460 // Float multiply and save result. 461 // CHECK: [[MULR:%.+]] = fmul double {{%.+}}, 5.000000e-01 462 // CHECK-NEXT: invoke {{.+}} @{{.*}}IterDouble{{.*}} 463 // CHECK: store double [[MULR:%.+]], double* [[RESULT_ADDR:%.+]], !llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 464 ++ic; 465 // 466 // CHECK: [[IV2:%.+]] = load i32, i32* [[IT_OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 467 // CHECK-NEXT: [[ADD2:%.+]] = add nsw i32 [[IV2]], 1 468 // CHECK-NEXT: store i32 [[ADD2]], i32* [[IT_OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[ITER_LOOP_ID]] 469 // br label %{{.*}}, !llvm.loop ![[ITER_LOOP_ID]] 470 } 471 // CHECK: [[IT_END]] 472 // CHECK: call void @__kmpc_for_static_fini(%ident_t* {{.+}}, i32 %{{.+}}) 473 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 474 // CHECK: ret void 475 } 476 477 478 // CHECK-LABEL: define {{.*void}} @{{.*}}collapsed{{.*}} 479 void collapsed(float *a, float *b, float *c, float *d) { 480 int i; // outer loop counter 481 unsigned j; // middle loop couter, leads to unsigned icmp in loop header. 482 // k declared in the loop init below 483 short l; // inner loop counter 484 // CHECK: call void @__kmpc_for_static_init_4u(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i32* [[LB:%[^,]+]], i32* [[UB:%[^,]+]], i32* [[STRIDE:%[^,]+]], i32 1, i32 1) 485 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 486 // CHECK: [[CMP:%.+]] = icmp ugt i32 [[UB_VAL]], 119 487 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 488 // CHECK: [[TRUE]] 489 // CHECK: br label %[[SWITCH:[^,]+]] 490 // CHECK: [[FALSE]] 491 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]], 492 // CHECK: br label %[[SWITCH]] 493 // CHECK: [[SWITCH]] 494 // CHECK: [[UP:%.+]] = phi i32 [ 119, %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 495 // CHECK: store i32 [[UP]], i32* [[UB]], 496 // CHECK: [[LB_VAL:%.+]] = load i32, i32* [[LB]], 497 // CHECK: store i32 [[LB_VAL]], i32* [[OMP_IV:%[^,]+]], 498 // 499 #pragma omp parallel for simd collapse(4) 500 501 // CHECK: [[IV:%.+]] = load i32, i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID:[0-9]+]] 502 // CHECK: [[UB_VAL:%.+]] = load i32, i32* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 503 // CHECK-NEXT: [[CMP:%.+]] = icmp ule i32 [[IV]], [[UB_VAL]] 504 // CHECK-NEXT: br i1 [[CMP]], label %[[COLL1_BODY:[^,]+]], label %[[COLL1_END:[^,]+]] 505 for (i = 1; i < 3; i++) // 2 iterations 506 for (j = 2u; j < 5u; j++) //3 iterations 507 for (int k = 3; k <= 6; k++) // 4 iterations 508 for (l = 4; l < 9; ++l) // 5 iterations 509 { 510 // CHECK: [[COLL1_BODY]] 511 // Start of body: calculate i from index: 512 // CHECK: [[IV1:%.+]] = load i32, i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 513 // Calculation of the loop counters values. 514 // CHECK: [[CALC_I_1:%.+]] = udiv i32 [[IV1]], 60 515 // CHECK-NEXT: [[CALC_I_1_MUL1:%.+]] = mul i32 [[CALC_I_1]], 1 516 // CHECK-NEXT: [[CALC_I_2:%.+]] = add i32 1, [[CALC_I_1_MUL1]] 517 // CHECK-NEXT: store i32 [[CALC_I_2]], i32* [[LC_I:.+]] 518 // CHECK: [[IV1_2:%.+]] = load i32, i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 519 // CHECK-NEXT: [[CALC_J_1:%.+]] = udiv i32 [[IV1_2]], 20 520 // CHECK-NEXT: [[CALC_J_2:%.+]] = urem i32 [[CALC_J_1]], 3 521 // CHECK-NEXT: [[CALC_J_2_MUL1:%.+]] = mul i32 [[CALC_J_2]], 1 522 // CHECK-NEXT: [[CALC_J_3:%.+]] = add i32 2, [[CALC_J_2_MUL1]] 523 // CHECK-NEXT: store i32 [[CALC_J_3]], i32* [[LC_J:.+]] 524 // CHECK: [[IV1_3:%.+]] = load i32, i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 525 // CHECK-NEXT: [[CALC_K_1:%.+]] = udiv i32 [[IV1_3]], 5 526 // CHECK-NEXT: [[CALC_K_2:%.+]] = urem i32 [[CALC_K_1]], 4 527 // CHECK-NEXT: [[CALC_K_2_MUL1:%.+]] = mul i32 [[CALC_K_2]], 1 528 // CHECK-NEXT: [[CALC_K_3:%.+]] = add i32 3, [[CALC_K_2_MUL1]] 529 // CHECK-NEXT: store i32 [[CALC_K_3]], i32* [[LC_K:.+]] 530 // CHECK: [[IV1_4:%.+]] = load i32, i32* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 531 // CHECK-NEXT: [[CALC_L_1:%.+]] = urem i32 [[IV1_4]], 5 532 // CHECK-NEXT: [[CALC_L_1_MUL1:%.+]] = mul i32 [[CALC_L_1]], 1 533 // CHECK-NEXT: [[CALC_L_2:%.+]] = add i32 4, [[CALC_L_1_MUL1]] 534 // CHECK-NEXT: [[CALC_L_3:%.+]] = trunc i32 [[CALC_L_2]] to i16 535 // CHECK-NEXT: store i16 [[CALC_L_3]], i16* [[LC_L:.+]] 536 // ... loop body ... 537 // End of body: store into a[i]: 538 // CHECK: store float [[RESULT:%.+]], float* [[RESULT_ADDR:%.+]]{{.+}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 539 float res = b[j] * c[k]; 540 a[i] = res * d[l]; 541 // CHECK: [[IV2:%.+]] = load i32, i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 542 // CHECK-NEXT: [[ADD2:%.+]] = add i32 [[IV2]], 1 543 // CHECK-NEXT: store i32 [[ADD2]], i32* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[COLL1_LOOP_ID]] 544 // br label %{{[^,]+}}, !llvm.loop ![[COLL1_LOOP_ID]] 545 // CHECK: [[COLL1_END]] 546 } 547 // i,j,l are updated; k is not updated. 548 // CHECK: call void @__kmpc_for_static_fini(%ident_t* {{.+}}, i32 %{{.+}}) 549 // CHECK: store i32 3, i32* [[I:%[^,]+]] 550 // CHECK: store i32 5, i32* [[I:%[^,]+]] 551 // CHECK: store i16 9, i16* [[I:%[^,]+]] 552 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 553 // CHECK: ret void 554 } 555 556 extern char foo(); 557 extern double globalfloat; 558 559 // CHECK-LABEL: define {{.*void}} @{{.*}}widened{{.*}} 560 void widened(float *a, float *b, float *c, float *d) { 561 int i; // outer loop counter 562 short j; // inner loop counter 563 globalfloat = 1.0; 564 int localint = 1; 565 // CHECK: store double {{.+}}, double* [[GLOBALFLOAT:@.+]] 566 // Counter is widened to 64 bits. 567 // CHECK: [[MUL:%.+]] = mul nsw i64 2, %{{.+}} 568 // CHECK-NEXT: [[SUB:%.+]] = sub nsw i64 [[MUL]], 1 569 // CHECK-NEXT: store i64 [[SUB]], i64* [[OMP_LAST_IT:%[^,]+]], 570 // CHECK: call void @__kmpc_for_static_init_8(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i64* [[LB:%[^,]+]], i64* [[UB:%[^,]+]], i64* [[STRIDE:%[^,]+]], i64 1, i64 1) 571 // CHECK-DAG: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 572 // CHECK-DAG: [[OMP_LAST_IT_VAL:%.+]] = load i64, i64* [[OMP_LAST_IT]], 573 // CHECK: [[CMP:%.+]] = icmp sgt i64 [[UB_VAL]], [[OMP_LAST_IT_VAL]] 574 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 575 // CHECK: [[TRUE]] 576 // CHECK: [[OMP_LAST_IT_VAL:%.+]] = load i64, i64* [[OMP_LAST_IT]], 577 // CHECK: br label %[[SWITCH:[^,]+]] 578 // CHECK: [[FALSE]] 579 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 580 // CHECK: br label %[[SWITCH]] 581 // CHECK: [[SWITCH]] 582 // CHECK: [[UP:%.+]] = phi i64 [ [[OMP_LAST_IT_VAL]], %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 583 // CHECK: store i64 [[UP]], i64* [[UB]], 584 // CHECK: [[LB_VAL:%.+]] = load i64, i64* [[LB]], 585 // CHECK: store i64 [[LB_VAL]], i64* [[OMP_IV:%[^,]+]], 586 // 587 #pragma omp parallel for simd collapse(2) private(globalfloat, localint) 588 589 // CHECK: [[IV:%.+]] = load i64, i64* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID:[0-9]+]] 590 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 591 // CHECK-NEXT: [[CMP:%.+]] = icmp sle i64 [[IV]], [[UB_VAL]] 592 // CHECK-NEXT: br i1 [[CMP]], label %[[WIDE1_BODY:[^,]+]], label %[[WIDE1_END:[^,]+]] 593 for (i = 1; i < 3; i++) // 2 iterations 594 for (j = 0; j < foo(); j++) // foo() iterations 595 { 596 // CHECK: [[WIDE1_BODY]] 597 // Start of body: calculate i from index: 598 // CHECK: [[IV1:%.+]] = load i64, i64* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 599 // Calculation of the loop counters values... 600 // CHECK: store i32 {{[^,]+}}, i32* [[LC_I:.+]] 601 // CHECK: [[IV1_2:%.+]] = load i64, i64* [[OMP_IV]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 602 // CHECK: store i16 {{[^,]+}}, i16* [[LC_J:.+]] 603 // ... loop body ... 604 // 605 // Here we expect store into private double var, not global 606 // CHECK-NOT: store double {{.+}}, double* [[GLOBALFLOAT]] 607 globalfloat = (float)j/i; 608 float res = b[j] * c[j]; 609 // Store into a[i]: 610 // CHECK: store float [[RESULT:%.+]], float* [[RESULT_ADDR:%.+]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 611 a[i] = res * d[i]; 612 // Then there's a store into private var localint: 613 // CHECK: store i32 {{.+}}, i32* [[LOCALINT:%[^,]+]]{{.+}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 614 localint = (int)j; 615 // CHECK: [[IV2:%.+]] = load i64, i64* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 616 // CHECK-NEXT: [[ADD2:%.+]] = add nsw i64 [[IV2]], 1 617 // CHECK-NEXT: store i64 [[ADD2]], i64* [[OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[WIDE1_LOOP_ID]] 618 // 619 // br label %{{[^,]+}}, !llvm.loop ![[WIDE1_LOOP_ID]] 620 // CHECK: [[WIDE1_END]] 621 } 622 // i,j are updated. 623 // CHECK: store i32 3, i32* [[I:%[^,]+]] 624 // CHECK: store i16 625 // 626 // Here we expect store into original localint, not its privatized version. 627 // CHECK-NOT: store i32 {{.+}}, i32* [[LOCALINT]] 628 localint = (int)j; 629 // CHECK: ret void 630 } 631 632 // CHECK: call void @__kmpc_for_static_init_8(%ident_t* {{[^,]+}}, i32 %{{[^,]+}}, i32 34, i32* %{{[^,]+}}, i64* [[LB:%[^,]+]], i64* [[UB:%[^,]+]], i64* [[STRIDE:%[^,]+]], i64 1, i64 1) 633 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 634 // CHECK: [[CMP:%.+]] = icmp sgt i64 [[UB_VAL]], 15 635 // CHECK: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:[^,]+]] 636 // CHECK: [[TRUE]] 637 // CHECK: br label %[[SWITCH:[^,]+]] 638 // CHECK: [[FALSE]] 639 // CHECK: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 640 // CHECK: br label %[[SWITCH]] 641 // CHECK: [[SWITCH]] 642 // CHECK: [[UP:%.+]] = phi i64 [ 15, %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 643 // CHECK: store i64 [[UP]], i64* [[UB]], 644 // CHECK: [[LB_VAL:%.+]] = load i64, i64* [[LB]], 645 // CHECK: store i64 [[LB_VAL]], i64* [[T1_OMP_IV:%[^,]+]], 646 647 // ... 648 // CHECK: [[IV:%.+]] = load i64, i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID:[0-9]+]] 649 // CHECK-NEXT: [[UB_VAL:%.+]] = load i64, i64* [[UB]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 650 // CHECK-NEXT: [[CMP1:%.+]] = icmp sle i64 [[IV]], [[UB_VAL]] 651 // CHECK-NEXT: br i1 [[CMP1]], label %[[T1_BODY:.+]], label %[[T1_END:[^,]+]] 652 // CHECK: [[T1_BODY]] 653 // Loop counters i and j updates: 654 // CHECK: [[IV1:%.+]] = load i64, i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 655 // CHECK-NEXT: [[I_1:%.+]] = sdiv i64 [[IV1]], 4 656 // CHECK-NEXT: [[I_1_MUL1:%.+]] = mul nsw i64 [[I_1]], 1 657 // CHECK-NEXT: [[I_1_ADD0:%.+]] = add nsw i64 0, [[I_1_MUL1]] 658 // CHECK-NEXT: [[I_2:%.+]] = trunc i64 [[I_1_ADD0]] to i32 659 // CHECK-NEXT: store i32 [[I_2]], i32* {{%.+}}{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 660 // CHECK: [[IV2:%.+]] = load i64, i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 661 // CHECK-NEXT: [[J_1:%.+]] = srem i64 [[IV2]], 4 662 // CHECK-NEXT: [[J_2:%.+]] = mul nsw i64 [[J_1]], 2 663 // CHECK-NEXT: [[J_2_ADD0:%.+]] = add nsw i64 0, [[J_2]] 664 // CHECK-NEXT: store i64 [[J_2_ADD0]], i64* {{%.+}}{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 665 // simd.for.inc: 666 // CHECK: [[IV3:%.+]] = load i64, i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 667 // CHECK-NEXT: [[INC:%.+]] = add nsw i64 [[IV3]], 1 668 // CHECK-NEXT: store i64 [[INC]], i64* [[T1_OMP_IV]]{{.*}}!llvm.mem.parallel_loop_access ![[T1_ID]] 669 // CHECK-NEXT: br label {{%.+}} 670 // CHECK: [[T1_END]] 671 // CHECK: call void @__kmpc_for_static_fini(%ident_t* {{.+}}, i32 %{{.+}}) 672 // CHECK: call void @__kmpc_barrier(%ident_t* {{.+}}, i32 %{{.+}}) 673 // CHECK: ret void 674 // 675 // TERM_DEBUG-LABEL: bar 676 int bar() {return 0;}; 677 678 // TERM_DEBUG-LABEL: parallel_simd 679 void parallel_simd(float *a) { 680 #pragma omp parallel for simd 681 // TERM_DEBUG-NOT: __kmpc_global_thread_num 682 // TERM_DEBUG: invoke i32 {{.*}}bar{{.*}}() 683 // TERM_DEBUG: unwind label %[[TERM_LPAD:.+]], 684 // TERM_DEBUG-NOT: __kmpc_global_thread_num 685 // TERM_DEBUG: [[TERM_LPAD]] 686 // TERM_DEBUG: call void @__clang_call_terminate 687 // TERM_DEBUG: unreachable 688 for (unsigned i = 131071; i <= 2147483647; i += 127) 689 a[i] += bar(); 690 } 691 // TERM_DEBUG: !{{[0-9]+}} = !DILocation(line: [[@LINE-11]], 692 #endif // HEADER 693 694