1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2 4 5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 6 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 7 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 10 11 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -O1 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 13 14 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK7 15 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 16 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK8 17 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9 18 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -O1 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10 19 // expected-no-diagnostics 20 21 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 23 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 24 // RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK13 25 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 26 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK14 27 #ifndef HEADER 28 #define HEADER 29 30 #ifndef OMP5 31 32 void with_var_schedule() { 33 double a = 5; 34 35 #pragma omp parallel for schedule(static, char(a)) private(a) 36 for (unsigned long long i = 1; i < 2 + a; ++i) { 37 } 38 } 39 40 void without_schedule_clause(float *a, float *b, float *c, float *d) { 41 #pragma omp parallel for 42 // UB = min(UB, GlobalUB) 43 // Loop header 44 for (int i = 33; i < 32000000; i += 7) { 45 // Start of body: calculate i from IV: 46 // ... loop body ... 47 // End of body: store into a[i]: 48 a[i] = b[i] * c[i] * d[i]; 49 } 50 } 51 52 void static_not_chunked(float *a, float *b, float *c, float *d) { 53 #pragma omp parallel for schedule(static) 54 // UB = min(UB, GlobalUB) 55 // Loop header 56 for (int i = 32000000; i > 33; i += -7) { 57 // Start of body: calculate i from IV: 58 // ... loop body ... 59 // End of body: store into a[i]: 60 a[i] = b[i] * c[i] * d[i]; 61 } 62 } 63 64 void static_chunked(float *a, float *b, float *c, float *d) { 65 #pragma omp parallel for schedule(static, 5) 66 // UB = min(UB, GlobalUB) 67 68 // Outer loop header 69 70 // Loop header 71 for (unsigned i = 131071; i <= 2147483647; i += 127) { 72 // Start of body: calculate i from IV: 73 // ... loop body ... 74 // End of body: store into a[i]: 75 a[i] = b[i] * c[i] * d[i]; 76 } 77 // Update the counters, adding stride 78 79 } 80 81 void dynamic1(float *a, float *b, float *c, float *d) { 82 #pragma omp parallel for schedule(dynamic) 83 84 // Loop header 85 86 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 87 // Start of body: calculate i from IV: 88 // ... loop body ... 89 // End of body: store into a[i]: 90 a[i] = b[i] * c[i] * d[i]; 91 } 92 } 93 94 void guided7(float *a, float *b, float *c, float *d) { 95 #pragma omp parallel for schedule(guided, 7) 96 97 // Loop header 98 99 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 100 // Start of body: calculate i from IV: 101 // ... loop body ... 102 // End of body: store into a[i]: 103 a[i] = b[i] * c[i] * d[i]; 104 } 105 } 106 107 void test_auto(float *a, float *b, float *c, float *d) { 108 unsigned int x = 0; 109 unsigned int y = 0; 110 #pragma omp parallel for schedule(auto) collapse(2) 111 112 // Loop header 113 114 // FIXME: When the iteration count of some nested loop is not a known constant, 115 // we should pre-calculate it, like we do for the total number of iterations! 116 for (char i = static_cast<char>(y); i <= '9'; ++i) 117 for (x = 11; x > 0; --x) { 118 // Start of body: indices are calculated from IV: 119 // ... loop body ... 120 // End of body: store into a[i]: 121 a[i] = b[i] * c[i] * d[i]; 122 } 123 } 124 125 void runtime(float *a, float *b, float *c, float *d) { 126 int x = 0; 127 #pragma omp parallel for collapse(2) schedule(runtime) 128 129 // Loop header 130 131 for (unsigned char i = '0' ; i <= '9'; ++i) 132 for (x = -10; x < 10; ++x) { 133 // Start of body: indices are calculated from IV: 134 // ... loop body ... 135 // End of body: store into a[i]: 136 a[i] = b[i] * c[i] * d[i]; 137 } 138 } 139 140 int foo() { extern void mayThrow(); mayThrow(); return 0; }; 141 142 void parallel_for(float *a, const int n) { 143 float arr[n]; 144 #pragma omp parallel for schedule(static, 5) private(arr) default(none) firstprivate(n) shared(a) 145 for (unsigned i = 131071; i <= 2147483647; i += 127) 146 a[i] += foo() + arr[i] + n; 147 } 148 // Check source line corresponds to "#pragma omp parallel for schedule(static, 5)" above: 149 150 #else // OMP5 151 int increment () { 152 #pragma omp for 153 // Determine UB = min(UB, GlobalUB) 154 155 // Loop header 156 157 for (int i = 0 ; i != 5; ++i) 158 // Start of body: calculate i from IV: 159 ; 160 return 0; 161 } 162 163 int decrement_nowait () { 164 #pragma omp for nowait 165 // Determine UB = min(UB, GlobalUB) 166 167 // Loop header 168 for (int j = 5 ; j != 0; --j) 169 // Start of body: calculate i from IV: 170 ; 171 return 0; 172 } 173 174 void range_for_single() { 175 int arr[10] = {0}; 176 #pragma omp parallel for 177 for (auto &a : arr) 178 (void)a; 179 } 180 181 182 // __range = arr; 183 184 // __end = end(_range); 185 186 187 // calculate number of elements. 188 189 // __begin = begin(range); 190 191 // __begin >= __end ? goto then : goto exit; 192 193 194 // lb = 0; 195 196 // ub = number of elements 197 198 // stride = 1; 199 200 // is_last = 0; 201 202 // loop. 203 204 // ub = (ub > number_of_elems ? number_of_elems : ub); 205 206 207 208 // OMP%: store i64 [[MIN]], i64* [[UB]], 209 210 // iv = lb; 211 212 // goto loop; 213 // loop: 214 215 216 // iv <= ub ? goto body : goto end; 217 218 // body: 219 // __begin = begin(arr) + iv * 1; 220 221 // a = *__begin; 222 223 // (void)a; 224 225 // iv += 1; 226 227 // goto loop; 228 229 // end: 230 // exit: 231 232 void range_for_collapsed() { 233 int arr[10] = {0}; 234 #pragma omp parallel for collapse(2) 235 for (auto &a : arr) 236 for (auto b : arr) 237 a = b; 238 } 239 #endif // OMP5 240 241 #endif // HEADER 242 243 // CHECK1-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 244 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 245 // CHECK1-NEXT: entry: 246 // CHECK1-NEXT: [[A:%.*]] = alloca double, align 8 247 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 248 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 249 // CHECK1-NEXT: store double 5.000000e+00, double* [[A]], align 8 250 // CHECK1-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 251 // CHECK1-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 252 // CHECK1-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 253 // CHECK1-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 254 // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 255 // CHECK1-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 256 // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 257 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]]) 258 // CHECK1-NEXT: ret void 259 // 260 // 261 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 262 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 263 // CHECK1-NEXT: entry: 264 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 265 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 266 // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 267 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 268 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 269 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 270 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 271 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 272 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 273 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 274 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 275 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[A:%.*]] = alloca double, align 8 277 // CHECK1-NEXT: [[I5:%.*]] = alloca i64, align 8 278 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 279 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 280 // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 281 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 282 // CHECK1-NEXT: [[TMP0:%.*]] = load double, double* undef, align 8 283 // CHECK1-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]] 284 // CHECK1-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 285 // CHECK1-NEXT: [[TMP1:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 286 // CHECK1-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00 287 // CHECK1-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 288 // CHECK1-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64 289 // CHECK1-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1 290 // CHECK1-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8 291 // CHECK1-NEXT: store i64 1, i64* [[I]], align 8 292 // CHECK1-NEXT: [[TMP2:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 293 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] 294 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 295 // CHECK1: omp.precond.then: 296 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 297 // CHECK1-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 298 // CHECK1-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 299 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 300 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 301 // CHECK1-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8 302 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 303 // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 304 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 305 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) 306 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 307 // CHECK1: omp.dispatch.cond: 308 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 309 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 310 // CHECK1-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]] 311 // CHECK1-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 312 // CHECK1: cond.true: 313 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 314 // CHECK1-NEXT: br label [[COND_END:%.*]] 315 // CHECK1: cond.false: 316 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 317 // CHECK1-NEXT: br label [[COND_END]] 318 // CHECK1: cond.end: 319 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 320 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 321 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 322 // CHECK1-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 323 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 324 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 325 // CHECK1-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1 326 // CHECK1-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]] 327 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 328 // CHECK1: omp.dispatch.body: 329 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 330 // CHECK1: omp.inner.for.cond: 331 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 332 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 333 // CHECK1-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1 334 // CHECK1-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]] 335 // CHECK1-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 336 // CHECK1: omp.inner.for.body: 337 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 338 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1 339 // CHECK1-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]] 340 // CHECK1-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8 341 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 342 // CHECK1: omp.body.continue: 343 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 344 // CHECK1: omp.inner.for.inc: 345 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 346 // CHECK1-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1 347 // CHECK1-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8 348 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 349 // CHECK1: omp.inner.for.end: 350 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 351 // CHECK1: omp.dispatch.inc: 352 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 353 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 354 // CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]] 355 // CHECK1-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8 356 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 357 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 358 // CHECK1-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]] 359 // CHECK1-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8 360 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 361 // CHECK1: omp.dispatch.end: 362 // CHECK1-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 363 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 364 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 365 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 366 // CHECK1: omp.precond.end: 367 // CHECK1-NEXT: ret void 368 // 369 // 370 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 371 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 372 // CHECK1-NEXT: entry: 373 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 374 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 375 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 376 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 377 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 378 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 379 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 380 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 381 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 382 // CHECK1-NEXT: ret void 383 // 384 // 385 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 386 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 387 // CHECK1-NEXT: entry: 388 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 389 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 390 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 391 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 392 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 393 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 394 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 395 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 396 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 397 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 398 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 399 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 400 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 401 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 402 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 403 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 404 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 405 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 406 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 407 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 408 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 409 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 410 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 411 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 412 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 413 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 414 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 415 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 416 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 417 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 418 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 419 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 420 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 421 // CHECK1: cond.true: 422 // CHECK1-NEXT: br label [[COND_END:%.*]] 423 // CHECK1: cond.false: 424 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 425 // CHECK1-NEXT: br label [[COND_END]] 426 // CHECK1: cond.end: 427 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 428 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 429 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 430 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 431 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 432 // CHECK1: omp.inner.for.cond: 433 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 434 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 435 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 436 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 437 // CHECK1: omp.inner.for.body: 438 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 439 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 440 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 441 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 442 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 443 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 444 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 445 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 446 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 447 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 448 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 449 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 450 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 451 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 452 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 453 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 454 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 455 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 456 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 457 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 458 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 459 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 460 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 461 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 462 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 463 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 464 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 465 // CHECK1: omp.body.continue: 466 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 467 // CHECK1: omp.inner.for.inc: 468 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 469 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 470 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 471 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 472 // CHECK1: omp.inner.for.end: 473 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 474 // CHECK1: omp.loop.exit: 475 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 476 // CHECK1-NEXT: ret void 477 // 478 // 479 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 480 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 481 // CHECK1-NEXT: entry: 482 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 483 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 484 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 485 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 486 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 487 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 488 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 489 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 490 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 491 // CHECK1-NEXT: ret void 492 // 493 // 494 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 495 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 496 // CHECK1-NEXT: entry: 497 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 498 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 499 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 500 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 501 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 502 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 503 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 504 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 505 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 506 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 507 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 508 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 509 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 510 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 511 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 512 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 513 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 514 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 515 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 516 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 517 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 518 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 519 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 520 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 521 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 522 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 523 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 524 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 525 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 526 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 527 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 528 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 529 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 530 // CHECK1: cond.true: 531 // CHECK1-NEXT: br label [[COND_END:%.*]] 532 // CHECK1: cond.false: 533 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 534 // CHECK1-NEXT: br label [[COND_END]] 535 // CHECK1: cond.end: 536 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 537 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 538 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 539 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 540 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 541 // CHECK1: omp.inner.for.cond: 542 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 543 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 544 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 545 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 546 // CHECK1: omp.inner.for.body: 547 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 548 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 549 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 550 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 551 // CHECK1-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 552 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 553 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 554 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 555 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 556 // CHECK1-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 557 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 558 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 559 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 560 // CHECK1-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 561 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 562 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 563 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 564 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 565 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 566 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 567 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 568 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 569 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 570 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 571 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 572 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 573 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 574 // CHECK1: omp.body.continue: 575 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 576 // CHECK1: omp.inner.for.inc: 577 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 578 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 579 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 580 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 581 // CHECK1: omp.inner.for.end: 582 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 583 // CHECK1: omp.loop.exit: 584 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 585 // CHECK1-NEXT: ret void 586 // 587 // 588 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 589 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 590 // CHECK1-NEXT: entry: 591 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 592 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 593 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 594 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 595 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 596 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 597 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 598 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 599 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 600 // CHECK1-NEXT: ret void 601 // 602 // 603 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 604 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 605 // CHECK1-NEXT: entry: 606 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 607 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 608 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 609 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 610 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 611 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 612 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 613 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 614 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 615 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 616 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 617 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 618 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 619 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 620 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 621 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 622 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 623 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 624 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 625 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 626 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 627 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 628 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 629 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 630 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 631 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 632 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 633 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 634 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 635 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 636 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 637 // CHECK1: omp.dispatch.cond: 638 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 639 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 640 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 641 // CHECK1: cond.true: 642 // CHECK1-NEXT: br label [[COND_END:%.*]] 643 // CHECK1: cond.false: 644 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 645 // CHECK1-NEXT: br label [[COND_END]] 646 // CHECK1: cond.end: 647 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 648 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 649 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 650 // CHECK1-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 651 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 652 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 653 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 654 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 655 // CHECK1: omp.dispatch.body: 656 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 657 // CHECK1: omp.inner.for.cond: 658 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 659 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 660 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 661 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 662 // CHECK1: omp.inner.for.body: 663 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 664 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 665 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 666 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 667 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8 668 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 669 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 670 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 671 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 672 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8 673 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 674 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 675 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 676 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4 677 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 678 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8 679 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 680 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 681 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 682 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4 683 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 684 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8 685 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 686 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 687 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 688 // CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 689 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 690 // CHECK1: omp.body.continue: 691 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 692 // CHECK1: omp.inner.for.inc: 693 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 694 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 695 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 696 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 697 // CHECK1: omp.inner.for.end: 698 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 699 // CHECK1: omp.dispatch.inc: 700 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 701 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 702 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 703 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 704 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 705 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 706 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 707 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 708 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 709 // CHECK1: omp.dispatch.end: 710 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 711 // CHECK1-NEXT: ret void 712 // 713 // 714 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 715 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 716 // CHECK1-NEXT: entry: 717 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 718 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 719 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 720 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 721 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 722 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 723 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 724 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 725 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 726 // CHECK1-NEXT: ret void 727 // 728 // 729 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 730 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 731 // CHECK1-NEXT: entry: 732 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 733 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 734 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 735 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 736 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 737 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 738 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 739 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 740 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 741 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 742 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 743 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 744 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 745 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 746 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 747 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 748 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 749 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 750 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 751 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 752 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 753 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 754 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 755 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 756 // CHECK1-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 757 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 758 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 759 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 760 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 761 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1) 762 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 763 // CHECK1: omp.dispatch.cond: 764 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 765 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 766 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 767 // CHECK1: omp.dispatch.body: 768 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 769 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 770 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 771 // CHECK1: omp.inner.for.cond: 772 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 773 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !4 774 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 775 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 776 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 777 // CHECK1: omp.inner.for.body: 778 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 779 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 780 // CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 781 // CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !4 782 // CHECK1-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !4 783 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 784 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 785 // CHECK1-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !4 786 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !4 787 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 788 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 789 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !4 790 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 791 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !4 792 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 793 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 794 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !4 795 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 796 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !4 797 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 798 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 799 // CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !4 800 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 801 // CHECK1: omp.body.continue: 802 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 803 // CHECK1: omp.inner.for.inc: 804 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 805 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 806 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 807 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 808 // CHECK1: omp.inner.for.end: 809 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 810 // CHECK1: omp.dispatch.inc: 811 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 812 // CHECK1: omp.dispatch.end: 813 // CHECK1-NEXT: ret void 814 // 815 // 816 // CHECK1-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 817 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 818 // CHECK1-NEXT: entry: 819 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 820 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 821 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 822 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 823 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 824 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 825 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 826 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 827 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 828 // CHECK1-NEXT: ret void 829 // 830 // 831 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 832 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 833 // CHECK1-NEXT: entry: 834 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 835 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 836 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 837 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 838 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 839 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 840 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 841 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 842 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 843 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 844 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 845 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 846 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 847 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 848 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 849 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 850 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 851 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 852 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 853 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 854 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 855 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 856 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 857 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 858 // CHECK1-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 859 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 860 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 861 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 862 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 863 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7) 864 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 865 // CHECK1: omp.dispatch.cond: 866 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 867 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 868 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 869 // CHECK1: omp.dispatch.body: 870 // CHECK1-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 871 // CHECK1-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 872 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 873 // CHECK1: omp.inner.for.cond: 874 // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 875 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !7 876 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 877 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 878 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 879 // CHECK1: omp.inner.for.body: 880 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 881 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 882 // CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 883 // CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !7 884 // CHECK1-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !7 885 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 886 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 887 // CHECK1-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !7 888 // CHECK1-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !7 889 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 890 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 891 // CHECK1-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !7 892 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 893 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !7 894 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 895 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 896 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !7 897 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 898 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !7 899 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 900 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 901 // CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !7 902 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 903 // CHECK1: omp.body.continue: 904 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 905 // CHECK1: omp.inner.for.inc: 906 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 907 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 908 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 909 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 910 // CHECK1: omp.inner.for.end: 911 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 912 // CHECK1: omp.dispatch.inc: 913 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 914 // CHECK1: omp.dispatch.end: 915 // CHECK1-NEXT: ret void 916 // 917 // 918 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 919 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 920 // CHECK1-NEXT: entry: 921 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 922 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 923 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 924 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 925 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 926 // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 927 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 928 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 929 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 930 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 931 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 932 // CHECK1-NEXT: store i32 0, i32* [[Y]], align 4 933 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[Y]], float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 934 // CHECK1-NEXT: ret void 935 // 936 // 937 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 938 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 939 // CHECK1-NEXT: entry: 940 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 941 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 942 // CHECK1-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 943 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 944 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 945 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 946 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 947 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 948 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 949 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 950 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 951 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 952 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 953 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 954 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 955 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 956 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 957 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 958 // CHECK1-NEXT: [[I7:%.*]] = alloca i8, align 1 959 // CHECK1-NEXT: [[X8:%.*]] = alloca i32, align 4 960 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 961 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 962 // CHECK1-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 963 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 964 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 965 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 966 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 967 // CHECK1-NEXT: [[TMP0:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 968 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[A_ADDR]], align 8 969 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[B_ADDR]], align 8 970 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[C_ADDR]], align 8 971 // CHECK1-NEXT: [[TMP4:%.*]] = load float**, float*** [[D_ADDR]], align 8 972 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 973 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8 974 // CHECK1-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 975 // CHECK1-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 976 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32 977 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 978 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 979 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 980 // CHECK1-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 981 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 982 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 983 // CHECK1-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 984 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 985 // CHECK1-NEXT: store i8 [[TMP7]], i8* [[I]], align 1 986 // CHECK1-NEXT: store i32 11, i32* [[X]], align 4 987 // CHECK1-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 988 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32 989 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 990 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 991 // CHECK1: omp.precond.then: 992 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 993 // CHECK1-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 994 // CHECK1-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 995 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 996 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 997 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 998 // CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 999 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 1000 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1) 1001 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1002 // CHECK1: omp.dispatch.cond: 1003 // CHECK1-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1004 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 1005 // CHECK1-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1006 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 1007 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1008 // CHECK1: omp.dispatch.body: 1009 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1010 // CHECK1-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 1011 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1012 // CHECK1: omp.inner.for.cond: 1013 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 1014 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !10 1015 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 1016 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1017 // CHECK1: omp.inner.for.body: 1018 // CHECK1-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !10 1019 // CHECK1-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64 1020 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 1021 // CHECK1-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11 1022 // CHECK1-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 1023 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 1024 // CHECK1-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 1025 // CHECK1-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !10 1026 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 1027 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 1028 // CHECK1-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11 1029 // CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 1030 // CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]] 1031 // CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 1032 // CHECK1-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 1033 // CHECK1-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 1034 // CHECK1-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !10 1035 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !10 1036 // CHECK1-NEXT: [[TMP24:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 1037 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64 1038 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM]] 1039 // CHECK1-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 1040 // CHECK1-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !10 1041 // CHECK1-NEXT: [[TMP27:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 1042 // CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64 1043 // CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM21]] 1044 // CHECK1-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !10 1045 // CHECK1-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]] 1046 // CHECK1-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !10 1047 // CHECK1-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 1048 // CHECK1-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64 1049 // CHECK1-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM24]] 1050 // CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !10 1051 // CHECK1-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]] 1052 // CHECK1-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !10 1053 // CHECK1-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 1054 // CHECK1-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64 1055 // CHECK1-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM27]] 1056 // CHECK1-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !10 1057 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1058 // CHECK1: omp.body.continue: 1059 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1060 // CHECK1: omp.inner.for.inc: 1061 // CHECK1-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 1062 // CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1 1063 // CHECK1-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 1064 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 1065 // CHECK1: omp.inner.for.end: 1066 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1067 // CHECK1: omp.dispatch.inc: 1068 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1069 // CHECK1: omp.dispatch.end: 1070 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 1071 // CHECK1: omp.precond.end: 1072 // CHECK1-NEXT: ret void 1073 // 1074 // 1075 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 1076 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1077 // CHECK1-NEXT: entry: 1078 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1079 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1080 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1081 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1082 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 1083 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1084 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1085 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1086 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1087 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 1088 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1089 // CHECK1-NEXT: ret void 1090 // 1091 // 1092 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 1093 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1094 // CHECK1-NEXT: entry: 1095 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1096 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1097 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1098 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1099 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1100 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1101 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1102 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1103 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1104 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1105 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1106 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1107 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1108 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 1109 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 1110 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1111 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1112 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1113 // CHECK1-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1114 // CHECK1-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1115 // CHECK1-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1116 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1117 // CHECK1-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1118 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1119 // CHECK1-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1120 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1121 // CHECK1-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 1122 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1123 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1124 // CHECK1-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1125 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1126 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1) 1127 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1128 // CHECK1: omp.dispatch.cond: 1129 // CHECK1-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1130 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 1131 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1132 // CHECK1: omp.dispatch.body: 1133 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1134 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 1135 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1136 // CHECK1: omp.inner.for.cond: 1137 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 1138 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 1139 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 1140 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1141 // CHECK1: omp.inner.for.body: 1142 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 1143 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20 1144 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1145 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 1146 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 1147 // CHECK1-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !13 1148 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 1149 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 1150 // CHECK1-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20 1151 // CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 1152 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]] 1153 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 1154 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 1155 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !13 1156 // CHECK1-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !13 1157 // CHECK1-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 1158 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64 1159 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 1160 // CHECK1-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 1161 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !13 1162 // CHECK1-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 1163 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64 1164 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM6]] 1165 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !13 1166 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]] 1167 // CHECK1-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !13 1168 // CHECK1-NEXT: [[TMP20:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 1169 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64 1170 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM9]] 1171 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !13 1172 // CHECK1-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]] 1173 // CHECK1-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !13 1174 // CHECK1-NEXT: [[TMP23:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 1175 // CHECK1-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64 1176 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM12]] 1177 // CHECK1-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !13 1178 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1179 // CHECK1: omp.body.continue: 1180 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1181 // CHECK1: omp.inner.for.inc: 1182 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 1183 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1 1184 // CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 1185 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 1186 // CHECK1: omp.inner.for.end: 1187 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1188 // CHECK1: omp.dispatch.inc: 1189 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1190 // CHECK1: omp.dispatch.end: 1191 // CHECK1-NEXT: ret void 1192 // 1193 // 1194 // CHECK1-LABEL: define {{[^@]+}}@_Z3foov 1195 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 1196 // CHECK1-NEXT: entry: 1197 // CHECK1-NEXT: call void @_Z8mayThrowv() 1198 // CHECK1-NEXT: ret i32 0 1199 // 1200 // 1201 // CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 1202 // CHECK1-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { 1203 // CHECK1-NEXT: entry: 1204 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1205 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1206 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1207 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1208 // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 1209 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1210 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1211 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1212 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1213 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1214 // CHECK1-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 1215 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 1216 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1217 // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 1218 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 1219 // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 1220 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 1221 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) 1222 // CHECK1-NEXT: [[TMP5:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1223 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]) 1224 // CHECK1-NEXT: ret void 1225 // 1226 // 1227 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 1228 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 1229 // CHECK1-NEXT: entry: 1230 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1231 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1232 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1233 // CHECK1-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 1234 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 1235 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1236 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1237 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1238 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1239 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1240 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1241 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1242 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1243 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1244 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1245 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1246 // CHECK1-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1247 // CHECK1-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 1248 // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 1249 // CHECK1-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1250 // CHECK1-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 1251 // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 1252 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1253 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1254 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1255 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1256 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1257 // CHECK1-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 1258 // CHECK1-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 1259 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1260 // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1261 // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 1262 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1263 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1264 // CHECK1: omp.dispatch.cond: 1265 // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1266 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288 1267 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1268 // CHECK1: cond.true: 1269 // CHECK1-NEXT: br label [[COND_END:%.*]] 1270 // CHECK1: cond.false: 1271 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1272 // CHECK1-NEXT: br label [[COND_END]] 1273 // CHECK1: cond.end: 1274 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 1275 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1276 // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1277 // CHECK1-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 1278 // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1279 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1280 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]] 1281 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 1282 // CHECK1: omp.dispatch.cleanup: 1283 // CHECK1-NEXT: br label [[OMP_DISPATCH_END:%.*]] 1284 // CHECK1: omp.dispatch.body: 1285 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1286 // CHECK1: omp.inner.for.cond: 1287 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1288 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1289 // CHECK1-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] 1290 // CHECK1-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1291 // CHECK1: omp.inner.for.cond.cleanup: 1292 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1293 // CHECK1: omp.inner.for.body: 1294 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1295 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 1296 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1297 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1298 // CHECK1-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 1299 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1300 // CHECK1: invoke.cont: 1301 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float 1302 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1303 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 1304 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] 1305 // CHECK1-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1306 // CHECK1-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] 1307 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 1308 // CHECK1-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float 1309 // CHECK1-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] 1310 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 1311 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 1312 // CHECK1-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 1313 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] 1314 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 1315 // CHECK1-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] 1316 // CHECK1-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4 1317 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1318 // CHECK1: omp.body.continue: 1319 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1320 // CHECK1: omp.inner.for.inc: 1321 // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1322 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1 1323 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1324 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1325 // CHECK1: omp.inner.for.end: 1326 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1327 // CHECK1: omp.dispatch.inc: 1328 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1329 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1330 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]] 1331 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 1332 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1333 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1334 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]] 1335 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 1336 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1337 // CHECK1: omp.dispatch.end: 1338 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) 1339 // CHECK1-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1340 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 1341 // CHECK1-NEXT: ret void 1342 // CHECK1: terminate.lpad: 1343 // CHECK1-NEXT: [[TMP25:%.*]] = landingpad { i8*, i32 } 1344 // CHECK1-NEXT: catch i8* null 1345 // CHECK1-NEXT: [[TMP26:%.*]] = extractvalue { i8*, i32 } [[TMP25]], 0 1346 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]] 1347 // CHECK1-NEXT: unreachable 1348 // 1349 // 1350 // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate 1351 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 1352 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 1353 // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 1354 // CHECK1-NEXT: unreachable 1355 // 1356 // 1357 // CHECK2-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 1358 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 1359 // CHECK2-NEXT: entry: 1360 // CHECK2-NEXT: [[A:%.*]] = alloca double, align 8 1361 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1362 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 1363 // CHECK2-NEXT: store double 5.000000e+00, double* [[A]], align 8 1364 // CHECK2-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 1365 // CHECK2-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 1366 // CHECK2-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 1367 // CHECK2-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1368 // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 1369 // CHECK2-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 1370 // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 1371 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]]) 1372 // CHECK2-NEXT: ret void 1373 // 1374 // 1375 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1376 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 1377 // CHECK2-NEXT: entry: 1378 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1379 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1380 // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 1381 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1382 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 1383 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 1384 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 1385 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 1386 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1387 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1388 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1389 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1390 // CHECK2-NEXT: [[A:%.*]] = alloca double, align 8 1391 // CHECK2-NEXT: [[I5:%.*]] = alloca i64, align 8 1392 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1393 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1394 // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 1395 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 1396 // CHECK2-NEXT: [[TMP0:%.*]] = load double, double* undef, align 8 1397 // CHECK2-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]] 1398 // CHECK2-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 1399 // CHECK2-NEXT: [[TMP1:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 1400 // CHECK2-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00 1401 // CHECK2-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 1402 // CHECK2-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64 1403 // CHECK2-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1 1404 // CHECK2-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8 1405 // CHECK2-NEXT: store i64 1, i64* [[I]], align 8 1406 // CHECK2-NEXT: [[TMP2:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 1407 // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] 1408 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1409 // CHECK2: omp.precond.then: 1410 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1411 // CHECK2-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1412 // CHECK2-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 1413 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1414 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1415 // CHECK2-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8 1416 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 1417 // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1418 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 1419 // CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) 1420 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1421 // CHECK2: omp.dispatch.cond: 1422 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1423 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1424 // CHECK2-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]] 1425 // CHECK2-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1426 // CHECK2: cond.true: 1427 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1428 // CHECK2-NEXT: br label [[COND_END:%.*]] 1429 // CHECK2: cond.false: 1430 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1431 // CHECK2-NEXT: br label [[COND_END]] 1432 // CHECK2: cond.end: 1433 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 1434 // CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1435 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1436 // CHECK2-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 1437 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1438 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1439 // CHECK2-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1 1440 // CHECK2-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]] 1441 // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1442 // CHECK2: omp.dispatch.body: 1443 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1444 // CHECK2: omp.inner.for.cond: 1445 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1446 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1447 // CHECK2-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1 1448 // CHECK2-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]] 1449 // CHECK2-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1450 // CHECK2: omp.inner.for.body: 1451 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1452 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1 1453 // CHECK2-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]] 1454 // CHECK2-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8 1455 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1456 // CHECK2: omp.body.continue: 1457 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1458 // CHECK2: omp.inner.for.inc: 1459 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1460 // CHECK2-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1 1461 // CHECK2-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8 1462 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1463 // CHECK2: omp.inner.for.end: 1464 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1465 // CHECK2: omp.dispatch.inc: 1466 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1467 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 1468 // CHECK2-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]] 1469 // CHECK2-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8 1470 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1471 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 1472 // CHECK2-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]] 1473 // CHECK2-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8 1474 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1475 // CHECK2: omp.dispatch.end: 1476 // CHECK2-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1477 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 1478 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 1479 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1480 // CHECK2: omp.precond.end: 1481 // CHECK2-NEXT: ret void 1482 // 1483 // 1484 // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 1485 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1486 // CHECK2-NEXT: entry: 1487 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1488 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1489 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1490 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1491 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1492 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1493 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1494 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1495 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1496 // CHECK2-NEXT: ret void 1497 // 1498 // 1499 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 1500 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1501 // CHECK2-NEXT: entry: 1502 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1503 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1504 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1505 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1506 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1507 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1508 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1509 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1510 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1511 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1512 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1513 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1514 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1515 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1516 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1517 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1518 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1519 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1520 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1521 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1522 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1523 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1524 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1525 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1526 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1527 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1528 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1529 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1530 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1531 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1532 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1533 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1534 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1535 // CHECK2: cond.true: 1536 // CHECK2-NEXT: br label [[COND_END:%.*]] 1537 // CHECK2: cond.false: 1538 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1539 // CHECK2-NEXT: br label [[COND_END]] 1540 // CHECK2: cond.end: 1541 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1542 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1543 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1544 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1545 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1546 // CHECK2: omp.inner.for.cond: 1547 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1548 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1549 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1550 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1551 // CHECK2: omp.inner.for.body: 1552 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1553 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1554 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1555 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1556 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 1557 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1558 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 1559 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 1560 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1561 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 1562 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1563 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 1564 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 1565 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1566 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 1567 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 1568 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1569 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 1570 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 1571 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1572 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 1573 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 1574 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1575 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 1576 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 1577 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1578 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1579 // CHECK2: omp.body.continue: 1580 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1581 // CHECK2: omp.inner.for.inc: 1582 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1583 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 1584 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 1585 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1586 // CHECK2: omp.inner.for.end: 1587 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1588 // CHECK2: omp.loop.exit: 1589 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1590 // CHECK2-NEXT: ret void 1591 // 1592 // 1593 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1594 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1595 // CHECK2-NEXT: entry: 1596 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1597 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1598 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1599 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1600 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1601 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1602 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1603 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1604 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1605 // CHECK2-NEXT: ret void 1606 // 1607 // 1608 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 1609 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1610 // CHECK2-NEXT: entry: 1611 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1612 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1613 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1614 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1615 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1616 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1617 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1618 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1619 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1620 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1621 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1622 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1623 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1624 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1625 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1626 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1627 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1628 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1629 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1630 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1631 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1632 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1633 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1634 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1635 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1636 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1637 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1638 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1639 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1640 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1641 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1642 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 1643 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1644 // CHECK2: cond.true: 1645 // CHECK2-NEXT: br label [[COND_END:%.*]] 1646 // CHECK2: cond.false: 1647 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1648 // CHECK2-NEXT: br label [[COND_END]] 1649 // CHECK2: cond.end: 1650 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1651 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1652 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1653 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1654 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1655 // CHECK2: omp.inner.for.cond: 1656 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1657 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1658 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 1659 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1660 // CHECK2: omp.inner.for.body: 1661 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1662 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 1663 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1664 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1665 // CHECK2-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 1666 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 1667 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 1668 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 1669 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 1670 // CHECK2-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 1671 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 1672 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 1673 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 1674 // CHECK2-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1675 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 1676 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 1677 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 1678 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 1679 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 1680 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1681 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 1682 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 1683 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1684 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 1685 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 1686 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1687 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1688 // CHECK2: omp.body.continue: 1689 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1690 // CHECK2: omp.inner.for.inc: 1691 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1692 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 1693 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1694 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1695 // CHECK2: omp.inner.for.end: 1696 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1697 // CHECK2: omp.loop.exit: 1698 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1699 // CHECK2-NEXT: ret void 1700 // 1701 // 1702 // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 1703 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1704 // CHECK2-NEXT: entry: 1705 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1706 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1707 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1708 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1709 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1710 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1711 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1712 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1713 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1714 // CHECK2-NEXT: ret void 1715 // 1716 // 1717 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1718 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1719 // CHECK2-NEXT: entry: 1720 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1721 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1722 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1723 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1724 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1725 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1726 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1727 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1728 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1729 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1730 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1731 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1732 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1733 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1734 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1735 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1736 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1737 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1738 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1739 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1740 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1741 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1742 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1743 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1744 // CHECK2-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1745 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1746 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1747 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1748 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1749 // CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1750 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1751 // CHECK2: omp.dispatch.cond: 1752 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1753 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 1754 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1755 // CHECK2: cond.true: 1756 // CHECK2-NEXT: br label [[COND_END:%.*]] 1757 // CHECK2: cond.false: 1758 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1759 // CHECK2-NEXT: br label [[COND_END]] 1760 // CHECK2: cond.end: 1761 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 1762 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1763 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1764 // CHECK2-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 1765 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1766 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1767 // CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 1768 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1769 // CHECK2: omp.dispatch.body: 1770 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1771 // CHECK2: omp.inner.for.cond: 1772 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1773 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1774 // CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 1775 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1776 // CHECK2: omp.inner.for.body: 1777 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1778 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 1779 // CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1780 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1781 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8 1782 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 1783 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 1784 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 1785 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 1786 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8 1787 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 1788 // CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 1789 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 1790 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1791 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 1792 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8 1793 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 1794 // CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 1795 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 1796 // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4 1797 // CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 1798 // CHECK2-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8 1799 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 1800 // CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 1801 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 1802 // CHECK2-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 1803 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1804 // CHECK2: omp.body.continue: 1805 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1806 // CHECK2: omp.inner.for.inc: 1807 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1808 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 1809 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1810 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1811 // CHECK2: omp.inner.for.end: 1812 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1813 // CHECK2: omp.dispatch.inc: 1814 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1815 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1816 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 1817 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 1818 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1819 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1820 // CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 1821 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 1822 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1823 // CHECK2: omp.dispatch.end: 1824 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 1825 // CHECK2-NEXT: ret void 1826 // 1827 // 1828 // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 1829 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1830 // CHECK2-NEXT: entry: 1831 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1832 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1833 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1834 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1835 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1836 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1837 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1838 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1839 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1840 // CHECK2-NEXT: ret void 1841 // 1842 // 1843 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1844 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1845 // CHECK2-NEXT: entry: 1846 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1847 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1848 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1849 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1850 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1851 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1852 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1853 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 1854 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1855 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1856 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1857 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1858 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 1859 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1860 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1861 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1862 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1863 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1864 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1865 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1866 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1867 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1868 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1869 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1870 // CHECK2-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 1871 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1872 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1873 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1874 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1875 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 35, i64 0, i64 16908287, i64 1, i64 1) 1876 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1877 // CHECK2: omp.dispatch.cond: 1878 // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1879 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 1880 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1881 // CHECK2: omp.dispatch.body: 1882 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1883 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 1884 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1885 // CHECK2: omp.inner.for.cond: 1886 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 1887 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !4 1888 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 1889 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 1890 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1891 // CHECK2: omp.inner.for.body: 1892 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 1893 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 1894 // CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 1895 // CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !4 1896 // CHECK2-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !4 1897 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 1898 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 1899 // CHECK2-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !4 1900 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !4 1901 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 1902 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 1903 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !4 1904 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 1905 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !4 1906 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 1907 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 1908 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !4 1909 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 1910 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !4 1911 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 1912 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 1913 // CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !4 1914 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1915 // CHECK2: omp.body.continue: 1916 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1917 // CHECK2: omp.inner.for.inc: 1918 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 1919 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 1920 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 1921 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 1922 // CHECK2: omp.inner.for.end: 1923 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1924 // CHECK2: omp.dispatch.inc: 1925 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1926 // CHECK2: omp.dispatch.end: 1927 // CHECK2-NEXT: ret void 1928 // 1929 // 1930 // CHECK2-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 1931 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1932 // CHECK2-NEXT: entry: 1933 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1934 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1935 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1936 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1937 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1938 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1939 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1940 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1941 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 1942 // CHECK2-NEXT: ret void 1943 // 1944 // 1945 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 1946 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 1947 // CHECK2-NEXT: entry: 1948 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1949 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1950 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 1951 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 1952 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 1953 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 1954 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1955 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 1956 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1957 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1958 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1959 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1960 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 1961 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1962 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1963 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 1964 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 1965 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 1966 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 1967 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 1968 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 1969 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 1970 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 1971 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1972 // CHECK2-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 1973 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1974 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1975 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1976 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 1977 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 36, i64 0, i64 16908287, i64 1, i64 7) 1978 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1979 // CHECK2: omp.dispatch.cond: 1980 // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1981 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 1982 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1983 // CHECK2: omp.dispatch.body: 1984 // CHECK2-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1985 // CHECK2-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 1986 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1987 // CHECK2: omp.inner.for.cond: 1988 // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 1989 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !7 1990 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 1991 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 1992 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1993 // CHECK2: omp.inner.for.body: 1994 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 1995 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 1996 // CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 1997 // CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !7 1998 // CHECK2-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !7 1999 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 2000 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 2001 // CHECK2-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !7 2002 // CHECK2-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !7 2003 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 2004 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 2005 // CHECK2-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !7 2006 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 2007 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !7 2008 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 2009 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 2010 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !7 2011 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 2012 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !7 2013 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 2014 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 2015 // CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !7 2016 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2017 // CHECK2: omp.body.continue: 2018 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2019 // CHECK2: omp.inner.for.inc: 2020 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 2021 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 2022 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 2023 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 2024 // CHECK2: omp.inner.for.end: 2025 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2026 // CHECK2: omp.dispatch.inc: 2027 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2028 // CHECK2: omp.dispatch.end: 2029 // CHECK2-NEXT: ret void 2030 // 2031 // 2032 // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2033 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2034 // CHECK2-NEXT: entry: 2035 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2036 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2037 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2038 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2039 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2040 // CHECK2-NEXT: [[Y:%.*]] = alloca i32, align 4 2041 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2042 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2043 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2044 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2045 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 2046 // CHECK2-NEXT: store i32 0, i32* [[Y]], align 4 2047 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[Y]], float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2048 // CHECK2-NEXT: ret void 2049 // 2050 // 2051 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 2052 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2053 // CHECK2-NEXT: entry: 2054 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2055 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2056 // CHECK2-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 2057 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2058 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2059 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2060 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2061 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2062 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 2063 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2064 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2065 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2066 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 2067 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2068 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2069 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2070 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2071 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2072 // CHECK2-NEXT: [[I7:%.*]] = alloca i8, align 1 2073 // CHECK2-NEXT: [[X8:%.*]] = alloca i32, align 4 2074 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2075 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2076 // CHECK2-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 2077 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2078 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2079 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2080 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2081 // CHECK2-NEXT: [[TMP0:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 2082 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[A_ADDR]], align 8 2083 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[B_ADDR]], align 8 2084 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[C_ADDR]], align 8 2085 // CHECK2-NEXT: [[TMP4:%.*]] = load float**, float*** [[D_ADDR]], align 8 2086 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 2087 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8 2088 // CHECK2-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 2089 // CHECK2-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2090 // CHECK2-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32 2091 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 2092 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 2093 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2094 // CHECK2-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 2095 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 2096 // CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 2097 // CHECK2-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 2098 // CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2099 // CHECK2-NEXT: store i8 [[TMP7]], i8* [[I]], align 1 2100 // CHECK2-NEXT: store i32 11, i32* [[X]], align 4 2101 // CHECK2-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2102 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32 2103 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 2104 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2105 // CHECK2: omp.precond.then: 2106 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2107 // CHECK2-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2108 // CHECK2-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 2109 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2110 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2111 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2112 // CHECK2-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2113 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 2114 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 38, i64 0, i64 [[TMP10]], i64 1, i64 1) 2115 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2116 // CHECK2: omp.dispatch.cond: 2117 // CHECK2-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2118 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 2119 // CHECK2-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2120 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 2121 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2122 // CHECK2: omp.dispatch.body: 2123 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2124 // CHECK2-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 2125 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2126 // CHECK2: omp.inner.for.cond: 2127 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 2128 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !10 2129 // CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 2130 // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2131 // CHECK2: omp.inner.for.body: 2132 // CHECK2-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !10 2133 // CHECK2-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64 2134 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 2135 // CHECK2-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11 2136 // CHECK2-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 2137 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 2138 // CHECK2-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 2139 // CHECK2-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !10 2140 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 2141 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 2142 // CHECK2-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11 2143 // CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 2144 // CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]] 2145 // CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 2146 // CHECK2-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 2147 // CHECK2-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 2148 // CHECK2-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !10 2149 // CHECK2-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !10 2150 // CHECK2-NEXT: [[TMP24:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 2151 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64 2152 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM]] 2153 // CHECK2-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 2154 // CHECK2-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !10 2155 // CHECK2-NEXT: [[TMP27:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 2156 // CHECK2-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64 2157 // CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM21]] 2158 // CHECK2-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !10 2159 // CHECK2-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]] 2160 // CHECK2-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !10 2161 // CHECK2-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 2162 // CHECK2-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64 2163 // CHECK2-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM24]] 2164 // CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !10 2165 // CHECK2-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]] 2166 // CHECK2-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !10 2167 // CHECK2-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 2168 // CHECK2-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64 2169 // CHECK2-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM27]] 2170 // CHECK2-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !10 2171 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2172 // CHECK2: omp.body.continue: 2173 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2174 // CHECK2: omp.inner.for.inc: 2175 // CHECK2-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 2176 // CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1 2177 // CHECK2-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 2178 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 2179 // CHECK2: omp.inner.for.end: 2180 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2181 // CHECK2: omp.dispatch.inc: 2182 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2183 // CHECK2: omp.dispatch.end: 2184 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 2185 // CHECK2: omp.precond.end: 2186 // CHECK2-NEXT: ret void 2187 // 2188 // 2189 // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 2190 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2191 // CHECK2-NEXT: entry: 2192 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2193 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2194 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2195 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2196 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2197 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2198 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2199 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2200 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2201 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 2202 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2203 // CHECK2-NEXT: ret void 2204 // 2205 // 2206 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 2207 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2208 // CHECK2-NEXT: entry: 2209 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2210 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2211 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2212 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2213 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2214 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2215 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2216 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 2217 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2218 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2219 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2220 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2221 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2222 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 2223 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2224 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2225 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2226 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2227 // CHECK2-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2228 // CHECK2-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2229 // CHECK2-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2230 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2231 // CHECK2-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2232 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2233 // CHECK2-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2234 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2235 // CHECK2-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 2236 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2237 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2238 // CHECK2-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2239 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2240 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 37, i32 0, i32 199, i32 1, i32 1) 2241 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2242 // CHECK2: omp.dispatch.cond: 2243 // CHECK2-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2244 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 2245 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2246 // CHECK2: omp.dispatch.body: 2247 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2248 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 2249 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2250 // CHECK2: omp.inner.for.cond: 2251 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2252 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 2253 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 2254 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2255 // CHECK2: omp.inner.for.body: 2256 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2257 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20 2258 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2259 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 2260 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 2261 // CHECK2-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !13 2262 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2263 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2264 // CHECK2-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20 2265 // CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 2266 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]] 2267 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 2268 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 2269 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !13 2270 // CHECK2-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !13 2271 // CHECK2-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 2272 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64 2273 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 2274 // CHECK2-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 2275 // CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !13 2276 // CHECK2-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 2277 // CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64 2278 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM6]] 2279 // CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !13 2280 // CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]] 2281 // CHECK2-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !13 2282 // CHECK2-NEXT: [[TMP20:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 2283 // CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64 2284 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM9]] 2285 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !13 2286 // CHECK2-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]] 2287 // CHECK2-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !13 2288 // CHECK2-NEXT: [[TMP23:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 2289 // CHECK2-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64 2290 // CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM12]] 2291 // CHECK2-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !13 2292 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2293 // CHECK2: omp.body.continue: 2294 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2295 // CHECK2: omp.inner.for.inc: 2296 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2297 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1 2298 // CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 2299 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 2300 // CHECK2: omp.inner.for.end: 2301 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2302 // CHECK2: omp.dispatch.inc: 2303 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2304 // CHECK2: omp.dispatch.end: 2305 // CHECK2-NEXT: ret void 2306 // 2307 // 2308 // CHECK2-LABEL: define {{[^@]+}}@_Z3foov 2309 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 2310 // CHECK2-NEXT: entry: 2311 // CHECK2-NEXT: call void @_Z8mayThrowv() 2312 // CHECK2-NEXT: ret i32 0 2313 // 2314 // 2315 // CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 2316 // CHECK2-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { 2317 // CHECK2-NEXT: entry: 2318 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2319 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2320 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2321 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2322 // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 2323 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2324 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2325 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2326 // CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2327 // CHECK2-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2328 // CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 2329 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 2330 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 2331 // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 2332 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 2333 // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 2334 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 2335 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) 2336 // CHECK2-NEXT: [[TMP5:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2337 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]) 2338 // CHECK2-NEXT: ret void 2339 // 2340 // 2341 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 2342 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 2343 // CHECK2-NEXT: entry: 2344 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2345 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2346 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2347 // CHECK2-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 2348 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 2349 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2350 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 2351 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2352 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2353 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2354 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2355 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2356 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2357 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2358 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2359 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2360 // CHECK2-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2361 // CHECK2-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 2362 // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 2363 // CHECK2-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2364 // CHECK2-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 2365 // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 2366 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2367 // CHECK2-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2368 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2369 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2370 // CHECK2-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2371 // CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 2372 // CHECK2-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 2373 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 2374 // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2375 // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 2376 // CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2377 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2378 // CHECK2: omp.dispatch.cond: 2379 // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2380 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288 2381 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2382 // CHECK2: cond.true: 2383 // CHECK2-NEXT: br label [[COND_END:%.*]] 2384 // CHECK2: cond.false: 2385 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2386 // CHECK2-NEXT: br label [[COND_END]] 2387 // CHECK2: cond.end: 2388 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 2389 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2390 // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2391 // CHECK2-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 2392 // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2393 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2394 // CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]] 2395 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 2396 // CHECK2: omp.dispatch.cleanup: 2397 // CHECK2-NEXT: br label [[OMP_DISPATCH_END:%.*]] 2398 // CHECK2: omp.dispatch.body: 2399 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2400 // CHECK2: omp.inner.for.cond: 2401 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2402 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2403 // CHECK2-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] 2404 // CHECK2-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2405 // CHECK2: omp.inner.for.cond.cleanup: 2406 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2407 // CHECK2: omp.inner.for.body: 2408 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2409 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 2410 // CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2411 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2412 // CHECK2-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 2413 // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2414 // CHECK2: invoke.cont: 2415 // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float 2416 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2417 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 2418 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] 2419 // CHECK2-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2420 // CHECK2-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] 2421 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 2422 // CHECK2-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float 2423 // CHECK2-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] 2424 // CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 2425 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 2426 // CHECK2-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 2427 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] 2428 // CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 2429 // CHECK2-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] 2430 // CHECK2-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4 2431 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2432 // CHECK2: omp.body.continue: 2433 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2434 // CHECK2: omp.inner.for.inc: 2435 // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2436 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1 2437 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 2438 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2439 // CHECK2: omp.inner.for.end: 2440 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2441 // CHECK2: omp.dispatch.inc: 2442 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2443 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2444 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]] 2445 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 2446 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2447 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2448 // CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]] 2449 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 2450 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2451 // CHECK2: omp.dispatch.end: 2452 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) 2453 // CHECK2-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2454 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 2455 // CHECK2-NEXT: ret void 2456 // CHECK2: terminate.lpad: 2457 // CHECK2-NEXT: [[TMP25:%.*]] = landingpad { i8*, i32 } 2458 // CHECK2-NEXT: catch i8* null 2459 // CHECK2-NEXT: [[TMP26:%.*]] = extractvalue { i8*, i32 } [[TMP25]], 0 2460 // CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]] 2461 // CHECK2-NEXT: unreachable 2462 // 2463 // 2464 // CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate 2465 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 2466 // CHECK2-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 2467 // CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 2468 // CHECK2-NEXT: unreachable 2469 // 2470 // 2471 // CHECK3-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 2472 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 2473 // CHECK3-NEXT: entry: 2474 // CHECK3-NEXT: [[A:%.*]] = alloca double, align 8 2475 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2476 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 2477 // CHECK3-NEXT: store double 5.000000e+00, double* [[A]], align 8 2478 // CHECK3-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 2479 // CHECK3-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 2480 // CHECK3-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 2481 // CHECK3-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2482 // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 2483 // CHECK3-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 2484 // CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 2485 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]]) 2486 // CHECK3-NEXT: ret void 2487 // 2488 // 2489 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2490 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 2491 // CHECK3-NEXT: entry: 2492 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2493 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2494 // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 2495 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2496 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 8 2497 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 2498 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2499 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 2500 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2501 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2502 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2503 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2504 // CHECK3-NEXT: [[A:%.*]] = alloca double, align 8 2505 // CHECK3-NEXT: [[I5:%.*]] = alloca i64, align 8 2506 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2507 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2508 // CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 2509 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 2510 // CHECK3-NEXT: [[TMP0:%.*]] = load double, double* undef, align 8 2511 // CHECK3-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]] 2512 // CHECK3-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 2513 // CHECK3-NEXT: [[TMP1:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 2514 // CHECK3-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00 2515 // CHECK3-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 2516 // CHECK3-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64 2517 // CHECK3-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1 2518 // CHECK3-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8 2519 // CHECK3-NEXT: store i64 1, i64* [[I]], align 8 2520 // CHECK3-NEXT: [[TMP2:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 2521 // CHECK3-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] 2522 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2523 // CHECK3: omp.precond.then: 2524 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2525 // CHECK3-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2526 // CHECK3-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 2527 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2528 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2529 // CHECK3-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8 2530 // CHECK3-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 2531 // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2532 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 2533 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) 2534 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2535 // CHECK3: omp.dispatch.cond: 2536 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2537 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2538 // CHECK3-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]] 2539 // CHECK3-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2540 // CHECK3: cond.true: 2541 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2542 // CHECK3-NEXT: br label [[COND_END:%.*]] 2543 // CHECK3: cond.false: 2544 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2545 // CHECK3-NEXT: br label [[COND_END]] 2546 // CHECK3: cond.end: 2547 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 2548 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2549 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2550 // CHECK3-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 2551 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2552 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2553 // CHECK3-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1 2554 // CHECK3-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]] 2555 // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2556 // CHECK3: omp.dispatch.body: 2557 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2558 // CHECK3: omp.inner.for.cond: 2559 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2560 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2561 // CHECK3-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1 2562 // CHECK3-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]] 2563 // CHECK3-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2564 // CHECK3: omp.inner.for.body: 2565 // CHECK3-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2566 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1 2567 // CHECK3-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]] 2568 // CHECK3-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8 2569 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2570 // CHECK3: omp.body.continue: 2571 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2572 // CHECK3: omp.inner.for.inc: 2573 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2574 // CHECK3-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1 2575 // CHECK3-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8 2576 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2577 // CHECK3: omp.inner.for.end: 2578 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2579 // CHECK3: omp.dispatch.inc: 2580 // CHECK3-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2581 // CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 2582 // CHECK3-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]] 2583 // CHECK3-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8 2584 // CHECK3-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2585 // CHECK3-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 2586 // CHECK3-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]] 2587 // CHECK3-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8 2588 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2589 // CHECK3: omp.dispatch.end: 2590 // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2591 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 2592 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 2593 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 2594 // CHECK3: omp.precond.end: 2595 // CHECK3-NEXT: ret void 2596 // 2597 // 2598 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 2599 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2600 // CHECK3-NEXT: entry: 2601 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2602 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2603 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2604 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2605 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2606 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2607 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2608 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2609 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2610 // CHECK3-NEXT: ret void 2611 // 2612 // 2613 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 2614 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2615 // CHECK3-NEXT: entry: 2616 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2617 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2618 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2619 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2620 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2621 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2622 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2623 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2624 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2625 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2626 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2627 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2628 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2629 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2630 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2631 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2632 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2633 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2634 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2635 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2636 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2637 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2638 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2639 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2640 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2641 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2642 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2643 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2644 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2645 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2646 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2647 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2648 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2649 // CHECK3: cond.true: 2650 // CHECK3-NEXT: br label [[COND_END:%.*]] 2651 // CHECK3: cond.false: 2652 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2653 // CHECK3-NEXT: br label [[COND_END]] 2654 // CHECK3: cond.end: 2655 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2656 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2657 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2658 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2659 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2660 // CHECK3: omp.inner.for.cond: 2661 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2662 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2663 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2664 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2665 // CHECK3: omp.inner.for.body: 2666 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2667 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2668 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 2669 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2670 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 2671 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2672 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 2673 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 2674 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2675 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 2676 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2677 // CHECK3-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 2678 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 2679 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 2680 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 2681 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 2682 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2683 // CHECK3-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 2684 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 2685 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2686 // CHECK3-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 2687 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 2688 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2689 // CHECK3-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 2690 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 2691 // CHECK3-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 2692 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2693 // CHECK3: omp.body.continue: 2694 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2695 // CHECK3: omp.inner.for.inc: 2696 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2697 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 2698 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 2699 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2700 // CHECK3: omp.inner.for.end: 2701 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2702 // CHECK3: omp.loop.exit: 2703 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2704 // CHECK3-NEXT: ret void 2705 // 2706 // 2707 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2708 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2709 // CHECK3-NEXT: entry: 2710 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2711 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2712 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2713 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2714 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2715 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2716 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2717 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2718 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2719 // CHECK3-NEXT: ret void 2720 // 2721 // 2722 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2723 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2724 // CHECK3-NEXT: entry: 2725 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2726 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2727 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2728 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2729 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2730 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2731 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2732 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2733 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2734 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2735 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2736 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2737 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2738 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2739 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2740 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2741 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2742 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2743 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2744 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2745 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2746 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2747 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2748 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2749 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2750 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2751 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2752 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2753 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2754 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2755 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2756 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 2757 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2758 // CHECK3: cond.true: 2759 // CHECK3-NEXT: br label [[COND_END:%.*]] 2760 // CHECK3: cond.false: 2761 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2762 // CHECK3-NEXT: br label [[COND_END]] 2763 // CHECK3: cond.end: 2764 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2765 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2766 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2767 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2768 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2769 // CHECK3: omp.inner.for.cond: 2770 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2771 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2772 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 2773 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2774 // CHECK3: omp.inner.for.body: 2775 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2776 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 2777 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2778 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2779 // CHECK3-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 2780 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 2781 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 2782 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 2783 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 2784 // CHECK3-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 2785 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 2786 // CHECK3-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 2787 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 2788 // CHECK3-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 2789 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 2790 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 2791 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 2792 // CHECK3-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 2793 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 2794 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2795 // CHECK3-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 2796 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 2797 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2798 // CHECK3-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 2799 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 2800 // CHECK3-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 2801 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2802 // CHECK3: omp.body.continue: 2803 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2804 // CHECK3: omp.inner.for.inc: 2805 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2806 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 2807 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2808 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2809 // CHECK3: omp.inner.for.end: 2810 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2811 // CHECK3: omp.loop.exit: 2812 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2813 // CHECK3-NEXT: ret void 2814 // 2815 // 2816 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 2817 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2818 // CHECK3-NEXT: entry: 2819 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2820 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2821 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2822 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2823 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2824 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2825 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2826 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2827 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2828 // CHECK3-NEXT: ret void 2829 // 2830 // 2831 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2832 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2833 // CHECK3-NEXT: entry: 2834 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2835 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2836 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2837 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2838 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2839 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2840 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2841 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2842 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2843 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2844 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2845 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2846 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2847 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2848 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2849 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2850 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2851 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2852 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2853 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2854 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2855 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2856 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2857 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2858 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2859 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2860 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2861 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2862 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2863 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2864 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2865 // CHECK3: omp.dispatch.cond: 2866 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2867 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 2868 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2869 // CHECK3: cond.true: 2870 // CHECK3-NEXT: br label [[COND_END:%.*]] 2871 // CHECK3: cond.false: 2872 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2873 // CHECK3-NEXT: br label [[COND_END]] 2874 // CHECK3: cond.end: 2875 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 2876 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2877 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2878 // CHECK3-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 2879 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2880 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2881 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 2882 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2883 // CHECK3: omp.dispatch.body: 2884 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2885 // CHECK3: omp.inner.for.cond: 2886 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2887 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2888 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 2889 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2890 // CHECK3: omp.inner.for.body: 2891 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2892 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 2893 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2894 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2895 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8 2896 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 2897 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 2898 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 2899 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 2900 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8 2901 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 2902 // CHECK3-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 2903 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 2904 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4 2905 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 2906 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8 2907 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 2908 // CHECK3-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 2909 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 2910 // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2911 // CHECK3-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 2912 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8 2913 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 2914 // CHECK3-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 2915 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 2916 // CHECK3-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 2917 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2918 // CHECK3: omp.body.continue: 2919 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2920 // CHECK3: omp.inner.for.inc: 2921 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2922 // CHECK3-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 2923 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 2924 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2925 // CHECK3: omp.inner.for.end: 2926 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2927 // CHECK3: omp.dispatch.inc: 2928 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2929 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2930 // CHECK3-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 2931 // CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 2932 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2933 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2934 // CHECK3-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 2935 // CHECK3-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 2936 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2937 // CHECK3: omp.dispatch.end: 2938 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 2939 // CHECK3-NEXT: ret void 2940 // 2941 // 2942 // CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 2943 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2944 // CHECK3-NEXT: entry: 2945 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2946 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2947 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2948 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2949 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2950 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2951 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2952 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2953 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 2954 // CHECK3-NEXT: ret void 2955 // 2956 // 2957 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 2958 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 2959 // CHECK3-NEXT: entry: 2960 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2961 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2962 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 2963 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 2964 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 2965 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 2966 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2967 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 8 2968 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2969 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2970 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2971 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2972 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 2973 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2974 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2975 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 2976 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 2977 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 2978 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 2979 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 2980 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 2981 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 2982 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 2983 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2984 // CHECK3-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 2985 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2986 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2987 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2988 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 2989 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1) 2990 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2991 // CHECK3: omp.dispatch.cond: 2992 // CHECK3-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2993 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 2994 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2995 // CHECK3: omp.dispatch.body: 2996 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2997 // CHECK3-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 2998 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2999 // CHECK3: omp.inner.for.cond: 3000 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 3001 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !4 3002 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 3003 // CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 3004 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3005 // CHECK3: omp.inner.for.body: 3006 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 3007 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 3008 // CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 3009 // CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !4 3010 // CHECK3-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !4 3011 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 3012 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 3013 // CHECK3-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !4 3014 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !4 3015 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 3016 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 3017 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !4 3018 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 3019 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !4 3020 // CHECK3-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 3021 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 3022 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !4 3023 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 3024 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !4 3025 // CHECK3-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 3026 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 3027 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !4 3028 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3029 // CHECK3: omp.body.continue: 3030 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3031 // CHECK3: omp.inner.for.inc: 3032 // CHECK3-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 3033 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 3034 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 3035 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 3036 // CHECK3: omp.inner.for.end: 3037 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3038 // CHECK3: omp.dispatch.inc: 3039 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3040 // CHECK3: omp.dispatch.end: 3041 // CHECK3-NEXT: ret void 3042 // 3043 // 3044 // CHECK3-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 3045 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3046 // CHECK3-NEXT: entry: 3047 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3048 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3049 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3050 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3051 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3052 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3053 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3054 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3055 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3056 // CHECK3-NEXT: ret void 3057 // 3058 // 3059 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 3060 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3061 // CHECK3-NEXT: entry: 3062 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3063 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3064 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3065 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3066 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3067 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3068 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3069 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 8 3070 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3071 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3072 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3073 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3074 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 3075 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3076 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3077 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3078 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3079 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3080 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3081 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3082 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3083 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3084 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3085 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3086 // CHECK3-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 3087 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3088 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3089 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3090 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3091 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7) 3092 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3093 // CHECK3: omp.dispatch.cond: 3094 // CHECK3-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 3095 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 3096 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3097 // CHECK3: omp.dispatch.body: 3098 // CHECK3-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3099 // CHECK3-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 3100 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3101 // CHECK3: omp.inner.for.cond: 3102 // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 3103 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !7 3104 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 3105 // CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 3106 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3107 // CHECK3: omp.inner.for.body: 3108 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 3109 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 3110 // CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 3111 // CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !7 3112 // CHECK3-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !7 3113 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 3114 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 3115 // CHECK3-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !7 3116 // CHECK3-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !7 3117 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 3118 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 3119 // CHECK3-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !7 3120 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 3121 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !7 3122 // CHECK3-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 3123 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 3124 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !7 3125 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 3126 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !7 3127 // CHECK3-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 3128 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 3129 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !7 3130 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3131 // CHECK3: omp.body.continue: 3132 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3133 // CHECK3: omp.inner.for.inc: 3134 // CHECK3-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 3135 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 3136 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 3137 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 3138 // CHECK3: omp.inner.for.end: 3139 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3140 // CHECK3: omp.dispatch.inc: 3141 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3142 // CHECK3: omp.dispatch.end: 3143 // CHECK3-NEXT: ret void 3144 // 3145 // 3146 // CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 3147 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3148 // CHECK3-NEXT: entry: 3149 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3150 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3151 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3152 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3153 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 3154 // CHECK3-NEXT: [[Y:%.*]] = alloca i32, align 4 3155 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3156 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3157 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3158 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3159 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 3160 // CHECK3-NEXT: store i32 0, i32* [[Y]], align 4 3161 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[Y]], float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3162 // CHECK3-NEXT: ret void 3163 // 3164 // 3165 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 3166 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3167 // CHECK3-NEXT: entry: 3168 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3169 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3170 // CHECK3-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 3171 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3172 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3173 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3174 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3175 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3176 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 3177 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3178 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3179 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 3180 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 3181 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 3182 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3183 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3184 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3185 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3186 // CHECK3-NEXT: [[I7:%.*]] = alloca i8, align 1 3187 // CHECK3-NEXT: [[X8:%.*]] = alloca i32, align 4 3188 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3189 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3190 // CHECK3-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 3191 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3192 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3193 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3194 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3195 // CHECK3-NEXT: [[TMP0:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 3196 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[A_ADDR]], align 8 3197 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[B_ADDR]], align 8 3198 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[C_ADDR]], align 8 3199 // CHECK3-NEXT: [[TMP4:%.*]] = load float**, float*** [[D_ADDR]], align 8 3200 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 3201 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8 3202 // CHECK3-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 3203 // CHECK3-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3204 // CHECK3-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32 3205 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 3206 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 3207 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3208 // CHECK3-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 3209 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 3210 // CHECK3-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 3211 // CHECK3-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 3212 // CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3213 // CHECK3-NEXT: store i8 [[TMP7]], i8* [[I]], align 1 3214 // CHECK3-NEXT: store i32 11, i32* [[X]], align 4 3215 // CHECK3-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3216 // CHECK3-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32 3217 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 3218 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3219 // CHECK3: omp.precond.then: 3220 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3221 // CHECK3-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3222 // CHECK3-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 3223 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3224 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3225 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3226 // CHECK3-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3227 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 3228 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1) 3229 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3230 // CHECK3: omp.dispatch.cond: 3231 // CHECK3-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3232 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 3233 // CHECK3-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 3234 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 3235 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3236 // CHECK3: omp.dispatch.body: 3237 // CHECK3-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3238 // CHECK3-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 3239 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3240 // CHECK3: omp.inner.for.cond: 3241 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 3242 // CHECK3-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !10 3243 // CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 3244 // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3245 // CHECK3: omp.inner.for.body: 3246 // CHECK3-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !10 3247 // CHECK3-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64 3248 // CHECK3-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 3249 // CHECK3-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11 3250 // CHECK3-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 3251 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 3252 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 3253 // CHECK3-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !10 3254 // CHECK3-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 3255 // CHECK3-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 3256 // CHECK3-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11 3257 // CHECK3-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 3258 // CHECK3-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]] 3259 // CHECK3-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 3260 // CHECK3-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 3261 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 3262 // CHECK3-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !10 3263 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !10 3264 // CHECK3-NEXT: [[TMP24:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 3265 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64 3266 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM]] 3267 // CHECK3-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 3268 // CHECK3-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !10 3269 // CHECK3-NEXT: [[TMP27:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 3270 // CHECK3-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64 3271 // CHECK3-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM21]] 3272 // CHECK3-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !10 3273 // CHECK3-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]] 3274 // CHECK3-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !10 3275 // CHECK3-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 3276 // CHECK3-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64 3277 // CHECK3-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM24]] 3278 // CHECK3-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !10 3279 // CHECK3-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]] 3280 // CHECK3-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !10 3281 // CHECK3-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 3282 // CHECK3-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64 3283 // CHECK3-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM27]] 3284 // CHECK3-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !10 3285 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3286 // CHECK3: omp.body.continue: 3287 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3288 // CHECK3: omp.inner.for.inc: 3289 // CHECK3-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 3290 // CHECK3-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1 3291 // CHECK3-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 3292 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 3293 // CHECK3: omp.inner.for.end: 3294 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3295 // CHECK3: omp.dispatch.inc: 3296 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3297 // CHECK3: omp.dispatch.end: 3298 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 3299 // CHECK3: omp.precond.end: 3300 // CHECK3-NEXT: ret void 3301 // 3302 // 3303 // CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 3304 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3305 // CHECK3-NEXT: entry: 3306 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3307 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3308 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3309 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3310 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 3311 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3312 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3313 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3314 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3315 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 3316 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3317 // CHECK3-NEXT: ret void 3318 // 3319 // 3320 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 3321 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3322 // CHECK3-NEXT: entry: 3323 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3324 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3325 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3326 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3327 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3328 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3329 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3330 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 3331 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3332 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3333 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3334 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3335 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3336 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 3337 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 3338 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3339 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3340 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3341 // CHECK3-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3342 // CHECK3-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3343 // CHECK3-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3344 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3345 // CHECK3-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3346 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3347 // CHECK3-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3348 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3349 // CHECK3-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 3350 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3351 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3352 // CHECK3-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3353 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3354 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1) 3355 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3356 // CHECK3: omp.dispatch.cond: 3357 // CHECK3-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 3358 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 3359 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3360 // CHECK3: omp.dispatch.body: 3361 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3362 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 3363 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3364 // CHECK3: omp.inner.for.cond: 3365 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3366 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 3367 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 3368 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3369 // CHECK3: omp.inner.for.body: 3370 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3371 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20 3372 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 3373 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 3374 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 3375 // CHECK3-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !13 3376 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3377 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3378 // CHECK3-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20 3379 // CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 3380 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]] 3381 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 3382 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 3383 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !13 3384 // CHECK3-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !13 3385 // CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 3386 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64 3387 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 3388 // CHECK3-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 3389 // CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !13 3390 // CHECK3-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 3391 // CHECK3-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64 3392 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM6]] 3393 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !13 3394 // CHECK3-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]] 3395 // CHECK3-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !13 3396 // CHECK3-NEXT: [[TMP20:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 3397 // CHECK3-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64 3398 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM9]] 3399 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !13 3400 // CHECK3-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]] 3401 // CHECK3-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !13 3402 // CHECK3-NEXT: [[TMP23:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 3403 // CHECK3-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64 3404 // CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM12]] 3405 // CHECK3-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !13 3406 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3407 // CHECK3: omp.body.continue: 3408 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3409 // CHECK3: omp.inner.for.inc: 3410 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3411 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1 3412 // CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 3413 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 3414 // CHECK3: omp.inner.for.end: 3415 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3416 // CHECK3: omp.dispatch.inc: 3417 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3418 // CHECK3: omp.dispatch.end: 3419 // CHECK3-NEXT: ret void 3420 // 3421 // 3422 // CHECK3-LABEL: define {{[^@]+}}@_Z3foov 3423 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 3424 // CHECK3-NEXT: entry: 3425 // CHECK3-NEXT: call void @_Z8mayThrowv() 3426 // CHECK3-NEXT: ret i32 0 3427 // 3428 // 3429 // CHECK3-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 3430 // CHECK3-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { 3431 // CHECK3-NEXT: entry: 3432 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3433 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3434 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3435 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3436 // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 3437 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3438 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3439 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3440 // CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 3441 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3442 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 3443 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 3444 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 3445 // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 3446 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 3447 // CHECK3-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 3448 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 3449 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) 3450 // CHECK3-NEXT: [[TMP5:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3451 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]) 3452 // CHECK3-NEXT: ret void 3453 // 3454 // 3455 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 3456 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 3457 // CHECK3-NEXT: entry: 3458 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3459 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3460 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3461 // CHECK3-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 3462 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 3463 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3464 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3465 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3466 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3467 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3468 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3469 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3470 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3471 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3472 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3473 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3474 // CHECK3-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3475 // CHECK3-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 3476 // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 3477 // CHECK3-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3478 // CHECK3-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 3479 // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 3480 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3481 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 3482 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3483 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3484 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3485 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 3486 // CHECK3-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 3487 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 3488 // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3489 // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 3490 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 3491 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3492 // CHECK3: omp.dispatch.cond: 3493 // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3494 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288 3495 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3496 // CHECK3: cond.true: 3497 // CHECK3-NEXT: br label [[COND_END:%.*]] 3498 // CHECK3: cond.false: 3499 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3500 // CHECK3-NEXT: br label [[COND_END]] 3501 // CHECK3: cond.end: 3502 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 3503 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3504 // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3505 // CHECK3-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 3506 // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3507 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3508 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]] 3509 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 3510 // CHECK3: omp.dispatch.cleanup: 3511 // CHECK3-NEXT: br label [[OMP_DISPATCH_END:%.*]] 3512 // CHECK3: omp.dispatch.body: 3513 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3514 // CHECK3: omp.inner.for.cond: 3515 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3516 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3517 // CHECK3-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] 3518 // CHECK3-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3519 // CHECK3: omp.inner.for.cond.cleanup: 3520 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3521 // CHECK3: omp.inner.for.body: 3522 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3523 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 3524 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 3525 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3526 // CHECK3-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 3527 // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 3528 // CHECK3: invoke.cont: 3529 // CHECK3-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float 3530 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 3531 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 3532 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] 3533 // CHECK3-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 3534 // CHECK3-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] 3535 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 3536 // CHECK3-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float 3537 // CHECK3-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] 3538 // CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 3539 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 3540 // CHECK3-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 3541 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] 3542 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 3543 // CHECK3-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] 3544 // CHECK3-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4 3545 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3546 // CHECK3: omp.body.continue: 3547 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3548 // CHECK3: omp.inner.for.inc: 3549 // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3550 // CHECK3-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1 3551 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 3552 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3553 // CHECK3: omp.inner.for.end: 3554 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3555 // CHECK3: omp.dispatch.inc: 3556 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3557 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3558 // CHECK3-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]] 3559 // CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 3560 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3561 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3562 // CHECK3-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]] 3563 // CHECK3-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 3564 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3565 // CHECK3: omp.dispatch.end: 3566 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) 3567 // CHECK3-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3568 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 3569 // CHECK3-NEXT: ret void 3570 // CHECK3: terminate.lpad: 3571 // CHECK3-NEXT: [[TMP25:%.*]] = landingpad { i8*, i32 } 3572 // CHECK3-NEXT: catch i8* null 3573 // CHECK3-NEXT: [[TMP26:%.*]] = extractvalue { i8*, i32 } [[TMP25]], 0 3574 // CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]] 3575 // CHECK3-NEXT: unreachable 3576 // 3577 // 3578 // CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate 3579 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 3580 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 3581 // CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 3582 // CHECK3-NEXT: unreachable 3583 // 3584 // 3585 // CHECK4-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 3586 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 3587 // CHECK4-NEXT: entry: 3588 // CHECK4-NEXT: [[A:%.*]] = alloca double, align 8 3589 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3590 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 3591 // CHECK4-NEXT: store double 5.000000e+00, double* [[A]], align 8 3592 // CHECK4-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 3593 // CHECK4-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 3594 // CHECK4-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 3595 // CHECK4-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3596 // CHECK4-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8* 3597 // CHECK4-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1 3598 // CHECK4-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 3599 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]]) 3600 // CHECK4-NEXT: ret void 3601 // 3602 // 3603 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 3604 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] { 3605 // CHECK4-NEXT: entry: 3606 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3607 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3608 // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 3609 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3610 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 8 3611 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 3612 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 3613 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 3614 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3615 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3616 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3617 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3618 // CHECK4-NEXT: [[A:%.*]] = alloca double, align 8 3619 // CHECK4-NEXT: [[I5:%.*]] = alloca i64, align 8 3620 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3621 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3622 // CHECK4-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 3623 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8* 3624 // CHECK4-NEXT: [[TMP0:%.*]] = load double, double* undef, align 8 3625 // CHECK4-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]] 3626 // CHECK4-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 3627 // CHECK4-NEXT: [[TMP1:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 3628 // CHECK4-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00 3629 // CHECK4-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 3630 // CHECK4-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64 3631 // CHECK4-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1 3632 // CHECK4-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8 3633 // CHECK4-NEXT: store i64 1, i64* [[I]], align 8 3634 // CHECK4-NEXT: [[TMP2:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 3635 // CHECK4-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]] 3636 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3637 // CHECK4: omp.precond.then: 3638 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3639 // CHECK4-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3640 // CHECK4-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8 3641 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3642 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3643 // CHECK4-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8 3644 // CHECK4-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64 3645 // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3646 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 3647 // CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]) 3648 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3649 // CHECK4: omp.dispatch.cond: 3650 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3651 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3652 // CHECK4-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]] 3653 // CHECK4-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3654 // CHECK4: cond.true: 3655 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3656 // CHECK4-NEXT: br label [[COND_END:%.*]] 3657 // CHECK4: cond.false: 3658 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3659 // CHECK4-NEXT: br label [[COND_END]] 3660 // CHECK4: cond.end: 3661 // CHECK4-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] 3662 // CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3663 // CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3664 // CHECK4-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8 3665 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3666 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3667 // CHECK4-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1 3668 // CHECK4-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]] 3669 // CHECK4-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3670 // CHECK4: omp.dispatch.body: 3671 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3672 // CHECK4: omp.inner.for.cond: 3673 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3674 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3675 // CHECK4-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1 3676 // CHECK4-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]] 3677 // CHECK4-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3678 // CHECK4: omp.inner.for.body: 3679 // CHECK4-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3680 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1 3681 // CHECK4-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]] 3682 // CHECK4-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8 3683 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3684 // CHECK4: omp.body.continue: 3685 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3686 // CHECK4: omp.inner.for.inc: 3687 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3688 // CHECK4-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1 3689 // CHECK4-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8 3690 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3691 // CHECK4: omp.inner.for.end: 3692 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3693 // CHECK4: omp.dispatch.inc: 3694 // CHECK4-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3695 // CHECK4-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 3696 // CHECK4-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]] 3697 // CHECK4-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8 3698 // CHECK4-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3699 // CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 3700 // CHECK4-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]] 3701 // CHECK4-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8 3702 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 3703 // CHECK4: omp.dispatch.end: 3704 // CHECK4-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3705 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 3706 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) 3707 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 3708 // CHECK4: omp.precond.end: 3709 // CHECK4-NEXT: ret void 3710 // 3711 // 3712 // CHECK4-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 3713 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3714 // CHECK4-NEXT: entry: 3715 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3716 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3717 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3718 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3719 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3720 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3721 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3722 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3723 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3724 // CHECK4-NEXT: ret void 3725 // 3726 // 3727 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 3728 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3729 // CHECK4-NEXT: entry: 3730 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3731 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3732 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3733 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3734 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3735 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3736 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3737 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3738 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3739 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3740 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3741 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3742 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3743 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3744 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3745 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3746 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3747 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3748 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3749 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3750 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3751 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3752 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3753 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3754 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3755 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3756 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3757 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3758 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3759 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3760 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3761 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 3762 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3763 // CHECK4: cond.true: 3764 // CHECK4-NEXT: br label [[COND_END:%.*]] 3765 // CHECK4: cond.false: 3766 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3767 // CHECK4-NEXT: br label [[COND_END]] 3768 // CHECK4: cond.end: 3769 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3770 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3771 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3772 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3773 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3774 // CHECK4: omp.inner.for.cond: 3775 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3776 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3777 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3778 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3779 // CHECK4: omp.inner.for.body: 3780 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3781 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 3782 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 3783 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3784 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 3785 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 3786 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 3787 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 3788 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 3789 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 3790 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 3791 // CHECK4-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 3792 // CHECK4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 3793 // CHECK4-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 3794 // CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 3795 // CHECK4-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 3796 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3797 // CHECK4-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 3798 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 3799 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 3800 // CHECK4-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 3801 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 3802 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 3803 // CHECK4-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 3804 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 3805 // CHECK4-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 3806 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3807 // CHECK4: omp.body.continue: 3808 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3809 // CHECK4: omp.inner.for.inc: 3810 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3811 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1 3812 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 3813 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3814 // CHECK4: omp.inner.for.end: 3815 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3816 // CHECK4: omp.loop.exit: 3817 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3818 // CHECK4-NEXT: ret void 3819 // 3820 // 3821 // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 3822 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3823 // CHECK4-NEXT: entry: 3824 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3825 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3826 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3827 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3828 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3829 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3830 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3831 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3832 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3833 // CHECK4-NEXT: ret void 3834 // 3835 // 3836 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 3837 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3838 // CHECK4-NEXT: entry: 3839 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3840 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3841 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3842 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3843 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3844 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3845 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3846 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3847 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3848 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3849 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3850 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3851 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3852 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3853 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3854 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3855 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3856 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3857 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3858 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3859 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3860 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3861 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3862 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3863 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3864 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3865 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3866 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3867 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3868 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3869 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3870 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423 3871 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3872 // CHECK4: cond.true: 3873 // CHECK4-NEXT: br label [[COND_END:%.*]] 3874 // CHECK4: cond.false: 3875 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3876 // CHECK4-NEXT: br label [[COND_END]] 3877 // CHECK4: cond.end: 3878 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3879 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3880 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3881 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3882 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3883 // CHECK4: omp.inner.for.cond: 3884 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3885 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3886 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]] 3887 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3888 // CHECK4: omp.inner.for.body: 3889 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3890 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7 3891 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 3892 // CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4 3893 // CHECK4-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8 3894 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 3895 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64 3896 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 3897 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 3898 // CHECK4-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8 3899 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4 3900 // CHECK4-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64 3901 // CHECK4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]] 3902 // CHECK4-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4 3903 // CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]] 3904 // CHECK4-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8 3905 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4 3906 // CHECK4-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64 3907 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]] 3908 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4 3909 // CHECK4-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]] 3910 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8 3911 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 3912 // CHECK4-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64 3913 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]] 3914 // CHECK4-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 3915 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3916 // CHECK4: omp.body.continue: 3917 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3918 // CHECK4: omp.inner.for.inc: 3919 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3920 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1 3921 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 3922 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3923 // CHECK4: omp.inner.for.end: 3924 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 3925 // CHECK4: omp.loop.exit: 3926 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 3927 // CHECK4-NEXT: ret void 3928 // 3929 // 3930 // CHECK4-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 3931 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3932 // CHECK4-NEXT: entry: 3933 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3934 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3935 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3936 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3937 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3938 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3939 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3940 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3941 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 3942 // CHECK4-NEXT: ret void 3943 // 3944 // 3945 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 3946 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 3947 // CHECK4-NEXT: entry: 3948 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3949 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3950 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 3951 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 3952 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 3953 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 3954 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3955 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3956 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3957 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3958 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3959 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3960 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3961 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3962 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3963 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 3964 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 3965 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 3966 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 3967 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 3968 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 3969 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 3970 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 3971 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3972 // CHECK4-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 3973 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3974 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3975 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3976 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 3977 // CHECK4-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 3978 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3979 // CHECK4: omp.dispatch.cond: 3980 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3981 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288 3982 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3983 // CHECK4: cond.true: 3984 // CHECK4-NEXT: br label [[COND_END:%.*]] 3985 // CHECK4: cond.false: 3986 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3987 // CHECK4-NEXT: br label [[COND_END]] 3988 // CHECK4: cond.end: 3989 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ] 3990 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3991 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3992 // CHECK4-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4 3993 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3994 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3995 // CHECK4-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]] 3996 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3997 // CHECK4: omp.dispatch.body: 3998 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3999 // CHECK4: omp.inner.for.cond: 4000 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4001 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4002 // CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]] 4003 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4004 // CHECK4: omp.inner.for.body: 4005 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4006 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127 4007 // CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4008 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4009 // CHECK4-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8 4010 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4 4011 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64 4012 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]] 4013 // CHECK4-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4 4014 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8 4015 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 4016 // CHECK4-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64 4017 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]] 4018 // CHECK4-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4 4019 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]] 4020 // CHECK4-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8 4021 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 4022 // CHECK4-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64 4023 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]] 4024 // CHECK4-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4 4025 // CHECK4-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]] 4026 // CHECK4-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8 4027 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 4028 // CHECK4-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64 4029 // CHECK4-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]] 4030 // CHECK4-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 4031 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4032 // CHECK4: omp.body.continue: 4033 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4034 // CHECK4: omp.inner.for.inc: 4035 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4036 // CHECK4-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1 4037 // CHECK4-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 4038 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 4039 // CHECK4: omp.inner.for.end: 4040 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4041 // CHECK4: omp.dispatch.inc: 4042 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4043 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4044 // CHECK4-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]] 4045 // CHECK4-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 4046 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4047 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4048 // CHECK4-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]] 4049 // CHECK4-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 4050 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4051 // CHECK4: omp.dispatch.end: 4052 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]]) 4053 // CHECK4-NEXT: ret void 4054 // 4055 // 4056 // CHECK4-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 4057 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4058 // CHECK4-NEXT: entry: 4059 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4060 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4061 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4062 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4063 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4064 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4065 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4066 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4067 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4068 // CHECK4-NEXT: ret void 4069 // 4070 // 4071 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 4072 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4073 // CHECK4-NEXT: entry: 4074 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4075 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4076 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4077 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4078 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4079 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4080 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4081 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 8 4082 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4083 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4084 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4085 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4086 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 4087 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4088 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4089 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4090 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4091 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4092 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4093 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4094 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 4095 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 4096 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 4097 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4098 // CHECK4-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 4099 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4100 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4101 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4102 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4103 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 35, i64 0, i64 16908287, i64 1, i64 1) 4104 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4105 // CHECK4: omp.dispatch.cond: 4106 // CHECK4-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4107 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 4108 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4109 // CHECK4: omp.dispatch.body: 4110 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4111 // CHECK4-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 4112 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4113 // CHECK4: omp.inner.for.cond: 4114 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 4115 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !4 4116 // CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 4117 // CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 4118 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4119 // CHECK4: omp.inner.for.body: 4120 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 4121 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 4122 // CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 4123 // CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !4 4124 // CHECK4-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !4 4125 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 4126 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 4127 // CHECK4-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !4 4128 // CHECK4-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !4 4129 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 4130 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 4131 // CHECK4-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !4 4132 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 4133 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !4 4134 // CHECK4-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 4135 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 4136 // CHECK4-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !4 4137 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 4138 // CHECK4-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !4 4139 // CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !4 4140 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 4141 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !4 4142 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4143 // CHECK4: omp.body.continue: 4144 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4145 // CHECK4: omp.inner.for.inc: 4146 // CHECK4-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 4147 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 4148 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !4 4149 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 4150 // CHECK4: omp.inner.for.end: 4151 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4152 // CHECK4: omp.dispatch.inc: 4153 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4154 // CHECK4: omp.dispatch.end: 4155 // CHECK4-NEXT: ret void 4156 // 4157 // 4158 // CHECK4-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 4159 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4160 // CHECK4-NEXT: entry: 4161 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4162 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4163 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4164 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4165 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4166 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4167 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4168 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4169 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4170 // CHECK4-NEXT: ret void 4171 // 4172 // 4173 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 4174 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4175 // CHECK4-NEXT: entry: 4176 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4177 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4178 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4179 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4180 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4181 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4182 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4183 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 8 4184 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4185 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4186 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4187 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4188 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 4189 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4190 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4191 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4192 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4193 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4194 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4195 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4196 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 4197 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 4198 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 4199 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4200 // CHECK4-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 4201 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4202 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4203 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4204 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4205 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 36, i64 0, i64 16908287, i64 1, i64 7) 4206 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4207 // CHECK4: omp.dispatch.cond: 4208 // CHECK4-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4209 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 4210 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4211 // CHECK4: omp.dispatch.body: 4212 // CHECK4-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4213 // CHECK4-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8 4214 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4215 // CHECK4: omp.inner.for.cond: 4216 // CHECK4-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 4217 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !7 4218 // CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1 4219 // CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]] 4220 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4221 // CHECK4: omp.inner.for.body: 4222 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 4223 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127 4224 // CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 4225 // CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !7 4226 // CHECK4-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !7 4227 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 4228 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]] 4229 // CHECK4-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !7 4230 // CHECK4-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !7 4231 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 4232 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]] 4233 // CHECK4-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !7 4234 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]] 4235 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !7 4236 // CHECK4-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 4237 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]] 4238 // CHECK4-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !7 4239 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]] 4240 // CHECK4-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !7 4241 // CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !7 4242 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]] 4243 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !7 4244 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4245 // CHECK4: omp.body.continue: 4246 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4247 // CHECK4: omp.inner.for.inc: 4248 // CHECK4-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 4249 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1 4250 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !7 4251 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 4252 // CHECK4: omp.inner.for.end: 4253 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4254 // CHECK4: omp.dispatch.inc: 4255 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4256 // CHECK4: omp.dispatch.end: 4257 // CHECK4-NEXT: ret void 4258 // 4259 // 4260 // CHECK4-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 4261 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4262 // CHECK4-NEXT: entry: 4263 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4264 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4265 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4266 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4267 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 4268 // CHECK4-NEXT: [[Y:%.*]] = alloca i32, align 4 4269 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4270 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4271 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4272 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4273 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 4274 // CHECK4-NEXT: store i32 0, i32* [[Y]], align 4 4275 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[Y]], float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4276 // CHECK4-NEXT: ret void 4277 // 4278 // 4279 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 4280 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4281 // CHECK4-NEXT: entry: 4282 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4283 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4284 // CHECK4-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 4285 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4286 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4287 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4288 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4289 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4290 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 4291 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4292 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4293 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 4294 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 4295 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 4296 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4297 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4298 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4299 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4300 // CHECK4-NEXT: [[I7:%.*]] = alloca i8, align 1 4301 // CHECK4-NEXT: [[X8:%.*]] = alloca i32, align 4 4302 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4303 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4304 // CHECK4-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 4305 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4306 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4307 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4308 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4309 // CHECK4-NEXT: [[TMP0:%.*]] = load i32*, i32** [[Y_ADDR]], align 8 4310 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[A_ADDR]], align 8 4311 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[B_ADDR]], align 8 4312 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[C_ADDR]], align 8 4313 // CHECK4-NEXT: [[TMP4:%.*]] = load float**, float*** [[D_ADDR]], align 8 4314 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4 4315 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8 4316 // CHECK4-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 4317 // CHECK4-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4318 // CHECK4-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32 4319 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 4320 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 4321 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4322 // CHECK4-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 4323 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 4324 // CHECK4-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 4325 // CHECK4-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 4326 // CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4327 // CHECK4-NEXT: store i8 [[TMP7]], i8* [[I]], align 1 4328 // CHECK4-NEXT: store i32 11, i32* [[X]], align 4 4329 // CHECK4-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4330 // CHECK4-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32 4331 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 4332 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4333 // CHECK4: omp.precond.then: 4334 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4335 // CHECK4-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 4336 // CHECK4-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 4337 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4338 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4339 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 4340 // CHECK4-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4341 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4 4342 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP12]], i32 38, i64 0, i64 [[TMP10]], i64 1, i64 1) 4343 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4344 // CHECK4: omp.dispatch.cond: 4345 // CHECK4-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4346 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4 4347 // CHECK4-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4348 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0 4349 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4350 // CHECK4: omp.dispatch.body: 4351 // CHECK4-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4352 // CHECK4-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 4353 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4354 // CHECK4: omp.inner.for.cond: 4355 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 4356 // CHECK4-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !10 4357 // CHECK4-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 4358 // CHECK4-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4359 // CHECK4: omp.inner.for.body: 4360 // CHECK4-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !10 4361 // CHECK4-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64 4362 // CHECK4-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 4363 // CHECK4-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11 4364 // CHECK4-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 4365 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 4366 // CHECK4-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 4367 // CHECK4-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !10 4368 // CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 4369 // CHECK4-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 4370 // CHECK4-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11 4371 // CHECK4-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 4372 // CHECK4-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]] 4373 // CHECK4-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 4374 // CHECK4-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 4375 // CHECK4-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 4376 // CHECK4-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !10 4377 // CHECK4-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !10 4378 // CHECK4-NEXT: [[TMP24:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 4379 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64 4380 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM]] 4381 // CHECK4-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !10 4382 // CHECK4-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !10 4383 // CHECK4-NEXT: [[TMP27:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 4384 // CHECK4-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64 4385 // CHECK4-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM21]] 4386 // CHECK4-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !10 4387 // CHECK4-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]] 4388 // CHECK4-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !10 4389 // CHECK4-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 4390 // CHECK4-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64 4391 // CHECK4-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM24]] 4392 // CHECK4-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !10 4393 // CHECK4-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]] 4394 // CHECK4-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !10 4395 // CHECK4-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !10 4396 // CHECK4-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64 4397 // CHECK4-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM27]] 4398 // CHECK4-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !10 4399 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4400 // CHECK4: omp.body.continue: 4401 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4402 // CHECK4: omp.inner.for.inc: 4403 // CHECK4-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 4404 // CHECK4-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1 4405 // CHECK4-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !10 4406 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP11:![0-9]+]] 4407 // CHECK4: omp.inner.for.end: 4408 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4409 // CHECK4: omp.dispatch.inc: 4410 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4411 // CHECK4: omp.dispatch.end: 4412 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 4413 // CHECK4: omp.precond.end: 4414 // CHECK4-NEXT: ret void 4415 // 4416 // 4417 // CHECK4-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 4418 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4419 // CHECK4-NEXT: entry: 4420 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4421 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4422 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4423 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4424 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 4425 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4426 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4427 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4428 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4429 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 4430 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]) 4431 // CHECK4-NEXT: ret void 4432 // 4433 // 4434 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 4435 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] { 4436 // CHECK4-NEXT: entry: 4437 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4438 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4439 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4440 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4441 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4442 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4443 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4444 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 4445 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4446 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4447 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4448 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4449 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4450 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 4451 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 4452 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4453 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4454 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4455 // CHECK4-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4456 // CHECK4-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4457 // CHECK4-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4458 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4459 // CHECK4-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8 4460 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8 4461 // CHECK4-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8 4462 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4463 // CHECK4-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 4464 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4465 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4466 // CHECK4-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4467 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4 4468 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32 37, i32 0, i32 199, i32 1, i32 1) 4469 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4470 // CHECK4: omp.dispatch.cond: 4471 // CHECK4-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4472 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0 4473 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4474 // CHECK4: omp.dispatch.body: 4475 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4476 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 4477 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4478 // CHECK4: omp.inner.for.cond: 4479 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4480 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !13 4481 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]] 4482 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4483 // CHECK4: omp.inner.for.body: 4484 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4485 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20 4486 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 4487 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 4488 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 4489 // CHECK4-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !13 4490 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4491 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4492 // CHECK4-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20 4493 // CHECK4-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 4494 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]] 4495 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 4496 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 4497 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !13 4498 // CHECK4-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !llvm.access.group !13 4499 // CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 4500 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64 4501 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 4502 // CHECK4-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !13 4503 // CHECK4-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !13 4504 // CHECK4-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 4505 // CHECK4-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64 4506 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM6]] 4507 // CHECK4-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !13 4508 // CHECK4-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]] 4509 // CHECK4-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !llvm.access.group !13 4510 // CHECK4-NEXT: [[TMP20:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 4511 // CHECK4-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64 4512 // CHECK4-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM9]] 4513 // CHECK4-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !13 4514 // CHECK4-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]] 4515 // CHECK4-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !llvm.access.group !13 4516 // CHECK4-NEXT: [[TMP23:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !13 4517 // CHECK4-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64 4518 // CHECK4-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM12]] 4519 // CHECK4-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !13 4520 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4521 // CHECK4: omp.body.continue: 4522 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4523 // CHECK4: omp.inner.for.inc: 4524 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4525 // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1 4526 // CHECK4-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !13 4527 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP14:![0-9]+]] 4528 // CHECK4: omp.inner.for.end: 4529 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4530 // CHECK4: omp.dispatch.inc: 4531 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4532 // CHECK4: omp.dispatch.end: 4533 // CHECK4-NEXT: ret void 4534 // 4535 // 4536 // CHECK4-LABEL: define {{[^@]+}}@_Z3foov 4537 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 4538 // CHECK4-NEXT: entry: 4539 // CHECK4-NEXT: call void @_Z8mayThrowv() 4540 // CHECK4-NEXT: ret i32 0 4541 // 4542 // 4543 // CHECK4-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 4544 // CHECK4-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { 4545 // CHECK4-NEXT: entry: 4546 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4547 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4548 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4549 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4550 // CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 4551 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4552 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4553 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4554 // CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 4555 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 4556 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 4557 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 4558 // CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 4559 // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4 4560 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* 4561 // CHECK4-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 4562 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 4563 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]) 4564 // CHECK4-NEXT: [[TMP5:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4565 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]) 4566 // CHECK4-NEXT: ret void 4567 // 4568 // 4569 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 4570 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 4571 // CHECK4-NEXT: entry: 4572 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4573 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4574 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4575 // CHECK4-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 4576 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 4577 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4578 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 4579 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4580 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4581 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4582 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4583 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4584 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4585 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 4586 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4587 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4588 // CHECK4-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4589 // CHECK4-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 4590 // CHECK4-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 4591 // CHECK4-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8 4592 // CHECK4-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8 4593 // CHECK4-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* 4594 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4595 // CHECK4-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 4596 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4597 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4598 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 4599 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 4600 // CHECK4-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16 4601 // CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 4602 // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4603 // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4 4604 // CHECK4-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 4605 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4606 // CHECK4: omp.dispatch.cond: 4607 // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4608 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288 4609 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4610 // CHECK4: cond.true: 4611 // CHECK4-NEXT: br label [[COND_END:%.*]] 4612 // CHECK4: cond.false: 4613 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4614 // CHECK4-NEXT: br label [[COND_END]] 4615 // CHECK4: cond.end: 4616 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ] 4617 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4618 // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4619 // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4 4620 // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4621 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4622 // CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]] 4623 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 4624 // CHECK4: omp.dispatch.cleanup: 4625 // CHECK4-NEXT: br label [[OMP_DISPATCH_END:%.*]] 4626 // CHECK4: omp.dispatch.body: 4627 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4628 // CHECK4: omp.inner.for.cond: 4629 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4630 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4631 // CHECK4-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]] 4632 // CHECK4-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4633 // CHECK4: omp.inner.for.cond.cleanup: 4634 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4635 // CHECK4: omp.inner.for.body: 4636 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4637 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127 4638 // CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4639 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4640 // CHECK4-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 4641 // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 4642 // CHECK4: invoke.cont: 4643 // CHECK4-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float 4644 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4 4645 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64 4646 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] 4647 // CHECK4-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4 4648 // CHECK4-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]] 4649 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8 4650 // CHECK4-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float 4651 // CHECK4-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] 4652 // CHECK4-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8 4653 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4 4654 // CHECK4-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64 4655 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]] 4656 // CHECK4-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4 4657 // CHECK4-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]] 4658 // CHECK4-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4 4659 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4660 // CHECK4: omp.body.continue: 4661 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4662 // CHECK4: omp.inner.for.inc: 4663 // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4664 // CHECK4-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1 4665 // CHECK4-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 4666 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 4667 // CHECK4: omp.inner.for.end: 4668 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4669 // CHECK4: omp.dispatch.inc: 4670 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4671 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4672 // CHECK4-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]] 4673 // CHECK4-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 4674 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4675 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4676 // CHECK4-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]] 4677 // CHECK4-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 4678 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4679 // CHECK4: omp.dispatch.end: 4680 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP4]]) 4681 // CHECK4-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4682 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]) 4683 // CHECK4-NEXT: ret void 4684 // CHECK4: terminate.lpad: 4685 // CHECK4-NEXT: [[TMP25:%.*]] = landingpad { i8*, i32 } 4686 // CHECK4-NEXT: catch i8* null 4687 // CHECK4-NEXT: [[TMP26:%.*]] = extractvalue { i8*, i32 } [[TMP25]], 0 4688 // CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]] 4689 // CHECK4-NEXT: unreachable 4690 // 4691 // 4692 // CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate 4693 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 4694 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 4695 // CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 4696 // CHECK4-NEXT: unreachable 4697 // 4698 // 4699 // CHECK5-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 4700 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { 4701 // CHECK5-NEXT: entry: 4702 // CHECK5-NEXT: [[A:%.*]] = alloca double, align 8 4703 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4704 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 4705 // CHECK5-NEXT: store double 5.000000e+00, double* [[A]], align 8, !dbg [[DBG9:![0-9]+]] 4706 // CHECK5-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8, !dbg [[DBG10:![0-9]+]] 4707 // CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG10]] 4708 // CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG10]] 4709 // CHECK5-NEXT: [[TMP1:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG10]] 4710 // CHECK5-NEXT: [[CONV1:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i8*, !dbg [[DBG10]] 4711 // CHECK5-NEXT: store i8 [[TMP1]], i8* [[CONV1]], align 1, !dbg [[DBG10]] 4712 // CHECK5-NEXT: [[TMP2:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8, !dbg [[DBG10]] 4713 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP2]]), !dbg [[DBG10]] 4714 // CHECK5-NEXT: ret void, !dbg [[DBG11:![0-9]+]] 4715 // 4716 // 4717 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 4718 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG12:![0-9]+]] { 4719 // CHECK5-NEXT: entry: 4720 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4721 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4722 // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 4723 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4724 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4725 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 4726 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 4727 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 4728 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4729 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4730 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4731 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4732 // CHECK5-NEXT: [[A:%.*]] = alloca double, align 8 4733 // CHECK5-NEXT: [[I5:%.*]] = alloca i64, align 8 4734 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4735 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4736 // CHECK5-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 4737 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i8*, !dbg [[DBG13:![0-9]+]] 4738 // CHECK5-NEXT: [[TMP0:%.*]] = load double, double* undef, align 8, !dbg [[DBG14:![0-9]+]] 4739 // CHECK5-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP0]], !dbg [[DBG14]] 4740 // CHECK5-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]] 4741 // CHECK5-NEXT: [[TMP1:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]] 4742 // CHECK5-NEXT: [[SUB:%.*]] = fsub double [[TMP1]], 1.000000e+00, !dbg [[DBG14]] 4743 // CHECK5-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00, !dbg [[DBG14]] 4744 // CHECK5-NEXT: [[CONV3:%.*]] = fptoui double [[DIV]] to i64, !dbg [[DBG14]] 4745 // CHECK5-NEXT: [[SUB4:%.*]] = sub i64 [[CONV3]], 1, !dbg [[DBG14]] 4746 // CHECK5-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]] 4747 // CHECK5-NEXT: store i64 1, i64* [[I]], align 8, !dbg [[DBG14]] 4748 // CHECK5-NEXT: [[TMP2:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG14]] 4749 // CHECK5-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP2]], !dbg [[DBG14]] 4750 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG13]] 4751 // CHECK5: omp.precond.then: 4752 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG14]] 4753 // CHECK5-NEXT: [[TMP3:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]] 4754 // CHECK5-NEXT: store i64 [[TMP3]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]] 4755 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]] 4756 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG14]] 4757 // CHECK5-NEXT: [[TMP4:%.*]] = load i8, i8* [[CONV]], align 8, !dbg [[DBG13]] 4758 // CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG13]] 4759 // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG13]] 4760 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4, !dbg [[DBG13]] 4761 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV6]]), !dbg [[DBG13]] 4762 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG13]] 4763 // CHECK5: omp.dispatch.cond: 4764 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]] 4765 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]] 4766 // CHECK5-NEXT: [[CMP7:%.*]] = icmp ugt i64 [[TMP7]], [[TMP8]], !dbg [[DBG14]] 4767 // CHECK5-NEXT: br i1 [[CMP7]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG14]] 4768 // CHECK5: cond.true: 4769 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG14]] 4770 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG14]] 4771 // CHECK5: cond.false: 4772 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]] 4773 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG14]] 4774 // CHECK5: cond.end: 4775 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ], !dbg [[DBG14]] 4776 // CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]] 4777 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG14]] 4778 // CHECK5-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG14]] 4779 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG14]] 4780 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]] 4781 // CHECK5-NEXT: [[ADD8:%.*]] = add i64 [[TMP13]], 1, !dbg [[DBG14]] 4782 // CHECK5-NEXT: [[CMP9:%.*]] = icmp ult i64 [[TMP12]], [[ADD8]], !dbg [[DBG14]] 4783 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG13]] 4784 // CHECK5: omp.dispatch.body: 4785 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG13]] 4786 // CHECK5: omp.inner.for.cond: 4787 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG14]] 4788 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]] 4789 // CHECK5-NEXT: [[ADD10:%.*]] = add i64 [[TMP15]], 1, !dbg [[DBG14]] 4790 // CHECK5-NEXT: [[CMP11:%.*]] = icmp ult i64 [[TMP14]], [[ADD10]], !dbg [[DBG14]] 4791 // CHECK5-NEXT: br i1 [[CMP11]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG13]] 4792 // CHECK5: omp.inner.for.body: 4793 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG14]] 4794 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP16]], 1, !dbg [[DBG14]] 4795 // CHECK5-NEXT: [[ADD12:%.*]] = add i64 1, [[MUL]], !dbg [[DBG14]] 4796 // CHECK5-NEXT: store i64 [[ADD12]], i64* [[I5]], align 8, !dbg [[DBG14]] 4797 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG15:![0-9]+]] 4798 // CHECK5: omp.body.continue: 4799 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG13]] 4800 // CHECK5: omp.inner.for.inc: 4801 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG14]] 4802 // CHECK5-NEXT: [[ADD13:%.*]] = add i64 [[TMP17]], 1, !dbg [[DBG14]] 4803 // CHECK5-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG14]] 4804 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG13]], !llvm.loop [[LOOP16:![0-9]+]] 4805 // CHECK5: omp.inner.for.end: 4806 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG13]] 4807 // CHECK5: omp.dispatch.inc: 4808 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG14]] 4809 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]] 4810 // CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP18]], [[TMP19]], !dbg [[DBG14]] 4811 // CHECK5-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_LB]], align 8, !dbg [[DBG14]] 4812 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]] 4813 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG14]] 4814 // CHECK5-NEXT: [[ADD15:%.*]] = add i64 [[TMP20]], [[TMP21]], !dbg [[DBG14]] 4815 // CHECK5-NEXT: store i64 [[ADD15]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG14]] 4816 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG13]], !llvm.loop [[LOOP17:![0-9]+]] 4817 // CHECK5: omp.dispatch.end: 4818 // CHECK5-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG13]] 4819 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4, !dbg [[DBG13]] 4820 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP23]]), !dbg [[DBG13]] 4821 // CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG13]] 4822 // CHECK5: omp.precond.end: 4823 // CHECK5-NEXT: ret void, !dbg [[DBG15]] 4824 // 4825 // 4826 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 4827 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG20:![0-9]+]] { 4828 // CHECK5-NEXT: entry: 4829 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4830 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4831 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4832 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4833 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4834 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4835 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4836 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4837 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB9:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG21:![0-9]+]] 4838 // CHECK5-NEXT: ret void, !dbg [[DBG22:![0-9]+]] 4839 // 4840 // 4841 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 4842 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG23:![0-9]+]] { 4843 // CHECK5-NEXT: entry: 4844 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4845 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4846 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4847 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4848 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4849 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4850 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4851 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4852 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4853 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4854 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4855 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4856 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4857 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4858 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4859 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4860 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4861 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4862 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4863 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG24:![0-9]+]] 4864 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG24]] 4865 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG24]] 4866 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG24]] 4867 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG25:![0-9]+]] 4868 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG25]] 4869 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG25]] 4870 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG25]] 4871 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG24]] 4872 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG24]] 4873 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG24]] 4874 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG25]] 4875 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG25]] 4876 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG25]] 4877 // CHECK5: cond.true: 4878 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG25]] 4879 // CHECK5: cond.false: 4880 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG25]] 4881 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG25]] 4882 // CHECK5: cond.end: 4883 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG25]] 4884 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG25]] 4885 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG25]] 4886 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG25]] 4887 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG24]] 4888 // CHECK5: omp.inner.for.cond: 4889 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG25]] 4890 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG25]] 4891 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG25]] 4892 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG24]] 4893 // CHECK5: omp.inner.for.body: 4894 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG25]] 4895 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG25]] 4896 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]], !dbg [[DBG25]] 4897 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG25]] 4898 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG26:![0-9]+]] 4899 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG26]] 4900 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG26]] 4901 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG26]] 4902 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG26]] 4903 // CHECK5-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG26]] 4904 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG26]] 4905 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG26]] 4906 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG26]] 4907 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !dbg [[DBG26]] 4908 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG26]] 4909 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG26]] 4910 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG26]] 4911 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG26]] 4912 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG26]] 4913 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG26]] 4914 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG26]] 4915 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG26]] 4916 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG26]] 4917 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG26]] 4918 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG26]] 4919 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG26]] 4920 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG27:![0-9]+]] 4921 // CHECK5: omp.body.continue: 4922 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG24]] 4923 // CHECK5: omp.inner.for.inc: 4924 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG25]] 4925 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG25]] 4926 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG25]] 4927 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG24]], !llvm.loop [[LOOP28:![0-9]+]] 4928 // CHECK5: omp.inner.for.end: 4929 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG24]] 4930 // CHECK5: omp.loop.exit: 4931 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB8:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG24]] 4932 // CHECK5-NEXT: ret void, !dbg [[DBG27]] 4933 // 4934 // 4935 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4936 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG29:![0-9]+]] { 4937 // CHECK5-NEXT: entry: 4938 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4939 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4940 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4941 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4942 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4943 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4944 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4945 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4946 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB14:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG30:![0-9]+]] 4947 // CHECK5-NEXT: ret void, !dbg [[DBG31:![0-9]+]] 4948 // 4949 // 4950 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 4951 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG32:![0-9]+]] { 4952 // CHECK5-NEXT: entry: 4953 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4954 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4955 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 4956 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 4957 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 4958 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 4959 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4960 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 4961 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4962 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4963 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4964 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4965 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 4966 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4967 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4968 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 4969 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 4970 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 4971 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 4972 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG33:![0-9]+]] 4973 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG33]] 4974 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG33]] 4975 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG33]] 4976 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG34:![0-9]+]] 4977 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG34]] 4978 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG34]] 4979 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG34]] 4980 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG33]] 4981 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG33]] 4982 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB11:[0-9]+]], i32 [[TMP5]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG33]] 4983 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG34]] 4984 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP6]], 4571423, !dbg [[DBG34]] 4985 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG34]] 4986 // CHECK5: cond.true: 4987 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG34]] 4988 // CHECK5: cond.false: 4989 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG34]] 4990 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG34]] 4991 // CHECK5: cond.end: 4992 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG34]] 4993 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG34]] 4994 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG34]] 4995 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG34]] 4996 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG33]] 4997 // CHECK5: omp.inner.for.cond: 4998 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG34]] 4999 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG34]] 5000 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP9]], [[TMP10]], !dbg [[DBG34]] 5001 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG33]] 5002 // CHECK5: omp.inner.for.body: 5003 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG34]] 5004 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP11]], 7, !dbg [[DBG34]] 5005 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]], !dbg [[DBG34]] 5006 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !dbg [[DBG34]] 5007 // CHECK5-NEXT: [[TMP12:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG35:![0-9]+]] 5008 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG35]] 5009 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP13]] to i64, !dbg [[DBG35]] 5010 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]], !dbg [[DBG35]] 5011 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG35]] 5012 // CHECK5-NEXT: [[TMP15:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG35]] 5013 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG35]] 5014 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP16]] to i64, !dbg [[DBG35]] 5015 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP15]], i64 [[IDXPROM2]], !dbg [[DBG35]] 5016 // CHECK5-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !dbg [[DBG35]] 5017 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP17]], !dbg [[DBG35]] 5018 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG35]] 5019 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG35]] 5020 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP19]] to i64, !dbg [[DBG35]] 5021 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM5]], !dbg [[DBG35]] 5022 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG35]] 5023 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP20]], !dbg [[DBG35]] 5024 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG35]] 5025 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG35]] 5026 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP22]] to i64, !dbg [[DBG35]] 5027 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM8]], !dbg [[DBG35]] 5028 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG35]] 5029 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG36:![0-9]+]] 5030 // CHECK5: omp.body.continue: 5031 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG33]] 5032 // CHECK5: omp.inner.for.inc: 5033 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG34]] 5034 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP23]], 1, !dbg [[DBG34]] 5035 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG34]] 5036 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG33]], !llvm.loop [[LOOP37:![0-9]+]] 5037 // CHECK5: omp.inner.for.end: 5038 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG33]] 5039 // CHECK5: omp.loop.exit: 5040 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB13:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG33]] 5041 // CHECK5-NEXT: ret void, !dbg [[DBG36]] 5042 // 5043 // 5044 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 5045 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG38:![0-9]+]] { 5046 // CHECK5-NEXT: entry: 5047 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5048 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5049 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5050 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5051 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5052 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5053 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5054 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5055 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB19:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG39:![0-9]+]] 5056 // CHECK5-NEXT: ret void, !dbg [[DBG40:![0-9]+]] 5057 // 5058 // 5059 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 5060 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG41:![0-9]+]] { 5061 // CHECK5-NEXT: entry: 5062 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5063 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5064 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 5065 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 5066 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 5067 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 5068 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5069 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5070 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5071 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5072 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5073 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5074 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5075 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5076 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5077 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 5078 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 5079 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 5080 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 5081 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG42:![0-9]+]] 5082 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG42]] 5083 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG42]] 5084 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG42]] 5085 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG43:![0-9]+]] 5086 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]] 5087 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG43]] 5088 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG43]] 5089 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG42]] 5090 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG42]] 5091 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB16:[0-9]+]], i32 [[TMP5]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG42]] 5092 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG42]] 5093 // CHECK5: omp.dispatch.cond: 5094 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]] 5095 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP6]], 16908288, !dbg [[DBG43]] 5096 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG43]] 5097 // CHECK5: cond.true: 5098 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG43]] 5099 // CHECK5: cond.false: 5100 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]] 5101 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG43]] 5102 // CHECK5: cond.end: 5103 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP7]], [[COND_FALSE]] ], !dbg [[DBG43]] 5104 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]] 5105 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG43]] 5106 // CHECK5-NEXT: store i32 [[TMP8]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG43]] 5107 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG43]] 5108 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]] 5109 // CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP9]], [[TMP10]], !dbg [[DBG43]] 5110 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG42]] 5111 // CHECK5: omp.dispatch.body: 5112 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG42]] 5113 // CHECK5: omp.inner.for.cond: 5114 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG43]] 5115 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]] 5116 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP11]], [[TMP12]], !dbg [[DBG43]] 5117 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG42]] 5118 // CHECK5: omp.inner.for.body: 5119 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG43]] 5120 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP13]], 127, !dbg [[DBG43]] 5121 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG43]] 5122 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG43]] 5123 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG44:![0-9]+]] 5124 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG44]] 5125 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP15]] to i64, !dbg [[DBG44]] 5126 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[IDXPROM]], !dbg [[DBG44]] 5127 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG44]] 5128 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG44]] 5129 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG44]] 5130 // CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP18]] to i64, !dbg [[DBG44]] 5131 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM3]], !dbg [[DBG44]] 5132 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG44]] 5133 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP16]], [[TMP19]], !dbg [[DBG44]] 5134 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG44]] 5135 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG44]] 5136 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP21]] to i64, !dbg [[DBG44]] 5137 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM6]], !dbg [[DBG44]] 5138 // CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG44]] 5139 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP22]], !dbg [[DBG44]] 5140 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG44]] 5141 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG44]] 5142 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP24]] to i64, !dbg [[DBG44]] 5143 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM9]], !dbg [[DBG44]] 5144 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !dbg [[DBG44]] 5145 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG45:![0-9]+]] 5146 // CHECK5: omp.body.continue: 5147 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG42]] 5148 // CHECK5: omp.inner.for.inc: 5149 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG43]] 5150 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP25]], 1, !dbg [[DBG43]] 5151 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG43]] 5152 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG42]], !llvm.loop [[LOOP46:![0-9]+]] 5153 // CHECK5: omp.inner.for.end: 5154 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG42]] 5155 // CHECK5: omp.dispatch.inc: 5156 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG43]] 5157 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG43]] 5158 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP26]], [[TMP27]], !dbg [[DBG43]] 5159 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG43]] 5160 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]] 5161 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG43]] 5162 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP28]], [[TMP29]], !dbg [[DBG43]] 5163 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG43]] 5164 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG42]], !llvm.loop [[LOOP47:![0-9]+]] 5165 // CHECK5: omp.dispatch.end: 5166 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB18:[0-9]+]], i32 [[TMP5]]), !dbg [[DBG42]] 5167 // CHECK5-NEXT: ret void, !dbg [[DBG45]] 5168 // 5169 // 5170 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 5171 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG48:![0-9]+]] { 5172 // CHECK5-NEXT: entry: 5173 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5174 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5175 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5176 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5177 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5178 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5179 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5180 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5181 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB21:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG49:![0-9]+]] 5182 // CHECK5-NEXT: ret void, !dbg [[DBG50:![0-9]+]] 5183 // 5184 // 5185 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 5186 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG51:![0-9]+]] { 5187 // CHECK5-NEXT: entry: 5188 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5189 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5190 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 5191 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 5192 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 5193 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 5194 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5195 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 5196 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5197 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5198 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5199 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5200 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 5201 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5202 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5203 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 5204 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 5205 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 5206 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 5207 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG52:![0-9]+]] 5208 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG52]] 5209 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG52]] 5210 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG52]] 5211 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG53:![0-9]+]] 5212 // CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG53]] 5213 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG53]] 5214 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG53]] 5215 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG52]] 5216 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG52]] 5217 // CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB21]], i32 [[TMP5]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1), !dbg [[DBG52]] 5218 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG52]] 5219 // CHECK5: omp.dispatch.cond: 5220 // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB21]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG52]] 5221 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG52]] 5222 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG52]] 5223 // CHECK5: omp.dispatch.body: 5224 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG53]] 5225 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG53]] 5226 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG52]] 5227 // CHECK5: omp.inner.for.cond: 5228 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG53]], !llvm.access.group !54 5229 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG53]], !llvm.access.group !54 5230 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG53]] 5231 // CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG53]] 5232 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG52]] 5233 // CHECK5: omp.inner.for.body: 5234 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG53]], !llvm.access.group !54 5235 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG53]] 5236 // CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG53]] 5237 // CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG53]], !llvm.access.group !54 5238 // CHECK5-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG55:![0-9]+]], !llvm.access.group !54 5239 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG55]], !llvm.access.group !54 5240 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]], !dbg [[DBG55]] 5241 // CHECK5-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG55]], !llvm.access.group !54 5242 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG55]], !llvm.access.group !54 5243 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG55]], !llvm.access.group !54 5244 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]], !dbg [[DBG55]] 5245 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG55]], !llvm.access.group !54 5246 // CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG55]] 5247 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG55]], !llvm.access.group !54 5248 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG55]], !llvm.access.group !54 5249 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]], !dbg [[DBG55]] 5250 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG55]], !llvm.access.group !54 5251 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG55]] 5252 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG55]], !llvm.access.group !54 5253 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG55]], !llvm.access.group !54 5254 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]], !dbg [[DBG55]] 5255 // CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG55]], !llvm.access.group !54 5256 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG56:![0-9]+]] 5257 // CHECK5: omp.body.continue: 5258 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG52]] 5259 // CHECK5: omp.inner.for.inc: 5260 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG53]], !llvm.access.group !54 5261 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG53]] 5262 // CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG53]], !llvm.access.group !54 5263 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG52]], !llvm.loop [[LOOP57:![0-9]+]] 5264 // CHECK5: omp.inner.for.end: 5265 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG52]] 5266 // CHECK5: omp.dispatch.inc: 5267 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG52]], !llvm.loop [[LOOP59:![0-9]+]] 5268 // CHECK5: omp.dispatch.end: 5269 // CHECK5-NEXT: ret void, !dbg [[DBG56]] 5270 // 5271 // 5272 // CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 5273 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG60:![0-9]+]] { 5274 // CHECK5-NEXT: entry: 5275 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5276 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5277 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5278 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5279 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5280 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5281 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5282 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5283 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB23:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG61:![0-9]+]] 5284 // CHECK5-NEXT: ret void, !dbg [[DBG62:![0-9]+]] 5285 // 5286 // 5287 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 5288 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG63:![0-9]+]] { 5289 // CHECK5-NEXT: entry: 5290 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5291 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5292 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 5293 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 5294 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 5295 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 5296 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5297 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 5298 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5299 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5300 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5301 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5302 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 5303 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5304 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5305 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 5306 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 5307 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 5308 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 5309 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG64:![0-9]+]] 5310 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG64]] 5311 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG64]] 5312 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG64]] 5313 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG65:![0-9]+]] 5314 // CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG65]] 5315 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG65]] 5316 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG65]] 5317 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG64]] 5318 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG64]] 5319 // CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB23]], i32 [[TMP5]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7), !dbg [[DBG64]] 5320 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG64]] 5321 // CHECK5: omp.dispatch.cond: 5322 // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB23]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG64]] 5323 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG64]] 5324 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG64]] 5325 // CHECK5: omp.dispatch.body: 5326 // CHECK5-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG65]] 5327 // CHECK5-NEXT: store i64 [[TMP7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG65]] 5328 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG64]] 5329 // CHECK5: omp.inner.for.cond: 5330 // CHECK5-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG65]], !llvm.access.group !66 5331 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG65]], !llvm.access.group !66 5332 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP9]], 1, !dbg [[DBG65]] 5333 // CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP8]], [[ADD]], !dbg [[DBG65]] 5334 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG64]] 5335 // CHECK5: omp.inner.for.body: 5336 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG65]], !llvm.access.group !66 5337 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP10]], 127, !dbg [[DBG65]] 5338 // CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG65]] 5339 // CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG65]], !llvm.access.group !66 5340 // CHECK5-NEXT: [[TMP11:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG67:![0-9]+]], !llvm.access.group !66 5341 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG67]], !llvm.access.group !66 5342 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP12]], !dbg [[DBG67]] 5343 // CHECK5-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG67]], !llvm.access.group !66 5344 // CHECK5-NEXT: [[TMP14:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG67]], !llvm.access.group !66 5345 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG67]], !llvm.access.group !66 5346 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP14]], i64 [[TMP15]], !dbg [[DBG67]] 5347 // CHECK5-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG67]], !llvm.access.group !66 5348 // CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP16]], !dbg [[DBG67]] 5349 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG67]], !llvm.access.group !66 5350 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG67]], !llvm.access.group !66 5351 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[TMP18]], !dbg [[DBG67]] 5352 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG67]], !llvm.access.group !66 5353 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP19]], !dbg [[DBG67]] 5354 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG67]], !llvm.access.group !66 5355 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG67]], !llvm.access.group !66 5356 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[TMP21]], !dbg [[DBG67]] 5357 // CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG67]], !llvm.access.group !66 5358 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG68:![0-9]+]] 5359 // CHECK5: omp.body.continue: 5360 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG64]] 5361 // CHECK5: omp.inner.for.inc: 5362 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG65]], !llvm.access.group !66 5363 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP22]], 1, !dbg [[DBG65]] 5364 // CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG65]], !llvm.access.group !66 5365 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG64]], !llvm.loop [[LOOP69:![0-9]+]] 5366 // CHECK5: omp.inner.for.end: 5367 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG64]] 5368 // CHECK5: omp.dispatch.inc: 5369 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG64]], !llvm.loop [[LOOP71:![0-9]+]] 5370 // CHECK5: omp.dispatch.end: 5371 // CHECK5-NEXT: ret void, !dbg [[DBG68]] 5372 // 5373 // 5374 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 5375 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG72:![0-9]+]] { 5376 // CHECK5-NEXT: entry: 5377 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5378 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5379 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5380 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5381 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5382 // CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 4 5383 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5384 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5385 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5386 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5387 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG73:![0-9]+]] 5388 // CHECK5-NEXT: store i32 0, i32* [[Y]], align 4, !dbg [[DBG74:![0-9]+]] 5389 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB25:[0-9]+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* [[Y]], float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG75:![0-9]+]] 5390 // CHECK5-NEXT: ret void, !dbg [[DBG76:![0-9]+]] 5391 // 5392 // 5393 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 5394 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[Y:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG77:![0-9]+]] { 5395 // CHECK5-NEXT: entry: 5396 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5397 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5398 // CHECK5-NEXT: [[Y_ADDR:%.*]] = alloca i32*, align 8 5399 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 5400 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 5401 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 5402 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 5403 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5404 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 5405 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 5406 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 5407 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 5408 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 5409 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5410 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5411 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5412 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5413 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5414 // CHECK5-NEXT: [[I7:%.*]] = alloca i8, align 1 5415 // CHECK5-NEXT: [[X8:%.*]] = alloca i32, align 4 5416 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5417 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5418 // CHECK5-NEXT: store i32* [[Y]], i32** [[Y_ADDR]], align 8 5419 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 5420 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 5421 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 5422 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 5423 // CHECK5-NEXT: [[TMP0:%.*]] = load i32*, i32** [[Y_ADDR]], align 8, !dbg [[DBG78:![0-9]+]] 5424 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG78]] 5425 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG78]] 5426 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG78]] 5427 // CHECK5-NEXT: [[TMP4:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG78]] 5428 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4, !dbg [[DBG79:![0-9]+]] 5429 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP5]] to i8, !dbg [[DBG79]] 5430 // CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]] 5431 // CHECK5-NEXT: [[TMP6:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]] 5432 // CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP6]] to i32, !dbg [[DBG79]] 5433 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]], !dbg [[DBG79]] 5434 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1, !dbg [[DBG79]] 5435 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1, !dbg [[DBG79]] 5436 // CHECK5-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64, !dbg [[DBG79]] 5437 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11, !dbg [[DBG80:![0-9]+]] 5438 // CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1, !dbg [[DBG80]] 5439 // CHECK5-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG79]] 5440 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]] 5441 // CHECK5-NEXT: store i8 [[TMP7]], i8* [[I]], align 1, !dbg [[DBG79]] 5442 // CHECK5-NEXT: store i32 11, i32* [[X]], align 4, !dbg [[DBG80]] 5443 // CHECK5-NEXT: [[TMP8:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]] 5444 // CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP8]] to i32, !dbg [[DBG79]] 5445 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57, !dbg [[DBG79]] 5446 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG78]] 5447 // CHECK5: omp.precond.then: 5448 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG79]] 5449 // CHECK5-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]] 5450 // CHECK5-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG79]] 5451 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG79]] 5452 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG79]] 5453 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]] 5454 // CHECK5-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG78]] 5455 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[TMP11]], align 4, !dbg [[DBG78]] 5456 // CHECK5-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB25]], i32 [[TMP12]], i32 1073741862, i64 0, i64 [[TMP10]], i64 1, i64 1), !dbg [[DBG78]] 5457 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG78]] 5458 // CHECK5: omp.dispatch.cond: 5459 // CHECK5-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG78]] 5460 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[TMP13]], align 4, !dbg [[DBG78]] 5461 // CHECK5-NEXT: [[TMP15:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB25]], i32 [[TMP14]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG78]] 5462 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP15]], 0, !dbg [[DBG78]] 5463 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG78]] 5464 // CHECK5: omp.dispatch.body: 5465 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG79]] 5466 // CHECK5-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG79]] 5467 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG78]] 5468 // CHECK5: omp.inner.for.cond: 5469 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81 5470 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG79]], !llvm.access.group !81 5471 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]], !dbg [[DBG79]] 5472 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG78]] 5473 // CHECK5: omp.inner.for.body: 5474 // CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG79]], !llvm.access.group !81 5475 // CHECK5-NEXT: [[CONV10:%.*]] = sext i8 [[TMP19]] to i64, !dbg [[DBG79]] 5476 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81 5477 // CHECK5-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP20]], 11, !dbg [[DBG79]] 5478 // CHECK5-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1, !dbg [[DBG79]] 5479 // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]], !dbg [[DBG79]] 5480 // CHECK5-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8, !dbg [[DBG79]] 5481 // CHECK5-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !dbg [[DBG79]], !llvm.access.group !81 5482 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81 5483 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81 5484 // CHECK5-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP22]], 11, !dbg [[DBG79]] 5485 // CHECK5-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11, !dbg [[DBG79]] 5486 // CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP21]], [[MUL16]], !dbg [[DBG79]] 5487 // CHECK5-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1, !dbg [[DBG80]] 5488 // CHECK5-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]], !dbg [[DBG80]] 5489 // CHECK5-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32, !dbg [[DBG80]] 5490 // CHECK5-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !dbg [[DBG80]], !llvm.access.group !81 5491 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG82:![0-9]+]], !llvm.access.group !81 5492 // CHECK5-NEXT: [[TMP24:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG82]], !llvm.access.group !81 5493 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP24]] to i64, !dbg [[DBG82]] 5494 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM]], !dbg [[DBG82]] 5495 // CHECK5-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG82]], !llvm.access.group !81 5496 // CHECK5-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG82]], !llvm.access.group !81 5497 // CHECK5-NEXT: [[TMP27:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG82]], !llvm.access.group !81 5498 // CHECK5-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP27]] to i64, !dbg [[DBG82]] 5499 // CHECK5-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM21]], !dbg [[DBG82]] 5500 // CHECK5-NEXT: [[TMP28:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !dbg [[DBG82]], !llvm.access.group !81 5501 // CHECK5-NEXT: [[MUL23:%.*]] = fmul float [[TMP25]], [[TMP28]], !dbg [[DBG82]] 5502 // CHECK5-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP4]], align 8, !dbg [[DBG82]], !llvm.access.group !81 5503 // CHECK5-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG82]], !llvm.access.group !81 5504 // CHECK5-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP30]] to i64, !dbg [[DBG82]] 5505 // CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM24]], !dbg [[DBG82]] 5506 // CHECK5-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !dbg [[DBG82]], !llvm.access.group !81 5507 // CHECK5-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP31]], !dbg [[DBG82]] 5508 // CHECK5-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG82]], !llvm.access.group !81 5509 // CHECK5-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG82]], !llvm.access.group !81 5510 // CHECK5-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP33]] to i64, !dbg [[DBG82]] 5511 // CHECK5-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM27]], !dbg [[DBG82]] 5512 // CHECK5-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !dbg [[DBG82]], !llvm.access.group !81 5513 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG83:![0-9]+]] 5514 // CHECK5: omp.body.continue: 5515 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG78]] 5516 // CHECK5: omp.inner.for.inc: 5517 // CHECK5-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81 5518 // CHECK5-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP34]], 1, !dbg [[DBG79]] 5519 // CHECK5-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG79]], !llvm.access.group !81 5520 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG78]], !llvm.loop [[LOOP84:![0-9]+]] 5521 // CHECK5: omp.inner.for.end: 5522 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG78]] 5523 // CHECK5: omp.dispatch.inc: 5524 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG78]], !llvm.loop [[LOOP86:![0-9]+]] 5525 // CHECK5: omp.dispatch.end: 5526 // CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG78]] 5527 // CHECK5: omp.precond.end: 5528 // CHECK5-NEXT: ret void, !dbg [[DBG83]] 5529 // 5530 // 5531 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 5532 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG87:![0-9]+]] { 5533 // CHECK5-NEXT: entry: 5534 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5535 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5536 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5537 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5538 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5539 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5540 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5541 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5542 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5543 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG88:![0-9]+]] 5544 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB27:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** [[A_ADDR]], float** [[B_ADDR]], float** [[C_ADDR]], float** [[D_ADDR]]), !dbg [[DBG89:![0-9]+]] 5545 // CHECK5-NEXT: ret void, !dbg [[DBG90:![0-9]+]] 5546 // 5547 // 5548 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 5549 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], float** nonnull align 8 dereferenceable(8) [[B:%.*]], float** nonnull align 8 dereferenceable(8) [[C:%.*]], float** nonnull align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR1]] !dbg [[DBG91:![0-9]+]] { 5550 // CHECK5-NEXT: entry: 5551 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5552 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5553 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 5554 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float**, align 8 5555 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float**, align 8 5556 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float**, align 8 5557 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5558 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 5559 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 5560 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5561 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5562 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5563 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5564 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 5565 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5566 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5567 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5568 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 5569 // CHECK5-NEXT: store float** [[B]], float*** [[B_ADDR]], align 8 5570 // CHECK5-NEXT: store float** [[C]], float*** [[C_ADDR]], align 8 5571 // CHECK5-NEXT: store float** [[D]], float*** [[D_ADDR]], align 8 5572 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG92:![0-9]+]] 5573 // CHECK5-NEXT: [[TMP1:%.*]] = load float**, float*** [[B_ADDR]], align 8, !dbg [[DBG92]] 5574 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[C_ADDR]], align 8, !dbg [[DBG92]] 5575 // CHECK5-NEXT: [[TMP3:%.*]] = load float**, float*** [[D_ADDR]], align 8, !dbg [[DBG92]] 5576 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG93:![0-9]+]] 5577 // CHECK5-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG93]] 5578 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG93]] 5579 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG93]] 5580 // CHECK5-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG92]] 5581 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4, !dbg [[DBG92]] 5582 // CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB27]], i32 [[TMP5]], i32 1073741861, i32 0, i32 199, i32 1, i32 1), !dbg [[DBG92]] 5583 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG92]] 5584 // CHECK5: omp.dispatch.cond: 5585 // CHECK5-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB27]], i32 [[TMP5]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]), !dbg [[DBG92]] 5586 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP6]], 0, !dbg [[DBG92]] 5587 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG92]] 5588 // CHECK5: omp.dispatch.body: 5589 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG93]] 5590 // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG93]] 5591 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG92]] 5592 // CHECK5: omp.inner.for.cond: 5593 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94 5594 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG93]], !llvm.access.group !94 5595 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP8]], [[TMP9]], !dbg [[DBG93]] 5596 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG92]] 5597 // CHECK5: omp.inner.for.body: 5598 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94 5599 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP10]], 20, !dbg [[DBG93]] 5600 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1, !dbg [[DBG93]] 5601 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]], !dbg [[DBG93]] 5602 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8, !dbg [[DBG93]] 5603 // CHECK5-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !dbg [[DBG93]], !llvm.access.group !94 5604 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94 5605 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94 5606 // CHECK5-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP12]], 20, !dbg [[DBG93]] 5607 // CHECK5-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20, !dbg [[DBG93]] 5608 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP11]], [[MUL3]], !dbg [[DBG93]] 5609 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1, !dbg [[DBG95:![0-9]+]] 5610 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]], !dbg [[DBG95]] 5611 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !dbg [[DBG95]], !llvm.access.group !94 5612 // CHECK5-NEXT: [[TMP13:%.*]] = load float*, float** [[TMP1]], align 8, !dbg [[DBG96:![0-9]+]], !llvm.access.group !94 5613 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG96]], !llvm.access.group !94 5614 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP14]] to i64, !dbg [[DBG96]] 5615 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]], !dbg [[DBG96]] 5616 // CHECK5-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG96]], !llvm.access.group !94 5617 // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG96]], !llvm.access.group !94 5618 // CHECK5-NEXT: [[TMP17:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG96]], !llvm.access.group !94 5619 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP17]] to i64, !dbg [[DBG96]] 5620 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM6]], !dbg [[DBG96]] 5621 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG96]], !llvm.access.group !94 5622 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP18]], !dbg [[DBG96]] 5623 // CHECK5-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP3]], align 8, !dbg [[DBG96]], !llvm.access.group !94 5624 // CHECK5-NEXT: [[TMP20:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG96]], !llvm.access.group !94 5625 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP20]] to i64, !dbg [[DBG96]] 5626 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM9]], !dbg [[DBG96]] 5627 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !dbg [[DBG96]], !llvm.access.group !94 5628 // CHECK5-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP21]], !dbg [[DBG96]] 5629 // CHECK5-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG96]], !llvm.access.group !94 5630 // CHECK5-NEXT: [[TMP23:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG96]], !llvm.access.group !94 5631 // CHECK5-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP23]] to i64, !dbg [[DBG96]] 5632 // CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM12]], !dbg [[DBG96]] 5633 // CHECK5-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !dbg [[DBG96]], !llvm.access.group !94 5634 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG97:![0-9]+]] 5635 // CHECK5: omp.body.continue: 5636 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG92]] 5637 // CHECK5: omp.inner.for.inc: 5638 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94 5639 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP24]], 1, !dbg [[DBG93]] 5640 // CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG93]], !llvm.access.group !94 5641 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP98:![0-9]+]] 5642 // CHECK5: omp.inner.for.end: 5643 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG92]] 5644 // CHECK5: omp.dispatch.inc: 5645 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP100:![0-9]+]] 5646 // CHECK5: omp.dispatch.end: 5647 // CHECK5-NEXT: ret void, !dbg [[DBG97]] 5648 // 5649 // 5650 // CHECK5-LABEL: define {{[^@]+}}@_Z3foov 5651 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] !dbg [[DBG101:![0-9]+]] { 5652 // CHECK5-NEXT: entry: 5653 // CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG102:![0-9]+]] 5654 // CHECK5-NEXT: ret i32 0, !dbg [[DBG102]] 5655 // 5656 // 5657 // CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 5658 // CHECK5-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] !dbg [[DBG103:![0-9]+]] { 5659 // CHECK5-NEXT: entry: 5660 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5661 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5662 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 5663 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 5664 // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 5665 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5666 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5667 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG104:![0-9]+]] 5668 // CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG104]] 5669 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG104]] 5670 // CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG104]] 5671 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG104]] 5672 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG104]] 5673 // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]] 5674 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32*, !dbg [[DBG105]] 5675 // CHECK5-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4, !dbg [[DBG105]] 5676 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8, !dbg [[DBG105]] 5677 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB32:[0-9]+]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** [[A_ADDR]], i64 [[TMP1]], i64 [[TMP4]]), !dbg [[DBG105]] 5678 // CHECK5-NEXT: [[TMP5:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG106:![0-9]+]] 5679 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP5]]), !dbg [[DBG106]] 5680 // CHECK5-NEXT: ret void, !dbg [[DBG106]] 5681 // 5682 // 5683 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 5684 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], float** nonnull align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG107:![0-9]+]] { 5685 // CHECK5-NEXT: entry: 5686 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5687 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5688 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float**, align 8 5689 // CHECK5-NEXT: [[VLA_ADDR:%.*]] = alloca i64, align 8 5690 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 5691 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5692 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5693 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5694 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5695 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5696 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5697 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 5698 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 5699 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5700 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5701 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5702 // CHECK5-NEXT: store float** [[A]], float*** [[A_ADDR]], align 8 5703 // CHECK5-NEXT: store i64 [[VLA]], i64* [[VLA_ADDR]], align 8 5704 // CHECK5-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 5705 // CHECK5-NEXT: [[TMP0:%.*]] = load float**, float*** [[A_ADDR]], align 8, !dbg [[DBG108:![0-9]+]] 5706 // CHECK5-NEXT: [[TMP1:%.*]] = load i64, i64* [[VLA_ADDR]], align 8, !dbg [[DBG108]] 5707 // CHECK5-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32*, !dbg [[DBG108]] 5708 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG109:![0-9]+]] 5709 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]] 5710 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG109]] 5711 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG109]] 5712 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG108]] 5713 // CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG108]] 5714 // CHECK5-NEXT: [[VLA1:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG108]] 5715 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG108]] 5716 // CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG108]] 5717 // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[TMP3]], align 4, !dbg [[DBG108]] 5718 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB29:[0-9]+]], i32 [[TMP4]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG108]] 5719 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG108]] 5720 // CHECK5: omp.dispatch.cond: 5721 // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]] 5722 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP5]], 16908288, !dbg [[DBG109]] 5723 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG109]] 5724 // CHECK5: cond.true: 5725 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG109]] 5726 // CHECK5: cond.false: 5727 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]] 5728 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG109]] 5729 // CHECK5: cond.end: 5730 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP6]], [[COND_FALSE]] ], !dbg [[DBG109]] 5731 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]] 5732 // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG109]] 5733 // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG109]] 5734 // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG109]] 5735 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]] 5736 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP8]], [[TMP9]], !dbg [[DBG109]] 5737 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]], !dbg [[DBG108]] 5738 // CHECK5: omp.dispatch.cleanup: 5739 // CHECK5-NEXT: br label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG108]] 5740 // CHECK5: omp.dispatch.body: 5741 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG108]] 5742 // CHECK5: omp.inner.for.cond: 5743 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG109]] 5744 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]] 5745 // CHECK5-NEXT: [[CMP3:%.*]] = icmp ule i32 [[TMP10]], [[TMP11]], !dbg [[DBG109]] 5746 // CHECK5-NEXT: br i1 [[CMP3]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]], !dbg [[DBG108]] 5747 // CHECK5: omp.inner.for.cond.cleanup: 5748 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG108]] 5749 // CHECK5: omp.inner.for.body: 5750 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG109]] 5751 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP12]], 127, !dbg [[DBG109]] 5752 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG109]] 5753 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG109]] 5754 // CHECK5-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 5755 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG110:![0-9]+]] 5756 // CHECK5: invoke.cont: 5757 // CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG110]] 5758 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG110]] 5759 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP13]] to i64, !dbg [[DBG110]] 5760 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]], !dbg [[DBG110]] 5761 // CHECK5-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG110]] 5762 // CHECK5-NEXT: [[ADD5:%.*]] = fadd float [[CONV4]], [[TMP14]], !dbg [[DBG110]] 5763 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[CONV]], align 8, !dbg [[DBG110]] 5764 // CHECK5-NEXT: [[CONV6:%.*]] = sitofp i32 [[TMP15]] to float, !dbg [[DBG110]] 5765 // CHECK5-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]], !dbg [[DBG110]] 5766 // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP0]], align 8, !dbg [[DBG110]] 5767 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG110]] 5768 // CHECK5-NEXT: [[IDXPROM8:%.*]] = zext i32 [[TMP17]] to i64, !dbg [[DBG110]] 5769 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[IDXPROM8]], !dbg [[DBG110]] 5770 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !dbg [[DBG110]] 5771 // CHECK5-NEXT: [[ADD10:%.*]] = fadd float [[TMP18]], [[ADD7]], !dbg [[DBG110]] 5772 // CHECK5-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG110]] 5773 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG110]] 5774 // CHECK5: omp.body.continue: 5775 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG108]] 5776 // CHECK5: omp.inner.for.inc: 5777 // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG109]] 5778 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP19]], 1, !dbg [[DBG109]] 5779 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG109]] 5780 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG108]], !llvm.loop [[LOOP111:![0-9]+]] 5781 // CHECK5: omp.inner.for.end: 5782 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG108]] 5783 // CHECK5: omp.dispatch.inc: 5784 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG109]] 5785 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG109]] 5786 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP20]], [[TMP21]], !dbg [[DBG109]] 5787 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG109]] 5788 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]] 5789 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG109]] 5790 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP22]], [[TMP23]], !dbg [[DBG109]] 5791 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG109]] 5792 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG108]], !llvm.loop [[LOOP112:![0-9]+]] 5793 // CHECK5: omp.dispatch.end: 5794 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB31:[0-9]+]], i32 [[TMP4]]), !dbg [[DBG108]] 5795 // CHECK5-NEXT: [[TMP24:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG108]] 5796 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP24]]), !dbg [[DBG108]] 5797 // CHECK5-NEXT: ret void, !dbg [[DBG110]] 5798 // CHECK5: terminate.lpad: 5799 // CHECK5-NEXT: [[TMP25:%.*]] = landingpad { i8*, i32 } 5800 // CHECK5-NEXT: catch i8* null, !dbg [[DBG110]] 5801 // CHECK5-NEXT: [[TMP26:%.*]] = extractvalue { i8*, i32 } [[TMP25]], 0, !dbg [[DBG110]] 5802 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP26]]) #[[ATTR7:[0-9]+]], !dbg [[DBG110]] 5803 // CHECK5-NEXT: unreachable, !dbg [[DBG110]] 5804 // 5805 // 5806 // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate 5807 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] { 5808 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 5809 // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 5810 // CHECK5-NEXT: unreachable 5811 // 5812 // 5813 // CHECK6-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 5814 // CHECK6-SAME: () local_unnamed_addr #[[ATTR0:[0-9]+]] { 5815 // CHECK6-NEXT: entry: 5816 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 5) 5817 // CHECK6-NEXT: ret void 5818 // 5819 // 5820 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. 5821 // CHECK6-SAME: (i32* noalias nocapture [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture [[DOTBOUND_TID_:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]]) #[[ATTR2:[0-9]+]] { 5822 // CHECK6-NEXT: entry: 5823 // CHECK6-NEXT: ret void 5824 // 5825 // 5826 // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 5827 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) local_unnamed_addr #[[ATTR0]] { 5828 // CHECK6-NEXT: entry: 5829 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5830 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5831 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5832 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5833 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8, !tbaa [[TBAA4:![0-9]+]] 5834 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8, !tbaa [[TBAA4]] 5835 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8, !tbaa [[TBAA4]] 5836 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8, !tbaa [[TBAA4]] 5837 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..1 to void (i32*, i32*, ...)*), float** nonnull [[A_ADDR]], float** nonnull [[B_ADDR]], float** nonnull [[C_ADDR]], float** nonnull [[D_ADDR]]) 5838 // CHECK6-NEXT: ret void 5839 // 5840 // 5841 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 5842 // CHECK6-SAME: (i32* noalias nocapture readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture readnone [[DOTBOUND_TID_:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[A:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[B:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[C:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR4:[0-9]+]] { 5843 // CHECK6-NEXT: entry: 5844 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5845 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5846 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5847 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5848 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast i32* [[DOTOMP_LB]] to i8* 5849 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3:[0-9]+]] 5850 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8:![0-9]+]] 5851 // CHECK6-NEXT: [[TMP1:%.*]] = bitcast i32* [[DOTOMP_UB]] to i8* 5852 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 5853 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 5854 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast i32* [[DOTOMP_STRIDE]] to i8* 5855 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 5856 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]] 5857 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTOMP_IS_LAST]] to i8* 5858 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 5859 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]] 5860 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTGLOBAL_TID_]], align 4, !tbaa [[TBAA8]] 5861 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* nonnull @[[GLOB1:[0-9]+]], i32 [[TMP4]], i32 34, i32* nonnull [[DOTOMP_IS_LAST]], i32* nonnull [[DOTOMP_LB]], i32* nonnull [[DOTOMP_UB]], i32* nonnull [[DOTOMP_STRIDE]], i32 1, i32 1) #[[ATTR3]] 5862 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 5863 // CHECK6-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 4571423 5864 // CHECK6-NEXT: [[COND:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 4571423 5865 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 5866 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 5867 // CHECK6-NEXT: [[TMP8:%.*]] = load float*, float** [[B]], align 8 5868 // CHECK6-NEXT: [[TMP9:%.*]] = load float*, float** [[C]], align 8 5869 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[D]], align 8 5870 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[A]], align 8 5871 // CHECK6-NEXT: [[CMP1_NOT18:%.*]] = icmp sgt i32 [[TMP7]], [[COND]] 5872 // CHECK6-NEXT: br i1 [[CMP1_NOT18]], label [[OMP_LOOP_EXIT:%.*]], label [[OMP_INNER_FOR_BODY_PREHEADER:%.*]] 5873 // CHECK6: omp.inner.for.body.preheader: 5874 // CHECK6-NEXT: [[TMP12:%.*]] = sext i32 [[TMP7]] to i64 5875 // CHECK6-NEXT: [[TMP13:%.*]] = add nsw i32 [[COND]], 1 5876 // CHECK6-NEXT: br label [[OMP_INNER_FOR_BODY:%.*]] 5877 // CHECK6: omp.inner.for.body: 5878 // CHECK6-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP12]], [[OMP_INNER_FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[OMP_INNER_FOR_BODY]] ] 5879 // CHECK6-NEXT: [[TMP14:%.*]] = mul nsw i64 [[INDVARS_IV]], 7 5880 // CHECK6-NEXT: [[TMP15:%.*]] = add nsw i64 [[TMP14]], 33 5881 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[TMP15]] 5882 // CHECK6-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA10:![0-9]+]] 5883 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[TMP15]] 5884 // CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !tbaa [[TBAA10]] 5885 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP16]], [[TMP17]] 5886 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP15]] 5887 // CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !tbaa [[TBAA10]] 5888 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP18]] 5889 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[TMP15]] 5890 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !tbaa [[TBAA10]] 5891 // CHECK6-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], 1 5892 // CHECK6-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 5893 // CHECK6-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[TMP13]], [[LFTR_WIDEIV]] 5894 // CHECK6-NEXT: br i1 [[EXITCOND_NOT]], label [[OMP_LOOP_EXIT]], label [[OMP_INNER_FOR_BODY]] 5895 // CHECK6: omp.loop.exit: 5896 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* nonnull @[[GLOB1]], i32 [[TMP4]]) 5897 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 5898 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 5899 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 5900 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 5901 // CHECK6-NEXT: ret void 5902 // 5903 // 5904 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 5905 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) local_unnamed_addr #[[ATTR0]] { 5906 // CHECK6-NEXT: entry: 5907 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5908 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5909 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5910 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5911 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8, !tbaa [[TBAA4]] 5912 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8, !tbaa [[TBAA4]] 5913 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8, !tbaa [[TBAA4]] 5914 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8, !tbaa [[TBAA4]] 5915 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..2 to void (i32*, i32*, ...)*), float** nonnull [[A_ADDR]], float** nonnull [[B_ADDR]], float** nonnull [[C_ADDR]], float** nonnull [[D_ADDR]]) 5916 // CHECK6-NEXT: ret void 5917 // 5918 // 5919 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 5920 // CHECK6-SAME: (i32* noalias nocapture readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture readnone [[DOTBOUND_TID_:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[A:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[B:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[C:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR4]] { 5921 // CHECK6-NEXT: entry: 5922 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5923 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5924 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5925 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5926 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast i32* [[DOTOMP_LB]] to i8* 5927 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 5928 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 5929 // CHECK6-NEXT: [[TMP1:%.*]] = bitcast i32* [[DOTOMP_UB]] to i8* 5930 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 5931 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 5932 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast i32* [[DOTOMP_STRIDE]] to i8* 5933 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 5934 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]] 5935 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTOMP_IS_LAST]] to i8* 5936 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 5937 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]] 5938 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTGLOBAL_TID_]], align 4, !tbaa [[TBAA8]] 5939 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* nonnull @[[GLOB1]], i32 [[TMP4]], i32 34, i32* nonnull [[DOTOMP_IS_LAST]], i32* nonnull [[DOTOMP_LB]], i32* nonnull [[DOTOMP_UB]], i32* nonnull [[DOTOMP_STRIDE]], i32 1, i32 1) #[[ATTR3]] 5940 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 5941 // CHECK6-NEXT: [[TMP6:%.*]] = icmp slt i32 [[TMP5]], 4571423 5942 // CHECK6-NEXT: [[COND:%.*]] = select i1 [[TMP6]], i32 [[TMP5]], i32 4571423 5943 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 5944 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 5945 // CHECK6-NEXT: [[TMP8:%.*]] = load float*, float** [[B]], align 8 5946 // CHECK6-NEXT: [[TMP9:%.*]] = load float*, float** [[C]], align 8 5947 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[D]], align 8 5948 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[A]], align 8 5949 // CHECK6-NEXT: [[CMP1_NOT17:%.*]] = icmp sgt i32 [[TMP7]], [[COND]] 5950 // CHECK6-NEXT: br i1 [[CMP1_NOT17]], label [[OMP_LOOP_EXIT:%.*]], label [[OMP_INNER_FOR_BODY_PREHEADER:%.*]] 5951 // CHECK6: omp.inner.for.body.preheader: 5952 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[TMP7]] to i64 5953 // CHECK6-NEXT: [[TMP13:%.*]] = add nsw i32 [[COND]], 1 5954 // CHECK6-NEXT: br label [[OMP_INNER_FOR_BODY:%.*]] 5955 // CHECK6: omp.inner.for.body: 5956 // CHECK6-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[TMP12]], [[OMP_INNER_FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT:%.*]], [[OMP_INNER_FOR_BODY]] ] 5957 // CHECK6-NEXT: [[SUB:%.*]] = mul i64 [[INDVARS_IV]], -30064771072 5958 // CHECK6-NEXT: [[SEXT:%.*]] = add i64 [[SUB]], 137438953472000000 5959 // CHECK6-NEXT: [[IDXPROM:%.*]] = ashr exact i64 [[SEXT]], 32 5960 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 5961 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA10]] 5962 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM]] 5963 // CHECK6-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !tbaa [[TBAA10]] 5964 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP14]], [[TMP15]] 5965 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM]] 5966 // CHECK6-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !tbaa [[TBAA10]] 5967 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP16]] 5968 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM]] 5969 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !tbaa [[TBAA10]] 5970 // CHECK6-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 5971 // CHECK6-NEXT: [[LFTR_WIDEIV:%.*]] = trunc i64 [[INDVARS_IV_NEXT]] to i32 5972 // CHECK6-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[TMP13]], [[LFTR_WIDEIV]] 5973 // CHECK6-NEXT: br i1 [[EXITCOND_NOT]], label [[OMP_LOOP_EXIT]], label [[OMP_INNER_FOR_BODY]] 5974 // CHECK6: omp.loop.exit: 5975 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* nonnull @[[GLOB1]], i32 [[TMP4]]) 5976 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 5977 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 5978 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 5979 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 5980 // CHECK6-NEXT: ret void 5981 // 5982 // 5983 // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 5984 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) local_unnamed_addr #[[ATTR0]] { 5985 // CHECK6-NEXT: entry: 5986 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5987 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5988 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5989 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5990 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8, !tbaa [[TBAA4]] 5991 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8, !tbaa [[TBAA4]] 5992 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8, !tbaa [[TBAA4]] 5993 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8, !tbaa [[TBAA4]] 5994 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..3 to void (i32*, i32*, ...)*), float** nonnull [[A_ADDR]], float** nonnull [[B_ADDR]], float** nonnull [[C_ADDR]], float** nonnull [[D_ADDR]]) 5995 // CHECK6-NEXT: ret void 5996 // 5997 // 5998 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 5999 // CHECK6-SAME: (i32* noalias nocapture readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture readnone [[DOTBOUND_TID_:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[A:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[B:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[C:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR4]] { 6000 // CHECK6-NEXT: entry: 6001 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6002 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6003 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6004 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6005 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast i32* [[DOTOMP_LB]] to i8* 6006 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 6007 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 6008 // CHECK6-NEXT: [[TMP1:%.*]] = bitcast i32* [[DOTOMP_UB]] to i8* 6009 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 6010 // CHECK6-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6011 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast i32* [[DOTOMP_STRIDE]] to i8* 6012 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 6013 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]] 6014 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTOMP_IS_LAST]] to i8* 6015 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6016 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]] 6017 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTGLOBAL_TID_]], align 4, !tbaa [[TBAA8]] 6018 // CHECK6-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* nonnull @[[GLOB1]], i32 [[TMP4]], i32 33, i32* nonnull [[DOTOMP_IS_LAST]], i32* nonnull [[DOTOMP_LB]], i32* nonnull [[DOTOMP_UB]], i32* nonnull [[DOTOMP_STRIDE]], i32 1, i32 5) #[[ATTR3]] 6019 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6020 // CHECK6-NEXT: [[DOTOMP_UB_PROMOTED:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6021 // CHECK6-NEXT: [[TMP6:%.*]] = icmp ult i32 [[DOTOMP_UB_PROMOTED]], 16908288 6022 // CHECK6-NEXT: [[COND25:%.*]] = select i1 [[TMP6]], i32 [[DOTOMP_UB_PROMOTED]], i32 16908288 6023 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 6024 // CHECK6-NEXT: [[CMP1_NOT26:%.*]] = icmp ugt i32 [[TMP7]], [[COND25]] 6025 // CHECK6-NEXT: br i1 [[CMP1_NOT26]], label [[OMP_DISPATCH_END:%.*]], label [[OMP_INNER_FOR_COND_PREHEADER:%.*]] 6026 // CHECK6: omp.inner.for.cond.preheader: 6027 // CHECK6-NEXT: [[INDVARS_IV:%.*]] = phi i32 [ [[INDVARS_IV_NEXT:%.*]], [[OMP_DISPATCH_INC:%.*]] ], [ [[TMP7]], [[ENTRY:%.*]] ] 6028 // CHECK6-NEXT: [[COND27:%.*]] = phi i32 [ [[COND:%.*]], [[OMP_DISPATCH_INC]] ], [ [[COND25]], [[ENTRY]] ] 6029 // CHECK6-NEXT: [[TMP8:%.*]] = load float*, float** [[B]], align 8 6030 // CHECK6-NEXT: [[TMP9:%.*]] = load float*, float** [[C]], align 8 6031 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[D]], align 8 6032 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[A]], align 8 6033 // CHECK6-NEXT: [[CMP2_NOT22:%.*]] = icmp ugt i32 [[INDVARS_IV]], [[COND27]] 6034 // CHECK6-NEXT: br i1 [[CMP2_NOT22]], label [[OMP_DISPATCH_INC]], label [[OMP_INNER_FOR_BODY_PREHEADER:%.*]] 6035 // CHECK6: omp.inner.for.body.preheader: 6036 // CHECK6-NEXT: [[TMP12:%.*]] = zext i32 [[INDVARS_IV]] to i64 6037 // CHECK6-NEXT: br label [[OMP_INNER_FOR_BODY:%.*]] 6038 // CHECK6: omp.inner.for.body: 6039 // CHECK6-NEXT: [[INDVARS_IV29:%.*]] = phi i64 [ [[TMP12]], [[OMP_INNER_FOR_BODY_PREHEADER]] ], [ [[INDVARS_IV_NEXT30:%.*]], [[OMP_INNER_FOR_BODY]] ] 6040 // CHECK6-NEXT: [[DOTOMP_IV_023:%.*]] = phi i32 [ [[INDVARS_IV]], [[OMP_INNER_FOR_BODY_PREHEADER]] ], [ [[ADD11:%.*]], [[OMP_INNER_FOR_BODY]] ] 6041 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[INDVARS_IV29]], 127 6042 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[MUL]], 131071 6043 // CHECK6-NEXT: [[IDXPROM:%.*]] = and i64 [[ADD]], 4294967295 6044 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM]] 6045 // CHECK6-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA10]] 6046 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM]] 6047 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA10]] 6048 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP13]], [[TMP14]] 6049 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM]] 6050 // CHECK6-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !tbaa [[TBAA10]] 6051 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP15]] 6052 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM]] 6053 // CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !tbaa [[TBAA10]] 6054 // CHECK6-NEXT: [[ADD11]] = add i32 [[DOTOMP_IV_023]], 1 6055 // CHECK6-NEXT: [[CMP2_NOT:%.*]] = icmp ugt i32 [[ADD11]], [[COND27]] 6056 // CHECK6-NEXT: [[INDVARS_IV_NEXT30]] = add nuw nsw i64 [[INDVARS_IV29]], 1 6057 // CHECK6-NEXT: br i1 [[CMP2_NOT]], label [[OMP_DISPATCH_INC]], label [[OMP_INNER_FOR_BODY]] 6058 // CHECK6: omp.dispatch.inc: 6059 // CHECK6-NEXT: [[INDVARS_IV_NEXT]] = add i32 [[INDVARS_IV]], [[TMP5]] 6060 // CHECK6-NEXT: [[ADD13:%.*]] = add i32 [[TMP5]], [[COND27]] 6061 // CHECK6-NEXT: [[TMP16:%.*]] = icmp ult i32 [[ADD13]], 16908288 6062 // CHECK6-NEXT: [[COND]] = select i1 [[TMP16]], i32 [[ADD13]], i32 16908288 6063 // CHECK6-NEXT: [[CMP1_NOT:%.*]] = icmp ugt i32 [[INDVARS_IV_NEXT]], [[COND]] 6064 // CHECK6-NEXT: br i1 [[CMP1_NOT]], label [[OMP_DISPATCH_COND_OMP_DISPATCH_END_CRIT_EDGE:%.*]], label [[OMP_INNER_FOR_COND_PREHEADER]] 6065 // CHECK6: omp.dispatch.cond.omp.dispatch.end_crit_edge: 6066 // CHECK6-NEXT: store i32 [[INDVARS_IV_NEXT]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 6067 // CHECK6-NEXT: br label [[OMP_DISPATCH_END]] 6068 // CHECK6: omp.dispatch.end: 6069 // CHECK6-NEXT: [[COND_LCSSA:%.*]] = phi i32 [ [[COND]], [[OMP_DISPATCH_COND_OMP_DISPATCH_END_CRIT_EDGE]] ], [ [[COND25]], [[ENTRY]] ] 6070 // CHECK6-NEXT: store i32 [[COND_LCSSA]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6071 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* nonnull @[[GLOB1]], i32 [[TMP4]]) 6072 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6073 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 6074 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 6075 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 6076 // CHECK6-NEXT: ret void 6077 // 6078 // 6079 // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 6080 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) local_unnamed_addr #[[ATTR0]] { 6081 // CHECK6-NEXT: entry: 6082 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6083 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6084 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6085 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6086 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8, !tbaa [[TBAA4]] 6087 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8, !tbaa [[TBAA4]] 6088 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8, !tbaa [[TBAA4]] 6089 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8, !tbaa [[TBAA4]] 6090 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..4 to void (i32*, i32*, ...)*), float** nonnull [[A_ADDR]], float** nonnull [[B_ADDR]], float** nonnull [[C_ADDR]], float** nonnull [[D_ADDR]]) 6091 // CHECK6-NEXT: ret void 6092 // 6093 // 6094 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 6095 // CHECK6-SAME: (i32* noalias nocapture readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture readnone [[DOTBOUND_TID_:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[A:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[B:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[C:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR4]] { 6096 // CHECK6-NEXT: entry: 6097 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6098 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6099 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6100 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6101 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast i64* [[DOTOMP_LB]] to i8* 6102 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull [[TMP0]]) #[[ATTR3]] 6103 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !tbaa [[TBAA12:![0-9]+]] 6104 // CHECK6-NEXT: [[TMP1:%.*]] = bitcast i64* [[DOTOMP_UB]] to i8* 6105 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull [[TMP1]]) #[[ATTR3]] 6106 // CHECK6-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !tbaa [[TBAA12]] 6107 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast i64* [[DOTOMP_STRIDE]] to i8* 6108 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull [[TMP2]]) #[[ATTR3]] 6109 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !tbaa [[TBAA12]] 6110 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTOMP_IS_LAST]] to i8* 6111 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6112 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]] 6113 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTGLOBAL_TID_]], align 4, !tbaa [[TBAA8]] 6114 // CHECK6-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP4]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1) #[[ATTR3]] 6115 // CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP4]], i32* nonnull [[DOTOMP_IS_LAST]], i64* nonnull [[DOTOMP_LB]], i64* nonnull [[DOTOMP_UB]], i64* nonnull [[DOTOMP_STRIDE]]) #[[ATTR3]] 6116 // CHECK6-NEXT: [[TOBOOL_NOT17:%.*]] = icmp eq i32 [[TMP5]], 0 6117 // CHECK6-NEXT: br i1 [[TOBOOL_NOT17]], label [[OMP_DISPATCH_END:%.*]], label [[OMP_DISPATCH_BODY:%.*]] 6118 // CHECK6: omp.dispatch.cond.loopexit: 6119 // CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP4]], i32* nonnull [[DOTOMP_IS_LAST]], i64* nonnull [[DOTOMP_LB]], i64* nonnull [[DOTOMP_UB]], i64* nonnull [[DOTOMP_STRIDE]]) #[[ATTR3]] 6120 // CHECK6-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP6]], 0 6121 // CHECK6-NEXT: br i1 [[TOBOOL_NOT]], label [[OMP_DISPATCH_END]], label [[OMP_DISPATCH_BODY]] 6122 // CHECK6: omp.dispatch.body: 6123 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !tbaa [[TBAA12]] 6124 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !tbaa [[TBAA12]], !llvm.access.group !14 6125 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP8]], 1 6126 // CHECK6-NEXT: [[TMP9:%.*]] = load float*, float** [[B]], align 8 6127 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[C]], align 8 6128 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[D]], align 8 6129 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[A]], align 8 6130 // CHECK6-NEXT: [[CMP15:%.*]] = icmp ult i64 [[TMP7]], [[ADD]] 6131 // CHECK6-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_DISPATCH_COND_LOOPEXIT:%.*]] 6132 // CHECK6: omp.inner.for.body: 6133 // CHECK6-NEXT: [[DOTOMP_IV_016:%.*]] = phi i64 [ [[ADD7:%.*]], [[OMP_INNER_FOR_BODY]] ], [ [[TMP7]], [[OMP_DISPATCH_BODY]] ] 6134 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[DOTOMP_IV_016]], 127 6135 // CHECK6-NEXT: [[ADD1:%.*]] = add i64 [[MUL]], 131071 6136 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[ADD1]] 6137 // CHECK6-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA10]], !llvm.access.group !14 6138 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[ADD1]] 6139 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA10]], !llvm.access.group !14 6140 // CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP14]] 6141 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[ADD1]] 6142 // CHECK6-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA10]], !llvm.access.group !14 6143 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP15]] 6144 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[ADD1]] 6145 // CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !tbaa [[TBAA10]], !llvm.access.group !14 6146 // CHECK6-NEXT: [[ADD7]] = add nuw i64 [[DOTOMP_IV_016]], 1 6147 // CHECK6-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[DOTOMP_IV_016]], [[TMP8]] 6148 // CHECK6-NEXT: br i1 [[EXITCOND_NOT]], label [[OMP_DISPATCH_COND_LOOPEXIT]], label [[OMP_INNER_FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] 6149 // CHECK6: omp.dispatch.end: 6150 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6151 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull [[TMP2]]) #[[ATTR3]] 6152 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull [[TMP1]]) #[[ATTR3]] 6153 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull [[TMP0]]) #[[ATTR3]] 6154 // CHECK6-NEXT: ret void 6155 // 6156 // 6157 // CHECK6-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 6158 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) local_unnamed_addr #[[ATTR0]] { 6159 // CHECK6-NEXT: entry: 6160 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6161 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6162 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6163 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6164 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8, !tbaa [[TBAA4]] 6165 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8, !tbaa [[TBAA4]] 6166 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8, !tbaa [[TBAA4]] 6167 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8, !tbaa [[TBAA4]] 6168 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..5 to void (i32*, i32*, ...)*), float** nonnull [[A_ADDR]], float** nonnull [[B_ADDR]], float** nonnull [[C_ADDR]], float** nonnull [[D_ADDR]]) 6169 // CHECK6-NEXT: ret void 6170 // 6171 // 6172 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 6173 // CHECK6-SAME: (i32* noalias nocapture readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture readnone [[DOTBOUND_TID_:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[A:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[B:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[C:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR4]] { 6174 // CHECK6-NEXT: entry: 6175 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6176 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6177 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6178 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6179 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast i64* [[DOTOMP_LB]] to i8* 6180 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull [[TMP0]]) #[[ATTR3]] 6181 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !tbaa [[TBAA12]] 6182 // CHECK6-NEXT: [[TMP1:%.*]] = bitcast i64* [[DOTOMP_UB]] to i8* 6183 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull [[TMP1]]) #[[ATTR3]] 6184 // CHECK6-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !tbaa [[TBAA12]] 6185 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast i64* [[DOTOMP_STRIDE]] to i8* 6186 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull [[TMP2]]) #[[ATTR3]] 6187 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !tbaa [[TBAA12]] 6188 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTOMP_IS_LAST]] to i8* 6189 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6190 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]] 6191 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTGLOBAL_TID_]], align 4, !tbaa [[TBAA8]] 6192 // CHECK6-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP4]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7) #[[ATTR3]] 6193 // CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP4]], i32* nonnull [[DOTOMP_IS_LAST]], i64* nonnull [[DOTOMP_LB]], i64* nonnull [[DOTOMP_UB]], i64* nonnull [[DOTOMP_STRIDE]]) #[[ATTR3]] 6194 // CHECK6-NEXT: [[TOBOOL_NOT17:%.*]] = icmp eq i32 [[TMP5]], 0 6195 // CHECK6-NEXT: br i1 [[TOBOOL_NOT17]], label [[OMP_DISPATCH_END:%.*]], label [[OMP_DISPATCH_BODY:%.*]] 6196 // CHECK6: omp.dispatch.cond.loopexit: 6197 // CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP4]], i32* nonnull [[DOTOMP_IS_LAST]], i64* nonnull [[DOTOMP_LB]], i64* nonnull [[DOTOMP_UB]], i64* nonnull [[DOTOMP_STRIDE]]) #[[ATTR3]] 6198 // CHECK6-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP6]], 0 6199 // CHECK6-NEXT: br i1 [[TOBOOL_NOT]], label [[OMP_DISPATCH_END]], label [[OMP_DISPATCH_BODY]] 6200 // CHECK6: omp.dispatch.body: 6201 // CHECK6-NEXT: [[TMP7:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !tbaa [[TBAA12]] 6202 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !tbaa [[TBAA12]], !llvm.access.group !17 6203 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP8]], 1 6204 // CHECK6-NEXT: [[TMP9:%.*]] = load float*, float** [[B]], align 8 6205 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[C]], align 8 6206 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[D]], align 8 6207 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[A]], align 8 6208 // CHECK6-NEXT: [[CMP15:%.*]] = icmp ult i64 [[TMP7]], [[ADD]] 6209 // CHECK6-NEXT: br i1 [[CMP15]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_DISPATCH_COND_LOOPEXIT:%.*]] 6210 // CHECK6: omp.inner.for.body: 6211 // CHECK6-NEXT: [[DOTOMP_IV_016:%.*]] = phi i64 [ [[ADD7:%.*]], [[OMP_INNER_FOR_BODY]] ], [ [[TMP7]], [[OMP_DISPATCH_BODY]] ] 6212 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[DOTOMP_IV_016]], 127 6213 // CHECK6-NEXT: [[ADD1:%.*]] = add i64 [[MUL]], 131071 6214 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[ADD1]] 6215 // CHECK6-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA10]], !llvm.access.group !17 6216 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[ADD1]] 6217 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA10]], !llvm.access.group !17 6218 // CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP13]], [[TMP14]] 6219 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[ADD1]] 6220 // CHECK6-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA10]], !llvm.access.group !17 6221 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP15]] 6222 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[ADD1]] 6223 // CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !tbaa [[TBAA10]], !llvm.access.group !17 6224 // CHECK6-NEXT: [[ADD7]] = add nuw i64 [[DOTOMP_IV_016]], 1 6225 // CHECK6-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[DOTOMP_IV_016]], [[TMP8]] 6226 // CHECK6-NEXT: br i1 [[EXITCOND_NOT]], label [[OMP_DISPATCH_COND_LOOPEXIT]], label [[OMP_INNER_FOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]] 6227 // CHECK6: omp.dispatch.end: 6228 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6229 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull [[TMP2]]) #[[ATTR3]] 6230 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull [[TMP1]]) #[[ATTR3]] 6231 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull [[TMP0]]) #[[ATTR3]] 6232 // CHECK6-NEXT: ret void 6233 // 6234 // 6235 // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 6236 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) local_unnamed_addr #[[ATTR0]] { 6237 // CHECK6-NEXT: entry: 6238 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6239 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6240 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6241 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6242 // CHECK6-NEXT: [[Y:%.*]] = alloca i32, align 4 6243 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8, !tbaa [[TBAA4]] 6244 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8, !tbaa [[TBAA4]] 6245 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8, !tbaa [[TBAA4]] 6246 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8, !tbaa [[TBAA4]] 6247 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast i32* [[Y]] to i8* 6248 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 6249 // CHECK6-NEXT: store i32 0, i32* [[Y]], align 4, !tbaa [[TBAA8]] 6250 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @[[GLOB2]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..6 to void (i32*, i32*, ...)*), i32* nonnull [[Y]], float** nonnull [[A_ADDR]], float** nonnull [[B_ADDR]], float** nonnull [[C_ADDR]], float** nonnull [[D_ADDR]]) 6251 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 6252 // CHECK6-NEXT: ret void 6253 // 6254 // 6255 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 6256 // CHECK6-SAME: (i32* noalias nocapture readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture readnone [[DOTBOUND_TID_:%.*]], i32* nocapture nonnull readonly align 4 dereferenceable(4) [[Y:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[A:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[B:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[C:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR4]] { 6257 // CHECK6-NEXT: entry: 6258 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6259 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6260 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6261 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6262 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4, !tbaa [[TBAA8]] 6263 // CHECK6-NEXT: [[SEXT:%.*]] = shl i32 [[TMP0]], 24 6264 // CHECK6-NEXT: [[CONV3:%.*]] = ashr exact i32 [[SEXT]], 24 6265 // CHECK6-NEXT: [[ADD:%.*]] = sub nsw i32 58, [[CONV3]] 6266 // CHECK6-NEXT: [[CONV4:%.*]] = zext i32 [[ADD]] to i64 6267 // CHECK6-NEXT: [[MUL:%.*]] = mul nuw nsw i64 [[CONV4]], 11 6268 // CHECK6-NEXT: [[SUB5:%.*]] = add nsw i64 [[MUL]], -1 6269 // CHECK6-NEXT: [[CMP:%.*]] = icmp slt i32 [[SEXT]], 973078528 6270 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 6271 // CHECK6: omp.precond.then: 6272 // CHECK6-NEXT: [[TMP1:%.*]] = bitcast i64* [[DOTOMP_LB]] to i8* 6273 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull [[TMP1]]) #[[ATTR3]] 6274 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !tbaa [[TBAA20:![0-9]+]] 6275 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast i64* [[DOTOMP_UB]] to i8* 6276 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull [[TMP2]]) #[[ATTR3]] 6277 // CHECK6-NEXT: store i64 [[SUB5]], i64* [[DOTOMP_UB]], align 8, !tbaa [[TBAA20]] 6278 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i64* [[DOTOMP_STRIDE]] to i8* 6279 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull [[TMP3]]) #[[ATTR3]] 6280 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !tbaa [[TBAA20]] 6281 // CHECK6-NEXT: [[TMP4:%.*]] = bitcast i32* [[DOTOMP_IS_LAST]] to i8* 6282 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP4]]) #[[ATTR3]] 6283 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]] 6284 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTGLOBAL_TID_]], align 4, !tbaa [[TBAA8]] 6285 // CHECK6-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP5]], i32 1073741862, i64 0, i64 [[SUB5]], i64 1, i64 1) #[[ATTR3]] 6286 // CHECK6-NEXT: [[SEXT46:%.*]] = zext i32 [[TMP0]] to i64 6287 // CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP5]], i32* nonnull [[DOTOMP_IS_LAST]], i64* nonnull [[DOTOMP_LB]], i64* nonnull [[DOTOMP_UB]], i64* nonnull [[DOTOMP_STRIDE]]) #[[ATTR3]] 6288 // CHECK6-NEXT: [[TOBOOL_NOT50:%.*]] = icmp eq i32 [[TMP6]], 0 6289 // CHECK6-NEXT: br i1 [[TOBOOL_NOT50]], label [[OMP_DISPATCH_END:%.*]], label [[OMP_DISPATCH_BODY:%.*]] 6290 // CHECK6: omp.dispatch.cond.loopexit: 6291 // CHECK6-NEXT: [[TMP7:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP5]], i32* nonnull [[DOTOMP_IS_LAST]], i64* nonnull [[DOTOMP_LB]], i64* nonnull [[DOTOMP_UB]], i64* nonnull [[DOTOMP_STRIDE]]) #[[ATTR3]] 6292 // CHECK6-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP7]], 0 6293 // CHECK6-NEXT: br i1 [[TOBOOL_NOT]], label [[OMP_DISPATCH_END]], label [[OMP_DISPATCH_BODY]] 6294 // CHECK6: omp.dispatch.body: 6295 // CHECK6-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !tbaa [[TBAA20]] 6296 // CHECK6-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !tbaa [[TBAA20]], !llvm.access.group !22 6297 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[B]], align 8 6298 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[C]], align 8 6299 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[D]], align 8 6300 // CHECK6-NEXT: [[TMP13:%.*]] = load float*, float** [[A]], align 8 6301 // CHECK6-NEXT: [[CMP9_NOT48:%.*]] = icmp sgt i64 [[TMP8]], [[TMP9]] 6302 // CHECK6-NEXT: br i1 [[CMP9_NOT48]], label [[OMP_DISPATCH_COND_LOOPEXIT:%.*]], label [[OMP_INNER_FOR_BODY:%.*]] 6303 // CHECK6: omp.inner.for.body: 6304 // CHECK6-NEXT: [[DOTOMP_IV_049:%.*]] = phi i64 [ [[ADD29:%.*]], [[OMP_INNER_FOR_BODY]] ], [ [[TMP8]], [[OMP_DISPATCH_BODY]] ] 6305 // CHECK6-NEXT: [[DIV11:%.*]] = sdiv i64 [[DOTOMP_IV_049]], 11 6306 // CHECK6-NEXT: [[ADD13:%.*]] = add nsw i64 [[DIV11]], [[SEXT46]] 6307 // CHECK6-NEXT: [[SEXT47:%.*]] = shl i64 [[ADD13]], 56 6308 // CHECK6-NEXT: [[IDXPROM:%.*]] = ashr exact i64 [[SEXT47]], 56 6309 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM]] 6310 // CHECK6-NEXT: [[TMP14:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA10]], !llvm.access.group !22 6311 // CHECK6-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM]] 6312 // CHECK6-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !tbaa [[TBAA10]], !llvm.access.group !22 6313 // CHECK6-NEXT: [[MUL23:%.*]] = fmul float [[TMP14]], [[TMP15]] 6314 // CHECK6-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 6315 // CHECK6-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !tbaa [[TBAA10]], !llvm.access.group !22 6316 // CHECK6-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP16]] 6317 // CHECK6-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP13]], i64 [[IDXPROM]] 6318 // CHECK6-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !tbaa [[TBAA10]], !llvm.access.group !22 6319 // CHECK6-NEXT: [[ADD29]] = add i64 [[DOTOMP_IV_049]], 1 6320 // CHECK6-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[DOTOMP_IV_049]], [[TMP9]] 6321 // CHECK6-NEXT: br i1 [[EXITCOND_NOT]], label [[OMP_DISPATCH_COND_LOOPEXIT]], label [[OMP_INNER_FOR_BODY]], !llvm.loop [[LOOP23:![0-9]+]] 6322 // CHECK6: omp.dispatch.end: 6323 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP4]]) #[[ATTR3]] 6324 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull [[TMP3]]) #[[ATTR3]] 6325 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull [[TMP2]]) #[[ATTR3]] 6326 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull [[TMP1]]) #[[ATTR3]] 6327 // CHECK6-NEXT: br label [[OMP_PRECOND_END]] 6328 // CHECK6: omp.precond.end: 6329 // CHECK6-NEXT: ret void 6330 // 6331 // 6332 // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 6333 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) local_unnamed_addr #[[ATTR0]] { 6334 // CHECK6-NEXT: entry: 6335 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6336 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6337 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6338 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6339 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8, !tbaa [[TBAA4]] 6340 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8, !tbaa [[TBAA4]] 6341 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8, !tbaa [[TBAA4]] 6342 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8, !tbaa [[TBAA4]] 6343 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* @.omp_outlined..7 to void (i32*, i32*, ...)*), float** nonnull [[A_ADDR]], float** nonnull [[B_ADDR]], float** nonnull [[C_ADDR]], float** nonnull [[D_ADDR]]) 6344 // CHECK6-NEXT: ret void 6345 // 6346 // 6347 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 6348 // CHECK6-SAME: (i32* noalias nocapture readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture readnone [[DOTBOUND_TID_:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[A:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[B:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[C:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[D:%.*]]) #[[ATTR4]] { 6349 // CHECK6-NEXT: entry: 6350 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6351 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6352 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6353 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6354 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast i32* [[DOTOMP_LB]] to i8* 6355 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 6356 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 6357 // CHECK6-NEXT: [[TMP1:%.*]] = bitcast i32* [[DOTOMP_UB]] to i8* 6358 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 6359 // CHECK6-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6360 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast i32* [[DOTOMP_STRIDE]] to i8* 6361 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 6362 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]] 6363 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTOMP_IS_LAST]] to i8* 6364 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6365 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]] 6366 // CHECK6-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTGLOBAL_TID_]], align 4, !tbaa [[TBAA8]] 6367 // CHECK6-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP4]], i32 1073741861, i32 0, i32 199, i32 1, i32 1) #[[ATTR3]] 6368 // CHECK6-NEXT: [[TMP5:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP4]], i32* nonnull [[DOTOMP_IS_LAST]], i32* nonnull [[DOTOMP_LB]], i32* nonnull [[DOTOMP_UB]], i32* nonnull [[DOTOMP_STRIDE]]) #[[ATTR3]] 6369 // CHECK6-NEXT: [[TOBOOL_NOT26:%.*]] = icmp eq i32 [[TMP5]], 0 6370 // CHECK6-NEXT: br i1 [[TOBOOL_NOT26]], label [[OMP_DISPATCH_END:%.*]], label [[OMP_DISPATCH_BODY:%.*]] 6371 // CHECK6: omp.dispatch.cond.loopexit: 6372 // CHECK6-NEXT: [[TMP6:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* nonnull @[[GLOB2]], i32 [[TMP4]], i32* nonnull [[DOTOMP_IS_LAST]], i32* nonnull [[DOTOMP_LB]], i32* nonnull [[DOTOMP_UB]], i32* nonnull [[DOTOMP_STRIDE]]) #[[ATTR3]] 6373 // CHECK6-NEXT: [[TOBOOL_NOT:%.*]] = icmp eq i32 [[TMP6]], 0 6374 // CHECK6-NEXT: br i1 [[TOBOOL_NOT]], label [[OMP_DISPATCH_END]], label [[OMP_DISPATCH_BODY]] 6375 // CHECK6: omp.dispatch.body: 6376 // CHECK6-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 6377 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]], !llvm.access.group !25 6378 // CHECK6-NEXT: [[TMP9:%.*]] = load float*, float** [[B]], align 8 6379 // CHECK6-NEXT: [[TMP10:%.*]] = load float*, float** [[C]], align 8 6380 // CHECK6-NEXT: [[TMP11:%.*]] = load float*, float** [[D]], align 8 6381 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[A]], align 8 6382 // CHECK6-NEXT: [[CMP_NOT24:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] 6383 // CHECK6-NEXT: br i1 [[CMP_NOT24]], label [[OMP_DISPATCH_COND_LOOPEXIT:%.*]], label [[OMP_INNER_FOR_BODY:%.*]] 6384 // CHECK6: omp.inner.for.body: 6385 // CHECK6-NEXT: [[DOTOMP_IV_025:%.*]] = phi i32 [ [[ADD14:%.*]], [[OMP_INNER_FOR_BODY]] ], [ [[TMP7]], [[OMP_DISPATCH_BODY]] ] 6386 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[DOTOMP_IV_025]], 20 6387 // CHECK6-NEXT: [[TMP13:%.*]] = add nsw i32 [[DIV]], 48 6388 // CHECK6-NEXT: [[TMP14:%.*]] = and i32 [[TMP13]], 255 6389 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP14]] to i64 6390 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM]] 6391 // CHECK6-NEXT: [[TMP15:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA10]], !llvm.access.group !25 6392 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM]] 6393 // CHECK6-NEXT: [[TMP16:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !tbaa [[TBAA10]], !llvm.access.group !25 6394 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[TMP15]], [[TMP16]] 6395 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM]] 6396 // CHECK6-NEXT: [[TMP17:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !tbaa [[TBAA10]], !llvm.access.group !25 6397 // CHECK6-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP17]] 6398 // CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 6399 // CHECK6-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !tbaa [[TBAA10]], !llvm.access.group !25 6400 // CHECK6-NEXT: [[ADD14]] = add i32 [[DOTOMP_IV_025]], 1 6401 // CHECK6-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[DOTOMP_IV_025]], [[TMP8]] 6402 // CHECK6-NEXT: br i1 [[EXITCOND_NOT]], label [[OMP_DISPATCH_COND_LOOPEXIT]], label [[OMP_INNER_FOR_BODY]], !llvm.loop [[LOOP26:![0-9]+]] 6403 // CHECK6: omp.dispatch.end: 6404 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6405 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 6406 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 6407 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 6408 // CHECK6-NEXT: ret void 6409 // 6410 // 6411 // CHECK6-LABEL: define {{[^@]+}}@_Z3foov 6412 // CHECK6-SAME: () local_unnamed_addr #[[ATTR0]] { 6413 // CHECK6-NEXT: entry: 6414 // CHECK6-NEXT: call void @_Z8mayThrowv() #[[ATTR3]] 6415 // CHECK6-NEXT: ret i32 0 6416 // 6417 // 6418 // CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 6419 // CHECK6-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) local_unnamed_addr #[[ATTR0]] { 6420 // CHECK6-NEXT: entry: 6421 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6422 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8, !tbaa [[TBAA4]] 6423 // CHECK6-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 6424 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* nonnull @[[GLOB2]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, i64, i64)* @.omp_outlined..8 to void (i32*, i32*, ...)*), float** nonnull [[A_ADDR]], i64 [[TMP0]], i64 [[TMP0]]) 6425 // CHECK6-NEXT: ret void 6426 // 6427 // 6428 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 6429 // CHECK6-SAME: (i32* noalias nocapture readonly [[DOTGLOBAL_TID_:%.*]], i32* noalias nocapture readnone [[DOTBOUND_TID_:%.*]], float** nocapture nonnull readonly align 8 dereferenceable(8) [[A:%.*]], i64 [[VLA:%.*]], i64 [[N:%.*]]) #[[ATTR4]] { 6430 // CHECK6-NEXT: entry: 6431 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6432 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6433 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6434 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6435 // CHECK6-NEXT: [[N_ADDR_SROA_0_0_EXTRACT_TRUNC:%.*]] = trunc i64 [[N]] to i32 6436 // CHECK6-NEXT: [[TMP0:%.*]] = bitcast i32* [[DOTOMP_LB]] to i8* 6437 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 6438 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 6439 // CHECK6-NEXT: [[TMP1:%.*]] = bitcast i32* [[DOTOMP_UB]] to i8* 6440 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 6441 // CHECK6-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6442 // CHECK6-NEXT: [[TMP2:%.*]] = bitcast i32* [[DOTOMP_STRIDE]] to i8* 6443 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 6444 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]] 6445 // CHECK6-NEXT: [[TMP3:%.*]] = bitcast i32* [[DOTOMP_IS_LAST]] to i8* 6446 // CHECK6-NEXT: call void @llvm.lifetime.start.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6447 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !tbaa [[TBAA8]] 6448 // CHECK6-NEXT: [[TMP4:%.*]] = call i8* @llvm.stacksave() 6449 // CHECK6-NEXT: [[VLA1:%.*]] = alloca float, i64 [[VLA]], align 16 6450 // CHECK6-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTGLOBAL_TID_]], align 4, !tbaa [[TBAA8]] 6451 // CHECK6-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* nonnull @[[GLOB1]], i32 [[TMP5]], i32 33, i32* nonnull [[DOTOMP_IS_LAST]], i32* nonnull [[DOTOMP_LB]], i32* nonnull [[DOTOMP_UB]], i32* nonnull [[DOTOMP_STRIDE]], i32 1, i32 5) #[[ATTR3]] 6452 // CHECK6-NEXT: [[CONV6:%.*]] = sitofp i32 [[N_ADDR_SROA_0_0_EXTRACT_TRUNC]] to float 6453 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6454 // CHECK6-NEXT: [[TMP7:%.*]] = icmp ult i32 [[TMP6]], 16908288 6455 // CHECK6-NEXT: [[COND22:%.*]] = select i1 [[TMP7]], i32 [[TMP6]], i32 16908288 6456 // CHECK6-NEXT: store i32 [[COND22]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6457 // CHECK6-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 6458 // CHECK6-NEXT: [[CMP2_NOT23:%.*]] = icmp ugt i32 [[TMP8]], [[COND22]] 6459 // CHECK6-NEXT: br i1 [[CMP2_NOT23]], label [[OMP_DISPATCH_END:%.*]], label [[OMP_INNER_FOR_COND_PREHEADER:%.*]] 6460 // CHECK6: omp.inner.for.cond.preheader: 6461 // CHECK6-NEXT: [[TMP9:%.*]] = phi i32 [ [[ADD12:%.*]], [[OMP_DISPATCH_INC:%.*]] ], [ [[TMP8]], [[ENTRY:%.*]] ] 6462 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6463 // CHECK6-NEXT: [[CMP3_NOT20:%.*]] = icmp ugt i32 [[TMP9]], [[TMP10]] 6464 // CHECK6-NEXT: br i1 [[CMP3_NOT20]], label [[OMP_DISPATCH_INC]], label [[OMP_INNER_FOR_BODY:%.*]] 6465 // CHECK6: omp.inner.for.body: 6466 // CHECK6-NEXT: [[DOTOMP_IV_021:%.*]] = phi i32 [ [[ADD11:%.*]], [[OMP_INNER_FOR_BODY]] ], [ [[TMP9]], [[OMP_INNER_FOR_COND_PREHEADER]] ] 6467 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[DOTOMP_IV_021]], 127 6468 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[MUL]], 131071 6469 // CHECK6-NEXT: call void @_Z8mayThrowv() #[[ATTR3]] 6470 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[ADD]] to i64 6471 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA1]], i64 [[IDXPROM]] 6472 // CHECK6-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA10]] 6473 // CHECK6-NEXT: [[ADD5:%.*]] = fadd float [[TMP11]], 0.000000e+00 6474 // CHECK6-NEXT: [[ADD7:%.*]] = fadd float [[ADD5]], [[CONV6]] 6475 // CHECK6-NEXT: [[TMP12:%.*]] = load float*, float** [[A]], align 8, !tbaa [[TBAA4]] 6476 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM]] 6477 // CHECK6-NEXT: [[TMP13:%.*]] = load float, float* [[ARRAYIDX9]], align 4, !tbaa [[TBAA10]] 6478 // CHECK6-NEXT: [[ADD10:%.*]] = fadd float [[TMP13]], [[ADD7]] 6479 // CHECK6-NEXT: store float [[ADD10]], float* [[ARRAYIDX9]], align 4, !tbaa [[TBAA10]] 6480 // CHECK6-NEXT: [[ADD11]] = add i32 [[DOTOMP_IV_021]], 1 6481 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6482 // CHECK6-NEXT: [[CMP3_NOT:%.*]] = icmp ugt i32 [[ADD11]], [[TMP14]] 6483 // CHECK6-NEXT: br i1 [[CMP3_NOT]], label [[OMP_DISPATCH_INC]], label [[OMP_INNER_FOR_BODY]] 6484 // CHECK6: omp.dispatch.inc: 6485 // CHECK6-NEXT: [[DOTLCSSA:%.*]] = phi i32 [ [[TMP10]], [[OMP_INNER_FOR_COND_PREHEADER]] ], [ [[TMP14]], [[OMP_INNER_FOR_BODY]] ] 6486 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 6487 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !tbaa [[TBAA8]] 6488 // CHECK6-NEXT: [[ADD12]] = add i32 [[TMP16]], [[TMP15]] 6489 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !tbaa [[TBAA8]] 6490 // CHECK6-NEXT: [[ADD13:%.*]] = add i32 [[TMP16]], [[DOTLCSSA]] 6491 // CHECK6-NEXT: [[TMP17:%.*]] = icmp ult i32 [[ADD13]], 16908288 6492 // CHECK6-NEXT: [[COND:%.*]] = select i1 [[TMP17]], i32 [[ADD13]], i32 16908288 6493 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !tbaa [[TBAA8]] 6494 // CHECK6-NEXT: [[CMP2_NOT:%.*]] = icmp ugt i32 [[ADD12]], [[COND]] 6495 // CHECK6-NEXT: br i1 [[CMP2_NOT]], label [[OMP_DISPATCH_END]], label [[OMP_INNER_FOR_COND_PREHEADER]] 6496 // CHECK6: omp.dispatch.end: 6497 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* nonnull @[[GLOB1]], i32 [[TMP5]]) 6498 // CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP4]]) 6499 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP3]]) #[[ATTR3]] 6500 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP2]]) #[[ATTR3]] 6501 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP1]]) #[[ATTR3]] 6502 // CHECK6-NEXT: call void @llvm.lifetime.end.p0i8(i64 4, i8* nonnull [[TMP0]]) #[[ATTR3]] 6503 // CHECK6-NEXT: ret void 6504 // 6505 // 6506 // CHECK7-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 6507 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] { 6508 // CHECK7-NEXT: entry: 6509 // CHECK7-NEXT: [[A:%.*]] = alloca double, align 8 6510 // CHECK7-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6511 // CHECK7-NEXT: [[A1:%.*]] = alloca double, align 8 6512 // CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 6513 // CHECK7-NEXT: store double 5.000000e+00, double* [[A]], align 8 6514 // CHECK7-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 6515 // CHECK7-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 6516 // CHECK7-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 6517 // CHECK7-NEXT: store i64 1, i64* [[I]], align 8 6518 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 6519 // CHECK7: for.cond: 6520 // CHECK7-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 6521 // CHECK7-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double 6522 // CHECK7-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8 6523 // CHECK7-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]] 6524 // CHECK7-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]] 6525 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6526 // CHECK7: for.body: 6527 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 6528 // CHECK7: for.inc: 6529 // CHECK7-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8 6530 // CHECK7-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1 6531 // CHECK7-NEXT: store i64 [[INC]], i64* [[I]], align 8 6532 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 6533 // CHECK7: for.end: 6534 // CHECK7-NEXT: ret void 6535 // 6536 // 6537 // CHECK7-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 6538 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6539 // CHECK7-NEXT: entry: 6540 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6541 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6542 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6543 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6544 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 6545 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6546 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6547 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6548 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6549 // CHECK7-NEXT: store i32 33, i32* [[I]], align 4 6550 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 6551 // CHECK7: for.cond: 6552 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 6553 // CHECK7-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 6554 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6555 // CHECK7: for.body: 6556 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6557 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 6558 // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 6559 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 6560 // CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6561 // CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6562 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 6563 // CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 6564 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 6565 // CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6566 // CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 6567 // CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 6568 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 6569 // CHECK7-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 6570 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 6571 // CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6572 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 6573 // CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 6574 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 6575 // CHECK7-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 6576 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 6577 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 6578 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 6579 // CHECK7: for.inc: 6580 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 6581 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 6582 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6583 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 6584 // CHECK7: for.end: 6585 // CHECK7-NEXT: ret void 6586 // 6587 // 6588 // CHECK7-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 6589 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6590 // CHECK7-NEXT: entry: 6591 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6592 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6593 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6594 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6595 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 6596 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6597 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6598 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6599 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6600 // CHECK7-NEXT: store i32 32000000, i32* [[I]], align 4 6601 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 6602 // CHECK7: for.cond: 6603 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 6604 // CHECK7-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 6605 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6606 // CHECK7: for.body: 6607 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6608 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 6609 // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 6610 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 6611 // CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6612 // CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6613 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 6614 // CHECK7-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 6615 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 6616 // CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6617 // CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 6618 // CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 6619 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 6620 // CHECK7-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 6621 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 6622 // CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6623 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 6624 // CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 6625 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 6626 // CHECK7-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 6627 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 6628 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 6629 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 6630 // CHECK7: for.inc: 6631 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 6632 // CHECK7-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 6633 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6634 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 6635 // CHECK7: for.end: 6636 // CHECK7-NEXT: ret void 6637 // 6638 // 6639 // CHECK7-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 6640 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6641 // CHECK7-NEXT: entry: 6642 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6643 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6644 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6645 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6646 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 6647 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6648 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6649 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6650 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6651 // CHECK7-NEXT: store i32 131071, i32* [[I]], align 4 6652 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 6653 // CHECK7: for.cond: 6654 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 6655 // CHECK7-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 6656 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6657 // CHECK7: for.body: 6658 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6659 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 6660 // CHECK7-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 6661 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 6662 // CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6663 // CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6664 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 6665 // CHECK7-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 6666 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 6667 // CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6668 // CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 6669 // CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 6670 // CHECK7-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 6671 // CHECK7-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 6672 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 6673 // CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6674 // CHECK7-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 6675 // CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 6676 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 6677 // CHECK7-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 6678 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 6679 // CHECK7-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 6680 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 6681 // CHECK7: for.inc: 6682 // CHECK7-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 6683 // CHECK7-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 6684 // CHECK7-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6685 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 6686 // CHECK7: for.end: 6687 // CHECK7-NEXT: ret void 6688 // 6689 // 6690 // CHECK7-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 6691 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6692 // CHECK7-NEXT: entry: 6693 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6694 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6695 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6696 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6697 // CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 6698 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6699 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6700 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6701 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6702 // CHECK7-NEXT: store i64 131071, i64* [[I]], align 8 6703 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 6704 // CHECK7: for.cond: 6705 // CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 6706 // CHECK7-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 6707 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6708 // CHECK7: for.body: 6709 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6710 // CHECK7-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 6711 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 6712 // CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6713 // CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6714 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 6715 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 6716 // CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 6717 // CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 6718 // CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 6719 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 6720 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 6721 // CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6722 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 6723 // CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 6724 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 6725 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 6726 // CHECK7-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 6727 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 6728 // CHECK7: for.inc: 6729 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 6730 // CHECK7-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 6731 // CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8 6732 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 6733 // CHECK7: for.end: 6734 // CHECK7-NEXT: ret void 6735 // 6736 // 6737 // CHECK7-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 6738 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6739 // CHECK7-NEXT: entry: 6740 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6741 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6742 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6743 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6744 // CHECK7-NEXT: [[I:%.*]] = alloca i64, align 8 6745 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6746 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6747 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6748 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6749 // CHECK7-NEXT: store i64 131071, i64* [[I]], align 8 6750 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 6751 // CHECK7: for.cond: 6752 // CHECK7-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 6753 // CHECK7-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 6754 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6755 // CHECK7: for.body: 6756 // CHECK7-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 6757 // CHECK7-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 6758 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 6759 // CHECK7-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 6760 // CHECK7-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 6761 // CHECK7-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 6762 // CHECK7-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 6763 // CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 6764 // CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 6765 // CHECK7-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 6766 // CHECK7-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 6767 // CHECK7-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 6768 // CHECK7-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 6769 // CHECK7-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 6770 // CHECK7-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 6771 // CHECK7-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 6772 // CHECK7-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 6773 // CHECK7-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 6774 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 6775 // CHECK7: for.inc: 6776 // CHECK7-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 6777 // CHECK7-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 6778 // CHECK7-NEXT: store i64 [[ADD]], i64* [[I]], align 8 6779 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 6780 // CHECK7: for.end: 6781 // CHECK7-NEXT: ret void 6782 // 6783 // 6784 // CHECK7-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 6785 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6786 // CHECK7-NEXT: entry: 6787 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6788 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6789 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6790 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6791 // CHECK7-NEXT: [[X:%.*]] = alloca i32, align 4 6792 // CHECK7-NEXT: [[Y:%.*]] = alloca i32, align 4 6793 // CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1 6794 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6795 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6796 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6797 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6798 // CHECK7-NEXT: store i32 0, i32* [[X]], align 4 6799 // CHECK7-NEXT: store i32 0, i32* [[Y]], align 4 6800 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 6801 // CHECK7-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 6802 // CHECK7-NEXT: store i8 [[CONV]], i8* [[I]], align 1 6803 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 6804 // CHECK7: for.cond: 6805 // CHECK7-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 6806 // CHECK7-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 6807 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 6808 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 6809 // CHECK7: for.body: 6810 // CHECK7-NEXT: store i32 11, i32* [[X]], align 4 6811 // CHECK7-NEXT: br label [[FOR_COND2:%.*]] 6812 // CHECK7: for.cond2: 6813 // CHECK7-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 6814 // CHECK7-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 6815 // CHECK7-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 6816 // CHECK7: for.body4: 6817 // CHECK7-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 6818 // CHECK7-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 6819 // CHECK7-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 6820 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] 6821 // CHECK7-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 6822 // CHECK7-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 6823 // CHECK7-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 6824 // CHECK7-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 6825 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] 6826 // CHECK7-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 6827 // CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] 6828 // CHECK7-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 6829 // CHECK7-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 6830 // CHECK7-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 6831 // CHECK7-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] 6832 // CHECK7-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 6833 // CHECK7-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] 6834 // CHECK7-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 6835 // CHECK7-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 6836 // CHECK7-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 6837 // CHECK7-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] 6838 // CHECK7-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 6839 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 6840 // CHECK7: for.inc: 6841 // CHECK7-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 6842 // CHECK7-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 6843 // CHECK7-NEXT: store i32 [[DEC]], i32* [[X]], align 4 6844 // CHECK7-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] 6845 // CHECK7: for.end: 6846 // CHECK7-NEXT: br label [[FOR_INC12:%.*]] 6847 // CHECK7: for.inc12: 6848 // CHECK7-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 6849 // CHECK7-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 6850 // CHECK7-NEXT: store i8 [[INC]], i8* [[I]], align 1 6851 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 6852 // CHECK7: for.end13: 6853 // CHECK7-NEXT: ret void 6854 // 6855 // 6856 // CHECK7-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 6857 // CHECK7-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6858 // CHECK7-NEXT: entry: 6859 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6860 // CHECK7-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6861 // CHECK7-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6862 // CHECK7-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6863 // CHECK7-NEXT: [[X:%.*]] = alloca i32, align 4 6864 // CHECK7-NEXT: [[I:%.*]] = alloca i8, align 1 6865 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6866 // CHECK7-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6867 // CHECK7-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6868 // CHECK7-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6869 // CHECK7-NEXT: store i32 0, i32* [[X]], align 4 6870 // CHECK7-NEXT: store i8 48, i8* [[I]], align 1 6871 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 6872 // CHECK7: for.cond: 6873 // CHECK7-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 6874 // CHECK7-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 6875 // CHECK7-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 6876 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 6877 // CHECK7: for.body: 6878 // CHECK7-NEXT: store i32 -10, i32* [[X]], align 4 6879 // CHECK7-NEXT: br label [[FOR_COND1:%.*]] 6880 // CHECK7: for.cond1: 6881 // CHECK7-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 6882 // CHECK7-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 6883 // CHECK7-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 6884 // CHECK7: for.body3: 6885 // CHECK7-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 6886 // CHECK7-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 6887 // CHECK7-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 6888 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] 6889 // CHECK7-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 6890 // CHECK7-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 6891 // CHECK7-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 6892 // CHECK7-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 6893 // CHECK7-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] 6894 // CHECK7-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 6895 // CHECK7-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] 6896 // CHECK7-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 6897 // CHECK7-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 6898 // CHECK7-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 6899 // CHECK7-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] 6900 // CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 6901 // CHECK7-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] 6902 // CHECK7-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 6903 // CHECK7-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 6904 // CHECK7-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 6905 // CHECK7-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] 6906 // CHECK7-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 6907 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 6908 // CHECK7: for.inc: 6909 // CHECK7-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 6910 // CHECK7-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 6911 // CHECK7-NEXT: store i32 [[INC]], i32* [[X]], align 4 6912 // CHECK7-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] 6913 // CHECK7: for.end: 6914 // CHECK7-NEXT: br label [[FOR_INC11:%.*]] 6915 // CHECK7: for.inc11: 6916 // CHECK7-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 6917 // CHECK7-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 6918 // CHECK7-NEXT: store i8 [[INC12]], i8* [[I]], align 1 6919 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 6920 // CHECK7: for.end13: 6921 // CHECK7-NEXT: ret void 6922 // 6923 // 6924 // CHECK7-LABEL: define {{[^@]+}}@_Z3foov 6925 // CHECK7-SAME: () #[[ATTR1:[0-9]+]] { 6926 // CHECK7-NEXT: entry: 6927 // CHECK7-NEXT: call void @_Z8mayThrowv() 6928 // CHECK7-NEXT: ret i32 0 6929 // 6930 // 6931 // CHECK7-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 6932 // CHECK7-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 6933 // CHECK7-NEXT: entry: 6934 // CHECK7-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6935 // CHECK7-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 6936 // CHECK7-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6937 // CHECK7-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6938 // CHECK7-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 6939 // CHECK7-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 6940 // CHECK7-NEXT: [[I:%.*]] = alloca i32, align 4 6941 // CHECK7-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6942 // CHECK7-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 6943 // CHECK7-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 6944 // CHECK7-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 6945 // CHECK7-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 6946 // CHECK7-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 6947 // CHECK7-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 6948 // CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 6949 // CHECK7-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 6950 // CHECK7-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8 6951 // CHECK7-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16 6952 // CHECK7-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 6953 // CHECK7-NEXT: store i32 131071, i32* [[I]], align 4 6954 // CHECK7-NEXT: br label [[FOR_COND:%.*]] 6955 // CHECK7: for.cond: 6956 // CHECK7-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 6957 // CHECK7-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647 6958 // CHECK7-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 6959 // CHECK7: for.body: 6960 // CHECK7-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 6961 // CHECK7-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 6962 // CHECK7: invoke.cont: 6963 // CHECK7-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float 6964 // CHECK7-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 6965 // CHECK7-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 6966 // CHECK7-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]] 6967 // CHECK7-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 6968 // CHECK7-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]] 6969 // CHECK7-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 6970 // CHECK7-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float 6971 // CHECK7-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]] 6972 // CHECK7-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 6973 // CHECK7-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 6974 // CHECK7-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64 6975 // CHECK7-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]] 6976 // CHECK7-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4 6977 // CHECK7-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]] 6978 // CHECK7-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4 6979 // CHECK7-NEXT: br label [[FOR_INC:%.*]] 6980 // CHECK7: for.inc: 6981 // CHECK7-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 6982 // CHECK7-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127 6983 // CHECK7-NEXT: store i32 [[ADD8]], i32* [[I]], align 4 6984 // CHECK7-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 6985 // CHECK7: for.end: 6986 // CHECK7-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8 6987 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) 6988 // CHECK7-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 6989 // CHECK7-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) 6990 // CHECK7-NEXT: ret void 6991 // CHECK7: terminate.lpad: 6992 // CHECK7-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } 6993 // CHECK7-NEXT: catch i8* null 6994 // CHECK7-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 6995 // CHECK7-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]] 6996 // CHECK7-NEXT: unreachable 6997 // 6998 // 6999 // CHECK7-LABEL: define {{[^@]+}}@__clang_call_terminate 7000 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { 7001 // CHECK7-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] 7002 // CHECK7-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] 7003 // CHECK7-NEXT: unreachable 7004 // 7005 // 7006 // CHECK8-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 7007 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] { 7008 // CHECK8-NEXT: entry: 7009 // CHECK8-NEXT: [[A:%.*]] = alloca double, align 8 7010 // CHECK8-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 7011 // CHECK8-NEXT: [[A1:%.*]] = alloca double, align 8 7012 // CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 7013 // CHECK8-NEXT: store double 5.000000e+00, double* [[A]], align 8 7014 // CHECK8-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 7015 // CHECK8-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 7016 // CHECK8-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 7017 // CHECK8-NEXT: store i64 1, i64* [[I]], align 8 7018 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 7019 // CHECK8: for.cond: 7020 // CHECK8-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8 7021 // CHECK8-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double 7022 // CHECK8-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8 7023 // CHECK8-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]] 7024 // CHECK8-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]] 7025 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7026 // CHECK8: for.body: 7027 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 7028 // CHECK8: for.inc: 7029 // CHECK8-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8 7030 // CHECK8-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1 7031 // CHECK8-NEXT: store i64 [[INC]], i64* [[I]], align 8 7032 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 7033 // CHECK8: for.end: 7034 // CHECK8-NEXT: ret void 7035 // 7036 // 7037 // CHECK8-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 7038 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7039 // CHECK8-NEXT: entry: 7040 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7041 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7042 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7043 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7044 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 7045 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7046 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7047 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7048 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7049 // CHECK8-NEXT: store i32 33, i32* [[I]], align 4 7050 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 7051 // CHECK8: for.cond: 7052 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7053 // CHECK8-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000 7054 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7055 // CHECK8: for.body: 7056 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7057 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7058 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 7059 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7060 // CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7061 // CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7062 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7063 // CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 7064 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7065 // CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7066 // CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7067 // CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7068 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7069 // CHECK8-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 7070 // CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7071 // CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7072 // CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7073 // CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7074 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7075 // CHECK8-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 7076 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7077 // CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7078 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 7079 // CHECK8: for.inc: 7080 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7081 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7 7082 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7083 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 7084 // CHECK8: for.end: 7085 // CHECK8-NEXT: ret void 7086 // 7087 // 7088 // CHECK8-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 7089 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7090 // CHECK8-NEXT: entry: 7091 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7092 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7093 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7094 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7095 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 7096 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7097 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7098 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7099 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7100 // CHECK8-NEXT: store i32 32000000, i32* [[I]], align 4 7101 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 7102 // CHECK8: for.cond: 7103 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7104 // CHECK8-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33 7105 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7106 // CHECK8: for.body: 7107 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7108 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7109 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64 7110 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7111 // CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7112 // CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7113 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7114 // CHECK8-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64 7115 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7116 // CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7117 // CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7118 // CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7119 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7120 // CHECK8-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64 7121 // CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7122 // CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7123 // CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7124 // CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7125 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7126 // CHECK8-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64 7127 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7128 // CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7129 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 7130 // CHECK8: for.inc: 7131 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7132 // CHECK8-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7 7133 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7134 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP5:![0-9]+]] 7135 // CHECK8: for.end: 7136 // CHECK8-NEXT: ret void 7137 // 7138 // 7139 // CHECK8-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 7140 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7141 // CHECK8-NEXT: entry: 7142 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7143 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7144 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7145 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7146 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 7147 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7148 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7149 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7150 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7151 // CHECK8-NEXT: store i32 131071, i32* [[I]], align 4 7152 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 7153 // CHECK8: for.cond: 7154 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 7155 // CHECK8-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647 7156 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7157 // CHECK8: for.body: 7158 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7159 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4 7160 // CHECK8-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64 7161 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]] 7162 // CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7163 // CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7164 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7165 // CHECK8-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64 7166 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]] 7167 // CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7168 // CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7169 // CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7170 // CHECK8-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4 7171 // CHECK8-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64 7172 // CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]] 7173 // CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4 7174 // CHECK8-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]] 7175 // CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7176 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7177 // CHECK8-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64 7178 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]] 7179 // CHECK8-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4 7180 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 7181 // CHECK8: for.inc: 7182 // CHECK8-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4 7183 // CHECK8-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127 7184 // CHECK8-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7185 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 7186 // CHECK8: for.end: 7187 // CHECK8-NEXT: ret void 7188 // 7189 // 7190 // CHECK8-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 7191 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7192 // CHECK8-NEXT: entry: 7193 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7194 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7195 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7196 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7197 // CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 7198 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7199 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7200 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7201 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7202 // CHECK8-NEXT: store i64 131071, i64* [[I]], align 8 7203 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 7204 // CHECK8: for.cond: 7205 // CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 7206 // CHECK8-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 7207 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7208 // CHECK8: for.body: 7209 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7210 // CHECK8-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 7211 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 7212 // CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7213 // CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7214 // CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 7215 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 7216 // CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 7217 // CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7218 // CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7219 // CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 7220 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 7221 // CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7222 // CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 7223 // CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7224 // CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 7225 // CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 7226 // CHECK8-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 7227 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 7228 // CHECK8: for.inc: 7229 // CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 7230 // CHECK8-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 7231 // CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8 7232 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP7:![0-9]+]] 7233 // CHECK8: for.end: 7234 // CHECK8-NEXT: ret void 7235 // 7236 // 7237 // CHECK8-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 7238 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7239 // CHECK8-NEXT: entry: 7240 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7241 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7242 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7243 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7244 // CHECK8-NEXT: [[I:%.*]] = alloca i64, align 8 7245 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7246 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7247 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7248 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7249 // CHECK8-NEXT: store i64 131071, i64* [[I]], align 8 7250 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 7251 // CHECK8: for.cond: 7252 // CHECK8-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8 7253 // CHECK8-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647 7254 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7255 // CHECK8: for.body: 7256 // CHECK8-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8 7257 // CHECK8-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8 7258 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]] 7259 // CHECK8-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4 7260 // CHECK8-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8 7261 // CHECK8-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8 7262 // CHECK8-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]] 7263 // CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4 7264 // CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]] 7265 // CHECK8-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8 7266 // CHECK8-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8 7267 // CHECK8-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]] 7268 // CHECK8-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4 7269 // CHECK8-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]] 7270 // CHECK8-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8 7271 // CHECK8-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8 7272 // CHECK8-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]] 7273 // CHECK8-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4 7274 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 7275 // CHECK8: for.inc: 7276 // CHECK8-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8 7277 // CHECK8-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127 7278 // CHECK8-NEXT: store i64 [[ADD]], i64* [[I]], align 8 7279 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]] 7280 // CHECK8: for.end: 7281 // CHECK8-NEXT: ret void 7282 // 7283 // 7284 // CHECK8-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 7285 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7286 // CHECK8-NEXT: entry: 7287 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7288 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7289 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7290 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7291 // CHECK8-NEXT: [[X:%.*]] = alloca i32, align 4 7292 // CHECK8-NEXT: [[Y:%.*]] = alloca i32, align 4 7293 // CHECK8-NEXT: [[I:%.*]] = alloca i8, align 1 7294 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7295 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7296 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7297 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7298 // CHECK8-NEXT: store i32 0, i32* [[X]], align 4 7299 // CHECK8-NEXT: store i32 0, i32* [[Y]], align 4 7300 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4 7301 // CHECK8-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8 7302 // CHECK8-NEXT: store i8 [[CONV]], i8* [[I]], align 1 7303 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 7304 // CHECK8: for.cond: 7305 // CHECK8-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1 7306 // CHECK8-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32 7307 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57 7308 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 7309 // CHECK8: for.body: 7310 // CHECK8-NEXT: store i32 11, i32* [[X]], align 4 7311 // CHECK8-NEXT: br label [[FOR_COND2:%.*]] 7312 // CHECK8: for.cond2: 7313 // CHECK8-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4 7314 // CHECK8-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0 7315 // CHECK8-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]] 7316 // CHECK8: for.body4: 7317 // CHECK8-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8 7318 // CHECK8-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1 7319 // CHECK8-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64 7320 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]] 7321 // CHECK8-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4 7322 // CHECK8-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8 7323 // CHECK8-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1 7324 // CHECK8-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64 7325 // CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]] 7326 // CHECK8-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4 7327 // CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]] 7328 // CHECK8-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8 7329 // CHECK8-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1 7330 // CHECK8-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64 7331 // CHECK8-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]] 7332 // CHECK8-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4 7333 // CHECK8-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]] 7334 // CHECK8-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8 7335 // CHECK8-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1 7336 // CHECK8-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64 7337 // CHECK8-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]] 7338 // CHECK8-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4 7339 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 7340 // CHECK8: for.inc: 7341 // CHECK8-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4 7342 // CHECK8-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1 7343 // CHECK8-NEXT: store i32 [[DEC]], i32* [[X]], align 4 7344 // CHECK8-NEXT: br label [[FOR_COND2]], !llvm.loop [[LOOP9:![0-9]+]] 7345 // CHECK8: for.end: 7346 // CHECK8-NEXT: br label [[FOR_INC12:%.*]] 7347 // CHECK8: for.inc12: 7348 // CHECK8-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1 7349 // CHECK8-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1 7350 // CHECK8-NEXT: store i8 [[INC]], i8* [[I]], align 1 7351 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP10:![0-9]+]] 7352 // CHECK8: for.end13: 7353 // CHECK8-NEXT: ret void 7354 // 7355 // 7356 // CHECK8-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 7357 // CHECK8-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7358 // CHECK8-NEXT: entry: 7359 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7360 // CHECK8-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7361 // CHECK8-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7362 // CHECK8-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7363 // CHECK8-NEXT: [[X:%.*]] = alloca i32, align 4 7364 // CHECK8-NEXT: [[I:%.*]] = alloca i8, align 1 7365 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7366 // CHECK8-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7367 // CHECK8-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7368 // CHECK8-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7369 // CHECK8-NEXT: store i32 0, i32* [[X]], align 4 7370 // CHECK8-NEXT: store i8 48, i8* [[I]], align 1 7371 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 7372 // CHECK8: for.cond: 7373 // CHECK8-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1 7374 // CHECK8-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32 7375 // CHECK8-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57 7376 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]] 7377 // CHECK8: for.body: 7378 // CHECK8-NEXT: store i32 -10, i32* [[X]], align 4 7379 // CHECK8-NEXT: br label [[FOR_COND1:%.*]] 7380 // CHECK8: for.cond1: 7381 // CHECK8-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4 7382 // CHECK8-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10 7383 // CHECK8-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]] 7384 // CHECK8: for.body3: 7385 // CHECK8-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8 7386 // CHECK8-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1 7387 // CHECK8-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64 7388 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]] 7389 // CHECK8-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4 7390 // CHECK8-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8 7391 // CHECK8-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1 7392 // CHECK8-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64 7393 // CHECK8-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]] 7394 // CHECK8-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4 7395 // CHECK8-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]] 7396 // CHECK8-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8 7397 // CHECK8-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1 7398 // CHECK8-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64 7399 // CHECK8-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]] 7400 // CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4 7401 // CHECK8-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]] 7402 // CHECK8-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8 7403 // CHECK8-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1 7404 // CHECK8-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64 7405 // CHECK8-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]] 7406 // CHECK8-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 7407 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 7408 // CHECK8: for.inc: 7409 // CHECK8-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4 7410 // CHECK8-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1 7411 // CHECK8-NEXT: store i32 [[INC]], i32* [[X]], align 4 7412 // CHECK8-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP11:![0-9]+]] 7413 // CHECK8: for.end: 7414 // CHECK8-NEXT: br label [[FOR_INC11:%.*]] 7415 // CHECK8: for.inc11: 7416 // CHECK8-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1 7417 // CHECK8-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1 7418 // CHECK8-NEXT: store i8 [[INC12]], i8* [[I]], align 1 7419 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 7420 // CHECK8: for.end13: 7421 // CHECK8-NEXT: ret void 7422 // 7423 // 7424 // CHECK8-LABEL: define {{[^@]+}}@_Z3foov 7425 // CHECK8-SAME: () #[[ATTR1:[0-9]+]] { 7426 // CHECK8-NEXT: entry: 7427 // CHECK8-NEXT: call void @_Z8mayThrowv() 7428 // CHECK8-NEXT: ret i32 0 7429 // 7430 // 7431 // CHECK8-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 7432 // CHECK8-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 7433 // CHECK8-NEXT: entry: 7434 // CHECK8-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7435 // CHECK8-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7436 // CHECK8-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7437 // CHECK8-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7438 // CHECK8-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 7439 // CHECK8-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7440 // CHECK8-NEXT: [[I:%.*]] = alloca i32, align 4 7441 // CHECK8-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7442 // CHECK8-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7443 // CHECK8-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7444 // CHECK8-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 7445 // CHECK8-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 7446 // CHECK8-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 7447 // CHECK8-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 7448 // CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 7449 // CHECK8-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave() 7450 // CHECK8-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8 7451 // CHECK8-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16 7452 // CHECK8-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8 7453 // CHECK8-NEXT: store i32 131071, i32* [[I]], align 4 7454 // CHECK8-NEXT: br label [[FOR_COND:%.*]] 7455 // CHECK8: for.cond: 7456 // CHECK8-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4 7457 // CHECK8-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647 7458 // CHECK8-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 7459 // CHECK8: for.body: 7460 // CHECK8-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 7461 // CHECK8-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 7462 // CHECK8: invoke.cont: 7463 // CHECK8-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float 7464 // CHECK8-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4 7465 // CHECK8-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64 7466 // CHECK8-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]] 7467 // CHECK8-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4 7468 // CHECK8-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]] 7469 // CHECK8-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4 7470 // CHECK8-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float 7471 // CHECK8-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]] 7472 // CHECK8-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8 7473 // CHECK8-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4 7474 // CHECK8-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64 7475 // CHECK8-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]] 7476 // CHECK8-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4 7477 // CHECK8-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]] 7478 // CHECK8-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4 7479 // CHECK8-NEXT: br label [[FOR_INC:%.*]] 7480 // CHECK8: for.inc: 7481 // CHECK8-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4 7482 // CHECK8-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127 7483 // CHECK8-NEXT: store i32 [[ADD8]], i32* [[I]], align 4 7484 // CHECK8-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP13:![0-9]+]] 7485 // CHECK8: for.end: 7486 // CHECK8-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8 7487 // CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]) 7488 // CHECK8-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7489 // CHECK8-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]) 7490 // CHECK8-NEXT: ret void 7491 // CHECK8: terminate.lpad: 7492 // CHECK8-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } 7493 // CHECK8-NEXT: catch i8* null 7494 // CHECK8-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0 7495 // CHECK8-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]] 7496 // CHECK8-NEXT: unreachable 7497 // 7498 // 7499 // CHECK8-LABEL: define {{[^@]+}}@__clang_call_terminate 7500 // CHECK8-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] comdat { 7501 // CHECK8-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] 7502 // CHECK8-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] 7503 // CHECK8-NEXT: unreachable 7504 // 7505 // 7506 // CHECK9-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 7507 // CHECK9-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG6:![0-9]+]] { 7508 // CHECK9-NEXT: entry: 7509 // CHECK9-NEXT: [[A:%.*]] = alloca double, align 8 7510 // CHECK9-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 7511 // CHECK9-NEXT: [[A1:%.*]] = alloca double, align 8 7512 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7513 // CHECK9-NEXT: store double 5.000000e+00, double* [[A]], align 8, !dbg [[DBG9:![0-9]+]] 7514 // CHECK9-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8, !dbg [[DBG10:![0-9]+]] 7515 // CHECK9-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG10]] 7516 // CHECK9-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11:![0-9]+]] 7517 // CHECK9-NEXT: store i64 1, i64* [[I]], align 8, !dbg [[DBG12:![0-9]+]] 7518 // CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG13:![0-9]+]] 7519 // CHECK9: for.cond: 7520 // CHECK9-NEXT: [[TMP1:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG14:![0-9]+]] 7521 // CHECK9-NEXT: [[CONV2:%.*]] = uitofp i64 [[TMP1]] to double, !dbg [[DBG14]] 7522 // CHECK9-NEXT: [[TMP2:%.*]] = load double, double* [[A1]], align 8, !dbg [[DBG15:![0-9]+]] 7523 // CHECK9-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP2]], !dbg [[DBG16:![0-9]+]] 7524 // CHECK9-NEXT: [[CMP:%.*]] = fcmp olt double [[CONV2]], [[ADD]], !dbg [[DBG17:![0-9]+]] 7525 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG18:![0-9]+]] 7526 // CHECK9: for.body: 7527 // CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG19:![0-9]+]] 7528 // CHECK9: for.inc: 7529 // CHECK9-NEXT: [[TMP3:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG20:![0-9]+]] 7530 // CHECK9-NEXT: [[INC:%.*]] = add i64 [[TMP3]], 1, !dbg [[DBG20]] 7531 // CHECK9-NEXT: store i64 [[INC]], i64* [[I]], align 8, !dbg [[DBG20]] 7532 // CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG18]], !llvm.loop [[LOOP21:![0-9]+]] 7533 // CHECK9: for.end: 7534 // CHECK9-NEXT: ret void, !dbg [[DBG23:![0-9]+]] 7535 // 7536 // 7537 // CHECK9-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 7538 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG24:![0-9]+]] { 7539 // CHECK9-NEXT: entry: 7540 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7541 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7542 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7543 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7544 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7545 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7546 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7547 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7548 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7549 // CHECK9-NEXT: store i32 33, i32* [[I]], align 4, !dbg [[DBG25:![0-9]+]] 7550 // CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG26:![0-9]+]] 7551 // CHECK9: for.cond: 7552 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27:![0-9]+]] 7553 // CHECK9-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP0]], 32000000, !dbg [[DBG28:![0-9]+]] 7554 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG29:![0-9]+]] 7555 // CHECK9: for.body: 7556 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG30:![0-9]+]] 7557 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG31:![0-9]+]] 7558 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64, !dbg [[DBG30]] 7559 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]], !dbg [[DBG30]] 7560 // CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG30]] 7561 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG32:![0-9]+]] 7562 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG33:![0-9]+]] 7563 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64, !dbg [[DBG32]] 7564 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]], !dbg [[DBG32]] 7565 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG32]] 7566 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG34:![0-9]+]] 7567 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG35:![0-9]+]] 7568 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36:![0-9]+]] 7569 // CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG35]] 7570 // CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]], !dbg [[DBG35]] 7571 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG35]] 7572 // CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG37:![0-9]+]] 7573 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG38:![0-9]+]] 7574 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG39:![0-9]+]] 7575 // CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG38]] 7576 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]], !dbg [[DBG38]] 7577 // CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG40:![0-9]+]] 7578 // CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG41:![0-9]+]] 7579 // CHECK9: for.inc: 7580 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG42:![0-9]+]] 7581 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], 7, !dbg [[DBG42]] 7582 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG42]] 7583 // CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG29]], !llvm.loop [[LOOP43:![0-9]+]] 7584 // CHECK9: for.end: 7585 // CHECK9-NEXT: ret void, !dbg [[DBG44:![0-9]+]] 7586 // 7587 // 7588 // CHECK9-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 7589 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG45:![0-9]+]] { 7590 // CHECK9-NEXT: entry: 7591 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7592 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7593 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7594 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7595 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7596 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7597 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7598 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7599 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7600 // CHECK9-NEXT: store i32 32000000, i32* [[I]], align 4, !dbg [[DBG46:![0-9]+]] 7601 // CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG47:![0-9]+]] 7602 // CHECK9: for.cond: 7603 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG48:![0-9]+]] 7604 // CHECK9-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 33, !dbg [[DBG49:![0-9]+]] 7605 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG50:![0-9]+]] 7606 // CHECK9: for.body: 7607 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG51:![0-9]+]] 7608 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG52:![0-9]+]] 7609 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP2]] to i64, !dbg [[DBG51]] 7610 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]], !dbg [[DBG51]] 7611 // CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG51]] 7612 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG53:![0-9]+]] 7613 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG54:![0-9]+]] 7614 // CHECK9-NEXT: [[IDXPROM1:%.*]] = sext i32 [[TMP5]] to i64, !dbg [[DBG53]] 7615 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]], !dbg [[DBG53]] 7616 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG53]] 7617 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG55:![0-9]+]] 7618 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG56:![0-9]+]] 7619 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG57:![0-9]+]] 7620 // CHECK9-NEXT: [[IDXPROM3:%.*]] = sext i32 [[TMP8]] to i64, !dbg [[DBG56]] 7621 // CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]], !dbg [[DBG56]] 7622 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG56]] 7623 // CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG58:![0-9]+]] 7624 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG59:![0-9]+]] 7625 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG60:![0-9]+]] 7626 // CHECK9-NEXT: [[IDXPROM6:%.*]] = sext i32 [[TMP11]] to i64, !dbg [[DBG59]] 7627 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]], !dbg [[DBG59]] 7628 // CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG61:![0-9]+]] 7629 // CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG62:![0-9]+]] 7630 // CHECK9: for.inc: 7631 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG63:![0-9]+]] 7632 // CHECK9-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP12]], -7, !dbg [[DBG63]] 7633 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG63]] 7634 // CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG50]], !llvm.loop [[LOOP64:![0-9]+]] 7635 // CHECK9: for.end: 7636 // CHECK9-NEXT: ret void, !dbg [[DBG65:![0-9]+]] 7637 // 7638 // 7639 // CHECK9-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 7640 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG66:![0-9]+]] { 7641 // CHECK9-NEXT: entry: 7642 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7643 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7644 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7645 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7646 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7647 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7648 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7649 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7650 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7651 // CHECK9-NEXT: store i32 131071, i32* [[I]], align 4, !dbg [[DBG67:![0-9]+]] 7652 // CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG68:![0-9]+]] 7653 // CHECK9: for.cond: 7654 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG69:![0-9]+]] 7655 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP0]], 2147483647, !dbg [[DBG70:![0-9]+]] 7656 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG71:![0-9]+]] 7657 // CHECK9: for.body: 7658 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG72:![0-9]+]] 7659 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG73:![0-9]+]] 7660 // CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP2]] to i64, !dbg [[DBG72]] 7661 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[IDXPROM]], !dbg [[DBG72]] 7662 // CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG72]] 7663 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG74:![0-9]+]] 7664 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG75:![0-9]+]] 7665 // CHECK9-NEXT: [[IDXPROM1:%.*]] = zext i32 [[TMP5]] to i64, !dbg [[DBG74]] 7666 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[IDXPROM1]], !dbg [[DBG74]] 7667 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG74]] 7668 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG76:![0-9]+]] 7669 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG77:![0-9]+]] 7670 // CHECK9-NEXT: [[TMP8:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG78:![0-9]+]] 7671 // CHECK9-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP8]] to i64, !dbg [[DBG77]] 7672 // CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[IDXPROM3]], !dbg [[DBG77]] 7673 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG77]] 7674 // CHECK9-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG79:![0-9]+]] 7675 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG80:![0-9]+]] 7676 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG81:![0-9]+]] 7677 // CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP11]] to i64, !dbg [[DBG80]] 7678 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[IDXPROM6]], !dbg [[DBG80]] 7679 // CHECK9-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG82:![0-9]+]] 7680 // CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG83:![0-9]+]] 7681 // CHECK9: for.inc: 7682 // CHECK9-NEXT: [[TMP12:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG84:![0-9]+]] 7683 // CHECK9-NEXT: [[ADD:%.*]] = add i32 [[TMP12]], 127, !dbg [[DBG84]] 7684 // CHECK9-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG84]] 7685 // CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG71]], !llvm.loop [[LOOP85:![0-9]+]] 7686 // CHECK9: for.end: 7687 // CHECK9-NEXT: ret void, !dbg [[DBG86:![0-9]+]] 7688 // 7689 // 7690 // CHECK9-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 7691 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG87:![0-9]+]] { 7692 // CHECK9-NEXT: entry: 7693 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7694 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7695 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7696 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7697 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7698 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7699 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7700 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7701 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7702 // CHECK9-NEXT: store i64 131071, i64* [[I]], align 8, !dbg [[DBG88:![0-9]+]] 7703 // CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG89:![0-9]+]] 7704 // CHECK9: for.cond: 7705 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG90:![0-9]+]] 7706 // CHECK9-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647, !dbg [[DBG91:![0-9]+]] 7707 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG92:![0-9]+]] 7708 // CHECK9: for.body: 7709 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG93:![0-9]+]] 7710 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG94:![0-9]+]] 7711 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]], !dbg [[DBG93]] 7712 // CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG93]] 7713 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG95:![0-9]+]] 7714 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG96:![0-9]+]] 7715 // CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]], !dbg [[DBG95]] 7716 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !dbg [[DBG95]] 7717 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG97:![0-9]+]] 7718 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG98:![0-9]+]] 7719 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG99:![0-9]+]] 7720 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]], !dbg [[DBG98]] 7721 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG98]] 7722 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG100:![0-9]+]] 7723 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG101:![0-9]+]] 7724 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG102:![0-9]+]] 7725 // CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]], !dbg [[DBG101]] 7726 // CHECK9-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !dbg [[DBG103:![0-9]+]] 7727 // CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG104:![0-9]+]] 7728 // CHECK9: for.inc: 7729 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG105:![0-9]+]] 7730 // CHECK9-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127, !dbg [[DBG105]] 7731 // CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !dbg [[DBG105]] 7732 // CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG92]], !llvm.loop [[LOOP106:![0-9]+]] 7733 // CHECK9: for.end: 7734 // CHECK9-NEXT: ret void, !dbg [[DBG107:![0-9]+]] 7735 // 7736 // 7737 // CHECK9-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 7738 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG108:![0-9]+]] { 7739 // CHECK9-NEXT: entry: 7740 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7741 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7742 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7743 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7744 // CHECK9-NEXT: [[I:%.*]] = alloca i64, align 8 7745 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7746 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7747 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7748 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7749 // CHECK9-NEXT: store i64 131071, i64* [[I]], align 8, !dbg [[DBG109:![0-9]+]] 7750 // CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG110:![0-9]+]] 7751 // CHECK9: for.cond: 7752 // CHECK9-NEXT: [[TMP0:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG111:![0-9]+]] 7753 // CHECK9-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP0]], 2147483647, !dbg [[DBG112:![0-9]+]] 7754 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG113:![0-9]+]] 7755 // CHECK9: for.body: 7756 // CHECK9-NEXT: [[TMP1:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG114:![0-9]+]] 7757 // CHECK9-NEXT: [[TMP2:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG115:![0-9]+]] 7758 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP1]], i64 [[TMP2]], !dbg [[DBG114]] 7759 // CHECK9-NEXT: [[TMP3:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG114]] 7760 // CHECK9-NEXT: [[TMP4:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG116:![0-9]+]] 7761 // CHECK9-NEXT: [[TMP5:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG117:![0-9]+]] 7762 // CHECK9-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[TMP4]], i64 [[TMP5]], !dbg [[DBG116]] 7763 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !dbg [[DBG116]] 7764 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP3]], [[TMP6]], !dbg [[DBG118:![0-9]+]] 7765 // CHECK9-NEXT: [[TMP7:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG119:![0-9]+]] 7766 // CHECK9-NEXT: [[TMP8:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG120:![0-9]+]] 7767 // CHECK9-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP7]], i64 [[TMP8]], !dbg [[DBG119]] 7768 // CHECK9-NEXT: [[TMP9:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG119]] 7769 // CHECK9-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP9]], !dbg [[DBG121:![0-9]+]] 7770 // CHECK9-NEXT: [[TMP10:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG122:![0-9]+]] 7771 // CHECK9-NEXT: [[TMP11:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG123:![0-9]+]] 7772 // CHECK9-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP10]], i64 [[TMP11]], !dbg [[DBG122]] 7773 // CHECK9-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !dbg [[DBG124:![0-9]+]] 7774 // CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG125:![0-9]+]] 7775 // CHECK9: for.inc: 7776 // CHECK9-NEXT: [[TMP12:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG126:![0-9]+]] 7777 // CHECK9-NEXT: [[ADD:%.*]] = add i64 [[TMP12]], 127, !dbg [[DBG126]] 7778 // CHECK9-NEXT: store i64 [[ADD]], i64* [[I]], align 8, !dbg [[DBG126]] 7779 // CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG113]], !llvm.loop [[LOOP127:![0-9]+]] 7780 // CHECK9: for.end: 7781 // CHECK9-NEXT: ret void, !dbg [[DBG128:![0-9]+]] 7782 // 7783 // 7784 // CHECK9-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 7785 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG129:![0-9]+]] { 7786 // CHECK9-NEXT: entry: 7787 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7788 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7789 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7790 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7791 // CHECK9-NEXT: [[X:%.*]] = alloca i32, align 4 7792 // CHECK9-NEXT: [[Y:%.*]] = alloca i32, align 4 7793 // CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 7794 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7795 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7796 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7797 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7798 // CHECK9-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG130:![0-9]+]] 7799 // CHECK9-NEXT: store i32 0, i32* [[Y]], align 4, !dbg [[DBG131:![0-9]+]] 7800 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[Y]], align 4, !dbg [[DBG132:![0-9]+]] 7801 // CHECK9-NEXT: [[CONV:%.*]] = trunc i32 [[TMP0]] to i8, !dbg [[DBG132]] 7802 // CHECK9-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !dbg [[DBG133:![0-9]+]] 7803 // CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG134:![0-9]+]] 7804 // CHECK9: for.cond: 7805 // CHECK9-NEXT: [[TMP1:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG135:![0-9]+]] 7806 // CHECK9-NEXT: [[CONV1:%.*]] = sext i8 [[TMP1]] to i32, !dbg [[DBG135]] 7807 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV1]], 57, !dbg [[DBG136:![0-9]+]] 7808 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]], !dbg [[DBG137:![0-9]+]] 7809 // CHECK9: for.body: 7810 // CHECK9-NEXT: store i32 11, i32* [[X]], align 4, !dbg [[DBG138:![0-9]+]] 7811 // CHECK9-NEXT: br label [[FOR_COND2:%.*]], !dbg [[DBG139:![0-9]+]] 7812 // CHECK9: for.cond2: 7813 // CHECK9-NEXT: [[TMP2:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG140:![0-9]+]] 7814 // CHECK9-NEXT: [[CMP3:%.*]] = icmp ugt i32 [[TMP2]], 0, !dbg [[DBG141:![0-9]+]] 7815 // CHECK9-NEXT: br i1 [[CMP3]], label [[FOR_BODY4:%.*]], label [[FOR_END:%.*]], !dbg [[DBG142:![0-9]+]] 7816 // CHECK9: for.body4: 7817 // CHECK9-NEXT: [[TMP3:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG143:![0-9]+]] 7818 // CHECK9-NEXT: [[TMP4:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG144:![0-9]+]] 7819 // CHECK9-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP4]] to i64, !dbg [[DBG143]] 7820 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP3]], i64 [[IDXPROM]], !dbg [[DBG143]] 7821 // CHECK9-NEXT: [[TMP5:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG143]] 7822 // CHECK9-NEXT: [[TMP6:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG145:![0-9]+]] 7823 // CHECK9-NEXT: [[TMP7:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG146:![0-9]+]] 7824 // CHECK9-NEXT: [[IDXPROM5:%.*]] = sext i8 [[TMP7]] to i64, !dbg [[DBG145]] 7825 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP6]], i64 [[IDXPROM5]], !dbg [[DBG145]] 7826 // CHECK9-NEXT: [[TMP8:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG145]] 7827 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP5]], [[TMP8]], !dbg [[DBG147:![0-9]+]] 7828 // CHECK9-NEXT: [[TMP9:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG148:![0-9]+]] 7829 // CHECK9-NEXT: [[TMP10:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG149:![0-9]+]] 7830 // CHECK9-NEXT: [[IDXPROM7:%.*]] = sext i8 [[TMP10]] to i64, !dbg [[DBG148]] 7831 // CHECK9-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[TMP9]], i64 [[IDXPROM7]], !dbg [[DBG148]] 7832 // CHECK9-NEXT: [[TMP11:%.*]] = load float, float* [[ARRAYIDX8]], align 4, !dbg [[DBG148]] 7833 // CHECK9-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP11]], !dbg [[DBG150:![0-9]+]] 7834 // CHECK9-NEXT: [[TMP12:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG151:![0-9]+]] 7835 // CHECK9-NEXT: [[TMP13:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG152:![0-9]+]] 7836 // CHECK9-NEXT: [[IDXPROM10:%.*]] = sext i8 [[TMP13]] to i64, !dbg [[DBG151]] 7837 // CHECK9-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[TMP12]], i64 [[IDXPROM10]], !dbg [[DBG151]] 7838 // CHECK9-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4, !dbg [[DBG153:![0-9]+]] 7839 // CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG154:![0-9]+]] 7840 // CHECK9: for.inc: 7841 // CHECK9-NEXT: [[TMP14:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG155:![0-9]+]] 7842 // CHECK9-NEXT: [[DEC:%.*]] = add i32 [[TMP14]], -1, !dbg [[DBG155]] 7843 // CHECK9-NEXT: store i32 [[DEC]], i32* [[X]], align 4, !dbg [[DBG155]] 7844 // CHECK9-NEXT: br label [[FOR_COND2]], !dbg [[DBG142]], !llvm.loop [[LOOP156:![0-9]+]] 7845 // CHECK9: for.end: 7846 // CHECK9-NEXT: br label [[FOR_INC12:%.*]], !dbg [[DBG154]] 7847 // CHECK9: for.inc12: 7848 // CHECK9-NEXT: [[TMP15:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG157:![0-9]+]] 7849 // CHECK9-NEXT: [[INC:%.*]] = add i8 [[TMP15]], 1, !dbg [[DBG157]] 7850 // CHECK9-NEXT: store i8 [[INC]], i8* [[I]], align 1, !dbg [[DBG157]] 7851 // CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG137]], !llvm.loop [[LOOP158:![0-9]+]] 7852 // CHECK9: for.end13: 7853 // CHECK9-NEXT: ret void, !dbg [[DBG159:![0-9]+]] 7854 // 7855 // 7856 // CHECK9-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 7857 // CHECK9-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG160:![0-9]+]] { 7858 // CHECK9-NEXT: entry: 7859 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7860 // CHECK9-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7861 // CHECK9-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7862 // CHECK9-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7863 // CHECK9-NEXT: [[X:%.*]] = alloca i32, align 4 7864 // CHECK9-NEXT: [[I:%.*]] = alloca i8, align 1 7865 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7866 // CHECK9-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7867 // CHECK9-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7868 // CHECK9-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7869 // CHECK9-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG161:![0-9]+]] 7870 // CHECK9-NEXT: store i8 48, i8* [[I]], align 1, !dbg [[DBG162:![0-9]+]] 7871 // CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG163:![0-9]+]] 7872 // CHECK9: for.cond: 7873 // CHECK9-NEXT: [[TMP0:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG164:![0-9]+]] 7874 // CHECK9-NEXT: [[CONV:%.*]] = zext i8 [[TMP0]] to i32, !dbg [[DBG164]] 7875 // CHECK9-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV]], 57, !dbg [[DBG165:![0-9]+]] 7876 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END13:%.*]], !dbg [[DBG166:![0-9]+]] 7877 // CHECK9: for.body: 7878 // CHECK9-NEXT: store i32 -10, i32* [[X]], align 4, !dbg [[DBG167:![0-9]+]] 7879 // CHECK9-NEXT: br label [[FOR_COND1:%.*]], !dbg [[DBG168:![0-9]+]] 7880 // CHECK9: for.cond1: 7881 // CHECK9-NEXT: [[TMP1:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG169:![0-9]+]] 7882 // CHECK9-NEXT: [[CMP2:%.*]] = icmp slt i32 [[TMP1]], 10, !dbg [[DBG170:![0-9]+]] 7883 // CHECK9-NEXT: br i1 [[CMP2]], label [[FOR_BODY3:%.*]], label [[FOR_END:%.*]], !dbg [[DBG171:![0-9]+]] 7884 // CHECK9: for.body3: 7885 // CHECK9-NEXT: [[TMP2:%.*]] = load float*, float** [[B_ADDR]], align 8, !dbg [[DBG172:![0-9]+]] 7886 // CHECK9-NEXT: [[TMP3:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG173:![0-9]+]] 7887 // CHECK9-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP3]] to i64, !dbg [[DBG172]] 7888 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP2]], i64 [[IDXPROM]], !dbg [[DBG172]] 7889 // CHECK9-NEXT: [[TMP4:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG172]] 7890 // CHECK9-NEXT: [[TMP5:%.*]] = load float*, float** [[C_ADDR]], align 8, !dbg [[DBG174:![0-9]+]] 7891 // CHECK9-NEXT: [[TMP6:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG175:![0-9]+]] 7892 // CHECK9-NEXT: [[IDXPROM4:%.*]] = zext i8 [[TMP6]] to i64, !dbg [[DBG174]] 7893 // CHECK9-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[TMP5]], i64 [[IDXPROM4]], !dbg [[DBG174]] 7894 // CHECK9-NEXT: [[TMP7:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !dbg [[DBG174]] 7895 // CHECK9-NEXT: [[MUL:%.*]] = fmul float [[TMP4]], [[TMP7]], !dbg [[DBG176:![0-9]+]] 7896 // CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[D_ADDR]], align 8, !dbg [[DBG177:![0-9]+]] 7897 // CHECK9-NEXT: [[TMP9:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG178:![0-9]+]] 7898 // CHECK9-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP9]] to i64, !dbg [[DBG177]] 7899 // CHECK9-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM6]], !dbg [[DBG177]] 7900 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG177]] 7901 // CHECK9-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP10]], !dbg [[DBG179:![0-9]+]] 7902 // CHECK9-NEXT: [[TMP11:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG180:![0-9]+]] 7903 // CHECK9-NEXT: [[TMP12:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG181:![0-9]+]] 7904 // CHECK9-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP12]] to i64, !dbg [[DBG180]] 7905 // CHECK9-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP11]], i64 [[IDXPROM9]], !dbg [[DBG180]] 7906 // CHECK9-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !dbg [[DBG182:![0-9]+]] 7907 // CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG183:![0-9]+]] 7908 // CHECK9: for.inc: 7909 // CHECK9-NEXT: [[TMP13:%.*]] = load i32, i32* [[X]], align 4, !dbg [[DBG184:![0-9]+]] 7910 // CHECK9-NEXT: [[INC:%.*]] = add nsw i32 [[TMP13]], 1, !dbg [[DBG184]] 7911 // CHECK9-NEXT: store i32 [[INC]], i32* [[X]], align 4, !dbg [[DBG184]] 7912 // CHECK9-NEXT: br label [[FOR_COND1]], !dbg [[DBG171]], !llvm.loop [[LOOP185:![0-9]+]] 7913 // CHECK9: for.end: 7914 // CHECK9-NEXT: br label [[FOR_INC11:%.*]], !dbg [[DBG183]] 7915 // CHECK9: for.inc11: 7916 // CHECK9-NEXT: [[TMP14:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG186:![0-9]+]] 7917 // CHECK9-NEXT: [[INC12:%.*]] = add i8 [[TMP14]], 1, !dbg [[DBG186]] 7918 // CHECK9-NEXT: store i8 [[INC12]], i8* [[I]], align 1, !dbg [[DBG186]] 7919 // CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG166]], !llvm.loop [[LOOP187:![0-9]+]] 7920 // CHECK9: for.end13: 7921 // CHECK9-NEXT: ret void, !dbg [[DBG188:![0-9]+]] 7922 // 7923 // 7924 // CHECK9-LABEL: define {{[^@]+}}@_Z3foov 7925 // CHECK9-SAME: () #[[ATTR1:[0-9]+]] !dbg [[DBG189:![0-9]+]] { 7926 // CHECK9-NEXT: entry: 7927 // CHECK9-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG190:![0-9]+]] 7928 // CHECK9-NEXT: ret i32 0, !dbg [[DBG191:![0-9]+]] 7929 // 7930 // 7931 // CHECK9-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 7932 // CHECK9-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG192:![0-9]+]] { 7933 // CHECK9-NEXT: entry: 7934 // CHECK9-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7935 // CHECK9-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7936 // CHECK9-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7937 // CHECK9-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7938 // CHECK9-NEXT: [[SAVED_STACK1:%.*]] = alloca i8*, align 8 7939 // CHECK9-NEXT: [[__VLA_EXPR1:%.*]] = alloca i64, align 8 7940 // CHECK9-NEXT: [[I:%.*]] = alloca i32, align 4 7941 // CHECK9-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7942 // CHECK9-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7943 // CHECK9-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG193:![0-9]+]] 7944 // CHECK9-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG194:![0-9]+]] 7945 // CHECK9-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG194]] 7946 // CHECK9-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG194]] 7947 // CHECK9-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG194]] 7948 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG194]] 7949 // CHECK9-NEXT: [[TMP3:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG195:![0-9]+]] 7950 // CHECK9-NEXT: store i8* [[TMP3]], i8** [[SAVED_STACK1]], align 8, !dbg [[DBG195]] 7951 // CHECK9-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG195]] 7952 // CHECK9-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR1]], align 8, !dbg [[DBG195]] 7953 // CHECK9-NEXT: store i32 131071, i32* [[I]], align 4, !dbg [[DBG196:![0-9]+]] 7954 // CHECK9-NEXT: br label [[FOR_COND:%.*]], !dbg [[DBG197:![0-9]+]] 7955 // CHECK9: for.cond: 7956 // CHECK9-NEXT: [[TMP4:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG198:![0-9]+]] 7957 // CHECK9-NEXT: [[CMP:%.*]] = icmp ule i32 [[TMP4]], 2147483647, !dbg [[DBG199:![0-9]+]] 7958 // CHECK9-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]], !dbg [[DBG200:![0-9]+]] 7959 // CHECK9: for.body: 7960 // CHECK9-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 7961 // CHECK9-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG201:![0-9]+]] 7962 // CHECK9: invoke.cont: 7963 // CHECK9-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG201]] 7964 // CHECK9-NEXT: [[TMP5:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG202:![0-9]+]] 7965 // CHECK9-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP5]] to i64, !dbg [[DBG203:![0-9]+]] 7966 // CHECK9-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 [[IDXPROM]], !dbg [[DBG203]] 7967 // CHECK9-NEXT: [[TMP6:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG203]] 7968 // CHECK9-NEXT: [[ADD:%.*]] = fadd float [[CONV]], [[TMP6]], !dbg [[DBG204:![0-9]+]] 7969 // CHECK9-NEXT: [[TMP7:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG205:![0-9]+]] 7970 // CHECK9-NEXT: [[CONV3:%.*]] = sitofp i32 [[TMP7]] to float, !dbg [[DBG205]] 7971 // CHECK9-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]], !dbg [[DBG206:![0-9]+]] 7972 // CHECK9-NEXT: [[TMP8:%.*]] = load float*, float** [[A_ADDR]], align 8, !dbg [[DBG207:![0-9]+]] 7973 // CHECK9-NEXT: [[TMP9:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG208:![0-9]+]] 7974 // CHECK9-NEXT: [[IDXPROM5:%.*]] = zext i32 [[TMP9]] to i64, !dbg [[DBG207]] 7975 // CHECK9-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP8]], i64 [[IDXPROM5]], !dbg [[DBG207]] 7976 // CHECK9-NEXT: [[TMP10:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG209:![0-9]+]] 7977 // CHECK9-NEXT: [[ADD7:%.*]] = fadd float [[TMP10]], [[ADD4]], !dbg [[DBG209]] 7978 // CHECK9-NEXT: store float [[ADD7]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG209]] 7979 // CHECK9-NEXT: br label [[FOR_INC:%.*]], !dbg [[DBG207]] 7980 // CHECK9: for.inc: 7981 // CHECK9-NEXT: [[TMP11:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG210:![0-9]+]] 7982 // CHECK9-NEXT: [[ADD8:%.*]] = add i32 [[TMP11]], 127, !dbg [[DBG210]] 7983 // CHECK9-NEXT: store i32 [[ADD8]], i32* [[I]], align 4, !dbg [[DBG210]] 7984 // CHECK9-NEXT: br label [[FOR_COND]], !dbg [[DBG200]], !llvm.loop [[LOOP211:![0-9]+]] 7985 // CHECK9: for.end: 7986 // CHECK9-NEXT: [[TMP12:%.*]] = load i8*, i8** [[SAVED_STACK1]], align 8, !dbg [[DBG205]] 7987 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP12]]), !dbg [[DBG205]] 7988 // CHECK9-NEXT: [[TMP13:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG212:![0-9]+]] 7989 // CHECK9-NEXT: call void @llvm.stackrestore(i8* [[TMP13]]), !dbg [[DBG212]] 7990 // CHECK9-NEXT: ret void, !dbg [[DBG212]] 7991 // CHECK9: terminate.lpad: 7992 // CHECK9-NEXT: [[TMP14:%.*]] = landingpad { i8*, i32 } 7993 // CHECK9-NEXT: catch i8* null, !dbg [[DBG201]] 7994 // CHECK9-NEXT: [[TMP15:%.*]] = extractvalue { i8*, i32 } [[TMP14]], 0, !dbg [[DBG201]] 7995 // CHECK9-NEXT: call void @__clang_call_terminate(i8* [[TMP15]]) #[[ATTR5:[0-9]+]], !dbg [[DBG201]] 7996 // CHECK9-NEXT: unreachable, !dbg [[DBG201]] 7997 // 7998 // 7999 // CHECK9-LABEL: define {{[^@]+}}@__clang_call_terminate 8000 // CHECK9-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] { 8001 // CHECK9-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR6:[0-9]+]] 8002 // CHECK9-NEXT: call void @_ZSt9terminatev() #[[ATTR5]] 8003 // CHECK9-NEXT: unreachable 8004 // 8005 // 8006 // CHECK10-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 8007 // CHECK10-SAME: () local_unnamed_addr #[[ATTR0:[0-9]+]] { 8008 // CHECK10-NEXT: entry: 8009 // CHECK10-NEXT: ret void 8010 // 8011 // 8012 // CHECK10-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 8013 // CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1:[0-9]+]] { 8014 // CHECK10-NEXT: entry: 8015 // CHECK10-NEXT: br label [[FOR_BODY:%.*]] 8016 // CHECK10: for.cond.cleanup: 8017 // CHECK10-NEXT: ret void 8018 // CHECK10: for.body: 8019 // CHECK10-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 33, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] 8020 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV]] 8021 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2:![0-9]+]] 8022 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV]] 8023 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA2]] 8024 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] 8025 // CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV]] 8026 // CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA2]] 8027 // CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP2]] 8028 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV]] 8029 // CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !tbaa [[TBAA2]] 8030 // CHECK10-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 7 8031 // CHECK10-NEXT: [[CMP:%.*]] = icmp ult i64 [[INDVARS_IV]], 31999993 8032 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP6:![0-9]+]] 8033 // 8034 // 8035 // CHECK10-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 8036 // CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { 8037 // CHECK10-NEXT: entry: 8038 // CHECK10-NEXT: br label [[FOR_BODY:%.*]] 8039 // CHECK10: for.cond.cleanup: 8040 // CHECK10-NEXT: ret void 8041 // CHECK10: for.body: 8042 // CHECK10-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 32000000, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] 8043 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV]] 8044 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] 8045 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV]] 8046 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA2]] 8047 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] 8048 // CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV]] 8049 // CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA2]] 8050 // CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP2]] 8051 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV]] 8052 // CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7]], align 4, !tbaa [[TBAA2]] 8053 // CHECK10-NEXT: [[INDVARS_IV_NEXT]] = add nsw i64 [[INDVARS_IV]], -7 8054 // CHECK10-NEXT: [[CMP:%.*]] = icmp ugt i64 [[INDVARS_IV]], 40 8055 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP9:![0-9]+]] 8056 // 8057 // 8058 // CHECK10-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 8059 // CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { 8060 // CHECK10-NEXT: entry: 8061 // CHECK10-NEXT: [[ARRAYIDX_0:%.*]] = getelementptr inbounds float, float* [[B]], i64 131071 8062 // CHECK10-NEXT: [[ARRAYIDX2_0:%.*]] = getelementptr inbounds float, float* [[C]], i64 131071 8063 // CHECK10-NEXT: [[ARRAYIDX4_0:%.*]] = getelementptr inbounds float, float* [[D]], i64 131071 8064 // CHECK10-NEXT: [[ARRAYIDX7_0:%.*]] = getelementptr inbounds float, float* [[A]], i64 131071 8065 // CHECK10-NEXT: [[INDVARS_IV_NEXT_0:%.*]] = add nuw nsw i64 131071, 127 8066 // CHECK10-NEXT: br label [[FOR_BODY:%.*]] 8067 // CHECK10: for.cond.cleanup: 8068 // CHECK10-NEXT: ret void 8069 // CHECK10: for.body: 8070 // CHECK10-NEXT: [[INDVARS_IV_NEXT_PHI:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_0]], [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE:%.*]] ] 8071 // CHECK10-NEXT: [[ARRAYIDX7_PHI:%.*]] = phi float* [ [[ARRAYIDX7_0]], [[ENTRY]] ], [ [[ARRAYIDX7_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] 8072 // CHECK10-NEXT: [[ARRAYIDX4_PHI:%.*]] = phi float* [ [[ARRAYIDX4_0]], [[ENTRY]] ], [ [[ARRAYIDX4_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] 8073 // CHECK10-NEXT: [[ARRAYIDX2_PHI:%.*]] = phi float* [ [[ARRAYIDX2_0]], [[ENTRY]] ], [ [[ARRAYIDX2_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] 8074 // CHECK10-NEXT: [[ARRAYIDX_PHI:%.*]] = phi float* [ [[ARRAYIDX_0]], [[ENTRY]] ], [ [[ARRAYIDX_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] 8075 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX_PHI]], align 4, !tbaa [[TBAA2]] 8076 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX2_PHI]], align 4, !tbaa [[TBAA2]] 8077 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] 8078 // CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX4_PHI]], align 4, !tbaa [[TBAA2]] 8079 // CHECK10-NEXT: [[MUL5:%.*]] = fmul float [[MUL]], [[TMP2]] 8080 // CHECK10-NEXT: store float [[MUL5]], float* [[ARRAYIDX7_PHI]], align 4, !tbaa [[TBAA2]] 8081 // CHECK10-NEXT: [[TMP3:%.*]] = trunc i64 [[INDVARS_IV_NEXT_PHI]] to i32 8082 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], -1 8083 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP10:![0-9]+]] 8084 // CHECK10: for.body.for.body_crit_edge: 8085 // CHECK10-NEXT: [[ARRAYIDX_1]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV_NEXT_PHI]] 8086 // CHECK10-NEXT: [[ARRAYIDX2_1]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV_NEXT_PHI]] 8087 // CHECK10-NEXT: [[ARRAYIDX4_1]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV_NEXT_PHI]] 8088 // CHECK10-NEXT: [[ARRAYIDX7_1]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV_NEXT_PHI]] 8089 // CHECK10-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV_NEXT_PHI]], 127 8090 // CHECK10-NEXT: br label [[FOR_BODY]] 8091 // 8092 // 8093 // CHECK10-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 8094 // CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { 8095 // CHECK10-NEXT: entry: 8096 // CHECK10-NEXT: br label [[FOR_BODY:%.*]] 8097 // CHECK10: for.cond.cleanup: 8098 // CHECK10-NEXT: ret void 8099 // CHECK10: for.body: 8100 // CHECK10-NEXT: [[I_011:%.*]] = phi i64 [ 131071, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[FOR_BODY]] ] 8101 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[I_011]] 8102 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] 8103 // CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[I_011]] 8104 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] 8105 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] 8106 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[I_011]] 8107 // CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA2]] 8108 // CHECK10-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP2]] 8109 // CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[I_011]] 8110 // CHECK10-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA2]] 8111 // CHECK10-NEXT: [[ADD]] = add nuw nsw i64 [[I_011]], 127 8112 // CHECK10-NEXT: [[CMP:%.*]] = icmp ult i64 [[I_011]], 2147483520 8113 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP11:![0-9]+]] 8114 // 8115 // 8116 // CHECK10-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 8117 // CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { 8118 // CHECK10-NEXT: entry: 8119 // CHECK10-NEXT: br label [[FOR_BODY:%.*]] 8120 // CHECK10: for.cond.cleanup: 8121 // CHECK10-NEXT: ret void 8122 // CHECK10: for.body: 8123 // CHECK10-NEXT: [[I_011:%.*]] = phi i64 [ 131071, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[FOR_BODY]] ] 8124 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[I_011]] 8125 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] 8126 // CHECK10-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[I_011]] 8127 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX1]], align 4, !tbaa [[TBAA2]] 8128 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] 8129 // CHECK10-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[I_011]] 8130 // CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !tbaa [[TBAA2]] 8131 // CHECK10-NEXT: [[MUL3:%.*]] = fmul float [[MUL]], [[TMP2]] 8132 // CHECK10-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[I_011]] 8133 // CHECK10-NEXT: store float [[MUL3]], float* [[ARRAYIDX4]], align 4, !tbaa [[TBAA2]] 8134 // CHECK10-NEXT: [[ADD]] = add nuw nsw i64 [[I_011]], 127 8135 // CHECK10-NEXT: [[CMP:%.*]] = icmp ult i64 [[I_011]], 2147483520 8136 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP12:![0-9]+]] 8137 // 8138 // 8139 // CHECK10-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 8140 // CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { 8141 // CHECK10-NEXT: entry: 8142 // CHECK10-NEXT: br label [[FOR_COND2_PREHEADER:%.*]] 8143 // CHECK10: for.cond2.preheader: 8144 // CHECK10-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC12:%.*]] ] 8145 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV]] 8146 // CHECK10-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV]] 8147 // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV]] 8148 // CHECK10-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV]] 8149 // CHECK10-NEXT: [[DEC_0:%.*]] = add nsw i32 11, -1 8150 // CHECK10-NEXT: br label [[FOR_BODY4:%.*]] 8151 // CHECK10: for.cond.cleanup: 8152 // CHECK10-NEXT: ret void 8153 // CHECK10: for.body4: 8154 // CHECK10-NEXT: [[DEC_PHI:%.*]] = phi i32 [ [[DEC_0]], [[FOR_COND2_PREHEADER]] ], [ [[DEC_1:%.*]], [[FOR_BODY4_FOR_BODY4_CRIT_EDGE:%.*]] ] 8155 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] 8156 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !tbaa [[TBAA2]] 8157 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] 8158 // CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX8]], align 4, !tbaa [[TBAA2]] 8159 // CHECK10-NEXT: [[MUL9:%.*]] = fmul float [[MUL]], [[TMP2]] 8160 // CHECK10-NEXT: store float [[MUL9]], float* [[ARRAYIDX11]], align 4, !tbaa [[TBAA2]] 8161 // CHECK10-NEXT: [[CMP3_NOT:%.*]] = icmp eq i32 [[DEC_PHI]], 0 8162 // CHECK10-NEXT: br i1 [[CMP3_NOT]], label [[FOR_INC12]], label [[FOR_BODY4_FOR_BODY4_CRIT_EDGE]], !llvm.loop [[LOOP13:![0-9]+]] 8163 // CHECK10: for.body4.for.body4_crit_edge: 8164 // CHECK10-NEXT: [[DEC_1]] = add nsw i32 [[DEC_PHI]], -1 8165 // CHECK10-NEXT: br label [[FOR_BODY4]] 8166 // CHECK10: for.inc12: 8167 // CHECK10-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 8168 // CHECK10-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 58 8169 // CHECK10-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND2_PREHEADER]], !llvm.loop [[LOOP14:![0-9]+]] 8170 // 8171 // 8172 // CHECK10-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 8173 // CHECK10-SAME: (float* nocapture [[A:%.*]], float* nocapture readonly [[B:%.*]], float* nocapture readonly [[C:%.*]], float* nocapture readonly [[D:%.*]]) local_unnamed_addr #[[ATTR1]] { 8174 // CHECK10-NEXT: entry: 8175 // CHECK10-NEXT: br label [[FOR_COND1_PREHEADER:%.*]] 8176 // CHECK10: for.cond1.preheader: 8177 // CHECK10-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ 48, [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_INC11:%.*]] ] 8178 // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[B]], i64 [[INDVARS_IV]] 8179 // CHECK10-NEXT: [[ARRAYIDX5:%.*]] = getelementptr inbounds float, float* [[C]], i64 [[INDVARS_IV]] 8180 // CHECK10-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[D]], i64 [[INDVARS_IV]] 8181 // CHECK10-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV]] 8182 // CHECK10-NEXT: [[INC_0:%.*]] = add nsw i32 -10, 1 8183 // CHECK10-NEXT: br label [[FOR_BODY3:%.*]] 8184 // CHECK10: for.cond.cleanup: 8185 // CHECK10-NEXT: ret void 8186 // CHECK10: for.body3: 8187 // CHECK10-NEXT: [[INC_PHI:%.*]] = phi i32 [ [[INC_0]], [[FOR_COND1_PREHEADER]] ], [ [[INC_1:%.*]], [[FOR_BODY3_FOR_BODY3_CRIT_EDGE:%.*]] ] 8188 // CHECK10-NEXT: [[TMP0:%.*]] = load float, float* [[ARRAYIDX]], align 4, !tbaa [[TBAA2]] 8189 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX5]], align 4, !tbaa [[TBAA2]] 8190 // CHECK10-NEXT: [[MUL:%.*]] = fmul float [[TMP0]], [[TMP1]] 8191 // CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !tbaa [[TBAA2]] 8192 // CHECK10-NEXT: [[MUL8:%.*]] = fmul float [[MUL]], [[TMP2]] 8193 // CHECK10-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !tbaa [[TBAA2]] 8194 // CHECK10-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i32 [[INC_PHI]], 10 8195 // CHECK10-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_INC11]], label [[FOR_BODY3_FOR_BODY3_CRIT_EDGE]], !llvm.loop [[LOOP15:![0-9]+]] 8196 // CHECK10: for.body3.for.body3_crit_edge: 8197 // CHECK10-NEXT: [[INC_1]] = add nsw i32 [[INC_PHI]], 1 8198 // CHECK10-NEXT: br label [[FOR_BODY3]] 8199 // CHECK10: for.inc11: 8200 // CHECK10-NEXT: [[INDVARS_IV_NEXT]] = add nuw nsw i64 [[INDVARS_IV]], 1 8201 // CHECK10-NEXT: [[EXITCOND23_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 58 8202 // CHECK10-NEXT: br i1 [[EXITCOND23_NOT]], label [[FOR_COND_CLEANUP:%.*]], label [[FOR_COND1_PREHEADER]], !llvm.loop [[LOOP16:![0-9]+]] 8203 // 8204 // 8205 // CHECK10-LABEL: define {{[^@]+}}@_Z3foov 8206 // CHECK10-SAME: () local_unnamed_addr #[[ATTR2:[0-9]+]] { 8207 // CHECK10-NEXT: entry: 8208 // CHECK10-NEXT: call void @_Z8mayThrowv() #[[ATTR4:[0-9]+]] 8209 // CHECK10-NEXT: ret i32 0 8210 // 8211 // 8212 // CHECK10-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 8213 // CHECK10-SAME: (float* nocapture [[A:%.*]], i32 [[N:%.*]]) local_unnamed_addr #[[ATTR2]] { 8214 // CHECK10-NEXT: entry: 8215 // CHECK10-NEXT: [[TMP0:%.*]] = zext i32 [[N]] to i64 8216 // CHECK10-NEXT: [[VLA2:%.*]] = alloca float, i64 [[TMP0]], align 16 8217 // CHECK10-NEXT: [[CONV3:%.*]] = sitofp i32 [[N]] to float 8218 // CHECK10-NEXT: [[ARRAYIDX_0:%.*]] = getelementptr inbounds float, float* [[VLA2]], i64 131071 8219 // CHECK10-NEXT: [[ARRAYIDX6_0:%.*]] = getelementptr inbounds float, float* [[A]], i64 131071 8220 // CHECK10-NEXT: [[INDVARS_IV_NEXT_0:%.*]] = add nuw nsw i64 131071, 127 8221 // CHECK10-NEXT: br label [[FOR_BODY:%.*]] 8222 // CHECK10: for.cond.cleanup: 8223 // CHECK10-NEXT: ret void 8224 // CHECK10: for.body: 8225 // CHECK10-NEXT: [[INDVARS_IV_NEXT_PHI:%.*]] = phi i64 [ [[INDVARS_IV_NEXT_0]], [[ENTRY:%.*]] ], [ [[INDVARS_IV_NEXT_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE:%.*]] ] 8226 // CHECK10-NEXT: [[ARRAYIDX6_PHI:%.*]] = phi float* [ [[ARRAYIDX6_0]], [[ENTRY]] ], [ [[ARRAYIDX6_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] 8227 // CHECK10-NEXT: [[ARRAYIDX_PHI:%.*]] = phi float* [ [[ARRAYIDX_0]], [[ENTRY]] ], [ [[ARRAYIDX_1:%.*]], [[FOR_BODY_FOR_BODY_CRIT_EDGE]] ] 8228 // CHECK10-NEXT: call void @_Z8mayThrowv() #[[ATTR4]] 8229 // CHECK10-NEXT: [[TMP1:%.*]] = load float, float* [[ARRAYIDX_PHI]], align 4, !tbaa [[TBAA2]] 8230 // CHECK10-NEXT: [[ADD:%.*]] = fadd float [[TMP1]], 0.000000e+00 8231 // CHECK10-NEXT: [[ADD4:%.*]] = fadd float [[ADD]], [[CONV3]] 8232 // CHECK10-NEXT: [[TMP2:%.*]] = load float, float* [[ARRAYIDX6_PHI]], align 4, !tbaa [[TBAA2]] 8233 // CHECK10-NEXT: [[ADD7:%.*]] = fadd float [[TMP2]], [[ADD4]] 8234 // CHECK10-NEXT: store float [[ADD7]], float* [[ARRAYIDX6_PHI]], align 4, !tbaa [[TBAA2]] 8235 // CHECK10-NEXT: [[TMP3:%.*]] = trunc i64 [[INDVARS_IV_NEXT_PHI]] to i32 8236 // CHECK10-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP3]], -1 8237 // CHECK10-NEXT: br i1 [[CMP]], label [[FOR_BODY_FOR_BODY_CRIT_EDGE]], label [[FOR_COND_CLEANUP:%.*]], !llvm.loop [[LOOP17:![0-9]+]] 8238 // CHECK10: for.body.for.body_crit_edge: 8239 // CHECK10-NEXT: [[ARRAYIDX_1]] = getelementptr inbounds float, float* [[VLA2]], i64 [[INDVARS_IV_NEXT_PHI]] 8240 // CHECK10-NEXT: [[ARRAYIDX6_1]] = getelementptr inbounds float, float* [[A]], i64 [[INDVARS_IV_NEXT_PHI]] 8241 // CHECK10-NEXT: [[INDVARS_IV_NEXT_1]] = add nuw nsw i64 [[INDVARS_IV_NEXT_PHI]], 127 8242 // CHECK10-NEXT: br label [[FOR_BODY]] 8243 // 8244 // 8245 // CHECK11-LABEL: define {{[^@]+}}@_Z9incrementv 8246 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 8247 // CHECK11-NEXT: entry: 8248 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8249 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8250 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8251 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8252 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8253 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8254 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 8255 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 8256 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8257 // CHECK11-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 8258 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8259 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8260 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8261 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8262 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 8263 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8264 // CHECK11: cond.true: 8265 // CHECK11-NEXT: br label [[COND_END:%.*]] 8266 // CHECK11: cond.false: 8267 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8268 // CHECK11-NEXT: br label [[COND_END]] 8269 // CHECK11: cond.end: 8270 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 8271 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8272 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8273 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 8274 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8275 // CHECK11: omp.inner.for.cond: 8276 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8277 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8278 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 8279 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8280 // CHECK11: omp.inner.for.body: 8281 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8282 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 8283 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 8284 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8285 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8286 // CHECK11: omp.body.continue: 8287 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8288 // CHECK11: omp.inner.for.inc: 8289 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8290 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1 8291 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 8292 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8293 // CHECK11: omp.inner.for.end: 8294 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8295 // CHECK11: omp.loop.exit: 8296 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 8297 // CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) 8298 // CHECK11-NEXT: ret i32 0 8299 // 8300 // 8301 // CHECK11-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv 8302 // CHECK11-SAME: () #[[ATTR0]] { 8303 // CHECK11-NEXT: entry: 8304 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8305 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 8306 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8307 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8308 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8309 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8310 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 8311 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 8312 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8313 // CHECK11-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 8314 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8315 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8316 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8317 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8318 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 8319 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8320 // CHECK11: cond.true: 8321 // CHECK11-NEXT: br label [[COND_END:%.*]] 8322 // CHECK11: cond.false: 8323 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8324 // CHECK11-NEXT: br label [[COND_END]] 8325 // CHECK11: cond.end: 8326 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 8327 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8328 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8329 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 8330 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8331 // CHECK11: omp.inner.for.cond: 8332 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8333 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8334 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 8335 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8336 // CHECK11: omp.inner.for.body: 8337 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8338 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 8339 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]] 8340 // CHECK11-NEXT: store i32 [[SUB]], i32* [[J]], align 4 8341 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8342 // CHECK11: omp.body.continue: 8343 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8344 // CHECK11: omp.inner.for.inc: 8345 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8346 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 8347 // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 8348 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8349 // CHECK11: omp.inner.for.end: 8350 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8351 // CHECK11: omp.loop.exit: 8352 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 8353 // CHECK11-NEXT: ret i32 0 8354 // 8355 // 8356 // CHECK11-LABEL: define {{[^@]+}}@_Z16range_for_singlev 8357 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 8358 // CHECK11-NEXT: entry: 8359 // CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 8360 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 8361 // CHECK11-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 8362 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) 8363 // CHECK11-NEXT: ret void 8364 // 8365 // 8366 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 8367 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { 8368 // CHECK11-NEXT: entry: 8369 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8370 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8371 // CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 8372 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8373 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 8374 // CHECK11-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 8375 // CHECK11-NEXT: [[__END1:%.*]] = alloca i32*, align 8 8376 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 8377 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32*, align 8 8378 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 8379 // CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 8380 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8381 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8382 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8383 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8384 // CHECK11-NEXT: [[__BEGIN15:%.*]] = alloca i32*, align 8 8385 // CHECK11-NEXT: [[A:%.*]] = alloca i32*, align 8 8386 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8387 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8388 // CHECK11-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 8389 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 8390 // CHECK11-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 8391 // CHECK11-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8392 // CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 8393 // CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 8394 // CHECK11-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 8395 // CHECK11-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8396 // CHECK11-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 8397 // CHECK11-NEXT: store i32* [[ARRAYDECAY1]], i32** [[DOTCAPTURE_EXPR_]], align 8 8398 // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__END1]], align 8 8399 // CHECK11-NEXT: store i32* [[TMP3]], i32** [[DOTCAPTURE_EXPR_2]], align 8 8400 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 8401 // CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8402 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP4]] to i64 8403 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP5]] to i64 8404 // CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 8405 // CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 8406 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 8407 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 8408 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 8409 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1 8410 // CHECK11-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_3]], align 8 8411 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8412 // CHECK11-NEXT: store i32* [[TMP6]], i32** [[__BEGIN1]], align 8 8413 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8414 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 8415 // CHECK11-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP7]], [[TMP8]] 8416 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 8417 // CHECK11: omp.precond.then: 8418 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8419 // CHECK11-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 8420 // CHECK11-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 8421 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8422 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8423 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8424 // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 8425 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8426 // CHECK11-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8427 // CHECK11-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 8428 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 8429 // CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8430 // CHECK11: cond.true: 8431 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 8432 // CHECK11-NEXT: br label [[COND_END:%.*]] 8433 // CHECK11: cond.false: 8434 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8435 // CHECK11-NEXT: br label [[COND_END]] 8436 // CHECK11: cond.end: 8437 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 8438 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8439 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8440 // CHECK11-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 8441 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8442 // CHECK11: omp.inner.for.cond: 8443 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8444 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8445 // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 8446 // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8447 // CHECK11: omp.inner.for.body: 8448 // CHECK11-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8449 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8450 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP20]], 1 8451 // CHECK11-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[MUL]] 8452 // CHECK11-NEXT: store i32* [[ADD_PTR8]], i32** [[__BEGIN15]], align 8 8453 // CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[__BEGIN15]], align 8 8454 // CHECK11-NEXT: store i32* [[TMP21]], i32** [[A]], align 8 8455 // CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[A]], align 8 8456 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8457 // CHECK11: omp.body.continue: 8458 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8459 // CHECK11: omp.inner.for.inc: 8460 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8461 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP23]], 1 8462 // CHECK11-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 8463 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8464 // CHECK11: omp.inner.for.end: 8465 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8466 // CHECK11: omp.loop.exit: 8467 // CHECK11-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8468 // CHECK11-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 8469 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) 8470 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 8471 // CHECK11: omp.precond.end: 8472 // CHECK11-NEXT: ret void 8473 // 8474 // 8475 // CHECK11-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv 8476 // CHECK11-SAME: () #[[ATTR3]] { 8477 // CHECK11-NEXT: entry: 8478 // CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 8479 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 8480 // CHECK11-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 8481 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) 8482 // CHECK11-NEXT: ret void 8483 // 8484 // 8485 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 8486 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { 8487 // CHECK11-NEXT: entry: 8488 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8489 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8490 // CHECK11-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 8491 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8492 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 8493 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 8494 // CHECK11-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 8495 // CHECK11-NEXT: [[__END1:%.*]] = alloca i32*, align 8 8496 // CHECK11-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 8497 // CHECK11-NEXT: [[__END2:%.*]] = alloca i32*, align 8 8498 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 8499 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32*, align 8 8500 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32*, align 8 8501 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32*, align 8 8502 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8 8503 // CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 8504 // CHECK11-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 8505 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8506 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8507 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8508 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8509 // CHECK11-NEXT: [[__BEGIN119:%.*]] = alloca i32*, align 8 8510 // CHECK11-NEXT: [[__BEGIN220:%.*]] = alloca i32*, align 8 8511 // CHECK11-NEXT: [[A:%.*]] = alloca i32*, align 8 8512 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 8513 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8514 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8515 // CHECK11-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 8516 // CHECK11-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 8517 // CHECK11-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 8518 // CHECK11-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8519 // CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 8520 // CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 8521 // CHECK11-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 8522 // CHECK11-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE2]], align 8 8523 // CHECK11-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 8524 // CHECK11-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 8525 // CHECK11-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY2]], i64 10 8526 // CHECK11-NEXT: store i32* [[ADD_PTR3]], i32** [[__END2]], align 8 8527 // CHECK11-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8528 // CHECK11-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 8529 // CHECK11-NEXT: store i32* [[ARRAYDECAY4]], i32** [[DOTCAPTURE_EXPR_]], align 8 8530 // CHECK11-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 8531 // CHECK11-NEXT: store i32* [[TMP4]], i32** [[DOTCAPTURE_EXPR_5]], align 8 8532 // CHECK11-NEXT: [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 8533 // CHECK11-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP5]], i64 0, i64 0 8534 // CHECK11-NEXT: store i32* [[ARRAYDECAY7]], i32** [[DOTCAPTURE_EXPR_6]], align 8 8535 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[__END2]], align 8 8536 // CHECK11-NEXT: store i32* [[TMP6]], i32** [[DOTCAPTURE_EXPR_8]], align 8 8537 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 8538 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8539 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP7]] to i64 8540 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP8]] to i64 8541 // CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 8542 // CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 8543 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 8544 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 8545 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 8546 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8547 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8548 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint i32* [[TMP9]] to i64 8549 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint i32* [[TMP10]] to i64 8550 // CHECK11-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]] 8551 // CHECK11-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4 8552 // CHECK11-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1 8553 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1 8554 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1 8555 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]] 8556 // CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1 8557 // CHECK11-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_9]], align 8 8558 // CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8559 // CHECK11-NEXT: store i32* [[TMP11]], i32** [[__BEGIN1]], align 8 8560 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8561 // CHECK11-NEXT: store i32* [[TMP12]], i32** [[__BEGIN2]], align 8 8562 // CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8563 // CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 8564 // CHECK11-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP13]], [[TMP14]] 8565 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 8566 // CHECK11: land.lhs.true: 8567 // CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8568 // CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8569 // CHECK11-NEXT: [[CMP18:%.*]] = icmp ult i32* [[TMP15]], [[TMP16]] 8570 // CHECK11-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 8571 // CHECK11: omp.precond.then: 8572 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8573 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 8574 // CHECK11-NEXT: store i64 [[TMP17]], i64* [[DOTOMP_UB]], align 8 8575 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8576 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8577 // CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8578 // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 8579 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8580 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8581 // CHECK11-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 8582 // CHECK11-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]] 8583 // CHECK11-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8584 // CHECK11: cond.true: 8585 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 8586 // CHECK11-NEXT: br label [[COND_END:%.*]] 8587 // CHECK11: cond.false: 8588 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8589 // CHECK11-NEXT: br label [[COND_END]] 8590 // CHECK11: cond.end: 8591 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ] 8592 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8593 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8594 // CHECK11-NEXT: store i64 [[TMP24]], i64* [[DOTOMP_IV]], align 8 8595 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8596 // CHECK11: omp.inner.for.cond: 8597 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8598 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8599 // CHECK11-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] 8600 // CHECK11-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8601 // CHECK11: omp.inner.for.body: 8602 // CHECK11-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8603 // CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8604 // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8605 // CHECK11-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8606 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint i32* [[TMP29]] to i64 8607 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint i32* [[TMP30]] to i64 8608 // CHECK11-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]] 8609 // CHECK11-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4 8610 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1 8611 // CHECK11-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1 8612 // CHECK11-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1 8613 // CHECK11-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]] 8614 // CHECK11-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]] 8615 // CHECK11-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1 8616 // CHECK11-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[MUL32]] 8617 // CHECK11-NEXT: store i32* [[ADD_PTR33]], i32** [[__BEGIN119]], align 8 8618 // CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8619 // CHECK11-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8620 // CHECK11-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8621 // CHECK11-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8622 // CHECK11-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8623 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint i32* [[TMP34]] to i64 8624 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint i32* [[TMP35]] to i64 8625 // CHECK11-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]] 8626 // CHECK11-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4 8627 // CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1 8628 // CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1 8629 // CHECK11-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1 8630 // CHECK11-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]] 8631 // CHECK11-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]] 8632 // CHECK11-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8633 // CHECK11-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8634 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint i32* [[TMP36]] to i64 8635 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint i32* [[TMP37]] to i64 8636 // CHECK11-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]] 8637 // CHECK11-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4 8638 // CHECK11-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1 8639 // CHECK11-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1 8640 // CHECK11-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1 8641 // CHECK11-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]] 8642 // CHECK11-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]] 8643 // CHECK11-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]] 8644 // CHECK11-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1 8645 // CHECK11-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, i32* [[TMP31]], i64 [[MUL53]] 8646 // CHECK11-NEXT: store i32* [[ADD_PTR54]], i32** [[__BEGIN220]], align 8 8647 // CHECK11-NEXT: [[TMP38:%.*]] = load i32*, i32** [[__BEGIN119]], align 8 8648 // CHECK11-NEXT: store i32* [[TMP38]], i32** [[A]], align 8 8649 // CHECK11-NEXT: [[TMP39:%.*]] = load i32*, i32** [[__BEGIN220]], align 8 8650 // CHECK11-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP39]], align 4 8651 // CHECK11-NEXT: store i32 [[TMP40]], i32* [[B]], align 4 8652 // CHECK11-NEXT: [[TMP41:%.*]] = load i32, i32* [[B]], align 4 8653 // CHECK11-NEXT: [[TMP42:%.*]] = load i32*, i32** [[A]], align 8 8654 // CHECK11-NEXT: store i32 [[TMP41]], i32* [[TMP42]], align 4 8655 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8656 // CHECK11: omp.body.continue: 8657 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8658 // CHECK11: omp.inner.for.inc: 8659 // CHECK11-NEXT: [[TMP43:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8660 // CHECK11-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP43]], 1 8661 // CHECK11-NEXT: store i64 [[ADD55]], i64* [[DOTOMP_IV]], align 8 8662 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 8663 // CHECK11: omp.inner.for.end: 8664 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8665 // CHECK11: omp.loop.exit: 8666 // CHECK11-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8667 // CHECK11-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 8668 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP45]]) 8669 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 8670 // CHECK11: omp.precond.end: 8671 // CHECK11-NEXT: ret void 8672 // 8673 // 8674 // CHECK12-LABEL: define {{[^@]+}}@_Z9incrementv 8675 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 8676 // CHECK12-NEXT: entry: 8677 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8678 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 8679 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8680 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8681 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8682 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8683 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 8684 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 8685 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8686 // CHECK12-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 8687 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8688 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8689 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8690 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8691 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 8692 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8693 // CHECK12: cond.true: 8694 // CHECK12-NEXT: br label [[COND_END:%.*]] 8695 // CHECK12: cond.false: 8696 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8697 // CHECK12-NEXT: br label [[COND_END]] 8698 // CHECK12: cond.end: 8699 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 8700 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8701 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8702 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 8703 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8704 // CHECK12: omp.inner.for.cond: 8705 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8706 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8707 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 8708 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8709 // CHECK12: omp.inner.for.body: 8710 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8711 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 8712 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 8713 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 8714 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8715 // CHECK12: omp.body.continue: 8716 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8717 // CHECK12: omp.inner.for.inc: 8718 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8719 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1 8720 // CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 8721 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 8722 // CHECK12: omp.inner.for.end: 8723 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8724 // CHECK12: omp.loop.exit: 8725 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 8726 // CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) 8727 // CHECK12-NEXT: ret i32 0 8728 // 8729 // 8730 // CHECK12-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv 8731 // CHECK12-SAME: () #[[ATTR0]] { 8732 // CHECK12-NEXT: entry: 8733 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 8734 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 8735 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 8736 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 8737 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 8738 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8739 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 8740 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 8741 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 8742 // CHECK12-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 8743 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 8744 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8745 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 8746 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8747 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 8748 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8749 // CHECK12: cond.true: 8750 // CHECK12-NEXT: br label [[COND_END:%.*]] 8751 // CHECK12: cond.false: 8752 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8753 // CHECK12-NEXT: br label [[COND_END]] 8754 // CHECK12: cond.end: 8755 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 8756 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 8757 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 8758 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 8759 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8760 // CHECK12: omp.inner.for.cond: 8761 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8762 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 8763 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 8764 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8765 // CHECK12: omp.inner.for.body: 8766 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8767 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 8768 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]] 8769 // CHECK12-NEXT: store i32 [[SUB]], i32* [[J]], align 4 8770 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8771 // CHECK12: omp.body.continue: 8772 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8773 // CHECK12: omp.inner.for.inc: 8774 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 8775 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 8776 // CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 8777 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 8778 // CHECK12: omp.inner.for.end: 8779 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8780 // CHECK12: omp.loop.exit: 8781 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 8782 // CHECK12-NEXT: ret i32 0 8783 // 8784 // 8785 // CHECK12-LABEL: define {{[^@]+}}@_Z16range_for_singlev 8786 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 8787 // CHECK12-NEXT: entry: 8788 // CHECK12-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 8789 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 8790 // CHECK12-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 8791 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) 8792 // CHECK12-NEXT: ret void 8793 // 8794 // 8795 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 8796 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5:[0-9]+]] { 8797 // CHECK12-NEXT: entry: 8798 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8799 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8800 // CHECK12-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 8801 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8802 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 8803 // CHECK12-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 8804 // CHECK12-NEXT: [[__END1:%.*]] = alloca i32*, align 8 8805 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 8806 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32*, align 8 8807 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 8808 // CHECK12-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 8809 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8810 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8811 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8812 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8813 // CHECK12-NEXT: [[__BEGIN15:%.*]] = alloca i32*, align 8 8814 // CHECK12-NEXT: [[A:%.*]] = alloca i32*, align 8 8815 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8816 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8817 // CHECK12-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 8818 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 8819 // CHECK12-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 8820 // CHECK12-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8821 // CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 8822 // CHECK12-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 8823 // CHECK12-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 8824 // CHECK12-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8825 // CHECK12-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 8826 // CHECK12-NEXT: store i32* [[ARRAYDECAY1]], i32** [[DOTCAPTURE_EXPR_]], align 8 8827 // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__END1]], align 8 8828 // CHECK12-NEXT: store i32* [[TMP3]], i32** [[DOTCAPTURE_EXPR_2]], align 8 8829 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 8830 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8831 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP4]] to i64 8832 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP5]] to i64 8833 // CHECK12-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 8834 // CHECK12-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 8835 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 8836 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 8837 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 8838 // CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1 8839 // CHECK12-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_3]], align 8 8840 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8841 // CHECK12-NEXT: store i32* [[TMP6]], i32** [[__BEGIN1]], align 8 8842 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8843 // CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 8844 // CHECK12-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP7]], [[TMP8]] 8845 // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 8846 // CHECK12: omp.precond.then: 8847 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8848 // CHECK12-NEXT: [[TMP9:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 8849 // CHECK12-NEXT: store i64 [[TMP9]], i64* [[DOTOMP_UB]], align 8 8850 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8851 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8852 // CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8853 // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 8854 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP11]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8855 // CHECK12-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8856 // CHECK12-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 8857 // CHECK12-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP12]], [[TMP13]] 8858 // CHECK12-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8859 // CHECK12: cond.true: 8860 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 8861 // CHECK12-NEXT: br label [[COND_END:%.*]] 8862 // CHECK12: cond.false: 8863 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8864 // CHECK12-NEXT: br label [[COND_END]] 8865 // CHECK12: cond.end: 8866 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP14]], [[COND_TRUE]] ], [ [[TMP15]], [[COND_FALSE]] ] 8867 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8868 // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8869 // CHECK12-NEXT: store i64 [[TMP16]], i64* [[DOTOMP_IV]], align 8 8870 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8871 // CHECK12: omp.inner.for.cond: 8872 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8873 // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8874 // CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP17]], [[TMP18]] 8875 // CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8876 // CHECK12: omp.inner.for.body: 8877 // CHECK12-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8878 // CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8879 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP20]], 1 8880 // CHECK12-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, i32* [[TMP19]], i64 [[MUL]] 8881 // CHECK12-NEXT: store i32* [[ADD_PTR8]], i32** [[__BEGIN15]], align 8 8882 // CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[__BEGIN15]], align 8 8883 // CHECK12-NEXT: store i32* [[TMP21]], i32** [[A]], align 8 8884 // CHECK12-NEXT: [[TMP22:%.*]] = load i32*, i32** [[A]], align 8 8885 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8886 // CHECK12: omp.body.continue: 8887 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8888 // CHECK12: omp.inner.for.inc: 8889 // CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8890 // CHECK12-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP23]], 1 8891 // CHECK12-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 8892 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 8893 // CHECK12: omp.inner.for.end: 8894 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8895 // CHECK12: omp.loop.exit: 8896 // CHECK12-NEXT: [[TMP24:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8897 // CHECK12-NEXT: [[TMP25:%.*]] = load i32, i32* [[TMP24]], align 4 8898 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP25]]) 8899 // CHECK12-NEXT: br label [[OMP_PRECOND_END]] 8900 // CHECK12: omp.precond.end: 8901 // CHECK12-NEXT: ret void 8902 // 8903 // 8904 // CHECK12-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv 8905 // CHECK12-SAME: () #[[ATTR3]] { 8906 // CHECK12-NEXT: entry: 8907 // CHECK12-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 8908 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 8909 // CHECK12-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 8910 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), [10 x i32]* [[ARR]]) 8911 // CHECK12-NEXT: ret void 8912 // 8913 // 8914 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 8915 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [10 x i32]* nonnull align 4 dereferenceable(40) [[ARR:%.*]]) #[[ATTR5]] { 8916 // CHECK12-NEXT: entry: 8917 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 8918 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 8919 // CHECK12-NEXT: [[ARR_ADDR:%.*]] = alloca [10 x i32]*, align 8 8920 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 8921 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 8922 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 8923 // CHECK12-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 8924 // CHECK12-NEXT: [[__END1:%.*]] = alloca i32*, align 8 8925 // CHECK12-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 8926 // CHECK12-NEXT: [[__END2:%.*]] = alloca i32*, align 8 8927 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 8928 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32*, align 8 8929 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32*, align 8 8930 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32*, align 8 8931 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8 8932 // CHECK12-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 8933 // CHECK12-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 8934 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8935 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8936 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8937 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8938 // CHECK12-NEXT: [[__BEGIN119:%.*]] = alloca i32*, align 8 8939 // CHECK12-NEXT: [[__BEGIN220:%.*]] = alloca i32*, align 8 8940 // CHECK12-NEXT: [[A:%.*]] = alloca i32*, align 8 8941 // CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 8942 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8943 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8944 // CHECK12-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[ARR_ADDR]], align 8 8945 // CHECK12-NEXT: [[TMP0:%.*]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], align 8 8946 // CHECK12-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE1]], align 8 8947 // CHECK12-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8948 // CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 8949 // CHECK12-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 8950 // CHECK12-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 8951 // CHECK12-NEXT: store [10 x i32]* [[TMP0]], [10 x i32]** [[__RANGE2]], align 8 8952 // CHECK12-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 8953 // CHECK12-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 8954 // CHECK12-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY2]], i64 10 8955 // CHECK12-NEXT: store i32* [[ADD_PTR3]], i32** [[__END2]], align 8 8956 // CHECK12-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8957 // CHECK12-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 8958 // CHECK12-NEXT: store i32* [[ARRAYDECAY4]], i32** [[DOTCAPTURE_EXPR_]], align 8 8959 // CHECK12-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 8960 // CHECK12-NEXT: store i32* [[TMP4]], i32** [[DOTCAPTURE_EXPR_5]], align 8 8961 // CHECK12-NEXT: [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 8962 // CHECK12-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP5]], i64 0, i64 0 8963 // CHECK12-NEXT: store i32* [[ARRAYDECAY7]], i32** [[DOTCAPTURE_EXPR_6]], align 8 8964 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[__END2]], align 8 8965 // CHECK12-NEXT: store i32* [[TMP6]], i32** [[DOTCAPTURE_EXPR_8]], align 8 8966 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 8967 // CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8968 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP7]] to i64 8969 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP8]] to i64 8970 // CHECK12-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 8971 // CHECK12-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 8972 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 8973 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 8974 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 8975 // CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8976 // CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8977 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint i32* [[TMP9]] to i64 8978 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint i32* [[TMP10]] to i64 8979 // CHECK12-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]] 8980 // CHECK12-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4 8981 // CHECK12-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1 8982 // CHECK12-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1 8983 // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1 8984 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]] 8985 // CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1 8986 // CHECK12-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_9]], align 8 8987 // CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8988 // CHECK12-NEXT: store i32* [[TMP11]], i32** [[__BEGIN1]], align 8 8989 // CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8990 // CHECK12-NEXT: store i32* [[TMP12]], i32** [[__BEGIN2]], align 8 8991 // CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8992 // CHECK12-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 8993 // CHECK12-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP13]], [[TMP14]] 8994 // CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 8995 // CHECK12: land.lhs.true: 8996 // CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8997 // CHECK12-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8998 // CHECK12-NEXT: [[CMP18:%.*]] = icmp ult i32* [[TMP15]], [[TMP16]] 8999 // CHECK12-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 9000 // CHECK12: omp.precond.then: 9001 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 9002 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 9003 // CHECK12-NEXT: store i64 [[TMP17]], i64* [[DOTOMP_UB]], align 8 9004 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 9005 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 9006 // CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9007 // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 9008 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP19]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 9009 // CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9010 // CHECK12-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 9011 // CHECK12-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP20]], [[TMP21]] 9012 // CHECK12-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 9013 // CHECK12: cond.true: 9014 // CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 9015 // CHECK12-NEXT: br label [[COND_END:%.*]] 9016 // CHECK12: cond.false: 9017 // CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9018 // CHECK12-NEXT: br label [[COND_END]] 9019 // CHECK12: cond.end: 9020 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP22]], [[COND_TRUE]] ], [ [[TMP23]], [[COND_FALSE]] ] 9021 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 9022 // CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 9023 // CHECK12-NEXT: store i64 [[TMP24]], i64* [[DOTOMP_IV]], align 8 9024 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 9025 // CHECK12: omp.inner.for.cond: 9026 // CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9027 // CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 9028 // CHECK12-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP25]], [[TMP26]] 9029 // CHECK12-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 9030 // CHECK12: omp.inner.for.body: 9031 // CHECK12-NEXT: [[TMP27:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 9032 // CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9033 // CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 9034 // CHECK12-NEXT: [[TMP30:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 9035 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint i32* [[TMP29]] to i64 9036 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint i32* [[TMP30]] to i64 9037 // CHECK12-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]] 9038 // CHECK12-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4 9039 // CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1 9040 // CHECK12-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1 9041 // CHECK12-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1 9042 // CHECK12-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]] 9043 // CHECK12-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP28]], [[MUL30]] 9044 // CHECK12-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1 9045 // CHECK12-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, i32* [[TMP27]], i64 [[MUL32]] 9046 // CHECK12-NEXT: store i32* [[ADD_PTR33]], i32** [[__BEGIN119]], align 8 9047 // CHECK12-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 9048 // CHECK12-NEXT: [[TMP32:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9049 // CHECK12-NEXT: [[TMP33:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9050 // CHECK12-NEXT: [[TMP34:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 9051 // CHECK12-NEXT: [[TMP35:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 9052 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint i32* [[TMP34]] to i64 9053 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint i32* [[TMP35]] to i64 9054 // CHECK12-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]] 9055 // CHECK12-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4 9056 // CHECK12-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1 9057 // CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1 9058 // CHECK12-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1 9059 // CHECK12-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]] 9060 // CHECK12-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP33]], [[MUL41]] 9061 // CHECK12-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 9062 // CHECK12-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 9063 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint i32* [[TMP36]] to i64 9064 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint i32* [[TMP37]] to i64 9065 // CHECK12-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]] 9066 // CHECK12-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4 9067 // CHECK12-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1 9068 // CHECK12-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1 9069 // CHECK12-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1 9070 // CHECK12-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]] 9071 // CHECK12-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]] 9072 // CHECK12-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP32]], [[MUL51]] 9073 // CHECK12-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1 9074 // CHECK12-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, i32* [[TMP31]], i64 [[MUL53]] 9075 // CHECK12-NEXT: store i32* [[ADD_PTR54]], i32** [[__BEGIN220]], align 8 9076 // CHECK12-NEXT: [[TMP38:%.*]] = load i32*, i32** [[__BEGIN119]], align 8 9077 // CHECK12-NEXT: store i32* [[TMP38]], i32** [[A]], align 8 9078 // CHECK12-NEXT: [[TMP39:%.*]] = load i32*, i32** [[__BEGIN220]], align 8 9079 // CHECK12-NEXT: [[TMP40:%.*]] = load i32, i32* [[TMP39]], align 4 9080 // CHECK12-NEXT: store i32 [[TMP40]], i32* [[B]], align 4 9081 // CHECK12-NEXT: [[TMP41:%.*]] = load i32, i32* [[B]], align 4 9082 // CHECK12-NEXT: [[TMP42:%.*]] = load i32*, i32** [[A]], align 8 9083 // CHECK12-NEXT: store i32 [[TMP41]], i32* [[TMP42]], align 4 9084 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 9085 // CHECK12: omp.body.continue: 9086 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 9087 // CHECK12: omp.inner.for.inc: 9088 // CHECK12-NEXT: [[TMP43:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 9089 // CHECK12-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP43]], 1 9090 // CHECK12-NEXT: store i64 [[ADD55]], i64* [[DOTOMP_IV]], align 8 9091 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 9092 // CHECK12: omp.inner.for.end: 9093 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 9094 // CHECK12: omp.loop.exit: 9095 // CHECK12-NEXT: [[TMP44:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 9096 // CHECK12-NEXT: [[TMP45:%.*]] = load i32, i32* [[TMP44]], align 4 9097 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP45]]) 9098 // CHECK12-NEXT: br label [[OMP_PRECOND_END]] 9099 // CHECK12: omp.precond.end: 9100 // CHECK12-NEXT: ret void 9101 // 9102 // 9103 // CHECK13-LABEL: define {{[^@]+}}@_Z9incrementv 9104 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] { 9105 // CHECK13-NEXT: entry: 9106 // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 9107 // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 9108 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 9109 // CHECK13: for.cond: 9110 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 9111 // CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 5 9112 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 9113 // CHECK13: for.body: 9114 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 9115 // CHECK13: for.inc: 9116 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 9117 // CHECK13-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 9118 // CHECK13-NEXT: store i32 [[INC]], i32* [[I]], align 4 9119 // CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 9120 // CHECK13: for.end: 9121 // CHECK13-NEXT: ret i32 0 9122 // 9123 // 9124 // CHECK13-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv 9125 // CHECK13-SAME: () #[[ATTR0]] { 9126 // CHECK13-NEXT: entry: 9127 // CHECK13-NEXT: [[J:%.*]] = alloca i32, align 4 9128 // CHECK13-NEXT: store i32 5, i32* [[J]], align 4 9129 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 9130 // CHECK13: for.cond: 9131 // CHECK13-NEXT: [[TMP0:%.*]] = load i32, i32* [[J]], align 4 9132 // CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 0 9133 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 9134 // CHECK13: for.body: 9135 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 9136 // CHECK13: for.inc: 9137 // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 9138 // CHECK13-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP1]], -1 9139 // CHECK13-NEXT: store i32 [[DEC]], i32* [[J]], align 4 9140 // CHECK13-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 9141 // CHECK13: for.end: 9142 // CHECK13-NEXT: ret i32 0 9143 // 9144 // 9145 // CHECK13-LABEL: define {{[^@]+}}@_Z16range_for_singlev 9146 // CHECK13-SAME: () #[[ATTR0]] { 9147 // CHECK13-NEXT: entry: 9148 // CHECK13-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 9149 // CHECK13-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 9150 // CHECK13-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 9151 // CHECK13-NEXT: [[__END1:%.*]] = alloca i32*, align 8 9152 // CHECK13-NEXT: [[A:%.*]] = alloca i32*, align 8 9153 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 9154 // CHECK13-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 9155 // CHECK13-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 9156 // CHECK13-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 9157 // CHECK13-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 9158 // CHECK13-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 9159 // CHECK13-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 9160 // CHECK13-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 9161 // CHECK13-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 9162 // CHECK13-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 9163 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 9164 // CHECK13: for.cond: 9165 // CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9166 // CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 9167 // CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] 9168 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 9169 // CHECK13: for.body: 9170 // CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9171 // CHECK13-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 9172 // CHECK13-NEXT: [[TMP6:%.*]] = load i32*, i32** [[A]], align 8 9173 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 9174 // CHECK13: for.inc: 9175 // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9176 // CHECK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 1 9177 // CHECK13-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN1]], align 8 9178 // CHECK13-NEXT: br label [[FOR_COND]] 9179 // CHECK13: for.end: 9180 // CHECK13-NEXT: ret void 9181 // 9182 // 9183 // CHECK13-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv 9184 // CHECK13-SAME: () #[[ATTR0]] { 9185 // CHECK13-NEXT: entry: 9186 // CHECK13-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 9187 // CHECK13-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 9188 // CHECK13-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 9189 // CHECK13-NEXT: [[__END1:%.*]] = alloca i32*, align 8 9190 // CHECK13-NEXT: [[A:%.*]] = alloca i32*, align 8 9191 // CHECK13-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 9192 // CHECK13-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 9193 // CHECK13-NEXT: [[__END2:%.*]] = alloca i32*, align 8 9194 // CHECK13-NEXT: [[B:%.*]] = alloca i32, align 4 9195 // CHECK13-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 9196 // CHECK13-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 9197 // CHECK13-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 9198 // CHECK13-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 9199 // CHECK13-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 9200 // CHECK13-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 9201 // CHECK13-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 9202 // CHECK13-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 9203 // CHECK13-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 9204 // CHECK13-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 9205 // CHECK13-NEXT: br label [[FOR_COND:%.*]] 9206 // CHECK13: for.cond: 9207 // CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9208 // CHECK13-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 9209 // CHECK13-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] 9210 // CHECK13-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END10:%.*]] 9211 // CHECK13: for.body: 9212 // CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9213 // CHECK13-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 9214 // CHECK13-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE2]], align 8 9215 // CHECK13-NEXT: [[TMP6:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 9216 // CHECK13-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP6]], i64 0, i64 0 9217 // CHECK13-NEXT: store i32* [[ARRAYDECAY2]], i32** [[__BEGIN2]], align 8 9218 // CHECK13-NEXT: [[TMP7:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 9219 // CHECK13-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP7]], i64 0, i64 0 9220 // CHECK13-NEXT: [[ADD_PTR4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY3]], i64 10 9221 // CHECK13-NEXT: store i32* [[ADD_PTR4]], i32** [[__END2]], align 8 9222 // CHECK13-NEXT: br label [[FOR_COND5:%.*]] 9223 // CHECK13: for.cond5: 9224 // CHECK13-NEXT: [[TMP8:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 9225 // CHECK13-NEXT: [[TMP9:%.*]] = load i32*, i32** [[__END2]], align 8 9226 // CHECK13-NEXT: [[CMP6:%.*]] = icmp ne i32* [[TMP8]], [[TMP9]] 9227 // CHECK13-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END:%.*]] 9228 // CHECK13: for.body7: 9229 // CHECK13-NEXT: [[TMP10:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 9230 // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 9231 // CHECK13-NEXT: store i32 [[TMP11]], i32* [[B]], align 4 9232 // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 9233 // CHECK13-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A]], align 8 9234 // CHECK13-NEXT: store i32 [[TMP12]], i32* [[TMP13]], align 4 9235 // CHECK13-NEXT: br label [[FOR_INC:%.*]] 9236 // CHECK13: for.inc: 9237 // CHECK13-NEXT: [[TMP14:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 9238 // CHECK13-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP14]], i32 1 9239 // CHECK13-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN2]], align 8 9240 // CHECK13-NEXT: br label [[FOR_COND5]] 9241 // CHECK13: for.end: 9242 // CHECK13-NEXT: br label [[FOR_INC8:%.*]] 9243 // CHECK13: for.inc8: 9244 // CHECK13-NEXT: [[TMP15:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9245 // CHECK13-NEXT: [[INCDEC_PTR9:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i32 1 9246 // CHECK13-NEXT: store i32* [[INCDEC_PTR9]], i32** [[__BEGIN1]], align 8 9247 // CHECK13-NEXT: br label [[FOR_COND]] 9248 // CHECK13: for.end10: 9249 // CHECK13-NEXT: ret void 9250 // 9251 // 9252 // CHECK14-LABEL: define {{[^@]+}}@_Z9incrementv 9253 // CHECK14-SAME: () #[[ATTR0:[0-9]+]] { 9254 // CHECK14-NEXT: entry: 9255 // CHECK14-NEXT: [[I:%.*]] = alloca i32, align 4 9256 // CHECK14-NEXT: store i32 0, i32* [[I]], align 4 9257 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 9258 // CHECK14: for.cond: 9259 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[I]], align 4 9260 // CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 5 9261 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 9262 // CHECK14: for.body: 9263 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 9264 // CHECK14: for.inc: 9265 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[I]], align 4 9266 // CHECK14-NEXT: [[INC:%.*]] = add nsw i32 [[TMP1]], 1 9267 // CHECK14-NEXT: store i32 [[INC]], i32* [[I]], align 4 9268 // CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP2:![0-9]+]] 9269 // CHECK14: for.end: 9270 // CHECK14-NEXT: ret i32 0 9271 // 9272 // 9273 // CHECK14-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv 9274 // CHECK14-SAME: () #[[ATTR0]] { 9275 // CHECK14-NEXT: entry: 9276 // CHECK14-NEXT: [[J:%.*]] = alloca i32, align 4 9277 // CHECK14-NEXT: store i32 5, i32* [[J]], align 4 9278 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 9279 // CHECK14: for.cond: 9280 // CHECK14-NEXT: [[TMP0:%.*]] = load i32, i32* [[J]], align 4 9281 // CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32 [[TMP0]], 0 9282 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 9283 // CHECK14: for.body: 9284 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 9285 // CHECK14: for.inc: 9286 // CHECK14-NEXT: [[TMP1:%.*]] = load i32, i32* [[J]], align 4 9287 // CHECK14-NEXT: [[DEC:%.*]] = add nsw i32 [[TMP1]], -1 9288 // CHECK14-NEXT: store i32 [[DEC]], i32* [[J]], align 4 9289 // CHECK14-NEXT: br label [[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]] 9290 // CHECK14: for.end: 9291 // CHECK14-NEXT: ret i32 0 9292 // 9293 // 9294 // CHECK14-LABEL: define {{[^@]+}}@_Z16range_for_singlev 9295 // CHECK14-SAME: () #[[ATTR0]] { 9296 // CHECK14-NEXT: entry: 9297 // CHECK14-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 9298 // CHECK14-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 9299 // CHECK14-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 9300 // CHECK14-NEXT: [[__END1:%.*]] = alloca i32*, align 8 9301 // CHECK14-NEXT: [[A:%.*]] = alloca i32*, align 8 9302 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 9303 // CHECK14-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 9304 // CHECK14-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 9305 // CHECK14-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 9306 // CHECK14-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 9307 // CHECK14-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 9308 // CHECK14-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 9309 // CHECK14-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 9310 // CHECK14-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 9311 // CHECK14-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 9312 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 9313 // CHECK14: for.cond: 9314 // CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9315 // CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 9316 // CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] 9317 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END:%.*]] 9318 // CHECK14: for.body: 9319 // CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9320 // CHECK14-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 9321 // CHECK14-NEXT: [[TMP6:%.*]] = load i32*, i32** [[A]], align 8 9322 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 9323 // CHECK14: for.inc: 9324 // CHECK14-NEXT: [[TMP7:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9325 // CHECK14-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP7]], i32 1 9326 // CHECK14-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN1]], align 8 9327 // CHECK14-NEXT: br label [[FOR_COND]] 9328 // CHECK14: for.end: 9329 // CHECK14-NEXT: ret void 9330 // 9331 // 9332 // CHECK14-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv 9333 // CHECK14-SAME: () #[[ATTR0]] { 9334 // CHECK14-NEXT: entry: 9335 // CHECK14-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 9336 // CHECK14-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 9337 // CHECK14-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 9338 // CHECK14-NEXT: [[__END1:%.*]] = alloca i32*, align 8 9339 // CHECK14-NEXT: [[A:%.*]] = alloca i32*, align 8 9340 // CHECK14-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 9341 // CHECK14-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 9342 // CHECK14-NEXT: [[__END2:%.*]] = alloca i32*, align 8 9343 // CHECK14-NEXT: [[B:%.*]] = alloca i32, align 4 9344 // CHECK14-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 9345 // CHECK14-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 9346 // CHECK14-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE1]], align 8 9347 // CHECK14-NEXT: [[TMP1:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 9348 // CHECK14-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP1]], i64 0, i64 0 9349 // CHECK14-NEXT: store i32* [[ARRAYDECAY]], i32** [[__BEGIN1]], align 8 9350 // CHECK14-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 9351 // CHECK14-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP2]], i64 0, i64 0 9352 // CHECK14-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY1]], i64 10 9353 // CHECK14-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 9354 // CHECK14-NEXT: br label [[FOR_COND:%.*]] 9355 // CHECK14: for.cond: 9356 // CHECK14-NEXT: [[TMP3:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9357 // CHECK14-NEXT: [[TMP4:%.*]] = load i32*, i32** [[__END1]], align 8 9358 // CHECK14-NEXT: [[CMP:%.*]] = icmp ne i32* [[TMP3]], [[TMP4]] 9359 // CHECK14-NEXT: br i1 [[CMP]], label [[FOR_BODY:%.*]], label [[FOR_END10:%.*]] 9360 // CHECK14: for.body: 9361 // CHECK14-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9362 // CHECK14-NEXT: store i32* [[TMP5]], i32** [[A]], align 8 9363 // CHECK14-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[__RANGE2]], align 8 9364 // CHECK14-NEXT: [[TMP6:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 9365 // CHECK14-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP6]], i64 0, i64 0 9366 // CHECK14-NEXT: store i32* [[ARRAYDECAY2]], i32** [[__BEGIN2]], align 8 9367 // CHECK14-NEXT: [[TMP7:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 9368 // CHECK14-NEXT: [[ARRAYDECAY3:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP7]], i64 0, i64 0 9369 // CHECK14-NEXT: [[ADD_PTR4:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY3]], i64 10 9370 // CHECK14-NEXT: store i32* [[ADD_PTR4]], i32** [[__END2]], align 8 9371 // CHECK14-NEXT: br label [[FOR_COND5:%.*]] 9372 // CHECK14: for.cond5: 9373 // CHECK14-NEXT: [[TMP8:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 9374 // CHECK14-NEXT: [[TMP9:%.*]] = load i32*, i32** [[__END2]], align 8 9375 // CHECK14-NEXT: [[CMP6:%.*]] = icmp ne i32* [[TMP8]], [[TMP9]] 9376 // CHECK14-NEXT: br i1 [[CMP6]], label [[FOR_BODY7:%.*]], label [[FOR_END:%.*]] 9377 // CHECK14: for.body7: 9378 // CHECK14-NEXT: [[TMP10:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 9379 // CHECK14-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP10]], align 4 9380 // CHECK14-NEXT: store i32 [[TMP11]], i32* [[B]], align 4 9381 // CHECK14-NEXT: [[TMP12:%.*]] = load i32, i32* [[B]], align 4 9382 // CHECK14-NEXT: [[TMP13:%.*]] = load i32*, i32** [[A]], align 8 9383 // CHECK14-NEXT: store i32 [[TMP12]], i32* [[TMP13]], align 4 9384 // CHECK14-NEXT: br label [[FOR_INC:%.*]] 9385 // CHECK14: for.inc: 9386 // CHECK14-NEXT: [[TMP14:%.*]] = load i32*, i32** [[__BEGIN2]], align 8 9387 // CHECK14-NEXT: [[INCDEC_PTR:%.*]] = getelementptr inbounds i32, i32* [[TMP14]], i32 1 9388 // CHECK14-NEXT: store i32* [[INCDEC_PTR]], i32** [[__BEGIN2]], align 8 9389 // CHECK14-NEXT: br label [[FOR_COND5]] 9390 // CHECK14: for.end: 9391 // CHECK14-NEXT: br label [[FOR_INC8:%.*]] 9392 // CHECK14: for.inc8: 9393 // CHECK14-NEXT: [[TMP15:%.*]] = load i32*, i32** [[__BEGIN1]], align 8 9394 // CHECK14-NEXT: [[INCDEC_PTR9:%.*]] = getelementptr inbounds i32, i32* [[TMP15]], i32 1 9395 // CHECK14-NEXT: store i32* [[INCDEC_PTR9]], i32** [[__BEGIN1]], align 8 9396 // CHECK14-NEXT: br label [[FOR_COND]] 9397 // CHECK14: for.end10: 9398 // CHECK14-NEXT: ret void 9399 // 9400