1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ 2 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK1 3 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK2 4 5 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 6 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 7 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 9 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK4 10 11 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5 12 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6 13 14 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 15 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 16 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 17 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 18 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 19 // expected-no-diagnostics 20 21 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefix=CHECK11 22 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 23 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12 24 // RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 25 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 26 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" 27 #ifndef HEADER 28 #define HEADER 29 30 #ifndef OMP5 31 32 void with_var_schedule() { 33 double a = 5; 34 35 #pragma omp parallel for schedule(static, char(a)) private(a) 36 for (unsigned long long i = 1; i < 2 + a; ++i) { 37 } 38 } 39 40 void without_schedule_clause(float *a, float *b, float *c, float *d) { 41 #pragma omp parallel for 42 // UB = min(UB, GlobalUB) 43 // Loop header 44 for (int i = 33; i < 32000000; i += 7) { 45 // Start of body: calculate i from IV: 46 // ... loop body ... 47 // End of body: store into a[i]: 48 a[i] = b[i] * c[i] * d[i]; 49 } 50 } 51 52 void static_not_chunked(float *a, float *b, float *c, float *d) { 53 #pragma omp parallel for schedule(static) 54 // UB = min(UB, GlobalUB) 55 // Loop header 56 for (int i = 32000000; i > 33; i += -7) { 57 // Start of body: calculate i from IV: 58 // ... loop body ... 59 // End of body: store into a[i]: 60 a[i] = b[i] * c[i] * d[i]; 61 } 62 } 63 64 void static_chunked(float *a, float *b, float *c, float *d) { 65 #pragma omp parallel for schedule(static, 5) 66 // UB = min(UB, GlobalUB) 67 68 // Outer loop header 69 70 // Loop header 71 for (unsigned i = 131071; i <= 2147483647; i += 127) { 72 // Start of body: calculate i from IV: 73 // ... loop body ... 74 // End of body: store into a[i]: 75 a[i] = b[i] * c[i] * d[i]; 76 } 77 // Update the counters, adding stride 78 79 } 80 81 void dynamic1(float *a, float *b, float *c, float *d) { 82 #pragma omp parallel for schedule(dynamic) 83 84 // Loop header 85 86 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 87 // Start of body: calculate i from IV: 88 // ... loop body ... 89 // End of body: store into a[i]: 90 a[i] = b[i] * c[i] * d[i]; 91 } 92 } 93 94 void guided7(float *a, float *b, float *c, float *d) { 95 #pragma omp parallel for schedule(guided, 7) 96 97 // Loop header 98 99 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 100 // Start of body: calculate i from IV: 101 // ... loop body ... 102 // End of body: store into a[i]: 103 a[i] = b[i] * c[i] * d[i]; 104 } 105 } 106 107 void test_auto(float *a, float *b, float *c, float *d) { 108 unsigned int x = 0; 109 unsigned int y = 0; 110 #pragma omp parallel for schedule(auto) collapse(2) 111 112 // Loop header 113 114 // FIXME: When the iteration count of some nested loop is not a known constant, 115 // we should pre-calculate it, like we do for the total number of iterations! 116 for (char i = static_cast<char>(y); i <= '9'; ++i) 117 for (x = 11; x > 0; --x) { 118 // Start of body: indices are calculated from IV: 119 // ... loop body ... 120 // End of body: store into a[i]: 121 a[i] = b[i] * c[i] * d[i]; 122 } 123 } 124 125 void runtime(float *a, float *b, float *c, float *d) { 126 int x = 0; 127 #pragma omp parallel for collapse(2) schedule(runtime) 128 129 // Loop header 130 131 for (unsigned char i = '0' ; i <= '9'; ++i) 132 for (x = -10; x < 10; ++x) { 133 // Start of body: indices are calculated from IV: 134 // ... loop body ... 135 // End of body: store into a[i]: 136 a[i] = b[i] * c[i] * d[i]; 137 } 138 } 139 140 int foo() { extern void mayThrow(); mayThrow(); return 0; }; 141 142 void parallel_for(float *a, const int n) { 143 float arr[n]; 144 #pragma omp parallel for schedule(static, 5) private(arr) default(none) firstprivate(n) shared(a) 145 for (unsigned i = 131071; i <= 2147483647; i += 127) 146 a[i] += foo() + arr[i] + n; 147 } 148 // Check source line corresponds to "#pragma omp parallel for schedule(static, 5)" above: 149 150 #else // OMP5 151 int increment () { 152 #pragma omp for 153 // Determine UB = min(UB, GlobalUB) 154 155 // Loop header 156 157 for (int i = 0 ; i != 5; ++i) 158 // Start of body: calculate i from IV: 159 ; 160 return 0; 161 } 162 163 int decrement_nowait () { 164 #pragma omp for nowait 165 // Determine UB = min(UB, GlobalUB) 166 167 // Loop header 168 for (int j = 5 ; j != 0; --j) 169 // Start of body: calculate i from IV: 170 ; 171 return 0; 172 } 173 174 void range_for_single() { 175 int arr[10] = {0}; 176 #pragma omp parallel for 177 for (auto &a : arr) 178 (void)a; 179 } 180 181 182 // __range = arr; 183 184 // __end = end(_range); 185 186 187 // calculate number of elements. 188 189 // __begin = begin(range); 190 191 // __begin >= __end ? goto then : goto exit; 192 193 194 // lb = 0; 195 196 // ub = number of elements 197 198 // stride = 1; 199 200 // is_last = 0; 201 202 // loop. 203 204 // ub = (ub > number_of_elems ? number_of_elems : ub); 205 206 207 208 // OMP%: store i64 [[MIN]], i64* [[UB]], 209 210 // iv = lb; 211 212 // goto loop; 213 // loop: 214 215 216 // iv <= ub ? goto body : goto end; 217 218 // body: 219 // __begin = begin(arr) + iv * 1; 220 221 // a = *__begin; 222 223 // (void)a; 224 225 // iv += 1; 226 227 // goto loop; 228 229 // end: 230 // exit: 231 232 void range_for_collapsed() { 233 int arr[10] = {0}; 234 #pragma omp parallel for collapse(2) 235 for (auto &a : arr) 236 for (auto b : arr) 237 a = b; 238 } 239 #endif // OMP5 240 241 #endif // HEADER 242 243 // CHECK1-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 244 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] { 245 // CHECK1-NEXT: entry: 246 // CHECK1-NEXT: [[A:%.*]] = alloca double, align 8 247 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 248 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 249 // CHECK1-NEXT: store double 5.000000e+00, double* [[A]], align 8 250 // CHECK1-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 251 // CHECK1-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 252 // CHECK1-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 253 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 254 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 255 // CHECK1-NEXT: store i8 [[TMP2]], i8* [[TMP1]], align 1 256 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 257 // CHECK1-NEXT: ret void 258 // 259 // 260 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. 261 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { 262 // CHECK1-NEXT: entry: 263 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 264 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 265 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 266 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 267 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 268 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 269 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 270 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 271 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 272 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 273 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 274 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 275 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 276 // CHECK1-NEXT: [[A:%.*]] = alloca double, align 8 277 // CHECK1-NEXT: [[I4:%.*]] = alloca i64, align 8 278 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 279 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 280 // CHECK1-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 281 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 282 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 283 // CHECK1-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 284 // CHECK1-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 285 // CHECK1-NEXT: [[TMP3:%.*]] = load double, double* undef, align 8 286 // CHECK1-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 287 // CHECK1-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 288 // CHECK1-NEXT: [[TMP4:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 289 // CHECK1-NEXT: [[SUB:%.*]] = fsub double [[TMP4]], 1.000000e+00 290 // CHECK1-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 291 // CHECK1-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i64 292 // CHECK1-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 1 293 // CHECK1-NEXT: store i64 [[SUB3]], i64* [[DOTCAPTURE_EXPR_2]], align 8 294 // CHECK1-NEXT: store i64 1, i64* [[I]], align 8 295 // CHECK1-NEXT: [[TMP5:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 296 // CHECK1-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP5]] 297 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 298 // CHECK1: omp.precond.then: 299 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 300 // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 301 // CHECK1-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_UB]], align 8 302 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 303 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 304 // CHECK1-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 305 // CHECK1-NEXT: [[CONV5:%.*]] = sext i8 [[TMP7]] to i64 306 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 307 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 308 // CHECK1-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]]) 309 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 310 // CHECK1: omp.dispatch.cond: 311 // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 312 // CHECK1-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 313 // CHECK1-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP10]], [[TMP11]] 314 // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 315 // CHECK1: cond.true: 316 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 317 // CHECK1-NEXT: br label [[COND_END:%.*]] 318 // CHECK1: cond.false: 319 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 320 // CHECK1-NEXT: br label [[COND_END]] 321 // CHECK1: cond.end: 322 // CHECK1-NEXT: [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 323 // CHECK1-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 324 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 325 // CHECK1-NEXT: store i64 [[TMP14]], i64* [[DOTOMP_IV]], align 8 326 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 327 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 328 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 329 // CHECK1-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP15]], [[ADD7]] 330 // CHECK1-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 331 // CHECK1: omp.dispatch.body: 332 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 333 // CHECK1: omp.inner.for.cond: 334 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 335 // CHECK1-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 336 // CHECK1-NEXT: [[ADD9:%.*]] = add i64 [[TMP18]], 1 337 // CHECK1-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP17]], [[ADD9]] 338 // CHECK1-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 339 // CHECK1: omp.inner.for.body: 340 // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 341 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP19]], 1 342 // CHECK1-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]] 343 // CHECK1-NEXT: store i64 [[ADD11]], i64* [[I4]], align 8 344 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 345 // CHECK1: omp.body.continue: 346 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 347 // CHECK1: omp.inner.for.inc: 348 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 349 // CHECK1-NEXT: [[ADD12:%.*]] = add i64 [[TMP20]], 1 350 // CHECK1-NEXT: store i64 [[ADD12]], i64* [[DOTOMP_IV]], align 8 351 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 352 // CHECK1: omp.inner.for.end: 353 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 354 // CHECK1: omp.dispatch.inc: 355 // CHECK1-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 356 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 357 // CHECK1-NEXT: [[ADD13:%.*]] = add i64 [[TMP21]], [[TMP22]] 358 // CHECK1-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_LB]], align 8 359 // CHECK1-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 360 // CHECK1-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 361 // CHECK1-NEXT: [[ADD14:%.*]] = add i64 [[TMP23]], [[TMP24]] 362 // CHECK1-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_UB]], align 8 363 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 364 // CHECK1: omp.dispatch.end: 365 // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 366 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 367 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 368 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 369 // CHECK1: omp.precond.end: 370 // CHECK1-NEXT: ret void 371 // 372 // 373 // CHECK1-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 374 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 375 // CHECK1-NEXT: entry: 376 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 377 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 378 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 379 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 380 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 381 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 382 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 383 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 384 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 385 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 386 // CHECK1-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 387 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 388 // CHECK1-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 389 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 390 // CHECK1-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 391 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 392 // CHECK1-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 393 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]]) 394 // CHECK1-NEXT: ret void 395 // 396 // 397 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 398 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 399 // CHECK1-NEXT: entry: 400 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 401 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 402 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.0*, align 8 403 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 404 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 405 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 406 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 407 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 408 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 409 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 410 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 411 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 412 // CHECK1-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 413 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 414 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 415 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 416 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 417 // CHECK1-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 418 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 419 // CHECK1-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 420 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 3 421 // CHECK1-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 422 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 423 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 424 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 425 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 426 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 427 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 428 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 429 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 430 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 431 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 432 // CHECK1: cond.true: 433 // CHECK1-NEXT: br label [[COND_END:%.*]] 434 // CHECK1: cond.false: 435 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 436 // CHECK1-NEXT: br label [[COND_END]] 437 // CHECK1: cond.end: 438 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 439 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 440 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 441 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 442 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 443 // CHECK1: omp.inner.for.cond: 444 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 445 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 446 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 447 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 448 // CHECK1: omp.inner.for.body: 449 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 450 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 451 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 452 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 453 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 454 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 455 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 456 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 457 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 458 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 459 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 460 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 461 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 462 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 463 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 464 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 465 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 466 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 467 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 468 // CHECK1-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 469 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 470 // CHECK1-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 471 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 472 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 473 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 474 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 475 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 476 // CHECK1: omp.body.continue: 477 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 478 // CHECK1: omp.inner.for.inc: 479 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 480 // CHECK1-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP28]], 1 481 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 482 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 483 // CHECK1: omp.inner.for.end: 484 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 485 // CHECK1: omp.loop.exit: 486 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 487 // CHECK1-NEXT: ret void 488 // 489 // 490 // CHECK1-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 491 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 492 // CHECK1-NEXT: entry: 493 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 494 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 495 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 496 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 497 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 498 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 499 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 500 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 501 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 502 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 503 // CHECK1-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 504 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 505 // CHECK1-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 506 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 507 // CHECK1-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 508 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 509 // CHECK1-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 510 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.1*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]]) 511 // CHECK1-NEXT: ret void 512 // 513 // 514 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 515 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 516 // CHECK1-NEXT: entry: 517 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 518 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 519 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.1*, align 8 520 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 521 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 522 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 523 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 524 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 525 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 526 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 527 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 528 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 529 // CHECK1-NEXT: store %struct.anon.1* [[__CONTEXT]], %struct.anon.1** [[__CONTEXT_ADDR]], align 8 530 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR]], align 8 531 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP0]], i32 0, i32 0 532 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 533 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 1 534 // CHECK1-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 535 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 2 536 // CHECK1-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 537 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 3 538 // CHECK1-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 539 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 540 // CHECK1-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 541 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 542 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 543 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 544 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 545 // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 546 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 547 // CHECK1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 548 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 549 // CHECK1: cond.true: 550 // CHECK1-NEXT: br label [[COND_END:%.*]] 551 // CHECK1: cond.false: 552 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 553 // CHECK1-NEXT: br label [[COND_END]] 554 // CHECK1: cond.end: 555 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 556 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 557 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 558 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 559 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 560 // CHECK1: omp.inner.for.cond: 561 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 562 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 563 // CHECK1-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 564 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 565 // CHECK1: omp.inner.for.body: 566 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 567 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 568 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 569 // CHECK1-NEXT: store i32 [[SUB]], i32* [[I]], align 4 570 // CHECK1-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 571 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 572 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 573 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 574 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 575 // CHECK1-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 576 // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 577 // CHECK1-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 578 // CHECK1-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 579 // CHECK1-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 580 // CHECK1-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 581 // CHECK1-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 582 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 583 // CHECK1-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 584 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 585 // CHECK1-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 586 // CHECK1-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 587 // CHECK1-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 588 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 589 // CHECK1-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 590 // CHECK1-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 591 // CHECK1-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 592 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 593 // CHECK1: omp.body.continue: 594 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 595 // CHECK1: omp.inner.for.inc: 596 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 597 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP28]], 1 598 // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 599 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 600 // CHECK1: omp.inner.for.end: 601 // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 602 // CHECK1: omp.loop.exit: 603 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 604 // CHECK1-NEXT: ret void 605 // 606 // 607 // CHECK1-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 608 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 609 // CHECK1-NEXT: entry: 610 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 611 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 612 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 613 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 614 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8 615 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 616 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 617 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 618 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 619 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 620 // CHECK1-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 621 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 622 // CHECK1-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 623 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 624 // CHECK1-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 625 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 626 // CHECK1-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 627 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.2*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]]) 628 // CHECK1-NEXT: ret void 629 // 630 // 631 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 632 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 633 // CHECK1-NEXT: entry: 634 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 635 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 636 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.2*, align 8 637 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 638 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 639 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 640 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 641 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 642 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 643 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 644 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 645 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 646 // CHECK1-NEXT: store %struct.anon.2* [[__CONTEXT]], %struct.anon.2** [[__CONTEXT_ADDR]], align 8 647 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR]], align 8 648 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], %struct.anon.2* [[TMP0]], i32 0, i32 0 649 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 650 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 1 651 // CHECK1-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 652 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 2 653 // CHECK1-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 654 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 3 655 // CHECK1-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 656 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 657 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 658 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 659 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 660 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 661 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 662 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 663 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 664 // CHECK1: omp.dispatch.cond: 665 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 666 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP11]], 16908288 667 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 668 // CHECK1: cond.true: 669 // CHECK1-NEXT: br label [[COND_END:%.*]] 670 // CHECK1: cond.false: 671 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 672 // CHECK1-NEXT: br label [[COND_END]] 673 // CHECK1: cond.end: 674 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 675 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 676 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 677 // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 678 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 679 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 680 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]] 681 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 682 // CHECK1: omp.dispatch.body: 683 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 684 // CHECK1: omp.inner.for.cond: 685 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 686 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 687 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP16]], [[TMP17]] 688 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 689 // CHECK1: omp.inner.for.body: 690 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 691 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP18]], 127 692 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 693 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 694 // CHECK1-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP4]], align 8 695 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 696 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP20]] to i64 697 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM]] 698 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 699 // CHECK1-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP6]], align 8 700 // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 701 // CHECK1-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP23]] to i64 702 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM3]] 703 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4 704 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[TMP21]], [[TMP24]] 705 // CHECK1-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP8]], align 8 706 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 707 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP26]] to i64 708 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[IDXPROM6]] 709 // CHECK1-NEXT: [[TMP27:%.*]] = load float, float* [[ARRAYIDX7]], align 4 710 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP27]] 711 // CHECK1-NEXT: [[TMP28:%.*]] = load float*, float** [[TMP2]], align 8 712 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[I]], align 4 713 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP29]] to i64 714 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP28]], i64 [[IDXPROM9]] 715 // CHECK1-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 716 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 717 // CHECK1: omp.body.continue: 718 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 719 // CHECK1: omp.inner.for.inc: 720 // CHECK1-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 721 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP30]], 1 722 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 723 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 724 // CHECK1: omp.inner.for.end: 725 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 726 // CHECK1: omp.dispatch.inc: 727 // CHECK1-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 728 // CHECK1-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 729 // CHECK1-NEXT: [[ADD12:%.*]] = add i32 [[TMP31]], [[TMP32]] 730 // CHECK1-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 731 // CHECK1-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 732 // CHECK1-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 733 // CHECK1-NEXT: [[ADD13:%.*]] = add i32 [[TMP33]], [[TMP34]] 734 // CHECK1-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 735 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 736 // CHECK1: omp.dispatch.end: 737 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 738 // CHECK1-NEXT: ret void 739 // 740 // 741 // CHECK1-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 742 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 743 // CHECK1-NEXT: entry: 744 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 745 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 746 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 747 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 748 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 8 749 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 750 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 751 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 752 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 753 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 754 // CHECK1-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 755 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 756 // CHECK1-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 757 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 758 // CHECK1-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 759 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 760 // CHECK1-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 761 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.3*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]]) 762 // CHECK1-NEXT: ret void 763 // 764 // 765 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..4 766 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 767 // CHECK1-NEXT: entry: 768 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 769 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 770 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.3*, align 8 771 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 772 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 773 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 774 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 775 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 776 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 777 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 778 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 779 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 780 // CHECK1-NEXT: store %struct.anon.3* [[__CONTEXT]], %struct.anon.3** [[__CONTEXT_ADDR]], align 8 781 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.3*, %struct.anon.3** [[__CONTEXT_ADDR]], align 8 782 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], %struct.anon.3* [[TMP0]], i32 0, i32 0 783 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 784 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 1 785 // CHECK1-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 786 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 2 787 // CHECK1-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 788 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 3 789 // CHECK1-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 790 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 791 // CHECK1-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 792 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 793 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 794 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 795 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 796 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1) 797 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 798 // CHECK1: omp.dispatch.cond: 799 // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 800 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 801 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 802 // CHECK1: omp.dispatch.body: 803 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 804 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 805 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 806 // CHECK1: omp.inner.for.cond: 807 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 808 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 809 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 810 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 811 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 812 // CHECK1: omp.inner.for.body: 813 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 814 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 815 // CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 816 // CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5 817 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !5 818 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 819 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 820 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !5 821 // CHECK1-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !5 822 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 823 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 824 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !5 825 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 826 // CHECK1-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !5 827 // CHECK1-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 828 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 829 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !5 830 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 831 // CHECK1-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !5 832 // CHECK1-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 833 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 834 // CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5 835 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 836 // CHECK1: omp.body.continue: 837 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 838 // CHECK1: omp.inner.for.inc: 839 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 840 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 841 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 842 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 843 // CHECK1: omp.inner.for.end: 844 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 845 // CHECK1: omp.dispatch.inc: 846 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 847 // CHECK1: omp.dispatch.end: 848 // CHECK1-NEXT: ret void 849 // 850 // 851 // CHECK1-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 852 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 853 // CHECK1-NEXT: entry: 854 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 855 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 856 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 857 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 858 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8 859 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 860 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 861 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 862 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 863 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 864 // CHECK1-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 865 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 866 // CHECK1-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 867 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 868 // CHECK1-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 869 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 870 // CHECK1-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 871 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.4*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]]) 872 // CHECK1-NEXT: ret void 873 // 874 // 875 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..5 876 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 877 // CHECK1-NEXT: entry: 878 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 879 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 880 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.4*, align 8 881 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 882 // CHECK1-NEXT: [[TMP:%.*]] = alloca i64, align 8 883 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 884 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 885 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 886 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 887 // CHECK1-NEXT: [[I:%.*]] = alloca i64, align 8 888 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 889 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 890 // CHECK1-NEXT: store %struct.anon.4* [[__CONTEXT]], %struct.anon.4** [[__CONTEXT_ADDR]], align 8 891 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR]], align 8 892 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], %struct.anon.4* [[TMP0]], i32 0, i32 0 893 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 894 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 1 895 // CHECK1-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 896 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 2 897 // CHECK1-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 898 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 3 899 // CHECK1-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 900 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 901 // CHECK1-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 902 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 903 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 904 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 905 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 906 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7) 907 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 908 // CHECK1: omp.dispatch.cond: 909 // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 910 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 911 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 912 // CHECK1: omp.dispatch.body: 913 // CHECK1-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 914 // CHECK1-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 915 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 916 // CHECK1: omp.inner.for.cond: 917 // CHECK1-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 918 // CHECK1-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !8 919 // CHECK1-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 920 // CHECK1-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 921 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 922 // CHECK1: omp.inner.for.body: 923 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 924 // CHECK1-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 925 // CHECK1-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 926 // CHECK1-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8 927 // CHECK1-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !8 928 // CHECK1-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 929 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 930 // CHECK1-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 931 // CHECK1-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !8 932 // CHECK1-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 933 // CHECK1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 934 // CHECK1-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !8 935 // CHECK1-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 936 // CHECK1-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !8 937 // CHECK1-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 938 // CHECK1-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 939 // CHECK1-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !8 940 // CHECK1-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 941 // CHECK1-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 942 // CHECK1-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 943 // CHECK1-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 944 // CHECK1-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 945 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 946 // CHECK1: omp.body.continue: 947 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 948 // CHECK1: omp.inner.for.inc: 949 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 950 // CHECK1-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 951 // CHECK1-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 952 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 953 // CHECK1: omp.inner.for.end: 954 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 955 // CHECK1: omp.dispatch.inc: 956 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 957 // CHECK1: omp.dispatch.end: 958 // CHECK1-NEXT: ret void 959 // 960 // 961 // CHECK1-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 962 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 963 // CHECK1-NEXT: entry: 964 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 965 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 966 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 967 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 968 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 969 // CHECK1-NEXT: [[Y:%.*]] = alloca i32, align 4 970 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_5:%.*]], align 8 971 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 972 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 973 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 974 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 975 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 976 // CHECK1-NEXT: store i32 0, i32* [[Y]], align 4 977 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 978 // CHECK1-NEXT: store i32* [[Y]], i32** [[TMP0]], align 8 979 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 980 // CHECK1-NEXT: store float** [[A_ADDR]], float*** [[TMP1]], align 8 981 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 982 // CHECK1-NEXT: store float** [[B_ADDR]], float*** [[TMP2]], align 8 983 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 984 // CHECK1-NEXT: store float** [[C_ADDR]], float*** [[TMP3]], align 8 985 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 4 986 // CHECK1-NEXT: store float** [[D_ADDR]], float*** [[TMP4]], align 8 987 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.5*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]) 988 // CHECK1-NEXT: ret void 989 // 990 // 991 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..6 992 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 993 // CHECK1-NEXT: entry: 994 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 995 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 996 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.5*, align 8 997 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 998 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 999 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1000 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1001 // CHECK1-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 1002 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 1003 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 1004 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1005 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1006 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1007 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1008 // CHECK1-NEXT: [[I7:%.*]] = alloca i8, align 1 1009 // CHECK1-NEXT: [[X8:%.*]] = alloca i32, align 4 1010 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1011 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1012 // CHECK1-NEXT: store %struct.anon.5* [[__CONTEXT]], %struct.anon.5** [[__CONTEXT_ADDR]], align 8 1013 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.5*, %struct.anon.5** [[__CONTEXT_ADDR]], align 8 1014 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], %struct.anon.5* [[TMP0]], i32 0, i32 0 1015 // CHECK1-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 1016 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 1 1017 // CHECK1-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 1018 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 2 1019 // CHECK1-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 1020 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 3 1021 // CHECK1-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 1022 // CHECK1-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 4 1023 // CHECK1-NEXT: [[TMP10:%.*]] = load float**, float*** [[TMP9]], align 8 1024 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP2]], align 4 1025 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[TMP11]] to i8 1026 // CHECK1-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 1027 // CHECK1-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1028 // CHECK1-NEXT: [[CONV3:%.*]] = sext i8 [[TMP12]] to i32 1029 // CHECK1-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 1030 // CHECK1-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 1031 // CHECK1-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 1032 // CHECK1-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 1033 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 1034 // CHECK1-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 1035 // CHECK1-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 1036 // CHECK1-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1037 // CHECK1-NEXT: store i8 [[TMP13]], i8* [[I]], align 1 1038 // CHECK1-NEXT: store i32 11, i32* [[X]], align 4 1039 // CHECK1-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1040 // CHECK1-NEXT: [[CONV6:%.*]] = sext i8 [[TMP14]] to i32 1041 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 1042 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1043 // CHECK1: omp.precond.then: 1044 // CHECK1-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1045 // CHECK1-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1046 // CHECK1-NEXT: store i64 [[TMP15]], i64* [[DOTOMP_UB]], align 8 1047 // CHECK1-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1048 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1049 // CHECK1-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1050 // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1051 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 1052 // CHECK1-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], i32 1073741862, i64 0, i64 [[TMP16]], i64 1, i64 1) 1053 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1054 // CHECK1: omp.dispatch.cond: 1055 // CHECK1-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1056 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 1057 // CHECK1-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP20]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1058 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP21]], 0 1059 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1060 // CHECK1: omp.dispatch.body: 1061 // CHECK1-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1062 // CHECK1-NEXT: store i64 [[TMP22]], i64* [[DOTOMP_IV]], align 8 1063 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1064 // CHECK1: omp.inner.for.cond: 1065 // CHECK1-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1066 // CHECK1-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !11 1067 // CHECK1-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP23]], [[TMP24]] 1068 // CHECK1-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1069 // CHECK1: omp.inner.for.body: 1070 // CHECK1-NEXT: [[TMP25:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11 1071 // CHECK1-NEXT: [[CONV10:%.*]] = sext i8 [[TMP25]] to i64 1072 // CHECK1-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1073 // CHECK1-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP26]], 11 1074 // CHECK1-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 1075 // CHECK1-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 1076 // CHECK1-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 1077 // CHECK1-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11 1078 // CHECK1-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1079 // CHECK1-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1080 // CHECK1-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP28]], 11 1081 // CHECK1-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 1082 // CHECK1-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP27]], [[MUL16]] 1083 // CHECK1-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 1084 // CHECK1-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 1085 // CHECK1-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 1086 // CHECK1-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11 1087 // CHECK1-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !11 1088 // CHECK1-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 1089 // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP30]] to i64 1090 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM]] 1091 // CHECK1-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 1092 // CHECK1-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !11 1093 // CHECK1-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 1094 // CHECK1-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP33]] to i64 1095 // CHECK1-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM21]] 1096 // CHECK1-NEXT: [[TMP34:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !11 1097 // CHECK1-NEXT: [[MUL23:%.*]] = fmul float [[TMP31]], [[TMP34]] 1098 // CHECK1-NEXT: [[TMP35:%.*]] = load float*, float** [[TMP10]], align 8, !llvm.access.group !11 1099 // CHECK1-NEXT: [[TMP36:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 1100 // CHECK1-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP36]] to i64 1101 // CHECK1-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP35]], i64 [[IDXPROM24]] 1102 // CHECK1-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !11 1103 // CHECK1-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP37]] 1104 // CHECK1-NEXT: [[TMP38:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !11 1105 // CHECK1-NEXT: [[TMP39:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 1106 // CHECK1-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP39]] to i64 1107 // CHECK1-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP38]], i64 [[IDXPROM27]] 1108 // CHECK1-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11 1109 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1110 // CHECK1: omp.body.continue: 1111 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1112 // CHECK1: omp.inner.for.inc: 1113 // CHECK1-NEXT: [[TMP40:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1114 // CHECK1-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP40]], 1 1115 // CHECK1-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 1116 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 1117 // CHECK1: omp.inner.for.end: 1118 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1119 // CHECK1: omp.dispatch.inc: 1120 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1121 // CHECK1: omp.dispatch.end: 1122 // CHECK1-NEXT: br label [[OMP_PRECOND_END]] 1123 // CHECK1: omp.precond.end: 1124 // CHECK1-NEXT: ret void 1125 // 1126 // 1127 // CHECK1-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 1128 // CHECK1-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1129 // CHECK1-NEXT: entry: 1130 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1131 // CHECK1-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1132 // CHECK1-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1133 // CHECK1-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1134 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 1135 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 8 1136 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1137 // CHECK1-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1138 // CHECK1-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1139 // CHECK1-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1140 // CHECK1-NEXT: store i32 0, i32* [[X]], align 4 1141 // CHECK1-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 1142 // CHECK1-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 1143 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 1144 // CHECK1-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 1145 // CHECK1-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 1146 // CHECK1-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 1147 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 1148 // CHECK1-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 1149 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.6*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]]) 1150 // CHECK1-NEXT: ret void 1151 // 1152 // 1153 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..7 1154 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 1155 // CHECK1-NEXT: entry: 1156 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1157 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1158 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.6*, align 8 1159 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1160 // CHECK1-NEXT: [[TMP:%.*]] = alloca i8, align 1 1161 // CHECK1-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 1162 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1163 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1164 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1165 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1166 // CHECK1-NEXT: [[I:%.*]] = alloca i8, align 1 1167 // CHECK1-NEXT: [[X:%.*]] = alloca i32, align 4 1168 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1169 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1170 // CHECK1-NEXT: store %struct.anon.6* [[__CONTEXT]], %struct.anon.6** [[__CONTEXT_ADDR]], align 8 1171 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR]], align 8 1172 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], %struct.anon.6* [[TMP0]], i32 0, i32 0 1173 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 1174 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 1 1175 // CHECK1-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 1176 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 2 1177 // CHECK1-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 1178 // CHECK1-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 3 1179 // CHECK1-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 1180 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1181 // CHECK1-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 1182 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1183 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1184 // CHECK1-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1185 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1186 // CHECK1-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 1073741861, i32 0, i32 199, i32 1, i32 1) 1187 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1188 // CHECK1: omp.dispatch.cond: 1189 // CHECK1-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 1190 // CHECK1-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 1191 // CHECK1-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1192 // CHECK1: omp.dispatch.body: 1193 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1194 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1195 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1196 // CHECK1: omp.inner.for.cond: 1197 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1198 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 1199 // CHECK1-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 1200 // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1201 // CHECK1: omp.inner.for.body: 1202 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1203 // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP15]], 20 1204 // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 1205 // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 1206 // CHECK1-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 1207 // CHECK1-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14 1208 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1209 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1210 // CHECK1-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP17]], 20 1211 // CHECK1-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 1212 // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP16]], [[MUL3]] 1213 // CHECK1-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 1214 // CHECK1-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 1215 // CHECK1-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14 1216 // CHECK1-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !14 1217 // CHECK1-NEXT: [[TMP19:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 1218 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP19]] to i64 1219 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM]] 1220 // CHECK1-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 1221 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !14 1222 // CHECK1-NEXT: [[TMP22:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 1223 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP22]] to i64 1224 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 1225 // CHECK1-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !14 1226 // CHECK1-NEXT: [[MUL8:%.*]] = fmul float [[TMP20]], [[TMP23]] 1227 // CHECK1-NEXT: [[TMP24:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !14 1228 // CHECK1-NEXT: [[TMP25:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 1229 // CHECK1-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP25]] to i64 1230 // CHECK1-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM9]] 1231 // CHECK1-NEXT: [[TMP26:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 1232 // CHECK1-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP26]] 1233 // CHECK1-NEXT: [[TMP27:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !14 1234 // CHECK1-NEXT: [[TMP28:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 1235 // CHECK1-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP28]] to i64 1236 // CHECK1-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP27]], i64 [[IDXPROM12]] 1237 // CHECK1-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14 1238 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1239 // CHECK1: omp.body.continue: 1240 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1241 // CHECK1: omp.inner.for.inc: 1242 // CHECK1-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1243 // CHECK1-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP29]], 1 1244 // CHECK1-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 1245 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 1246 // CHECK1: omp.inner.for.end: 1247 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1248 // CHECK1: omp.dispatch.inc: 1249 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1250 // CHECK1: omp.dispatch.end: 1251 // CHECK1-NEXT: ret void 1252 // 1253 // 1254 // CHECK1-LABEL: define {{[^@]+}}@_Z3foov 1255 // CHECK1-SAME: () #[[ATTR3:[0-9]+]] { 1256 // CHECK1-NEXT: entry: 1257 // CHECK1-NEXT: call void @_Z8mayThrowv() 1258 // CHECK1-NEXT: ret i32 0 1259 // 1260 // 1261 // CHECK1-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 1262 // CHECK1-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { 1263 // CHECK1-NEXT: entry: 1264 // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1265 // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 1266 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1267 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1268 // CHECK1-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_7:%.*]], align 8 1269 // CHECK1-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1270 // CHECK1-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 1271 // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 1272 // CHECK1-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 1273 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 1274 // CHECK1-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 1275 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 1276 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 1277 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 1278 // CHECK1-NEXT: store float** [[A_ADDR]], float*** [[TMP3]], align 8 1279 // CHECK1-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 1280 // CHECK1-NEXT: store i64 [[TMP1]], i64* [[TMP4]], align 8 1281 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 1282 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 1283 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[TMP5]], align 8 1284 // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.7*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]]) 1285 // CHECK1-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1286 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) 1287 // CHECK1-NEXT: ret void 1288 // 1289 // 1290 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..8 1291 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 1292 // CHECK1-NEXT: entry: 1293 // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1294 // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1295 // CHECK1-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.7*, align 8 1296 // CHECK1-NEXT: [[N:%.*]] = alloca i32, align 4 1297 // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1298 // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 1299 // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1300 // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1301 // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1302 // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1303 // CHECK1-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 1304 // CHECK1-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 1305 // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 1306 // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1307 // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1308 // CHECK1-NEXT: store %struct.anon.7* [[__CONTEXT]], %struct.anon.7** [[__CONTEXT_ADDR]], align 8 1309 // CHECK1-NEXT: [[TMP0:%.*]] = load %struct.anon.7*, %struct.anon.7** [[__CONTEXT_ADDR]], align 8 1310 // CHECK1-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], %struct.anon.7* [[TMP0]], i32 0, i32 0 1311 // CHECK1-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 1312 // CHECK1-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 1 1313 // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 8 1314 // CHECK1-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 2 1315 // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 8 1316 // CHECK1-NEXT: store i32 [[TMP6]], i32* [[N]], align 4 1317 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1318 // CHECK1-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1319 // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1320 // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1321 // CHECK1-NEXT: [[TMP7:%.*]] = call i8* @llvm.stacksave() 1322 // CHECK1-NEXT: store i8* [[TMP7]], i8** [[SAVED_STACK]], align 8 1323 // CHECK1-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP4]], align 16 1324 // CHECK1-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR0]], align 8 1325 // CHECK1-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1326 // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 1327 // CHECK1-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1328 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1329 // CHECK1: omp.dispatch.cond: 1330 // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1331 // CHECK1-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP10]], 16908288 1332 // CHECK1-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1333 // CHECK1: cond.true: 1334 // CHECK1-NEXT: br label [[COND_END:%.*]] 1335 // CHECK1: cond.false: 1336 // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1337 // CHECK1-NEXT: br label [[COND_END]] 1338 // CHECK1: cond.end: 1339 // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 1340 // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1341 // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1342 // CHECK1-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 1343 // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1344 // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1345 // CHECK1-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP13]], [[TMP14]] 1346 // CHECK1-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 1347 // CHECK1: omp.dispatch.cleanup: 1348 // CHECK1-NEXT: br label [[OMP_DISPATCH_END:%.*]] 1349 // CHECK1: omp.dispatch.body: 1350 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1351 // CHECK1: omp.inner.for.cond: 1352 // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1353 // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1354 // CHECK1-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP15]], [[TMP16]] 1355 // CHECK1-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 1356 // CHECK1: omp.inner.for.cond.cleanup: 1357 // CHECK1-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 1358 // CHECK1: omp.inner.for.body: 1359 // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1360 // CHECK1-NEXT: [[MUL:%.*]] = mul i32 [[TMP17]], 127 1361 // CHECK1-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1362 // CHECK1-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1363 // CHECK1-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 1364 // CHECK1-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 1365 // CHECK1: invoke.cont: 1366 // CHECK1-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float 1367 // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 1368 // CHECK1-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP18]] to i64 1369 // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 [[IDXPROM]] 1370 // CHECK1-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 1371 // CHECK1-NEXT: [[ADD3:%.*]] = fadd float [[CONV]], [[TMP19]] 1372 // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[N]], align 4 1373 // CHECK1-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP20]] to float 1374 // CHECK1-NEXT: [[ADD5:%.*]] = fadd float [[ADD3]], [[CONV4]] 1375 // CHECK1-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP2]], align 8 1376 // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 1377 // CHECK1-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP22]] to i64 1378 // CHECK1-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 1379 // CHECK1-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4 1380 // CHECK1-NEXT: [[ADD8:%.*]] = fadd float [[TMP23]], [[ADD5]] 1381 // CHECK1-NEXT: store float [[ADD8]], float* [[ARRAYIDX7]], align 4 1382 // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1383 // CHECK1: omp.body.continue: 1384 // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1385 // CHECK1: omp.inner.for.inc: 1386 // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1387 // CHECK1-NEXT: [[ADD9:%.*]] = add i32 [[TMP24]], 1 1388 // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 1389 // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] 1390 // CHECK1: omp.inner.for.end: 1391 // CHECK1-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1392 // CHECK1: omp.dispatch.inc: 1393 // CHECK1-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1394 // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1395 // CHECK1-NEXT: [[ADD10:%.*]] = add i32 [[TMP25]], [[TMP26]] 1396 // CHECK1-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4 1397 // CHECK1-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1398 // CHECK1-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1399 // CHECK1-NEXT: [[ADD11:%.*]] = add i32 [[TMP27]], [[TMP28]] 1400 // CHECK1-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4 1401 // CHECK1-NEXT: br label [[OMP_DISPATCH_COND]] 1402 // CHECK1: omp.dispatch.end: 1403 // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 1404 // CHECK1-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 1405 // CHECK1-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 1406 // CHECK1-NEXT: ret void 1407 // CHECK1: terminate.lpad: 1408 // CHECK1-NEXT: [[TMP30:%.*]] = landingpad { i8*, i32 } 1409 // CHECK1-NEXT: catch i8* null 1410 // CHECK1-NEXT: [[TMP31:%.*]] = extractvalue { i8*, i32 } [[TMP30]], 0 1411 // CHECK1-NEXT: call void @__clang_call_terminate(i8* [[TMP31]]) #[[ATTR7:[0-9]+]] 1412 // CHECK1-NEXT: unreachable 1413 // 1414 // 1415 // CHECK1-LABEL: define {{[^@]+}}@__clang_call_terminate 1416 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 1417 // CHECK1-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 1418 // CHECK1-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 1419 // CHECK1-NEXT: unreachable 1420 // 1421 // 1422 // CHECK2-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 1423 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] { 1424 // CHECK2-NEXT: entry: 1425 // CHECK2-NEXT: [[A:%.*]] = alloca double, align 8 1426 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1427 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 1428 // CHECK2-NEXT: store double 5.000000e+00, double* [[A]], align 8 1429 // CHECK2-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 1430 // CHECK2-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 1431 // CHECK2-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 1432 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 1433 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1434 // CHECK2-NEXT: store i8 [[TMP2]], i8* [[TMP1]], align 1 1435 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 1436 // CHECK2-NEXT: ret void 1437 // 1438 // 1439 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. 1440 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { 1441 // CHECK2-NEXT: entry: 1442 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1443 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1444 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 1445 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 1446 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1447 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 1448 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 1449 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 1450 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 1451 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1452 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1453 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1454 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1455 // CHECK2-NEXT: [[A:%.*]] = alloca double, align 8 1456 // CHECK2-NEXT: [[I4:%.*]] = alloca i64, align 8 1457 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1458 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1459 // CHECK2-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 1460 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 1461 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 1462 // CHECK2-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 1463 // CHECK2-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 1464 // CHECK2-NEXT: [[TMP3:%.*]] = load double, double* undef, align 8 1465 // CHECK2-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 1466 // CHECK2-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 1467 // CHECK2-NEXT: [[TMP4:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 1468 // CHECK2-NEXT: [[SUB:%.*]] = fsub double [[TMP4]], 1.000000e+00 1469 // CHECK2-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 1470 // CHECK2-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i64 1471 // CHECK2-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 1 1472 // CHECK2-NEXT: store i64 [[SUB3]], i64* [[DOTCAPTURE_EXPR_2]], align 8 1473 // CHECK2-NEXT: store i64 1, i64* [[I]], align 8 1474 // CHECK2-NEXT: [[TMP5:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 1475 // CHECK2-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP5]] 1476 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 1477 // CHECK2: omp.precond.then: 1478 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1479 // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1480 // CHECK2-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_UB]], align 8 1481 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1482 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1483 // CHECK2-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 1484 // CHECK2-NEXT: [[CONV5:%.*]] = sext i8 [[TMP7]] to i64 1485 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1486 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 1487 // CHECK2-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]]) 1488 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1489 // CHECK2: omp.dispatch.cond: 1490 // CHECK2-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1491 // CHECK2-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1492 // CHECK2-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP10]], [[TMP11]] 1493 // CHECK2-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1494 // CHECK2: cond.true: 1495 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 1496 // CHECK2-NEXT: br label [[COND_END:%.*]] 1497 // CHECK2: cond.false: 1498 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1499 // CHECK2-NEXT: br label [[COND_END]] 1500 // CHECK2: cond.end: 1501 // CHECK2-NEXT: [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 1502 // CHECK2-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 1503 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1504 // CHECK2-NEXT: store i64 [[TMP14]], i64* [[DOTOMP_IV]], align 8 1505 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1506 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1507 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 1508 // CHECK2-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP15]], [[ADD7]] 1509 // CHECK2-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1510 // CHECK2: omp.dispatch.body: 1511 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1512 // CHECK2: omp.inner.for.cond: 1513 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1514 // CHECK2-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1515 // CHECK2-NEXT: [[ADD9:%.*]] = add i64 [[TMP18]], 1 1516 // CHECK2-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP17]], [[ADD9]] 1517 // CHECK2-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1518 // CHECK2: omp.inner.for.body: 1519 // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1520 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP19]], 1 1521 // CHECK2-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]] 1522 // CHECK2-NEXT: store i64 [[ADD11]], i64* [[I4]], align 8 1523 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1524 // CHECK2: omp.body.continue: 1525 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1526 // CHECK2: omp.inner.for.inc: 1527 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 1528 // CHECK2-NEXT: [[ADD12:%.*]] = add i64 [[TMP20]], 1 1529 // CHECK2-NEXT: store i64 [[ADD12]], i64* [[DOTOMP_IV]], align 8 1530 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1531 // CHECK2: omp.inner.for.end: 1532 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1533 // CHECK2: omp.dispatch.inc: 1534 // CHECK2-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1535 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 1536 // CHECK2-NEXT: [[ADD13:%.*]] = add i64 [[TMP21]], [[TMP22]] 1537 // CHECK2-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_LB]], align 8 1538 // CHECK2-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 1539 // CHECK2-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 1540 // CHECK2-NEXT: [[ADD14:%.*]] = add i64 [[TMP23]], [[TMP24]] 1541 // CHECK2-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_UB]], align 8 1542 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1543 // CHECK2: omp.dispatch.end: 1544 // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1545 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 1546 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 1547 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 1548 // CHECK2: omp.precond.end: 1549 // CHECK2-NEXT: ret void 1550 // 1551 // 1552 // CHECK2-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 1553 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1554 // CHECK2-NEXT: entry: 1555 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1556 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1557 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1558 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1559 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 1560 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1561 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1562 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1563 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1564 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 1565 // CHECK2-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 1566 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 1567 // CHECK2-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 1568 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 1569 // CHECK2-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 1570 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 1571 // CHECK2-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 1572 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]]) 1573 // CHECK2-NEXT: ret void 1574 // 1575 // 1576 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 1577 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 1578 // CHECK2-NEXT: entry: 1579 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1580 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1581 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.0*, align 8 1582 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1583 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1584 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1585 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1586 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1587 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1588 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1589 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1590 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1591 // CHECK2-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 1592 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 1593 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 1594 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 1595 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 1596 // CHECK2-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 1597 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 1598 // CHECK2-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 1599 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 3 1600 // CHECK2-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 1601 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1602 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1603 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1604 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1605 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1606 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1607 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1608 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1609 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 1610 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1611 // CHECK2: cond.true: 1612 // CHECK2-NEXT: br label [[COND_END:%.*]] 1613 // CHECK2: cond.false: 1614 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1615 // CHECK2-NEXT: br label [[COND_END]] 1616 // CHECK2: cond.end: 1617 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1618 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1619 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1620 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1621 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1622 // CHECK2: omp.inner.for.cond: 1623 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1624 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1625 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1626 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1627 // CHECK2: omp.inner.for.body: 1628 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1629 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 1630 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 1631 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1632 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 1633 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 1634 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 1635 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 1636 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 1637 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 1638 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 1639 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 1640 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 1641 // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1642 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 1643 // CHECK2-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 1644 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 1645 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 1646 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 1647 // CHECK2-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1648 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 1649 // CHECK2-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 1650 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 1651 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 1652 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 1653 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1654 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1655 // CHECK2: omp.body.continue: 1656 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1657 // CHECK2: omp.inner.for.inc: 1658 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1659 // CHECK2-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP28]], 1 1660 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 1661 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1662 // CHECK2: omp.inner.for.end: 1663 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1664 // CHECK2: omp.loop.exit: 1665 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 1666 // CHECK2-NEXT: ret void 1667 // 1668 // 1669 // CHECK2-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 1670 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1671 // CHECK2-NEXT: entry: 1672 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1673 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1674 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1675 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1676 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 1677 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1678 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1679 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1680 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1681 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 1682 // CHECK2-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 1683 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 1684 // CHECK2-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 1685 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 1686 // CHECK2-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 1687 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 1688 // CHECK2-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 1689 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.1*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]]) 1690 // CHECK2-NEXT: ret void 1691 // 1692 // 1693 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 1694 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 1695 // CHECK2-NEXT: entry: 1696 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1697 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1698 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.1*, align 8 1699 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1700 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1701 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1702 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1703 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1704 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1705 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1706 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1707 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1708 // CHECK2-NEXT: store %struct.anon.1* [[__CONTEXT]], %struct.anon.1** [[__CONTEXT_ADDR]], align 8 1709 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR]], align 8 1710 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP0]], i32 0, i32 0 1711 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 1712 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 1 1713 // CHECK2-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 1714 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 2 1715 // CHECK2-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 1716 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 3 1717 // CHECK2-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 1718 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1719 // CHECK2-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 1720 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1721 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1722 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1723 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1724 // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 1725 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1726 // CHECK2-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 1727 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1728 // CHECK2: cond.true: 1729 // CHECK2-NEXT: br label [[COND_END:%.*]] 1730 // CHECK2: cond.false: 1731 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1732 // CHECK2-NEXT: br label [[COND_END]] 1733 // CHECK2: cond.end: 1734 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1735 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1736 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1737 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1738 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1739 // CHECK2: omp.inner.for.cond: 1740 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1741 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1742 // CHECK2-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 1743 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1744 // CHECK2: omp.inner.for.body: 1745 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1746 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 1747 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 1748 // CHECK2-NEXT: store i32 [[SUB]], i32* [[I]], align 4 1749 // CHECK2-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 1750 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 1751 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 1752 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 1753 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 1754 // CHECK2-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 1755 // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 1756 // CHECK2-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 1757 // CHECK2-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 1758 // CHECK2-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 1759 // CHECK2-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 1760 // CHECK2-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 1761 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 1762 // CHECK2-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 1763 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 1764 // CHECK2-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 1765 // CHECK2-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 1766 // CHECK2-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 1767 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 1768 // CHECK2-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 1769 // CHECK2-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 1770 // CHECK2-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 1771 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1772 // CHECK2: omp.body.continue: 1773 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1774 // CHECK2: omp.inner.for.inc: 1775 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1776 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP28]], 1 1777 // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 1778 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1779 // CHECK2: omp.inner.for.end: 1780 // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 1781 // CHECK2: omp.loop.exit: 1782 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 1783 // CHECK2-NEXT: ret void 1784 // 1785 // 1786 // CHECK2-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 1787 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1788 // CHECK2-NEXT: entry: 1789 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1790 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1791 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1792 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1793 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8 1794 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1795 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1796 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1797 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1798 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 1799 // CHECK2-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 1800 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 1801 // CHECK2-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 1802 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 1803 // CHECK2-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 1804 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 1805 // CHECK2-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 1806 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.2*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]]) 1807 // CHECK2-NEXT: ret void 1808 // 1809 // 1810 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 1811 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 1812 // CHECK2-NEXT: entry: 1813 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1814 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1815 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.2*, align 8 1816 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 1817 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 1818 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 1819 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 1820 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 1821 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1822 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 1823 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1824 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1825 // CHECK2-NEXT: store %struct.anon.2* [[__CONTEXT]], %struct.anon.2** [[__CONTEXT_ADDR]], align 8 1826 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR]], align 8 1827 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], %struct.anon.2* [[TMP0]], i32 0, i32 0 1828 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 1829 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 1 1830 // CHECK2-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 1831 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 2 1832 // CHECK2-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 1833 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 3 1834 // CHECK2-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 1835 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 1836 // CHECK2-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 1837 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 1838 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1839 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1840 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1841 // CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 1842 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1843 // CHECK2: omp.dispatch.cond: 1844 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1845 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP11]], 16908288 1846 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 1847 // CHECK2: cond.true: 1848 // CHECK2-NEXT: br label [[COND_END:%.*]] 1849 // CHECK2: cond.false: 1850 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1851 // CHECK2-NEXT: br label [[COND_END]] 1852 // CHECK2: cond.end: 1853 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 1854 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 1855 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1856 // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 1857 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1858 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1859 // CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]] 1860 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1861 // CHECK2: omp.dispatch.body: 1862 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1863 // CHECK2: omp.inner.for.cond: 1864 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1865 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1866 // CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP16]], [[TMP17]] 1867 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1868 // CHECK2: omp.inner.for.body: 1869 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1870 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP18]], 127 1871 // CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 1872 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 1873 // CHECK2-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP4]], align 8 1874 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 1875 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP20]] to i64 1876 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM]] 1877 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 1878 // CHECK2-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP6]], align 8 1879 // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 1880 // CHECK2-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP23]] to i64 1881 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM3]] 1882 // CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4 1883 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[TMP21]], [[TMP24]] 1884 // CHECK2-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP8]], align 8 1885 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 1886 // CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP26]] to i64 1887 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[IDXPROM6]] 1888 // CHECK2-NEXT: [[TMP27:%.*]] = load float, float* [[ARRAYIDX7]], align 4 1889 // CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP27]] 1890 // CHECK2-NEXT: [[TMP28:%.*]] = load float*, float** [[TMP2]], align 8 1891 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[I]], align 4 1892 // CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP29]] to i64 1893 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP28]], i64 [[IDXPROM9]] 1894 // CHECK2-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 1895 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 1896 // CHECK2: omp.body.continue: 1897 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 1898 // CHECK2: omp.inner.for.inc: 1899 // CHECK2-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 1900 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP30]], 1 1901 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 1902 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 1903 // CHECK2: omp.inner.for.end: 1904 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 1905 // CHECK2: omp.dispatch.inc: 1906 // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 1907 // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1908 // CHECK2-NEXT: [[ADD12:%.*]] = add i32 [[TMP31]], [[TMP32]] 1909 // CHECK2-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 1910 // CHECK2-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 1911 // CHECK2-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 1912 // CHECK2-NEXT: [[ADD13:%.*]] = add i32 [[TMP33]], [[TMP34]] 1913 // CHECK2-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 1914 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 1915 // CHECK2: omp.dispatch.end: 1916 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 1917 // CHECK2-NEXT: ret void 1918 // 1919 // 1920 // CHECK2-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 1921 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 1922 // CHECK2-NEXT: entry: 1923 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 1924 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 1925 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 1926 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 1927 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 8 1928 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 1929 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 1930 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 1931 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 1932 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 1933 // CHECK2-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 1934 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 1935 // CHECK2-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 1936 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 1937 // CHECK2-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 1938 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 1939 // CHECK2-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 1940 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.3*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]]) 1941 // CHECK2-NEXT: ret void 1942 // 1943 // 1944 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..4 1945 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 1946 // CHECK2-NEXT: entry: 1947 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 1948 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 1949 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.3*, align 8 1950 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 1951 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 1952 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 1953 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 1954 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 1955 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 1956 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 1957 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 1958 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 1959 // CHECK2-NEXT: store %struct.anon.3* [[__CONTEXT]], %struct.anon.3** [[__CONTEXT_ADDR]], align 8 1960 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon.3*, %struct.anon.3** [[__CONTEXT_ADDR]], align 8 1961 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], %struct.anon.3* [[TMP0]], i32 0, i32 0 1962 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 1963 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 1 1964 // CHECK2-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 1965 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 2 1966 // CHECK2-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 1967 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 3 1968 // CHECK2-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 1969 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 1970 // CHECK2-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 1971 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 1972 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 1973 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 1974 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 1975 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 35, i64 0, i64 16908287, i64 1, i64 1) 1976 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 1977 // CHECK2: omp.dispatch.cond: 1978 // CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 1979 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 1980 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 1981 // CHECK2: omp.dispatch.body: 1982 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 1983 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 1984 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 1985 // CHECK2: omp.inner.for.cond: 1986 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1987 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 1988 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 1989 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 1990 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 1991 // CHECK2: omp.inner.for.body: 1992 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 1993 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 1994 // CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 1995 // CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5 1996 // CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !5 1997 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 1998 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 1999 // CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !5 2000 // CHECK2-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !5 2001 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 2002 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 2003 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !5 2004 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 2005 // CHECK2-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !5 2006 // CHECK2-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 2007 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 2008 // CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !5 2009 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 2010 // CHECK2-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !5 2011 // CHECK2-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 2012 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 2013 // CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5 2014 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2015 // CHECK2: omp.body.continue: 2016 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2017 // CHECK2: omp.inner.for.inc: 2018 // CHECK2-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 2019 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 2020 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 2021 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 2022 // CHECK2: omp.inner.for.end: 2023 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2024 // CHECK2: omp.dispatch.inc: 2025 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2026 // CHECK2: omp.dispatch.end: 2027 // CHECK2-NEXT: ret void 2028 // 2029 // 2030 // CHECK2-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 2031 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2032 // CHECK2-NEXT: entry: 2033 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2034 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2035 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2036 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2037 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8 2038 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2039 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2040 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2041 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2042 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 2043 // CHECK2-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 2044 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 2045 // CHECK2-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 2046 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 2047 // CHECK2-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 2048 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 2049 // CHECK2-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 2050 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.4*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]]) 2051 // CHECK2-NEXT: ret void 2052 // 2053 // 2054 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..5 2055 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 2056 // CHECK2-NEXT: entry: 2057 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2058 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2059 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.4*, align 8 2060 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2061 // CHECK2-NEXT: [[TMP:%.*]] = alloca i64, align 8 2062 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2063 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2064 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2065 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2066 // CHECK2-NEXT: [[I:%.*]] = alloca i64, align 8 2067 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2068 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2069 // CHECK2-NEXT: store %struct.anon.4* [[__CONTEXT]], %struct.anon.4** [[__CONTEXT_ADDR]], align 8 2070 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR]], align 8 2071 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], %struct.anon.4* [[TMP0]], i32 0, i32 0 2072 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 2073 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 1 2074 // CHECK2-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 2075 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 2 2076 // CHECK2-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 2077 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 3 2078 // CHECK2-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 2079 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2080 // CHECK2-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 2081 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2082 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2083 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2084 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2085 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 36, i64 0, i64 16908287, i64 1, i64 7) 2086 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2087 // CHECK2: omp.dispatch.cond: 2088 // CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2089 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 2090 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2091 // CHECK2: omp.dispatch.body: 2092 // CHECK2-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2093 // CHECK2-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 2094 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2095 // CHECK2: omp.inner.for.cond: 2096 // CHECK2-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 2097 // CHECK2-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !8 2098 // CHECK2-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 2099 // CHECK2-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 2100 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2101 // CHECK2: omp.inner.for.body: 2102 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 2103 // CHECK2-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 2104 // CHECK2-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 2105 // CHECK2-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8 2106 // CHECK2-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !8 2107 // CHECK2-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 2108 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 2109 // CHECK2-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 2110 // CHECK2-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !8 2111 // CHECK2-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 2112 // CHECK2-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 2113 // CHECK2-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !8 2114 // CHECK2-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 2115 // CHECK2-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !8 2116 // CHECK2-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 2117 // CHECK2-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 2118 // CHECK2-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !8 2119 // CHECK2-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 2120 // CHECK2-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 2121 // CHECK2-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 2122 // CHECK2-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 2123 // CHECK2-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 2124 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2125 // CHECK2: omp.body.continue: 2126 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2127 // CHECK2: omp.inner.for.inc: 2128 // CHECK2-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 2129 // CHECK2-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 2130 // CHECK2-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 2131 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 2132 // CHECK2: omp.inner.for.end: 2133 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2134 // CHECK2: omp.dispatch.inc: 2135 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2136 // CHECK2: omp.dispatch.end: 2137 // CHECK2-NEXT: ret void 2138 // 2139 // 2140 // CHECK2-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 2141 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2142 // CHECK2-NEXT: entry: 2143 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2144 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2145 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2146 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2147 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2148 // CHECK2-NEXT: [[Y:%.*]] = alloca i32, align 4 2149 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_5:%.*]], align 8 2150 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2151 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2152 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2153 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2154 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 2155 // CHECK2-NEXT: store i32 0, i32* [[Y]], align 4 2156 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 2157 // CHECK2-NEXT: store i32* [[Y]], i32** [[TMP0]], align 8 2158 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 2159 // CHECK2-NEXT: store float** [[A_ADDR]], float*** [[TMP1]], align 8 2160 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 2161 // CHECK2-NEXT: store float** [[B_ADDR]], float*** [[TMP2]], align 8 2162 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 2163 // CHECK2-NEXT: store float** [[C_ADDR]], float*** [[TMP3]], align 8 2164 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 4 2165 // CHECK2-NEXT: store float** [[D_ADDR]], float*** [[TMP4]], align 8 2166 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.5*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]) 2167 // CHECK2-NEXT: ret void 2168 // 2169 // 2170 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..6 2171 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 2172 // CHECK2-NEXT: entry: 2173 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2174 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2175 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.5*, align 8 2176 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2177 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 2178 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2179 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2180 // CHECK2-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2181 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 2182 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2183 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2184 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2185 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2186 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2187 // CHECK2-NEXT: [[I7:%.*]] = alloca i8, align 1 2188 // CHECK2-NEXT: [[X8:%.*]] = alloca i32, align 4 2189 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2190 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2191 // CHECK2-NEXT: store %struct.anon.5* [[__CONTEXT]], %struct.anon.5** [[__CONTEXT_ADDR]], align 8 2192 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon.5*, %struct.anon.5** [[__CONTEXT_ADDR]], align 8 2193 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], %struct.anon.5* [[TMP0]], i32 0, i32 0 2194 // CHECK2-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 2195 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 1 2196 // CHECK2-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 2197 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 2 2198 // CHECK2-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 2199 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 3 2200 // CHECK2-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 2201 // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 4 2202 // CHECK2-NEXT: [[TMP10:%.*]] = load float**, float*** [[TMP9]], align 8 2203 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP2]], align 4 2204 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[TMP11]] to i8 2205 // CHECK2-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 2206 // CHECK2-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2207 // CHECK2-NEXT: [[CONV3:%.*]] = sext i8 [[TMP12]] to i32 2208 // CHECK2-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 2209 // CHECK2-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 2210 // CHECK2-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 2211 // CHECK2-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 2212 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 2213 // CHECK2-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 2214 // CHECK2-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 2215 // CHECK2-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2216 // CHECK2-NEXT: store i8 [[TMP13]], i8* [[I]], align 1 2217 // CHECK2-NEXT: store i32 11, i32* [[X]], align 4 2218 // CHECK2-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2219 // CHECK2-NEXT: [[CONV6:%.*]] = sext i8 [[TMP14]] to i32 2220 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 2221 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2222 // CHECK2: omp.precond.then: 2223 // CHECK2-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2224 // CHECK2-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2225 // CHECK2-NEXT: store i64 [[TMP15]], i64* [[DOTOMP_UB]], align 8 2226 // CHECK2-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2227 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2228 // CHECK2-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2229 // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2230 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 2231 // CHECK2-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], i32 38, i64 0, i64 [[TMP16]], i64 1, i64 1) 2232 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2233 // CHECK2: omp.dispatch.cond: 2234 // CHECK2-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2235 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 2236 // CHECK2-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP20]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 2237 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP21]], 0 2238 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2239 // CHECK2: omp.dispatch.body: 2240 // CHECK2-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2241 // CHECK2-NEXT: store i64 [[TMP22]], i64* [[DOTOMP_IV]], align 8 2242 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2243 // CHECK2: omp.inner.for.cond: 2244 // CHECK2-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2245 // CHECK2-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !11 2246 // CHECK2-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP23]], [[TMP24]] 2247 // CHECK2-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2248 // CHECK2: omp.inner.for.body: 2249 // CHECK2-NEXT: [[TMP25:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11 2250 // CHECK2-NEXT: [[CONV10:%.*]] = sext i8 [[TMP25]] to i64 2251 // CHECK2-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2252 // CHECK2-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP26]], 11 2253 // CHECK2-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 2254 // CHECK2-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 2255 // CHECK2-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 2256 // CHECK2-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11 2257 // CHECK2-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2258 // CHECK2-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2259 // CHECK2-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP28]], 11 2260 // CHECK2-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 2261 // CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP27]], [[MUL16]] 2262 // CHECK2-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 2263 // CHECK2-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 2264 // CHECK2-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 2265 // CHECK2-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11 2266 // CHECK2-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !11 2267 // CHECK2-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 2268 // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP30]] to i64 2269 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM]] 2270 // CHECK2-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 2271 // CHECK2-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !11 2272 // CHECK2-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 2273 // CHECK2-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP33]] to i64 2274 // CHECK2-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM21]] 2275 // CHECK2-NEXT: [[TMP34:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !11 2276 // CHECK2-NEXT: [[MUL23:%.*]] = fmul float [[TMP31]], [[TMP34]] 2277 // CHECK2-NEXT: [[TMP35:%.*]] = load float*, float** [[TMP10]], align 8, !llvm.access.group !11 2278 // CHECK2-NEXT: [[TMP36:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 2279 // CHECK2-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP36]] to i64 2280 // CHECK2-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP35]], i64 [[IDXPROM24]] 2281 // CHECK2-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !11 2282 // CHECK2-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP37]] 2283 // CHECK2-NEXT: [[TMP38:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !11 2284 // CHECK2-NEXT: [[TMP39:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 2285 // CHECK2-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP39]] to i64 2286 // CHECK2-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP38]], i64 [[IDXPROM27]] 2287 // CHECK2-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11 2288 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2289 // CHECK2: omp.body.continue: 2290 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2291 // CHECK2: omp.inner.for.inc: 2292 // CHECK2-NEXT: [[TMP40:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2293 // CHECK2-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP40]], 1 2294 // CHECK2-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 2295 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 2296 // CHECK2: omp.inner.for.end: 2297 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2298 // CHECK2: omp.dispatch.inc: 2299 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2300 // CHECK2: omp.dispatch.end: 2301 // CHECK2-NEXT: br label [[OMP_PRECOND_END]] 2302 // CHECK2: omp.precond.end: 2303 // CHECK2-NEXT: ret void 2304 // 2305 // 2306 // CHECK2-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 2307 // CHECK2-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2308 // CHECK2-NEXT: entry: 2309 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2310 // CHECK2-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2311 // CHECK2-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2312 // CHECK2-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2313 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2314 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 8 2315 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2316 // CHECK2-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2317 // CHECK2-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2318 // CHECK2-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2319 // CHECK2-NEXT: store i32 0, i32* [[X]], align 4 2320 // CHECK2-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 2321 // CHECK2-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 2322 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 2323 // CHECK2-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 2324 // CHECK2-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 2325 // CHECK2-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 2326 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 2327 // CHECK2-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 2328 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.6*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]]) 2329 // CHECK2-NEXT: ret void 2330 // 2331 // 2332 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..7 2333 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 2334 // CHECK2-NEXT: entry: 2335 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2336 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2337 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.6*, align 8 2338 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2339 // CHECK2-NEXT: [[TMP:%.*]] = alloca i8, align 1 2340 // CHECK2-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 2341 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2342 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2343 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2344 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2345 // CHECK2-NEXT: [[I:%.*]] = alloca i8, align 1 2346 // CHECK2-NEXT: [[X:%.*]] = alloca i32, align 4 2347 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2348 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2349 // CHECK2-NEXT: store %struct.anon.6* [[__CONTEXT]], %struct.anon.6** [[__CONTEXT_ADDR]], align 8 2350 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR]], align 8 2351 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], %struct.anon.6* [[TMP0]], i32 0, i32 0 2352 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 2353 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 1 2354 // CHECK2-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 2355 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 2 2356 // CHECK2-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 2357 // CHECK2-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 3 2358 // CHECK2-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 2359 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2360 // CHECK2-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 2361 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2362 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2363 // CHECK2-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2364 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2365 // CHECK2-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 37, i32 0, i32 199, i32 1, i32 1) 2366 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2367 // CHECK2: omp.dispatch.cond: 2368 // CHECK2-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 2369 // CHECK2-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 2370 // CHECK2-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2371 // CHECK2: omp.dispatch.body: 2372 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2373 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2374 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2375 // CHECK2: omp.inner.for.cond: 2376 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2377 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 2378 // CHECK2-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 2379 // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2380 // CHECK2: omp.inner.for.body: 2381 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2382 // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP15]], 20 2383 // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 2384 // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 2385 // CHECK2-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 2386 // CHECK2-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14 2387 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2388 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2389 // CHECK2-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP17]], 20 2390 // CHECK2-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 2391 // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP16]], [[MUL3]] 2392 // CHECK2-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 2393 // CHECK2-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 2394 // CHECK2-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14 2395 // CHECK2-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !14 2396 // CHECK2-NEXT: [[TMP19:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 2397 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP19]] to i64 2398 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM]] 2399 // CHECK2-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 2400 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !14 2401 // CHECK2-NEXT: [[TMP22:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 2402 // CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP22]] to i64 2403 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 2404 // CHECK2-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !14 2405 // CHECK2-NEXT: [[MUL8:%.*]] = fmul float [[TMP20]], [[TMP23]] 2406 // CHECK2-NEXT: [[TMP24:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !14 2407 // CHECK2-NEXT: [[TMP25:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 2408 // CHECK2-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP25]] to i64 2409 // CHECK2-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM9]] 2410 // CHECK2-NEXT: [[TMP26:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 2411 // CHECK2-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP26]] 2412 // CHECK2-NEXT: [[TMP27:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !14 2413 // CHECK2-NEXT: [[TMP28:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 2414 // CHECK2-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP28]] to i64 2415 // CHECK2-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP27]], i64 [[IDXPROM12]] 2416 // CHECK2-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14 2417 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2418 // CHECK2: omp.body.continue: 2419 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2420 // CHECK2: omp.inner.for.inc: 2421 // CHECK2-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2422 // CHECK2-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP29]], 1 2423 // CHECK2-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 2424 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 2425 // CHECK2: omp.inner.for.end: 2426 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2427 // CHECK2: omp.dispatch.inc: 2428 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2429 // CHECK2: omp.dispatch.end: 2430 // CHECK2-NEXT: ret void 2431 // 2432 // 2433 // CHECK2-LABEL: define {{[^@]+}}@_Z3foov 2434 // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { 2435 // CHECK2-NEXT: entry: 2436 // CHECK2-NEXT: call void @_Z8mayThrowv() 2437 // CHECK2-NEXT: ret i32 0 2438 // 2439 // 2440 // CHECK2-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 2441 // CHECK2-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { 2442 // CHECK2-NEXT: entry: 2443 // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2444 // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 2445 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2446 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2447 // CHECK2-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_7:%.*]], align 8 2448 // CHECK2-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2449 // CHECK2-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 2450 // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 2451 // CHECK2-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 2452 // CHECK2-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 2453 // CHECK2-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 2454 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 2455 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 2456 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 2457 // CHECK2-NEXT: store float** [[A_ADDR]], float*** [[TMP3]], align 8 2458 // CHECK2-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 2459 // CHECK2-NEXT: store i64 [[TMP1]], i64* [[TMP4]], align 8 2460 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 2461 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 2462 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[TMP5]], align 8 2463 // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.7*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]]) 2464 // CHECK2-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2465 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) 2466 // CHECK2-NEXT: ret void 2467 // 2468 // 2469 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..8 2470 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 2471 // CHECK2-NEXT: entry: 2472 // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2473 // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2474 // CHECK2-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.7*, align 8 2475 // CHECK2-NEXT: [[N:%.*]] = alloca i32, align 4 2476 // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2477 // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 2478 // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2479 // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2480 // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2481 // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2482 // CHECK2-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 2483 // CHECK2-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 2484 // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 2485 // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2486 // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2487 // CHECK2-NEXT: store %struct.anon.7* [[__CONTEXT]], %struct.anon.7** [[__CONTEXT_ADDR]], align 8 2488 // CHECK2-NEXT: [[TMP0:%.*]] = load %struct.anon.7*, %struct.anon.7** [[__CONTEXT_ADDR]], align 8 2489 // CHECK2-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], %struct.anon.7* [[TMP0]], i32 0, i32 0 2490 // CHECK2-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 2491 // CHECK2-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 1 2492 // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 8 2493 // CHECK2-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 2 2494 // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 8 2495 // CHECK2-NEXT: store i32 [[TMP6]], i32* [[N]], align 4 2496 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2497 // CHECK2-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 2498 // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2499 // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2500 // CHECK2-NEXT: [[TMP7:%.*]] = call i8* @llvm.stacksave() 2501 // CHECK2-NEXT: store i8* [[TMP7]], i8** [[SAVED_STACK]], align 8 2502 // CHECK2-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP4]], align 16 2503 // CHECK2-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR0]], align 8 2504 // CHECK2-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2505 // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 2506 // CHECK2-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 2507 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2508 // CHECK2: omp.dispatch.cond: 2509 // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2510 // CHECK2-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP10]], 16908288 2511 // CHECK2-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2512 // CHECK2: cond.true: 2513 // CHECK2-NEXT: br label [[COND_END:%.*]] 2514 // CHECK2: cond.false: 2515 // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2516 // CHECK2-NEXT: br label [[COND_END]] 2517 // CHECK2: cond.end: 2518 // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 2519 // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2520 // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2521 // CHECK2-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 2522 // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2523 // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2524 // CHECK2-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP13]], [[TMP14]] 2525 // CHECK2-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 2526 // CHECK2: omp.dispatch.cleanup: 2527 // CHECK2-NEXT: br label [[OMP_DISPATCH_END:%.*]] 2528 // CHECK2: omp.dispatch.body: 2529 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2530 // CHECK2: omp.inner.for.cond: 2531 // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2532 // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2533 // CHECK2-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP15]], [[TMP16]] 2534 // CHECK2-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 2535 // CHECK2: omp.inner.for.cond.cleanup: 2536 // CHECK2-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 2537 // CHECK2: omp.inner.for.body: 2538 // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2539 // CHECK2-NEXT: [[MUL:%.*]] = mul i32 [[TMP17]], 127 2540 // CHECK2-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 2541 // CHECK2-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2542 // CHECK2-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 2543 // CHECK2-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 2544 // CHECK2: invoke.cont: 2545 // CHECK2-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float 2546 // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 2547 // CHECK2-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP18]] to i64 2548 // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 [[IDXPROM]] 2549 // CHECK2-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 2550 // CHECK2-NEXT: [[ADD3:%.*]] = fadd float [[CONV]], [[TMP19]] 2551 // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[N]], align 4 2552 // CHECK2-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP20]] to float 2553 // CHECK2-NEXT: [[ADD5:%.*]] = fadd float [[ADD3]], [[CONV4]] 2554 // CHECK2-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP2]], align 8 2555 // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 2556 // CHECK2-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP22]] to i64 2557 // CHECK2-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 2558 // CHECK2-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4 2559 // CHECK2-NEXT: [[ADD8:%.*]] = fadd float [[TMP23]], [[ADD5]] 2560 // CHECK2-NEXT: store float [[ADD8]], float* [[ARRAYIDX7]], align 4 2561 // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2562 // CHECK2: omp.body.continue: 2563 // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2564 // CHECK2: omp.inner.for.inc: 2565 // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2566 // CHECK2-NEXT: [[ADD9:%.*]] = add i32 [[TMP24]], 1 2567 // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 2568 // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] 2569 // CHECK2: omp.inner.for.end: 2570 // CHECK2-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2571 // CHECK2: omp.dispatch.inc: 2572 // CHECK2-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2573 // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2574 // CHECK2-NEXT: [[ADD10:%.*]] = add i32 [[TMP25]], [[TMP26]] 2575 // CHECK2-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4 2576 // CHECK2-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2577 // CHECK2-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 2578 // CHECK2-NEXT: [[ADD11:%.*]] = add i32 [[TMP27]], [[TMP28]] 2579 // CHECK2-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4 2580 // CHECK2-NEXT: br label [[OMP_DISPATCH_COND]] 2581 // CHECK2: omp.dispatch.end: 2582 // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 2583 // CHECK2-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 2584 // CHECK2-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 2585 // CHECK2-NEXT: ret void 2586 // CHECK2: terminate.lpad: 2587 // CHECK2-NEXT: [[TMP30:%.*]] = landingpad { i8*, i32 } 2588 // CHECK2-NEXT: catch i8* null 2589 // CHECK2-NEXT: [[TMP31:%.*]] = extractvalue { i8*, i32 } [[TMP30]], 0 2590 // CHECK2-NEXT: call void @__clang_call_terminate(i8* [[TMP31]]) #[[ATTR7:[0-9]+]] 2591 // CHECK2-NEXT: unreachable 2592 // 2593 // 2594 // CHECK2-LABEL: define {{[^@]+}}@__clang_call_terminate 2595 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 2596 // CHECK2-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 2597 // CHECK2-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 2598 // CHECK2-NEXT: unreachable 2599 // 2600 // 2601 // CHECK3-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 2602 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] { 2603 // CHECK3-NEXT: entry: 2604 // CHECK3-NEXT: [[A:%.*]] = alloca double, align 8 2605 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2606 // CHECK3-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 2607 // CHECK3-NEXT: store double 5.000000e+00, double* [[A]], align 8 2608 // CHECK3-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 2609 // CHECK3-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 2610 // CHECK3-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 2611 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 2612 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2613 // CHECK3-NEXT: store i8 [[TMP2]], i8* [[TMP1]], align 1 2614 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 2615 // CHECK3-NEXT: ret void 2616 // 2617 // 2618 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. 2619 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { 2620 // CHECK3-NEXT: entry: 2621 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2622 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2623 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 2624 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 2625 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 2626 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 8 2627 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 2628 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 2629 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 2630 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 2631 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 2632 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 2633 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2634 // CHECK3-NEXT: [[A:%.*]] = alloca double, align 8 2635 // CHECK3-NEXT: [[I4:%.*]] = alloca i64, align 8 2636 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2637 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2638 // CHECK3-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 2639 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 2640 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 2641 // CHECK3-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 2642 // CHECK3-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 2643 // CHECK3-NEXT: [[TMP3:%.*]] = load double, double* undef, align 8 2644 // CHECK3-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 2645 // CHECK3-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 2646 // CHECK3-NEXT: [[TMP4:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 2647 // CHECK3-NEXT: [[SUB:%.*]] = fsub double [[TMP4]], 1.000000e+00 2648 // CHECK3-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 2649 // CHECK3-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i64 2650 // CHECK3-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 1 2651 // CHECK3-NEXT: store i64 [[SUB3]], i64* [[DOTCAPTURE_EXPR_2]], align 8 2652 // CHECK3-NEXT: store i64 1, i64* [[I]], align 8 2653 // CHECK3-NEXT: [[TMP5:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 2654 // CHECK3-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP5]] 2655 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 2656 // CHECK3: omp.precond.then: 2657 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 2658 // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2659 // CHECK3-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_UB]], align 8 2660 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 2661 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2662 // CHECK3-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 2663 // CHECK3-NEXT: [[CONV5:%.*]] = sext i8 [[TMP7]] to i64 2664 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2665 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 2666 // CHECK3-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]]) 2667 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 2668 // CHECK3: omp.dispatch.cond: 2669 // CHECK3-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2670 // CHECK3-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2671 // CHECK3-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP10]], [[TMP11]] 2672 // CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2673 // CHECK3: cond.true: 2674 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 2675 // CHECK3-NEXT: br label [[COND_END:%.*]] 2676 // CHECK3: cond.false: 2677 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2678 // CHECK3-NEXT: br label [[COND_END]] 2679 // CHECK3: cond.end: 2680 // CHECK3-NEXT: [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 2681 // CHECK3-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 2682 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2683 // CHECK3-NEXT: store i64 [[TMP14]], i64* [[DOTOMP_IV]], align 8 2684 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2685 // CHECK3-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2686 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 2687 // CHECK3-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP15]], [[ADD7]] 2688 // CHECK3-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 2689 // CHECK3: omp.dispatch.body: 2690 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2691 // CHECK3: omp.inner.for.cond: 2692 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2693 // CHECK3-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2694 // CHECK3-NEXT: [[ADD9:%.*]] = add i64 [[TMP18]], 1 2695 // CHECK3-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP17]], [[ADD9]] 2696 // CHECK3-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2697 // CHECK3: omp.inner.for.body: 2698 // CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2699 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP19]], 1 2700 // CHECK3-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]] 2701 // CHECK3-NEXT: store i64 [[ADD11]], i64* [[I4]], align 8 2702 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2703 // CHECK3: omp.body.continue: 2704 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2705 // CHECK3: omp.inner.for.inc: 2706 // CHECK3-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 2707 // CHECK3-NEXT: [[ADD12:%.*]] = add i64 [[TMP20]], 1 2708 // CHECK3-NEXT: store i64 [[ADD12]], i64* [[DOTOMP_IV]], align 8 2709 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2710 // CHECK3: omp.inner.for.end: 2711 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 2712 // CHECK3: omp.dispatch.inc: 2713 // CHECK3-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 2714 // CHECK3-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 2715 // CHECK3-NEXT: [[ADD13:%.*]] = add i64 [[TMP21]], [[TMP22]] 2716 // CHECK3-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_LB]], align 8 2717 // CHECK3-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 2718 // CHECK3-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 2719 // CHECK3-NEXT: [[ADD14:%.*]] = add i64 [[TMP23]], [[TMP24]] 2720 // CHECK3-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_UB]], align 8 2721 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 2722 // CHECK3: omp.dispatch.end: 2723 // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2724 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 2725 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 2726 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 2727 // CHECK3: omp.precond.end: 2728 // CHECK3-NEXT: ret void 2729 // 2730 // 2731 // CHECK3-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 2732 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2733 // CHECK3-NEXT: entry: 2734 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2735 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2736 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2737 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2738 // CHECK3-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 2739 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2740 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2741 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2742 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2743 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 2744 // CHECK3-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 2745 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 2746 // CHECK3-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 2747 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 2748 // CHECK3-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 2749 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 2750 // CHECK3-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 2751 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]]) 2752 // CHECK3-NEXT: ret void 2753 // 2754 // 2755 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 2756 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 2757 // CHECK3-NEXT: entry: 2758 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2759 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2760 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.0*, align 8 2761 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2762 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2763 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2764 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2765 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2766 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2767 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2768 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2769 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2770 // CHECK3-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 2771 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 2772 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 2773 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 2774 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 2775 // CHECK3-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 2776 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 2777 // CHECK3-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 2778 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 3 2779 // CHECK3-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 2780 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2781 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2782 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2783 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2784 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2785 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2786 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2787 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2788 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 2789 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2790 // CHECK3: cond.true: 2791 // CHECK3-NEXT: br label [[COND_END:%.*]] 2792 // CHECK3: cond.false: 2793 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2794 // CHECK3-NEXT: br label [[COND_END]] 2795 // CHECK3: cond.end: 2796 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2797 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2798 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2799 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2800 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2801 // CHECK3: omp.inner.for.cond: 2802 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2803 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2804 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2805 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2806 // CHECK3: omp.inner.for.body: 2807 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2808 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 2809 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 2810 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 2811 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 2812 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 2813 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 2814 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 2815 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 2816 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 2817 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 2818 // CHECK3-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 2819 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 2820 // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 2821 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 2822 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 2823 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 2824 // CHECK3-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 2825 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 2826 // CHECK3-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2827 // CHECK3-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 2828 // CHECK3-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 2829 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 2830 // CHECK3-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 2831 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 2832 // CHECK3-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 2833 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2834 // CHECK3: omp.body.continue: 2835 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2836 // CHECK3: omp.inner.for.inc: 2837 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2838 // CHECK3-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP28]], 1 2839 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 2840 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2841 // CHECK3: omp.inner.for.end: 2842 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2843 // CHECK3: omp.loop.exit: 2844 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 2845 // CHECK3-NEXT: ret void 2846 // 2847 // 2848 // CHECK3-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 2849 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2850 // CHECK3-NEXT: entry: 2851 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2852 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2853 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2854 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2855 // CHECK3-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 2856 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2857 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2858 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2859 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2860 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 2861 // CHECK3-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 2862 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 2863 // CHECK3-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 2864 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 2865 // CHECK3-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 2866 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 2867 // CHECK3-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 2868 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.1*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]]) 2869 // CHECK3-NEXT: ret void 2870 // 2871 // 2872 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 2873 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 2874 // CHECK3-NEXT: entry: 2875 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2876 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2877 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.1*, align 8 2878 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2879 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2880 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2881 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2882 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 2883 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 2884 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 2885 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 2886 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 2887 // CHECK3-NEXT: store %struct.anon.1* [[__CONTEXT]], %struct.anon.1** [[__CONTEXT_ADDR]], align 8 2888 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR]], align 8 2889 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP0]], i32 0, i32 0 2890 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 2891 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 1 2892 // CHECK3-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 2893 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 2 2894 // CHECK3-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 2895 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 3 2896 // CHECK3-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 2897 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 2898 // CHECK3-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 2899 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 2900 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 2901 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 2902 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 2903 // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 2904 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2905 // CHECK3-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 2906 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 2907 // CHECK3: cond.true: 2908 // CHECK3-NEXT: br label [[COND_END:%.*]] 2909 // CHECK3: cond.false: 2910 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2911 // CHECK3-NEXT: br label [[COND_END]] 2912 // CHECK3: cond.end: 2913 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 2914 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 2915 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 2916 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 2917 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 2918 // CHECK3: omp.inner.for.cond: 2919 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2920 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 2921 // CHECK3-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 2922 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 2923 // CHECK3: omp.inner.for.body: 2924 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2925 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 2926 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 2927 // CHECK3-NEXT: store i32 [[SUB]], i32* [[I]], align 4 2928 // CHECK3-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 2929 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 2930 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 2931 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 2932 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 2933 // CHECK3-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 2934 // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 2935 // CHECK3-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 2936 // CHECK3-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 2937 // CHECK3-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 2938 // CHECK3-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 2939 // CHECK3-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 2940 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 2941 // CHECK3-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 2942 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 2943 // CHECK3-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 2944 // CHECK3-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 2945 // CHECK3-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 2946 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 2947 // CHECK3-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 2948 // CHECK3-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 2949 // CHECK3-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 2950 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 2951 // CHECK3: omp.body.continue: 2952 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 2953 // CHECK3: omp.inner.for.inc: 2954 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 2955 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP28]], 1 2956 // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 2957 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 2958 // CHECK3: omp.inner.for.end: 2959 // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 2960 // CHECK3: omp.loop.exit: 2961 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 2962 // CHECK3-NEXT: ret void 2963 // 2964 // 2965 // CHECK3-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 2966 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 2967 // CHECK3-NEXT: entry: 2968 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 2969 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 2970 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 2971 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 2972 // CHECK3-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8 2973 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 2974 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 2975 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 2976 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 2977 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 2978 // CHECK3-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 2979 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 2980 // CHECK3-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 2981 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 2982 // CHECK3-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 2983 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 2984 // CHECK3-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 2985 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.2*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]]) 2986 // CHECK3-NEXT: ret void 2987 // 2988 // 2989 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 2990 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 2991 // CHECK3-NEXT: entry: 2992 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 2993 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 2994 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.2*, align 8 2995 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 2996 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 2997 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 2998 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 2999 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3000 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3001 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3002 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3003 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3004 // CHECK3-NEXT: store %struct.anon.2* [[__CONTEXT]], %struct.anon.2** [[__CONTEXT_ADDR]], align 8 3005 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR]], align 8 3006 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], %struct.anon.2* [[TMP0]], i32 0, i32 0 3007 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 3008 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 1 3009 // CHECK3-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 3010 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 2 3011 // CHECK3-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 3012 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 3 3013 // CHECK3-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 3014 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3015 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 3016 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3017 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3018 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3019 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3020 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 3021 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3022 // CHECK3: omp.dispatch.cond: 3023 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3024 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP11]], 16908288 3025 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3026 // CHECK3: cond.true: 3027 // CHECK3-NEXT: br label [[COND_END:%.*]] 3028 // CHECK3: cond.false: 3029 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3030 // CHECK3-NEXT: br label [[COND_END]] 3031 // CHECK3: cond.end: 3032 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 3033 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3034 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3035 // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 3036 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3037 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3038 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]] 3039 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3040 // CHECK3: omp.dispatch.body: 3041 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3042 // CHECK3: omp.inner.for.cond: 3043 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3044 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3045 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP16]], [[TMP17]] 3046 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3047 // CHECK3: omp.inner.for.body: 3048 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3049 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP18]], 127 3050 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 3051 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3052 // CHECK3-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP4]], align 8 3053 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 3054 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP20]] to i64 3055 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM]] 3056 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 3057 // CHECK3-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP6]], align 8 3058 // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 3059 // CHECK3-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP23]] to i64 3060 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM3]] 3061 // CHECK3-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4 3062 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[TMP21]], [[TMP24]] 3063 // CHECK3-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP8]], align 8 3064 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 3065 // CHECK3-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP26]] to i64 3066 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[IDXPROM6]] 3067 // CHECK3-NEXT: [[TMP27:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3068 // CHECK3-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP27]] 3069 // CHECK3-NEXT: [[TMP28:%.*]] = load float*, float** [[TMP2]], align 8 3070 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[I]], align 4 3071 // CHECK3-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP29]] to i64 3072 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP28]], i64 [[IDXPROM9]] 3073 // CHECK3-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 3074 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3075 // CHECK3: omp.body.continue: 3076 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3077 // CHECK3: omp.inner.for.inc: 3078 // CHECK3-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3079 // CHECK3-NEXT: [[ADD11:%.*]] = add i32 [[TMP30]], 1 3080 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 3081 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3082 // CHECK3: omp.inner.for.end: 3083 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3084 // CHECK3: omp.dispatch.inc: 3085 // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3086 // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3087 // CHECK3-NEXT: [[ADD12:%.*]] = add i32 [[TMP31]], [[TMP32]] 3088 // CHECK3-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 3089 // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3090 // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3091 // CHECK3-NEXT: [[ADD13:%.*]] = add i32 [[TMP33]], [[TMP34]] 3092 // CHECK3-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 3093 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3094 // CHECK3: omp.dispatch.end: 3095 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 3096 // CHECK3-NEXT: ret void 3097 // 3098 // 3099 // CHECK3-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 3100 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3101 // CHECK3-NEXT: entry: 3102 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3103 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3104 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3105 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3106 // CHECK3-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 8 3107 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3108 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3109 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3110 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3111 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 3112 // CHECK3-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 3113 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 3114 // CHECK3-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 3115 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 3116 // CHECK3-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 3117 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 3118 // CHECK3-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 3119 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.3*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]]) 3120 // CHECK3-NEXT: ret void 3121 // 3122 // 3123 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..4 3124 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 3125 // CHECK3-NEXT: entry: 3126 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3127 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3128 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.3*, align 8 3129 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3130 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 8 3131 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3132 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3133 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3134 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3135 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 3136 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3137 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3138 // CHECK3-NEXT: store %struct.anon.3* [[__CONTEXT]], %struct.anon.3** [[__CONTEXT_ADDR]], align 8 3139 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon.3*, %struct.anon.3** [[__CONTEXT_ADDR]], align 8 3140 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], %struct.anon.3* [[TMP0]], i32 0, i32 0 3141 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 3142 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 1 3143 // CHECK3-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 3144 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 2 3145 // CHECK3-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 3146 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 3 3147 // CHECK3-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 3148 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3149 // CHECK3-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 3150 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3151 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3152 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3153 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3154 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1) 3155 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3156 // CHECK3: omp.dispatch.cond: 3157 // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 3158 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 3159 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3160 // CHECK3: omp.dispatch.body: 3161 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3162 // CHECK3-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 3163 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3164 // CHECK3: omp.inner.for.cond: 3165 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 3166 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 3167 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 3168 // CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 3169 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3170 // CHECK3: omp.inner.for.body: 3171 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 3172 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 3173 // CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 3174 // CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5 3175 // CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !5 3176 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 3177 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 3178 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !5 3179 // CHECK3-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !5 3180 // CHECK3-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 3181 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 3182 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !5 3183 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 3184 // CHECK3-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !5 3185 // CHECK3-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 3186 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 3187 // CHECK3-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !5 3188 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 3189 // CHECK3-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !5 3190 // CHECK3-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 3191 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 3192 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5 3193 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3194 // CHECK3: omp.body.continue: 3195 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3196 // CHECK3: omp.inner.for.inc: 3197 // CHECK3-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 3198 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 3199 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 3200 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 3201 // CHECK3: omp.inner.for.end: 3202 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3203 // CHECK3: omp.dispatch.inc: 3204 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3205 // CHECK3: omp.dispatch.end: 3206 // CHECK3-NEXT: ret void 3207 // 3208 // 3209 // CHECK3-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 3210 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3211 // CHECK3-NEXT: entry: 3212 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3213 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3214 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3215 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3216 // CHECK3-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8 3217 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3218 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3219 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3220 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3221 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 3222 // CHECK3-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 3223 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 3224 // CHECK3-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 3225 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 3226 // CHECK3-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 3227 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 3228 // CHECK3-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 3229 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.4*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]]) 3230 // CHECK3-NEXT: ret void 3231 // 3232 // 3233 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..5 3234 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 3235 // CHECK3-NEXT: entry: 3236 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3237 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3238 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.4*, align 8 3239 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3240 // CHECK3-NEXT: [[TMP:%.*]] = alloca i64, align 8 3241 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3242 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3243 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3244 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3245 // CHECK3-NEXT: [[I:%.*]] = alloca i64, align 8 3246 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3247 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3248 // CHECK3-NEXT: store %struct.anon.4* [[__CONTEXT]], %struct.anon.4** [[__CONTEXT_ADDR]], align 8 3249 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR]], align 8 3250 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], %struct.anon.4* [[TMP0]], i32 0, i32 0 3251 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 3252 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 1 3253 // CHECK3-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 3254 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 2 3255 // CHECK3-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 3256 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 3 3257 // CHECK3-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 3258 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3259 // CHECK3-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 3260 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3261 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3262 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3263 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3264 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7) 3265 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3266 // CHECK3: omp.dispatch.cond: 3267 // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 3268 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 3269 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3270 // CHECK3: omp.dispatch.body: 3271 // CHECK3-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3272 // CHECK3-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 3273 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3274 // CHECK3: omp.inner.for.cond: 3275 // CHECK3-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 3276 // CHECK3-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !8 3277 // CHECK3-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 3278 // CHECK3-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 3279 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3280 // CHECK3: omp.inner.for.body: 3281 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 3282 // CHECK3-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 3283 // CHECK3-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 3284 // CHECK3-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8 3285 // CHECK3-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !8 3286 // CHECK3-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 3287 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 3288 // CHECK3-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 3289 // CHECK3-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !8 3290 // CHECK3-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 3291 // CHECK3-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 3292 // CHECK3-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !8 3293 // CHECK3-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 3294 // CHECK3-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !8 3295 // CHECK3-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 3296 // CHECK3-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 3297 // CHECK3-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !8 3298 // CHECK3-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 3299 // CHECK3-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 3300 // CHECK3-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 3301 // CHECK3-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 3302 // CHECK3-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 3303 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3304 // CHECK3: omp.body.continue: 3305 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3306 // CHECK3: omp.inner.for.inc: 3307 // CHECK3-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 3308 // CHECK3-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 3309 // CHECK3-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 3310 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 3311 // CHECK3: omp.inner.for.end: 3312 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3313 // CHECK3: omp.dispatch.inc: 3314 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3315 // CHECK3: omp.dispatch.end: 3316 // CHECK3-NEXT: ret void 3317 // 3318 // 3319 // CHECK3-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 3320 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3321 // CHECK3-NEXT: entry: 3322 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3323 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3324 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3325 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3326 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 3327 // CHECK3-NEXT: [[Y:%.*]] = alloca i32, align 4 3328 // CHECK3-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_5:%.*]], align 8 3329 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3330 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3331 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3332 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3333 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 3334 // CHECK3-NEXT: store i32 0, i32* [[Y]], align 4 3335 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 3336 // CHECK3-NEXT: store i32* [[Y]], i32** [[TMP0]], align 8 3337 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 3338 // CHECK3-NEXT: store float** [[A_ADDR]], float*** [[TMP1]], align 8 3339 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 3340 // CHECK3-NEXT: store float** [[B_ADDR]], float*** [[TMP2]], align 8 3341 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 3342 // CHECK3-NEXT: store float** [[C_ADDR]], float*** [[TMP3]], align 8 3343 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 4 3344 // CHECK3-NEXT: store float** [[D_ADDR]], float*** [[TMP4]], align 8 3345 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.5*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]) 3346 // CHECK3-NEXT: ret void 3347 // 3348 // 3349 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..6 3350 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 3351 // CHECK3-NEXT: entry: 3352 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3353 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3354 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.5*, align 8 3355 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3356 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 3357 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3358 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3359 // CHECK3-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 3360 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 3361 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 3362 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3363 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3364 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3365 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3366 // CHECK3-NEXT: [[I7:%.*]] = alloca i8, align 1 3367 // CHECK3-NEXT: [[X8:%.*]] = alloca i32, align 4 3368 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3369 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3370 // CHECK3-NEXT: store %struct.anon.5* [[__CONTEXT]], %struct.anon.5** [[__CONTEXT_ADDR]], align 8 3371 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon.5*, %struct.anon.5** [[__CONTEXT_ADDR]], align 8 3372 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], %struct.anon.5* [[TMP0]], i32 0, i32 0 3373 // CHECK3-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 3374 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 1 3375 // CHECK3-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 3376 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 2 3377 // CHECK3-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 3378 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 3 3379 // CHECK3-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 3380 // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 4 3381 // CHECK3-NEXT: [[TMP10:%.*]] = load float**, float*** [[TMP9]], align 8 3382 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP2]], align 4 3383 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[TMP11]] to i8 3384 // CHECK3-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 3385 // CHECK3-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3386 // CHECK3-NEXT: [[CONV3:%.*]] = sext i8 [[TMP12]] to i32 3387 // CHECK3-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 3388 // CHECK3-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 3389 // CHECK3-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 3390 // CHECK3-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 3391 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 3392 // CHECK3-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 3393 // CHECK3-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 3394 // CHECK3-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3395 // CHECK3-NEXT: store i8 [[TMP13]], i8* [[I]], align 1 3396 // CHECK3-NEXT: store i32 11, i32* [[X]], align 4 3397 // CHECK3-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3398 // CHECK3-NEXT: [[CONV6:%.*]] = sext i8 [[TMP14]] to i32 3399 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 3400 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3401 // CHECK3: omp.precond.then: 3402 // CHECK3-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3403 // CHECK3-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3404 // CHECK3-NEXT: store i64 [[TMP15]], i64* [[DOTOMP_UB]], align 8 3405 // CHECK3-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3406 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3407 // CHECK3-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3408 // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3409 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 3410 // CHECK3-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], i32 1073741862, i64 0, i64 [[TMP16]], i64 1, i64 1) 3411 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3412 // CHECK3: omp.dispatch.cond: 3413 // CHECK3-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3414 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 3415 // CHECK3-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP20]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 3416 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP21]], 0 3417 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3418 // CHECK3: omp.dispatch.body: 3419 // CHECK3-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3420 // CHECK3-NEXT: store i64 [[TMP22]], i64* [[DOTOMP_IV]], align 8 3421 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3422 // CHECK3: omp.inner.for.cond: 3423 // CHECK3-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 3424 // CHECK3-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !11 3425 // CHECK3-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP23]], [[TMP24]] 3426 // CHECK3-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3427 // CHECK3: omp.inner.for.body: 3428 // CHECK3-NEXT: [[TMP25:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11 3429 // CHECK3-NEXT: [[CONV10:%.*]] = sext i8 [[TMP25]] to i64 3430 // CHECK3-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 3431 // CHECK3-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP26]], 11 3432 // CHECK3-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 3433 // CHECK3-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 3434 // CHECK3-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 3435 // CHECK3-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11 3436 // CHECK3-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 3437 // CHECK3-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 3438 // CHECK3-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP28]], 11 3439 // CHECK3-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 3440 // CHECK3-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP27]], [[MUL16]] 3441 // CHECK3-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 3442 // CHECK3-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 3443 // CHECK3-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 3444 // CHECK3-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11 3445 // CHECK3-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !11 3446 // CHECK3-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 3447 // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP30]] to i64 3448 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM]] 3449 // CHECK3-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 3450 // CHECK3-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !11 3451 // CHECK3-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 3452 // CHECK3-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP33]] to i64 3453 // CHECK3-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM21]] 3454 // CHECK3-NEXT: [[TMP34:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !11 3455 // CHECK3-NEXT: [[MUL23:%.*]] = fmul float [[TMP31]], [[TMP34]] 3456 // CHECK3-NEXT: [[TMP35:%.*]] = load float*, float** [[TMP10]], align 8, !llvm.access.group !11 3457 // CHECK3-NEXT: [[TMP36:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 3458 // CHECK3-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP36]] to i64 3459 // CHECK3-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP35]], i64 [[IDXPROM24]] 3460 // CHECK3-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !11 3461 // CHECK3-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP37]] 3462 // CHECK3-NEXT: [[TMP38:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !11 3463 // CHECK3-NEXT: [[TMP39:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 3464 // CHECK3-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP39]] to i64 3465 // CHECK3-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP38]], i64 [[IDXPROM27]] 3466 // CHECK3-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11 3467 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3468 // CHECK3: omp.body.continue: 3469 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3470 // CHECK3: omp.inner.for.inc: 3471 // CHECK3-NEXT: [[TMP40:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 3472 // CHECK3-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP40]], 1 3473 // CHECK3-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 3474 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 3475 // CHECK3: omp.inner.for.end: 3476 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3477 // CHECK3: omp.dispatch.inc: 3478 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3479 // CHECK3: omp.dispatch.end: 3480 // CHECK3-NEXT: br label [[OMP_PRECOND_END]] 3481 // CHECK3: omp.precond.end: 3482 // CHECK3-NEXT: ret void 3483 // 3484 // 3485 // CHECK3-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 3486 // CHECK3-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3487 // CHECK3-NEXT: entry: 3488 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3489 // CHECK3-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3490 // CHECK3-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3491 // CHECK3-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3492 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 3493 // CHECK3-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 8 3494 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3495 // CHECK3-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3496 // CHECK3-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3497 // CHECK3-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3498 // CHECK3-NEXT: store i32 0, i32* [[X]], align 4 3499 // CHECK3-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 3500 // CHECK3-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 3501 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 3502 // CHECK3-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 3503 // CHECK3-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 3504 // CHECK3-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 3505 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 3506 // CHECK3-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 3507 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.6*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]]) 3508 // CHECK3-NEXT: ret void 3509 // 3510 // 3511 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..7 3512 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 3513 // CHECK3-NEXT: entry: 3514 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3515 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3516 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.6*, align 8 3517 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3518 // CHECK3-NEXT: [[TMP:%.*]] = alloca i8, align 1 3519 // CHECK3-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 3520 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3521 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3522 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3523 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3524 // CHECK3-NEXT: [[I:%.*]] = alloca i8, align 1 3525 // CHECK3-NEXT: [[X:%.*]] = alloca i32, align 4 3526 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3527 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3528 // CHECK3-NEXT: store %struct.anon.6* [[__CONTEXT]], %struct.anon.6** [[__CONTEXT_ADDR]], align 8 3529 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR]], align 8 3530 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], %struct.anon.6* [[TMP0]], i32 0, i32 0 3531 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 3532 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 1 3533 // CHECK3-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 3534 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 2 3535 // CHECK3-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 3536 // CHECK3-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 3 3537 // CHECK3-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 3538 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3539 // CHECK3-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 3540 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3541 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3542 // CHECK3-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3543 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3544 // CHECK3-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 1073741861, i32 0, i32 199, i32 1, i32 1) 3545 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3546 // CHECK3: omp.dispatch.cond: 3547 // CHECK3-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 3548 // CHECK3-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 3549 // CHECK3-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3550 // CHECK3: omp.dispatch.body: 3551 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3552 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 3553 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3554 // CHECK3: omp.inner.for.cond: 3555 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 3556 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 3557 // CHECK3-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 3558 // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3559 // CHECK3: omp.inner.for.body: 3560 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 3561 // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP15]], 20 3562 // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 3563 // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 3564 // CHECK3-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 3565 // CHECK3-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14 3566 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 3567 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 3568 // CHECK3-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP17]], 20 3569 // CHECK3-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 3570 // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP16]], [[MUL3]] 3571 // CHECK3-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 3572 // CHECK3-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 3573 // CHECK3-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14 3574 // CHECK3-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !14 3575 // CHECK3-NEXT: [[TMP19:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 3576 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP19]] to i64 3577 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM]] 3578 // CHECK3-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 3579 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !14 3580 // CHECK3-NEXT: [[TMP22:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 3581 // CHECK3-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP22]] to i64 3582 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 3583 // CHECK3-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !14 3584 // CHECK3-NEXT: [[MUL8:%.*]] = fmul float [[TMP20]], [[TMP23]] 3585 // CHECK3-NEXT: [[TMP24:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !14 3586 // CHECK3-NEXT: [[TMP25:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 3587 // CHECK3-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP25]] to i64 3588 // CHECK3-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM9]] 3589 // CHECK3-NEXT: [[TMP26:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 3590 // CHECK3-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP26]] 3591 // CHECK3-NEXT: [[TMP27:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !14 3592 // CHECK3-NEXT: [[TMP28:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 3593 // CHECK3-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP28]] to i64 3594 // CHECK3-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP27]], i64 [[IDXPROM12]] 3595 // CHECK3-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14 3596 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3597 // CHECK3: omp.body.continue: 3598 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3599 // CHECK3: omp.inner.for.inc: 3600 // CHECK3-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 3601 // CHECK3-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP29]], 1 3602 // CHECK3-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 3603 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 3604 // CHECK3: omp.inner.for.end: 3605 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3606 // CHECK3: omp.dispatch.inc: 3607 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3608 // CHECK3: omp.dispatch.end: 3609 // CHECK3-NEXT: ret void 3610 // 3611 // 3612 // CHECK3-LABEL: define {{[^@]+}}@_Z3foov 3613 // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { 3614 // CHECK3-NEXT: entry: 3615 // CHECK3-NEXT: call void @_Z8mayThrowv() 3616 // CHECK3-NEXT: ret i32 0 3617 // 3618 // 3619 // CHECK3-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 3620 // CHECK3-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { 3621 // CHECK3-NEXT: entry: 3622 // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3623 // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 3624 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3625 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3626 // CHECK3-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_7:%.*]], align 8 3627 // CHECK3-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3628 // CHECK3-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 3629 // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 3630 // CHECK3-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 3631 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 3632 // CHECK3-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 3633 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 3634 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 3635 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 3636 // CHECK3-NEXT: store float** [[A_ADDR]], float*** [[TMP3]], align 8 3637 // CHECK3-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 3638 // CHECK3-NEXT: store i64 [[TMP1]], i64* [[TMP4]], align 8 3639 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 3640 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 3641 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[TMP5]], align 8 3642 // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.7*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]]) 3643 // CHECK3-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3644 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) 3645 // CHECK3-NEXT: ret void 3646 // 3647 // 3648 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..8 3649 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 3650 // CHECK3-NEXT: entry: 3651 // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3652 // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3653 // CHECK3-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.7*, align 8 3654 // CHECK3-NEXT: [[N:%.*]] = alloca i32, align 4 3655 // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3656 // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 3657 // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3658 // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3659 // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3660 // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3661 // CHECK3-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 3662 // CHECK3-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 3663 // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 3664 // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3665 // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3666 // CHECK3-NEXT: store %struct.anon.7* [[__CONTEXT]], %struct.anon.7** [[__CONTEXT_ADDR]], align 8 3667 // CHECK3-NEXT: [[TMP0:%.*]] = load %struct.anon.7*, %struct.anon.7** [[__CONTEXT_ADDR]], align 8 3668 // CHECK3-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], %struct.anon.7* [[TMP0]], i32 0, i32 0 3669 // CHECK3-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 3670 // CHECK3-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 1 3671 // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 8 3672 // CHECK3-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 2 3673 // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 8 3674 // CHECK3-NEXT: store i32 [[TMP6]], i32* [[N]], align 4 3675 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3676 // CHECK3-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 3677 // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3678 // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3679 // CHECK3-NEXT: [[TMP7:%.*]] = call i8* @llvm.stacksave() 3680 // CHECK3-NEXT: store i8* [[TMP7]], i8** [[SAVED_STACK]], align 8 3681 // CHECK3-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP4]], align 16 3682 // CHECK3-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR0]], align 8 3683 // CHECK3-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3684 // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 3685 // CHECK3-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 3686 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3687 // CHECK3: omp.dispatch.cond: 3688 // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3689 // CHECK3-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP10]], 16908288 3690 // CHECK3-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3691 // CHECK3: cond.true: 3692 // CHECK3-NEXT: br label [[COND_END:%.*]] 3693 // CHECK3: cond.false: 3694 // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3695 // CHECK3-NEXT: br label [[COND_END]] 3696 // CHECK3: cond.end: 3697 // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 3698 // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3699 // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3700 // CHECK3-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 3701 // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3702 // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3703 // CHECK3-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP13]], [[TMP14]] 3704 // CHECK3-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 3705 // CHECK3: omp.dispatch.cleanup: 3706 // CHECK3-NEXT: br label [[OMP_DISPATCH_END:%.*]] 3707 // CHECK3: omp.dispatch.body: 3708 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3709 // CHECK3: omp.inner.for.cond: 3710 // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3711 // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3712 // CHECK3-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP15]], [[TMP16]] 3713 // CHECK3-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 3714 // CHECK3: omp.inner.for.cond.cleanup: 3715 // CHECK3-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 3716 // CHECK3: omp.inner.for.body: 3717 // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3718 // CHECK3-NEXT: [[MUL:%.*]] = mul i32 [[TMP17]], 127 3719 // CHECK3-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 3720 // CHECK3-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3721 // CHECK3-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 3722 // CHECK3-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 3723 // CHECK3: invoke.cont: 3724 // CHECK3-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float 3725 // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 3726 // CHECK3-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP18]] to i64 3727 // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 [[IDXPROM]] 3728 // CHECK3-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 3729 // CHECK3-NEXT: [[ADD3:%.*]] = fadd float [[CONV]], [[TMP19]] 3730 // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[N]], align 4 3731 // CHECK3-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP20]] to float 3732 // CHECK3-NEXT: [[ADD5:%.*]] = fadd float [[ADD3]], [[CONV4]] 3733 // CHECK3-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP2]], align 8 3734 // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 3735 // CHECK3-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP22]] to i64 3736 // CHECK3-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 3737 // CHECK3-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4 3738 // CHECK3-NEXT: [[ADD8:%.*]] = fadd float [[TMP23]], [[ADD5]] 3739 // CHECK3-NEXT: store float [[ADD8]], float* [[ARRAYIDX7]], align 4 3740 // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3741 // CHECK3: omp.body.continue: 3742 // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3743 // CHECK3: omp.inner.for.inc: 3744 // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3745 // CHECK3-NEXT: [[ADD9:%.*]] = add i32 [[TMP24]], 1 3746 // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 3747 // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] 3748 // CHECK3: omp.inner.for.end: 3749 // CHECK3-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3750 // CHECK3: omp.dispatch.inc: 3751 // CHECK3-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3752 // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3753 // CHECK3-NEXT: [[ADD10:%.*]] = add i32 [[TMP25]], [[TMP26]] 3754 // CHECK3-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4 3755 // CHECK3-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3756 // CHECK3-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 3757 // CHECK3-NEXT: [[ADD11:%.*]] = add i32 [[TMP27]], [[TMP28]] 3758 // CHECK3-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4 3759 // CHECK3-NEXT: br label [[OMP_DISPATCH_COND]] 3760 // CHECK3: omp.dispatch.end: 3761 // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 3762 // CHECK3-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 3763 // CHECK3-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 3764 // CHECK3-NEXT: ret void 3765 // CHECK3: terminate.lpad: 3766 // CHECK3-NEXT: [[TMP30:%.*]] = landingpad { i8*, i32 } 3767 // CHECK3-NEXT: catch i8* null 3768 // CHECK3-NEXT: [[TMP31:%.*]] = extractvalue { i8*, i32 } [[TMP30]], 0 3769 // CHECK3-NEXT: call void @__clang_call_terminate(i8* [[TMP31]]) #[[ATTR7:[0-9]+]] 3770 // CHECK3-NEXT: unreachable 3771 // 3772 // 3773 // CHECK3-LABEL: define {{[^@]+}}@__clang_call_terminate 3774 // CHECK3-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 3775 // CHECK3-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 3776 // CHECK3-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 3777 // CHECK3-NEXT: unreachable 3778 // 3779 // 3780 // CHECK4-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 3781 // CHECK4-SAME: () #[[ATTR0:[0-9]+]] { 3782 // CHECK4-NEXT: entry: 3783 // CHECK4-NEXT: [[A:%.*]] = alloca double, align 8 3784 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3785 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 3786 // CHECK4-NEXT: store double 5.000000e+00, double* [[A]], align 8 3787 // CHECK4-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 3788 // CHECK4-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 3789 // CHECK4-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 3790 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 3791 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3792 // CHECK4-NEXT: store i8 [[TMP2]], i8* [[TMP1]], align 1 3793 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 3794 // CHECK4-NEXT: ret void 3795 // 3796 // 3797 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. 3798 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { 3799 // CHECK4-NEXT: entry: 3800 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3801 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3802 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 3803 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 3804 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 3805 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 8 3806 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 3807 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 3808 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 3809 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 3810 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 3811 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 3812 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3813 // CHECK4-NEXT: [[A:%.*]] = alloca double, align 8 3814 // CHECK4-NEXT: [[I4:%.*]] = alloca i64, align 8 3815 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3816 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3817 // CHECK4-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 3818 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 3819 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 3820 // CHECK4-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 3821 // CHECK4-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 3822 // CHECK4-NEXT: [[TMP3:%.*]] = load double, double* undef, align 8 3823 // CHECK4-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 3824 // CHECK4-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 3825 // CHECK4-NEXT: [[TMP4:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 3826 // CHECK4-NEXT: [[SUB:%.*]] = fsub double [[TMP4]], 1.000000e+00 3827 // CHECK4-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 3828 // CHECK4-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i64 3829 // CHECK4-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 1 3830 // CHECK4-NEXT: store i64 [[SUB3]], i64* [[DOTCAPTURE_EXPR_2]], align 8 3831 // CHECK4-NEXT: store i64 1, i64* [[I]], align 8 3832 // CHECK4-NEXT: [[TMP5:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 3833 // CHECK4-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP5]] 3834 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 3835 // CHECK4: omp.precond.then: 3836 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 3837 // CHECK4-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3838 // CHECK4-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_UB]], align 8 3839 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 3840 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3841 // CHECK4-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 3842 // CHECK4-NEXT: [[CONV5:%.*]] = sext i8 [[TMP7]] to i64 3843 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3844 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 3845 // CHECK4-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]]) 3846 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 3847 // CHECK4: omp.dispatch.cond: 3848 // CHECK4-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3849 // CHECK4-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3850 // CHECK4-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP10]], [[TMP11]] 3851 // CHECK4-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3852 // CHECK4: cond.true: 3853 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 3854 // CHECK4-NEXT: br label [[COND_END:%.*]] 3855 // CHECK4: cond.false: 3856 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3857 // CHECK4-NEXT: br label [[COND_END]] 3858 // CHECK4: cond.end: 3859 // CHECK4-NEXT: [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 3860 // CHECK4-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 3861 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3862 // CHECK4-NEXT: store i64 [[TMP14]], i64* [[DOTOMP_IV]], align 8 3863 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3864 // CHECK4-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3865 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 3866 // CHECK4-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP15]], [[ADD7]] 3867 // CHECK4-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 3868 // CHECK4: omp.dispatch.body: 3869 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3870 // CHECK4: omp.inner.for.cond: 3871 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3872 // CHECK4-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3873 // CHECK4-NEXT: [[ADD9:%.*]] = add i64 [[TMP18]], 1 3874 // CHECK4-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP17]], [[ADD9]] 3875 // CHECK4-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3876 // CHECK4: omp.inner.for.body: 3877 // CHECK4-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3878 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP19]], 1 3879 // CHECK4-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]] 3880 // CHECK4-NEXT: store i64 [[ADD11]], i64* [[I4]], align 8 3881 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 3882 // CHECK4: omp.body.continue: 3883 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 3884 // CHECK4: omp.inner.for.inc: 3885 // CHECK4-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 3886 // CHECK4-NEXT: [[ADD12:%.*]] = add i64 [[TMP20]], 1 3887 // CHECK4-NEXT: store i64 [[ADD12]], i64* [[DOTOMP_IV]], align 8 3888 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 3889 // CHECK4: omp.inner.for.end: 3890 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 3891 // CHECK4: omp.dispatch.inc: 3892 // CHECK4-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 3893 // CHECK4-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 3894 // CHECK4-NEXT: [[ADD13:%.*]] = add i64 [[TMP21]], [[TMP22]] 3895 // CHECK4-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_LB]], align 8 3896 // CHECK4-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 3897 // CHECK4-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 3898 // CHECK4-NEXT: [[ADD14:%.*]] = add i64 [[TMP23]], [[TMP24]] 3899 // CHECK4-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_UB]], align 8 3900 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 3901 // CHECK4: omp.dispatch.end: 3902 // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3903 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 3904 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 3905 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 3906 // CHECK4: omp.precond.end: 3907 // CHECK4-NEXT: ret void 3908 // 3909 // 3910 // CHECK4-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 3911 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 3912 // CHECK4-NEXT: entry: 3913 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 3914 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 3915 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 3916 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 3917 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 3918 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 3919 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 3920 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 3921 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 3922 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 3923 // CHECK4-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 3924 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 3925 // CHECK4-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 3926 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 3927 // CHECK4-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 3928 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 3929 // CHECK4-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 3930 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]]) 3931 // CHECK4-NEXT: ret void 3932 // 3933 // 3934 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 3935 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 3936 // CHECK4-NEXT: entry: 3937 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 3938 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 3939 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.0*, align 8 3940 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 3941 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 3942 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 3943 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 3944 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 3945 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 3946 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 3947 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 3948 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 3949 // CHECK4-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 3950 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 3951 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 3952 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 3953 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 3954 // CHECK4-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 3955 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 3956 // CHECK4-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 3957 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 3 3958 // CHECK4-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 3959 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 3960 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 3961 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 3962 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 3963 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 3964 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 3965 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 3966 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3967 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 3968 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 3969 // CHECK4: cond.true: 3970 // CHECK4-NEXT: br label [[COND_END:%.*]] 3971 // CHECK4: cond.false: 3972 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3973 // CHECK4-NEXT: br label [[COND_END]] 3974 // CHECK4: cond.end: 3975 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 3976 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 3977 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 3978 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 3979 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 3980 // CHECK4: omp.inner.for.cond: 3981 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3982 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 3983 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 3984 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 3985 // CHECK4: omp.inner.for.body: 3986 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 3987 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 3988 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 3989 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 3990 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 3991 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 3992 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 3993 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 3994 // CHECK4-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 3995 // CHECK4-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 3996 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 3997 // CHECK4-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 3998 // CHECK4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 3999 // CHECK4-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 4000 // CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 4001 // CHECK4-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 4002 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 4003 // CHECK4-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 4004 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 4005 // CHECK4-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 4006 // CHECK4-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 4007 // CHECK4-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 4008 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 4009 // CHECK4-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 4010 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 4011 // CHECK4-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 4012 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4013 // CHECK4: omp.body.continue: 4014 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4015 // CHECK4: omp.inner.for.inc: 4016 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4017 // CHECK4-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP28]], 1 4018 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 4019 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 4020 // CHECK4: omp.inner.for.end: 4021 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4022 // CHECK4: omp.loop.exit: 4023 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4024 // CHECK4-NEXT: ret void 4025 // 4026 // 4027 // CHECK4-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 4028 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4029 // CHECK4-NEXT: entry: 4030 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4031 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4032 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4033 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4034 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 4035 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4036 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4037 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4038 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4039 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 4040 // CHECK4-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 4041 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 4042 // CHECK4-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 4043 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 4044 // CHECK4-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 4045 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 4046 // CHECK4-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 4047 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.1*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]]) 4048 // CHECK4-NEXT: ret void 4049 // 4050 // 4051 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 4052 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 4053 // CHECK4-NEXT: entry: 4054 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4055 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4056 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.1*, align 8 4057 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4058 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 4059 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4060 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4061 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4062 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4063 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 4064 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4065 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4066 // CHECK4-NEXT: store %struct.anon.1* [[__CONTEXT]], %struct.anon.1** [[__CONTEXT_ADDR]], align 8 4067 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR]], align 8 4068 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP0]], i32 0, i32 0 4069 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 4070 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 1 4071 // CHECK4-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 4072 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 2 4073 // CHECK4-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 4074 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 3 4075 // CHECK4-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 4076 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4077 // CHECK4-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 4078 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4079 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4080 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4081 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4082 // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 4083 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4084 // CHECK4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 4085 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4086 // CHECK4: cond.true: 4087 // CHECK4-NEXT: br label [[COND_END:%.*]] 4088 // CHECK4: cond.false: 4089 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4090 // CHECK4-NEXT: br label [[COND_END]] 4091 // CHECK4: cond.end: 4092 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4093 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4094 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4095 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 4096 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4097 // CHECK4: omp.inner.for.cond: 4098 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4099 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4100 // CHECK4-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 4101 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4102 // CHECK4: omp.inner.for.body: 4103 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4104 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 4105 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 4106 // CHECK4-NEXT: store i32 [[SUB]], i32* [[I]], align 4 4107 // CHECK4-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 4108 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 4109 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 4110 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 4111 // CHECK4-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 4112 // CHECK4-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 4113 // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 4114 // CHECK4-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 4115 // CHECK4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 4116 // CHECK4-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 4117 // CHECK4-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 4118 // CHECK4-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 4119 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 4120 // CHECK4-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 4121 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 4122 // CHECK4-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 4123 // CHECK4-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 4124 // CHECK4-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 4125 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 4126 // CHECK4-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 4127 // CHECK4-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 4128 // CHECK4-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 4129 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4130 // CHECK4: omp.body.continue: 4131 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4132 // CHECK4: omp.inner.for.inc: 4133 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4134 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP28]], 1 4135 // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 4136 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 4137 // CHECK4: omp.inner.for.end: 4138 // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 4139 // CHECK4: omp.loop.exit: 4140 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4141 // CHECK4-NEXT: ret void 4142 // 4143 // 4144 // CHECK4-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 4145 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4146 // CHECK4-NEXT: entry: 4147 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4148 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4149 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4150 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4151 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8 4152 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4153 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4154 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4155 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4156 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 4157 // CHECK4-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 4158 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 4159 // CHECK4-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 4160 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 4161 // CHECK4-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 4162 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 4163 // CHECK4-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 4164 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.2*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]]) 4165 // CHECK4-NEXT: ret void 4166 // 4167 // 4168 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 4169 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 4170 // CHECK4-NEXT: entry: 4171 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4172 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4173 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.2*, align 8 4174 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4175 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 4176 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4177 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4178 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4179 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4180 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 4181 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4182 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4183 // CHECK4-NEXT: store %struct.anon.2* [[__CONTEXT]], %struct.anon.2** [[__CONTEXT_ADDR]], align 8 4184 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR]], align 8 4185 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], %struct.anon.2* [[TMP0]], i32 0, i32 0 4186 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 4187 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 1 4188 // CHECK4-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 4189 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 2 4190 // CHECK4-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 4191 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 3 4192 // CHECK4-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 4193 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4194 // CHECK4-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 4195 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4196 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4197 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4198 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4199 // CHECK4-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 4200 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4201 // CHECK4: omp.dispatch.cond: 4202 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4203 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP11]], 16908288 4204 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4205 // CHECK4: cond.true: 4206 // CHECK4-NEXT: br label [[COND_END:%.*]] 4207 // CHECK4: cond.false: 4208 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4209 // CHECK4-NEXT: br label [[COND_END]] 4210 // CHECK4: cond.end: 4211 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 4212 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4213 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4214 // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 4215 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4216 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4217 // CHECK4-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]] 4218 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4219 // CHECK4: omp.dispatch.body: 4220 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4221 // CHECK4: omp.inner.for.cond: 4222 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4223 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4224 // CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP16]], [[TMP17]] 4225 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4226 // CHECK4: omp.inner.for.body: 4227 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4228 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP18]], 127 4229 // CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4230 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4231 // CHECK4-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP4]], align 8 4232 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 4233 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP20]] to i64 4234 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM]] 4235 // CHECK4-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 4236 // CHECK4-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP6]], align 8 4237 // CHECK4-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 4238 // CHECK4-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP23]] to i64 4239 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM3]] 4240 // CHECK4-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4 4241 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[TMP21]], [[TMP24]] 4242 // CHECK4-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP8]], align 8 4243 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 4244 // CHECK4-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP26]] to i64 4245 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[IDXPROM6]] 4246 // CHECK4-NEXT: [[TMP27:%.*]] = load float, float* [[ARRAYIDX7]], align 4 4247 // CHECK4-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP27]] 4248 // CHECK4-NEXT: [[TMP28:%.*]] = load float*, float** [[TMP2]], align 8 4249 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[I]], align 4 4250 // CHECK4-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP29]] to i64 4251 // CHECK4-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP28]], i64 [[IDXPROM9]] 4252 // CHECK4-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 4253 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4254 // CHECK4: omp.body.continue: 4255 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4256 // CHECK4: omp.inner.for.inc: 4257 // CHECK4-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4258 // CHECK4-NEXT: [[ADD11:%.*]] = add i32 [[TMP30]], 1 4259 // CHECK4-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 4260 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 4261 // CHECK4: omp.inner.for.end: 4262 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4263 // CHECK4: omp.dispatch.inc: 4264 // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4265 // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4266 // CHECK4-NEXT: [[ADD12:%.*]] = add i32 [[TMP31]], [[TMP32]] 4267 // CHECK4-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 4268 // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4269 // CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4270 // CHECK4-NEXT: [[ADD13:%.*]] = add i32 [[TMP33]], [[TMP34]] 4271 // CHECK4-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 4272 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4273 // CHECK4: omp.dispatch.end: 4274 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 4275 // CHECK4-NEXT: ret void 4276 // 4277 // 4278 // CHECK4-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 4279 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4280 // CHECK4-NEXT: entry: 4281 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4282 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4283 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4284 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4285 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 8 4286 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4287 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4288 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4289 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4290 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 4291 // CHECK4-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 4292 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 4293 // CHECK4-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 4294 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 4295 // CHECK4-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 4296 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 4297 // CHECK4-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 4298 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.3*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]]) 4299 // CHECK4-NEXT: ret void 4300 // 4301 // 4302 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..4 4303 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 4304 // CHECK4-NEXT: entry: 4305 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4306 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4307 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.3*, align 8 4308 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4309 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 8 4310 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4311 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4312 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4313 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4314 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 4315 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4316 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4317 // CHECK4-NEXT: store %struct.anon.3* [[__CONTEXT]], %struct.anon.3** [[__CONTEXT_ADDR]], align 8 4318 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon.3*, %struct.anon.3** [[__CONTEXT_ADDR]], align 8 4319 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], %struct.anon.3* [[TMP0]], i32 0, i32 0 4320 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 4321 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 1 4322 // CHECK4-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 4323 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 2 4324 // CHECK4-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 4325 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 3 4326 // CHECK4-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 4327 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4328 // CHECK4-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 4329 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4330 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4331 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4332 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4333 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 35, i64 0, i64 16908287, i64 1, i64 1) 4334 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4335 // CHECK4: omp.dispatch.cond: 4336 // CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4337 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 4338 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4339 // CHECK4: omp.dispatch.body: 4340 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4341 // CHECK4-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 4342 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4343 // CHECK4: omp.inner.for.cond: 4344 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 4345 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 4346 // CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 4347 // CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 4348 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4349 // CHECK4: omp.inner.for.body: 4350 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 4351 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 4352 // CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 4353 // CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5 4354 // CHECK4-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !5 4355 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 4356 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 4357 // CHECK4-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !5 4358 // CHECK4-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !5 4359 // CHECK4-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 4360 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 4361 // CHECK4-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !5 4362 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 4363 // CHECK4-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !5 4364 // CHECK4-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 4365 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 4366 // CHECK4-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !5 4367 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 4368 // CHECK4-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !5 4369 // CHECK4-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 4370 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 4371 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5 4372 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4373 // CHECK4: omp.body.continue: 4374 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4375 // CHECK4: omp.inner.for.inc: 4376 // CHECK4-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 4377 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 4378 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 4379 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 4380 // CHECK4: omp.inner.for.end: 4381 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4382 // CHECK4: omp.dispatch.inc: 4383 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4384 // CHECK4: omp.dispatch.end: 4385 // CHECK4-NEXT: ret void 4386 // 4387 // 4388 // CHECK4-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 4389 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4390 // CHECK4-NEXT: entry: 4391 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4392 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4393 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4394 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4395 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8 4396 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4397 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4398 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4399 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4400 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 4401 // CHECK4-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 4402 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 4403 // CHECK4-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 4404 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 4405 // CHECK4-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 4406 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 4407 // CHECK4-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 4408 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.4*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]]) 4409 // CHECK4-NEXT: ret void 4410 // 4411 // 4412 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..5 4413 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 4414 // CHECK4-NEXT: entry: 4415 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4416 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4417 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.4*, align 8 4418 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4419 // CHECK4-NEXT: [[TMP:%.*]] = alloca i64, align 8 4420 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4421 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4422 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4423 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4424 // CHECK4-NEXT: [[I:%.*]] = alloca i64, align 8 4425 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4426 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4427 // CHECK4-NEXT: store %struct.anon.4* [[__CONTEXT]], %struct.anon.4** [[__CONTEXT_ADDR]], align 8 4428 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR]], align 8 4429 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], %struct.anon.4* [[TMP0]], i32 0, i32 0 4430 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 4431 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 1 4432 // CHECK4-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 4433 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 2 4434 // CHECK4-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 4435 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 3 4436 // CHECK4-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 4437 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4438 // CHECK4-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 4439 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4440 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4441 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4442 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4443 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 36, i64 0, i64 16908287, i64 1, i64 7) 4444 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4445 // CHECK4: omp.dispatch.cond: 4446 // CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4447 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 4448 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4449 // CHECK4: omp.dispatch.body: 4450 // CHECK4-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4451 // CHECK4-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 4452 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4453 // CHECK4: omp.inner.for.cond: 4454 // CHECK4-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 4455 // CHECK4-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !8 4456 // CHECK4-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 4457 // CHECK4-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 4458 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4459 // CHECK4: omp.inner.for.body: 4460 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 4461 // CHECK4-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 4462 // CHECK4-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 4463 // CHECK4-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8 4464 // CHECK4-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !8 4465 // CHECK4-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 4466 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 4467 // CHECK4-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 4468 // CHECK4-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !8 4469 // CHECK4-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 4470 // CHECK4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 4471 // CHECK4-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !8 4472 // CHECK4-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 4473 // CHECK4-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !8 4474 // CHECK4-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 4475 // CHECK4-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 4476 // CHECK4-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !8 4477 // CHECK4-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 4478 // CHECK4-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 4479 // CHECK4-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 4480 // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 4481 // CHECK4-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 4482 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4483 // CHECK4: omp.body.continue: 4484 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4485 // CHECK4: omp.inner.for.inc: 4486 // CHECK4-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 4487 // CHECK4-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 4488 // CHECK4-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 4489 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 4490 // CHECK4: omp.inner.for.end: 4491 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4492 // CHECK4: omp.dispatch.inc: 4493 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4494 // CHECK4: omp.dispatch.end: 4495 // CHECK4-NEXT: ret void 4496 // 4497 // 4498 // CHECK4-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 4499 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4500 // CHECK4-NEXT: entry: 4501 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4502 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4503 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4504 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4505 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 4506 // CHECK4-NEXT: [[Y:%.*]] = alloca i32, align 4 4507 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_5:%.*]], align 8 4508 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4509 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4510 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4511 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4512 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 4513 // CHECK4-NEXT: store i32 0, i32* [[Y]], align 4 4514 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 4515 // CHECK4-NEXT: store i32* [[Y]], i32** [[TMP0]], align 8 4516 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 4517 // CHECK4-NEXT: store float** [[A_ADDR]], float*** [[TMP1]], align 8 4518 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 4519 // CHECK4-NEXT: store float** [[B_ADDR]], float*** [[TMP2]], align 8 4520 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 4521 // CHECK4-NEXT: store float** [[C_ADDR]], float*** [[TMP3]], align 8 4522 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 4 4523 // CHECK4-NEXT: store float** [[D_ADDR]], float*** [[TMP4]], align 8 4524 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.5*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]) 4525 // CHECK4-NEXT: ret void 4526 // 4527 // 4528 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..6 4529 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 4530 // CHECK4-NEXT: entry: 4531 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4532 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4533 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.5*, align 8 4534 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4535 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 4536 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4537 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4538 // CHECK4-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 4539 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 4540 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 4541 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4542 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4543 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4544 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4545 // CHECK4-NEXT: [[I7:%.*]] = alloca i8, align 1 4546 // CHECK4-NEXT: [[X8:%.*]] = alloca i32, align 4 4547 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4548 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4549 // CHECK4-NEXT: store %struct.anon.5* [[__CONTEXT]], %struct.anon.5** [[__CONTEXT_ADDR]], align 8 4550 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon.5*, %struct.anon.5** [[__CONTEXT_ADDR]], align 8 4551 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], %struct.anon.5* [[TMP0]], i32 0, i32 0 4552 // CHECK4-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 4553 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 1 4554 // CHECK4-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 4555 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 2 4556 // CHECK4-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 4557 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 3 4558 // CHECK4-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 4559 // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 4 4560 // CHECK4-NEXT: [[TMP10:%.*]] = load float**, float*** [[TMP9]], align 8 4561 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP2]], align 4 4562 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[TMP11]] to i8 4563 // CHECK4-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 4564 // CHECK4-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4565 // CHECK4-NEXT: [[CONV3:%.*]] = sext i8 [[TMP12]] to i32 4566 // CHECK4-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 4567 // CHECK4-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 4568 // CHECK4-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 4569 // CHECK4-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 4570 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 4571 // CHECK4-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 4572 // CHECK4-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 4573 // CHECK4-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4574 // CHECK4-NEXT: store i8 [[TMP13]], i8* [[I]], align 1 4575 // CHECK4-NEXT: store i32 11, i32* [[X]], align 4 4576 // CHECK4-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 4577 // CHECK4-NEXT: [[CONV6:%.*]] = sext i8 [[TMP14]] to i32 4578 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 4579 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 4580 // CHECK4: omp.precond.then: 4581 // CHECK4-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 4582 // CHECK4-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 4583 // CHECK4-NEXT: store i64 [[TMP15]], i64* [[DOTOMP_UB]], align 8 4584 // CHECK4-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 4585 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4586 // CHECK4-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 4587 // CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4588 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 4589 // CHECK4-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], i32 38, i64 0, i64 [[TMP16]], i64 1, i64 1) 4590 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4591 // CHECK4: omp.dispatch.cond: 4592 // CHECK4-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4593 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 4594 // CHECK4-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP20]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 4595 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP21]], 0 4596 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4597 // CHECK4: omp.dispatch.body: 4598 // CHECK4-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 4599 // CHECK4-NEXT: store i64 [[TMP22]], i64* [[DOTOMP_IV]], align 8 4600 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4601 // CHECK4: omp.inner.for.cond: 4602 // CHECK4-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4603 // CHECK4-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !11 4604 // CHECK4-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP23]], [[TMP24]] 4605 // CHECK4-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4606 // CHECK4: omp.inner.for.body: 4607 // CHECK4-NEXT: [[TMP25:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11 4608 // CHECK4-NEXT: [[CONV10:%.*]] = sext i8 [[TMP25]] to i64 4609 // CHECK4-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4610 // CHECK4-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP26]], 11 4611 // CHECK4-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 4612 // CHECK4-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 4613 // CHECK4-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 4614 // CHECK4-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11 4615 // CHECK4-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4616 // CHECK4-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4617 // CHECK4-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP28]], 11 4618 // CHECK4-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 4619 // CHECK4-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP27]], [[MUL16]] 4620 // CHECK4-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 4621 // CHECK4-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 4622 // CHECK4-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 4623 // CHECK4-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11 4624 // CHECK4-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !11 4625 // CHECK4-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 4626 // CHECK4-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP30]] to i64 4627 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM]] 4628 // CHECK4-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 4629 // CHECK4-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !11 4630 // CHECK4-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 4631 // CHECK4-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP33]] to i64 4632 // CHECK4-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM21]] 4633 // CHECK4-NEXT: [[TMP34:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !11 4634 // CHECK4-NEXT: [[MUL23:%.*]] = fmul float [[TMP31]], [[TMP34]] 4635 // CHECK4-NEXT: [[TMP35:%.*]] = load float*, float** [[TMP10]], align 8, !llvm.access.group !11 4636 // CHECK4-NEXT: [[TMP36:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 4637 // CHECK4-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP36]] to i64 4638 // CHECK4-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP35]], i64 [[IDXPROM24]] 4639 // CHECK4-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !11 4640 // CHECK4-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP37]] 4641 // CHECK4-NEXT: [[TMP38:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !11 4642 // CHECK4-NEXT: [[TMP39:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 4643 // CHECK4-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP39]] to i64 4644 // CHECK4-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP38]], i64 [[IDXPROM27]] 4645 // CHECK4-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11 4646 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4647 // CHECK4: omp.body.continue: 4648 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4649 // CHECK4: omp.inner.for.inc: 4650 // CHECK4-NEXT: [[TMP40:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4651 // CHECK4-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP40]], 1 4652 // CHECK4-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 4653 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 4654 // CHECK4: omp.inner.for.end: 4655 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4656 // CHECK4: omp.dispatch.inc: 4657 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4658 // CHECK4: omp.dispatch.end: 4659 // CHECK4-NEXT: br label [[OMP_PRECOND_END]] 4660 // CHECK4: omp.precond.end: 4661 // CHECK4-NEXT: ret void 4662 // 4663 // 4664 // CHECK4-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 4665 // CHECK4-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 4666 // CHECK4-NEXT: entry: 4667 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4668 // CHECK4-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 4669 // CHECK4-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 4670 // CHECK4-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 4671 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 4672 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 8 4673 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4674 // CHECK4-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 4675 // CHECK4-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 4676 // CHECK4-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 4677 // CHECK4-NEXT: store i32 0, i32* [[X]], align 4 4678 // CHECK4-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 4679 // CHECK4-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 4680 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 4681 // CHECK4-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 4682 // CHECK4-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 4683 // CHECK4-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 4684 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 4685 // CHECK4-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 4686 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.6*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]]) 4687 // CHECK4-NEXT: ret void 4688 // 4689 // 4690 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..7 4691 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 4692 // CHECK4-NEXT: entry: 4693 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4694 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4695 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.6*, align 8 4696 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4697 // CHECK4-NEXT: [[TMP:%.*]] = alloca i8, align 1 4698 // CHECK4-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 4699 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4700 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4701 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4702 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4703 // CHECK4-NEXT: [[I:%.*]] = alloca i8, align 1 4704 // CHECK4-NEXT: [[X:%.*]] = alloca i32, align 4 4705 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4706 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4707 // CHECK4-NEXT: store %struct.anon.6* [[__CONTEXT]], %struct.anon.6** [[__CONTEXT_ADDR]], align 8 4708 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR]], align 8 4709 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], %struct.anon.6* [[TMP0]], i32 0, i32 0 4710 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 4711 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 1 4712 // CHECK4-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 4713 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 2 4714 // CHECK4-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 4715 // CHECK4-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 3 4716 // CHECK4-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 4717 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4718 // CHECK4-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 4719 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4720 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4721 // CHECK4-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4722 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 4723 // CHECK4-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 37, i32 0, i32 199, i32 1, i32 1) 4724 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4725 // CHECK4: omp.dispatch.cond: 4726 // CHECK4-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 4727 // CHECK4-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 4728 // CHECK4-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 4729 // CHECK4: omp.dispatch.body: 4730 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4731 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 4732 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4733 // CHECK4: omp.inner.for.cond: 4734 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4735 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 4736 // CHECK4-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 4737 // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 4738 // CHECK4: omp.inner.for.body: 4739 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4740 // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP15]], 20 4741 // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 4742 // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 4743 // CHECK4-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 4744 // CHECK4-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14 4745 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4746 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4747 // CHECK4-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP17]], 20 4748 // CHECK4-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 4749 // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP16]], [[MUL3]] 4750 // CHECK4-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 4751 // CHECK4-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 4752 // CHECK4-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14 4753 // CHECK4-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !14 4754 // CHECK4-NEXT: [[TMP19:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 4755 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP19]] to i64 4756 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM]] 4757 // CHECK4-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 4758 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !14 4759 // CHECK4-NEXT: [[TMP22:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 4760 // CHECK4-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP22]] to i64 4761 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 4762 // CHECK4-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !14 4763 // CHECK4-NEXT: [[MUL8:%.*]] = fmul float [[TMP20]], [[TMP23]] 4764 // CHECK4-NEXT: [[TMP24:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !14 4765 // CHECK4-NEXT: [[TMP25:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 4766 // CHECK4-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP25]] to i64 4767 // CHECK4-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM9]] 4768 // CHECK4-NEXT: [[TMP26:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 4769 // CHECK4-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP26]] 4770 // CHECK4-NEXT: [[TMP27:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !14 4771 // CHECK4-NEXT: [[TMP28:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 4772 // CHECK4-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP28]] to i64 4773 // CHECK4-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP27]], i64 [[IDXPROM12]] 4774 // CHECK4-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14 4775 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4776 // CHECK4: omp.body.continue: 4777 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4778 // CHECK4: omp.inner.for.inc: 4779 // CHECK4-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4780 // CHECK4-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP29]], 1 4781 // CHECK4-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 4782 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 4783 // CHECK4: omp.inner.for.end: 4784 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4785 // CHECK4: omp.dispatch.inc: 4786 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4787 // CHECK4: omp.dispatch.end: 4788 // CHECK4-NEXT: ret void 4789 // 4790 // 4791 // CHECK4-LABEL: define {{[^@]+}}@_Z3foov 4792 // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { 4793 // CHECK4-NEXT: entry: 4794 // CHECK4-NEXT: call void @_Z8mayThrowv() 4795 // CHECK4-NEXT: ret i32 0 4796 // 4797 // 4798 // CHECK4-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 4799 // CHECK4-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { 4800 // CHECK4-NEXT: entry: 4801 // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 4802 // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 4803 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4804 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4805 // CHECK4-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_7:%.*]], align 8 4806 // CHECK4-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 4807 // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 4808 // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 4809 // CHECK4-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 4810 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 4811 // CHECK4-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 4812 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 4813 // CHECK4-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 4814 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 4815 // CHECK4-NEXT: store float** [[A_ADDR]], float*** [[TMP3]], align 8 4816 // CHECK4-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 4817 // CHECK4-NEXT: store i64 [[TMP1]], i64* [[TMP4]], align 8 4818 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 4819 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 4820 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[TMP5]], align 8 4821 // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.7*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]]) 4822 // CHECK4-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4823 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) 4824 // CHECK4-NEXT: ret void 4825 // 4826 // 4827 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..8 4828 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) { 4829 // CHECK4-NEXT: entry: 4830 // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4831 // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4832 // CHECK4-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.7*, align 8 4833 // CHECK4-NEXT: [[N:%.*]] = alloca i32, align 4 4834 // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 4835 // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 4836 // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 4837 // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 4838 // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 4839 // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4840 // CHECK4-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 4841 // CHECK4-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 4842 // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 4843 // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4844 // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4845 // CHECK4-NEXT: store %struct.anon.7* [[__CONTEXT]], %struct.anon.7** [[__CONTEXT_ADDR]], align 8 4846 // CHECK4-NEXT: [[TMP0:%.*]] = load %struct.anon.7*, %struct.anon.7** [[__CONTEXT_ADDR]], align 8 4847 // CHECK4-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], %struct.anon.7* [[TMP0]], i32 0, i32 0 4848 // CHECK4-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 4849 // CHECK4-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 1 4850 // CHECK4-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 8 4851 // CHECK4-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 2 4852 // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 8 4853 // CHECK4-NEXT: store i32 [[TMP6]], i32* [[N]], align 4 4854 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 4855 // CHECK4-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 4856 // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 4857 // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 4858 // CHECK4-NEXT: [[TMP7:%.*]] = call i8* @llvm.stacksave() 4859 // CHECK4-NEXT: store i8* [[TMP7]], i8** [[SAVED_STACK]], align 8 4860 // CHECK4-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP4]], align 16 4861 // CHECK4-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR0]], align 8 4862 // CHECK4-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 4863 // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 4864 // CHECK4-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 4865 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 4866 // CHECK4: omp.dispatch.cond: 4867 // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4868 // CHECK4-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP10]], 16908288 4869 // CHECK4-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 4870 // CHECK4: cond.true: 4871 // CHECK4-NEXT: br label [[COND_END:%.*]] 4872 // CHECK4: cond.false: 4873 // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4874 // CHECK4-NEXT: br label [[COND_END]] 4875 // CHECK4: cond.end: 4876 // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 4877 // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 4878 // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4879 // CHECK4-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 4880 // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4881 // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4882 // CHECK4-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP13]], [[TMP14]] 4883 // CHECK4-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 4884 // CHECK4: omp.dispatch.cleanup: 4885 // CHECK4-NEXT: br label [[OMP_DISPATCH_END:%.*]] 4886 // CHECK4: omp.dispatch.body: 4887 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 4888 // CHECK4: omp.inner.for.cond: 4889 // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4890 // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4891 // CHECK4-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP15]], [[TMP16]] 4892 // CHECK4-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 4893 // CHECK4: omp.inner.for.cond.cleanup: 4894 // CHECK4-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 4895 // CHECK4: omp.inner.for.body: 4896 // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4897 // CHECK4-NEXT: [[MUL:%.*]] = mul i32 [[TMP17]], 127 4898 // CHECK4-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 4899 // CHECK4-NEXT: store i32 [[ADD]], i32* [[I]], align 4 4900 // CHECK4-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 4901 // CHECK4-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]] 4902 // CHECK4: invoke.cont: 4903 // CHECK4-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float 4904 // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 4905 // CHECK4-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP18]] to i64 4906 // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 [[IDXPROM]] 4907 // CHECK4-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 4908 // CHECK4-NEXT: [[ADD3:%.*]] = fadd float [[CONV]], [[TMP19]] 4909 // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[N]], align 4 4910 // CHECK4-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP20]] to float 4911 // CHECK4-NEXT: [[ADD5:%.*]] = fadd float [[ADD3]], [[CONV4]] 4912 // CHECK4-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP2]], align 8 4913 // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 4914 // CHECK4-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP22]] to i64 4915 // CHECK4-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 4916 // CHECK4-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4 4917 // CHECK4-NEXT: [[ADD8:%.*]] = fadd float [[TMP23]], [[ADD5]] 4918 // CHECK4-NEXT: store float [[ADD8]], float* [[ARRAYIDX7]], align 4 4919 // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 4920 // CHECK4: omp.body.continue: 4921 // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 4922 // CHECK4: omp.inner.for.inc: 4923 // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 4924 // CHECK4-NEXT: [[ADD9:%.*]] = add i32 [[TMP24]], 1 4925 // CHECK4-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 4926 // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] 4927 // CHECK4: omp.inner.for.end: 4928 // CHECK4-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 4929 // CHECK4: omp.dispatch.inc: 4930 // CHECK4-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 4931 // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4932 // CHECK4-NEXT: [[ADD10:%.*]] = add i32 [[TMP25]], [[TMP26]] 4933 // CHECK4-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4 4934 // CHECK4-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 4935 // CHECK4-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 4936 // CHECK4-NEXT: [[ADD11:%.*]] = add i32 [[TMP27]], [[TMP28]] 4937 // CHECK4-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4 4938 // CHECK4-NEXT: br label [[OMP_DISPATCH_COND]] 4939 // CHECK4: omp.dispatch.end: 4940 // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 4941 // CHECK4-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 4942 // CHECK4-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 4943 // CHECK4-NEXT: ret void 4944 // CHECK4: terminate.lpad: 4945 // CHECK4-NEXT: [[TMP30:%.*]] = landingpad { i8*, i32 } 4946 // CHECK4-NEXT: catch i8* null 4947 // CHECK4-NEXT: [[TMP31:%.*]] = extractvalue { i8*, i32 } [[TMP30]], 0 4948 // CHECK4-NEXT: call void @__clang_call_terminate(i8* [[TMP31]]) #[[ATTR7:[0-9]+]] 4949 // CHECK4-NEXT: unreachable 4950 // 4951 // 4952 // CHECK4-LABEL: define {{[^@]+}}@__clang_call_terminate 4953 // CHECK4-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] comdat { 4954 // CHECK4-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 4955 // CHECK4-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 4956 // CHECK4-NEXT: unreachable 4957 // 4958 // 4959 // CHECK5-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 4960 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] !dbg [[DBG7:![0-9]+]] { 4961 // CHECK5-NEXT: entry: 4962 // CHECK5-NEXT: [[A:%.*]] = alloca double, align 8 4963 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4964 // CHECK5-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 4965 // CHECK5-NEXT: store double 5.000000e+00, double* [[A]], align 8, !dbg [[DBG10:![0-9]+]] 4966 // CHECK5-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8, !dbg [[DBG11:![0-9]+]] 4967 // CHECK5-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8, !dbg [[DBG11]] 4968 // CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]] 4969 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG11]] 4970 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG11]] 4971 // CHECK5-NEXT: store i8 [[TMP2]], i8* [[TMP1]], align 1, !dbg [[DBG11]] 4972 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB4:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]), !dbg [[DBG11]] 4973 // CHECK5-NEXT: ret void, !dbg [[DBG12:![0-9]+]] 4974 // 4975 // 4976 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. 4977 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] !dbg [[DBG13:![0-9]+]] { 4978 // CHECK5-NEXT: entry: 4979 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 4980 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 4981 // CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 4982 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 4983 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 4984 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 4985 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 4986 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 4987 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 4988 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 4989 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 4990 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 4991 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 4992 // CHECK5-NEXT: [[A:%.*]] = alloca double, align 8 4993 // CHECK5-NEXT: [[I4:%.*]] = alloca i64, align 8 4994 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 4995 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 4996 // CHECK5-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 4997 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG14:![0-9]+]] 4998 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0, !dbg [[DBG14]] 4999 // CHECK5-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1, !dbg [[DBG14]] 5000 // CHECK5-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG14]] 5001 // CHECK5-NEXT: [[TMP3:%.*]] = load double, double* undef, align 8, !dbg [[DBG15:![0-9]+]] 5002 // CHECK5-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]], !dbg [[DBG15]] 5003 // CHECK5-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG15]] 5004 // CHECK5-NEXT: [[TMP4:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG15]] 5005 // CHECK5-NEXT: [[SUB:%.*]] = fsub double [[TMP4]], 1.000000e+00, !dbg [[DBG15]] 5006 // CHECK5-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00, !dbg [[DBG15]] 5007 // CHECK5-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i64, !dbg [[DBG15]] 5008 // CHECK5-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 1, !dbg [[DBG15]] 5009 // CHECK5-NEXT: store i64 [[SUB3]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] 5010 // CHECK5-NEXT: store i64 1, i64* [[I]], align 8, !dbg [[DBG15]] 5011 // CHECK5-NEXT: [[TMP5:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8, !dbg [[DBG15]] 5012 // CHECK5-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP5]], !dbg [[DBG15]] 5013 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG14]] 5014 // CHECK5: omp.precond.then: 5015 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]] 5016 // CHECK5-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] 5017 // CHECK5-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 5018 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]] 5019 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG15]] 5020 // CHECK5-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG14]] 5021 // CHECK5-NEXT: [[CONV5:%.*]] = sext i8 [[TMP7]] to i64, !dbg [[DBG14]] 5022 // CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG14]] 5023 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4, !dbg [[DBG14]] 5024 // CHECK5-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]]), !dbg [[DBG14]] 5025 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG14]] 5026 // CHECK5: omp.dispatch.cond: 5027 // CHECK5-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 5028 // CHECK5-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] 5029 // CHECK5-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP10]], [[TMP11]], !dbg [[DBG15]] 5030 // CHECK5-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG15]] 5031 // CHECK5: cond.true: 5032 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG15]] 5033 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG15]] 5034 // CHECK5: cond.false: 5035 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 5036 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG15]] 5037 // CHECK5: cond.end: 5038 // CHECK5-NEXT: [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ], !dbg [[DBG15]] 5039 // CHECK5-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 5040 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]] 5041 // CHECK5-NEXT: store i64 [[TMP14]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 5042 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 5043 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 5044 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1, !dbg [[DBG15]] 5045 // CHECK5-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP15]], [[ADD7]], !dbg [[DBG15]] 5046 // CHECK5-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG14]] 5047 // CHECK5: omp.dispatch.body: 5048 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG14]] 5049 // CHECK5: omp.inner.for.cond: 5050 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 5051 // CHECK5-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 5052 // CHECK5-NEXT: [[ADD9:%.*]] = add i64 [[TMP18]], 1, !dbg [[DBG15]] 5053 // CHECK5-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP17]], [[ADD9]], !dbg [[DBG15]] 5054 // CHECK5-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG14]] 5055 // CHECK5: omp.inner.for.body: 5056 // CHECK5-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 5057 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP19]], 1, !dbg [[DBG15]] 5058 // CHECK5-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]], !dbg [[DBG15]] 5059 // CHECK5-NEXT: store i64 [[ADD11]], i64* [[I4]], align 8, !dbg [[DBG15]] 5060 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG16:![0-9]+]] 5061 // CHECK5: omp.body.continue: 5062 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG14]] 5063 // CHECK5: omp.inner.for.inc: 5064 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 5065 // CHECK5-NEXT: [[ADD12:%.*]] = add i64 [[TMP20]], 1, !dbg [[DBG15]] 5066 // CHECK5-NEXT: store i64 [[ADD12]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG15]] 5067 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG14]], !llvm.loop [[LOOP17:![0-9]+]] 5068 // CHECK5: omp.inner.for.end: 5069 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG14]] 5070 // CHECK5: omp.dispatch.inc: 5071 // CHECK5-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]] 5072 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]] 5073 // CHECK5-NEXT: [[ADD13:%.*]] = add i64 [[TMP21]], [[TMP22]], !dbg [[DBG15]] 5074 // CHECK5-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_LB]], align 8, !dbg [[DBG15]] 5075 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 5076 // CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG15]] 5077 // CHECK5-NEXT: [[ADD14:%.*]] = add i64 [[TMP23]], [[TMP24]], !dbg [[DBG15]] 5078 // CHECK5-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG15]] 5079 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG14]], !llvm.loop [[LOOP18:![0-9]+]] 5080 // CHECK5: omp.dispatch.end: 5081 // CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG14]] 5082 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4, !dbg [[DBG14]] 5083 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP26]]), !dbg [[DBG14]] 5084 // CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG14]] 5085 // CHECK5: omp.precond.end: 5086 // CHECK5-NEXT: ret void, !dbg [[DBG16]] 5087 // 5088 // 5089 // CHECK5-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 5090 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG21:![0-9]+]] { 5091 // CHECK5-NEXT: entry: 5092 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5093 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5094 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5095 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5096 // CHECK5-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 5097 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5098 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5099 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5100 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5101 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG22:![0-9]+]] 5102 // CHECK5-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8, !dbg [[DBG22]] 5103 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG22]] 5104 // CHECK5-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8, !dbg [[DBG22]] 5105 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG22]] 5106 // CHECK5-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8, !dbg [[DBG22]] 5107 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG22]] 5108 // CHECK5-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8, !dbg [[DBG22]] 5109 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB9:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]]), !dbg [[DBG22]] 5110 // CHECK5-NEXT: ret void, !dbg [[DBG23:![0-9]+]] 5111 // 5112 // 5113 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 5114 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] !dbg [[DBG24:![0-9]+]] { 5115 // CHECK5-NEXT: entry: 5116 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5117 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5118 // CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.0*, align 8 5119 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5120 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5121 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5122 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5123 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5124 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5125 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5126 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5127 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5128 // CHECK5-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 5129 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG25:![0-9]+]] 5130 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0, !dbg [[DBG25]] 5131 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8, !dbg [[DBG25]] 5132 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1, !dbg [[DBG25]] 5133 // CHECK5-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8, !dbg [[DBG25]] 5134 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2, !dbg [[DBG25]] 5135 // CHECK5-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8, !dbg [[DBG25]] 5136 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 3, !dbg [[DBG25]] 5137 // CHECK5-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8, !dbg [[DBG25]] 5138 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG26:![0-9]+]] 5139 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 5140 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG26]] 5141 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG26]] 5142 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG25]] 5143 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4, !dbg [[DBG25]] 5144 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB6:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG25]] 5145 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 5146 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423, !dbg [[DBG26]] 5147 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG26]] 5148 // CHECK5: cond.true: 5149 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG26]] 5150 // CHECK5: cond.false: 5151 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 5152 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG26]] 5153 // CHECK5: cond.end: 5154 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG26]] 5155 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 5156 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG26]] 5157 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 5158 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG25]] 5159 // CHECK5: omp.inner.for.cond: 5160 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 5161 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG26]] 5162 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG26]] 5163 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG25]] 5164 // CHECK5: omp.inner.for.body: 5165 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 5166 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7, !dbg [[DBG26]] 5167 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]], !dbg [[DBG26]] 5168 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG26]] 5169 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8, !dbg [[DBG27:![0-9]+]] 5170 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27]] 5171 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG27]] 5172 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]], !dbg [[DBG27]] 5173 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG27]] 5174 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8, !dbg [[DBG27]] 5175 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27]] 5176 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG27]] 5177 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]], !dbg [[DBG27]] 5178 // CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !dbg [[DBG27]] 5179 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]], !dbg [[DBG27]] 5180 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8, !dbg [[DBG27]] 5181 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27]] 5182 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG27]] 5183 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]], !dbg [[DBG27]] 5184 // CHECK5-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG27]] 5185 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]], !dbg [[DBG27]] 5186 // CHECK5-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG27]] 5187 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG27]] 5188 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG27]] 5189 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]], !dbg [[DBG27]] 5190 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG27]] 5191 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG28:![0-9]+]] 5192 // CHECK5: omp.body.continue: 5193 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG25]] 5194 // CHECK5: omp.inner.for.inc: 5195 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 5196 // CHECK5-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP28]], 1, !dbg [[DBG26]] 5197 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG26]] 5198 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG25]], !llvm.loop [[LOOP29:![0-9]+]] 5199 // CHECK5: omp.inner.for.end: 5200 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG25]] 5201 // CHECK5: omp.loop.exit: 5202 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB8:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG25]] 5203 // CHECK5-NEXT: ret void, !dbg [[DBG28]] 5204 // 5205 // 5206 // CHECK5-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 5207 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG30:![0-9]+]] { 5208 // CHECK5-NEXT: entry: 5209 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5210 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5211 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5212 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5213 // CHECK5-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 5214 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5215 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5216 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5217 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5218 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG31:![0-9]+]] 5219 // CHECK5-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8, !dbg [[DBG31]] 5220 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG31]] 5221 // CHECK5-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8, !dbg [[DBG31]] 5222 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG31]] 5223 // CHECK5-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8, !dbg [[DBG31]] 5224 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG31]] 5225 // CHECK5-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8, !dbg [[DBG31]] 5226 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB14:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.1*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]]), !dbg [[DBG31]] 5227 // CHECK5-NEXT: ret void, !dbg [[DBG32:![0-9]+]] 5228 // 5229 // 5230 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 5231 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] !dbg [[DBG33:![0-9]+]] { 5232 // CHECK5-NEXT: entry: 5233 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5234 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5235 // CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.1*, align 8 5236 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5237 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5238 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5239 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5240 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5241 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5242 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5243 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5244 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5245 // CHECK5-NEXT: store %struct.anon.1* [[__CONTEXT]], %struct.anon.1** [[__CONTEXT_ADDR]], align 8 5246 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG34:![0-9]+]] 5247 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP0]], i32 0, i32 0, !dbg [[DBG34]] 5248 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8, !dbg [[DBG34]] 5249 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 1, !dbg [[DBG34]] 5250 // CHECK5-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8, !dbg [[DBG34]] 5251 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 2, !dbg [[DBG34]] 5252 // CHECK5-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8, !dbg [[DBG34]] 5253 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 3, !dbg [[DBG34]] 5254 // CHECK5-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8, !dbg [[DBG34]] 5255 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG35:![0-9]+]] 5256 // CHECK5-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 5257 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG35]] 5258 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG35]] 5259 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG34]] 5260 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4, !dbg [[DBG34]] 5261 // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB11:[0-9]+]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1), !dbg [[DBG34]] 5262 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 5263 // CHECK5-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423, !dbg [[DBG35]] 5264 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG35]] 5265 // CHECK5: cond.true: 5266 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG35]] 5267 // CHECK5: cond.false: 5268 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 5269 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG35]] 5270 // CHECK5: cond.end: 5271 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG35]] 5272 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 5273 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG35]] 5274 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 5275 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG34]] 5276 // CHECK5: omp.inner.for.cond: 5277 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 5278 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG35]] 5279 // CHECK5-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]], !dbg [[DBG35]] 5280 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG34]] 5281 // CHECK5: omp.inner.for.body: 5282 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 5283 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7, !dbg [[DBG35]] 5284 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]], !dbg [[DBG35]] 5285 // CHECK5-NEXT: store i32 [[SUB]], i32* [[I]], align 4, !dbg [[DBG35]] 5286 // CHECK5-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8, !dbg [[DBG36:![0-9]+]] 5287 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36]] 5288 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64, !dbg [[DBG36]] 5289 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]], !dbg [[DBG36]] 5290 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG36]] 5291 // CHECK5-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8, !dbg [[DBG36]] 5292 // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36]] 5293 // CHECK5-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64, !dbg [[DBG36]] 5294 // CHECK5-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]], !dbg [[DBG36]] 5295 // CHECK5-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4, !dbg [[DBG36]] 5296 // CHECK5-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]], !dbg [[DBG36]] 5297 // CHECK5-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8, !dbg [[DBG36]] 5298 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36]] 5299 // CHECK5-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64, !dbg [[DBG36]] 5300 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]], !dbg [[DBG36]] 5301 // CHECK5-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4, !dbg [[DBG36]] 5302 // CHECK5-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]], !dbg [[DBG36]] 5303 // CHECK5-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG36]] 5304 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG36]] 5305 // CHECK5-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64, !dbg [[DBG36]] 5306 // CHECK5-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]], !dbg [[DBG36]] 5307 // CHECK5-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4, !dbg [[DBG36]] 5308 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG37:![0-9]+]] 5309 // CHECK5: omp.body.continue: 5310 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG34]] 5311 // CHECK5: omp.inner.for.inc: 5312 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 5313 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP28]], 1, !dbg [[DBG35]] 5314 // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG35]] 5315 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG34]], !llvm.loop [[LOOP38:![0-9]+]] 5316 // CHECK5: omp.inner.for.end: 5317 // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]], !dbg [[DBG34]] 5318 // CHECK5: omp.loop.exit: 5319 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB13:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG34]] 5320 // CHECK5-NEXT: ret void, !dbg [[DBG37]] 5321 // 5322 // 5323 // CHECK5-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 5324 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG39:![0-9]+]] { 5325 // CHECK5-NEXT: entry: 5326 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5327 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5328 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5329 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5330 // CHECK5-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8 5331 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5332 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5333 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5334 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5335 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG40:![0-9]+]] 5336 // CHECK5-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8, !dbg [[DBG40]] 5337 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG40]] 5338 // CHECK5-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8, !dbg [[DBG40]] 5339 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG40]] 5340 // CHECK5-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8, !dbg [[DBG40]] 5341 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG40]] 5342 // CHECK5-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8, !dbg [[DBG40]] 5343 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB19:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.2*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]]), !dbg [[DBG40]] 5344 // CHECK5-NEXT: ret void, !dbg [[DBG41:![0-9]+]] 5345 // 5346 // 5347 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 5348 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] !dbg [[DBG42:![0-9]+]] { 5349 // CHECK5-NEXT: entry: 5350 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5351 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5352 // CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.2*, align 8 5353 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5354 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 5355 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5356 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5357 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5358 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5359 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 5360 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5361 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5362 // CHECK5-NEXT: store %struct.anon.2* [[__CONTEXT]], %struct.anon.2** [[__CONTEXT_ADDR]], align 8 5363 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG43:![0-9]+]] 5364 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], %struct.anon.2* [[TMP0]], i32 0, i32 0, !dbg [[DBG43]] 5365 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8, !dbg [[DBG43]] 5366 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 1, !dbg [[DBG43]] 5367 // CHECK5-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8, !dbg [[DBG43]] 5368 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 2, !dbg [[DBG43]] 5369 // CHECK5-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8, !dbg [[DBG43]] 5370 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 3, !dbg [[DBG43]] 5371 // CHECK5-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8, !dbg [[DBG43]] 5372 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44:![0-9]+]] 5373 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 5374 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]] 5375 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG44]] 5376 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG43]] 5377 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4, !dbg [[DBG43]] 5378 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB16:[0-9]+]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG43]] 5379 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG43]] 5380 // CHECK5: omp.dispatch.cond: 5381 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 5382 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP11]], 16908288, !dbg [[DBG44]] 5383 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG44]] 5384 // CHECK5: cond.true: 5385 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG44]] 5386 // CHECK5: cond.false: 5387 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 5388 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG44]] 5389 // CHECK5: cond.end: 5390 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ], !dbg [[DBG44]] 5391 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 5392 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44]] 5393 // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 5394 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 5395 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 5396 // CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]], !dbg [[DBG44]] 5397 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG43]] 5398 // CHECK5: omp.dispatch.body: 5399 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG43]] 5400 // CHECK5: omp.inner.for.cond: 5401 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 5402 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 5403 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP16]], [[TMP17]], !dbg [[DBG44]] 5404 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG43]] 5405 // CHECK5: omp.inner.for.body: 5406 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 5407 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP18]], 127, !dbg [[DBG44]] 5408 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG44]] 5409 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG44]] 5410 // CHECK5-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP4]], align 8, !dbg [[DBG45:![0-9]+]] 5411 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG45]] 5412 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP20]] to i64, !dbg [[DBG45]] 5413 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM]], !dbg [[DBG45]] 5414 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG45]] 5415 // CHECK5-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP6]], align 8, !dbg [[DBG45]] 5416 // CHECK5-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG45]] 5417 // CHECK5-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP23]] to i64, !dbg [[DBG45]] 5418 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM3]], !dbg [[DBG45]] 5419 // CHECK5-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG45]] 5420 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[TMP21]], [[TMP24]], !dbg [[DBG45]] 5421 // CHECK5-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP8]], align 8, !dbg [[DBG45]] 5422 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG45]] 5423 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP26]] to i64, !dbg [[DBG45]] 5424 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[IDXPROM6]], !dbg [[DBG45]] 5425 // CHECK5-NEXT: [[TMP27:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG45]] 5426 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP27]], !dbg [[DBG45]] 5427 // CHECK5-NEXT: [[TMP28:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG45]] 5428 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG45]] 5429 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP29]] to i64, !dbg [[DBG45]] 5430 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP28]], i64 [[IDXPROM9]], !dbg [[DBG45]] 5431 // CHECK5-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4, !dbg [[DBG45]] 5432 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG46:![0-9]+]] 5433 // CHECK5: omp.body.continue: 5434 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG43]] 5435 // CHECK5: omp.inner.for.inc: 5436 // CHECK5-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 5437 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP30]], 1, !dbg [[DBG44]] 5438 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG44]] 5439 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP47:![0-9]+]] 5440 // CHECK5: omp.inner.for.end: 5441 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG43]] 5442 // CHECK5: omp.dispatch.inc: 5443 // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44]] 5444 // CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]] 5445 // CHECK5-NEXT: [[ADD12:%.*]] = add i32 [[TMP31]], [[TMP32]], !dbg [[DBG44]] 5446 // CHECK5-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG44]] 5447 // CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 5448 // CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG44]] 5449 // CHECK5-NEXT: [[ADD13:%.*]] = add i32 [[TMP33]], [[TMP34]], !dbg [[DBG44]] 5450 // CHECK5-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG44]] 5451 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG43]], !llvm.loop [[LOOP48:![0-9]+]] 5452 // CHECK5: omp.dispatch.end: 5453 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB18:[0-9]+]], i32 [[TMP10]]), !dbg [[DBG43]] 5454 // CHECK5-NEXT: ret void, !dbg [[DBG46]] 5455 // 5456 // 5457 // CHECK5-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 5458 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG49:![0-9]+]] { 5459 // CHECK5-NEXT: entry: 5460 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5461 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5462 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5463 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5464 // CHECK5-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 8 5465 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5466 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5467 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5468 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5469 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG50:![0-9]+]] 5470 // CHECK5-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8, !dbg [[DBG50]] 5471 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG50]] 5472 // CHECK5-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8, !dbg [[DBG50]] 5473 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG50]] 5474 // CHECK5-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8, !dbg [[DBG50]] 5475 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG50]] 5476 // CHECK5-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8, !dbg [[DBG50]] 5477 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB21:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.3*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]]), !dbg [[DBG50]] 5478 // CHECK5-NEXT: ret void, !dbg [[DBG51:![0-9]+]] 5479 // 5480 // 5481 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..4 5482 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] !dbg [[DBG52:![0-9]+]] { 5483 // CHECK5-NEXT: entry: 5484 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5485 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5486 // CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.3*, align 8 5487 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5488 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 5489 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5490 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5491 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5492 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5493 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 5494 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5495 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5496 // CHECK5-NEXT: store %struct.anon.3* [[__CONTEXT]], %struct.anon.3** [[__CONTEXT_ADDR]], align 8 5497 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.anon.3*, %struct.anon.3** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG53:![0-9]+]] 5498 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], %struct.anon.3* [[TMP0]], i32 0, i32 0, !dbg [[DBG53]] 5499 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8, !dbg [[DBG53]] 5500 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 1, !dbg [[DBG53]] 5501 // CHECK5-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8, !dbg [[DBG53]] 5502 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 2, !dbg [[DBG53]] 5503 // CHECK5-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8, !dbg [[DBG53]] 5504 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 3, !dbg [[DBG53]] 5505 // CHECK5-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8, !dbg [[DBG53]] 5506 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG54:![0-9]+]] 5507 // CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG54]] 5508 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG54]] 5509 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG54]] 5510 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG53]] 5511 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4, !dbg [[DBG53]] 5512 // CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB21]], i32 [[TMP10]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1), !dbg [[DBG53]] 5513 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG53]] 5514 // CHECK5: omp.dispatch.cond: 5515 // CHECK5-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB21]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG53]] 5516 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0, !dbg [[DBG53]] 5517 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG53]] 5518 // CHECK5: omp.dispatch.body: 5519 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG54]] 5520 // CHECK5-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]] 5521 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG53]] 5522 // CHECK5: omp.inner.for.cond: 5523 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55 5524 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG54]], !llvm.access.group !55 5525 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1, !dbg [[DBG54]] 5526 // CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]], !dbg [[DBG54]] 5527 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG53]] 5528 // CHECK5: omp.inner.for.body: 5529 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55 5530 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127, !dbg [[DBG54]] 5531 // CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG54]] 5532 // CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG54]], !llvm.access.group !55 5533 // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !dbg [[DBG56:![0-9]+]], !llvm.access.group !55 5534 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55 5535 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]], !dbg [[DBG56]] 5536 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG56]], !llvm.access.group !55 5537 // CHECK5-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !dbg [[DBG56]], !llvm.access.group !55 5538 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55 5539 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]], !dbg [[DBG56]] 5540 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG56]], !llvm.access.group !55 5541 // CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]], !dbg [[DBG56]] 5542 // CHECK5-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !dbg [[DBG56]], !llvm.access.group !55 5543 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55 5544 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]], !dbg [[DBG56]] 5545 // CHECK5-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG56]], !llvm.access.group !55 5546 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]], !dbg [[DBG56]] 5547 // CHECK5-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG56]], !llvm.access.group !55 5548 // CHECK5-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG56]], !llvm.access.group !55 5549 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]], !dbg [[DBG56]] 5550 // CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG56]], !llvm.access.group !55 5551 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG57:![0-9]+]] 5552 // CHECK5: omp.body.continue: 5553 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG53]] 5554 // CHECK5: omp.inner.for.inc: 5555 // CHECK5-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55 5556 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1, !dbg [[DBG54]] 5557 // CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG54]], !llvm.access.group !55 5558 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP58:![0-9]+]] 5559 // CHECK5: omp.inner.for.end: 5560 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG53]] 5561 // CHECK5: omp.dispatch.inc: 5562 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG53]], !llvm.loop [[LOOP60:![0-9]+]] 5563 // CHECK5: omp.dispatch.end: 5564 // CHECK5-NEXT: ret void, !dbg [[DBG57]] 5565 // 5566 // 5567 // CHECK5-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 5568 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG61:![0-9]+]] { 5569 // CHECK5-NEXT: entry: 5570 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5571 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5572 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5573 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5574 // CHECK5-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8 5575 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5576 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5577 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5578 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5579 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG62:![0-9]+]] 5580 // CHECK5-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8, !dbg [[DBG62]] 5581 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG62]] 5582 // CHECK5-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8, !dbg [[DBG62]] 5583 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG62]] 5584 // CHECK5-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8, !dbg [[DBG62]] 5585 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG62]] 5586 // CHECK5-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8, !dbg [[DBG62]] 5587 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB23:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.4*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]]), !dbg [[DBG62]] 5588 // CHECK5-NEXT: ret void, !dbg [[DBG63:![0-9]+]] 5589 // 5590 // 5591 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..5 5592 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] !dbg [[DBG64:![0-9]+]] { 5593 // CHECK5-NEXT: entry: 5594 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5595 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5596 // CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.4*, align 8 5597 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5598 // CHECK5-NEXT: [[TMP:%.*]] = alloca i64, align 8 5599 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5600 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5601 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5602 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5603 // CHECK5-NEXT: [[I:%.*]] = alloca i64, align 8 5604 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5605 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5606 // CHECK5-NEXT: store %struct.anon.4* [[__CONTEXT]], %struct.anon.4** [[__CONTEXT_ADDR]], align 8 5607 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG65:![0-9]+]] 5608 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], %struct.anon.4* [[TMP0]], i32 0, i32 0, !dbg [[DBG65]] 5609 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8, !dbg [[DBG65]] 5610 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 1, !dbg [[DBG65]] 5611 // CHECK5-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8, !dbg [[DBG65]] 5612 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 2, !dbg [[DBG65]] 5613 // CHECK5-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8, !dbg [[DBG65]] 5614 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 3, !dbg [[DBG65]] 5615 // CHECK5-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8, !dbg [[DBG65]] 5616 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG66:![0-9]+]] 5617 // CHECK5-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG66]] 5618 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG66]] 5619 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG66]] 5620 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG65]] 5621 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4, !dbg [[DBG65]] 5622 // CHECK5-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB23]], i32 [[TMP10]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7), !dbg [[DBG65]] 5623 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG65]] 5624 // CHECK5: omp.dispatch.cond: 5625 // CHECK5-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB23]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG65]] 5626 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0, !dbg [[DBG65]] 5627 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG65]] 5628 // CHECK5: omp.dispatch.body: 5629 // CHECK5-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG66]] 5630 // CHECK5-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]] 5631 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG65]] 5632 // CHECK5: omp.inner.for.cond: 5633 // CHECK5-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67 5634 // CHECK5-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG66]], !llvm.access.group !67 5635 // CHECK5-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1, !dbg [[DBG66]] 5636 // CHECK5-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]], !dbg [[DBG66]] 5637 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG65]] 5638 // CHECK5: omp.inner.for.body: 5639 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67 5640 // CHECK5-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127, !dbg [[DBG66]] 5641 // CHECK5-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]], !dbg [[DBG66]] 5642 // CHECK5-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !dbg [[DBG66]], !llvm.access.group !67 5643 // CHECK5-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !dbg [[DBG68:![0-9]+]], !llvm.access.group !67 5644 // CHECK5-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67 5645 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]], !dbg [[DBG68]] 5646 // CHECK5-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG68]], !llvm.access.group !67 5647 // CHECK5-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !dbg [[DBG68]], !llvm.access.group !67 5648 // CHECK5-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67 5649 // CHECK5-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]], !dbg [[DBG68]] 5650 // CHECK5-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !dbg [[DBG68]], !llvm.access.group !67 5651 // CHECK5-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]], !dbg [[DBG68]] 5652 // CHECK5-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !dbg [[DBG68]], !llvm.access.group !67 5653 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67 5654 // CHECK5-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]], !dbg [[DBG68]] 5655 // CHECK5-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !dbg [[DBG68]], !llvm.access.group !67 5656 // CHECK5-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]], !dbg [[DBG68]] 5657 // CHECK5-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG68]], !llvm.access.group !67 5658 // CHECK5-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !dbg [[DBG68]], !llvm.access.group !67 5659 // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]], !dbg [[DBG68]] 5660 // CHECK5-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !dbg [[DBG68]], !llvm.access.group !67 5661 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG69:![0-9]+]] 5662 // CHECK5: omp.body.continue: 5663 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG65]] 5664 // CHECK5: omp.inner.for.inc: 5665 // CHECK5-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67 5666 // CHECK5-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1, !dbg [[DBG66]] 5667 // CHECK5-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG66]], !llvm.access.group !67 5668 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP70:![0-9]+]] 5669 // CHECK5: omp.inner.for.end: 5670 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG65]] 5671 // CHECK5: omp.dispatch.inc: 5672 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG65]], !llvm.loop [[LOOP72:![0-9]+]] 5673 // CHECK5: omp.dispatch.end: 5674 // CHECK5-NEXT: ret void, !dbg [[DBG69]] 5675 // 5676 // 5677 // CHECK5-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 5678 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG73:![0-9]+]] { 5679 // CHECK5-NEXT: entry: 5680 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5681 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5682 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5683 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5684 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5685 // CHECK5-NEXT: [[Y:%.*]] = alloca i32, align 4 5686 // CHECK5-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_5:%.*]], align 8 5687 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5688 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5689 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5690 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5691 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG74:![0-9]+]] 5692 // CHECK5-NEXT: store i32 0, i32* [[Y]], align 4, !dbg [[DBG75:![0-9]+]] 5693 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG76:![0-9]+]] 5694 // CHECK5-NEXT: store i32* [[Y]], i32** [[TMP0]], align 8, !dbg [[DBG76]] 5695 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG76]] 5696 // CHECK5-NEXT: store float** [[A_ADDR]], float*** [[TMP1]], align 8, !dbg [[DBG76]] 5697 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG76]] 5698 // CHECK5-NEXT: store float** [[B_ADDR]], float*** [[TMP2]], align 8, !dbg [[DBG76]] 5699 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG76]] 5700 // CHECK5-NEXT: store float** [[C_ADDR]], float*** [[TMP3]], align 8, !dbg [[DBG76]] 5701 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 4, !dbg [[DBG76]] 5702 // CHECK5-NEXT: store float** [[D_ADDR]], float*** [[TMP4]], align 8, !dbg [[DBG76]] 5703 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB25:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.5*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]), !dbg [[DBG76]] 5704 // CHECK5-NEXT: ret void, !dbg [[DBG77:![0-9]+]] 5705 // 5706 // 5707 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..6 5708 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] !dbg [[DBG78:![0-9]+]] { 5709 // CHECK5-NEXT: entry: 5710 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5711 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5712 // CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.5*, align 8 5713 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 5714 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 5715 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 5716 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 5717 // CHECK5-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 5718 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 5719 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5720 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 5721 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 5722 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 5723 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5724 // CHECK5-NEXT: [[I7:%.*]] = alloca i8, align 1 5725 // CHECK5-NEXT: [[X8:%.*]] = alloca i32, align 4 5726 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5727 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5728 // CHECK5-NEXT: store %struct.anon.5* [[__CONTEXT]], %struct.anon.5** [[__CONTEXT_ADDR]], align 8 5729 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.anon.5*, %struct.anon.5** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG79:![0-9]+]] 5730 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], %struct.anon.5* [[TMP0]], i32 0, i32 0, !dbg [[DBG79]] 5731 // CHECK5-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8, !dbg [[DBG79]] 5732 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 1, !dbg [[DBG79]] 5733 // CHECK5-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8, !dbg [[DBG79]] 5734 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 2, !dbg [[DBG79]] 5735 // CHECK5-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8, !dbg [[DBG79]] 5736 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 3, !dbg [[DBG79]] 5737 // CHECK5-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8, !dbg [[DBG79]] 5738 // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 4, !dbg [[DBG79]] 5739 // CHECK5-NEXT: [[TMP10:%.*]] = load float**, float*** [[TMP9]], align 8, !dbg [[DBG79]] 5740 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP2]], align 4, !dbg [[DBG80:![0-9]+]] 5741 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[TMP11]] to i8, !dbg [[DBG80]] 5742 // CHECK5-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]] 5743 // CHECK5-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]] 5744 // CHECK5-NEXT: [[CONV3:%.*]] = sext i8 [[TMP12]] to i32, !dbg [[DBG80]] 5745 // CHECK5-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]], !dbg [[DBG80]] 5746 // CHECK5-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1, !dbg [[DBG80]] 5747 // CHECK5-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1, !dbg [[DBG80]] 5748 // CHECK5-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64, !dbg [[DBG80]] 5749 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11, !dbg [[DBG81:![0-9]+]] 5750 // CHECK5-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1, !dbg [[DBG81]] 5751 // CHECK5-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG80]] 5752 // CHECK5-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]] 5753 // CHECK5-NEXT: store i8 [[TMP13]], i8* [[I]], align 1, !dbg [[DBG80]] 5754 // CHECK5-NEXT: store i32 11, i32* [[X]], align 4, !dbg [[DBG81]] 5755 // CHECK5-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]] 5756 // CHECK5-NEXT: [[CONV6:%.*]] = sext i8 [[TMP14]] to i32, !dbg [[DBG80]] 5757 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57, !dbg [[DBG80]] 5758 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]], !dbg [[DBG79]] 5759 // CHECK5: omp.precond.then: 5760 // CHECK5-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG80]] 5761 // CHECK5-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]] 5762 // CHECK5-NEXT: store i64 [[TMP15]], i64* [[DOTOMP_UB]], align 8, !dbg [[DBG80]] 5763 // CHECK5-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8, !dbg [[DBG80]] 5764 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG80]] 5765 // CHECK5-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8, !dbg [[DBG81]] 5766 // CHECK5-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]] 5767 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4, !dbg [[DBG79]] 5768 // CHECK5-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB25]], i32 [[TMP18]], i32 1073741862, i64 0, i64 [[TMP16]], i64 1, i64 1), !dbg [[DBG79]] 5769 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG79]] 5770 // CHECK5: omp.dispatch.cond: 5771 // CHECK5-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG79]] 5772 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4, !dbg [[DBG79]] 5773 // CHECK5-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB25]], i32 [[TMP20]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]), !dbg [[DBG79]] 5774 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP21]], 0, !dbg [[DBG79]] 5775 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG79]] 5776 // CHECK5: omp.dispatch.body: 5777 // CHECK5-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8, !dbg [[DBG80]] 5778 // CHECK5-NEXT: store i64 [[TMP22]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]] 5779 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG79]] 5780 // CHECK5: omp.inner.for.cond: 5781 // CHECK5-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 5782 // CHECK5-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !dbg [[DBG80]], !llvm.access.group !82 5783 // CHECK5-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP23]], [[TMP24]], !dbg [[DBG80]] 5784 // CHECK5-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG79]] 5785 // CHECK5: omp.inner.for.body: 5786 // CHECK5-NEXT: [[TMP25:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !dbg [[DBG80]], !llvm.access.group !82 5787 // CHECK5-NEXT: [[CONV10:%.*]] = sext i8 [[TMP25]] to i64, !dbg [[DBG80]] 5788 // CHECK5-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 5789 // CHECK5-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP26]], 11, !dbg [[DBG80]] 5790 // CHECK5-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1, !dbg [[DBG80]] 5791 // CHECK5-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]], !dbg [[DBG80]] 5792 // CHECK5-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8, !dbg [[DBG80]] 5793 // CHECK5-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !dbg [[DBG80]], !llvm.access.group !82 5794 // CHECK5-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 5795 // CHECK5-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 5796 // CHECK5-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP28]], 11, !dbg [[DBG80]] 5797 // CHECK5-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11, !dbg [[DBG80]] 5798 // CHECK5-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP27]], [[MUL16]], !dbg [[DBG80]] 5799 // CHECK5-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1, !dbg [[DBG81]] 5800 // CHECK5-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]], !dbg [[DBG81]] 5801 // CHECK5-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32, !dbg [[DBG81]] 5802 // CHECK5-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !dbg [[DBG81]], !llvm.access.group !82 5803 // CHECK5-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP6]], align 8, !dbg [[DBG83:![0-9]+]], !llvm.access.group !82 5804 // CHECK5-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82 5805 // CHECK5-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP30]] to i64, !dbg [[DBG83]] 5806 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM]], !dbg [[DBG83]] 5807 // CHECK5-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG83]], !llvm.access.group !82 5808 // CHECK5-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP8]], align 8, !dbg [[DBG83]], !llvm.access.group !82 5809 // CHECK5-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82 5810 // CHECK5-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP33]] to i64, !dbg [[DBG83]] 5811 // CHECK5-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM21]], !dbg [[DBG83]] 5812 // CHECK5-NEXT: [[TMP34:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !dbg [[DBG83]], !llvm.access.group !82 5813 // CHECK5-NEXT: [[MUL23:%.*]] = fmul float [[TMP31]], [[TMP34]], !dbg [[DBG83]] 5814 // CHECK5-NEXT: [[TMP35:%.*]] = load float*, float** [[TMP10]], align 8, !dbg [[DBG83]], !llvm.access.group !82 5815 // CHECK5-NEXT: [[TMP36:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82 5816 // CHECK5-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP36]] to i64, !dbg [[DBG83]] 5817 // CHECK5-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP35]], i64 [[IDXPROM24]], !dbg [[DBG83]] 5818 // CHECK5-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !dbg [[DBG83]], !llvm.access.group !82 5819 // CHECK5-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP37]], !dbg [[DBG83]] 5820 // CHECK5-NEXT: [[TMP38:%.*]] = load float*, float** [[TMP4]], align 8, !dbg [[DBG83]], !llvm.access.group !82 5821 // CHECK5-NEXT: [[TMP39:%.*]] = load i8, i8* [[I7]], align 1, !dbg [[DBG83]], !llvm.access.group !82 5822 // CHECK5-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP39]] to i64, !dbg [[DBG83]] 5823 // CHECK5-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP38]], i64 [[IDXPROM27]], !dbg [[DBG83]] 5824 // CHECK5-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !dbg [[DBG83]], !llvm.access.group !82 5825 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG84:![0-9]+]] 5826 // CHECK5: omp.body.continue: 5827 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG79]] 5828 // CHECK5: omp.inner.for.inc: 5829 // CHECK5-NEXT: [[TMP40:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 5830 // CHECK5-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP40]], 1, !dbg [[DBG80]] 5831 // CHECK5-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !dbg [[DBG80]], !llvm.access.group !82 5832 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP85:![0-9]+]] 5833 // CHECK5: omp.inner.for.end: 5834 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG79]] 5835 // CHECK5: omp.dispatch.inc: 5836 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG79]], !llvm.loop [[LOOP87:![0-9]+]] 5837 // CHECK5: omp.dispatch.end: 5838 // CHECK5-NEXT: br label [[OMP_PRECOND_END]], !dbg [[DBG79]] 5839 // CHECK5: omp.precond.end: 5840 // CHECK5-NEXT: ret void, !dbg [[DBG84]] 5841 // 5842 // 5843 // CHECK5-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 5844 // CHECK5-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] !dbg [[DBG88:![0-9]+]] { 5845 // CHECK5-NEXT: entry: 5846 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5847 // CHECK5-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 5848 // CHECK5-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 5849 // CHECK5-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 5850 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5851 // CHECK5-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 8 5852 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5853 // CHECK5-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 5854 // CHECK5-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 5855 // CHECK5-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 5856 // CHECK5-NEXT: store i32 0, i32* [[X]], align 4, !dbg [[DBG89:![0-9]+]] 5857 // CHECK5-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG90:![0-9]+]] 5858 // CHECK5-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8, !dbg [[DBG90]] 5859 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG90]] 5860 // CHECK5-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8, !dbg [[DBG90]] 5861 // CHECK5-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG90]] 5862 // CHECK5-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8, !dbg [[DBG90]] 5863 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3, !dbg [[DBG90]] 5864 // CHECK5-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8, !dbg [[DBG90]] 5865 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB27:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.6*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]]), !dbg [[DBG90]] 5866 // CHECK5-NEXT: ret void, !dbg [[DBG91:![0-9]+]] 5867 // 5868 // 5869 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..7 5870 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] !dbg [[DBG92:![0-9]+]] { 5871 // CHECK5-NEXT: entry: 5872 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 5873 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 5874 // CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.6*, align 8 5875 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 5876 // CHECK5-NEXT: [[TMP:%.*]] = alloca i8, align 1 5877 // CHECK5-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 5878 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 5879 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 5880 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 5881 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 5882 // CHECK5-NEXT: [[I:%.*]] = alloca i8, align 1 5883 // CHECK5-NEXT: [[X:%.*]] = alloca i32, align 4 5884 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 5885 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 5886 // CHECK5-NEXT: store %struct.anon.6* [[__CONTEXT]], %struct.anon.6** [[__CONTEXT_ADDR]], align 8 5887 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG93:![0-9]+]] 5888 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], %struct.anon.6* [[TMP0]], i32 0, i32 0, !dbg [[DBG93]] 5889 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8, !dbg [[DBG93]] 5890 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 1, !dbg [[DBG93]] 5891 // CHECK5-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8, !dbg [[DBG93]] 5892 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 2, !dbg [[DBG93]] 5893 // CHECK5-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8, !dbg [[DBG93]] 5894 // CHECK5-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 3, !dbg [[DBG93]] 5895 // CHECK5-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8, !dbg [[DBG93]] 5896 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG94:![0-9]+]] 5897 // CHECK5-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG94]] 5898 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG94]] 5899 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG94]] 5900 // CHECK5-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG93]] 5901 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4, !dbg [[DBG93]] 5902 // CHECK5-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB27]], i32 [[TMP10]], i32 1073741861, i32 0, i32 199, i32 1, i32 1), !dbg [[DBG93]] 5903 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG93]] 5904 // CHECK5: omp.dispatch.cond: 5905 // CHECK5-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB27]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]), !dbg [[DBG93]] 5906 // CHECK5-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0, !dbg [[DBG93]] 5907 // CHECK5-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG93]] 5908 // CHECK5: omp.dispatch.body: 5909 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG94]] 5910 // CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]] 5911 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG93]] 5912 // CHECK5: omp.inner.for.cond: 5913 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 5914 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG94]], !llvm.access.group !95 5915 // CHECK5-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]], !dbg [[DBG94]] 5916 // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG93]] 5917 // CHECK5: omp.inner.for.body: 5918 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 5919 // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP15]], 20, !dbg [[DBG94]] 5920 // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1, !dbg [[DBG94]] 5921 // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]], !dbg [[DBG94]] 5922 // CHECK5-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8, !dbg [[DBG94]] 5923 // CHECK5-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !dbg [[DBG94]], !llvm.access.group !95 5924 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 5925 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 5926 // CHECK5-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP17]], 20, !dbg [[DBG94]] 5927 // CHECK5-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20, !dbg [[DBG94]] 5928 // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP16]], [[MUL3]], !dbg [[DBG94]] 5929 // CHECK5-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1, !dbg [[DBG96:![0-9]+]] 5930 // CHECK5-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]], !dbg [[DBG96]] 5931 // CHECK5-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !dbg [[DBG96]], !llvm.access.group !95 5932 // CHECK5-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP4]], align 8, !dbg [[DBG97:![0-9]+]], !llvm.access.group !95 5933 // CHECK5-NEXT: [[TMP19:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95 5934 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP19]] to i64, !dbg [[DBG97]] 5935 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM]], !dbg [[DBG97]] 5936 // CHECK5-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG97]], !llvm.access.group !95 5937 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP6]], align 8, !dbg [[DBG97]], !llvm.access.group !95 5938 // CHECK5-NEXT: [[TMP22:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95 5939 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP22]] to i64, !dbg [[DBG97]] 5940 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]], !dbg [[DBG97]] 5941 // CHECK5-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG97]], !llvm.access.group !95 5942 // CHECK5-NEXT: [[MUL8:%.*]] = fmul float [[TMP20]], [[TMP23]], !dbg [[DBG97]] 5943 // CHECK5-NEXT: [[TMP24:%.*]] = load float*, float** [[TMP8]], align 8, !dbg [[DBG97]], !llvm.access.group !95 5944 // CHECK5-NEXT: [[TMP25:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95 5945 // CHECK5-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP25]] to i64, !dbg [[DBG97]] 5946 // CHECK5-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM9]], !dbg [[DBG97]] 5947 // CHECK5-NEXT: [[TMP26:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !dbg [[DBG97]], !llvm.access.group !95 5948 // CHECK5-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP26]], !dbg [[DBG97]] 5949 // CHECK5-NEXT: [[TMP27:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG97]], !llvm.access.group !95 5950 // CHECK5-NEXT: [[TMP28:%.*]] = load i8, i8* [[I]], align 1, !dbg [[DBG97]], !llvm.access.group !95 5951 // CHECK5-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP28]] to i64, !dbg [[DBG97]] 5952 // CHECK5-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP27]], i64 [[IDXPROM12]], !dbg [[DBG97]] 5953 // CHECK5-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !dbg [[DBG97]], !llvm.access.group !95 5954 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG98:![0-9]+]] 5955 // CHECK5: omp.body.continue: 5956 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG93]] 5957 // CHECK5: omp.inner.for.inc: 5958 // CHECK5-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 5959 // CHECK5-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP29]], 1, !dbg [[DBG94]] 5960 // CHECK5-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG94]], !llvm.access.group !95 5961 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP99:![0-9]+]] 5962 // CHECK5: omp.inner.for.end: 5963 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG93]] 5964 // CHECK5: omp.dispatch.inc: 5965 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG93]], !llvm.loop [[LOOP101:![0-9]+]] 5966 // CHECK5: omp.dispatch.end: 5967 // CHECK5-NEXT: ret void, !dbg [[DBG98]] 5968 // 5969 // 5970 // CHECK5-LABEL: define {{[^@]+}}@_Z3foov 5971 // CHECK5-SAME: () #[[ATTR3:[0-9]+]] !dbg [[DBG102:![0-9]+]] { 5972 // CHECK5-NEXT: entry: 5973 // CHECK5-NEXT: call void @_Z8mayThrowv(), !dbg [[DBG103:![0-9]+]] 5974 // CHECK5-NEXT: ret i32 0, !dbg [[DBG103]] 5975 // 5976 // 5977 // CHECK5-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 5978 // CHECK5-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] !dbg [[DBG104:![0-9]+]] { 5979 // CHECK5-NEXT: entry: 5980 // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 5981 // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 5982 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 5983 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 5984 // CHECK5-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_7:%.*]], align 8 5985 // CHECK5-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 5986 // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 5987 // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG105:![0-9]+]] 5988 // CHECK5-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64, !dbg [[DBG105]] 5989 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG105]] 5990 // CHECK5-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG105]] 5991 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16, !dbg [[DBG105]] 5992 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG105]] 5993 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0, !dbg [[DBG106:![0-9]+]] 5994 // CHECK5-NEXT: store float** [[A_ADDR]], float*** [[TMP3]], align 8, !dbg [[DBG106]] 5995 // CHECK5-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1, !dbg [[DBG106]] 5996 // CHECK5-NEXT: store i64 [[TMP1]], i64* [[TMP4]], align 8, !dbg [[DBG106]] 5997 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2, !dbg [[DBG106]] 5998 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4, !dbg [[DBG107:![0-9]+]] 5999 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[TMP5]], align 8, !dbg [[DBG106]] 6000 // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB32:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.7*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]]), !dbg [[DBG106]] 6001 // CHECK5-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG108:![0-9]+]] 6002 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]), !dbg [[DBG108]] 6003 // CHECK5-NEXT: ret void, !dbg [[DBG108]] 6004 // 6005 // 6006 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..8 6007 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] personality i8* bitcast (i32 (...)* @__gxx_personality_v0 to i8*) !dbg [[DBG109:![0-9]+]] { 6008 // CHECK5-NEXT: entry: 6009 // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6010 // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6011 // CHECK5-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.7*, align 8 6012 // CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 6013 // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6014 // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 6015 // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6016 // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6017 // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6018 // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6019 // CHECK5-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 6020 // CHECK5-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 6021 // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 6022 // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6023 // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6024 // CHECK5-NEXT: store %struct.anon.7* [[__CONTEXT]], %struct.anon.7** [[__CONTEXT_ADDR]], align 8 6025 // CHECK5-NEXT: [[TMP0:%.*]] = load %struct.anon.7*, %struct.anon.7** [[__CONTEXT_ADDR]], align 8, !dbg [[DBG110:![0-9]+]] 6026 // CHECK5-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], %struct.anon.7* [[TMP0]], i32 0, i32 0, !dbg [[DBG110]] 6027 // CHECK5-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8, !dbg [[DBG110]] 6028 // CHECK5-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 1, !dbg [[DBG110]] 6029 // CHECK5-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 8, !dbg [[DBG110]] 6030 // CHECK5-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 2, !dbg [[DBG110]] 6031 // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 8, !dbg [[DBG110]] 6032 // CHECK5-NEXT: store i32 [[TMP6]], i32* [[N]], align 4, !dbg [[DBG110]] 6033 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG111:![0-9]+]] 6034 // CHECK5-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG111]] 6035 // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG111]] 6036 // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4, !dbg [[DBG111]] 6037 // CHECK5-NEXT: [[TMP7:%.*]] = call i8* @llvm.stacksave(), !dbg [[DBG110]] 6038 // CHECK5-NEXT: store i8* [[TMP7]], i8** [[SAVED_STACK]], align 8, !dbg [[DBG110]] 6039 // CHECK5-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP4]], align 16, !dbg [[DBG110]] 6040 // CHECK5-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR0]], align 8, !dbg [[DBG110]] 6041 // CHECK5-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8, !dbg [[DBG110]] 6042 // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4, !dbg [[DBG110]] 6043 // CHECK5-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB29:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5), !dbg [[DBG110]] 6044 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND:%.*]], !dbg [[DBG110]] 6045 // CHECK5: omp.dispatch.cond: 6046 // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG111]] 6047 // CHECK5-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP10]], 16908288, !dbg [[DBG111]] 6048 // CHECK5-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]], !dbg [[DBG111]] 6049 // CHECK5: cond.true: 6050 // CHECK5-NEXT: br label [[COND_END:%.*]], !dbg [[DBG111]] 6051 // CHECK5: cond.false: 6052 // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG111]] 6053 // CHECK5-NEXT: br label [[COND_END]], !dbg [[DBG111]] 6054 // CHECK5: cond.end: 6055 // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ], !dbg [[DBG111]] 6056 // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG111]] 6057 // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG111]] 6058 // CHECK5-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG111]] 6059 // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG111]] 6060 // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG111]] 6061 // CHECK5-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP13]], [[TMP14]], !dbg [[DBG111]] 6062 // CHECK5-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]], !dbg [[DBG110]] 6063 // CHECK5: omp.dispatch.cleanup: 6064 // CHECK5-NEXT: br label [[OMP_DISPATCH_END:%.*]], !dbg [[DBG110]] 6065 // CHECK5: omp.dispatch.body: 6066 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]], !dbg [[DBG110]] 6067 // CHECK5: omp.inner.for.cond: 6068 // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG111]] 6069 // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG111]] 6070 // CHECK5-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP15]], [[TMP16]], !dbg [[DBG111]] 6071 // CHECK5-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]], !dbg [[DBG110]] 6072 // CHECK5: omp.inner.for.cond.cleanup: 6073 // CHECK5-NEXT: br label [[OMP_INNER_FOR_END:%.*]], !dbg [[DBG110]] 6074 // CHECK5: omp.inner.for.body: 6075 // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG111]] 6076 // CHECK5-NEXT: [[MUL:%.*]] = mul i32 [[TMP17]], 127, !dbg [[DBG111]] 6077 // CHECK5-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]], !dbg [[DBG111]] 6078 // CHECK5-NEXT: store i32 [[ADD]], i32* [[I]], align 4, !dbg [[DBG111]] 6079 // CHECK5-NEXT: [[CALL:%.*]] = invoke i32 @_Z3foov() 6080 // CHECK5-NEXT: to label [[INVOKE_CONT:%.*]] unwind label [[TERMINATE_LPAD:%.*]], !dbg [[DBG112:![0-9]+]] 6081 // CHECK5: invoke.cont: 6082 // CHECK5-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float, !dbg [[DBG112]] 6083 // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG112]] 6084 // CHECK5-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP18]] to i64, !dbg [[DBG112]] 6085 // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 [[IDXPROM]], !dbg [[DBG112]] 6086 // CHECK5-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4, !dbg [[DBG112]] 6087 // CHECK5-NEXT: [[ADD3:%.*]] = fadd float [[CONV]], [[TMP19]], !dbg [[DBG112]] 6088 // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[N]], align 4, !dbg [[DBG112]] 6089 // CHECK5-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP20]] to float, !dbg [[DBG112]] 6090 // CHECK5-NEXT: [[ADD5:%.*]] = fadd float [[ADD3]], [[CONV4]], !dbg [[DBG112]] 6091 // CHECK5-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP2]], align 8, !dbg [[DBG112]] 6092 // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4, !dbg [[DBG112]] 6093 // CHECK5-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP22]] to i64, !dbg [[DBG112]] 6094 // CHECK5-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]], !dbg [[DBG112]] 6095 // CHECK5-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !dbg [[DBG112]] 6096 // CHECK5-NEXT: [[ADD8:%.*]] = fadd float [[TMP23]], [[ADD5]], !dbg [[DBG112]] 6097 // CHECK5-NEXT: store float [[ADD8]], float* [[ARRAYIDX7]], align 4, !dbg [[DBG112]] 6098 // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]], !dbg [[DBG112]] 6099 // CHECK5: omp.body.continue: 6100 // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]], !dbg [[DBG110]] 6101 // CHECK5: omp.inner.for.inc: 6102 // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !dbg [[DBG111]] 6103 // CHECK5-NEXT: [[ADD9:%.*]] = add i32 [[TMP24]], 1, !dbg [[DBG111]] 6104 // CHECK5-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4, !dbg [[DBG111]] 6105 // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]], !dbg [[DBG110]], !llvm.loop [[LOOP113:![0-9]+]] 6106 // CHECK5: omp.inner.for.end: 6107 // CHECK5-NEXT: br label [[OMP_DISPATCH_INC:%.*]], !dbg [[DBG110]] 6108 // CHECK5: omp.dispatch.inc: 6109 // CHECK5-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4, !dbg [[DBG111]] 6110 // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG111]] 6111 // CHECK5-NEXT: [[ADD10:%.*]] = add i32 [[TMP25]], [[TMP26]], !dbg [[DBG111]] 6112 // CHECK5-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4, !dbg [[DBG111]] 6113 // CHECK5-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !dbg [[DBG111]] 6114 // CHECK5-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4, !dbg [[DBG111]] 6115 // CHECK5-NEXT: [[ADD11:%.*]] = add i32 [[TMP27]], [[TMP28]], !dbg [[DBG111]] 6116 // CHECK5-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4, !dbg [[DBG111]] 6117 // CHECK5-NEXT: br label [[OMP_DISPATCH_COND]], !dbg [[DBG110]], !llvm.loop [[LOOP114:![0-9]+]] 6118 // CHECK5: omp.dispatch.end: 6119 // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB31:[0-9]+]], i32 [[TMP9]]), !dbg [[DBG110]] 6120 // CHECK5-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8, !dbg [[DBG110]] 6121 // CHECK5-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]), !dbg [[DBG110]] 6122 // CHECK5-NEXT: ret void, !dbg [[DBG112]] 6123 // CHECK5: terminate.lpad: 6124 // CHECK5-NEXT: [[TMP30:%.*]] = landingpad { i8*, i32 } 6125 // CHECK5-NEXT: catch i8* null, !dbg [[DBG112]] 6126 // CHECK5-NEXT: [[TMP31:%.*]] = extractvalue { i8*, i32 } [[TMP30]], 0, !dbg [[DBG112]] 6127 // CHECK5-NEXT: call void @__clang_call_terminate(i8* [[TMP31]]) #[[ATTR7:[0-9]+]], !dbg [[DBG112]] 6128 // CHECK5-NEXT: unreachable, !dbg [[DBG112]] 6129 // 6130 // 6131 // CHECK5-LABEL: define {{[^@]+}}@__clang_call_terminate 6132 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR6:[0-9]+]] { 6133 // CHECK5-NEXT: [[TMP2:%.*]] = call i8* @__cxa_begin_catch(i8* [[TMP0]]) #[[ATTR2:[0-9]+]] 6134 // CHECK5-NEXT: call void @_ZSt9terminatev() #[[ATTR7]] 6135 // CHECK5-NEXT: unreachable 6136 // 6137 // 6138 // CHECK6-LABEL: define {{[^@]+}}@_Z17with_var_schedulev 6139 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] { 6140 // CHECK6-NEXT: entry: 6141 // CHECK6-NEXT: [[A:%.*]] = alloca double, align 8 6142 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6143 // CHECK6-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 1 6144 // CHECK6-NEXT: store double 5.000000e+00, double* [[A]], align 8 6145 // CHECK6-NEXT: [[TMP0:%.*]] = load double, double* [[A]], align 8 6146 // CHECK6-NEXT: [[CONV:%.*]] = fptosi double [[TMP0]] to i8 6147 // CHECK6-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 6148 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 6149 // CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6150 // CHECK6-NEXT: store i8 [[TMP2]], i8* [[TMP1]], align 1 6151 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 6152 // CHECK6-NEXT: ret void 6153 // 6154 // 6155 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined. 6156 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR1:[0-9]+]] { 6157 // CHECK6-NEXT: entry: 6158 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6159 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6160 // CHECK6-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 6161 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6162 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6163 // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 6164 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca double, align 8 6165 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 6166 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 6167 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6168 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6169 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6170 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6171 // CHECK6-NEXT: [[A:%.*]] = alloca double, align 8 6172 // CHECK6-NEXT: [[I4:%.*]] = alloca i64, align 8 6173 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6174 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6175 // CHECK6-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 6176 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 6177 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 6178 // CHECK6-NEXT: [[TMP2:%.*]] = load i8, i8* [[TMP1]], align 1 6179 // CHECK6-NEXT: store i8 [[TMP2]], i8* [[DOTCAPTURE_EXPR_]], align 1 6180 // CHECK6-NEXT: [[TMP3:%.*]] = load double, double* undef, align 8 6181 // CHECK6-NEXT: [[ADD:%.*]] = fadd double 2.000000e+00, [[TMP3]] 6182 // CHECK6-NEXT: store double [[ADD]], double* [[DOTCAPTURE_EXPR_1]], align 8 6183 // CHECK6-NEXT: [[TMP4:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 6184 // CHECK6-NEXT: [[SUB:%.*]] = fsub double [[TMP4]], 1.000000e+00 6185 // CHECK6-NEXT: [[DIV:%.*]] = fdiv double [[SUB]], 1.000000e+00 6186 // CHECK6-NEXT: [[CONV:%.*]] = fptoui double [[DIV]] to i64 6187 // CHECK6-NEXT: [[SUB3:%.*]] = sub i64 [[CONV]], 1 6188 // CHECK6-NEXT: store i64 [[SUB3]], i64* [[DOTCAPTURE_EXPR_2]], align 8 6189 // CHECK6-NEXT: store i64 1, i64* [[I]], align 8 6190 // CHECK6-NEXT: [[TMP5:%.*]] = load double, double* [[DOTCAPTURE_EXPR_1]], align 8 6191 // CHECK6-NEXT: [[CMP:%.*]] = fcmp olt double 1.000000e+00, [[TMP5]] 6192 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 6193 // CHECK6: omp.precond.then: 6194 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6195 // CHECK6-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 6196 // CHECK6-NEXT: store i64 [[TMP6]], i64* [[DOTOMP_UB]], align 8 6197 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6198 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6199 // CHECK6-NEXT: [[TMP7:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6200 // CHECK6-NEXT: [[CONV5:%.*]] = sext i8 [[TMP7]] to i64 6201 // CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6202 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 6203 // CHECK6-NEXT: call void @__kmpc_for_static_init_8u(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 [[CONV5]]) 6204 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6205 // CHECK6: omp.dispatch.cond: 6206 // CHECK6-NEXT: [[TMP10:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6207 // CHECK6-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 6208 // CHECK6-NEXT: [[CMP6:%.*]] = icmp ugt i64 [[TMP10]], [[TMP11]] 6209 // CHECK6-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6210 // CHECK6: cond.true: 6211 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 6212 // CHECK6-NEXT: br label [[COND_END:%.*]] 6213 // CHECK6: cond.false: 6214 // CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6215 // CHECK6-NEXT: br label [[COND_END]] 6216 // CHECK6: cond.end: 6217 // CHECK6-NEXT: [[COND:%.*]] = phi i64 [ [[TMP12]], [[COND_TRUE]] ], [ [[TMP13]], [[COND_FALSE]] ] 6218 // CHECK6-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 6219 // CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6220 // CHECK6-NEXT: store i64 [[TMP14]], i64* [[DOTOMP_IV]], align 8 6221 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6222 // CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6223 // CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP16]], 1 6224 // CHECK6-NEXT: [[CMP8:%.*]] = icmp ult i64 [[TMP15]], [[ADD7]] 6225 // CHECK6-NEXT: br i1 [[CMP8]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6226 // CHECK6: omp.dispatch.body: 6227 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6228 // CHECK6: omp.inner.for.cond: 6229 // CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6230 // CHECK6-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6231 // CHECK6-NEXT: [[ADD9:%.*]] = add i64 [[TMP18]], 1 6232 // CHECK6-NEXT: [[CMP10:%.*]] = icmp ult i64 [[TMP17]], [[ADD9]] 6233 // CHECK6-NEXT: br i1 [[CMP10]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6234 // CHECK6: omp.inner.for.body: 6235 // CHECK6-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6236 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP19]], 1 6237 // CHECK6-NEXT: [[ADD11:%.*]] = add i64 1, [[MUL]] 6238 // CHECK6-NEXT: store i64 [[ADD11]], i64* [[I4]], align 8 6239 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6240 // CHECK6: omp.body.continue: 6241 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6242 // CHECK6: omp.inner.for.inc: 6243 // CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 6244 // CHECK6-NEXT: [[ADD12:%.*]] = add i64 [[TMP20]], 1 6245 // CHECK6-NEXT: store i64 [[ADD12]], i64* [[DOTOMP_IV]], align 8 6246 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 6247 // CHECK6: omp.inner.for.end: 6248 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6249 // CHECK6: omp.dispatch.inc: 6250 // CHECK6-NEXT: [[TMP21:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6251 // CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 6252 // CHECK6-NEXT: [[ADD13:%.*]] = add i64 [[TMP21]], [[TMP22]] 6253 // CHECK6-NEXT: store i64 [[ADD13]], i64* [[DOTOMP_LB]], align 8 6254 // CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 6255 // CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_STRIDE]], align 8 6256 // CHECK6-NEXT: [[ADD14:%.*]] = add i64 [[TMP23]], [[TMP24]] 6257 // CHECK6-NEXT: store i64 [[ADD14]], i64* [[DOTOMP_UB]], align 8 6258 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 6259 // CHECK6: omp.dispatch.end: 6260 // CHECK6-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6261 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 6262 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) 6263 // CHECK6-NEXT: br label [[OMP_PRECOND_END]] 6264 // CHECK6: omp.precond.end: 6265 // CHECK6-NEXT: ret void 6266 // 6267 // 6268 // CHECK6-LABEL: define {{[^@]+}}@_Z23without_schedule_clausePfS_S_S_ 6269 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6270 // CHECK6-NEXT: entry: 6271 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6272 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6273 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6274 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6275 // CHECK6-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 6276 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6277 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6278 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6279 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6280 // CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 6281 // CHECK6-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 6282 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 6283 // CHECK6-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 6284 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 6285 // CHECK6-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 6286 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 6287 // CHECK6-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 6288 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]]) 6289 // CHECK6-NEXT: ret void 6290 // 6291 // 6292 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..1 6293 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 6294 // CHECK6-NEXT: entry: 6295 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6296 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6297 // CHECK6-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.0*, align 8 6298 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6299 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 6300 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6301 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6302 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6303 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6304 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 6305 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6306 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6307 // CHECK6-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 6308 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 6309 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 6310 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 6311 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 1 6312 // CHECK6-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 6313 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 2 6314 // CHECK6-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 6315 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[TMP0]], i32 0, i32 3 6316 // CHECK6-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 6317 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6318 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 6319 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6320 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6321 // CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6322 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 6323 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6324 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6325 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 6326 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6327 // CHECK6: cond.true: 6328 // CHECK6-NEXT: br label [[COND_END:%.*]] 6329 // CHECK6: cond.false: 6330 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6331 // CHECK6-NEXT: br label [[COND_END]] 6332 // CHECK6: cond.end: 6333 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6334 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6335 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6336 // CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 6337 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6338 // CHECK6: omp.inner.for.cond: 6339 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6340 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6341 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6342 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6343 // CHECK6: omp.inner.for.body: 6344 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6345 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 6346 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 33, [[MUL]] 6347 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6348 // CHECK6-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 6349 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 6350 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 6351 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 6352 // CHECK6-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 6353 // CHECK6-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 6354 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 6355 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 6356 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 6357 // CHECK6-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 6358 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 6359 // CHECK6-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 6360 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 6361 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 6362 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 6363 // CHECK6-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 6364 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 6365 // CHECK6-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 6366 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 6367 // CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 6368 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 6369 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 6370 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6371 // CHECK6: omp.body.continue: 6372 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6373 // CHECK6: omp.inner.for.inc: 6374 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6375 // CHECK6-NEXT: [[ADD10:%.*]] = add nsw i32 [[TMP28]], 1 6376 // CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_IV]], align 4 6377 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 6378 // CHECK6: omp.inner.for.end: 6379 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6380 // CHECK6: omp.loop.exit: 6381 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 6382 // CHECK6-NEXT: ret void 6383 // 6384 // 6385 // CHECK6-LABEL: define {{[^@]+}}@_Z18static_not_chunkedPfS_S_S_ 6386 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6387 // CHECK6-NEXT: entry: 6388 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6389 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6390 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6391 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6392 // CHECK6-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_1:%.*]], align 8 6393 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6394 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6395 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6396 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6397 // CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 6398 // CHECK6-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 6399 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 6400 // CHECK6-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 6401 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 6402 // CHECK6-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 6403 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 6404 // CHECK6-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 6405 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.1*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), %struct.anon.1* [[OMP_OUTLINED_ARG_AGG_]]) 6406 // CHECK6-NEXT: ret void 6407 // 6408 // 6409 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..2 6410 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.1* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 6411 // CHECK6-NEXT: entry: 6412 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6413 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6414 // CHECK6-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.1*, align 8 6415 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6416 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 6417 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6418 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6419 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6420 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6421 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 6422 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6423 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6424 // CHECK6-NEXT: store %struct.anon.1* [[__CONTEXT]], %struct.anon.1** [[__CONTEXT_ADDR]], align 8 6425 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.anon.1*, %struct.anon.1** [[__CONTEXT_ADDR]], align 8 6426 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_1:%.*]], %struct.anon.1* [[TMP0]], i32 0, i32 0 6427 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 6428 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 1 6429 // CHECK6-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 6430 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 2 6431 // CHECK6-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 6432 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_1]], %struct.anon.1* [[TMP0]], i32 0, i32 3 6433 // CHECK6-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 6434 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6435 // CHECK6-NEXT: store i32 4571423, i32* [[DOTOMP_UB]], align 4 6436 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6437 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6438 // CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6439 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 6440 // CHECK6-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 6441 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6442 // CHECK6-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP11]], 4571423 6443 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6444 // CHECK6: cond.true: 6445 // CHECK6-NEXT: br label [[COND_END:%.*]] 6446 // CHECK6: cond.false: 6447 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6448 // CHECK6-NEXT: br label [[COND_END]] 6449 // CHECK6: cond.end: 6450 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 4571423, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6451 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6452 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6453 // CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 6454 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6455 // CHECK6: omp.inner.for.cond: 6456 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6457 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6458 // CHECK6-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] 6459 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6460 // CHECK6: omp.inner.for.body: 6461 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6462 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 7 6463 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 32000000, [[MUL]] 6464 // CHECK6-NEXT: store i32 [[SUB]], i32* [[I]], align 4 6465 // CHECK6-NEXT: [[TMP17:%.*]] = load float*, float** [[TMP4]], align 8 6466 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 6467 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP18]] to i64 6468 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP17]], i64 [[IDXPROM]] 6469 // CHECK6-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 6470 // CHECK6-NEXT: [[TMP20:%.*]] = load float*, float** [[TMP6]], align 8 6471 // CHECK6-NEXT: [[TMP21:%.*]] = load i32, i32* [[I]], align 4 6472 // CHECK6-NEXT: [[IDXPROM2:%.*]] = sext i32 [[TMP21]] to i64 6473 // CHECK6-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds float, float* [[TMP20]], i64 [[IDXPROM2]] 6474 // CHECK6-NEXT: [[TMP22:%.*]] = load float, float* [[ARRAYIDX3]], align 4 6475 // CHECK6-NEXT: [[MUL4:%.*]] = fmul float [[TMP19]], [[TMP22]] 6476 // CHECK6-NEXT: [[TMP23:%.*]] = load float*, float** [[TMP8]], align 8 6477 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[I]], align 4 6478 // CHECK6-NEXT: [[IDXPROM5:%.*]] = sext i32 [[TMP24]] to i64 6479 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP23]], i64 [[IDXPROM5]] 6480 // CHECK6-NEXT: [[TMP25:%.*]] = load float, float* [[ARRAYIDX6]], align 4 6481 // CHECK6-NEXT: [[MUL7:%.*]] = fmul float [[MUL4]], [[TMP25]] 6482 // CHECK6-NEXT: [[TMP26:%.*]] = load float*, float** [[TMP2]], align 8 6483 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[I]], align 4 6484 // CHECK6-NEXT: [[IDXPROM8:%.*]] = sext i32 [[TMP27]] to i64 6485 // CHECK6-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, float* [[TMP26]], i64 [[IDXPROM8]] 6486 // CHECK6-NEXT: store float [[MUL7]], float* [[ARRAYIDX9]], align 4 6487 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6488 // CHECK6: omp.body.continue: 6489 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6490 // CHECK6: omp.inner.for.inc: 6491 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6492 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP28]], 1 6493 // CHECK6-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 6494 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 6495 // CHECK6: omp.inner.for.end: 6496 // CHECK6-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 6497 // CHECK6: omp.loop.exit: 6498 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 6499 // CHECK6-NEXT: ret void 6500 // 6501 // 6502 // CHECK6-LABEL: define {{[^@]+}}@_Z14static_chunkedPfS_S_S_ 6503 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6504 // CHECK6-NEXT: entry: 6505 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6506 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6507 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6508 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6509 // CHECK6-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_2:%.*]], align 8 6510 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6511 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6512 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6513 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6514 // CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 6515 // CHECK6-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 6516 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 6517 // CHECK6-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 6518 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 6519 // CHECK6-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 6520 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 6521 // CHECK6-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 6522 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.2*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), %struct.anon.2* [[OMP_OUTLINED_ARG_AGG_]]) 6523 // CHECK6-NEXT: ret void 6524 // 6525 // 6526 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..3 6527 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.2* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 6528 // CHECK6-NEXT: entry: 6529 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6530 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6531 // CHECK6-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.2*, align 8 6532 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 6533 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 6534 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 6535 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 6536 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 6537 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6538 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 6539 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6540 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6541 // CHECK6-NEXT: store %struct.anon.2* [[__CONTEXT]], %struct.anon.2** [[__CONTEXT_ADDR]], align 8 6542 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.anon.2*, %struct.anon.2** [[__CONTEXT_ADDR]], align 8 6543 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_2:%.*]], %struct.anon.2* [[TMP0]], i32 0, i32 0 6544 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 6545 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 1 6546 // CHECK6-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 6547 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 2 6548 // CHECK6-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 6549 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_2]], %struct.anon.2* [[TMP0]], i32 0, i32 3 6550 // CHECK6-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 6551 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 6552 // CHECK6-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 6553 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 6554 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6555 // CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6556 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 6557 // CHECK6-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 6558 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6559 // CHECK6: omp.dispatch.cond: 6560 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6561 // CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP11]], 16908288 6562 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 6563 // CHECK6: cond.true: 6564 // CHECK6-NEXT: br label [[COND_END:%.*]] 6565 // CHECK6: cond.false: 6566 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6567 // CHECK6-NEXT: br label [[COND_END]] 6568 // CHECK6: cond.end: 6569 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] 6570 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 6571 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6572 // CHECK6-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 6573 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6574 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6575 // CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP14]], [[TMP15]] 6576 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6577 // CHECK6: omp.dispatch.body: 6578 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6579 // CHECK6: omp.inner.for.cond: 6580 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6581 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6582 // CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP16]], [[TMP17]] 6583 // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6584 // CHECK6: omp.inner.for.body: 6585 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6586 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP18]], 127 6587 // CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 6588 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 6589 // CHECK6-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP4]], align 8 6590 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[I]], align 4 6591 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP20]] to i64 6592 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[IDXPROM]] 6593 // CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX]], align 4 6594 // CHECK6-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP6]], align 8 6595 // CHECK6-NEXT: [[TMP23:%.*]] = load i32, i32* [[I]], align 4 6596 // CHECK6-NEXT: [[IDXPROM3:%.*]] = zext i32 [[TMP23]] to i64 6597 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[IDXPROM3]] 6598 // CHECK6-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4 6599 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[TMP21]], [[TMP24]] 6600 // CHECK6-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP8]], align 8 6601 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[I]], align 4 6602 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP26]] to i64 6603 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[IDXPROM6]] 6604 // CHECK6-NEXT: [[TMP27:%.*]] = load float, float* [[ARRAYIDX7]], align 4 6605 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[MUL5]], [[TMP27]] 6606 // CHECK6-NEXT: [[TMP28:%.*]] = load float*, float** [[TMP2]], align 8 6607 // CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[I]], align 4 6608 // CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i32 [[TMP29]] to i64 6609 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP28]], i64 [[IDXPROM9]] 6610 // CHECK6-NEXT: store float [[MUL8]], float* [[ARRAYIDX10]], align 4 6611 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6612 // CHECK6: omp.body.continue: 6613 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6614 // CHECK6: omp.inner.for.inc: 6615 // CHECK6-NEXT: [[TMP30:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 6616 // CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP30]], 1 6617 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_IV]], align 4 6618 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 6619 // CHECK6: omp.inner.for.end: 6620 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6621 // CHECK6: omp.dispatch.inc: 6622 // CHECK6-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 6623 // CHECK6-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6624 // CHECK6-NEXT: [[ADD12:%.*]] = add i32 [[TMP31]], [[TMP32]] 6625 // CHECK6-NEXT: store i32 [[ADD12]], i32* [[DOTOMP_LB]], align 4 6626 // CHECK6-NEXT: [[TMP33:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 6627 // CHECK6-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 6628 // CHECK6-NEXT: [[ADD13:%.*]] = add i32 [[TMP33]], [[TMP34]] 6629 // CHECK6-NEXT: store i32 [[ADD13]], i32* [[DOTOMP_UB]], align 4 6630 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 6631 // CHECK6: omp.dispatch.end: 6632 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]]) 6633 // CHECK6-NEXT: ret void 6634 // 6635 // 6636 // CHECK6-LABEL: define {{[^@]+}}@_Z8dynamic1PfS_S_S_ 6637 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6638 // CHECK6-NEXT: entry: 6639 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6640 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6641 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6642 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6643 // CHECK6-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_3:%.*]], align 8 6644 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6645 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6646 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6647 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6648 // CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 6649 // CHECK6-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 6650 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 6651 // CHECK6-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 6652 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 6653 // CHECK6-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 6654 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 6655 // CHECK6-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 6656 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.3*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), %struct.anon.3* [[OMP_OUTLINED_ARG_AGG_]]) 6657 // CHECK6-NEXT: ret void 6658 // 6659 // 6660 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..4 6661 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.3* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 6662 // CHECK6-NEXT: entry: 6663 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6664 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6665 // CHECK6-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.3*, align 8 6666 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6667 // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 6668 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6669 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6670 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6671 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6672 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 6673 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6674 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6675 // CHECK6-NEXT: store %struct.anon.3* [[__CONTEXT]], %struct.anon.3** [[__CONTEXT_ADDR]], align 8 6676 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.anon.3*, %struct.anon.3** [[__CONTEXT_ADDR]], align 8 6677 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_3:%.*]], %struct.anon.3* [[TMP0]], i32 0, i32 0 6678 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 6679 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 1 6680 // CHECK6-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 6681 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 2 6682 // CHECK6-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 6683 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_3]], %struct.anon.3* [[TMP0]], i32 0, i32 3 6684 // CHECK6-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 6685 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6686 // CHECK6-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 6687 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6688 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6689 // CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6690 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 6691 // CHECK6-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1) 6692 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6693 // CHECK6: omp.dispatch.cond: 6694 // CHECK6-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 6695 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 6696 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6697 // CHECK6: omp.dispatch.body: 6698 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6699 // CHECK6-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 6700 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6701 // CHECK6: omp.inner.for.cond: 6702 // CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 6703 // CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !5 6704 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 6705 // CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 6706 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6707 // CHECK6: omp.inner.for.body: 6708 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 6709 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 6710 // CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 6711 // CHECK6-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !5 6712 // CHECK6-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !5 6713 // CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 6714 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 6715 // CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !5 6716 // CHECK6-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !5 6717 // CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 6718 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 6719 // CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !5 6720 // CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 6721 // CHECK6-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !5 6722 // CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 6723 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 6724 // CHECK6-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !5 6725 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 6726 // CHECK6-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !5 6727 // CHECK6-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !5 6728 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 6729 // CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !5 6730 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6731 // CHECK6: omp.body.continue: 6732 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6733 // CHECK6: omp.inner.for.inc: 6734 // CHECK6-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 6735 // CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 6736 // CHECK6-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !5 6737 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]] 6738 // CHECK6: omp.inner.for.end: 6739 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6740 // CHECK6: omp.dispatch.inc: 6741 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 6742 // CHECK6: omp.dispatch.end: 6743 // CHECK6-NEXT: ret void 6744 // 6745 // 6746 // CHECK6-LABEL: define {{[^@]+}}@_Z7guided7PfS_S_S_ 6747 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6748 // CHECK6-NEXT: entry: 6749 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6750 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6751 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6752 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6753 // CHECK6-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_4:%.*]], align 8 6754 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6755 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6756 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6757 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6758 // CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 6759 // CHECK6-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 6760 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 6761 // CHECK6-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 6762 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 6763 // CHECK6-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 6764 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 6765 // CHECK6-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 6766 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.4*)* @.omp_outlined..5 to void (i32*, i32*, ...)*), %struct.anon.4* [[OMP_OUTLINED_ARG_AGG_]]) 6767 // CHECK6-NEXT: ret void 6768 // 6769 // 6770 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..5 6771 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.4* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 6772 // CHECK6-NEXT: entry: 6773 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6774 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6775 // CHECK6-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.4*, align 8 6776 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6777 // CHECK6-NEXT: [[TMP:%.*]] = alloca i64, align 8 6778 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6779 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6780 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6781 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6782 // CHECK6-NEXT: [[I:%.*]] = alloca i64, align 8 6783 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6784 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6785 // CHECK6-NEXT: store %struct.anon.4* [[__CONTEXT]], %struct.anon.4** [[__CONTEXT_ADDR]], align 8 6786 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.anon.4*, %struct.anon.4** [[__CONTEXT_ADDR]], align 8 6787 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_4:%.*]], %struct.anon.4* [[TMP0]], i32 0, i32 0 6788 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 6789 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 1 6790 // CHECK6-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 6791 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 2 6792 // CHECK6-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 6793 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_4]], %struct.anon.4* [[TMP0]], i32 0, i32 3 6794 // CHECK6-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 6795 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6796 // CHECK6-NEXT: store i64 16908287, i64* [[DOTOMP_UB]], align 8 6797 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6798 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6799 // CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6800 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 6801 // CHECK6-NEXT: call void @__kmpc_dispatch_init_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7) 6802 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6803 // CHECK6: omp.dispatch.cond: 6804 // CHECK6-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_8u(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 6805 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 6806 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6807 // CHECK6: omp.dispatch.body: 6808 // CHECK6-NEXT: [[TMP12:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6809 // CHECK6-NEXT: store i64 [[TMP12]], i64* [[DOTOMP_IV]], align 8 6810 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6811 // CHECK6: omp.inner.for.cond: 6812 // CHECK6-NEXT: [[TMP13:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 6813 // CHECK6-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !8 6814 // CHECK6-NEXT: [[ADD:%.*]] = add i64 [[TMP14]], 1 6815 // CHECK6-NEXT: [[CMP:%.*]] = icmp ult i64 [[TMP13]], [[ADD]] 6816 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6817 // CHECK6: omp.inner.for.body: 6818 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 6819 // CHECK6-NEXT: [[MUL:%.*]] = mul i64 [[TMP15]], 127 6820 // CHECK6-NEXT: [[ADD1:%.*]] = add i64 131071, [[MUL]] 6821 // CHECK6-NEXT: store i64 [[ADD1]], i64* [[I]], align 8, !llvm.access.group !8 6822 // CHECK6-NEXT: [[TMP16:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !8 6823 // CHECK6-NEXT: [[TMP17:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 6824 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP16]], i64 [[TMP17]] 6825 // CHECK6-NEXT: [[TMP18:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !8 6826 // CHECK6-NEXT: [[TMP19:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !8 6827 // CHECK6-NEXT: [[TMP20:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 6828 // CHECK6-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds float, float* [[TMP19]], i64 [[TMP20]] 6829 // CHECK6-NEXT: [[TMP21:%.*]] = load float, float* [[ARRAYIDX2]], align 4, !llvm.access.group !8 6830 // CHECK6-NEXT: [[MUL3:%.*]] = fmul float [[TMP18]], [[TMP21]] 6831 // CHECK6-NEXT: [[TMP22:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !8 6832 // CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 6833 // CHECK6-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds float, float* [[TMP22]], i64 [[TMP23]] 6834 // CHECK6-NEXT: [[TMP24:%.*]] = load float, float* [[ARRAYIDX4]], align 4, !llvm.access.group !8 6835 // CHECK6-NEXT: [[MUL5:%.*]] = fmul float [[MUL3]], [[TMP24]] 6836 // CHECK6-NEXT: [[TMP25:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !8 6837 // CHECK6-NEXT: [[TMP26:%.*]] = load i64, i64* [[I]], align 8, !llvm.access.group !8 6838 // CHECK6-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds float, float* [[TMP25]], i64 [[TMP26]] 6839 // CHECK6-NEXT: store float [[MUL5]], float* [[ARRAYIDX6]], align 4, !llvm.access.group !8 6840 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 6841 // CHECK6: omp.body.continue: 6842 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 6843 // CHECK6: omp.inner.for.inc: 6844 // CHECK6-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 6845 // CHECK6-NEXT: [[ADD7:%.*]] = add i64 [[TMP27]], 1 6846 // CHECK6-NEXT: store i64 [[ADD7]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !8 6847 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP9:![0-9]+]] 6848 // CHECK6: omp.inner.for.end: 6849 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 6850 // CHECK6: omp.dispatch.inc: 6851 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 6852 // CHECK6: omp.dispatch.end: 6853 // CHECK6-NEXT: ret void 6854 // 6855 // 6856 // CHECK6-LABEL: define {{[^@]+}}@_Z9test_autoPfS_S_S_ 6857 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 6858 // CHECK6-NEXT: entry: 6859 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 6860 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 6861 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 6862 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 6863 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 6864 // CHECK6-NEXT: [[Y:%.*]] = alloca i32, align 4 6865 // CHECK6-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_5:%.*]], align 8 6866 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 6867 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 6868 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 6869 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 6870 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 6871 // CHECK6-NEXT: store i32 0, i32* [[Y]], align 4 6872 // CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 6873 // CHECK6-NEXT: store i32* [[Y]], i32** [[TMP0]], align 8 6874 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 6875 // CHECK6-NEXT: store float** [[A_ADDR]], float*** [[TMP1]], align 8 6876 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 6877 // CHECK6-NEXT: store float** [[B_ADDR]], float*** [[TMP2]], align 8 6878 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 6879 // CHECK6-NEXT: store float** [[C_ADDR]], float*** [[TMP3]], align 8 6880 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 4 6881 // CHECK6-NEXT: store float** [[D_ADDR]], float*** [[TMP4]], align 8 6882 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.5*)* @.omp_outlined..6 to void (i32*, i32*, ...)*), %struct.anon.5* [[OMP_OUTLINED_ARG_AGG_]]) 6883 // CHECK6-NEXT: ret void 6884 // 6885 // 6886 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..6 6887 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.5* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 6888 // CHECK6-NEXT: entry: 6889 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 6890 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 6891 // CHECK6-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.5*, align 8 6892 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 6893 // CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1 6894 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 6895 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i8, align 1 6896 // CHECK6-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i64, align 8 6897 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 6898 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 6899 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 6900 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 6901 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 6902 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 6903 // CHECK6-NEXT: [[I7:%.*]] = alloca i8, align 1 6904 // CHECK6-NEXT: [[X8:%.*]] = alloca i32, align 4 6905 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 6906 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 6907 // CHECK6-NEXT: store %struct.anon.5* [[__CONTEXT]], %struct.anon.5** [[__CONTEXT_ADDR]], align 8 6908 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.anon.5*, %struct.anon.5** [[__CONTEXT_ADDR]], align 8 6909 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_5:%.*]], %struct.anon.5* [[TMP0]], i32 0, i32 0 6910 // CHECK6-NEXT: [[TMP2:%.*]] = load i32*, i32** [[TMP1]], align 8 6911 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 1 6912 // CHECK6-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 6913 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 2 6914 // CHECK6-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 6915 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 3 6916 // CHECK6-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 6917 // CHECK6-NEXT: [[TMP9:%.*]] = getelementptr inbounds [[STRUCT_ANON_5]], %struct.anon.5* [[TMP0]], i32 0, i32 4 6918 // CHECK6-NEXT: [[TMP10:%.*]] = load float**, float*** [[TMP9]], align 8 6919 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[TMP2]], align 4 6920 // CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[TMP11]] to i8 6921 // CHECK6-NEXT: store i8 [[CONV]], i8* [[DOTCAPTURE_EXPR_]], align 1 6922 // CHECK6-NEXT: [[TMP12:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6923 // CHECK6-NEXT: [[CONV3:%.*]] = sext i8 [[TMP12]] to i32 6924 // CHECK6-NEXT: [[SUB:%.*]] = sub i32 57, [[CONV3]] 6925 // CHECK6-NEXT: [[ADD:%.*]] = add i32 [[SUB]], 1 6926 // CHECK6-NEXT: [[DIV:%.*]] = udiv i32 [[ADD]], 1 6927 // CHECK6-NEXT: [[CONV4:%.*]] = zext i32 [[DIV]] to i64 6928 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i64 [[CONV4]], 11 6929 // CHECK6-NEXT: [[SUB5:%.*]] = sub nsw i64 [[MUL]], 1 6930 // CHECK6-NEXT: store i64 [[SUB5]], i64* [[DOTCAPTURE_EXPR_2]], align 8 6931 // CHECK6-NEXT: [[TMP13:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6932 // CHECK6-NEXT: store i8 [[TMP13]], i8* [[I]], align 1 6933 // CHECK6-NEXT: store i32 11, i32* [[X]], align 4 6934 // CHECK6-NEXT: [[TMP14:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1 6935 // CHECK6-NEXT: [[CONV6:%.*]] = sext i8 [[TMP14]] to i32 6936 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[CONV6]], 57 6937 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 6938 // CHECK6: omp.precond.then: 6939 // CHECK6-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 6940 // CHECK6-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 6941 // CHECK6-NEXT: store i64 [[TMP15]], i64* [[DOTOMP_UB]], align 8 6942 // CHECK6-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 6943 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 6944 // CHECK6-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_2]], align 8 6945 // CHECK6-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6946 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[TMP17]], align 4 6947 // CHECK6-NEXT: call void @__kmpc_dispatch_init_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP18]], i32 1073741862, i64 0, i64 [[TMP16]], i64 1, i64 1) 6948 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 6949 // CHECK6: omp.dispatch.cond: 6950 // CHECK6-NEXT: [[TMP19:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 6951 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[TMP19]], align 4 6952 // CHECK6-NEXT: [[TMP21:%.*]] = call i32 @__kmpc_dispatch_next_8(%struct.ident_t* @[[GLOB2]], i32 [[TMP20]], i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]]) 6953 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP21]], 0 6954 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 6955 // CHECK6: omp.dispatch.body: 6956 // CHECK6-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 6957 // CHECK6-NEXT: store i64 [[TMP22]], i64* [[DOTOMP_IV]], align 8 6958 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 6959 // CHECK6: omp.inner.for.cond: 6960 // CHECK6-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 6961 // CHECK6-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8, !llvm.access.group !11 6962 // CHECK6-NEXT: [[CMP9:%.*]] = icmp sle i64 [[TMP23]], [[TMP24]] 6963 // CHECK6-NEXT: br i1 [[CMP9]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 6964 // CHECK6: omp.inner.for.body: 6965 // CHECK6-NEXT: [[TMP25:%.*]] = load i8, i8* [[DOTCAPTURE_EXPR_]], align 1, !llvm.access.group !11 6966 // CHECK6-NEXT: [[CONV10:%.*]] = sext i8 [[TMP25]] to i64 6967 // CHECK6-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 6968 // CHECK6-NEXT: [[DIV11:%.*]] = sdiv i64 [[TMP26]], 11 6969 // CHECK6-NEXT: [[MUL12:%.*]] = mul nsw i64 [[DIV11]], 1 6970 // CHECK6-NEXT: [[ADD13:%.*]] = add nsw i64 [[CONV10]], [[MUL12]] 6971 // CHECK6-NEXT: [[CONV14:%.*]] = trunc i64 [[ADD13]] to i8 6972 // CHECK6-NEXT: store i8 [[CONV14]], i8* [[I7]], align 1, !llvm.access.group !11 6973 // CHECK6-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 6974 // CHECK6-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 6975 // CHECK6-NEXT: [[DIV15:%.*]] = sdiv i64 [[TMP28]], 11 6976 // CHECK6-NEXT: [[MUL16:%.*]] = mul nsw i64 [[DIV15]], 11 6977 // CHECK6-NEXT: [[SUB17:%.*]] = sub nsw i64 [[TMP27]], [[MUL16]] 6978 // CHECK6-NEXT: [[MUL18:%.*]] = mul nsw i64 [[SUB17]], 1 6979 // CHECK6-NEXT: [[SUB19:%.*]] = sub nsw i64 11, [[MUL18]] 6980 // CHECK6-NEXT: [[CONV20:%.*]] = trunc i64 [[SUB19]] to i32 6981 // CHECK6-NEXT: store i32 [[CONV20]], i32* [[X8]], align 4, !llvm.access.group !11 6982 // CHECK6-NEXT: [[TMP29:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !11 6983 // CHECK6-NEXT: [[TMP30:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 6984 // CHECK6-NEXT: [[IDXPROM:%.*]] = sext i8 [[TMP30]] to i64 6985 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP29]], i64 [[IDXPROM]] 6986 // CHECK6-NEXT: [[TMP31:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !11 6987 // CHECK6-NEXT: [[TMP32:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !11 6988 // CHECK6-NEXT: [[TMP33:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 6989 // CHECK6-NEXT: [[IDXPROM21:%.*]] = sext i8 [[TMP33]] to i64 6990 // CHECK6-NEXT: [[ARRAYIDX22:%.*]] = getelementptr inbounds float, float* [[TMP32]], i64 [[IDXPROM21]] 6991 // CHECK6-NEXT: [[TMP34:%.*]] = load float, float* [[ARRAYIDX22]], align 4, !llvm.access.group !11 6992 // CHECK6-NEXT: [[MUL23:%.*]] = fmul float [[TMP31]], [[TMP34]] 6993 // CHECK6-NEXT: [[TMP35:%.*]] = load float*, float** [[TMP10]], align 8, !llvm.access.group !11 6994 // CHECK6-NEXT: [[TMP36:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 6995 // CHECK6-NEXT: [[IDXPROM24:%.*]] = sext i8 [[TMP36]] to i64 6996 // CHECK6-NEXT: [[ARRAYIDX25:%.*]] = getelementptr inbounds float, float* [[TMP35]], i64 [[IDXPROM24]] 6997 // CHECK6-NEXT: [[TMP37:%.*]] = load float, float* [[ARRAYIDX25]], align 4, !llvm.access.group !11 6998 // CHECK6-NEXT: [[MUL26:%.*]] = fmul float [[MUL23]], [[TMP37]] 6999 // CHECK6-NEXT: [[TMP38:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !11 7000 // CHECK6-NEXT: [[TMP39:%.*]] = load i8, i8* [[I7]], align 1, !llvm.access.group !11 7001 // CHECK6-NEXT: [[IDXPROM27:%.*]] = sext i8 [[TMP39]] to i64 7002 // CHECK6-NEXT: [[ARRAYIDX28:%.*]] = getelementptr inbounds float, float* [[TMP38]], i64 [[IDXPROM27]] 7003 // CHECK6-NEXT: store float [[MUL26]], float* [[ARRAYIDX28]], align 4, !llvm.access.group !11 7004 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7005 // CHECK6: omp.body.continue: 7006 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7007 // CHECK6: omp.inner.for.inc: 7008 // CHECK6-NEXT: [[TMP40:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 7009 // CHECK6-NEXT: [[ADD29:%.*]] = add nsw i64 [[TMP40]], 1 7010 // CHECK6-NEXT: store i64 [[ADD29]], i64* [[DOTOMP_IV]], align 8, !llvm.access.group !11 7011 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP12:![0-9]+]] 7012 // CHECK6: omp.inner.for.end: 7013 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7014 // CHECK6: omp.dispatch.inc: 7015 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 7016 // CHECK6: omp.dispatch.end: 7017 // CHECK6-NEXT: br label [[OMP_PRECOND_END]] 7018 // CHECK6: omp.precond.end: 7019 // CHECK6-NEXT: ret void 7020 // 7021 // 7022 // CHECK6-LABEL: define {{[^@]+}}@_Z7runtimePfS_S_S_ 7023 // CHECK6-SAME: (float* [[A:%.*]], float* [[B:%.*]], float* [[C:%.*]], float* [[D:%.*]]) #[[ATTR0]] { 7024 // CHECK6-NEXT: entry: 7025 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7026 // CHECK6-NEXT: [[B_ADDR:%.*]] = alloca float*, align 8 7027 // CHECK6-NEXT: [[C_ADDR:%.*]] = alloca float*, align 8 7028 // CHECK6-NEXT: [[D_ADDR:%.*]] = alloca float*, align 8 7029 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 7030 // CHECK6-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_6:%.*]], align 8 7031 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7032 // CHECK6-NEXT: store float* [[B]], float** [[B_ADDR]], align 8 7033 // CHECK6-NEXT: store float* [[C]], float** [[C_ADDR]], align 8 7034 // CHECK6-NEXT: store float* [[D]], float** [[D_ADDR]], align 8 7035 // CHECK6-NEXT: store i32 0, i32* [[X]], align 4 7036 // CHECK6-NEXT: [[TMP0:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 7037 // CHECK6-NEXT: store float** [[A_ADDR]], float*** [[TMP0]], align 8 7038 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 7039 // CHECK6-NEXT: store float** [[B_ADDR]], float*** [[TMP1]], align 8 7040 // CHECK6-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 7041 // CHECK6-NEXT: store float** [[C_ADDR]], float*** [[TMP2]], align 8 7042 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 3 7043 // CHECK6-NEXT: store float** [[D_ADDR]], float*** [[TMP3]], align 8 7044 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.6*)* @.omp_outlined..7 to void (i32*, i32*, ...)*), %struct.anon.6* [[OMP_OUTLINED_ARG_AGG_]]) 7045 // CHECK6-NEXT: ret void 7046 // 7047 // 7048 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..7 7049 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.6* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 7050 // CHECK6-NEXT: entry: 7051 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7052 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7053 // CHECK6-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.6*, align 8 7054 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7055 // CHECK6-NEXT: [[TMP:%.*]] = alloca i8, align 1 7056 // CHECK6-NEXT: [[_TMP1:%.*]] = alloca i32, align 4 7057 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7058 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7059 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7060 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7061 // CHECK6-NEXT: [[I:%.*]] = alloca i8, align 1 7062 // CHECK6-NEXT: [[X:%.*]] = alloca i32, align 4 7063 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7064 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7065 // CHECK6-NEXT: store %struct.anon.6* [[__CONTEXT]], %struct.anon.6** [[__CONTEXT_ADDR]], align 8 7066 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.anon.6*, %struct.anon.6** [[__CONTEXT_ADDR]], align 8 7067 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_6:%.*]], %struct.anon.6* [[TMP0]], i32 0, i32 0 7068 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 7069 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 1 7070 // CHECK6-NEXT: [[TMP4:%.*]] = load float**, float*** [[TMP3]], align 8 7071 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 2 7072 // CHECK6-NEXT: [[TMP6:%.*]] = load float**, float*** [[TMP5]], align 8 7073 // CHECK6-NEXT: [[TMP7:%.*]] = getelementptr inbounds [[STRUCT_ANON_6]], %struct.anon.6* [[TMP0]], i32 0, i32 3 7074 // CHECK6-NEXT: [[TMP8:%.*]] = load float**, float*** [[TMP7]], align 8 7075 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7076 // CHECK6-NEXT: store i32 199, i32* [[DOTOMP_UB]], align 4 7077 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7078 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7079 // CHECK6-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7080 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4 7081 // CHECK6-NEXT: call void @__kmpc_dispatch_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32 1073741861, i32 0, i32 199, i32 1, i32 1) 7082 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7083 // CHECK6: omp.dispatch.cond: 7084 // CHECK6-NEXT: [[TMP11:%.*]] = call i32 @__kmpc_dispatch_next_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP10]], i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]]) 7085 // CHECK6-NEXT: [[TOBOOL:%.*]] = icmp ne i32 [[TMP11]], 0 7086 // CHECK6-NEXT: br i1 [[TOBOOL]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_END:%.*]] 7087 // CHECK6: omp.dispatch.body: 7088 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7089 // CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 7090 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7091 // CHECK6: omp.inner.for.cond: 7092 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 7093 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4, !llvm.access.group !14 7094 // CHECK6-NEXT: [[CMP:%.*]] = icmp sle i32 [[TMP13]], [[TMP14]] 7095 // CHECK6-NEXT: br i1 [[CMP]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7096 // CHECK6: omp.inner.for.body: 7097 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 7098 // CHECK6-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP15]], 20 7099 // CHECK6-NEXT: [[MUL:%.*]] = mul nsw i32 [[DIV]], 1 7100 // CHECK6-NEXT: [[ADD:%.*]] = add nsw i32 48, [[MUL]] 7101 // CHECK6-NEXT: [[CONV:%.*]] = trunc i32 [[ADD]] to i8 7102 // CHECK6-NEXT: store i8 [[CONV]], i8* [[I]], align 1, !llvm.access.group !14 7103 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 7104 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 7105 // CHECK6-NEXT: [[DIV2:%.*]] = sdiv i32 [[TMP17]], 20 7106 // CHECK6-NEXT: [[MUL3:%.*]] = mul nsw i32 [[DIV2]], 20 7107 // CHECK6-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP16]], [[MUL3]] 7108 // CHECK6-NEXT: [[MUL4:%.*]] = mul nsw i32 [[SUB]], 1 7109 // CHECK6-NEXT: [[ADD5:%.*]] = add nsw i32 -10, [[MUL4]] 7110 // CHECK6-NEXT: store i32 [[ADD5]], i32* [[X]], align 4, !llvm.access.group !14 7111 // CHECK6-NEXT: [[TMP18:%.*]] = load float*, float** [[TMP4]], align 8, !llvm.access.group !14 7112 // CHECK6-NEXT: [[TMP19:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 7113 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i8 [[TMP19]] to i64 7114 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[TMP18]], i64 [[IDXPROM]] 7115 // CHECK6-NEXT: [[TMP20:%.*]] = load float, float* [[ARRAYIDX]], align 4, !llvm.access.group !14 7116 // CHECK6-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP6]], align 8, !llvm.access.group !14 7117 // CHECK6-NEXT: [[TMP22:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 7118 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i8 [[TMP22]] to i64 7119 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 7120 // CHECK6-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4, !llvm.access.group !14 7121 // CHECK6-NEXT: [[MUL8:%.*]] = fmul float [[TMP20]], [[TMP23]] 7122 // CHECK6-NEXT: [[TMP24:%.*]] = load float*, float** [[TMP8]], align 8, !llvm.access.group !14 7123 // CHECK6-NEXT: [[TMP25:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 7124 // CHECK6-NEXT: [[IDXPROM9:%.*]] = zext i8 [[TMP25]] to i64 7125 // CHECK6-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds float, float* [[TMP24]], i64 [[IDXPROM9]] 7126 // CHECK6-NEXT: [[TMP26:%.*]] = load float, float* [[ARRAYIDX10]], align 4, !llvm.access.group !14 7127 // CHECK6-NEXT: [[MUL11:%.*]] = fmul float [[MUL8]], [[TMP26]] 7128 // CHECK6-NEXT: [[TMP27:%.*]] = load float*, float** [[TMP2]], align 8, !llvm.access.group !14 7129 // CHECK6-NEXT: [[TMP28:%.*]] = load i8, i8* [[I]], align 1, !llvm.access.group !14 7130 // CHECK6-NEXT: [[IDXPROM12:%.*]] = zext i8 [[TMP28]] to i64 7131 // CHECK6-NEXT: [[ARRAYIDX13:%.*]] = getelementptr inbounds float, float* [[TMP27]], i64 [[IDXPROM12]] 7132 // CHECK6-NEXT: store float [[MUL11]], float* [[ARRAYIDX13]], align 4, !llvm.access.group !14 7133 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7134 // CHECK6: omp.body.continue: 7135 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7136 // CHECK6: omp.inner.for.inc: 7137 // CHECK6-NEXT: [[TMP29:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 7138 // CHECK6-NEXT: [[ADD14:%.*]] = add nsw i32 [[TMP29]], 1 7139 // CHECK6-NEXT: store i32 [[ADD14]], i32* [[DOTOMP_IV]], align 4, !llvm.access.group !14 7140 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]], !llvm.loop [[LOOP15:![0-9]+]] 7141 // CHECK6: omp.inner.for.end: 7142 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7143 // CHECK6: omp.dispatch.inc: 7144 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 7145 // CHECK6: omp.dispatch.end: 7146 // CHECK6-NEXT: ret void 7147 // 7148 // 7149 // CHECK6-LABEL: define {{[^@]+}}@_Z3foov 7150 // CHECK6-SAME: () #[[ATTR0]] { 7151 // CHECK6-NEXT: entry: 7152 // CHECK6-NEXT: call void @_Z8mayThrowv() 7153 // CHECK6-NEXT: ret i32 0 7154 // 7155 // 7156 // CHECK6-LABEL: define {{[^@]+}}@_Z12parallel_forPfi 7157 // CHECK6-SAME: (float* [[A:%.*]], i32 [[N:%.*]]) #[[ATTR0]] { 7158 // CHECK6-NEXT: entry: 7159 // CHECK6-NEXT: [[A_ADDR:%.*]] = alloca float*, align 8 7160 // CHECK6-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 7161 // CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7162 // CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7163 // CHECK6-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_7:%.*]], align 8 7164 // CHECK6-NEXT: store float* [[A]], float** [[A_ADDR]], align 8 7165 // CHECK6-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 7166 // CHECK6-NEXT: [[TMP0:%.*]] = load i32, i32* [[N_ADDR]], align 4 7167 // CHECK6-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 7168 // CHECK6-NEXT: [[TMP2:%.*]] = call i8* @llvm.stacksave() 7169 // CHECK6-NEXT: store i8* [[TMP2]], i8** [[SAVED_STACK]], align 8 7170 // CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP1]], align 16 7171 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[__VLA_EXPR0]], align 8 7172 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 7173 // CHECK6-NEXT: store float** [[A_ADDR]], float*** [[TMP3]], align 8 7174 // CHECK6-NEXT: [[TMP4:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 1 7175 // CHECK6-NEXT: store i64 [[TMP1]], i64* [[TMP4]], align 8 7176 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 2 7177 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[N_ADDR]], align 4 7178 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[TMP5]], align 8 7179 // CHECK6-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.7*)* @.omp_outlined..8 to void (i32*, i32*, ...)*), %struct.anon.7* [[OMP_OUTLINED_ARG_AGG_]]) 7180 // CHECK6-NEXT: [[TMP7:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7181 // CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP7]]) 7182 // CHECK6-NEXT: ret void 7183 // 7184 // 7185 // CHECK6-LABEL: define {{[^@]+}}@.omp_outlined..8 7186 // CHECK6-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.7* noalias [[__CONTEXT:%.*]]) #[[ATTR1]] { 7187 // CHECK6-NEXT: entry: 7188 // CHECK6-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7189 // CHECK6-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7190 // CHECK6-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.7*, align 8 7191 // CHECK6-NEXT: [[N:%.*]] = alloca i32, align 4 7192 // CHECK6-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7193 // CHECK6-NEXT: [[TMP:%.*]] = alloca i32, align 4 7194 // CHECK6-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7195 // CHECK6-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7196 // CHECK6-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7197 // CHECK6-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7198 // CHECK6-NEXT: [[SAVED_STACK:%.*]] = alloca i8*, align 8 7199 // CHECK6-NEXT: [[__VLA_EXPR0:%.*]] = alloca i64, align 8 7200 // CHECK6-NEXT: [[I:%.*]] = alloca i32, align 4 7201 // CHECK6-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7202 // CHECK6-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7203 // CHECK6-NEXT: store %struct.anon.7* [[__CONTEXT]], %struct.anon.7** [[__CONTEXT_ADDR]], align 8 7204 // CHECK6-NEXT: [[TMP0:%.*]] = load %struct.anon.7*, %struct.anon.7** [[__CONTEXT_ADDR]], align 8 7205 // CHECK6-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_7:%.*]], %struct.anon.7* [[TMP0]], i32 0, i32 0 7206 // CHECK6-NEXT: [[TMP2:%.*]] = load float**, float*** [[TMP1]], align 8 7207 // CHECK6-NEXT: [[TMP3:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 1 7208 // CHECK6-NEXT: [[TMP4:%.*]] = load i64, i64* [[TMP3]], align 8 7209 // CHECK6-NEXT: [[TMP5:%.*]] = getelementptr inbounds [[STRUCT_ANON_7]], %struct.anon.7* [[TMP0]], i32 0, i32 2 7210 // CHECK6-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 8 7211 // CHECK6-NEXT: store i32 [[TMP6]], i32* [[N]], align 4 7212 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7213 // CHECK6-NEXT: store i32 16908288, i32* [[DOTOMP_UB]], align 4 7214 // CHECK6-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7215 // CHECK6-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7216 // CHECK6-NEXT: [[TMP7:%.*]] = call i8* @llvm.stacksave() 7217 // CHECK6-NEXT: store i8* [[TMP7]], i8** [[SAVED_STACK]], align 8 7218 // CHECK6-NEXT: [[VLA:%.*]] = alloca float, i64 [[TMP4]], align 16 7219 // CHECK6-NEXT: store i64 [[TMP4]], i64* [[__VLA_EXPR0]], align 8 7220 // CHECK6-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7221 // CHECK6-NEXT: [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4 7222 // CHECK6-NEXT: call void @__kmpc_for_static_init_4u(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]], i32 33, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 5) 7223 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND:%.*]] 7224 // CHECK6: omp.dispatch.cond: 7225 // CHECK6-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7226 // CHECK6-NEXT: [[CMP:%.*]] = icmp ugt i32 [[TMP10]], 16908288 7227 // CHECK6-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7228 // CHECK6: cond.true: 7229 // CHECK6-NEXT: br label [[COND_END:%.*]] 7230 // CHECK6: cond.false: 7231 // CHECK6-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7232 // CHECK6-NEXT: br label [[COND_END]] 7233 // CHECK6: cond.end: 7234 // CHECK6-NEXT: [[COND:%.*]] = phi i32 [ 16908288, [[COND_TRUE]] ], [ [[TMP11]], [[COND_FALSE]] ] 7235 // CHECK6-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7236 // CHECK6-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7237 // CHECK6-NEXT: store i32 [[TMP12]], i32* [[DOTOMP_IV]], align 4 7238 // CHECK6-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7239 // CHECK6-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7240 // CHECK6-NEXT: [[CMP1:%.*]] = icmp ule i32 [[TMP13]], [[TMP14]] 7241 // CHECK6-NEXT: br i1 [[CMP1]], label [[OMP_DISPATCH_BODY:%.*]], label [[OMP_DISPATCH_CLEANUP:%.*]] 7242 // CHECK6: omp.dispatch.cleanup: 7243 // CHECK6-NEXT: br label [[OMP_DISPATCH_END:%.*]] 7244 // CHECK6: omp.dispatch.body: 7245 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7246 // CHECK6: omp.inner.for.cond: 7247 // CHECK6-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7248 // CHECK6-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7249 // CHECK6-NEXT: [[CMP2:%.*]] = icmp ule i32 [[TMP15]], [[TMP16]] 7250 // CHECK6-NEXT: br i1 [[CMP2]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_COND_CLEANUP:%.*]] 7251 // CHECK6: omp.inner.for.cond.cleanup: 7252 // CHECK6-NEXT: br label [[OMP_INNER_FOR_END:%.*]] 7253 // CHECK6: omp.inner.for.body: 7254 // CHECK6-NEXT: [[TMP17:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7255 // CHECK6-NEXT: [[MUL:%.*]] = mul i32 [[TMP17]], 127 7256 // CHECK6-NEXT: [[ADD:%.*]] = add i32 131071, [[MUL]] 7257 // CHECK6-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7258 // CHECK6-NEXT: [[CALL:%.*]] = call i32 @_Z3foov() 7259 // CHECK6-NEXT: [[CONV:%.*]] = sitofp i32 [[CALL]] to float 7260 // CHECK6-NEXT: [[TMP18:%.*]] = load i32, i32* [[I]], align 4 7261 // CHECK6-NEXT: [[IDXPROM:%.*]] = zext i32 [[TMP18]] to i64 7262 // CHECK6-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, float* [[VLA]], i64 [[IDXPROM]] 7263 // CHECK6-NEXT: [[TMP19:%.*]] = load float, float* [[ARRAYIDX]], align 4 7264 // CHECK6-NEXT: [[ADD3:%.*]] = fadd float [[CONV]], [[TMP19]] 7265 // CHECK6-NEXT: [[TMP20:%.*]] = load i32, i32* [[N]], align 4 7266 // CHECK6-NEXT: [[CONV4:%.*]] = sitofp i32 [[TMP20]] to float 7267 // CHECK6-NEXT: [[ADD5:%.*]] = fadd float [[ADD3]], [[CONV4]] 7268 // CHECK6-NEXT: [[TMP21:%.*]] = load float*, float** [[TMP2]], align 8 7269 // CHECK6-NEXT: [[TMP22:%.*]] = load i32, i32* [[I]], align 4 7270 // CHECK6-NEXT: [[IDXPROM6:%.*]] = zext i32 [[TMP22]] to i64 7271 // CHECK6-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds float, float* [[TMP21]], i64 [[IDXPROM6]] 7272 // CHECK6-NEXT: [[TMP23:%.*]] = load float, float* [[ARRAYIDX7]], align 4 7273 // CHECK6-NEXT: [[ADD8:%.*]] = fadd float [[TMP23]], [[ADD5]] 7274 // CHECK6-NEXT: store float [[ADD8]], float* [[ARRAYIDX7]], align 4 7275 // CHECK6-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7276 // CHECK6: omp.body.continue: 7277 // CHECK6-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7278 // CHECK6: omp.inner.for.inc: 7279 // CHECK6-NEXT: [[TMP24:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7280 // CHECK6-NEXT: [[ADD9:%.*]] = add i32 [[TMP24]], 1 7281 // CHECK6-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 7282 // CHECK6-NEXT: br label [[OMP_INNER_FOR_COND]] 7283 // CHECK6: omp.inner.for.end: 7284 // CHECK6-NEXT: br label [[OMP_DISPATCH_INC:%.*]] 7285 // CHECK6: omp.dispatch.inc: 7286 // CHECK6-NEXT: [[TMP25:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7287 // CHECK6-NEXT: [[TMP26:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7288 // CHECK6-NEXT: [[ADD10:%.*]] = add i32 [[TMP25]], [[TMP26]] 7289 // CHECK6-NEXT: store i32 [[ADD10]], i32* [[DOTOMP_LB]], align 4 7290 // CHECK6-NEXT: [[TMP27:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7291 // CHECK6-NEXT: [[TMP28:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 7292 // CHECK6-NEXT: [[ADD11:%.*]] = add i32 [[TMP27]], [[TMP28]] 7293 // CHECK6-NEXT: store i32 [[ADD11]], i32* [[DOTOMP_UB]], align 4 7294 // CHECK6-NEXT: br label [[OMP_DISPATCH_COND]] 7295 // CHECK6: omp.dispatch.end: 7296 // CHECK6-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP9]]) 7297 // CHECK6-NEXT: [[TMP29:%.*]] = load i8*, i8** [[SAVED_STACK]], align 8 7298 // CHECK6-NEXT: call void @llvm.stackrestore(i8* [[TMP29]]) 7299 // CHECK6-NEXT: ret void 7300 // 7301 // 7302 // CHECK11-LABEL: define {{[^@]+}}@_Z9incrementv 7303 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] { 7304 // CHECK11-NEXT: entry: 7305 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7306 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7307 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7308 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7309 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7310 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7311 // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 7312 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 7313 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7314 // CHECK11-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 7315 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7316 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7317 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7318 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7319 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 7320 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7321 // CHECK11: cond.true: 7322 // CHECK11-NEXT: br label [[COND_END:%.*]] 7323 // CHECK11: cond.false: 7324 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7325 // CHECK11-NEXT: br label [[COND_END]] 7326 // CHECK11: cond.end: 7327 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 7328 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7329 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7330 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 7331 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7332 // CHECK11: omp.inner.for.cond: 7333 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7334 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7335 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 7336 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7337 // CHECK11: omp.inner.for.body: 7338 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7339 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 7340 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 7341 // CHECK11-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7342 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7343 // CHECK11: omp.body.continue: 7344 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7345 // CHECK11: omp.inner.for.inc: 7346 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7347 // CHECK11-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1 7348 // CHECK11-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 7349 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 7350 // CHECK11: omp.inner.for.end: 7351 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7352 // CHECK11: omp.loop.exit: 7353 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 7354 // CHECK11-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) 7355 // CHECK11-NEXT: ret i32 0 7356 // 7357 // 7358 // CHECK11-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv 7359 // CHECK11-SAME: () #[[ATTR0]] { 7360 // CHECK11-NEXT: entry: 7361 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7362 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 7363 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7364 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7365 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7366 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7367 // CHECK11-NEXT: [[J:%.*]] = alloca i32, align 4 7368 // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 7369 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7370 // CHECK11-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 7371 // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7372 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7373 // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7374 // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7375 // CHECK11-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 7376 // CHECK11-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7377 // CHECK11: cond.true: 7378 // CHECK11-NEXT: br label [[COND_END:%.*]] 7379 // CHECK11: cond.false: 7380 // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7381 // CHECK11-NEXT: br label [[COND_END]] 7382 // CHECK11: cond.end: 7383 // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 7384 // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7385 // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7386 // CHECK11-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 7387 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7388 // CHECK11: omp.inner.for.cond: 7389 // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7390 // CHECK11-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7391 // CHECK11-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 7392 // CHECK11-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7393 // CHECK11: omp.inner.for.body: 7394 // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7395 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 7396 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]] 7397 // CHECK11-NEXT: store i32 [[SUB]], i32* [[J]], align 4 7398 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7399 // CHECK11: omp.body.continue: 7400 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7401 // CHECK11: omp.inner.for.inc: 7402 // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7403 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 7404 // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 7405 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 7406 // CHECK11: omp.inner.for.end: 7407 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7408 // CHECK11: omp.loop.exit: 7409 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 7410 // CHECK11-NEXT: ret i32 0 7411 // 7412 // 7413 // CHECK11-LABEL: define {{[^@]+}}@_Z16range_for_singlev 7414 // CHECK11-SAME: () #[[ATTR3:[0-9]+]] { 7415 // CHECK11-NEXT: entry: 7416 // CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 7417 // CHECK11-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 7418 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 7419 // CHECK11-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 7420 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 7421 // CHECK11-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[TMP1]], align 8 7422 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 7423 // CHECK11-NEXT: ret void 7424 // 7425 // 7426 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. 7427 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR5:[0-9]+]] { 7428 // CHECK11-NEXT: entry: 7429 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7430 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7431 // CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 7432 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7433 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 7434 // CHECK11-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 7435 // CHECK11-NEXT: [[__END1:%.*]] = alloca i32*, align 8 7436 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 7437 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32*, align 8 7438 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 7439 // CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 7440 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7441 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7442 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7443 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7444 // CHECK11-NEXT: [[__BEGIN15:%.*]] = alloca i32*, align 8 7445 // CHECK11-NEXT: [[A:%.*]] = alloca i32*, align 8 7446 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7447 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7448 // CHECK11-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 7449 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 7450 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 7451 // CHECK11-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[TMP1]], align 8 7452 // CHECK11-NEXT: store [10 x i32]* [[TMP2]], [10 x i32]** [[__RANGE1]], align 8 7453 // CHECK11-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 7454 // CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 7455 // CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 7456 // CHECK11-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 7457 // CHECK11-NEXT: [[TMP4:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 7458 // CHECK11-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i64 0, i64 0 7459 // CHECK11-NEXT: store i32* [[ARRAYDECAY1]], i32** [[DOTCAPTURE_EXPR_]], align 8 7460 // CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__END1]], align 8 7461 // CHECK11-NEXT: store i32* [[TMP5]], i32** [[DOTCAPTURE_EXPR_2]], align 8 7462 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 7463 // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7464 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP6]] to i64 7465 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP7]] to i64 7466 // CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 7467 // CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 7468 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 7469 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 7470 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 7471 // CHECK11-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1 7472 // CHECK11-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_3]], align 8 7473 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7474 // CHECK11-NEXT: store i32* [[TMP8]], i32** [[__BEGIN1]], align 8 7475 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7476 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 7477 // CHECK11-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP9]], [[TMP10]] 7478 // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 7479 // CHECK11: omp.precond.then: 7480 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7481 // CHECK11-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 7482 // CHECK11-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 7483 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7484 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7485 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7486 // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 7487 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7488 // CHECK11-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7489 // CHECK11-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 7490 // CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 7491 // CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7492 // CHECK11: cond.true: 7493 // CHECK11-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 7494 // CHECK11-NEXT: br label [[COND_END:%.*]] 7495 // CHECK11: cond.false: 7496 // CHECK11-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7497 // CHECK11-NEXT: br label [[COND_END]] 7498 // CHECK11: cond.end: 7499 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 7500 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7501 // CHECK11-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7502 // CHECK11-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 7503 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7504 // CHECK11: omp.inner.for.cond: 7505 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7506 // CHECK11-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7507 // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 7508 // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7509 // CHECK11: omp.inner.for.body: 7510 // CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7511 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7512 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP22]], 1 7513 // CHECK11-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i64 [[MUL]] 7514 // CHECK11-NEXT: store i32* [[ADD_PTR8]], i32** [[__BEGIN15]], align 8 7515 // CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[__BEGIN15]], align 8 7516 // CHECK11-NEXT: store i32* [[TMP23]], i32** [[A]], align 8 7517 // CHECK11-NEXT: [[TMP24:%.*]] = load i32*, i32** [[A]], align 8 7518 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7519 // CHECK11: omp.body.continue: 7520 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7521 // CHECK11: omp.inner.for.inc: 7522 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7523 // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP25]], 1 7524 // CHECK11-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 7525 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 7526 // CHECK11: omp.inner.for.end: 7527 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7528 // CHECK11: omp.loop.exit: 7529 // CHECK11-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7530 // CHECK11-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 7531 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) 7532 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 7533 // CHECK11: omp.precond.end: 7534 // CHECK11-NEXT: ret void 7535 // 7536 // 7537 // CHECK11-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv 7538 // CHECK11-SAME: () #[[ATTR3]] { 7539 // CHECK11-NEXT: entry: 7540 // CHECK11-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 7541 // CHECK11-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 7542 // CHECK11-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 7543 // CHECK11-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 7544 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 7545 // CHECK11-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[TMP1]], align 8 7546 // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]]) 7547 // CHECK11-NEXT: ret void 7548 // 7549 // 7550 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 7551 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR5]] { 7552 // CHECK11-NEXT: entry: 7553 // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7554 // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7555 // CHECK11-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.0*, align 8 7556 // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7557 // CHECK11-NEXT: [[TMP:%.*]] = alloca i32*, align 8 7558 // CHECK11-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 7559 // CHECK11-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 7560 // CHECK11-NEXT: [[__END1:%.*]] = alloca i32*, align 8 7561 // CHECK11-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 7562 // CHECK11-NEXT: [[__END2:%.*]] = alloca i32*, align 8 7563 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 7564 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32*, align 8 7565 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32*, align 8 7566 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32*, align 8 7567 // CHECK11-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8 7568 // CHECK11-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 7569 // CHECK11-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 7570 // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7571 // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7572 // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7573 // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7574 // CHECK11-NEXT: [[__BEGIN119:%.*]] = alloca i32*, align 8 7575 // CHECK11-NEXT: [[__BEGIN220:%.*]] = alloca i32*, align 8 7576 // CHECK11-NEXT: [[A:%.*]] = alloca i32*, align 8 7577 // CHECK11-NEXT: [[B:%.*]] = alloca i32, align 4 7578 // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7579 // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7580 // CHECK11-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 7581 // CHECK11-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 7582 // CHECK11-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 7583 // CHECK11-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[TMP1]], align 8 7584 // CHECK11-NEXT: store [10 x i32]* [[TMP2]], [10 x i32]** [[__RANGE1]], align 8 7585 // CHECK11-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 7586 // CHECK11-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 7587 // CHECK11-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 7588 // CHECK11-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 7589 // CHECK11-NEXT: store [10 x i32]* [[TMP2]], [10 x i32]** [[__RANGE2]], align 8 7590 // CHECK11-NEXT: [[TMP4:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 7591 // CHECK11-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i64 0, i64 0 7592 // CHECK11-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY2]], i64 10 7593 // CHECK11-NEXT: store i32* [[ADD_PTR3]], i32** [[__END2]], align 8 7594 // CHECK11-NEXT: [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 7595 // CHECK11-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP5]], i64 0, i64 0 7596 // CHECK11-NEXT: store i32* [[ARRAYDECAY4]], i32** [[DOTCAPTURE_EXPR_]], align 8 7597 // CHECK11-NEXT: [[TMP6:%.*]] = load i32*, i32** [[__END1]], align 8 7598 // CHECK11-NEXT: store i32* [[TMP6]], i32** [[DOTCAPTURE_EXPR_5]], align 8 7599 // CHECK11-NEXT: [[TMP7:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 7600 // CHECK11-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP7]], i64 0, i64 0 7601 // CHECK11-NEXT: store i32* [[ARRAYDECAY7]], i32** [[DOTCAPTURE_EXPR_6]], align 8 7602 // CHECK11-NEXT: [[TMP8:%.*]] = load i32*, i32** [[__END2]], align 8 7603 // CHECK11-NEXT: store i32* [[TMP8]], i32** [[DOTCAPTURE_EXPR_8]], align 8 7604 // CHECK11-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 7605 // CHECK11-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7606 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP9]] to i64 7607 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP10]] to i64 7608 // CHECK11-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 7609 // CHECK11-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 7610 // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 7611 // CHECK11-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 7612 // CHECK11-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 7613 // CHECK11-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 7614 // CHECK11-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 7615 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint i32* [[TMP11]] to i64 7616 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint i32* [[TMP12]] to i64 7617 // CHECK11-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]] 7618 // CHECK11-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4 7619 // CHECK11-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1 7620 // CHECK11-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1 7621 // CHECK11-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1 7622 // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]] 7623 // CHECK11-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1 7624 // CHECK11-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_9]], align 8 7625 // CHECK11-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7626 // CHECK11-NEXT: store i32* [[TMP13]], i32** [[__BEGIN1]], align 8 7627 // CHECK11-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 7628 // CHECK11-NEXT: store i32* [[TMP14]], i32** [[__BEGIN2]], align 8 7629 // CHECK11-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7630 // CHECK11-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 7631 // CHECK11-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP15]], [[TMP16]] 7632 // CHECK11-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 7633 // CHECK11: land.lhs.true: 7634 // CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 7635 // CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 7636 // CHECK11-NEXT: [[CMP18:%.*]] = icmp ult i32* [[TMP17]], [[TMP18]] 7637 // CHECK11-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 7638 // CHECK11: omp.precond.then: 7639 // CHECK11-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7640 // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 7641 // CHECK11-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_UB]], align 8 7642 // CHECK11-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7643 // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7644 // CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7645 // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 7646 // CHECK11-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7647 // CHECK11-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7648 // CHECK11-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 7649 // CHECK11-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP22]], [[TMP23]] 7650 // CHECK11-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7651 // CHECK11: cond.true: 7652 // CHECK11-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 7653 // CHECK11-NEXT: br label [[COND_END:%.*]] 7654 // CHECK11: cond.false: 7655 // CHECK11-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7656 // CHECK11-NEXT: br label [[COND_END]] 7657 // CHECK11: cond.end: 7658 // CHECK11-NEXT: [[COND:%.*]] = phi i64 [ [[TMP24]], [[COND_TRUE]] ], [ [[TMP25]], [[COND_FALSE]] ] 7659 // CHECK11-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7660 // CHECK11-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7661 // CHECK11-NEXT: store i64 [[TMP26]], i64* [[DOTOMP_IV]], align 8 7662 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7663 // CHECK11: omp.inner.for.cond: 7664 // CHECK11-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7665 // CHECK11-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7666 // CHECK11-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP27]], [[TMP28]] 7667 // CHECK11-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7668 // CHECK11: omp.inner.for.body: 7669 // CHECK11-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7670 // CHECK11-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7671 // CHECK11-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 7672 // CHECK11-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 7673 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint i32* [[TMP31]] to i64 7674 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint i32* [[TMP32]] to i64 7675 // CHECK11-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]] 7676 // CHECK11-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4 7677 // CHECK11-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1 7678 // CHECK11-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1 7679 // CHECK11-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1 7680 // CHECK11-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]] 7681 // CHECK11-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP30]], [[MUL30]] 7682 // CHECK11-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1 7683 // CHECK11-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i64 [[MUL32]] 7684 // CHECK11-NEXT: store i32* [[ADD_PTR33]], i32** [[__BEGIN119]], align 8 7685 // CHECK11-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 7686 // CHECK11-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7687 // CHECK11-NEXT: [[TMP35:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7688 // CHECK11-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 7689 // CHECK11-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 7690 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint i32* [[TMP36]] to i64 7691 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint i32* [[TMP37]] to i64 7692 // CHECK11-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]] 7693 // CHECK11-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4 7694 // CHECK11-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1 7695 // CHECK11-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1 7696 // CHECK11-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1 7697 // CHECK11-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]] 7698 // CHECK11-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP35]], [[MUL41]] 7699 // CHECK11-NEXT: [[TMP38:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 7700 // CHECK11-NEXT: [[TMP39:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 7701 // CHECK11-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint i32* [[TMP38]] to i64 7702 // CHECK11-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint i32* [[TMP39]] to i64 7703 // CHECK11-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]] 7704 // CHECK11-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4 7705 // CHECK11-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1 7706 // CHECK11-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1 7707 // CHECK11-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1 7708 // CHECK11-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]] 7709 // CHECK11-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]] 7710 // CHECK11-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP34]], [[MUL51]] 7711 // CHECK11-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1 7712 // CHECK11-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, i32* [[TMP33]], i64 [[MUL53]] 7713 // CHECK11-NEXT: store i32* [[ADD_PTR54]], i32** [[__BEGIN220]], align 8 7714 // CHECK11-NEXT: [[TMP40:%.*]] = load i32*, i32** [[__BEGIN119]], align 8 7715 // CHECK11-NEXT: store i32* [[TMP40]], i32** [[A]], align 8 7716 // CHECK11-NEXT: [[TMP41:%.*]] = load i32*, i32** [[__BEGIN220]], align 8 7717 // CHECK11-NEXT: [[TMP42:%.*]] = load i32, i32* [[TMP41]], align 4 7718 // CHECK11-NEXT: store i32 [[TMP42]], i32* [[B]], align 4 7719 // CHECK11-NEXT: [[TMP43:%.*]] = load i32, i32* [[B]], align 4 7720 // CHECK11-NEXT: [[TMP44:%.*]] = load i32*, i32** [[A]], align 8 7721 // CHECK11-NEXT: store i32 [[TMP43]], i32* [[TMP44]], align 4 7722 // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7723 // CHECK11: omp.body.continue: 7724 // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7725 // CHECK11: omp.inner.for.inc: 7726 // CHECK11-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7727 // CHECK11-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP45]], 1 7728 // CHECK11-NEXT: store i64 [[ADD55]], i64* [[DOTOMP_IV]], align 8 7729 // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] 7730 // CHECK11: omp.inner.for.end: 7731 // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7732 // CHECK11: omp.loop.exit: 7733 // CHECK11-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7734 // CHECK11-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4 7735 // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]]) 7736 // CHECK11-NEXT: br label [[OMP_PRECOND_END]] 7737 // CHECK11: omp.precond.end: 7738 // CHECK11-NEXT: ret void 7739 // 7740 // 7741 // CHECK12-LABEL: define {{[^@]+}}@_Z9incrementv 7742 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] { 7743 // CHECK12-NEXT: entry: 7744 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7745 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 7746 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7747 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7748 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7749 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7750 // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 7751 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2:[0-9]+]]) 7752 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7753 // CHECK12-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 7754 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7755 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7756 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7757 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7758 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 7759 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7760 // CHECK12: cond.true: 7761 // CHECK12-NEXT: br label [[COND_END:%.*]] 7762 // CHECK12: cond.false: 7763 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7764 // CHECK12-NEXT: br label [[COND_END]] 7765 // CHECK12: cond.end: 7766 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 7767 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7768 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7769 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 7770 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7771 // CHECK12: omp.inner.for.cond: 7772 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7773 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7774 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 7775 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7776 // CHECK12: omp.inner.for.body: 7777 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7778 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 7779 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] 7780 // CHECK12-NEXT: store i32 [[ADD]], i32* [[I]], align 4 7781 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7782 // CHECK12: omp.body.continue: 7783 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7784 // CHECK12: omp.inner.for.inc: 7785 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7786 // CHECK12-NEXT: [[ADD2:%.*]] = add nsw i32 [[TMP7]], 1 7787 // CHECK12-NEXT: store i32 [[ADD2]], i32* [[DOTOMP_IV]], align 4 7788 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 7789 // CHECK12: omp.inner.for.end: 7790 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7791 // CHECK12: omp.loop.exit: 7792 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 7793 // CHECK12-NEXT: call void @__kmpc_barrier(%struct.ident_t* @[[GLOB3:[0-9]+]], i32 [[TMP0]]) 7794 // CHECK12-NEXT: ret i32 0 7795 // 7796 // 7797 // CHECK12-LABEL: define {{[^@]+}}@_Z16decrement_nowaitv 7798 // CHECK12-SAME: () #[[ATTR0]] { 7799 // CHECK12-NEXT: entry: 7800 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 7801 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 7802 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 7803 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 7804 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 7805 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7806 // CHECK12-NEXT: [[J:%.*]] = alloca i32, align 4 7807 // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB2]]) 7808 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 7809 // CHECK12-NEXT: store i32 4, i32* [[DOTOMP_UB]], align 4 7810 // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 7811 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7812 // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) 7813 // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7814 // CHECK12-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP1]], 4 7815 // CHECK12-NEXT: br i1 [[CMP]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7816 // CHECK12: cond.true: 7817 // CHECK12-NEXT: br label [[COND_END:%.*]] 7818 // CHECK12: cond.false: 7819 // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7820 // CHECK12-NEXT: br label [[COND_END]] 7821 // CHECK12: cond.end: 7822 // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ 4, [[COND_TRUE]] ], [ [[TMP2]], [[COND_FALSE]] ] 7823 // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 7824 // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 7825 // CHECK12-NEXT: store i32 [[TMP3]], i32* [[DOTOMP_IV]], align 4 7826 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7827 // CHECK12: omp.inner.for.cond: 7828 // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7829 // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 7830 // CHECK12-NEXT: [[CMP1:%.*]] = icmp sle i32 [[TMP4]], [[TMP5]] 7831 // CHECK12-NEXT: br i1 [[CMP1]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7832 // CHECK12: omp.inner.for.body: 7833 // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7834 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP6]], 1 7835 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 5, [[MUL]] 7836 // CHECK12-NEXT: store i32 [[SUB]], i32* [[J]], align 4 7837 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7838 // CHECK12: omp.body.continue: 7839 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7840 // CHECK12: omp.inner.for.inc: 7841 // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 7842 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP7]], 1 7843 // CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 7844 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 7845 // CHECK12: omp.inner.for.end: 7846 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7847 // CHECK12: omp.loop.exit: 7848 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]]) 7849 // CHECK12-NEXT: ret i32 0 7850 // 7851 // 7852 // CHECK12-LABEL: define {{[^@]+}}@_Z16range_for_singlev 7853 // CHECK12-SAME: () #[[ATTR3:[0-9]+]] { 7854 // CHECK12-NEXT: entry: 7855 // CHECK12-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 7856 // CHECK12-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON:%.*]], align 8 7857 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 7858 // CHECK12-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 7859 // CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON]], %struct.anon* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 7860 // CHECK12-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[TMP1]], align 8 7861 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon*)* @.omp_outlined. to void (i32*, i32*, ...)*), %struct.anon* [[OMP_OUTLINED_ARG_AGG_]]) 7862 // CHECK12-NEXT: ret void 7863 // 7864 // 7865 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. 7866 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon* noalias [[__CONTEXT:%.*]]) #[[ATTR5:[0-9]+]] { 7867 // CHECK12-NEXT: entry: 7868 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7869 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7870 // CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon*, align 8 7871 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7872 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 7873 // CHECK12-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 7874 // CHECK12-NEXT: [[__END1:%.*]] = alloca i32*, align 8 7875 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 7876 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_2:%.*]] = alloca i32*, align 8 7877 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i64, align 8 7878 // CHECK12-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 7879 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 7880 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 7881 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 7882 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 7883 // CHECK12-NEXT: [[__BEGIN15:%.*]] = alloca i32*, align 8 7884 // CHECK12-NEXT: [[A:%.*]] = alloca i32*, align 8 7885 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 7886 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 7887 // CHECK12-NEXT: store %struct.anon* [[__CONTEXT]], %struct.anon** [[__CONTEXT_ADDR]], align 8 7888 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.anon*, %struct.anon** [[__CONTEXT_ADDR]], align 8 7889 // CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON:%.*]], %struct.anon* [[TMP0]], i32 0, i32 0 7890 // CHECK12-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[TMP1]], align 8 7891 // CHECK12-NEXT: store [10 x i32]* [[TMP2]], [10 x i32]** [[__RANGE1]], align 8 7892 // CHECK12-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 7893 // CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 7894 // CHECK12-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 7895 // CHECK12-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 7896 // CHECK12-NEXT: [[TMP4:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 7897 // CHECK12-NEXT: [[ARRAYDECAY1:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i64 0, i64 0 7898 // CHECK12-NEXT: store i32* [[ARRAYDECAY1]], i32** [[DOTCAPTURE_EXPR_]], align 8 7899 // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[__END1]], align 8 7900 // CHECK12-NEXT: store i32* [[TMP5]], i32** [[DOTCAPTURE_EXPR_2]], align 8 7901 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 7902 // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7903 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP6]] to i64 7904 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP7]] to i64 7905 // CHECK12-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 7906 // CHECK12-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 7907 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 7908 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 7909 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 7910 // CHECK12-NEXT: [[SUB4:%.*]] = sub nsw i64 [[DIV]], 1 7911 // CHECK12-NEXT: store i64 [[SUB4]], i64* [[DOTCAPTURE_EXPR_3]], align 8 7912 // CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7913 // CHECK12-NEXT: store i32* [[TMP8]], i32** [[__BEGIN1]], align 8 7914 // CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7915 // CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_2]], align 8 7916 // CHECK12-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP9]], [[TMP10]] 7917 // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] 7918 // CHECK12: omp.precond.then: 7919 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 7920 // CHECK12-NEXT: [[TMP11:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 7921 // CHECK12-NEXT: store i64 [[TMP11]], i64* [[DOTOMP_UB]], align 8 7922 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 7923 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 7924 // CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7925 // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[TMP12]], align 4 7926 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP13]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 7927 // CHECK12-NEXT: [[TMP14:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7928 // CHECK12-NEXT: [[TMP15:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 7929 // CHECK12-NEXT: [[CMP6:%.*]] = icmp sgt i64 [[TMP14]], [[TMP15]] 7930 // CHECK12-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 7931 // CHECK12: cond.true: 7932 // CHECK12-NEXT: [[TMP16:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_3]], align 8 7933 // CHECK12-NEXT: br label [[COND_END:%.*]] 7934 // CHECK12: cond.false: 7935 // CHECK12-NEXT: [[TMP17:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7936 // CHECK12-NEXT: br label [[COND_END]] 7937 // CHECK12: cond.end: 7938 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP16]], [[COND_TRUE]] ], [ [[TMP17]], [[COND_FALSE]] ] 7939 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 7940 // CHECK12-NEXT: [[TMP18:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 7941 // CHECK12-NEXT: store i64 [[TMP18]], i64* [[DOTOMP_IV]], align 8 7942 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 7943 // CHECK12: omp.inner.for.cond: 7944 // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7945 // CHECK12-NEXT: [[TMP20:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 7946 // CHECK12-NEXT: [[CMP7:%.*]] = icmp sle i64 [[TMP19]], [[TMP20]] 7947 // CHECK12-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 7948 // CHECK12: omp.inner.for.body: 7949 // CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 7950 // CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7951 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[TMP22]], 1 7952 // CHECK12-NEXT: [[ADD_PTR8:%.*]] = getelementptr inbounds i32, i32* [[TMP21]], i64 [[MUL]] 7953 // CHECK12-NEXT: store i32* [[ADD_PTR8]], i32** [[__BEGIN15]], align 8 7954 // CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[__BEGIN15]], align 8 7955 // CHECK12-NEXT: store i32* [[TMP23]], i32** [[A]], align 8 7956 // CHECK12-NEXT: [[TMP24:%.*]] = load i32*, i32** [[A]], align 8 7957 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 7958 // CHECK12: omp.body.continue: 7959 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 7960 // CHECK12: omp.inner.for.inc: 7961 // CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 7962 // CHECK12-NEXT: [[ADD9:%.*]] = add nsw i64 [[TMP25]], 1 7963 // CHECK12-NEXT: store i64 [[ADD9]], i64* [[DOTOMP_IV]], align 8 7964 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 7965 // CHECK12: omp.inner.for.end: 7966 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 7967 // CHECK12: omp.loop.exit: 7968 // CHECK12-NEXT: [[TMP26:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 7969 // CHECK12-NEXT: [[TMP27:%.*]] = load i32, i32* [[TMP26]], align 4 7970 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP27]]) 7971 // CHECK12-NEXT: br label [[OMP_PRECOND_END]] 7972 // CHECK12: omp.precond.end: 7973 // CHECK12-NEXT: ret void 7974 // 7975 // 7976 // CHECK12-LABEL: define {{[^@]+}}@_Z19range_for_collapsedv 7977 // CHECK12-SAME: () #[[ATTR3]] { 7978 // CHECK12-NEXT: entry: 7979 // CHECK12-NEXT: [[ARR:%.*]] = alloca [10 x i32], align 16 7980 // CHECK12-NEXT: [[OMP_OUTLINED_ARG_AGG_:%.*]] = alloca [[STRUCT_ANON_0:%.*]], align 8 7981 // CHECK12-NEXT: [[TMP0:%.*]] = bitcast [10 x i32]* [[ARR]] to i8* 7982 // CHECK12-NEXT: call void @llvm.memset.p0i8.i64(i8* align 16 [[TMP0]], i8 0, i64 40, i1 false) 7983 // CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0]], %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]], i32 0, i32 0 7984 // CHECK12-NEXT: store [10 x i32]* [[ARR]], [10 x i32]** [[TMP1]], align 8 7985 // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, %struct.anon.0*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), %struct.anon.0* [[OMP_OUTLINED_ARG_AGG_]]) 7986 // CHECK12-NEXT: ret void 7987 // 7988 // 7989 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 7990 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], %struct.anon.0* noalias [[__CONTEXT:%.*]]) #[[ATTR5]] { 7991 // CHECK12-NEXT: entry: 7992 // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 7993 // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 7994 // CHECK12-NEXT: [[__CONTEXT_ADDR:%.*]] = alloca %struct.anon.0*, align 8 7995 // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i64, align 8 7996 // CHECK12-NEXT: [[TMP:%.*]] = alloca i32*, align 8 7997 // CHECK12-NEXT: [[_TMP1:%.*]] = alloca i32*, align 8 7998 // CHECK12-NEXT: [[__RANGE1:%.*]] = alloca [10 x i32]*, align 8 7999 // CHECK12-NEXT: [[__END1:%.*]] = alloca i32*, align 8 8000 // CHECK12-NEXT: [[__RANGE2:%.*]] = alloca [10 x i32]*, align 8 8001 // CHECK12-NEXT: [[__END2:%.*]] = alloca i32*, align 8 8002 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32*, align 8 8003 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32*, align 8 8004 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32*, align 8 8005 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_8:%.*]] = alloca i32*, align 8 8006 // CHECK12-NEXT: [[DOTCAPTURE_EXPR_9:%.*]] = alloca i64, align 8 8007 // CHECK12-NEXT: [[__BEGIN1:%.*]] = alloca i32*, align 8 8008 // CHECK12-NEXT: [[__BEGIN2:%.*]] = alloca i32*, align 8 8009 // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i64, align 8 8010 // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i64, align 8 8011 // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i64, align 8 8012 // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 8013 // CHECK12-NEXT: [[__BEGIN119:%.*]] = alloca i32*, align 8 8014 // CHECK12-NEXT: [[__BEGIN220:%.*]] = alloca i32*, align 8 8015 // CHECK12-NEXT: [[A:%.*]] = alloca i32*, align 8 8016 // CHECK12-NEXT: [[B:%.*]] = alloca i32, align 4 8017 // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 8018 // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 8019 // CHECK12-NEXT: store %struct.anon.0* [[__CONTEXT]], %struct.anon.0** [[__CONTEXT_ADDR]], align 8 8020 // CHECK12-NEXT: [[TMP0:%.*]] = load %struct.anon.0*, %struct.anon.0** [[__CONTEXT_ADDR]], align 8 8021 // CHECK12-NEXT: [[TMP1:%.*]] = getelementptr inbounds [[STRUCT_ANON_0:%.*]], %struct.anon.0* [[TMP0]], i32 0, i32 0 8022 // CHECK12-NEXT: [[TMP2:%.*]] = load [10 x i32]*, [10 x i32]** [[TMP1]], align 8 8023 // CHECK12-NEXT: store [10 x i32]* [[TMP2]], [10 x i32]** [[__RANGE1]], align 8 8024 // CHECK12-NEXT: [[TMP3:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8025 // CHECK12-NEXT: [[ARRAYDECAY:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP3]], i64 0, i64 0 8026 // CHECK12-NEXT: [[ADD_PTR:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY]], i64 10 8027 // CHECK12-NEXT: store i32* [[ADD_PTR]], i32** [[__END1]], align 8 8028 // CHECK12-NEXT: store [10 x i32]* [[TMP2]], [10 x i32]** [[__RANGE2]], align 8 8029 // CHECK12-NEXT: [[TMP4:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 8030 // CHECK12-NEXT: [[ARRAYDECAY2:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP4]], i64 0, i64 0 8031 // CHECK12-NEXT: [[ADD_PTR3:%.*]] = getelementptr inbounds i32, i32* [[ARRAYDECAY2]], i64 10 8032 // CHECK12-NEXT: store i32* [[ADD_PTR3]], i32** [[__END2]], align 8 8033 // CHECK12-NEXT: [[TMP5:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE1]], align 8 8034 // CHECK12-NEXT: [[ARRAYDECAY4:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP5]], i64 0, i64 0 8035 // CHECK12-NEXT: store i32* [[ARRAYDECAY4]], i32** [[DOTCAPTURE_EXPR_]], align 8 8036 // CHECK12-NEXT: [[TMP6:%.*]] = load i32*, i32** [[__END1]], align 8 8037 // CHECK12-NEXT: store i32* [[TMP6]], i32** [[DOTCAPTURE_EXPR_5]], align 8 8038 // CHECK12-NEXT: [[TMP7:%.*]] = load [10 x i32]*, [10 x i32]** [[__RANGE2]], align 8 8039 // CHECK12-NEXT: [[ARRAYDECAY7:%.*]] = getelementptr inbounds [10 x i32], [10 x i32]* [[TMP7]], i64 0, i64 0 8040 // CHECK12-NEXT: store i32* [[ARRAYDECAY7]], i32** [[DOTCAPTURE_EXPR_6]], align 8 8041 // CHECK12-NEXT: [[TMP8:%.*]] = load i32*, i32** [[__END2]], align 8 8042 // CHECK12-NEXT: store i32* [[TMP8]], i32** [[DOTCAPTURE_EXPR_8]], align 8 8043 // CHECK12-NEXT: [[TMP9:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 8044 // CHECK12-NEXT: [[TMP10:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8045 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST:%.*]] = ptrtoint i32* [[TMP9]] to i64 8046 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST:%.*]] = ptrtoint i32* [[TMP10]] to i64 8047 // CHECK12-NEXT: [[SUB_PTR_SUB:%.*]] = sub i64 [[SUB_PTR_LHS_CAST]], [[SUB_PTR_RHS_CAST]] 8048 // CHECK12-NEXT: [[SUB_PTR_DIV:%.*]] = sdiv exact i64 [[SUB_PTR_SUB]], 4 8049 // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i64 [[SUB_PTR_DIV]], 1 8050 // CHECK12-NEXT: [[ADD:%.*]] = add nsw i64 [[SUB]], 1 8051 // CHECK12-NEXT: [[DIV:%.*]] = sdiv i64 [[ADD]], 1 8052 // CHECK12-NEXT: [[TMP11:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8053 // CHECK12-NEXT: [[TMP12:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8054 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST10:%.*]] = ptrtoint i32* [[TMP11]] to i64 8055 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST11:%.*]] = ptrtoint i32* [[TMP12]] to i64 8056 // CHECK12-NEXT: [[SUB_PTR_SUB12:%.*]] = sub i64 [[SUB_PTR_LHS_CAST10]], [[SUB_PTR_RHS_CAST11]] 8057 // CHECK12-NEXT: [[SUB_PTR_DIV13:%.*]] = sdiv exact i64 [[SUB_PTR_SUB12]], 4 8058 // CHECK12-NEXT: [[SUB14:%.*]] = sub nsw i64 [[SUB_PTR_DIV13]], 1 8059 // CHECK12-NEXT: [[ADD15:%.*]] = add nsw i64 [[SUB14]], 1 8060 // CHECK12-NEXT: [[DIV16:%.*]] = sdiv i64 [[ADD15]], 1 8061 // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i64 [[DIV]], [[DIV16]] 8062 // CHECK12-NEXT: [[SUB17:%.*]] = sub nsw i64 [[MUL]], 1 8063 // CHECK12-NEXT: store i64 [[SUB17]], i64* [[DOTCAPTURE_EXPR_9]], align 8 8064 // CHECK12-NEXT: [[TMP13:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8065 // CHECK12-NEXT: store i32* [[TMP13]], i32** [[__BEGIN1]], align 8 8066 // CHECK12-NEXT: [[TMP14:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8067 // CHECK12-NEXT: store i32* [[TMP14]], i32** [[__BEGIN2]], align 8 8068 // CHECK12-NEXT: [[TMP15:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8069 // CHECK12-NEXT: [[TMP16:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_5]], align 8 8070 // CHECK12-NEXT: [[CMP:%.*]] = icmp ult i32* [[TMP15]], [[TMP16]] 8071 // CHECK12-NEXT: br i1 [[CMP]], label [[LAND_LHS_TRUE:%.*]], label [[OMP_PRECOND_END:%.*]] 8072 // CHECK12: land.lhs.true: 8073 // CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8074 // CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8075 // CHECK12-NEXT: [[CMP18:%.*]] = icmp ult i32* [[TMP17]], [[TMP18]] 8076 // CHECK12-NEXT: br i1 [[CMP18]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END]] 8077 // CHECK12: omp.precond.then: 8078 // CHECK12-NEXT: store i64 0, i64* [[DOTOMP_LB]], align 8 8079 // CHECK12-NEXT: [[TMP19:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 8080 // CHECK12-NEXT: store i64 [[TMP19]], i64* [[DOTOMP_UB]], align 8 8081 // CHECK12-NEXT: store i64 1, i64* [[DOTOMP_STRIDE]], align 8 8082 // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 8083 // CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8084 // CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 8085 // CHECK12-NEXT: call void @__kmpc_for_static_init_8(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]], i32 34, i32* [[DOTOMP_IS_LAST]], i64* [[DOTOMP_LB]], i64* [[DOTOMP_UB]], i64* [[DOTOMP_STRIDE]], i64 1, i64 1) 8086 // CHECK12-NEXT: [[TMP22:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8087 // CHECK12-NEXT: [[TMP23:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 8088 // CHECK12-NEXT: [[CMP21:%.*]] = icmp sgt i64 [[TMP22]], [[TMP23]] 8089 // CHECK12-NEXT: br i1 [[CMP21]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] 8090 // CHECK12: cond.true: 8091 // CHECK12-NEXT: [[TMP24:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR_9]], align 8 8092 // CHECK12-NEXT: br label [[COND_END:%.*]] 8093 // CHECK12: cond.false: 8094 // CHECK12-NEXT: [[TMP25:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8095 // CHECK12-NEXT: br label [[COND_END]] 8096 // CHECK12: cond.end: 8097 // CHECK12-NEXT: [[COND:%.*]] = phi i64 [ [[TMP24]], [[COND_TRUE]] ], [ [[TMP25]], [[COND_FALSE]] ] 8098 // CHECK12-NEXT: store i64 [[COND]], i64* [[DOTOMP_UB]], align 8 8099 // CHECK12-NEXT: [[TMP26:%.*]] = load i64, i64* [[DOTOMP_LB]], align 8 8100 // CHECK12-NEXT: store i64 [[TMP26]], i64* [[DOTOMP_IV]], align 8 8101 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] 8102 // CHECK12: omp.inner.for.cond: 8103 // CHECK12-NEXT: [[TMP27:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8104 // CHECK12-NEXT: [[TMP28:%.*]] = load i64, i64* [[DOTOMP_UB]], align 8 8105 // CHECK12-NEXT: [[CMP22:%.*]] = icmp sle i64 [[TMP27]], [[TMP28]] 8106 // CHECK12-NEXT: br i1 [[CMP22]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] 8107 // CHECK12: omp.inner.for.body: 8108 // CHECK12-NEXT: [[TMP29:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_]], align 8 8109 // CHECK12-NEXT: [[TMP30:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8110 // CHECK12-NEXT: [[TMP31:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8111 // CHECK12-NEXT: [[TMP32:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8112 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST23:%.*]] = ptrtoint i32* [[TMP31]] to i64 8113 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST24:%.*]] = ptrtoint i32* [[TMP32]] to i64 8114 // CHECK12-NEXT: [[SUB_PTR_SUB25:%.*]] = sub i64 [[SUB_PTR_LHS_CAST23]], [[SUB_PTR_RHS_CAST24]] 8115 // CHECK12-NEXT: [[SUB_PTR_DIV26:%.*]] = sdiv exact i64 [[SUB_PTR_SUB25]], 4 8116 // CHECK12-NEXT: [[SUB27:%.*]] = sub nsw i64 [[SUB_PTR_DIV26]], 1 8117 // CHECK12-NEXT: [[ADD28:%.*]] = add nsw i64 [[SUB27]], 1 8118 // CHECK12-NEXT: [[DIV29:%.*]] = sdiv i64 [[ADD28]], 1 8119 // CHECK12-NEXT: [[MUL30:%.*]] = mul nsw i64 1, [[DIV29]] 8120 // CHECK12-NEXT: [[DIV31:%.*]] = sdiv i64 [[TMP30]], [[MUL30]] 8121 // CHECK12-NEXT: [[MUL32:%.*]] = mul nsw i64 [[DIV31]], 1 8122 // CHECK12-NEXT: [[ADD_PTR33:%.*]] = getelementptr inbounds i32, i32* [[TMP29]], i64 [[MUL32]] 8123 // CHECK12-NEXT: store i32* [[ADD_PTR33]], i32** [[__BEGIN119]], align 8 8124 // CHECK12-NEXT: [[TMP33:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8125 // CHECK12-NEXT: [[TMP34:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8126 // CHECK12-NEXT: [[TMP35:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8127 // CHECK12-NEXT: [[TMP36:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8128 // CHECK12-NEXT: [[TMP37:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8129 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST34:%.*]] = ptrtoint i32* [[TMP36]] to i64 8130 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST35:%.*]] = ptrtoint i32* [[TMP37]] to i64 8131 // CHECK12-NEXT: [[SUB_PTR_SUB36:%.*]] = sub i64 [[SUB_PTR_LHS_CAST34]], [[SUB_PTR_RHS_CAST35]] 8132 // CHECK12-NEXT: [[SUB_PTR_DIV37:%.*]] = sdiv exact i64 [[SUB_PTR_SUB36]], 4 8133 // CHECK12-NEXT: [[SUB38:%.*]] = sub nsw i64 [[SUB_PTR_DIV37]], 1 8134 // CHECK12-NEXT: [[ADD39:%.*]] = add nsw i64 [[SUB38]], 1 8135 // CHECK12-NEXT: [[DIV40:%.*]] = sdiv i64 [[ADD39]], 1 8136 // CHECK12-NEXT: [[MUL41:%.*]] = mul nsw i64 1, [[DIV40]] 8137 // CHECK12-NEXT: [[DIV42:%.*]] = sdiv i64 [[TMP35]], [[MUL41]] 8138 // CHECK12-NEXT: [[TMP38:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_8]], align 8 8139 // CHECK12-NEXT: [[TMP39:%.*]] = load i32*, i32** [[DOTCAPTURE_EXPR_6]], align 8 8140 // CHECK12-NEXT: [[SUB_PTR_LHS_CAST43:%.*]] = ptrtoint i32* [[TMP38]] to i64 8141 // CHECK12-NEXT: [[SUB_PTR_RHS_CAST44:%.*]] = ptrtoint i32* [[TMP39]] to i64 8142 // CHECK12-NEXT: [[SUB_PTR_SUB45:%.*]] = sub i64 [[SUB_PTR_LHS_CAST43]], [[SUB_PTR_RHS_CAST44]] 8143 // CHECK12-NEXT: [[SUB_PTR_DIV46:%.*]] = sdiv exact i64 [[SUB_PTR_SUB45]], 4 8144 // CHECK12-NEXT: [[SUB47:%.*]] = sub nsw i64 [[SUB_PTR_DIV46]], 1 8145 // CHECK12-NEXT: [[ADD48:%.*]] = add nsw i64 [[SUB47]], 1 8146 // CHECK12-NEXT: [[DIV49:%.*]] = sdiv i64 [[ADD48]], 1 8147 // CHECK12-NEXT: [[MUL50:%.*]] = mul nsw i64 1, [[DIV49]] 8148 // CHECK12-NEXT: [[MUL51:%.*]] = mul nsw i64 [[DIV42]], [[MUL50]] 8149 // CHECK12-NEXT: [[SUB52:%.*]] = sub nsw i64 [[TMP34]], [[MUL51]] 8150 // CHECK12-NEXT: [[MUL53:%.*]] = mul nsw i64 [[SUB52]], 1 8151 // CHECK12-NEXT: [[ADD_PTR54:%.*]] = getelementptr inbounds i32, i32* [[TMP33]], i64 [[MUL53]] 8152 // CHECK12-NEXT: store i32* [[ADD_PTR54]], i32** [[__BEGIN220]], align 8 8153 // CHECK12-NEXT: [[TMP40:%.*]] = load i32*, i32** [[__BEGIN119]], align 8 8154 // CHECK12-NEXT: store i32* [[TMP40]], i32** [[A]], align 8 8155 // CHECK12-NEXT: [[TMP41:%.*]] = load i32*, i32** [[__BEGIN220]], align 8 8156 // CHECK12-NEXT: [[TMP42:%.*]] = load i32, i32* [[TMP41]], align 4 8157 // CHECK12-NEXT: store i32 [[TMP42]], i32* [[B]], align 4 8158 // CHECK12-NEXT: [[TMP43:%.*]] = load i32, i32* [[B]], align 4 8159 // CHECK12-NEXT: [[TMP44:%.*]] = load i32*, i32** [[A]], align 8 8160 // CHECK12-NEXT: store i32 [[TMP43]], i32* [[TMP44]], align 4 8161 // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] 8162 // CHECK12: omp.body.continue: 8163 // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] 8164 // CHECK12: omp.inner.for.inc: 8165 // CHECK12-NEXT: [[TMP45:%.*]] = load i64, i64* [[DOTOMP_IV]], align 8 8166 // CHECK12-NEXT: [[ADD55:%.*]] = add nsw i64 [[TMP45]], 1 8167 // CHECK12-NEXT: store i64 [[ADD55]], i64* [[DOTOMP_IV]], align 8 8168 // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] 8169 // CHECK12: omp.inner.for.end: 8170 // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] 8171 // CHECK12: omp.loop.exit: 8172 // CHECK12-NEXT: [[TMP46:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 8173 // CHECK12-NEXT: [[TMP47:%.*]] = load i32, i32* [[TMP46]], align 4 8174 // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP47]]) 8175 // CHECK12-NEXT: br label [[OMP_PRECOND_END]] 8176 // CHECK12: omp.precond.end: 8177 // CHECK12-NEXT: ret void 8178 // 8179