1 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=OMP50,CHECK 2 // RUN: %clang_cc1 -verify -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck %s --check-prefixes=OMP45,CHECK 3 4 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 5 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=OMP50,CHECK 6 7 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 8 // RUN: %clang_cc1 -fopenmp -fopenmp-version=45 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefixes=OMP45,CHECK 9 10 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -gno-column-info -x c++ -emit-llvm %s -o - | FileCheck %s --check-prefix=TERM_DEBUG 11 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -O1 -fopenmp -emit-llvm %s -o - | FileCheck %s --check-prefix=CLEANUP 12 13 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix SIMD-ONLY0 %s 14 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 15 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s 16 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -fopenmp-simd -fexceptions -fcxx-exceptions -debug-info-kind=line-tables-only -x c++ -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s 17 // RUN: %clang_cc1 -verify -triple x86_64-apple-darwin10 -O1 -fopenmp-simd -emit-llvm %s -o - | FileCheck --check-prefix SIMD-ONLY0 %s 18 // SIMD-ONLY0-NOT: {{__kmpc|__tgt}} 19 // expected-no-diagnostics 20 21 // RUN: %clang_cc1 -verify -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix=OMP5 %s 22 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 23 // RUN: %clang_cc1 -fopenmp -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix=OMP5 %s 24 // RUN: %clang_cc1 -verify -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -emit-llvm %s -fexceptions -fcxx-exceptions -o - | FileCheck --check-prefix SIMD-ONLY0 %s 25 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -std=c++11 -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -emit-pch -o %t %s 26 // RUN: %clang_cc1 -fopenmp-simd -DOMP5 -x c++ -triple x86_64-unknown-unknown -fexceptions -fcxx-exceptions -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck --check-prefix SIMD-ONLY0 %s 27 #ifndef HEADER 28 #define HEADER 29 30 #ifndef OMP5 31 // CHECK-DAG: [[IDENT_T_TY:%.+]] = type { i32, i32, i32, i32, i8* } 32 // CHECK-DAG: [[LOOP_LOC:@.+]] = private unnamed_addr constant [[IDENT_T_TY]] { i32 0, i32 514, i32 0, i32 0, i8* 33 34 // CHECK-LABEL: with_var_schedule 35 void with_var_schedule() { 36 double a = 5; 37 // CHECK: [[CHUNK_SIZE:%.+]] = fptosi double %{{.+}}to i8 38 // CHECK: store i8 %{{.+}}, i8* [[CHUNK:%.+]], 39 // CHECK: [[VAL:%.+]] = load i8, i8* [[CHUNK]], 40 // CHECK: store i8 [[VAL]], i8* 41 // CHECK: [[CHUNK:%.+]] = load i64, i64* % 42 // CHECK: call void {{.+}} @__kmpc_fork_call({{.+}}, i64 [[CHUNK]]) 43 44 // CHECK: [[UNDEF_A:%.+]] = load double, double* undef 45 // CHECK: fadd double 2.000000e+00, [[UNDEF_A]] 46 // CHECK: [[CHUNK_VAL:%.+]] = load i8, i8* % 47 // CHECK: [[CHUNK_SIZE:%.+]] = sext i8 [[CHUNK_VAL]] to i64 48 // CHECK: call void @__kmpc_for_static_init_8u([[IDENT_T_TY]]* [[LOOP_LOC]], i32 [[GTID:%[^,]+]], i32 33, i32* [[IS_LAST:%[^,]+]], i64* [[OMP_LB:%[^,]+]], i64* [[OMP_UB:%[^,]+]], i64* [[OMP_ST:%[^,]+]], i64 1, i64 [[CHUNK_SIZE]]) 49 // CHECK: call void @__kmpc_for_static_fini([[IDENT_T_TY]]* [[LOOP_LOC]], i32 [[GTID:%.+]]) 50 #pragma omp parallel for schedule(static, char(a)) private(a) 51 for (unsigned long long i = 1; i < 2 + a; ++i) { 52 } 53 } 54 55 // CHECK-LABEL: define {{.*void}} @{{.*}}without_schedule_clause{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) 56 void without_schedule_clause(float *a, float *b, float *c, float *d) { 57 #pragma omp parallel for 58 // CHECK: call void ([[IDENT_T_TY]]*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* [[OMP_PARALLEL_FUNC:@.+]] to void (i32*, i32*, ...)*), 59 // CHECK: define internal void [[OMP_PARALLEL_FUNC]](i32* noalias [[GTID_PARAM_ADDR:%.+]], i32* noalias %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}) 60 // CHECK: store i32* [[GTID_PARAM_ADDR]], i32** [[GTID_REF_ADDR:%.+]], 61 // CHECK: call void @__kmpc_for_static_init_4([[IDENT_T_TY]]* [[LOOP_LOC]], i32 [[GTID:%.+]], i32 34, i32* [[IS_LAST:%[^,]+]], i32* [[OMP_LB:%[^,]+]], i32* [[OMP_UB:%[^,]+]], i32* [[OMP_ST:%[^,]+]], i32 1, i32 1) 62 // UB = min(UB, GlobalUB) 63 // CHECK-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 64 // CHECK-NEXT: [[UBCMP:%.+]] = icmp sgt i32 [[UB]], 4571423 65 // CHECK-NEXT: br i1 [[UBCMP]], label [[UB_TRUE:%[^,]+]], label [[UB_FALSE:%[^,]+]] 66 // CHECK: [[UBRESULT:%.+]] = phi i32 [ 4571423, [[UB_TRUE]] ], [ [[UBVAL:%[^,]+]], [[UB_FALSE]] ] 67 // CHECK-NEXT: store i32 [[UBRESULT]], i32* [[OMP_UB]] 68 // CHECK-NEXT: [[LB:%.+]] = load i32, i32* [[OMP_LB]] 69 // CHECK-NEXT: store i32 [[LB]], i32* [[OMP_IV:[^,]+]] 70 // Loop header 71 // CHECK: [[IV:%.+]] = load i32, i32* [[OMP_IV]] 72 // CHECK-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 73 // CHECK-NEXT: [[CMP:%.+]] = icmp sle i32 [[IV]], [[UB]] 74 // CHECK-NEXT: br i1 [[CMP]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 75 for (int i = 33; i < 32000000; i += 7) { 76 // CHECK: [[LOOP1_BODY]] 77 // Start of body: calculate i from IV: 78 // CHECK: [[IV1_1:%.+]] = load i32, i32* [[OMP_IV]] 79 // CHECK-NEXT: [[CALC_I_1:%.+]] = mul nsw i32 [[IV1_1]], 7 80 // CHECK-NEXT: [[CALC_I_2:%.+]] = add nsw i32 33, [[CALC_I_1]] 81 // CHECK-NEXT: store i32 [[CALC_I_2]], i32* [[LC_I:.+]] 82 // ... loop body ... 83 // End of body: store into a[i]: 84 // CHECK: store float [[RESULT:%.+]], float* {{%.+}} 85 a[i] = b[i] * c[i] * d[i]; 86 // CHECK: [[IV1_2:%.+]] = load i32, i32* [[OMP_IV]]{{.*}} 87 // CHECK-NEXT: [[ADD1_2:%.+]] = add nsw i32 [[IV1_2]], 1 88 // CHECK-NEXT: store i32 [[ADD1_2]], i32* [[OMP_IV]] 89 // CHECK-NEXT: br label %{{.+}} 90 } 91 // CHECK: [[LOOP1_END]] 92 // CHECK: call void @__kmpc_for_static_fini([[IDENT_T_TY]]* [[LOOP_LOC]], i32 [[GTID]]) 93 // CHECK: ret void 94 } 95 96 // CHECK-LABEL: define {{.*void}} @{{.*}}static_not_chunked{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) 97 void static_not_chunked(float *a, float *b, float *c, float *d) { 98 #pragma omp parallel for schedule(static) 99 // CHECK: call void ([[IDENT_T_TY]]*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* [[OMP_PARALLEL_FUNC:@.+]] to void (i32*, i32*, ...)*), 100 // CHECK: define internal void [[OMP_PARALLEL_FUNC]](i32* noalias [[GTID_PARAM_ADDR:%.+]], i32* noalias %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}) 101 // CHECK: store i32* [[GTID_PARAM_ADDR]], i32** [[GTID_REF_ADDR:%.+]], 102 // CHECK: call void @__kmpc_for_static_init_4([[IDENT_T_TY]]* [[LOOP_LOC]], i32 [[GTID:%.+]], i32 34, i32* [[IS_LAST:%[^,]+]], i32* [[OMP_LB:%[^,]+]], i32* [[OMP_UB:%[^,]+]], i32* [[OMP_ST:%[^,]+]], i32 1, i32 1) 103 // UB = min(UB, GlobalUB) 104 // CHECK-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 105 // CHECK-NEXT: [[UBCMP:%.+]] = icmp sgt i32 [[UB]], 4571423 106 // CHECK-NEXT: br i1 [[UBCMP]], label [[UB_TRUE:%[^,]+]], label [[UB_FALSE:%[^,]+]] 107 // CHECK: [[UBRESULT:%.+]] = phi i32 [ 4571423, [[UB_TRUE]] ], [ [[UBVAL:%[^,]+]], [[UB_FALSE]] ] 108 // CHECK-NEXT: store i32 [[UBRESULT]], i32* [[OMP_UB]] 109 // CHECK-NEXT: [[LB:%.+]] = load i32, i32* [[OMP_LB]] 110 // CHECK-NEXT: store i32 [[LB]], i32* [[OMP_IV:[^,]+]] 111 // Loop header 112 // CHECK: [[IV:%.+]] = load i32, i32* [[OMP_IV]] 113 // CHECK-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 114 // CHECK-NEXT: [[CMP:%.+]] = icmp sle i32 [[IV]], [[UB]] 115 // CHECK-NEXT: br i1 [[CMP]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 116 for (int i = 32000000; i > 33; i += -7) { 117 // CHECK: [[LOOP1_BODY]] 118 // Start of body: calculate i from IV: 119 // CHECK: [[IV1_1:%.+]] = load i32, i32* [[OMP_IV]] 120 // CHECK-NEXT: [[CALC_I_1:%.+]] = mul nsw i32 [[IV1_1]], 7 121 // CHECK-NEXT: [[CALC_I_2:%.+]] = sub nsw i32 32000000, [[CALC_I_1]] 122 // CHECK-NEXT: store i32 [[CALC_I_2]], i32* [[LC_I:.+]] 123 // ... loop body ... 124 // End of body: store into a[i]: 125 // CHECK: store float [[RESULT:%.+]], float* {{%.+}} 126 a[i] = b[i] * c[i] * d[i]; 127 // CHECK: [[IV1_2:%.+]] = load i32, i32* [[OMP_IV]]{{.*}} 128 // CHECK-NEXT: [[ADD1_2:%.+]] = add nsw i32 [[IV1_2]], 1 129 // CHECK-NEXT: store i32 [[ADD1_2]], i32* [[OMP_IV]] 130 // CHECK-NEXT: br label %{{.+}} 131 } 132 // CHECK: [[LOOP1_END]] 133 // CHECK: call void @__kmpc_for_static_fini([[IDENT_T_TY]]* [[LOOP_LOC]], i32 [[GTID]]) 134 // CHECK: ret void 135 } 136 137 // CHECK-LABEL: define {{.*void}} @{{.*}}static_chunked{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) 138 void static_chunked(float *a, float *b, float *c, float *d) { 139 #pragma omp parallel for schedule(static, 5) 140 // CHECK: call void ([[IDENT_T_TY]]*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* [[OMP_PARALLEL_FUNC:@.+]] to void (i32*, i32*, ...)*), 141 // CHECK: define internal void [[OMP_PARALLEL_FUNC]](i32* noalias [[GTID_PARAM_ADDR:%.+]], i32* noalias %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}) 142 // CHECK: store i32* [[GTID_PARAM_ADDR]], i32** [[GTID_REF_ADDR:%.+]], 143 // CHECK: call void @__kmpc_for_static_init_4u([[IDENT_T_TY]]* [[LOOP_LOC]], i32 [[GTID:%.+]], i32 33, i32* [[IS_LAST:%[^,]+]], i32* [[OMP_LB:%[^,]+]], i32* [[OMP_UB:%[^,]+]], i32* [[OMP_ST:%[^,]+]], i32 1, i32 5) 144 // UB = min(UB, GlobalUB) 145 // CHECK: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 146 // CHECK-NEXT: [[UBCMP:%.+]] = icmp ugt i32 [[UB]], 16908288 147 // CHECK-NEXT: br i1 [[UBCMP]], label [[UB_TRUE:%[^,]+]], label [[UB_FALSE:%[^,]+]] 148 // CHECK: [[UBRESULT:%.+]] = phi i32 [ 16908288, [[UB_TRUE]] ], [ [[UBVAL:%[^,]+]], [[UB_FALSE]] ] 149 // CHECK-NEXT: store i32 [[UBRESULT]], i32* [[OMP_UB]] 150 // CHECK-NEXT: [[LB:%.+]] = load i32, i32* [[OMP_LB]] 151 // CHECK-NEXT: store i32 [[LB]], i32* [[OMP_IV:[^,]+]] 152 153 // Outer loop header 154 // CHECK: [[O_IV:%.+]] = load i32, i32* [[OMP_IV]] 155 // CHECK-NEXT: [[O_UB:%.+]] = load i32, i32* [[OMP_UB]] 156 // CHECK-NEXT: [[O_CMP:%.+]] = icmp ule i32 [[O_IV]], [[O_UB]] 157 // CHECK-NEXT: br i1 [[O_CMP]], label %[[O_LOOP1_BODY:[^,]+]], label %[[O_LOOP1_END:[^,]+]] 158 159 // Loop header 160 // CHECK: [[O_LOOP1_BODY]] 161 // CHECK: [[IV:%.+]] = load i32, i32* [[OMP_IV]] 162 // CHECK-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 163 // CHECK-NEXT: [[CMP:%.+]] = icmp ule i32 [[IV]], [[UB]] 164 // CHECK-NEXT: br i1 [[CMP]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 165 for (unsigned i = 131071; i <= 2147483647; i += 127) { 166 // CHECK: [[LOOP1_BODY]] 167 // Start of body: calculate i from IV: 168 // CHECK: [[IV1_1:%.+]] = load i32, i32* [[OMP_IV]] 169 // CHECK-NEXT: [[CALC_I_1:%.+]] = mul i32 [[IV1_1]], 127 170 // CHECK-NEXT: [[CALC_I_2:%.+]] = add i32 131071, [[CALC_I_1]] 171 // CHECK-NEXT: store i32 [[CALC_I_2]], i32* [[LC_I:.+]] 172 // ... loop body ... 173 // End of body: store into a[i]: 174 // CHECK: store float [[RESULT:%.+]], float* {{%.+}} 175 a[i] = b[i] * c[i] * d[i]; 176 // CHECK: [[IV1_2:%.+]] = load i32, i32* [[OMP_IV]]{{.*}} 177 // CHECK-NEXT: [[ADD1_2:%.+]] = add i32 [[IV1_2]], 1 178 // CHECK-NEXT: store i32 [[ADD1_2]], i32* [[OMP_IV]] 179 // CHECK-NEXT: br label %{{.+}} 180 } 181 // CHECK: [[LOOP1_END]] 182 // Update the counters, adding stride 183 // CHECK: [[LB:%.+]] = load i32, i32* [[OMP_LB]] 184 // CHECK-NEXT: [[ST:%.+]] = load i32, i32* [[OMP_ST]] 185 // CHECK-NEXT: [[ADD_LB:%.+]] = add i32 [[LB]], [[ST]] 186 // CHECK-NEXT: store i32 [[ADD_LB]], i32* [[OMP_LB]] 187 // CHECK-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 188 // CHECK-NEXT: [[ST:%.+]] = load i32, i32* [[OMP_ST]] 189 // CHECK-NEXT: [[ADD_UB:%.+]] = add i32 [[UB]], [[ST]] 190 // CHECK-NEXT: store i32 [[ADD_UB]], i32* [[OMP_UB]] 191 192 // CHECK: [[O_LOOP1_END]] 193 // CHECK: call void @__kmpc_for_static_fini([[IDENT_T_TY]]* [[LOOP_LOC]], i32 [[GTID]]) 194 // CHECK: ret void 195 } 196 197 // CHECK-LABEL: define {{.*void}} @{{.*}}dynamic1{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) 198 void dynamic1(float *a, float *b, float *c, float *d) { 199 #pragma omp parallel for schedule(dynamic) 200 // CHECK: call void ([[IDENT_T_TY]]*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* [[OMP_PARALLEL_FUNC:@.+]] to void (i32*, i32*, ...)*), 201 // CHECK: define internal void [[OMP_PARALLEL_FUNC]](i32* noalias [[GTID_PARAM_ADDR:%.+]], i32* noalias %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}) 202 // CHECK: store i32* [[GTID_PARAM_ADDR]], i32** [[GTID_REF_ADDR:%.+]], 203 // OMP45: call void @__kmpc_dispatch_init_8u([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID:%.+]], i32 35, i64 0, i64 16908287, i64 1, i64 1) 204 // OMP50: call void @__kmpc_dispatch_init_8u([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID:%.+]], i32 1073741859, i64 0, i64 16908287, i64 1, i64 1) 205 // 206 // CHECK: [[HASWORK:%.+]] = call i32 @__kmpc_dispatch_next_8u([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID]], i32* [[OMP_ISLAST:%[^,]+]], i64* [[OMP_LB:%[^,]+]], i64* [[OMP_UB:%[^,]+]], i64* [[OMP_ST:%[^,]+]]) 207 // CHECK-NEXT: [[O_CMP:%.+]] = icmp ne i32 [[HASWORK]], 0 208 // CHECK-NEXT: br i1 [[O_CMP]], label %[[O_LOOP1_BODY:[^,]+]], label %[[O_LOOP1_END:[^,]+]] 209 210 // Loop header 211 // CHECK: [[O_LOOP1_BODY]] 212 // CHECK: [[LB:%.+]] = load i64, i64* [[OMP_LB]] 213 // CHECK-NEXT: store i64 [[LB]], i64* [[OMP_IV:[^,]+]] 214 // CHECK: [[IV:%.+]] = load i64, i64* [[OMP_IV]] 215 216 // CHECK-NEXT: [[UB:%.+]] = load i64, i64* [[OMP_UB]] 217 // CHECK-NEXT: [[BOUND:%.+]] = add i64 [[UB]], 1 218 // CHECK-NEXT: [[CMP:%.+]] = icmp ult i64 [[IV]], [[BOUND]] 219 // CHECK-NEXT: br i1 [[CMP]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 220 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 221 // CHECK: [[LOOP1_BODY]] 222 // Start of body: calculate i from IV: 223 // CHECK: [[IV1_1:%.+]] = load i64, i64* [[OMP_IV]] 224 // CHECK-NEXT: [[CALC_I_1:%.+]] = mul i64 [[IV1_1]], 127 225 // CHECK-NEXT: [[CALC_I_2:%.+]] = add i64 131071, [[CALC_I_1]] 226 // CHECK-NEXT: store i64 [[CALC_I_2]], i64* [[LC_I:.+]] 227 // ... loop body ... 228 // End of body: store into a[i]: 229 // CHECK: store float [[RESULT:%.+]], float* {{%.+}} 230 a[i] = b[i] * c[i] * d[i]; 231 // CHECK: [[IV1_2:%.+]] = load i64, i64* [[OMP_IV]]{{.*}} 232 // CHECK-NEXT: [[ADD1_2:%.+]] = add i64 [[IV1_2]], 1 233 // CHECK-NEXT: store i64 [[ADD1_2]], i64* [[OMP_IV]] 234 // CHECK-NEXT: br label %{{.+}} 235 } 236 // CHECK: [[LOOP1_END]] 237 // CHECK: [[O_LOOP1_END]] 238 // CHECK: ret void 239 } 240 241 // CHECK-LABEL: define {{.*void}} @{{.*}}guided7{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) 242 void guided7(float *a, float *b, float *c, float *d) { 243 #pragma omp parallel for schedule(guided, 7) 244 // CHECK: call void ([[IDENT_T_TY]]*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* [[OMP_PARALLEL_FUNC:@.+]] to void (i32*, i32*, ...)*), 245 // CHECK: define internal void [[OMP_PARALLEL_FUNC]](i32* noalias [[GTID_PARAM_ADDR:%.+]], i32* noalias %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}) 246 // CHECK: store i32* [[GTID_PARAM_ADDR]], i32** [[GTID_REF_ADDR:%.+]], 247 // OMP45: call void @__kmpc_dispatch_init_8u([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID:%.+]], i32 36, i64 0, i64 16908287, i64 1, i64 7) 248 // OMP50: call void @__kmpc_dispatch_init_8u([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID:%.+]], i32 1073741860, i64 0, i64 16908287, i64 1, i64 7) 249 // 250 // CHECK: [[HASWORK:%.+]] = call i32 @__kmpc_dispatch_next_8u([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID]], i32* [[OMP_ISLAST:%[^,]+]], i64* [[OMP_LB:%[^,]+]], i64* [[OMP_UB:%[^,]+]], i64* [[OMP_ST:%[^,]+]]) 251 // CHECK-NEXT: [[O_CMP:%.+]] = icmp ne i32 [[HASWORK]], 0 252 // CHECK-NEXT: br i1 [[O_CMP]], label %[[O_LOOP1_BODY:[^,]+]], label %[[O_LOOP1_END:[^,]+]] 253 254 // Loop header 255 // CHECK: [[O_LOOP1_BODY]] 256 // CHECK: [[LB:%.+]] = load i64, i64* [[OMP_LB]] 257 // CHECK-NEXT: store i64 [[LB]], i64* [[OMP_IV:[^,]+]] 258 // CHECK: [[IV:%.+]] = load i64, i64* [[OMP_IV]] 259 260 // CHECK-NEXT: [[UB:%.+]] = load i64, i64* [[OMP_UB]] 261 // CHECK-NEXT: [[BOUND:%.+]] = add i64 [[UB]], 1 262 // CHECK-NEXT: [[CMP:%.+]] = icmp ult i64 [[IV]], [[BOUND]] 263 // CHECK-NEXT: br i1 [[CMP]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 264 for (unsigned long long i = 131071; i < 2147483647; i += 127) { 265 // CHECK: [[LOOP1_BODY]] 266 // Start of body: calculate i from IV: 267 // CHECK: [[IV1_1:%.+]] = load i64, i64* [[OMP_IV]] 268 // CHECK-NEXT: [[CALC_I_1:%.+]] = mul i64 [[IV1_1]], 127 269 // CHECK-NEXT: [[CALC_I_2:%.+]] = add i64 131071, [[CALC_I_1]] 270 // CHECK-NEXT: store i64 [[CALC_I_2]], i64* [[LC_I:.+]] 271 // ... loop body ... 272 // End of body: store into a[i]: 273 // CHECK: store float [[RESULT:%.+]], float* {{%.+}} 274 a[i] = b[i] * c[i] * d[i]; 275 // CHECK: [[IV1_2:%.+]] = load i64, i64* [[OMP_IV]]{{.*}} 276 // CHECK-NEXT: [[ADD1_2:%.+]] = add i64 [[IV1_2]], 1 277 // CHECK-NEXT: store i64 [[ADD1_2]], i64* [[OMP_IV]] 278 // CHECK-NEXT: br label %{{.+}} 279 } 280 // CHECK: [[LOOP1_END]] 281 // CHECK: [[O_LOOP1_END]] 282 // CHECK: ret void 283 } 284 285 // CHECK-LABEL: define {{.*void}} @{{.*}}test_auto{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) 286 void test_auto(float *a, float *b, float *c, float *d) { 287 unsigned int x = 0; 288 unsigned int y = 0; 289 #pragma omp parallel for schedule(auto) collapse(2) 290 // CHECK: call void ([[IDENT_T_TY]]*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, float**, float**, float**, float**)* [[OMP_PARALLEL_FUNC:@.+]] to void (i32*, i32*, ...)*), 291 // CHECK: define internal void [[OMP_PARALLEL_FUNC]](i32* noalias [[GTID_PARAM_ADDR:%.+]], i32* noalias %{{.+}}, i32* nonnull align 4 dereferenceable(4) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}) 292 // CHECK: store i32* [[GTID_PARAM_ADDR]], i32** [[GTID_REF_ADDR:%.+]], 293 // OMP45: call void @__kmpc_dispatch_init_8([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID:%.+]], i32 38, i64 0, i64 [[LAST_ITER:%[^,]+]], i64 1, i64 1) 294 // OMP50: call void @__kmpc_dispatch_init_8([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID:%.+]], i32 1073741862, i64 0, i64 [[LAST_ITER:%[^,]+]], i64 1, i64 1) 295 // 296 // CHECK: [[HASWORK:%.+]] = call i32 @__kmpc_dispatch_next_8([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID:%.+]], i32* [[OMP_ISLAST:%[^,]+]], i64* [[OMP_LB:%[^,]+]], i64* [[OMP_UB:%[^,]+]], i64* [[OMP_ST:%[^,]+]]) 297 // CHECK-NEXT: [[O_CMP:%.+]] = icmp ne i32 [[HASWORK]], 0 298 // CHECK-NEXT: br i1 [[O_CMP]], label %[[O_LOOP1_BODY:[^,]+]], label %[[O_LOOP1_END:[^,]+]] 299 300 // Loop header 301 // CHECK: [[O_LOOP1_BODY]] 302 // CHECK: [[LB:%.+]] = load i64, i64* [[OMP_LB]] 303 // CHECK-NEXT: store i64 [[LB]], i64* [[OMP_IV:[^,]+]] 304 // CHECK: [[IV:%.+]] = load i64, i64* [[OMP_IV]] 305 306 // CHECK-NEXT: [[UB:%.+]] = load i64, i64* [[OMP_UB]] 307 // CHECK-NEXT: [[CMP:%.+]] = icmp sle i64 [[IV]], [[UB]] 308 // CHECK-NEXT: br i1 [[CMP]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 309 // FIXME: When the iteration count of some nested loop is not a known constant, 310 // we should pre-calculate it, like we do for the total number of iterations! 311 for (char i = static_cast<char>(y); i <= '9'; ++i) 312 for (x = 11; x > 0; --x) { 313 // CHECK: [[LOOP1_BODY]] 314 // Start of body: indices are calculated from IV: 315 // CHECK: store i8 {{%[^,]+}}, i8* {{%[^,]+}} 316 // CHECK: store i32 {{%[^,]+}}, i32* {{%[^,]+}} 317 // ... loop body ... 318 // End of body: store into a[i]: 319 // CHECK: store float [[RESULT:%.+]], float* {{%.+}} 320 a[i] = b[i] * c[i] * d[i]; 321 // CHECK: [[IV1_2:%.+]] = load i64, i64* [[OMP_IV]]{{.*}} 322 // CHECK-NEXT: [[ADD1_2:%.+]] = add nsw i64 [[IV1_2]], 1 323 // CHECK-NEXT: store i64 [[ADD1_2]], i64* [[OMP_IV]] 324 // CHECK-NEXT: br label %{{.+}} 325 } 326 // CHECK: [[LOOP1_END]] 327 // CHECK: [[O_LOOP1_END]] 328 // CHECK: ret void 329 } 330 331 // CHECK-LABEL: define {{.*void}} @{{.*}}runtime{{.*}}(float* {{.+}}, float* {{.+}}, float* {{.+}}, float* {{.+}}) 332 void runtime(float *a, float *b, float *c, float *d) { 333 int x = 0; 334 #pragma omp parallel for collapse(2) schedule(runtime) 335 // CHECK: call void ([[IDENT_T_TY]]*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call([[IDENT_T_TY]]* [[DEFAULT_LOC:[@%].+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, float**, float**, float**, float**)* [[OMP_PARALLEL_FUNC:@.+]] to void (i32*, i32*, ...)*), 336 // CHECK: define internal void [[OMP_PARALLEL_FUNC]](i32* noalias [[GTID_PARAM_ADDR:%.+]], i32* noalias %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}, float** nonnull align 8 dereferenceable(8) %{{.+}}) 337 // CHECK: store i32* [[GTID_PARAM_ADDR]], i32** [[GTID_REF_ADDR:%.+]], 338 // OMP45: call void @__kmpc_dispatch_init_4([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID:%.+]], i32 37, i32 0, i32 199, i32 1, i32 1) 339 // OMP50: call void @__kmpc_dispatch_init_4([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID:%.+]], i32 1073741861, i32 0, i32 199, i32 1, i32 1) 340 // 341 // CHECK: [[HASWORK:%.+]] = call i32 @__kmpc_dispatch_next_4([[IDENT_T_TY]]* [[DEFAULT_LOC]], i32 [[GTID]], i32* [[OMP_ISLAST:%[^,]+]], i32* [[OMP_LB:%[^,]+]], i32* [[OMP_UB:%[^,]+]], i32* [[OMP_ST:%[^,]+]]) 342 // CHECK-NEXT: [[O_CMP:%.+]] = icmp ne i32 [[HASWORK]], 0 343 // CHECK-NEXT: br i1 [[O_CMP]], label %[[O_LOOP1_BODY:[^,]+]], label %[[O_LOOP1_END:[^,]+]] 344 345 // Loop header 346 // CHECK: [[O_LOOP1_BODY]] 347 // CHECK: [[LB:%.+]] = load i32, i32* [[OMP_LB]] 348 // CHECK-NEXT: store i32 [[LB]], i32* [[OMP_IV:[^,]+]] 349 // CHECK: [[IV:%.+]] = load i32, i32* [[OMP_IV]] 350 351 // CHECK-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 352 // CHECK-NEXT: [[CMP:%.+]] = icmp sle i32 [[IV]], [[UB]] 353 // CHECK-NEXT: br i1 [[CMP]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 354 for (unsigned char i = '0' ; i <= '9'; ++i) 355 for (x = -10; x < 10; ++x) { 356 // CHECK: [[LOOP1_BODY]] 357 // Start of body: indices are calculated from IV: 358 // CHECK: store i8 {{%[^,]+}}, i8* {{%[^,]+}} 359 // CHECK: store i32 {{%[^,]+}}, i32* {{%[^,]+}} 360 // ... loop body ... 361 // End of body: store into a[i]: 362 // CHECK: store float [[RESULT:%.+]], float* {{%.+}} 363 a[i] = b[i] * c[i] * d[i]; 364 // CHECK: [[IV1_2:%.+]] = load i32, i32* [[OMP_IV]]{{.*}} 365 // CHECK-NEXT: [[ADD1_2:%.+]] = add nsw i32 [[IV1_2]], 1 366 // CHECK-NEXT: store i32 [[ADD1_2]], i32* [[OMP_IV]] 367 // CHECK-NEXT: br label %{{.+}} 368 } 369 // CHECK: [[LOOP1_END]] 370 // CHECK: [[O_LOOP1_END]] 371 // CHECK: ret void 372 } 373 374 // TERM_DEBUG-LABEL: foo 375 int foo() { extern void mayThrow(); mayThrow(); return 0; }; 376 377 // TERM_DEBUG-LABEL: parallel_for 378 // CLEANUP: parallel_for 379 void parallel_for(float *a, const int n) { 380 float arr[n]; 381 #pragma omp parallel for schedule(static, 5) private(arr) default(none) firstprivate(n) shared(a) 382 // TERM_DEBUG-NOT: __kmpc_global_thread_num 383 // TERM_DEBUG: call void @__kmpc_for_static_init_4u({{.+}}), !dbg [[DBG_LOC_START:![0-9]+]] 384 // TERM_DEBUG: invoke i32 {{.*}}foo{{.*}}() 385 // TERM_DEBUG: unwind label %[[TERM_LPAD:.+]], 386 // TERM_DEBUG-NOT: __kmpc_global_thread_num 387 // TERM_DEBUG: call void @__kmpc_for_static_fini({{.+}}), !dbg [[DBG_LOC_START]] 388 // TERM_DEBUG: [[TERM_LPAD]] 389 // TERM_DEBUG: call void @__clang_call_terminate 390 // TERM_DEBUG: unreachable 391 // CLEANUP-NOT: __kmpc_global_thread_num 392 // CLEANUP: call void @__kmpc_for_static_init_4u({{.+}}) 393 // CLEANUP: call void @__kmpc_for_static_fini({{.+}}) 394 for (unsigned i = 131071; i <= 2147483647; i += 127) 395 a[i] += foo() + arr[i] + n; 396 } 397 // Check source line corresponds to "#pragma omp parallel for schedule(static, 5)" above: 398 // TERM_DEBUG-DAG: [[DBG_LOC_START]] = !DILocation(line: [[@LINE-17]], 399 400 #else // OMP5 401 // OMP5-LABEL: increment 402 int increment () { 403 // OMP5: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* [[DEFAULT_LOC:[@%].+]]) 404 #pragma omp for 405 // Determine UB = min(UB, GlobalUB) 406 // OMP5: call void @__kmpc_for_static_init_4(%struct.ident_t* [[LOOP_LOC:[@%].+]], i32 [[GTID]], i32 34, i32* [[IS_LAST:%[^,]+]], i32* [[OMP_LB:%[^,]+]], i32* [[OMP_UB:%[^,]+]], i32* [[OMP_ST:%[^,]+]], i32 1, i32 1) 407 // OMP5-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 408 // OMP5-NEXT: [[UBCMP:%.+]] = icmp sgt i32 [[UB]], 4 409 // OMP5-NEXT: br i1 [[UBCMP]], label [[UB_TRUE:%[^,]+]], label [[UB_FALSE:%[^,]+]] 410 // OMP5: [[UBRESULT:%.+]] = phi i32 [ 4, [[UB_TRUE]] ], [ [[UBVAL:%[^,]+]], [[UB_FALSE]] ] 411 // OMP5-NEXT: store i32 [[UBRESULT]], i32* [[OMP_UB]] 412 // OMP5-NEXT: [[LB:%.+]] = load i32, i32* [[OMP_LB]] 413 // OMP5-NEXT: store i32 [[LB]], i32* [[OMP_IV:[^,]+]] 414 // OMP5-NEXT: br label %[[LOOP1_HEAD:.+]] 415 416 // Loop header 417 // OMP5: [[LOOP1_HEAD]] 418 // OMP5: [[IV:%.+]] = load i32, i32* [[OMP_IV]] 419 // OMP5-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 420 // OMP5-NEXT: [[CMP:%.+]] = icmp sle i32 [[IV]], [[UB]] 421 // OMP5-NEXT: br i1 [[CMP]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 422 423 for (int i = 0 ; i != 5; ++i) 424 // Start of body: calculate i from IV: 425 // OMP5: [[LOOP1_BODY]] 426 // OMP5: [[IV1_1:%.+]] = load i32, i32* [[OMP_IV]] 427 // OMP5-NEXT: [[CALC_I_1:%.+]] = mul nsw i32 [[IV1_1]], 1 428 // OMP5-NEXT: [[CALC_I_2:%.+]] = add nsw i32 0, [[CALC_I_1]] 429 // OMP5-NEXT: store i32 [[CALC_I_2]], i32* [[LC_I:.+]] 430 // OMP5: [[IV1_2:%.+]] = load i32, i32* [[OMP_IV]]{{.*}} 431 // OMP5-NEXT: [[ADD1_2:%.+]] = add nsw i32 [[IV1_2]], 1 432 // OMP5-NEXT: store i32 [[ADD1_2]], i32* [[OMP_IV]] 433 // OMP5-NEXT: br label %[[LOOP1_HEAD]] 434 ; 435 // OMP5: [[LOOP1_END]] 436 // OMP5: call void @__kmpc_for_static_fini(%struct.ident_t* [[LOOP_LOC]], i32 [[GTID]]) 437 // OMP5: __kmpc_barrier 438 return 0; 439 // OMP5: ret i32 0 440 } 441 442 // OMP5-LABEL: decrement_nowait 443 int decrement_nowait () { 444 // OMP5: [[GTID:%.+]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* [[DEFAULT_LOC:[@%].+]]) 445 #pragma omp for nowait 446 // Determine UB = min(UB, GlobalUB) 447 // OMP5: call void @__kmpc_for_static_init_4(%struct.ident_t* [[LOOP_LOC]], i32 [[GTID]], i32 34, i32* [[IS_LAST:%[^,]+]], i32* [[OMP_LB:%[^,]+]], i32* [[OMP_UB:%[^,]+]], i32* [[OMP_ST:%[^,]+]], i32 1, i32 1) 448 // OMP5-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 449 // OMP5-NEXT: [[UBCMP:%.+]] = icmp sgt i32 [[UB]], 4 450 // OMP5-NEXT: br i1 [[UBCMP]], label [[UB_TRUE:%[^,]+]], label [[UB_FALSE:%[^,]+]] 451 // OMP5: [[UBRESULT:%.+]] = phi i32 [ 4, [[UB_TRUE]] ], [ [[UBVAL:%[^,]+]], [[UB_FALSE]] ] 452 // OMP5-NEXT: store i32 [[UBRESULT]], i32* [[OMP_UB]] 453 // OMP5-NEXT: [[LB:%.+]] = load i32, i32* [[OMP_LB]] 454 // OMP5-NEXT: store i32 [[LB]], i32* [[OMP_IV:[^,]+]] 455 // OMP5-NEXT: br label %[[LOOP1_HEAD:.+]] 456 457 // Loop header 458 // OMP5: [[LOOP1_HEAD]] 459 // OMP5: [[IV:%.+]] = load i32, i32* [[OMP_IV]] 460 // OMP5-NEXT: [[UB:%.+]] = load i32, i32* [[OMP_UB]] 461 // OMP5-NEXT: [[CMP:%.+]] = icmp sle i32 [[IV]], [[UB]] 462 // OMP5-NEXT: br i1 [[CMP]], label %[[LOOP1_BODY:[^,]+]], label %[[LOOP1_END:[^,]+]] 463 for (int j = 5 ; j != 0; --j) 464 // Start of body: calculate i from IV: 465 // OMP5: [[LOOP1_BODY]] 466 // OMP5: [[IV2_1:%.+]] = load i32, i32* [[OMP_IV]] 467 // OMP5-NEXT: [[CALC_II_1:%.+]] = mul nsw i32 [[IV2_1]], 1 468 // OMP5-NEXT: [[CALC_II_2:%.+]] = sub nsw i32 5, [[CALC_II_1]] 469 // OMP5-NEXT: store i32 [[CALC_II_2]], i32* [[LC_I:.+]] 470 // OMP5: [[IV2_2:%.+]] = load i32, i32* [[OMP_IV]]{{.*}} 471 // OMP5-NEXT: [[ADD2_2:%.+]] = add nsw i32 [[IV2_2]], 1 472 // OMP5-NEXT: store i32 [[ADD2_2]], i32* [[OMP_IV]] 473 // OMP5-NEXT: br label %[[LOOP1_HEAD]] 474 ; 475 // OMP5: [[LOOP1_END]] 476 // OMP5: call void @__kmpc_for_static_fini(%struct.ident_t* [[LOOP_LOC]], i32 [[GTID]]) 477 // OMP5-NOT: __kmpc_barrier 478 return 0; 479 // OMP5: ret i32 0 480 } 481 482 // OMP5-LABEL: range_for_single 483 void range_for_single() { 484 int arr[10] = {0}; 485 // OMP5: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* {{.+}}, i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [10 x i32]*)* [[OUTLINED:@.+]] to void (i32*, i32*, ...)*), [10 x i32]* %{{.+}}) 486 #pragma omp parallel for 487 for (auto &a : arr) 488 (void)a; 489 } 490 491 // OMP5: define internal void @.omp_outlined.(i32* {{.+}}, i32* {{.+}}, [10 x i32]* nonnull align 4 dereferenceable(40) %arr) 492 // OMP5: [[ARR_ADDR:%.+]] = alloca [10 x i32]*, 493 // OMP5: [[IV:%.+]] = alloca i64, 494 // OMP5: [[RANGE_ADDR:%.+]] = alloca [10 x i32]*, 495 // OMP5: [[END_ADDR:%.+]] = alloca i32*, 496 // OMP5: alloca i32*, 497 // OMP5: alloca i32*, 498 // OMP5: alloca i64, 499 // OMP5: [[BEGIN_INIT:%.+]] = alloca i32*, 500 // OMP5: [[LB:%.+]] = alloca i64, 501 // OMP5: [[UB:%.+]] = alloca i64, 502 // OMP5: [[STRIDE:%.+]] = alloca i64, 503 // OMP5: [[IS_LAST:%.+]] = alloca i32, 504 // OMP5: [[BEGIN:%.+]] = alloca i32*, 505 // OMP5: [[A_PTR:%.+]] = alloca i32*, 506 507 // __range = arr; 508 // OMP5: [[ARR:%.+]] = load [10 x i32]*, [10 x i32]** [[ARR_ADDR]], 509 // OMP5: store [10 x i32]* [[ARR]], [10 x i32]** [[RANGE_ADDR]], 510 511 // __end = end(_range); 512 // OMP5: [[RANGE:%.+]] = load [10 x i32]*, [10 x i32]** [[RANGE_ADDR]], 513 // OMP5: [[RANGE_0:%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[RANGE]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 514 // OMP5: [[RANGE_10:%.+]] = getelementptr inbounds i32, i32* [[RANGE_0]], i{{[0-9]+}} 10 515 // OMP5: store i32* [[RANGE_10]], i32** [[END_ADDR]], 516 517 // OMP5: [[RANGE:%.+]] = load [10 x i32]*, [10 x i32]** [[RANGE_ADDR]], 518 // OMP5: [[RANGE_0:%.+]] = getelementptr inbounds [10 x i32], [10 x i32]* [[RANGE]], i{{[0-9]+}} 0, i{{[0-9]+}} 0 519 // OMP5: store i32* [[RANGE_0]], i32** [[CAP1:%.+]], 520 // OMP5: [[END:%.+]] = load i32*, i32** [[END_ADDR]], 521 // OMP5: store i32* [[END]], i32** [[CAP2:%.+]], 522 523 // calculate number of elements. 524 // OMP5: [[CAP2_VAL:%.+]] = load i32*, i32** [[CAP2]], 525 // OMP5: [[CAP1_VAL:%.+]] = load i32*, i32** [[CAP1]], 526 // OMP5: [[CAP2_I64:%.+]] = ptrtoint i32* [[CAP2_VAL]] to i64 527 // OMP5: [[CAP1_I64:%.+]] = ptrtoint i32* [[CAP1_VAL]] to i64 528 // OMP5: [[DIFF:%.+]] = sub i64 [[CAP2_I64]], [[CAP1_I64]] 529 // OMP5: [[NUM:%.+]] = sdiv exact i64 [[DIFF]], 4 530 // OMP5: [[NUM1:%.+]] = sub nsw i64 [[NUM]], 1 531 // OMP5: [[NUM2:%.+]] = add nsw i64 [[NUM1]], 1 532 // OMP5: [[NUM3:%.+]] = sdiv i64 [[NUM2]], 1 533 // OMP5: [[NUM4:%.+]] = sub nsw i64 [[NUM3]], 1 534 // OMP5: store i64 [[NUM4]], i64* [[CAP3:%.+]], 535 // OMP5: [[RANGE_0:%.+]] = load i32*, i32** [[CAP1]], 536 537 // __begin = begin(range); 538 // OMP5: store i32* [[RANGE_0]], i32** [[BEGIN_INIT]], 539 // OMP5: [[CAP1_VAL:%.+]] = load i32*, i32** [[CAP1]], 540 // OMP5: [[CAP2_VAL:%.+]] = load i32*, i32** [[CAP2]], 541 // OMP5: [[CMP:%.+]] = icmp ult i32* [[CAP1_VAL]], [[CAP2_VAL]] 542 543 // __begin >= __end ? goto then : goto exit; 544 // OMP5: br i1 [[CMP]], label %[[THEN:.+]], label %[[EXIT:.+]] 545 546 // OMP5: [[THEN]]: 547 548 // lb = 0; 549 // OMP5: store i64 0, i64* [[LB]], 550 551 // ub = number of elements 552 // OMP5: [[NUM:%.+]] = load i64, i64* [[CAP3]], 553 // OMP5: store i64 [[NUM]], i64* [[UB]], 554 555 // stride = 1; 556 // OMP5: store i64 1, i64* [[STRIDE]], 557 558 // is_last = 0; 559 // OMP5: store i32 0, i32* [[IS_LAST]], 560 561 // loop. 562 // OMP5: call void @__kmpc_for_static_init_8(%struct.ident_t* {{.+}}, i32 [[GTID:%.+]], i32 34, i32* [[IS_LAST]], i64* [[LB]], i64* [[UB]], i64* [[STRIDE]], i64 1, i64 1) 563 564 // ub = (ub > number_of_elems ? number_of_elems : ub); 565 // OMP5: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 566 // OMP5: [[NUM_VAL:%.+]] = load i64, i64* [[CAP3]], 567 // OMP5: [[CMP:%.+]] = icmp sgt i64 [[UB_VAL]], [[NUM_VAL]] 568 // OMP5: br i1 [[CMP]], label %[[TRUE:.+]], label %[[FALSE:.+]] 569 570 // OMP5: [[TRUE]]: 571 // OMP5: [[NUM_VAL:%.+]] = load i64, i64* [[CAP3]], 572 // OMP5: br label %[[END:.+]] 573 574 // OMP5: [[FALSE]]: 575 // OMP5: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 576 // OMP5: br label %[[END:.+]] 577 578 // OMP5: [[END]]: 579 // OMP5: [[MIN:%.+]] = phi i64 [ [[NUM_VAL]], %[[TRUE]] ], [ [[UB_VAL]], %[[FALSE]] ] 580 // OMP%: store i64 [[MIN]], i64* [[UB]], 581 582 // iv = lb; 583 // OMP5: [[LB_VAL:%.+]] = load i64, i64* [[LB]], 584 // OMP5: store i64 [[LB_VAL]], i64* [[IV]], 585 586 // goto loop; 587 // loop: 588 // OMP5: br label %[[LOOP:.+]] 589 590 // OMP5: [[LOOP]]: 591 592 // iv <= ub ? goto body : goto end; 593 // OMP5: [[IV_VAL:%.+]] = load i64, i64* [[IV]], 594 // OMP5: [[UB_VAL:%.+]] = load i64, i64* [[UB]], 595 // OMP5: [[CMP:%.+]] = icmp sle i64 [[IV_VAL]], [[UB_VAL]] 596 // OMP5: br i1 [[CMP]], label %[[BODY:.+]], label %[[END:.+]] 597 598 // body: 599 // __begin = begin(arr) + iv * 1; 600 // OMP5: [[BODY]]: 601 // OMP5: [[CAP1_VAL:%.+]] = load i32*, i32** [[CAP1]], 602 // OMP5: [[IV_VAL:%.+]] = load i64, i64* [[IV]], 603 // OMP5: [[MUL:%.+]] = mul nsw i64 [[IV_VAL]], 1 604 // OMP5: [[ADDR:%.+]] = getelementptr inbounds i32, i32* [[CAP1_VAL]], i64 [[MUL]] 605 // OMP5: store i32* [[ADDR]], i32** [[BEGIN]], 606 607 // a = *__begin; 608 // OMP5: [[BEGIN_VAL:%.+]] = load i32*, i32** [[BEGIN]], 609 // OMP5: store i32* [[BEGIN_VAL]], i32** [[A_PTR]], 610 611 // (void)a; 612 // OMP5: load i32*, i32** [[A_PTR]], 613 614 // iv += 1; 615 // OMP5: [[IV_VAL:%.+]] = load i64, i64* [[IV]], 616 // OMP5: [[IV_VAL_ADD_1:%.+]] = add nsw i64 [[IV_VAL]], 1 617 // OMP5: store i64 [[IV_VAL_ADD_1]], i64* [[IV]], 618 619 // goto loop; 620 // OMP5: br label %[[LOOP]] 621 622 // end: 623 // OMP5: [[END]]: 624 // OMP5: call void @__kmpc_for_static_fini(%struct.ident_t* {{.+}}, i32 [[GTID:%.+]]) 625 // exit: 626 // OMP5: [[EXIT]]: 627 // OMP5: ret void 628 629 // OMP5-LABEL: range_for_collapsed 630 void range_for_collapsed() { 631 int arr[10] = {0}; 632 // OMP5: call void @__kmpc_for_static_init_8(%struct.ident_t* {{.+}}, i32 [[GTID:%.+]], i32 34, i32* %{{.+}}, i64* %{{.+}}, i64* %{{.+}}, i64* %{{.+}}, i64 1, i64 1) 633 #pragma omp parallel for collapse(2) 634 for (auto &a : arr) 635 for (auto b : arr) 636 a = b; 637 // OMP5: call void @__kmpc_for_static_fini(%struct.ident_t* {{.+}}, i32 [[GTID:%.+]]) 638 } 639 #endif // OMP5 640 641 #endif // HEADER 642 643