1 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _
2 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1
3 // RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s
4 // RUN: %clang_cc1 -fopenmp -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK2
5 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK3
6 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4
7 // RUN: %clang_cc1 -verify -fopenmp -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK5
8 
9 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK6
10 // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s
11 // RUN: %clang_cc1 -fopenmp-simd -fnoopenmp-use-tls -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK7
12 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK8
13 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK9
14 // RUN: %clang_cc1 -verify -fopenmp-simd -fnoopenmp-use-tls -x c++ -std=c++11 -DARRAY -triple x86_64-apple-darwin10 -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK10
15 
16 // RUN: %clang_cc1 -verify -fopenmp -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK11
17 // RUN: %clang_cc1 -fopenmp -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s
18 // RUN: %clang_cc1 -fopenmp -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK12
19 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK13
20 // RUN: %clang_cc1 -verify -fopenmp -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK14
21 // RUN: %clang_cc1 -verify -fopenmp -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK15
22 // RUN: %clang_cc1 -verify -fopenmp -x c++ -DNESTED -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK16
23 
24 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK17
25 // RUN: %clang_cc1 -fopenmp-simd -x c++ -std=c++11 -triple x86_64-linux -emit-pch -o %t %s
26 // RUN: %clang_cc1 -fopenmp-simd -x c++ -triple x86_64-linux -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK18
27 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DLAMBDA -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK19
28 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -fblocks -DBLOCKS -triple x86_64-linux -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK20
29 // RUN: %clang_cc1 -verify -fopenmp-simd -x c++ -std=c++11 -DARRAY -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK21
30 // expected-no-diagnostics
31 #if !defined(ARRAY) && !defined(NESTED)
32 #ifndef HEADER
33 #define HEADER
34 
35 volatile int g __attribute__((aligned(128))) = 1212;
36 #pragma omp threadprivate(g)
37 
38 template <class T>
39 struct S {
40   T f;
41   S(T a) : f(a + g) {}
42   S() : f(g) {}
43   S &operator=(const S &) { return *this; };
44   operator T() { return T(); }
45   ~S() {}
46 };
47 
48 
49 
50 template <typename T>
51 T tmain() {
52   S<T> test;
53   test = S<T>();
54   static T t_var __attribute__((aligned(128))) = 333;
55   static T vec[] __attribute__((aligned(128))) = {3, 3};
56   static S<T> s_arr[] __attribute__((aligned(128))) = {1, 2};
57   static S<T> var __attribute__((aligned(128))) (3);
58 #pragma omp threadprivate(t_var, vec, s_arr, var)
59 #pragma omp parallel copyin(t_var, vec, s_arr, var)
60   {
61     vec[0] = t_var;
62     s_arr[0] = var;
63   }
64 #pragma omp parallel copyin(t_var)
65   {}
66   return T();
67 }
68 
69 int main() {
70 #ifdef LAMBDA
71   [&]() {
72 
73 
74 #pragma omp parallel copyin(g)
75   {
76 
77     // threadprivate_g = g;
78 
79 
80     g = 1;
81 
82     [&]() {
83       g = 2;
84 
85     }();
86   }
87   }();
88   return 0;
89 #elif defined(BLOCKS)
90 
91   ^{
92 
93 
94 #pragma omp parallel copyin(g)
95   {
96 
97     // threadprivate_g = g;
98 
99 
100     g = 1;
101 
102 
103     ^{
104       g = 2;
105 
106     }();
107   }
108   }();
109   return 0;
110 #else
111   S<float> test;
112   test = S<float>();
113   static int t_var = 1122;
114   static int vec[] = {1, 2};
115   static S<float> s_arr[] = {1, 2};
116   static S<float> var(3);
117 #pragma omp threadprivate(t_var, vec, s_arr, var)
118 #pragma omp parallel copyin(t_var, vec, s_arr, var)
119   {
120     vec[0] = t_var;
121     s_arr[0] = var;
122   }
123 #pragma omp parallel copyin(t_var) default(none)
124   ++t_var;
125   return tmain<int>();
126 #endif
127 }
128 
129 
130 
131 
132 
133 // threadprivate_t_var = t_var;
134 
135 
136 
137 // threadprivate_vec = vec;
138 
139 
140 // threadprivate_s_arr = s_arr;
141 
142 
143 // threadprivate_var = var;
144 
145 
146 
147 
148 
149 
150 // threadprivate_t_var = t_var;
151 
152 
153 
154 
155 
156 
157 
158 // threadprivate_t_var = t_var;
159 
160 
161 
162 // threadprivate_vec = vec;
163 
164 
165 // threadprivate_s_arr = s_arr;
166 
167 
168 // threadprivate_var = var;
169 
170 
171 
172 
173 
174 
175 // threadprivate_t_var = t_var;
176 
177 
178 
179 
180 
181 #endif
182 #elif defined(ARRAY)
183 
184 struct St {
185   int a, b;
186   St() : a(0), b(0) {}
187   St &operator=(const St &) { return *this; };
188   ~St() {}
189 };
190 
191 void array_func() {
192   static int a[2];
193   static St s[2];
194 
195 
196 #pragma omp threadprivate(a, s)
197 #pragma omp parallel copyin(a, s)
198   ;
199 }
200 #elif defined(NESTED)
201 int t_init();
202 int t = t_init();
203 #pragma omp threadprivate(t)
204 void foo() {
205 #pragma omp parallel
206 #pragma omp parallel copyin(t)
207   ++t;
208 }
209 
210 #endif // NESTED
211 
212 // CHECK1-LABEL: define {{[^@]+}}@main
213 // CHECK1-SAME: () #[[ATTR0:[0-9]+]] {
214 // CHECK1-NEXT:  entry:
215 // CHECK1-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
216 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
217 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
218 // CHECK1-NEXT:    store i32 0, i32* [[RETVAL]], align 4
219 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
220 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
221 // CHECK1-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
222 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
223 // CHECK1-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8
224 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
225 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
226 // CHECK1:       init.check:
227 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
228 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
229 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
230 // CHECK1:       init:
231 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
232 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.)
233 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00)
234 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00)
235 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]]
236 // CHECK1-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
237 // CHECK1-NEXT:    br label [[INIT_END]]
238 // CHECK1:       init.end:
239 // CHECK1-NEXT:    [[TMP4:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8
240 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0
241 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
242 // CHECK1:       init.check2:
243 // CHECK1-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
244 // CHECK1-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0
245 // CHECK1-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
246 // CHECK1:       init4:
247 // CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
248 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* (i8*)* @.__kmpc_global_ctor_..1, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..2)
249 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00)
250 // CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
251 // CHECK1-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
252 // CHECK1-NEXT:    br label [[INIT_END5]]
253 // CHECK1:       init.end5:
254 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
255 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
256 // CHECK1-NEXT:    [[CALL6:%.*]] = call i32 @_Z5tmainIiET_v()
257 // CHECK1-NEXT:    store i32 [[CALL6]], i32* [[RETVAL]], align 4
258 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
259 // CHECK1-NEXT:    [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4
260 // CHECK1-NEXT:    ret i32 [[TMP8]]
261 //
262 //
263 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
264 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
265 // CHECK1-NEXT:  entry:
266 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
267 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
268 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
269 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
270 // CHECK1-NEXT:    ret void
271 //
272 //
273 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
274 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
275 // CHECK1-NEXT:  entry:
276 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
277 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S*, align 8
278 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
279 // CHECK1-NEXT:    store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
280 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
281 // CHECK1-NEXT:    ret %struct.S* [[THIS1]]
282 //
283 //
284 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
285 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
286 // CHECK1-NEXT:  entry:
287 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
288 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
289 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
290 // CHECK1-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
291 // CHECK1-NEXT:    ret void
292 //
293 //
294 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
295 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" {
296 // CHECK1-NEXT:  entry:
297 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
298 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
299 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
300 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %struct.S]*
301 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 0
302 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00)
303 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
304 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
305 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8
306 // CHECK1-NEXT:    ret i8* [[TMP3]]
307 //
308 //
309 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
310 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
311 // CHECK1-NEXT:  entry:
312 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
313 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
314 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
315 // CHECK1-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
316 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
317 // CHECK1-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
318 // CHECK1-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
319 // CHECK1-NEXT:    ret void
320 //
321 //
322 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
323 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
324 // CHECK1-NEXT:  entry:
325 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
326 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
327 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
328 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = bitcast i8* [[TMP1]] to %struct.S*
329 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
330 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
331 // CHECK1:       arraydestroy.body:
332 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
333 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
334 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
335 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
336 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
337 // CHECK1:       arraydestroy.done1:
338 // CHECK1-NEXT:    ret void
339 //
340 //
341 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
342 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
343 // CHECK1-NEXT:  entry:
344 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
345 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
346 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
347 // CHECK1:       arraydestroy.body:
348 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
349 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
350 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
351 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0)
352 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
353 // CHECK1:       arraydestroy.done1:
354 // CHECK1-NEXT:    ret void
355 //
356 //
357 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1
358 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
359 // CHECK1-NEXT:  entry:
360 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
361 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
362 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
363 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S*
364 // CHECK1-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], float 3.000000e+00)
365 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8
366 // CHECK1-NEXT:    ret i8* [[TMP3]]
367 //
368 //
369 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2
370 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
371 // CHECK1-NEXT:  entry:
372 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
373 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
374 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
375 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S*
376 // CHECK1-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]]
377 // CHECK1-NEXT:    ret void
378 //
379 //
380 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined.
381 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
382 // CHECK1-NEXT:  entry:
383 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
384 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
385 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
386 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
387 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
388 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
389 // CHECK1-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ4mainE5t_var to i8*), i64 4, i8*** @_ZZ4mainE5t_var.cache.)
390 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
391 // CHECK1-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
392 // CHECK1-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @_ZZ4mainE5t_var to i64), [[TMP4]]
393 // CHECK1-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
394 // CHECK1:       copyin.not.master:
395 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
396 // CHECK1-NEXT:    store i32 [[TMP6]], i32* [[TMP3]], align 4
397 // CHECK1-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i64 8, i8*** @_ZZ4mainE3vec.cache.)
398 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to [2 x i32]*
399 // CHECK1-NEXT:    [[TMP9:%.*]] = bitcast [2 x i32]* [[TMP8]] to i8*
400 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i64 8, i1 false)
401 // CHECK1-NEXT:    [[TMP10:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i64 8, i8*** @_ZZ4mainE5s_arr.cache.)
402 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8* [[TMP10]] to [2 x %struct.S]*
403 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP11]], i32 0, i32 0
404 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
405 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP12]]
406 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
407 // CHECK1:       omp.arraycpy.body:
408 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
409 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
410 // CHECK1-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
411 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
412 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
413 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]]
414 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
415 // CHECK1:       omp.arraycpy.done1:
416 // CHECK1-NEXT:    [[TMP13:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i64 4, i8*** @_ZZ4mainE3var.cache.)
417 // CHECK1-NEXT:    [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S*
418 // CHECK1-NEXT:    [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP14]], %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)
419 // CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
420 // CHECK1:       copyin.not.master.end:
421 // CHECK1-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]])
422 // CHECK1-NEXT:    [[TMP15:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ4mainE5t_var to i8*), i64 4, i8*** @_ZZ4mainE5t_var.cache.)
423 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8* [[TMP15]] to i32*
424 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
425 // CHECK1-NEXT:    [[TMP18:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i64 8, i8*** @_ZZ4mainE3vec.cache.)
426 // CHECK1-NEXT:    [[TMP19:%.*]] = bitcast i8* [[TMP18]] to [2 x i32]*
427 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP19]], i64 0, i64 0
428 // CHECK1-NEXT:    store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
429 // CHECK1-NEXT:    [[TMP20:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i64 4, i8*** @_ZZ4mainE3var.cache.)
430 // CHECK1-NEXT:    [[TMP21:%.*]] = bitcast i8* [[TMP20]] to %struct.S*
431 // CHECK1-NEXT:    [[TMP22:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i64 8, i8*** @_ZZ4mainE5s_arr.cache.)
432 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8* [[TMP22]] to [2 x %struct.S]*
433 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP23]], i64 0, i64 0
434 // CHECK1-NEXT:    [[CALL4:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP21]])
435 // CHECK1-NEXT:    ret void
436 //
437 //
438 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3
439 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
440 // CHECK1-NEXT:  entry:
441 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
442 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
443 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
444 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
445 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
446 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
447 // CHECK1-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ4mainE5t_var to i8*), i64 4, i8*** @_ZZ4mainE5t_var.cache.)
448 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
449 // CHECK1-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
450 // CHECK1-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @_ZZ4mainE5t_var to i64), [[TMP4]]
451 // CHECK1-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
452 // CHECK1:       copyin.not.master:
453 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
454 // CHECK1-NEXT:    store i32 [[TMP6]], i32* [[TMP3]], align 4
455 // CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
456 // CHECK1:       copyin.not.master.end:
457 // CHECK1-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]])
458 // CHECK1-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ4mainE5t_var to i8*), i64 4, i8*** @_ZZ4mainE5t_var.cache.)
459 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
460 // CHECK1-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
461 // CHECK1-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
462 // CHECK1-NEXT:    store i32 [[INC]], i32* [[TMP8]], align 4
463 // CHECK1-NEXT:    ret void
464 //
465 //
466 // CHECK1-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
467 // CHECK1-SAME: () #[[ATTR2]] comdat {
468 // CHECK1-NEXT:  entry:
469 // CHECK1-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
470 // CHECK1-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
471 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
472 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
473 // CHECK1-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
474 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]]
475 // CHECK1-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8
476 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
477 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]]
478 // CHECK1:       init.check:
479 // CHECK1-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
480 // CHECK1-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
481 // CHECK1-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
482 // CHECK1:       init:
483 // CHECK1-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
484 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i8* (i8*)* @.__kmpc_global_ctor_..4, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..5)
485 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1)
486 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2)
487 // CHECK1-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.6, i8* null, i8* @__dso_handle) #[[ATTR3]]
488 // CHECK1-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
489 // CHECK1-NEXT:    br label [[INIT_END]]
490 // CHECK1:       init.end:
491 // CHECK1-NEXT:    [[TMP4:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8
492 // CHECK1-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0
493 // CHECK1-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
494 // CHECK1:       init.check2:
495 // CHECK1-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
496 // CHECK1-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0
497 // CHECK1-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
498 // CHECK1:       init4:
499 // CHECK1-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
500 // CHECK1-NEXT:    call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* (i8*)* @.__kmpc_global_ctor_..7, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..8)
501 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3)
502 // CHECK1-NEXT:    [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
503 // CHECK1-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
504 // CHECK1-NEXT:    br label [[INIT_END5]]
505 // CHECK1:       init.end5:
506 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*))
507 // CHECK1-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
508 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
509 // CHECK1-NEXT:    ret i32 0
510 //
511 //
512 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
513 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
514 // CHECK1-NEXT:  entry:
515 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
516 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
517 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
518 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
519 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
520 // CHECK1-NEXT:    [[TMP1:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
521 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
522 // CHECK1-NEXT:    [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 128
523 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP3]] to float
524 // CHECK1-NEXT:    store float [[CONV]], float* [[F]], align 4
525 // CHECK1-NEXT:    ret void
526 //
527 //
528 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
529 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
530 // CHECK1-NEXT:  entry:
531 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
532 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
533 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
534 // CHECK1-NEXT:    ret void
535 //
536 //
537 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
538 // CHECK1-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
539 // CHECK1-NEXT:  entry:
540 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
541 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
542 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
543 // CHECK1-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
544 // CHECK1-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
545 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
546 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
547 // CHECK1-NEXT:    [[TMP1:%.*]] = load float, float* [[A_ADDR]], align 4
548 // CHECK1-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
549 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
550 // CHECK1-NEXT:    [[TMP4:%.*]] = load volatile i32, i32* [[TMP3]], align 128
551 // CHECK1-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to float
552 // CHECK1-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
553 // CHECK1-NEXT:    store float [[ADD]], float* [[F]], align 4
554 // CHECK1-NEXT:    ret void
555 //
556 //
557 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
558 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
559 // CHECK1-NEXT:  entry:
560 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
561 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
562 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
563 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
564 // CHECK1-NEXT:    ret void
565 //
566 //
567 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
568 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
569 // CHECK1-NEXT:  entry:
570 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
571 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8
572 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
573 // CHECK1-NEXT:    store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8
574 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
575 // CHECK1-NEXT:    ret %struct.S.0* [[THIS1]]
576 //
577 //
578 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
579 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
580 // CHECK1-NEXT:  entry:
581 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
582 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
583 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
584 // CHECK1-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
585 // CHECK1-NEXT:    ret void
586 //
587 //
588 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..4
589 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
590 // CHECK1-NEXT:  entry:
591 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
592 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
593 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
594 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %struct.S.0]*
595 // CHECK1-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i64 0, i64 0
596 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
597 // CHECK1-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
598 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
599 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8
600 // CHECK1-NEXT:    ret i8* [[TMP3]]
601 //
602 //
603 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
604 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
605 // CHECK1-NEXT:  entry:
606 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
607 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
608 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
609 // CHECK1-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
610 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
611 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
612 // CHECK1-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
613 // CHECK1-NEXT:    ret void
614 //
615 //
616 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..5
617 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
618 // CHECK1-NEXT:  entry:
619 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
620 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
621 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
622 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0*
623 // CHECK1-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
624 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
625 // CHECK1:       arraydestroy.body:
626 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
627 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
628 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
629 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
630 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
631 // CHECK1:       arraydestroy.done1:
632 // CHECK1-NEXT:    ret void
633 //
634 //
635 // CHECK1-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.6
636 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
637 // CHECK1-NEXT:  entry:
638 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
639 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
640 // CHECK1-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
641 // CHECK1:       arraydestroy.body:
642 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
643 // CHECK1-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
644 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
645 // CHECK1-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0)
646 // CHECK1-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
647 // CHECK1:       arraydestroy.done1:
648 // CHECK1-NEXT:    ret void
649 //
650 //
651 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..7
652 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
653 // CHECK1-NEXT:  entry:
654 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
655 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
656 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
657 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0*
658 // CHECK1-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]], i32 3)
659 // CHECK1-NEXT:    [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8
660 // CHECK1-NEXT:    ret i8* [[TMP3]]
661 //
662 //
663 // CHECK1-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..8
664 // CHECK1-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
665 // CHECK1-NEXT:  entry:
666 // CHECK1-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
667 // CHECK1-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
668 // CHECK1-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
669 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0*
670 // CHECK1-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]]
671 // CHECK1-NEXT:    ret void
672 //
673 //
674 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..9
675 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
676 // CHECK1-NEXT:  entry:
677 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
678 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
679 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
680 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
681 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
682 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
683 // CHECK1-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ5tmainIiET_vE5t_var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE5t_var.cache.)
684 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
685 // CHECK1-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
686 // CHECK1-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64), [[TMP4]]
687 // CHECK1-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
688 // CHECK1:       copyin.not.master:
689 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
690 // CHECK1-NEXT:    store i32 [[TMP6]], i32* [[TMP3]], align 128
691 // CHECK1-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE3vec.cache.)
692 // CHECK1-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to [2 x i32]*
693 // CHECK1-NEXT:    [[TMP9:%.*]] = bitcast [2 x i32]* [[TMP8]] to i8*
694 // CHECK1-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i64 8, i1 false)
695 // CHECK1-NEXT:    [[TMP10:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE5s_arr.cache.)
696 // CHECK1-NEXT:    [[TMP11:%.*]] = bitcast i8* [[TMP10]] to [2 x %struct.S.0]*
697 // CHECK1-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP11]], i32 0, i32 0
698 // CHECK1-NEXT:    [[TMP12:%.*]] = getelementptr [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
699 // CHECK1-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP12]]
700 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
701 // CHECK1:       omp.arraycpy.body:
702 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
703 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
704 // CHECK1-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
705 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
706 // CHECK1-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
707 // CHECK1-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]]
708 // CHECK1-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
709 // CHECK1:       omp.arraycpy.done1:
710 // CHECK1-NEXT:    [[TMP13:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE3var.cache.)
711 // CHECK1-NEXT:    [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S.0*
712 // CHECK1-NEXT:    [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]], %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)
713 // CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
714 // CHECK1:       copyin.not.master.end:
715 // CHECK1-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]])
716 // CHECK1-NEXT:    [[TMP15:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ5tmainIiET_vE5t_var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE5t_var.cache.)
717 // CHECK1-NEXT:    [[TMP16:%.*]] = bitcast i8* [[TMP15]] to i32*
718 // CHECK1-NEXT:    [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 128
719 // CHECK1-NEXT:    [[TMP18:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE3vec.cache.)
720 // CHECK1-NEXT:    [[TMP19:%.*]] = bitcast i8* [[TMP18]] to [2 x i32]*
721 // CHECK1-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP19]], i64 0, i64 0
722 // CHECK1-NEXT:    store i32 [[TMP17]], i32* [[ARRAYIDX]], align 128
723 // CHECK1-NEXT:    [[TMP20:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE3var.cache.)
724 // CHECK1-NEXT:    [[TMP21:%.*]] = bitcast i8* [[TMP20]] to %struct.S.0*
725 // CHECK1-NEXT:    [[TMP22:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE5s_arr.cache.)
726 // CHECK1-NEXT:    [[TMP23:%.*]] = bitcast i8* [[TMP22]] to [2 x %struct.S.0]*
727 // CHECK1-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP23]], i64 0, i64 0
728 // CHECK1-NEXT:    [[CALL4:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP21]])
729 // CHECK1-NEXT:    ret void
730 //
731 //
732 // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..10
733 // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
734 // CHECK1-NEXT:  entry:
735 // CHECK1-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
736 // CHECK1-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
737 // CHECK1-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
738 // CHECK1-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
739 // CHECK1-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
740 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
741 // CHECK1-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ5tmainIiET_vE5t_var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE5t_var.cache.)
742 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
743 // CHECK1-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
744 // CHECK1-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64), [[TMP4]]
745 // CHECK1-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
746 // CHECK1:       copyin.not.master:
747 // CHECK1-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
748 // CHECK1-NEXT:    store i32 [[TMP6]], i32* [[TMP3]], align 128
749 // CHECK1-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
750 // CHECK1:       copyin.not.master.end:
751 // CHECK1-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]])
752 // CHECK1-NEXT:    ret void
753 //
754 //
755 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
756 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
757 // CHECK1-NEXT:  entry:
758 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
759 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
760 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
761 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
762 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
763 // CHECK1-NEXT:    [[TMP1:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
764 // CHECK1-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
765 // CHECK1-NEXT:    [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 128
766 // CHECK1-NEXT:    store i32 [[TMP3]], i32* [[F]], align 4
767 // CHECK1-NEXT:    ret void
768 //
769 //
770 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
771 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
772 // CHECK1-NEXT:  entry:
773 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
774 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
775 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
776 // CHECK1-NEXT:    ret void
777 //
778 //
779 // CHECK1-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
780 // CHECK1-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
781 // CHECK1-NEXT:  entry:
782 // CHECK1-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
783 // CHECK1-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
784 // CHECK1-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
785 // CHECK1-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
786 // CHECK1-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
787 // CHECK1-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
788 // CHECK1-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
789 // CHECK1-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
790 // CHECK1-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
791 // CHECK1-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
792 // CHECK1-NEXT:    [[TMP4:%.*]] = load volatile i32, i32* [[TMP3]], align 128
793 // CHECK1-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP4]]
794 // CHECK1-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
795 // CHECK1-NEXT:    ret void
796 //
797 //
798 // CHECK2-LABEL: define {{[^@]+}}@main
799 // CHECK2-SAME: () #[[ATTR0:[0-9]+]] {
800 // CHECK2-NEXT:  entry:
801 // CHECK2-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
802 // CHECK2-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
803 // CHECK2-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
804 // CHECK2-NEXT:    store i32 0, i32* [[RETVAL]], align 4
805 // CHECK2-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
806 // CHECK2-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
807 // CHECK2-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
808 // CHECK2-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
809 // CHECK2-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8
810 // CHECK2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
811 // CHECK2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
812 // CHECK2:       init.check:
813 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
814 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
815 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
816 // CHECK2:       init:
817 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
818 // CHECK2-NEXT:    call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.)
819 // CHECK2-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00)
820 // CHECK2-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00)
821 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]]
822 // CHECK2-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
823 // CHECK2-NEXT:    br label [[INIT_END]]
824 // CHECK2:       init.end:
825 // CHECK2-NEXT:    [[TMP4:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8
826 // CHECK2-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0
827 // CHECK2-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
828 // CHECK2:       init.check2:
829 // CHECK2-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
830 // CHECK2-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0
831 // CHECK2-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
832 // CHECK2:       init4:
833 // CHECK2-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
834 // CHECK2-NEXT:    call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* (i8*)* @.__kmpc_global_ctor_..1, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..2)
835 // CHECK2-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00)
836 // CHECK2-NEXT:    [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
837 // CHECK2-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
838 // CHECK2-NEXT:    br label [[INIT_END5]]
839 // CHECK2:       init.end5:
840 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
841 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*))
842 // CHECK2-NEXT:    [[CALL6:%.*]] = call i32 @_Z5tmainIiET_v()
843 // CHECK2-NEXT:    store i32 [[CALL6]], i32* [[RETVAL]], align 4
844 // CHECK2-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
845 // CHECK2-NEXT:    [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4
846 // CHECK2-NEXT:    ret i32 [[TMP8]]
847 //
848 //
849 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
850 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
851 // CHECK2-NEXT:  entry:
852 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
853 // CHECK2-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
854 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
855 // CHECK2-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
856 // CHECK2-NEXT:    ret void
857 //
858 //
859 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
860 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
861 // CHECK2-NEXT:  entry:
862 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
863 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S*, align 8
864 // CHECK2-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
865 // CHECK2-NEXT:    store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
866 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
867 // CHECK2-NEXT:    ret %struct.S* [[THIS1]]
868 //
869 //
870 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
871 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
872 // CHECK2-NEXT:  entry:
873 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
874 // CHECK2-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
875 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
876 // CHECK2-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
877 // CHECK2-NEXT:    ret void
878 //
879 //
880 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
881 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" {
882 // CHECK2-NEXT:  entry:
883 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
884 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
885 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
886 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %struct.S]*
887 // CHECK2-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP2]], i64 0, i64 0
888 // CHECK2-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], float 1.000000e+00)
889 // CHECK2-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAYINIT_BEGIN]], i64 1
890 // CHECK2-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], float 2.000000e+00)
891 // CHECK2-NEXT:    [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8
892 // CHECK2-NEXT:    ret i8* [[TMP3]]
893 //
894 //
895 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
896 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
897 // CHECK2-NEXT:  entry:
898 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
899 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
900 // CHECK2-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
901 // CHECK2-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
902 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
903 // CHECK2-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
904 // CHECK2-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
905 // CHECK2-NEXT:    ret void
906 //
907 //
908 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
909 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
910 // CHECK2-NEXT:  entry:
911 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
912 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
913 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
914 // CHECK2-NEXT:    [[ARRAY_BEGIN:%.*]] = bitcast i8* [[TMP1]] to %struct.S*
915 // CHECK2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
916 // CHECK2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
917 // CHECK2:       arraydestroy.body:
918 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
919 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
920 // CHECK2-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
921 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
922 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
923 // CHECK2:       arraydestroy.done1:
924 // CHECK2-NEXT:    ret void
925 //
926 //
927 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
928 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
929 // CHECK2-NEXT:  entry:
930 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
931 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
932 // CHECK2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
933 // CHECK2:       arraydestroy.body:
934 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
935 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
936 // CHECK2-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
937 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0)
938 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
939 // CHECK2:       arraydestroy.done1:
940 // CHECK2-NEXT:    ret void
941 //
942 //
943 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..1
944 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
945 // CHECK2-NEXT:  entry:
946 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
947 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
948 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
949 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S*
950 // CHECK2-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]], float 3.000000e+00)
951 // CHECK2-NEXT:    [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8
952 // CHECK2-NEXT:    ret i8* [[TMP3]]
953 //
954 //
955 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..2
956 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
957 // CHECK2-NEXT:  entry:
958 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
959 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
960 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
961 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S*
962 // CHECK2-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]]
963 // CHECK2-NEXT:    ret void
964 //
965 //
966 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined.
967 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5:[0-9]+]] {
968 // CHECK2-NEXT:  entry:
969 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
970 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
971 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
972 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
973 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
974 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
975 // CHECK2-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ4mainE5t_var to i8*), i64 4, i8*** @_ZZ4mainE5t_var.cache.)
976 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
977 // CHECK2-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
978 // CHECK2-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @_ZZ4mainE5t_var to i64), [[TMP4]]
979 // CHECK2-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
980 // CHECK2:       copyin.not.master:
981 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
982 // CHECK2-NEXT:    store i32 [[TMP6]], i32* [[TMP3]], align 4
983 // CHECK2-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i64 8, i8*** @_ZZ4mainE3vec.cache.)
984 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to [2 x i32]*
985 // CHECK2-NEXT:    [[TMP9:%.*]] = bitcast [2 x i32]* [[TMP8]] to i8*
986 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP9]], i8* align 4 bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i64 8, i1 false)
987 // CHECK2-NEXT:    [[TMP10:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i64 8, i8*** @_ZZ4mainE5s_arr.cache.)
988 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8* [[TMP10]] to [2 x %struct.S]*
989 // CHECK2-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP11]], i32 0, i32 0
990 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr [[STRUCT_S:%.*]], %struct.S* [[ARRAY_BEGIN]], i64 2
991 // CHECK2-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S* [[ARRAY_BEGIN]], [[TMP12]]
992 // CHECK2-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
993 // CHECK2:       omp.arraycpy.body:
994 // CHECK2-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
995 // CHECK2-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
996 // CHECK2-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
997 // CHECK2-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
998 // CHECK2-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
999 // CHECK2-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]]
1000 // CHECK2-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
1001 // CHECK2:       omp.arraycpy.done1:
1002 // CHECK2-NEXT:    [[TMP13:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i64 4, i8*** @_ZZ4mainE3var.cache.)
1003 // CHECK2-NEXT:    [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S*
1004 // CHECK2-NEXT:    [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TMP14]], %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)
1005 // CHECK2-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1006 // CHECK2:       copyin.not.master.end:
1007 // CHECK2-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]])
1008 // CHECK2-NEXT:    [[TMP15:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ4mainE5t_var to i8*), i64 4, i8*** @_ZZ4mainE5t_var.cache.)
1009 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8* [[TMP15]] to i32*
1010 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 4
1011 // CHECK2-NEXT:    [[TMP18:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i64 8, i8*** @_ZZ4mainE3vec.cache.)
1012 // CHECK2-NEXT:    [[TMP19:%.*]] = bitcast i8* [[TMP18]] to [2 x i32]*
1013 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP19]], i64 0, i64 0
1014 // CHECK2-NEXT:    store i32 [[TMP17]], i32* [[ARRAYIDX]], align 4
1015 // CHECK2-NEXT:    [[TMP20:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i64 4, i8*** @_ZZ4mainE3var.cache.)
1016 // CHECK2-NEXT:    [[TMP21:%.*]] = bitcast i8* [[TMP20]] to %struct.S*
1017 // CHECK2-NEXT:    [[TMP22:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S]* @_ZZ4mainE5s_arr to i8*), i64 8, i8*** @_ZZ4mainE5s_arr.cache.)
1018 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8* [[TMP22]] to [2 x %struct.S]*
1019 // CHECK2-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S], [2 x %struct.S]* [[TMP23]], i64 0, i64 0
1020 // CHECK2-NEXT:    [[CALL4:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP21]])
1021 // CHECK2-NEXT:    ret void
1022 //
1023 //
1024 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3
1025 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
1026 // CHECK2-NEXT:  entry:
1027 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1028 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1029 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1030 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1031 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1032 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1033 // CHECK2-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ4mainE5t_var to i8*), i64 4, i8*** @_ZZ4mainE5t_var.cache.)
1034 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
1035 // CHECK2-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
1036 // CHECK2-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @_ZZ4mainE5t_var to i64), [[TMP4]]
1037 // CHECK2-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1038 // CHECK2:       copyin.not.master:
1039 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
1040 // CHECK2-NEXT:    store i32 [[TMP6]], i32* [[TMP3]], align 4
1041 // CHECK2-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1042 // CHECK2:       copyin.not.master.end:
1043 // CHECK2-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]])
1044 // CHECK2-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ4mainE5t_var to i8*), i64 4, i8*** @_ZZ4mainE5t_var.cache.)
1045 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1046 // CHECK2-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
1047 // CHECK2-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
1048 // CHECK2-NEXT:    store i32 [[INC]], i32* [[TMP8]], align 4
1049 // CHECK2-NEXT:    ret void
1050 //
1051 //
1052 // CHECK2-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1053 // CHECK2-SAME: () #[[ATTR2]] comdat {
1054 // CHECK2-NEXT:  entry:
1055 // CHECK2-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1056 // CHECK2-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
1057 // CHECK2-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1058 // CHECK2-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
1059 // CHECK2-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
1060 // CHECK2-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]]
1061 // CHECK2-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8
1062 // CHECK2-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1063 // CHECK2-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]]
1064 // CHECK2:       init.check:
1065 // CHECK2-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
1066 // CHECK2-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1067 // CHECK2-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
1068 // CHECK2:       init:
1069 // CHECK2-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1070 // CHECK2-NEXT:    call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i8* (i8*)* @.__kmpc_global_ctor_..4, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..5)
1071 // CHECK2-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1)
1072 // CHECK2-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2)
1073 // CHECK2-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.6, i8* null, i8* @__dso_handle) #[[ATTR3]]
1074 // CHECK2-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
1075 // CHECK2-NEXT:    br label [[INIT_END]]
1076 // CHECK2:       init.end:
1077 // CHECK2-NEXT:    [[TMP4:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8
1078 // CHECK2-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP4]], 0
1079 // CHECK2-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
1080 // CHECK2:       init.check2:
1081 // CHECK2-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
1082 // CHECK2-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP5]], 0
1083 // CHECK2-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
1084 // CHECK2:       init4:
1085 // CHECK2-NEXT:    [[TMP6:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1086 // CHECK2-NEXT:    call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* (i8*)* @.__kmpc_global_ctor_..7, i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_..8)
1087 // CHECK2-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3)
1088 // CHECK2-NEXT:    [[TMP7:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
1089 // CHECK2-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
1090 // CHECK2-NEXT:    br label [[INIT_END5]]
1091 // CHECK2:       init.end5:
1092 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..9 to void (i32*, i32*, ...)*))
1093 // CHECK2-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined..10 to void (i32*, i32*, ...)*))
1094 // CHECK2-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
1095 // CHECK2-NEXT:    ret i32 0
1096 //
1097 //
1098 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1099 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1100 // CHECK2-NEXT:  entry:
1101 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1102 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1103 // CHECK2-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1104 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1105 // CHECK2-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1106 // CHECK2-NEXT:    [[TMP1:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
1107 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
1108 // CHECK2-NEXT:    [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 128
1109 // CHECK2-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP3]] to float
1110 // CHECK2-NEXT:    store float [[CONV]], float* [[F]], align 4
1111 // CHECK2-NEXT:    ret void
1112 //
1113 //
1114 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1115 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1116 // CHECK2-NEXT:  entry:
1117 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1118 // CHECK2-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1119 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1120 // CHECK2-NEXT:    ret void
1121 //
1122 //
1123 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1124 // CHECK2-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1125 // CHECK2-NEXT:  entry:
1126 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1127 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1128 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1129 // CHECK2-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1130 // CHECK2-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
1131 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1132 // CHECK2-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1133 // CHECK2-NEXT:    [[TMP1:%.*]] = load float, float* [[A_ADDR]], align 4
1134 // CHECK2-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
1135 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
1136 // CHECK2-NEXT:    [[TMP4:%.*]] = load volatile i32, i32* [[TMP3]], align 128
1137 // CHECK2-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP4]] to float
1138 // CHECK2-NEXT:    [[ADD:%.*]] = fadd float [[TMP1]], [[CONV]]
1139 // CHECK2-NEXT:    store float [[ADD]], float* [[F]], align 4
1140 // CHECK2-NEXT:    ret void
1141 //
1142 //
1143 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1144 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1145 // CHECK2-NEXT:  entry:
1146 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1147 // CHECK2-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1148 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1149 // CHECK2-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1150 // CHECK2-NEXT:    ret void
1151 //
1152 //
1153 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
1154 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
1155 // CHECK2-NEXT:  entry:
1156 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1157 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8
1158 // CHECK2-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1159 // CHECK2-NEXT:    store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8
1160 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1161 // CHECK2-NEXT:    ret %struct.S.0* [[THIS1]]
1162 //
1163 //
1164 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1165 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1166 // CHECK2-NEXT:  entry:
1167 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1168 // CHECK2-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1169 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1170 // CHECK2-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
1171 // CHECK2-NEXT:    ret void
1172 //
1173 //
1174 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..4
1175 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
1176 // CHECK2-NEXT:  entry:
1177 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1178 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1179 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1180 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %struct.S.0]*
1181 // CHECK2-NEXT:    [[ARRAYINIT_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP2]], i64 0, i64 0
1182 // CHECK2-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_BEGIN]], i32 1)
1183 // CHECK2-NEXT:    [[ARRAYINIT_ELEMENT:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAYINIT_BEGIN]], i64 1
1184 // CHECK2-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYINIT_ELEMENT]], i32 2)
1185 // CHECK2-NEXT:    [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1186 // CHECK2-NEXT:    ret i8* [[TMP3]]
1187 //
1188 //
1189 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1190 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1191 // CHECK2-NEXT:  entry:
1192 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1193 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1194 // CHECK2-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1195 // CHECK2-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
1196 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1197 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1198 // CHECK2-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
1199 // CHECK2-NEXT:    ret void
1200 //
1201 //
1202 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..5
1203 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
1204 // CHECK2-NEXT:  entry:
1205 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1206 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1207 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1208 // CHECK2-NEXT:    [[ARRAY_BEGIN:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0*
1209 // CHECK2-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1210 // CHECK2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1211 // CHECK2:       arraydestroy.body:
1212 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1213 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1214 // CHECK2-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1215 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1216 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1217 // CHECK2:       arraydestroy.done1:
1218 // CHECK2-NEXT:    ret void
1219 //
1220 //
1221 // CHECK2-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.6
1222 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
1223 // CHECK2-NEXT:  entry:
1224 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1225 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1226 // CHECK2-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1227 // CHECK2:       arraydestroy.body:
1228 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1229 // CHECK2-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1230 // CHECK2-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1231 // CHECK2-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0)
1232 // CHECK2-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1233 // CHECK2:       arraydestroy.done1:
1234 // CHECK2-NEXT:    ret void
1235 //
1236 //
1237 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_..7
1238 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
1239 // CHECK2-NEXT:  entry:
1240 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1241 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1242 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1243 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0*
1244 // CHECK2-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]], i32 3)
1245 // CHECK2-NEXT:    [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1246 // CHECK2-NEXT:    ret i8* [[TMP3]]
1247 //
1248 //
1249 // CHECK2-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_..8
1250 // CHECK2-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
1251 // CHECK2-NEXT:  entry:
1252 // CHECK2-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1253 // CHECK2-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1254 // CHECK2-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1255 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to %struct.S.0*
1256 // CHECK2-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP2]]) #[[ATTR3]]
1257 // CHECK2-NEXT:    ret void
1258 //
1259 //
1260 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..9
1261 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
1262 // CHECK2-NEXT:  entry:
1263 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1264 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1265 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1266 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1267 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1268 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1269 // CHECK2-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ5tmainIiET_vE5t_var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE5t_var.cache.)
1270 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
1271 // CHECK2-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
1272 // CHECK2-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64), [[TMP4]]
1273 // CHECK2-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1274 // CHECK2:       copyin.not.master:
1275 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
1276 // CHECK2-NEXT:    store i32 [[TMP6]], i32* [[TMP3]], align 128
1277 // CHECK2-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE3vec.cache.)
1278 // CHECK2-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to [2 x i32]*
1279 // CHECK2-NEXT:    [[TMP9:%.*]] = bitcast [2 x i32]* [[TMP8]] to i8*
1280 // CHECK2-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 [[TMP9]], i8* align 128 bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i64 8, i1 false)
1281 // CHECK2-NEXT:    [[TMP10:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE5s_arr.cache.)
1282 // CHECK2-NEXT:    [[TMP11:%.*]] = bitcast i8* [[TMP10]] to [2 x %struct.S.0]*
1283 // CHECK2-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP11]], i32 0, i32 0
1284 // CHECK2-NEXT:    [[TMP12:%.*]] = getelementptr [[STRUCT_S_0:%.*]], %struct.S.0* [[ARRAY_BEGIN]], i64 2
1285 // CHECK2-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.S.0* [[ARRAY_BEGIN]], [[TMP12]]
1286 // CHECK2-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1287 // CHECK2:       omp.arraycpy.body:
1288 // CHECK2-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1289 // CHECK2-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1290 // CHECK2-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
1291 // CHECK2-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1292 // CHECK2-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1293 // CHECK2-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP12]]
1294 // CHECK2-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
1295 // CHECK2:       omp.arraycpy.done1:
1296 // CHECK2-NEXT:    [[TMP13:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE3var.cache.)
1297 // CHECK2-NEXT:    [[TMP14:%.*]] = bitcast i8* [[TMP13]] to %struct.S.0*
1298 // CHECK2-NEXT:    [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TMP14]], %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)
1299 // CHECK2-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1300 // CHECK2:       copyin.not.master.end:
1301 // CHECK2-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]])
1302 // CHECK2-NEXT:    [[TMP15:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ5tmainIiET_vE5t_var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE5t_var.cache.)
1303 // CHECK2-NEXT:    [[TMP16:%.*]] = bitcast i8* [[TMP15]] to i32*
1304 // CHECK2-NEXT:    [[TMP17:%.*]] = load i32, i32* [[TMP16]], align 128
1305 // CHECK2-NEXT:    [[TMP18:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE3vec.cache.)
1306 // CHECK2-NEXT:    [[TMP19:%.*]] = bitcast i8* [[TMP18]] to [2 x i32]*
1307 // CHECK2-NEXT:    [[ARRAYIDX:%.*]] = getelementptr inbounds [2 x i32], [2 x i32]* [[TMP19]], i64 0, i64 0
1308 // CHECK2-NEXT:    store i32 [[TMP17]], i32* [[ARRAYIDX]], align 128
1309 // CHECK2-NEXT:    [[TMP20:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE3var.cache.)
1310 // CHECK2-NEXT:    [[TMP21:%.*]] = bitcast i8* [[TMP20]] to %struct.S.0*
1311 // CHECK2-NEXT:    [[TMP22:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr to i8*), i64 8, i8*** @_ZZ5tmainIiET_vE5s_arr.cache.)
1312 // CHECK2-NEXT:    [[TMP23:%.*]] = bitcast i8* [[TMP22]] to [2 x %struct.S.0]*
1313 // CHECK2-NEXT:    [[ARRAYIDX3:%.*]] = getelementptr inbounds [2 x %struct.S.0], [2 x %struct.S.0]* [[TMP23]], i64 0, i64 0
1314 // CHECK2-NEXT:    [[CALL4:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYIDX3]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP21]])
1315 // CHECK2-NEXT:    ret void
1316 //
1317 //
1318 // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..10
1319 // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR5]] {
1320 // CHECK2-NEXT:  entry:
1321 // CHECK2-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1322 // CHECK2-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1323 // CHECK2-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1324 // CHECK2-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1325 // CHECK2-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1326 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1327 // CHECK2-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @_ZZ5tmainIiET_vE5t_var to i8*), i64 4, i8*** @_ZZ5tmainIiET_vE5t_var.cache.)
1328 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
1329 // CHECK2-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
1330 // CHECK2-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64), [[TMP4]]
1331 // CHECK2-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1332 // CHECK2:       copyin.not.master:
1333 // CHECK2-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
1334 // CHECK2-NEXT:    store i32 [[TMP6]], i32* [[TMP3]], align 128
1335 // CHECK2-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1336 // CHECK2:       copyin.not.master.end:
1337 // CHECK2-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2]], i32 [[TMP1]])
1338 // CHECK2-NEXT:    ret void
1339 //
1340 //
1341 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1342 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1343 // CHECK2-NEXT:  entry:
1344 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1345 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1346 // CHECK2-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1347 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1348 // CHECK2-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1349 // CHECK2-NEXT:    [[TMP1:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
1350 // CHECK2-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
1351 // CHECK2-NEXT:    [[TMP3:%.*]] = load volatile i32, i32* [[TMP2]], align 128
1352 // CHECK2-NEXT:    store i32 [[TMP3]], i32* [[F]], align 4
1353 // CHECK2-NEXT:    ret void
1354 //
1355 //
1356 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1357 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1358 // CHECK2-NEXT:  entry:
1359 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1360 // CHECK2-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1361 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1362 // CHECK2-NEXT:    ret void
1363 //
1364 //
1365 // CHECK2-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1366 // CHECK2-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1367 // CHECK2-NEXT:  entry:
1368 // CHECK2-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1369 // CHECK2-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1370 // CHECK2-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1371 // CHECK2-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1372 // CHECK2-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
1373 // CHECK2-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1374 // CHECK2-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1375 // CHECK2-NEXT:    [[TMP1:%.*]] = load i32, i32* [[A_ADDR]], align 4
1376 // CHECK2-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
1377 // CHECK2-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
1378 // CHECK2-NEXT:    [[TMP4:%.*]] = load volatile i32, i32* [[TMP3]], align 128
1379 // CHECK2-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP1]], [[TMP4]]
1380 // CHECK2-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
1381 // CHECK2-NEXT:    ret void
1382 //
1383 //
1384 // CHECK3-LABEL: define {{[^@]+}}@main
1385 // CHECK3-SAME: () #[[ATTR0:[0-9]+]] {
1386 // CHECK3-NEXT:  entry:
1387 // CHECK3-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1388 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
1389 // CHECK3-NEXT:    store i32 0, i32* [[RETVAL]], align 4
1390 // CHECK3-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
1391 // CHECK3-NEXT:    ret i32 0
1392 //
1393 //
1394 // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined.
1395 // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR2:[0-9]+]] {
1396 // CHECK3-NEXT:  entry:
1397 // CHECK3-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1398 // CHECK3-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1399 // CHECK3-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 1
1400 // CHECK3-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1401 // CHECK3-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1402 // CHECK3-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1403 // CHECK3-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1404 // CHECK3-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP1]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
1405 // CHECK3-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
1406 // CHECK3-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
1407 // CHECK3-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @g to i64), [[TMP4]]
1408 // CHECK3-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1409 // CHECK3:       copyin.not.master:
1410 // CHECK3-NEXT:    [[TMP6:%.*]] = load i32, i32* @g, align 128
1411 // CHECK3-NEXT:    store volatile i32 [[TMP6]], i32* [[TMP3]], align 128
1412 // CHECK3-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1413 // CHECK3:       copyin.not.master.end:
1414 // CHECK3-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]])
1415 // CHECK3-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
1416 // CHECK3-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1417 // CHECK3-NEXT:    store volatile i32 1, i32* [[TMP8]], align 128
1418 // CHECK3-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 1 dereferenceable(1) [[REF_TMP]])
1419 // CHECK3-NEXT:    ret void
1420 //
1421 //
1422 // CHECK4-LABEL: define {{[^@]+}}@main
1423 // CHECK4-SAME: () #[[ATTR1:[0-9]+]] {
1424 // CHECK4-NEXT:  entry:
1425 // CHECK4-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1426 // CHECK4-NEXT:    store i32 0, i32* [[RETVAL]], align 4
1427 // CHECK4-NEXT:    [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8
1428 // CHECK4-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
1429 // CHECK4-NEXT:    call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*))
1430 // CHECK4-NEXT:    ret i32 0
1431 //
1432 //
1433 // CHECK4-LABEL: define {{[^@]+}}@__main_block_invoke
1434 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
1435 // CHECK4-NEXT:  entry:
1436 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
1437 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
1438 // CHECK4-NEXT:    store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1439 // CHECK4-NEXT:    [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
1440 // CHECK4-NEXT:    store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
1441 // CHECK4-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1442 // CHECK4-NEXT:    ret void
1443 //
1444 //
1445 // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined.
1446 // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
1447 // CHECK4-NEXT:  entry:
1448 // CHECK4-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1449 // CHECK4-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1450 // CHECK4-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1451 // CHECK4-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1452 // CHECK4-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1453 // CHECK4-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1454 // CHECK4-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
1455 // CHECK4-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to i32*
1456 // CHECK4-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP3]] to i64
1457 // CHECK4-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint (i32* @g to i64), [[TMP4]]
1458 // CHECK4-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1459 // CHECK4:       copyin.not.master:
1460 // CHECK4-NEXT:    [[TMP6:%.*]] = load i32, i32* @g, align 128
1461 // CHECK4-NEXT:    store volatile i32 [[TMP6]], i32* [[TMP3]], align 128
1462 // CHECK4-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1463 // CHECK4:       copyin.not.master.end:
1464 // CHECK4-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]])
1465 // CHECK4-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
1466 // CHECK4-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to i32*
1467 // CHECK4-NEXT:    store volatile i32 1, i32* [[TMP8]], align 128
1468 // CHECK4-NEXT:    [[TMP9:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8
1469 // CHECK4-NEXT:    [[TMP10:%.*]] = bitcast i8* [[TMP9]] to void (i8*)*
1470 // CHECK4-NEXT:    call void [[TMP10]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*))
1471 // CHECK4-NEXT:    ret void
1472 //
1473 //
1474 // CHECK4-LABEL: define {{[^@]+}}@g_block_invoke
1475 // CHECK4-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
1476 // CHECK4-NEXT:  entry:
1477 // CHECK4-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
1478 // CHECK4-NEXT:    [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
1479 // CHECK4-NEXT:    [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1]])
1480 // CHECK4-NEXT:    store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
1481 // CHECK4-NEXT:    [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
1482 // CHECK4-NEXT:    store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
1483 // CHECK4-NEXT:    [[TMP1:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP0]], i8* bitcast (i32* @g to i8*), i64 4, i8*** @g.cache.)
1484 // CHECK4-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to i32*
1485 // CHECK4-NEXT:    store volatile i32 2, i32* [[TMP2]], align 128
1486 // CHECK4-NEXT:    ret void
1487 //
1488 //
1489 // CHECK5-LABEL: define {{[^@]+}}@_Z10array_funcv
1490 // CHECK5-SAME: () #[[ATTR0:[0-9]+]] {
1491 // CHECK5-NEXT:  entry:
1492 // CHECK5-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ10array_funcvE1s to i8*) acquire, align 8
1493 // CHECK5-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1494 // CHECK5-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
1495 // CHECK5:       init.check:
1496 // CHECK5-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]]
1497 // CHECK5-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1498 // CHECK5-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
1499 // CHECK5:       init:
1500 // CHECK5-NEXT:    [[TMP2:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB1:[0-9]+]])
1501 // CHECK5-NEXT:    call void @__kmpc_threadprivate_register(%struct.ident_t* @[[GLOB1]], i8* bitcast ([2 x %struct.St]* @_ZZ10array_funcvE1s to i8*), i8* (i8*)* @.__kmpc_global_ctor_., i8* (i8*, i8*)* null, void (i8*)* @.__kmpc_global_dtor_.)
1502 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1503 // CHECK5:       arrayctor.loop:
1504 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1505 // CHECK5-NEXT:    call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])
1506 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1
1507 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2)
1508 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1509 // CHECK5:       arrayctor.cont:
1510 // CHECK5-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR1]]
1511 // CHECK5-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1]]
1512 // CHECK5-NEXT:    br label [[INIT_END]]
1513 // CHECK5:       init.end:
1514 // CHECK5-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB1]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
1515 // CHECK5-NEXT:    ret void
1516 //
1517 //
1518 // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_ctor_.
1519 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
1520 // CHECK5-NEXT:  entry:
1521 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1522 // CHECK5-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1523 // CHECK5-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1524 // CHECK5-NEXT:    [[TMP2:%.*]] = bitcast i8* [[TMP1]] to [2 x %struct.St]*
1525 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], [2 x %struct.St]* [[TMP2]], i32 0, i32 0
1526 // CHECK5-NEXT:    [[ARRAYCTOR_END:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAY_BEGIN]], i64 2
1527 // CHECK5-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
1528 // CHECK5:       arrayctor.loop:
1529 // CHECK5-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ [[ARRAY_BEGIN]], [[ENTRY:%.*]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
1530 // CHECK5-NEXT:    call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])
1531 // CHECK5-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYCTOR_CUR]], i64 1
1532 // CHECK5-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], [[ARRAYCTOR_END]]
1533 // CHECK5-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
1534 // CHECK5:       arrayctor.cont:
1535 // CHECK5-NEXT:    [[TMP3:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1536 // CHECK5-NEXT:    ret i8* [[TMP3]]
1537 //
1538 //
1539 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StC1Ev
1540 // CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3:[0-9]+]] align 2 {
1541 // CHECK5-NEXT:  entry:
1542 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1543 // CHECK5-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1544 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1545 // CHECK5-NEXT:    call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
1546 // CHECK5-NEXT:    ret void
1547 //
1548 //
1549 // CHECK5-LABEL: define {{[^@]+}}@.__kmpc_global_dtor_.
1550 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {
1551 // CHECK5-NEXT:  entry:
1552 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1553 // CHECK5-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1554 // CHECK5-NEXT:    [[TMP1:%.*]] = load i8*, i8** [[DOTADDR]], align 8
1555 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = bitcast i8* [[TMP1]] to %struct.St*
1556 // CHECK5-NEXT:    [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAY_BEGIN]], i64 2
1557 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1558 // CHECK5:       arraydestroy.body:
1559 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ [[TMP2]], [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1560 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1561 // CHECK5-NEXT:    call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]]
1562 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], [[ARRAY_BEGIN]]
1563 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1564 // CHECK5:       arraydestroy.done1:
1565 // CHECK5-NEXT:    ret void
1566 //
1567 //
1568 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StD1Ev
1569 // CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
1570 // CHECK5-NEXT:  entry:
1571 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1572 // CHECK5-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1573 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1574 // CHECK5-NEXT:    call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]]
1575 // CHECK5-NEXT:    ret void
1576 //
1577 //
1578 // CHECK5-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1579 // CHECK5-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2]] section "__TEXT,__StaticInit,regular,pure_instructions" {
1580 // CHECK5-NEXT:  entry:
1581 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1582 // CHECK5-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1583 // CHECK5-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1584 // CHECK5:       arraydestroy.body:
1585 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1586 // CHECK5-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1587 // CHECK5-NEXT:    call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]]
1588 // CHECK5-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0)
1589 // CHECK5-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1590 // CHECK5:       arraydestroy.done1:
1591 // CHECK5-NEXT:    ret void
1592 //
1593 //
1594 // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined.
1595 // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR4:[0-9]+]] {
1596 // CHECK5-NEXT:  entry:
1597 // CHECK5-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
1598 // CHECK5-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
1599 // CHECK5-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
1600 // CHECK5-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
1601 // CHECK5-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
1602 // CHECK5-NEXT:    [[TMP1:%.*]] = load i32, i32* [[TMP0]], align 4
1603 // CHECK5-NEXT:    [[TMP2:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x i32]* @_ZZ10array_funcvE1a to i8*), i64 8, i8*** @_ZZ10array_funcvE1a.cache.)
1604 // CHECK5-NEXT:    [[TMP3:%.*]] = bitcast i8* [[TMP2]] to [2 x i32]*
1605 // CHECK5-NEXT:    [[TMP4:%.*]] = ptrtoint [2 x i32]* [[TMP3]] to i64
1606 // CHECK5-NEXT:    [[TMP5:%.*]] = icmp ne i64 ptrtoint ([2 x i32]* @_ZZ10array_funcvE1a to i64), [[TMP4]]
1607 // CHECK5-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
1608 // CHECK5:       copyin.not.master:
1609 // CHECK5-NEXT:    [[TMP6:%.*]] = bitcast [2 x i32]* [[TMP3]] to i8*
1610 // CHECK5-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 [[TMP6]], i8* align 4 bitcast ([2 x i32]* @_ZZ10array_funcvE1a to i8*), i64 8, i1 false)
1611 // CHECK5-NEXT:    [[TMP7:%.*]] = call i8* @__kmpc_threadprivate_cached(%struct.ident_t* @[[GLOB1]], i32 [[TMP1]], i8* bitcast ([2 x %struct.St]* @_ZZ10array_funcvE1s to i8*), i64 16, i8*** @_ZZ10array_funcvE1s.cache.)
1612 // CHECK5-NEXT:    [[TMP8:%.*]] = bitcast i8* [[TMP7]] to [2 x %struct.St]*
1613 // CHECK5-NEXT:    [[ARRAY_BEGIN:%.*]] = getelementptr inbounds [2 x %struct.St], [2 x %struct.St]* [[TMP8]], i32 0, i32 0
1614 // CHECK5-NEXT:    [[TMP9:%.*]] = getelementptr [[STRUCT_ST:%.*]], %struct.St* [[ARRAY_BEGIN]], i64 2
1615 // CHECK5-NEXT:    [[OMP_ARRAYCPY_ISEMPTY:%.*]] = icmp eq %struct.St* [[ARRAY_BEGIN]], [[TMP9]]
1616 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_ISEMPTY]], label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
1617 // CHECK5:       omp.arraycpy.body:
1618 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1619 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.St* [ [[ARRAY_BEGIN]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
1620 // CHECK5-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(8) %struct.St* @_ZN2StaSERKS_(%struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
1621 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
1622 // CHECK5-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
1623 // CHECK5-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.St* [[OMP_ARRAYCPY_DEST_ELEMENT]], [[TMP9]]
1624 // CHECK5-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
1625 // CHECK5:       omp.arraycpy.done1:
1626 // CHECK5-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
1627 // CHECK5:       copyin.not.master.end:
1628 // CHECK5-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP1]])
1629 // CHECK5-NEXT:    ret void
1630 //
1631 //
1632 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StaSERKS_
1633 // CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] align 2 {
1634 // CHECK5-NEXT:  entry:
1635 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1636 // CHECK5-NEXT:    [[DOTADDR:%.*]] = alloca %struct.St*, align 8
1637 // CHECK5-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1638 // CHECK5-NEXT:    store %struct.St* [[TMP0]], %struct.St** [[DOTADDR]], align 8
1639 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1640 // CHECK5-NEXT:    ret %struct.St* [[THIS1]]
1641 //
1642 //
1643 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StC2Ev
1644 // CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
1645 // CHECK5-NEXT:  entry:
1646 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1647 // CHECK5-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1648 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1649 // CHECK5-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
1650 // CHECK5-NEXT:    store i32 0, i32* [[A]], align 4
1651 // CHECK5-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
1652 // CHECK5-NEXT:    store i32 0, i32* [[B]], align 4
1653 // CHECK5-NEXT:    ret void
1654 //
1655 //
1656 // CHECK5-LABEL: define {{[^@]+}}@_ZN2StD2Ev
1657 // CHECK5-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR3]] align 2 {
1658 // CHECK5-NEXT:  entry:
1659 // CHECK5-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
1660 // CHECK5-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
1661 // CHECK5-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
1662 // CHECK5-NEXT:    ret void
1663 //
1664 //
1665 // CHECK6-LABEL: define {{[^@]+}}@main
1666 // CHECK6-SAME: () #[[ATTR0:[0-9]+]] {
1667 // CHECK6-NEXT:  entry:
1668 // CHECK6-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1669 // CHECK6-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1670 // CHECK6-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
1671 // CHECK6-NEXT:    store i32 0, i32* [[RETVAL]], align 4
1672 // CHECK6-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
1673 // CHECK6-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
1674 // CHECK6-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
1675 // CHECK6-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
1676 // CHECK6-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8
1677 // CHECK6-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1678 // CHECK6-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
1679 // CHECK6:       init.check:
1680 // CHECK6-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
1681 // CHECK6-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1682 // CHECK6-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
1683 // CHECK6:       init:
1684 // CHECK6-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00)
1685 // CHECK6-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00)
1686 // CHECK6-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]]
1687 // CHECK6-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
1688 // CHECK6-NEXT:    br label [[INIT_END]]
1689 // CHECK6:       init.end:
1690 // CHECK6-NEXT:    [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8
1691 // CHECK6-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0
1692 // CHECK6-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
1693 // CHECK6:       init.check2:
1694 // CHECK6-NEXT:    [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
1695 // CHECK6-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0
1696 // CHECK6-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
1697 // CHECK6:       init4:
1698 // CHECK6-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00)
1699 // CHECK6-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
1700 // CHECK6-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
1701 // CHECK6-NEXT:    br label [[INIT_END5]]
1702 // CHECK6:       init.end5:
1703 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
1704 // CHECK6-NEXT:    store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4
1705 // CHECK6-NEXT:    [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)
1706 // CHECK6-NEXT:    [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
1707 // CHECK6-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
1708 // CHECK6-NEXT:    store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4
1709 // CHECK6-NEXT:    [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v()
1710 // CHECK6-NEXT:    store i32 [[CALL7]], i32* [[RETVAL]], align 4
1711 // CHECK6-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
1712 // CHECK6-NEXT:    [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4
1713 // CHECK6-NEXT:    ret i32 [[TMP8]]
1714 //
1715 //
1716 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
1717 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
1718 // CHECK6-NEXT:  entry:
1719 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1720 // CHECK6-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1721 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1722 // CHECK6-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
1723 // CHECK6-NEXT:    ret void
1724 //
1725 //
1726 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
1727 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
1728 // CHECK6-NEXT:  entry:
1729 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1730 // CHECK6-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S*, align 8
1731 // CHECK6-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1732 // CHECK6-NEXT:    store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
1733 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1734 // CHECK6-NEXT:    ret %struct.S* [[THIS1]]
1735 //
1736 //
1737 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
1738 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1739 // CHECK6-NEXT:  entry:
1740 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1741 // CHECK6-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1742 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1743 // CHECK6-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
1744 // CHECK6-NEXT:    ret void
1745 //
1746 //
1747 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
1748 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1749 // CHECK6-NEXT:  entry:
1750 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1751 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1752 // CHECK6-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1753 // CHECK6-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
1754 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1755 // CHECK6-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1756 // CHECK6-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
1757 // CHECK6-NEXT:    ret void
1758 //
1759 //
1760 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
1761 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" {
1762 // CHECK6-NEXT:  entry:
1763 // CHECK6-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1764 // CHECK6-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1765 // CHECK6-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1766 // CHECK6:       arraydestroy.body:
1767 // CHECK6-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1768 // CHECK6-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1769 // CHECK6-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1770 // CHECK6-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0)
1771 // CHECK6-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1772 // CHECK6:       arraydestroy.done1:
1773 // CHECK6-NEXT:    ret void
1774 //
1775 //
1776 // CHECK6-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
1777 // CHECK6-SAME: () #[[ATTR2]] comdat {
1778 // CHECK6-NEXT:  entry:
1779 // CHECK6-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
1780 // CHECK6-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
1781 // CHECK6-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
1782 // CHECK6-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
1783 // CHECK6-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
1784 // CHECK6-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]]
1785 // CHECK6-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8
1786 // CHECK6-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1787 // CHECK6-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]]
1788 // CHECK6:       init.check:
1789 // CHECK6-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
1790 // CHECK6-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1791 // CHECK6-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
1792 // CHECK6:       init:
1793 // CHECK6-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1)
1794 // CHECK6-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2)
1795 // CHECK6-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]]
1796 // CHECK6-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
1797 // CHECK6-NEXT:    br label [[INIT_END]]
1798 // CHECK6:       init.end:
1799 // CHECK6-NEXT:    [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8
1800 // CHECK6-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0
1801 // CHECK6-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
1802 // CHECK6:       init.check2:
1803 // CHECK6-NEXT:    [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
1804 // CHECK6-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0
1805 // CHECK6-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
1806 // CHECK6:       init4:
1807 // CHECK6-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3)
1808 // CHECK6-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
1809 // CHECK6-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
1810 // CHECK6-NEXT:    br label [[INIT_END5]]
1811 // CHECK6:       init.end5:
1812 // CHECK6-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
1813 // CHECK6-NEXT:    store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128
1814 // CHECK6-NEXT:    [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)
1815 // CHECK6-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
1816 // CHECK6-NEXT:    ret i32 0
1817 //
1818 //
1819 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
1820 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1821 // CHECK6-NEXT:  entry:
1822 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1823 // CHECK6-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1824 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1825 // CHECK6-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1826 // CHECK6-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
1827 // CHECK6-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
1828 // CHECK6-NEXT:    store float [[CONV]], float* [[F]], align 4
1829 // CHECK6-NEXT:    ret void
1830 //
1831 //
1832 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
1833 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1834 // CHECK6-NEXT:  entry:
1835 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1836 // CHECK6-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1837 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1838 // CHECK6-NEXT:    ret void
1839 //
1840 //
1841 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
1842 // CHECK6-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1843 // CHECK6-NEXT:  entry:
1844 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
1845 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
1846 // CHECK6-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
1847 // CHECK6-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
1848 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
1849 // CHECK6-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
1850 // CHECK6-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
1851 // CHECK6-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
1852 // CHECK6-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
1853 // CHECK6-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
1854 // CHECK6-NEXT:    store float [[ADD]], float* [[F]], align 4
1855 // CHECK6-NEXT:    ret void
1856 //
1857 //
1858 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
1859 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1860 // CHECK6-NEXT:  entry:
1861 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1862 // CHECK6-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1863 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1864 // CHECK6-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
1865 // CHECK6-NEXT:    ret void
1866 //
1867 //
1868 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
1869 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
1870 // CHECK6-NEXT:  entry:
1871 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1872 // CHECK6-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8
1873 // CHECK6-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1874 // CHECK6-NEXT:    store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8
1875 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1876 // CHECK6-NEXT:    ret %struct.S.0* [[THIS1]]
1877 //
1878 //
1879 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
1880 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1881 // CHECK6-NEXT:  entry:
1882 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1883 // CHECK6-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1884 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1885 // CHECK6-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
1886 // CHECK6-NEXT:    ret void
1887 //
1888 //
1889 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
1890 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1891 // CHECK6-NEXT:  entry:
1892 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1893 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1894 // CHECK6-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1895 // CHECK6-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
1896 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1897 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1898 // CHECK6-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
1899 // CHECK6-NEXT:    ret void
1900 //
1901 //
1902 // CHECK6-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1
1903 // CHECK6-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
1904 // CHECK6-NEXT:  entry:
1905 // CHECK6-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
1906 // CHECK6-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
1907 // CHECK6-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
1908 // CHECK6:       arraydestroy.body:
1909 // CHECK6-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
1910 // CHECK6-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
1911 // CHECK6-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
1912 // CHECK6-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0)
1913 // CHECK6-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
1914 // CHECK6:       arraydestroy.done1:
1915 // CHECK6-NEXT:    ret void
1916 //
1917 //
1918 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
1919 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1920 // CHECK6-NEXT:  entry:
1921 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1922 // CHECK6-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1923 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1924 // CHECK6-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1925 // CHECK6-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
1926 // CHECK6-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
1927 // CHECK6-NEXT:    ret void
1928 //
1929 //
1930 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
1931 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1932 // CHECK6-NEXT:  entry:
1933 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1934 // CHECK6-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1935 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1936 // CHECK6-NEXT:    ret void
1937 //
1938 //
1939 // CHECK6-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
1940 // CHECK6-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
1941 // CHECK6-NEXT:  entry:
1942 // CHECK6-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
1943 // CHECK6-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
1944 // CHECK6-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
1945 // CHECK6-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
1946 // CHECK6-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
1947 // CHECK6-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
1948 // CHECK6-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
1949 // CHECK6-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
1950 // CHECK6-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
1951 // CHECK6-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
1952 // CHECK6-NEXT:    ret void
1953 //
1954 //
1955 // CHECK7-LABEL: define {{[^@]+}}@main
1956 // CHECK7-SAME: () #[[ATTR0:[0-9]+]] {
1957 // CHECK7-NEXT:  entry:
1958 // CHECK7-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
1959 // CHECK7-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
1960 // CHECK7-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
1961 // CHECK7-NEXT:    store i32 0, i32* [[RETVAL]], align 4
1962 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
1963 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
1964 // CHECK7-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
1965 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
1966 // CHECK7-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8
1967 // CHECK7-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
1968 // CHECK7-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
1969 // CHECK7:       init.check:
1970 // CHECK7-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
1971 // CHECK7-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
1972 // CHECK7-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
1973 // CHECK7:       init:
1974 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00)
1975 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00)
1976 // CHECK7-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]]
1977 // CHECK7-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
1978 // CHECK7-NEXT:    br label [[INIT_END]]
1979 // CHECK7:       init.end:
1980 // CHECK7-NEXT:    [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8
1981 // CHECK7-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0
1982 // CHECK7-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
1983 // CHECK7:       init.check2:
1984 // CHECK7-NEXT:    [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
1985 // CHECK7-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0
1986 // CHECK7-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
1987 // CHECK7:       init4:
1988 // CHECK7-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00)
1989 // CHECK7-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
1990 // CHECK7-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
1991 // CHECK7-NEXT:    br label [[INIT_END5]]
1992 // CHECK7:       init.end5:
1993 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
1994 // CHECK7-NEXT:    store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4
1995 // CHECK7-NEXT:    [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)
1996 // CHECK7-NEXT:    [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
1997 // CHECK7-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
1998 // CHECK7-NEXT:    store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4
1999 // CHECK7-NEXT:    [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v()
2000 // CHECK7-NEXT:    store i32 [[CALL7]], i32* [[RETVAL]], align 4
2001 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
2002 // CHECK7-NEXT:    [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4
2003 // CHECK7-NEXT:    ret i32 [[TMP8]]
2004 //
2005 //
2006 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2007 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2008 // CHECK7-NEXT:  entry:
2009 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2010 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2011 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2012 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2013 // CHECK7-NEXT:    ret void
2014 //
2015 //
2016 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
2017 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
2018 // CHECK7-NEXT:  entry:
2019 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2020 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S*, align 8
2021 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2022 // CHECK7-NEXT:    store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
2023 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2024 // CHECK7-NEXT:    ret %struct.S* [[THIS1]]
2025 //
2026 //
2027 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2028 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2029 // CHECK7-NEXT:  entry:
2030 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2031 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2032 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2033 // CHECK7-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
2034 // CHECK7-NEXT:    ret void
2035 //
2036 //
2037 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2038 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2039 // CHECK7-NEXT:  entry:
2040 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2041 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2042 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2043 // CHECK7-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
2044 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2045 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2046 // CHECK7-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2047 // CHECK7-NEXT:    ret void
2048 //
2049 //
2050 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2051 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" {
2052 // CHECK7-NEXT:  entry:
2053 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
2054 // CHECK7-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2055 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2056 // CHECK7:       arraydestroy.body:
2057 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2058 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2059 // CHECK7-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
2060 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0)
2061 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2062 // CHECK7:       arraydestroy.done1:
2063 // CHECK7-NEXT:    ret void
2064 //
2065 //
2066 // CHECK7-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2067 // CHECK7-SAME: () #[[ATTR2]] comdat {
2068 // CHECK7-NEXT:  entry:
2069 // CHECK7-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2070 // CHECK7-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
2071 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2072 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2073 // CHECK7-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2074 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]]
2075 // CHECK7-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8
2076 // CHECK7-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
2077 // CHECK7-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]]
2078 // CHECK7:       init.check:
2079 // CHECK7-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
2080 // CHECK7-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
2081 // CHECK7-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
2082 // CHECK7:       init:
2083 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1)
2084 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2)
2085 // CHECK7-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]]
2086 // CHECK7-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
2087 // CHECK7-NEXT:    br label [[INIT_END]]
2088 // CHECK7:       init.end:
2089 // CHECK7-NEXT:    [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8
2090 // CHECK7-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0
2091 // CHECK7-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
2092 // CHECK7:       init.check2:
2093 // CHECK7-NEXT:    [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
2094 // CHECK7-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0
2095 // CHECK7-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
2096 // CHECK7:       init4:
2097 // CHECK7-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3)
2098 // CHECK7-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
2099 // CHECK7-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
2100 // CHECK7-NEXT:    br label [[INIT_END5]]
2101 // CHECK7:       init.end5:
2102 // CHECK7-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
2103 // CHECK7-NEXT:    store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128
2104 // CHECK7-NEXT:    [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)
2105 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
2106 // CHECK7-NEXT:    ret i32 0
2107 //
2108 //
2109 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2110 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2111 // CHECK7-NEXT:  entry:
2112 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2113 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2114 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2115 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2116 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
2117 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2118 // CHECK7-NEXT:    store float [[CONV]], float* [[F]], align 4
2119 // CHECK7-NEXT:    ret void
2120 //
2121 //
2122 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2123 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2124 // CHECK7-NEXT:  entry:
2125 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2126 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2127 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2128 // CHECK7-NEXT:    ret void
2129 //
2130 //
2131 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2132 // CHECK7-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2133 // CHECK7-NEXT:  entry:
2134 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2135 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2136 // CHECK7-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2137 // CHECK7-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
2138 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2139 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2140 // CHECK7-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2141 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
2142 // CHECK7-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2143 // CHECK7-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2144 // CHECK7-NEXT:    store float [[ADD]], float* [[F]], align 4
2145 // CHECK7-NEXT:    ret void
2146 //
2147 //
2148 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2149 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2150 // CHECK7-NEXT:  entry:
2151 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2152 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2153 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2154 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2155 // CHECK7-NEXT:    ret void
2156 //
2157 //
2158 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
2159 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
2160 // CHECK7-NEXT:  entry:
2161 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2162 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8
2163 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2164 // CHECK7-NEXT:    store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8
2165 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2166 // CHECK7-NEXT:    ret %struct.S.0* [[THIS1]]
2167 //
2168 //
2169 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2170 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2171 // CHECK7-NEXT:  entry:
2172 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2173 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2174 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2175 // CHECK7-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
2176 // CHECK7-NEXT:    ret void
2177 //
2178 //
2179 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2180 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2181 // CHECK7-NEXT:  entry:
2182 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2183 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2184 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2185 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2186 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2187 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2188 // CHECK7-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
2189 // CHECK7-NEXT:    ret void
2190 //
2191 //
2192 // CHECK7-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1
2193 // CHECK7-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
2194 // CHECK7-NEXT:  entry:
2195 // CHECK7-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
2196 // CHECK7-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2197 // CHECK7-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2198 // CHECK7:       arraydestroy.body:
2199 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2200 // CHECK7-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2201 // CHECK7-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
2202 // CHECK7-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0)
2203 // CHECK7-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2204 // CHECK7:       arraydestroy.done1:
2205 // CHECK7-NEXT:    ret void
2206 //
2207 //
2208 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2209 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2210 // CHECK7-NEXT:  entry:
2211 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2212 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2213 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2214 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2215 // CHECK7-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
2216 // CHECK7-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
2217 // CHECK7-NEXT:    ret void
2218 //
2219 //
2220 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2221 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2222 // CHECK7-NEXT:  entry:
2223 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2224 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2225 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2226 // CHECK7-NEXT:    ret void
2227 //
2228 //
2229 // CHECK7-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2230 // CHECK7-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2231 // CHECK7-NEXT:  entry:
2232 // CHECK7-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2233 // CHECK7-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2234 // CHECK7-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2235 // CHECK7-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2236 // CHECK7-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2237 // CHECK7-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2238 // CHECK7-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2239 // CHECK7-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
2240 // CHECK7-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2241 // CHECK7-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
2242 // CHECK7-NEXT:    ret void
2243 //
2244 //
2245 // CHECK8-LABEL: define {{[^@]+}}@main
2246 // CHECK8-SAME: () #[[ATTR0:[0-9]+]] {
2247 // CHECK8-NEXT:  entry:
2248 // CHECK8-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2249 // CHECK8-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
2250 // CHECK8-NEXT:    store i32 0, i32* [[RETVAL]], align 4
2251 // CHECK8-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
2252 // CHECK8-NEXT:    ret i32 0
2253 //
2254 //
2255 // CHECK9-LABEL: define {{[^@]+}}@main
2256 // CHECK9-SAME: () #[[ATTR1:[0-9]+]] {
2257 // CHECK9-NEXT:  entry:
2258 // CHECK9-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2259 // CHECK9-NEXT:    store i32 0, i32* [[RETVAL]], align 4
2260 // CHECK9-NEXT:    [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8
2261 // CHECK9-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
2262 // CHECK9-NEXT:    call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*))
2263 // CHECK9-NEXT:    ret i32 0
2264 //
2265 //
2266 // CHECK9-LABEL: define {{[^@]+}}@__main_block_invoke
2267 // CHECK9-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
2268 // CHECK9-NEXT:  entry:
2269 // CHECK9-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
2270 // CHECK9-NEXT:    [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
2271 // CHECK9-NEXT:    store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2272 // CHECK9-NEXT:    [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
2273 // CHECK9-NEXT:    store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
2274 // CHECK9-NEXT:    store volatile i32 1, i32* @g, align 128
2275 // CHECK9-NEXT:    [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8
2276 // CHECK9-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
2277 // CHECK9-NEXT:    call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*))
2278 // CHECK9-NEXT:    ret void
2279 //
2280 //
2281 // CHECK9-LABEL: define {{[^@]+}}@__main_block_invoke_2
2282 // CHECK9-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
2283 // CHECK9-NEXT:  entry:
2284 // CHECK9-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
2285 // CHECK9-NEXT:    [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
2286 // CHECK9-NEXT:    store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
2287 // CHECK9-NEXT:    [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
2288 // CHECK9-NEXT:    store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
2289 // CHECK9-NEXT:    store volatile i32 2, i32* @g, align 128
2290 // CHECK9-NEXT:    ret void
2291 //
2292 //
2293 // CHECK10-LABEL: define {{[^@]+}}@_Z10array_funcv
2294 // CHECK10-SAME: () #[[ATTR0:[0-9]+]] {
2295 // CHECK10-NEXT:  entry:
2296 // CHECK10-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ10array_funcvE1s to i8*) acquire, align 8
2297 // CHECK10-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
2298 // CHECK10-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
2299 // CHECK10:       init.check:
2300 // CHECK10-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]]
2301 // CHECK10-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
2302 // CHECK10-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
2303 // CHECK10:       init:
2304 // CHECK10-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
2305 // CHECK10:       arrayctor.loop:
2306 // CHECK10-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
2307 // CHECK10-NEXT:    call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])
2308 // CHECK10-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1
2309 // CHECK10-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2)
2310 // CHECK10-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
2311 // CHECK10:       arrayctor.cont:
2312 // CHECK10-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR1]]
2313 // CHECK10-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1]]
2314 // CHECK10-NEXT:    br label [[INIT_END]]
2315 // CHECK10:       init.end:
2316 // CHECK10-NEXT:    ret void
2317 //
2318 //
2319 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC1Ev
2320 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] align 2 {
2321 // CHECK10-NEXT:  entry:
2322 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
2323 // CHECK10-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
2324 // CHECK10-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
2325 // CHECK10-NEXT:    call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
2326 // CHECK10-NEXT:    ret void
2327 //
2328 //
2329 // CHECK10-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2330 // CHECK10-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section "__TEXT,__StaticInit,regular,pure_instructions" {
2331 // CHECK10-NEXT:  entry:
2332 // CHECK10-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
2333 // CHECK10-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2334 // CHECK10-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2335 // CHECK10:       arraydestroy.body:
2336 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2337 // CHECK10-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2338 // CHECK10-NEXT:    call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]]
2339 // CHECK10-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0)
2340 // CHECK10-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2341 // CHECK10:       arraydestroy.done1:
2342 // CHECK10-NEXT:    ret void
2343 //
2344 //
2345 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD1Ev
2346 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
2347 // CHECK10-NEXT:  entry:
2348 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
2349 // CHECK10-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
2350 // CHECK10-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
2351 // CHECK10-NEXT:    call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]]
2352 // CHECK10-NEXT:    ret void
2353 //
2354 //
2355 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StC2Ev
2356 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
2357 // CHECK10-NEXT:  entry:
2358 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
2359 // CHECK10-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
2360 // CHECK10-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
2361 // CHECK10-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
2362 // CHECK10-NEXT:    store i32 0, i32* [[A]], align 4
2363 // CHECK10-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
2364 // CHECK10-NEXT:    store i32 0, i32* [[B]], align 4
2365 // CHECK10-NEXT:    ret void
2366 //
2367 //
2368 // CHECK10-LABEL: define {{[^@]+}}@_ZN2StD2Ev
2369 // CHECK10-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] align 2 {
2370 // CHECK10-NEXT:  entry:
2371 // CHECK10-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
2372 // CHECK10-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
2373 // CHECK10-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
2374 // CHECK10-NEXT:    ret void
2375 //
2376 //
2377 // CHECK11-LABEL: define {{[^@]+}}@main
2378 // CHECK11-SAME: () #[[ATTR0:[0-9]+]] {
2379 // CHECK11-NEXT:  entry:
2380 // CHECK11-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2381 // CHECK11-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2382 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
2383 // CHECK11-NEXT:    store i32 0, i32* [[RETVAL]], align 4
2384 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
2385 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2386 // CHECK11-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2387 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4:[0-9]+]]
2388 // CHECK11-NEXT:    [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE5s_arr, align 1
2389 // CHECK11-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
2390 // CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
2391 // CHECK11:       init.check:
2392 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00)
2393 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00)
2394 // CHECK11-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]]
2395 // CHECK11-NEXT:    store i8 1, i8* @_ZGVZ4mainE5s_arr, align 1
2396 // CHECK11-NEXT:    br label [[INIT_END]]
2397 // CHECK11:       init.end:
2398 // CHECK11-NEXT:    [[TMP2:%.*]] = load i8, i8* @_ZGVZ4mainE3var, align 1
2399 // CHECK11-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0
2400 // CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]]
2401 // CHECK11:       init.check2:
2402 // CHECK11-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00)
2403 // CHECK11-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR4]]
2404 // CHECK11-NEXT:    store i8 1, i8* @_ZGVZ4mainE3var, align 1
2405 // CHECK11-NEXT:    br label [[INIT_END3]]
2406 // CHECK11:       init.end3:
2407 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var, [2 x i32]* @_ZZ4mainE3vec, [2 x %struct.S]* @_ZZ4mainE5s_arr, %struct.S* @_ZZ4mainE3var)
2408 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var)
2409 // CHECK11-NEXT:    [[CALL4:%.*]] = call i32 @_Z5tmainIiET_v()
2410 // CHECK11-NEXT:    store i32 [[CALL4]], i32* [[RETVAL]], align 4
2411 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2412 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
2413 // CHECK11-NEXT:    ret i32 [[TMP4]]
2414 //
2415 //
2416 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2417 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2418 // CHECK11-NEXT:  entry:
2419 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2420 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2421 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2422 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2423 // CHECK11-NEXT:    ret void
2424 //
2425 //
2426 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
2427 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
2428 // CHECK11-NEXT:  entry:
2429 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2430 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S*, align 8
2431 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2432 // CHECK11-NEXT:    store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
2433 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2434 // CHECK11-NEXT:    ret %struct.S* [[THIS1]]
2435 //
2436 //
2437 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2438 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2439 // CHECK11-NEXT:  entry:
2440 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2441 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2442 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2443 // CHECK11-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2444 // CHECK11-NEXT:    ret void
2445 //
2446 //
2447 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2448 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2449 // CHECK11-NEXT:  entry:
2450 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2451 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2452 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2453 // CHECK11-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
2454 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2455 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2456 // CHECK11-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2457 // CHECK11-NEXT:    ret void
2458 //
2459 //
2460 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2461 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" {
2462 // CHECK11-NEXT:  entry:
2463 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
2464 // CHECK11-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2465 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2466 // CHECK11:       arraydestroy.body:
2467 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2468 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2469 // CHECK11-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2470 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0)
2471 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2472 // CHECK11:       arraydestroy.done1:
2473 // CHECK11-NEXT:    ret void
2474 //
2475 //
2476 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined.
2477 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] {
2478 // CHECK11-NEXT:  entry:
2479 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2480 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2481 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
2482 // CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2483 // CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
2484 // CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
2485 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2486 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2487 // CHECK11-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
2488 // CHECK11-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2489 // CHECK11-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2490 // CHECK11-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
2491 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
2492 // CHECK11-NEXT:    [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2493 // CHECK11-NEXT:    [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2494 // CHECK11-NEXT:    [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
2495 // CHECK11-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64
2496 // CHECK11-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ4mainE5t_var to i64)
2497 // CHECK11-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
2498 // CHECK11:       copyin.not.master:
2499 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4
2500 // CHECK11-NEXT:    store i32 [[TMP6]], i32* @_ZZ4mainE5t_var, align 4
2501 // CHECK11-NEXT:    [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8*
2502 // CHECK11-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i8* align 4 [[TMP7]], i64 8, i1 false)
2503 // CHECK11-NEXT:    [[TMP8:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S*
2504 // CHECK11-NEXT:    br i1 icmp eq (%struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), %struct.S* getelementptr ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2505 // CHECK11:       omp.arraycpy.body:
2506 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2507 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2508 // CHECK11-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
2509 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2510 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2511 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2)
2512 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
2513 // CHECK11:       omp.arraycpy.done1:
2514 // CHECK11-NEXT:    [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, %struct.S* nonnull align 4 dereferenceable(4) [[TMP3]])
2515 // CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
2516 // CHECK11:       copyin.not.master.end:
2517 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2518 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
2519 // CHECK11-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP10]])
2520 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
2521 // CHECK11-NEXT:    store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4
2522 // CHECK11-NEXT:    [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)
2523 // CHECK11-NEXT:    ret void
2524 //
2525 //
2526 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1
2527 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] {
2528 // CHECK11-NEXT:  entry:
2529 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2530 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2531 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
2532 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2533 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2534 // CHECK11-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
2535 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
2536 // CHECK11-NEXT:    [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64
2537 // CHECK11-NEXT:    [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ4mainE5t_var to i64)
2538 // CHECK11-NEXT:    br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
2539 // CHECK11:       copyin.not.master:
2540 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
2541 // CHECK11-NEXT:    store i32 [[TMP3]], i32* @_ZZ4mainE5t_var, align 4
2542 // CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
2543 // CHECK11:       copyin.not.master.end:
2544 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2545 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2546 // CHECK11-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
2547 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
2548 // CHECK11-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP6]], 1
2549 // CHECK11-NEXT:    store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4
2550 // CHECK11-NEXT:    ret void
2551 //
2552 //
2553 // CHECK11-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2554 // CHECK11-SAME: () #[[ATTR2]] comdat {
2555 // CHECK11-NEXT:  entry:
2556 // CHECK11-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2557 // CHECK11-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
2558 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2559 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2560 // CHECK11-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2561 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
2562 // CHECK11-NEXT:    [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8
2563 // CHECK11-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
2564 // CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]]
2565 // CHECK11:       init.check:
2566 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1)
2567 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2)
2568 // CHECK11-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor.2, i8* null, i8* @__dso_handle) #[[ATTR4]]
2569 // CHECK11-NEXT:    store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8
2570 // CHECK11-NEXT:    br label [[INIT_END]]
2571 // CHECK11:       init.end:
2572 // CHECK11-NEXT:    [[TMP2:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8
2573 // CHECK11-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0
2574 // CHECK11-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]]
2575 // CHECK11:       init.check2:
2576 // CHECK11-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3)
2577 // CHECK11-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR4]]
2578 // CHECK11-NEXT:    store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8
2579 // CHECK11-NEXT:    br label [[INIT_END3]]
2580 // CHECK11:       init.end3:
2581 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var, [2 x i32]* @_ZZ5tmainIiET_vE3vec, [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, %struct.S.0* @_ZZ5tmainIiET_vE3var)
2582 // CHECK11-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var)
2583 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2584 // CHECK11-NEXT:    ret i32 0
2585 //
2586 //
2587 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
2588 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2589 // CHECK11-NEXT:  entry:
2590 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2591 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2592 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2593 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2594 // CHECK11-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
2595 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
2596 // CHECK11-NEXT:    store float [[CONV]], float* [[F]], align 4
2597 // CHECK11-NEXT:    ret void
2598 //
2599 //
2600 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
2601 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2602 // CHECK11-NEXT:  entry:
2603 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2604 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2605 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2606 // CHECK11-NEXT:    ret void
2607 //
2608 //
2609 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
2610 // CHECK11-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2611 // CHECK11-NEXT:  entry:
2612 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2613 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2614 // CHECK11-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2615 // CHECK11-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
2616 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2617 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
2618 // CHECK11-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2619 // CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
2620 // CHECK11-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
2621 // CHECK11-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
2622 // CHECK11-NEXT:    store float [[ADD]], float* [[F]], align 4
2623 // CHECK11-NEXT:    ret void
2624 //
2625 //
2626 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
2627 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2628 // CHECK11-NEXT:  entry:
2629 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2630 // CHECK11-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2631 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2632 // CHECK11-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
2633 // CHECK11-NEXT:    ret void
2634 //
2635 //
2636 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
2637 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
2638 // CHECK11-NEXT:  entry:
2639 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2640 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8
2641 // CHECK11-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2642 // CHECK11-NEXT:    store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8
2643 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2644 // CHECK11-NEXT:    ret %struct.S.0* [[THIS1]]
2645 //
2646 //
2647 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
2648 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2649 // CHECK11-NEXT:  entry:
2650 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2651 // CHECK11-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2652 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2653 // CHECK11-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2654 // CHECK11-NEXT:    ret void
2655 //
2656 //
2657 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
2658 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2659 // CHECK11-NEXT:  entry:
2660 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2661 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2662 // CHECK11-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2663 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2664 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2665 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2666 // CHECK11-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
2667 // CHECK11-NEXT:    ret void
2668 //
2669 //
2670 // CHECK11-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.2
2671 // CHECK11-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {
2672 // CHECK11-NEXT:  entry:
2673 // CHECK11-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
2674 // CHECK11-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2675 // CHECK11-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2676 // CHECK11:       arraydestroy.body:
2677 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2678 // CHECK11-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2679 // CHECK11-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2680 // CHECK11-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0)
2681 // CHECK11-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2682 // CHECK11:       arraydestroy.done1:
2683 // CHECK11-NEXT:    ret void
2684 //
2685 //
2686 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3
2687 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] {
2688 // CHECK11-NEXT:  entry:
2689 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2690 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2691 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
2692 // CHECK11-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2693 // CHECK11-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
2694 // CHECK11-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
2695 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2696 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2697 // CHECK11-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
2698 // CHECK11-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2699 // CHECK11-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2700 // CHECK11-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
2701 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
2702 // CHECK11-NEXT:    [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2703 // CHECK11-NEXT:    [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
2704 // CHECK11-NEXT:    [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
2705 // CHECK11-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64
2706 // CHECK11-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64)
2707 // CHECK11-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
2708 // CHECK11:       copyin.not.master:
2709 // CHECK11-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 128
2710 // CHECK11-NEXT:    store i32 [[TMP6]], i32* @_ZZ5tmainIiET_vE5t_var, align 128
2711 // CHECK11-NEXT:    [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8*
2712 // CHECK11-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i8* align 128 [[TMP7]], i64 8, i1 false)
2713 // CHECK11-NEXT:    [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0*
2714 // CHECK11-NEXT:    br i1 icmp eq (%struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), %struct.S.0* getelementptr ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2715 // CHECK11:       omp.arraycpy.body:
2716 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2717 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2718 // CHECK11-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
2719 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2720 // CHECK11-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2721 // CHECK11-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S_0]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2)
2722 // CHECK11-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
2723 // CHECK11:       omp.arraycpy.done1:
2724 // CHECK11-NEXT:    [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]])
2725 // CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
2726 // CHECK11:       copyin.not.master.end:
2727 // CHECK11-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2728 // CHECK11-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
2729 // CHECK11-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
2730 // CHECK11-NEXT:    [[TMP11:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
2731 // CHECK11-NEXT:    store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128
2732 // CHECK11-NEXT:    [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)
2733 // CHECK11-NEXT:    ret void
2734 //
2735 //
2736 // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..4
2737 // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] {
2738 // CHECK11-NEXT:  entry:
2739 // CHECK11-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2740 // CHECK11-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2741 // CHECK11-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
2742 // CHECK11-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2743 // CHECK11-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2744 // CHECK11-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
2745 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
2746 // CHECK11-NEXT:    [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64
2747 // CHECK11-NEXT:    [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64)
2748 // CHECK11-NEXT:    br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
2749 // CHECK11:       copyin.not.master:
2750 // CHECK11-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128
2751 // CHECK11-NEXT:    store i32 [[TMP3]], i32* @_ZZ5tmainIiET_vE5t_var, align 128
2752 // CHECK11-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
2753 // CHECK11:       copyin.not.master.end:
2754 // CHECK11-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2755 // CHECK11-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2756 // CHECK11-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
2757 // CHECK11-NEXT:    ret void
2758 //
2759 //
2760 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
2761 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2762 // CHECK11-NEXT:  entry:
2763 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2764 // CHECK11-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2765 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2766 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2767 // CHECK11-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
2768 // CHECK11-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
2769 // CHECK11-NEXT:    ret void
2770 //
2771 //
2772 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
2773 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2774 // CHECK11-NEXT:  entry:
2775 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2776 // CHECK11-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2777 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2778 // CHECK11-NEXT:    ret void
2779 //
2780 //
2781 // CHECK11-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
2782 // CHECK11-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2783 // CHECK11-NEXT:  entry:
2784 // CHECK11-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
2785 // CHECK11-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
2786 // CHECK11-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
2787 // CHECK11-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
2788 // CHECK11-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
2789 // CHECK11-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
2790 // CHECK11-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
2791 // CHECK11-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
2792 // CHECK11-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
2793 // CHECK11-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
2794 // CHECK11-NEXT:    ret void
2795 //
2796 //
2797 // CHECK11-LABEL: define {{[^@]+}}@_ZTW1g
2798 // CHECK11-SAME: () #[[ATTR8:[0-9]+]] comdat {
2799 // CHECK11-NEXT:    ret i32* @g
2800 //
2801 //
2802 // CHECK12-LABEL: define {{[^@]+}}@main
2803 // CHECK12-SAME: () #[[ATTR0:[0-9]+]] {
2804 // CHECK12-NEXT:  entry:
2805 // CHECK12-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
2806 // CHECK12-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
2807 // CHECK12-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
2808 // CHECK12-NEXT:    store i32 0, i32* [[RETVAL]], align 4
2809 // CHECK12-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
2810 // CHECK12-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2811 // CHECK12-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2812 // CHECK12-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4:[0-9]+]]
2813 // CHECK12-NEXT:    [[TMP0:%.*]] = load i8, i8* @_ZGVZ4mainE5s_arr, align 1
2814 // CHECK12-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
2815 // CHECK12-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
2816 // CHECK12:       init.check:
2817 // CHECK12-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00)
2818 // CHECK12-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00)
2819 // CHECK12-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR4]]
2820 // CHECK12-NEXT:    store i8 1, i8* @_ZGVZ4mainE5s_arr, align 1
2821 // CHECK12-NEXT:    br label [[INIT_END]]
2822 // CHECK12:       init.end:
2823 // CHECK12-NEXT:    [[TMP2:%.*]] = load i8, i8* @_ZGVZ4mainE3var, align 1
2824 // CHECK12-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0
2825 // CHECK12-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]]
2826 // CHECK12:       init.check2:
2827 // CHECK12-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00)
2828 // CHECK12-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR4]]
2829 // CHECK12-NEXT:    store i8 1, i8* @_ZGVZ4mainE3var, align 1
2830 // CHECK12-NEXT:    br label [[INIT_END3]]
2831 // CHECK12:       init.end3:
2832 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S]*, %struct.S*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var, [2 x i32]* @_ZZ4mainE3vec, [2 x %struct.S]* @_ZZ4mainE5s_arr, %struct.S* @_ZZ4mainE3var)
2833 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* @_ZZ4mainE5t_var)
2834 // CHECK12-NEXT:    [[CALL4:%.*]] = call i32 @_Z5tmainIiET_v()
2835 // CHECK12-NEXT:    store i32 [[CALL4]], i32* [[RETVAL]], align 4
2836 // CHECK12-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
2837 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32, i32* [[RETVAL]], align 4
2838 // CHECK12-NEXT:    ret i32 [[TMP4]]
2839 //
2840 //
2841 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
2842 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
2843 // CHECK12-NEXT:  entry:
2844 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2845 // CHECK12-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2846 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2847 // CHECK12-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
2848 // CHECK12-NEXT:    ret void
2849 //
2850 //
2851 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
2852 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
2853 // CHECK12-NEXT:  entry:
2854 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2855 // CHECK12-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S*, align 8
2856 // CHECK12-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2857 // CHECK12-NEXT:    store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
2858 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2859 // CHECK12-NEXT:    ret %struct.S* [[THIS1]]
2860 //
2861 //
2862 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
2863 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2864 // CHECK12-NEXT:  entry:
2865 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2866 // CHECK12-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2867 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2868 // CHECK12-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
2869 // CHECK12-NEXT:    ret void
2870 //
2871 //
2872 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
2873 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
2874 // CHECK12-NEXT:  entry:
2875 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
2876 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
2877 // CHECK12-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
2878 // CHECK12-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
2879 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
2880 // CHECK12-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
2881 // CHECK12-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
2882 // CHECK12-NEXT:    ret void
2883 //
2884 //
2885 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
2886 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" {
2887 // CHECK12-NEXT:  entry:
2888 // CHECK12-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
2889 // CHECK12-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
2890 // CHECK12-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
2891 // CHECK12:       arraydestroy.body:
2892 // CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
2893 // CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
2894 // CHECK12-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
2895 // CHECK12-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0)
2896 // CHECK12-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
2897 // CHECK12:       arraydestroy.done1:
2898 // CHECK12-NEXT:    ret void
2899 //
2900 //
2901 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined.
2902 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5:[0-9]+]] {
2903 // CHECK12-NEXT:  entry:
2904 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2905 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2906 // CHECK12-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
2907 // CHECK12-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
2908 // CHECK12-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S]*, align 8
2909 // CHECK12-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S*, align 8
2910 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2911 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2912 // CHECK12-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
2913 // CHECK12-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
2914 // CHECK12-NEXT:    store [2 x %struct.S]* [[S_ARR]], [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2915 // CHECK12-NEXT:    store %struct.S* [[VAR]], %struct.S** [[VAR_ADDR]], align 8
2916 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
2917 // CHECK12-NEXT:    [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
2918 // CHECK12-NEXT:    [[TMP2:%.*]] = load [2 x %struct.S]*, [2 x %struct.S]** [[S_ARR_ADDR]], align 8
2919 // CHECK12-NEXT:    [[TMP3:%.*]] = load %struct.S*, %struct.S** [[VAR_ADDR]], align 8
2920 // CHECK12-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64
2921 // CHECK12-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ4mainE5t_var to i64)
2922 // CHECK12-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
2923 // CHECK12:       copyin.not.master:
2924 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 4
2925 // CHECK12-NEXT:    store i32 [[TMP6]], i32* @_ZZ4mainE5t_var, align 4
2926 // CHECK12-NEXT:    [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8*
2927 // CHECK12-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x i32]* @_ZZ4mainE3vec to i8*), i8* align 4 [[TMP7]], i64 8, i1 false)
2928 // CHECK12-NEXT:    [[TMP8:%.*]] = bitcast [2 x %struct.S]* [[TMP2]] to %struct.S*
2929 // CHECK12-NEXT:    br i1 icmp eq (%struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), %struct.S* getelementptr ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
2930 // CHECK12:       omp.arraycpy.body:
2931 // CHECK12-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2932 // CHECK12-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
2933 // CHECK12-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
2934 // CHECK12-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
2935 // CHECK12-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S]], %struct.S* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
2936 // CHECK12-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2)
2937 // CHECK12-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
2938 // CHECK12:       omp.arraycpy.done1:
2939 // CHECK12-NEXT:    [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, %struct.S* nonnull align 4 dereferenceable(4) [[TMP3]])
2940 // CHECK12-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
2941 // CHECK12:       copyin.not.master.end:
2942 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2943 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
2944 // CHECK12-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP10]])
2945 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
2946 // CHECK12-NEXT:    store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4
2947 // CHECK12-NEXT:    [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)
2948 // CHECK12-NEXT:    ret void
2949 //
2950 //
2951 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1
2952 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] {
2953 // CHECK12-NEXT:  entry:
2954 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
2955 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
2956 // CHECK12-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
2957 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
2958 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
2959 // CHECK12-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
2960 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
2961 // CHECK12-NEXT:    [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64
2962 // CHECK12-NEXT:    [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ4mainE5t_var to i64)
2963 // CHECK12-NEXT:    br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
2964 // CHECK12:       copyin.not.master:
2965 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 4
2966 // CHECK12-NEXT:    store i32 [[TMP3]], i32* @_ZZ4mainE5t_var, align 4
2967 // CHECK12-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
2968 // CHECK12:       copyin.not.master.end:
2969 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
2970 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
2971 // CHECK12-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
2972 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
2973 // CHECK12-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP6]], 1
2974 // CHECK12-NEXT:    store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4
2975 // CHECK12-NEXT:    ret void
2976 //
2977 //
2978 // CHECK12-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
2979 // CHECK12-SAME: () #[[ATTR2]] comdat {
2980 // CHECK12-NEXT:  entry:
2981 // CHECK12-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
2982 // CHECK12-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
2983 // CHECK12-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
2984 // CHECK12-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2985 // CHECK12-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
2986 // CHECK12-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR4]]
2987 // CHECK12-NEXT:    [[TMP0:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8
2988 // CHECK12-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
2989 // CHECK12-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]]
2990 // CHECK12:       init.check:
2991 // CHECK12-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1)
2992 // CHECK12-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2)
2993 // CHECK12-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor.2, i8* null, i8* @__dso_handle) #[[ATTR4]]
2994 // CHECK12-NEXT:    store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*), align 8
2995 // CHECK12-NEXT:    br label [[INIT_END]]
2996 // CHECK12:       init.end:
2997 // CHECK12-NEXT:    [[TMP2:%.*]] = load i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8
2998 // CHECK12-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP2]], 0
2999 // CHECK12-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END3:%.*]], !prof [[PROF2]]
3000 // CHECK12:       init.check2:
3001 // CHECK12-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3)
3002 // CHECK12-NEXT:    [[TMP3:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR4]]
3003 // CHECK12-NEXT:    store i8 1, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*), align 8
3004 // CHECK12-NEXT:    br label [[INIT_END3]]
3005 // CHECK12:       init.end3:
3006 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*, [2 x i32]*, [2 x %struct.S.0]*, %struct.S.0*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var, [2 x i32]* @_ZZ5tmainIiET_vE3vec, [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, %struct.S.0* @_ZZ5tmainIiET_vE3var)
3007 // CHECK12-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..4 to void (i32*, i32*, ...)*), i32* @_ZZ5tmainIiET_vE5t_var)
3008 // CHECK12-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR4]]
3009 // CHECK12-NEXT:    ret i32 0
3010 //
3011 //
3012 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3013 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3014 // CHECK12-NEXT:  entry:
3015 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3016 // CHECK12-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3017 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3018 // CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3019 // CHECK12-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
3020 // CHECK12-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3021 // CHECK12-NEXT:    store float [[CONV]], float* [[F]], align 4
3022 // CHECK12-NEXT:    ret void
3023 //
3024 //
3025 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3026 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3027 // CHECK12-NEXT:  entry:
3028 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3029 // CHECK12-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3030 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3031 // CHECK12-NEXT:    ret void
3032 //
3033 //
3034 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3035 // CHECK12-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3036 // CHECK12-NEXT:  entry:
3037 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3038 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3039 // CHECK12-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3040 // CHECK12-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
3041 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3042 // CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3043 // CHECK12-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3044 // CHECK12-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
3045 // CHECK12-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3046 // CHECK12-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3047 // CHECK12-NEXT:    store float [[ADD]], float* [[F]], align 4
3048 // CHECK12-NEXT:    ret void
3049 //
3050 //
3051 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3052 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3053 // CHECK12-NEXT:  entry:
3054 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3055 // CHECK12-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3056 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3057 // CHECK12-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3058 // CHECK12-NEXT:    ret void
3059 //
3060 //
3061 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
3062 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
3063 // CHECK12-NEXT:  entry:
3064 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3065 // CHECK12-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8
3066 // CHECK12-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3067 // CHECK12-NEXT:    store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8
3068 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3069 // CHECK12-NEXT:    ret %struct.S.0* [[THIS1]]
3070 //
3071 //
3072 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3073 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3074 // CHECK12-NEXT:  entry:
3075 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3076 // CHECK12-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3077 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3078 // CHECK12-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR4]]
3079 // CHECK12-NEXT:    ret void
3080 //
3081 //
3082 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3083 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3084 // CHECK12-NEXT:  entry:
3085 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3086 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3087 // CHECK12-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3088 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3089 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3090 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3091 // CHECK12-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
3092 // CHECK12-NEXT:    ret void
3093 //
3094 //
3095 // CHECK12-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.2
3096 // CHECK12-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3]] section ".text.startup" {
3097 // CHECK12-NEXT:  entry:
3098 // CHECK12-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
3099 // CHECK12-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3100 // CHECK12-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3101 // CHECK12:       arraydestroy.body:
3102 // CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3103 // CHECK12-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3104 // CHECK12-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR4]]
3105 // CHECK12-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0)
3106 // CHECK12-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3107 // CHECK12:       arraydestroy.done1:
3108 // CHECK12-NEXT:    ret void
3109 //
3110 //
3111 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3
3112 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[VEC:%.*]], [2 x %struct.S.0]* nonnull align 4 dereferenceable(8) [[S_ARR:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[VAR:%.*]]) #[[ATTR5]] {
3113 // CHECK12-NEXT:  entry:
3114 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3115 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3116 // CHECK12-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
3117 // CHECK12-NEXT:    [[VEC_ADDR:%.*]] = alloca [2 x i32]*, align 8
3118 // CHECK12-NEXT:    [[S_ARR_ADDR:%.*]] = alloca [2 x %struct.S.0]*, align 8
3119 // CHECK12-NEXT:    [[VAR_ADDR:%.*]] = alloca %struct.S.0*, align 8
3120 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3121 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3122 // CHECK12-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
3123 // CHECK12-NEXT:    store [2 x i32]* [[VEC]], [2 x i32]** [[VEC_ADDR]], align 8
3124 // CHECK12-NEXT:    store [2 x %struct.S.0]* [[S_ARR]], [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3125 // CHECK12-NEXT:    store %struct.S.0* [[VAR]], %struct.S.0** [[VAR_ADDR]], align 8
3126 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
3127 // CHECK12-NEXT:    [[TMP1:%.*]] = load [2 x i32]*, [2 x i32]** [[VEC_ADDR]], align 8
3128 // CHECK12-NEXT:    [[TMP2:%.*]] = load [2 x %struct.S.0]*, [2 x %struct.S.0]** [[S_ARR_ADDR]], align 8
3129 // CHECK12-NEXT:    [[TMP3:%.*]] = load %struct.S.0*, %struct.S.0** [[VAR_ADDR]], align 8
3130 // CHECK12-NEXT:    [[TMP4:%.*]] = ptrtoint i32* [[TMP0]] to i64
3131 // CHECK12-NEXT:    [[TMP5:%.*]] = icmp ne i64 [[TMP4]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64)
3132 // CHECK12-NEXT:    br i1 [[TMP5]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
3133 // CHECK12:       copyin.not.master:
3134 // CHECK12-NEXT:    [[TMP6:%.*]] = load i32, i32* [[TMP0]], align 128
3135 // CHECK12-NEXT:    store i32 [[TMP6]], i32* @_ZZ5tmainIiET_vE5t_var, align 128
3136 // CHECK12-NEXT:    [[TMP7:%.*]] = bitcast [2 x i32]* [[TMP1]] to i8*
3137 // CHECK12-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 128 bitcast ([2 x i32]* @_ZZ5tmainIiET_vE3vec to i8*), i8* align 128 [[TMP7]], i64 8, i1 false)
3138 // CHECK12-NEXT:    [[TMP8:%.*]] = bitcast [2 x %struct.S.0]* [[TMP2]] to %struct.S.0*
3139 // CHECK12-NEXT:    br i1 icmp eq (%struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), %struct.S.0* getelementptr ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3140 // CHECK12:       omp.arraycpy.body:
3141 // CHECK12-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.S.0* [ [[TMP8]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3142 // CHECK12-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3143 // CHECK12-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
3144 // CHECK12-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3145 // CHECK12-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_S_0]], %struct.S.0* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3146 // CHECK12-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.S.0* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_S_0]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2)
3147 // CHECK12-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
3148 // CHECK12:       omp.arraycpy.done1:
3149 // CHECK12-NEXT:    [[CALL2:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP3]])
3150 // CHECK12-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
3151 // CHECK12:       copyin.not.master.end:
3152 // CHECK12-NEXT:    [[TMP9:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3153 // CHECK12-NEXT:    [[TMP10:%.*]] = load i32, i32* [[TMP9]], align 4
3154 // CHECK12-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP10]])
3155 // CHECK12-NEXT:    [[TMP11:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
3156 // CHECK12-NEXT:    store i32 [[TMP11]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128
3157 // CHECK12-NEXT:    [[CALL3:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)
3158 // CHECK12-NEXT:    ret void
3159 //
3160 //
3161 // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..4
3162 // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T_VAR:%.*]]) #[[ATTR5]] {
3163 // CHECK12-NEXT:  entry:
3164 // CHECK12-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3165 // CHECK12-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3166 // CHECK12-NEXT:    [[T_VAR_ADDR:%.*]] = alloca i32*, align 8
3167 // CHECK12-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3168 // CHECK12-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3169 // CHECK12-NEXT:    store i32* [[T_VAR]], i32** [[T_VAR_ADDR]], align 8
3170 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_VAR_ADDR]], align 8
3171 // CHECK12-NEXT:    [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64
3172 // CHECK12-NEXT:    [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @_ZZ5tmainIiET_vE5t_var to i64)
3173 // CHECK12-NEXT:    br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
3174 // CHECK12:       copyin.not.master:
3175 // CHECK12-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128
3176 // CHECK12-NEXT:    store i32 [[TMP3]], i32* @_ZZ5tmainIiET_vE5t_var, align 128
3177 // CHECK12-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
3178 // CHECK12:       copyin.not.master.end:
3179 // CHECK12-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3180 // CHECK12-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3181 // CHECK12-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1]], i32 [[TMP5]])
3182 // CHECK12-NEXT:    ret void
3183 //
3184 //
3185 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3186 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3187 // CHECK12-NEXT:  entry:
3188 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3189 // CHECK12-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3190 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3191 // CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3192 // CHECK12-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
3193 // CHECK12-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
3194 // CHECK12-NEXT:    ret void
3195 //
3196 //
3197 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3198 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3199 // CHECK12-NEXT:  entry:
3200 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3201 // CHECK12-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3202 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3203 // CHECK12-NEXT:    ret void
3204 //
3205 //
3206 // CHECK12-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3207 // CHECK12-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3208 // CHECK12-NEXT:  entry:
3209 // CHECK12-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3210 // CHECK12-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3211 // CHECK12-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3212 // CHECK12-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3213 // CHECK12-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3214 // CHECK12-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3215 // CHECK12-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3216 // CHECK12-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
3217 // CHECK12-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3218 // CHECK12-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
3219 // CHECK12-NEXT:    ret void
3220 //
3221 //
3222 // CHECK12-LABEL: define {{[^@]+}}@_ZTW1g
3223 // CHECK12-SAME: () #[[ATTR8:[0-9]+]] comdat {
3224 // CHECK12-NEXT:    ret i32* @g
3225 //
3226 //
3227 // CHECK13-LABEL: define {{[^@]+}}@main
3228 // CHECK13-SAME: () #[[ATTR0:[0-9]+]] {
3229 // CHECK13-NEXT:  entry:
3230 // CHECK13-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3231 // CHECK13-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
3232 // CHECK13-NEXT:    store i32 0, i32* [[RETVAL]], align 4
3233 // CHECK13-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
3234 // CHECK13-NEXT:    ret i32 0
3235 //
3236 //
3237 // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined.
3238 // CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR2:[0-9]+]] {
3239 // CHECK13-NEXT:  entry:
3240 // CHECK13-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3241 // CHECK13-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3242 // CHECK13-NEXT:    [[G_ADDR:%.*]] = alloca i32*, align 8
3243 // CHECK13-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON_0:%.*]], align 1
3244 // CHECK13-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3245 // CHECK13-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3246 // CHECK13-NEXT:    store i32* [[G]], i32** [[G_ADDR]], align 8
3247 // CHECK13-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
3248 // CHECK13-NEXT:    [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64
3249 // CHECK13-NEXT:    [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @g to i64)
3250 // CHECK13-NEXT:    br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
3251 // CHECK13:       copyin.not.master:
3252 // CHECK13-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128
3253 // CHECK13-NEXT:    store volatile i32 [[TMP3]], i32* @g, align 128
3254 // CHECK13-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
3255 // CHECK13:       copyin.not.master.end:
3256 // CHECK13-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3257 // CHECK13-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3258 // CHECK13-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]])
3259 // CHECK13-NEXT:    store volatile i32 1, i32* @g, align 128
3260 // CHECK13-NEXT:    call void @"_ZZZ4mainENK3$_0clEvENKUlvE_clEv"(%class.anon.0* nonnull align 1 dereferenceable(1) [[REF_TMP]])
3261 // CHECK13-NEXT:    ret void
3262 //
3263 //
3264 // CHECK13-LABEL: define {{[^@]+}}@_ZTW1g
3265 // CHECK13-SAME: () #[[ATTR5:[0-9]+]] comdat {
3266 // CHECK13-NEXT:    ret i32* @g
3267 //
3268 //
3269 // CHECK14-LABEL: define {{[^@]+}}@main
3270 // CHECK14-SAME: () #[[ATTR1:[0-9]+]] {
3271 // CHECK14-NEXT:  entry:
3272 // CHECK14-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3273 // CHECK14-NEXT:    store i32 0, i32* [[RETVAL]], align 4
3274 // CHECK14-NEXT:    [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8
3275 // CHECK14-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
3276 // CHECK14-NEXT:    call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*))
3277 // CHECK14-NEXT:    ret i32 0
3278 //
3279 //
3280 // CHECK14-LABEL: define {{[^@]+}}@__main_block_invoke
3281 // CHECK14-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
3282 // CHECK14-NEXT:  entry:
3283 // CHECK14-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
3284 // CHECK14-NEXT:    [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
3285 // CHECK14-NEXT:    store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
3286 // CHECK14-NEXT:    [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
3287 // CHECK14-NEXT:    store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
3288 // CHECK14-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32* @g)
3289 // CHECK14-NEXT:    ret void
3290 //
3291 //
3292 // CHECK14-LABEL: define {{[^@]+}}@.omp_outlined.
3293 // CHECK14-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[G:%.*]]) #[[ATTR3:[0-9]+]] {
3294 // CHECK14-NEXT:  entry:
3295 // CHECK14-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3296 // CHECK14-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3297 // CHECK14-NEXT:    [[G_ADDR:%.*]] = alloca i32*, align 8
3298 // CHECK14-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3299 // CHECK14-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3300 // CHECK14-NEXT:    store i32* [[G]], i32** [[G_ADDR]], align 8
3301 // CHECK14-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[G_ADDR]], align 8
3302 // CHECK14-NEXT:    [[TMP1:%.*]] = ptrtoint i32* [[TMP0]] to i64
3303 // CHECK14-NEXT:    [[TMP2:%.*]] = icmp ne i64 [[TMP1]], ptrtoint (i32* @g to i64)
3304 // CHECK14-NEXT:    br i1 [[TMP2]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
3305 // CHECK14:       copyin.not.master:
3306 // CHECK14-NEXT:    [[TMP3:%.*]] = load i32, i32* [[TMP0]], align 128
3307 // CHECK14-NEXT:    store volatile i32 [[TMP3]], i32* @g, align 128
3308 // CHECK14-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
3309 // CHECK14:       copyin.not.master.end:
3310 // CHECK14-NEXT:    [[TMP4:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3311 // CHECK14-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP4]], align 4
3312 // CHECK14-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP5]])
3313 // CHECK14-NEXT:    store volatile i32 1, i32* @g, align 128
3314 // CHECK14-NEXT:    [[TMP6:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8
3315 // CHECK14-NEXT:    [[TMP7:%.*]] = bitcast i8* [[TMP6]] to void (i8*)*
3316 // CHECK14-NEXT:    call void [[TMP7]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*))
3317 // CHECK14-NEXT:    ret void
3318 //
3319 //
3320 // CHECK14-LABEL: define {{[^@]+}}@g_block_invoke
3321 // CHECK14-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
3322 // CHECK14-NEXT:  entry:
3323 // CHECK14-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
3324 // CHECK14-NEXT:    [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
3325 // CHECK14-NEXT:    store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
3326 // CHECK14-NEXT:    [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
3327 // CHECK14-NEXT:    store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
3328 // CHECK14-NEXT:    store volatile i32 2, i32* @g, align 128
3329 // CHECK14-NEXT:    ret void
3330 //
3331 //
3332 // CHECK14-LABEL: define {{[^@]+}}@_ZTW1g
3333 // CHECK14-SAME: () #[[ATTR6:[0-9]+]] comdat {
3334 // CHECK14-NEXT:    ret i32* @g
3335 //
3336 //
3337 // CHECK15-LABEL: define {{[^@]+}}@_Z10array_funcv
3338 // CHECK15-SAME: () #[[ATTR0:[0-9]+]] {
3339 // CHECK15-NEXT:  entry:
3340 // CHECK15-NEXT:    [[TMP0:%.*]] = load i8, i8* @_ZGVZ10array_funcvE1s, align 1
3341 // CHECK15-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3342 // CHECK15-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
3343 // CHECK15:       init.check:
3344 // CHECK15-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
3345 // CHECK15:       arrayctor.loop:
3346 // CHECK15-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT_CHECK]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
3347 // CHECK15-NEXT:    call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])
3348 // CHECK15-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1
3349 // CHECK15-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2)
3350 // CHECK15-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
3351 // CHECK15:       arrayctor.cont:
3352 // CHECK15-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_thread_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3:[0-9]+]]
3353 // CHECK15-NEXT:    store i8 1, i8* @_ZGVZ10array_funcvE1s, align 1
3354 // CHECK15-NEXT:    br label [[INIT_END]]
3355 // CHECK15:       init.end:
3356 // CHECK15-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, [2 x i32]*, [2 x %struct.St]*)* @.omp_outlined. to void (i32*, i32*, ...)*), [2 x i32]* @_ZZ10array_funcvE1a, [2 x %struct.St]* @_ZZ10array_funcvE1s)
3357 // CHECK15-NEXT:    ret void
3358 //
3359 //
3360 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC1Ev
3361 // CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3362 // CHECK15-NEXT:  entry:
3363 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
3364 // CHECK15-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
3365 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
3366 // CHECK15-NEXT:    call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
3367 // CHECK15-NEXT:    ret void
3368 //
3369 //
3370 // CHECK15-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3371 // CHECK15-SAME: (i8* [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] section ".text.startup" {
3372 // CHECK15-NEXT:  entry:
3373 // CHECK15-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
3374 // CHECK15-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3375 // CHECK15-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3376 // CHECK15:       arraydestroy.body:
3377 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3378 // CHECK15-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3379 // CHECK15-NEXT:    call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
3380 // CHECK15-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0)
3381 // CHECK15-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3382 // CHECK15:       arraydestroy.done1:
3383 // CHECK15-NEXT:    ret void
3384 //
3385 //
3386 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD1Ev
3387 // CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3388 // CHECK15-NEXT:  entry:
3389 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
3390 // CHECK15-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
3391 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
3392 // CHECK15-NEXT:    call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR3]]
3393 // CHECK15-NEXT:    ret void
3394 //
3395 //
3396 // CHECK15-LABEL: define {{[^@]+}}@.omp_outlined.
3397 // CHECK15-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], [2 x i32]* nonnull align 4 dereferenceable(8) [[A:%.*]], [2 x %struct.St]* nonnull align 4 dereferenceable(16) [[S:%.*]]) #[[ATTR4:[0-9]+]] {
3398 // CHECK15-NEXT:  entry:
3399 // CHECK15-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3400 // CHECK15-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3401 // CHECK15-NEXT:    [[A_ADDR:%.*]] = alloca [2 x i32]*, align 8
3402 // CHECK15-NEXT:    [[S_ADDR:%.*]] = alloca [2 x %struct.St]*, align 8
3403 // CHECK15-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3404 // CHECK15-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3405 // CHECK15-NEXT:    store [2 x i32]* [[A]], [2 x i32]** [[A_ADDR]], align 8
3406 // CHECK15-NEXT:    store [2 x %struct.St]* [[S]], [2 x %struct.St]** [[S_ADDR]], align 8
3407 // CHECK15-NEXT:    [[TMP0:%.*]] = load [2 x i32]*, [2 x i32]** [[A_ADDR]], align 8
3408 // CHECK15-NEXT:    [[TMP1:%.*]] = load [2 x %struct.St]*, [2 x %struct.St]** [[S_ADDR]], align 8
3409 // CHECK15-NEXT:    [[TMP2:%.*]] = ptrtoint [2 x i32]* [[TMP0]] to i64
3410 // CHECK15-NEXT:    [[TMP3:%.*]] = icmp ne i64 [[TMP2]], ptrtoint ([2 x i32]* @_ZZ10array_funcvE1a to i64)
3411 // CHECK15-NEXT:    br i1 [[TMP3]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
3412 // CHECK15:       copyin.not.master:
3413 // CHECK15-NEXT:    [[TMP4:%.*]] = bitcast [2 x i32]* [[TMP0]] to i8*
3414 // CHECK15-NEXT:    call void @llvm.memcpy.p0i8.p0i8.i64(i8* align 4 bitcast ([2 x i32]* @_ZZ10array_funcvE1a to i8*), i8* align 4 [[TMP4]], i64 8, i1 false)
3415 // CHECK15-NEXT:    [[TMP5:%.*]] = bitcast [2 x %struct.St]* [[TMP1]] to %struct.St*
3416 // CHECK15-NEXT:    br i1 icmp eq (%struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), %struct.St* getelementptr ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2)), label [[OMP_ARRAYCPY_DONE1:%.*]], label [[OMP_ARRAYCPY_BODY:%.*]]
3417 // CHECK15:       omp.arraycpy.body:
3418 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRCELEMENTPAST:%.*]] = phi %struct.St* [ [[TMP5]], [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_SRC_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3419 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DESTELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[COPYIN_NOT_MASTER]] ], [ [[OMP_ARRAYCPY_DEST_ELEMENT:%.*]], [[OMP_ARRAYCPY_BODY]] ]
3420 // CHECK15-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(8) %struct.St* @_ZN2StaSERKS_(%struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_DESTELEMENTPAST]], %struct.St* nonnull align 4 dereferenceable(8) [[OMP_ARRAYCPY_SRCELEMENTPAST]])
3421 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DEST_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_DESTELEMENTPAST]], i32 1
3422 // CHECK15-NEXT:    [[OMP_ARRAYCPY_SRC_ELEMENT]] = getelementptr [[STRUCT_ST]], %struct.St* [[OMP_ARRAYCPY_SRCELEMENTPAST]], i32 1
3423 // CHECK15-NEXT:    [[OMP_ARRAYCPY_DONE:%.*]] = icmp eq %struct.St* [[OMP_ARRAYCPY_DEST_ELEMENT]], getelementptr ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2)
3424 // CHECK15-NEXT:    br i1 [[OMP_ARRAYCPY_DONE]], label [[OMP_ARRAYCPY_DONE1]], label [[OMP_ARRAYCPY_BODY]]
3425 // CHECK15:       omp.arraycpy.done1:
3426 // CHECK15-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
3427 // CHECK15:       copyin.not.master.end:
3428 // CHECK15-NEXT:    [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3429 // CHECK15-NEXT:    [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
3430 // CHECK15-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]])
3431 // CHECK15-NEXT:    ret void
3432 //
3433 //
3434 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StaSERKS_
3435 // CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]], %struct.St* nonnull align 4 dereferenceable(8) [[TMP0:%.*]]) #[[ATTR0]] comdat align 2 {
3436 // CHECK15-NEXT:  entry:
3437 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
3438 // CHECK15-NEXT:    [[DOTADDR:%.*]] = alloca %struct.St*, align 8
3439 // CHECK15-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
3440 // CHECK15-NEXT:    store %struct.St* [[TMP0]], %struct.St** [[DOTADDR]], align 8
3441 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
3442 // CHECK15-NEXT:    ret %struct.St* [[THIS1]]
3443 //
3444 //
3445 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StC2Ev
3446 // CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3447 // CHECK15-NEXT:  entry:
3448 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
3449 // CHECK15-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
3450 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
3451 // CHECK15-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
3452 // CHECK15-NEXT:    store i32 0, i32* [[A]], align 4
3453 // CHECK15-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
3454 // CHECK15-NEXT:    store i32 0, i32* [[B]], align 4
3455 // CHECK15-NEXT:    ret void
3456 //
3457 //
3458 // CHECK15-LABEL: define {{[^@]+}}@_ZN2StD2Ev
3459 // CHECK15-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3460 // CHECK15-NEXT:  entry:
3461 // CHECK15-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
3462 // CHECK15-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
3463 // CHECK15-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
3464 // CHECK15-NEXT:    ret void
3465 //
3466 //
3467 // CHECK16-LABEL: define {{[^@]+}}@__cxx_global_var_init
3468 // CHECK16-SAME: () #[[ATTR0:[0-9]+]] section ".text.startup" {
3469 // CHECK16-NEXT:  entry:
3470 // CHECK16-NEXT:    [[CALL:%.*]] = call i32 @_Z6t_initv()
3471 // CHECK16-NEXT:    store i32 [[CALL]], i32* @t, align 4
3472 // CHECK16-NEXT:    ret void
3473 //
3474 //
3475 // CHECK16-LABEL: define {{[^@]+}}@_Z3foov
3476 // CHECK16-SAME: () #[[ATTR2:[0-9]+]] {
3477 // CHECK16-NEXT:  entry:
3478 // CHECK16-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 0, void (i32*, i32*, ...)* bitcast (void (i32*, i32*)* @.omp_outlined. to void (i32*, i32*, ...)*))
3479 // CHECK16-NEXT:    ret void
3480 //
3481 //
3482 // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined.
3483 // CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]]) #[[ATTR3:[0-9]+]] {
3484 // CHECK16-NEXT:  entry:
3485 // CHECK16-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3486 // CHECK16-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3487 // CHECK16-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3488 // CHECK16-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3489 // CHECK16-NEXT:    [[TMP0:%.*]] = call i32* @_ZTW1t()
3490 // CHECK16-NEXT:    call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB2]], i32 1, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32* [[TMP0]])
3491 // CHECK16-NEXT:    ret void
3492 //
3493 //
3494 // CHECK16-LABEL: define {{[^@]+}}@.omp_outlined..1
3495 // CHECK16-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32* nonnull align 4 dereferenceable(4) [[T:%.*]]) #[[ATTR3]] {
3496 // CHECK16-NEXT:  entry:
3497 // CHECK16-NEXT:    [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8
3498 // CHECK16-NEXT:    [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8
3499 // CHECK16-NEXT:    [[T_ADDR:%.*]] = alloca i32*, align 8
3500 // CHECK16-NEXT:    store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8
3501 // CHECK16-NEXT:    store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8
3502 // CHECK16-NEXT:    store i32* [[T]], i32** [[T_ADDR]], align 8
3503 // CHECK16-NEXT:    [[TMP0:%.*]] = load i32*, i32** [[T_ADDR]], align 8
3504 // CHECK16-NEXT:    [[TMP1:%.*]] = call i32* @_ZTW1t()
3505 // CHECK16-NEXT:    [[TMP2:%.*]] = ptrtoint i32* [[TMP0]] to i64
3506 // CHECK16-NEXT:    [[TMP3:%.*]] = ptrtoint i32* [[TMP1]] to i64
3507 // CHECK16-NEXT:    [[TMP4:%.*]] = icmp ne i64 [[TMP2]], [[TMP3]]
3508 // CHECK16-NEXT:    br i1 [[TMP4]], label [[COPYIN_NOT_MASTER:%.*]], label [[COPYIN_NOT_MASTER_END:%.*]]
3509 // CHECK16:       copyin.not.master:
3510 // CHECK16-NEXT:    [[TMP5:%.*]] = load i32, i32* [[TMP0]], align 4
3511 // CHECK16-NEXT:    store i32 [[TMP5]], i32* [[TMP1]], align 4
3512 // CHECK16-NEXT:    br label [[COPYIN_NOT_MASTER_END]]
3513 // CHECK16:       copyin.not.master.end:
3514 // CHECK16-NEXT:    [[TMP6:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8
3515 // CHECK16-NEXT:    [[TMP7:%.*]] = load i32, i32* [[TMP6]], align 4
3516 // CHECK16-NEXT:    call void @__kmpc_barrier(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP7]])
3517 // CHECK16-NEXT:    [[TMP8:%.*]] = call i32* @_ZTW1t()
3518 // CHECK16-NEXT:    [[TMP9:%.*]] = load i32, i32* [[TMP8]], align 4
3519 // CHECK16-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP9]], 1
3520 // CHECK16-NEXT:    store i32 [[INC]], i32* [[TMP8]], align 4
3521 // CHECK16-NEXT:    ret void
3522 //
3523 //
3524 // CHECK16-LABEL: define {{[^@]+}}@_ZTW1t
3525 // CHECK16-SAME: () #[[ATTR4:[0-9]+]] comdat {
3526 // CHECK16-NEXT:    call void @_ZTH1t()
3527 // CHECK16-NEXT:    ret i32* @t
3528 //
3529 //
3530 // CHECK16-LABEL: define {{[^@]+}}@__tls_init
3531 // CHECK16-SAME: () #[[ATTR0]] {
3532 // CHECK16-NEXT:  entry:
3533 // CHECK16-NEXT:    [[TMP0:%.*]] = load i8, i8* @__tls_guard, align 1
3534 // CHECK16-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3535 // CHECK16-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT:%.*]], label [[EXIT:%.*]], !prof [[PROF4:![0-9]+]]
3536 // CHECK16:       init:
3537 // CHECK16-NEXT:    store i8 1, i8* @__tls_guard, align 1
3538 // CHECK16-NEXT:    call void @__cxx_global_var_init()
3539 // CHECK16-NEXT:    br label [[EXIT]]
3540 // CHECK16:       exit:
3541 // CHECK16-NEXT:    ret void
3542 //
3543 //
3544 // CHECK17-LABEL: define {{[^@]+}}@main
3545 // CHECK17-SAME: () #[[ATTR0:[0-9]+]] {
3546 // CHECK17-NEXT:  entry:
3547 // CHECK17-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3548 // CHECK17-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3549 // CHECK17-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
3550 // CHECK17-NEXT:    store i32 0, i32* [[RETVAL]], align 4
3551 // CHECK17-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
3552 // CHECK17-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
3553 // CHECK17-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
3554 // CHECK17-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
3555 // CHECK17-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8
3556 // CHECK17-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3557 // CHECK17-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
3558 // CHECK17:       init.check:
3559 // CHECK17-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
3560 // CHECK17-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
3561 // CHECK17-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
3562 // CHECK17:       init:
3563 // CHECK17-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00)
3564 // CHECK17-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00)
3565 // CHECK17-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]]
3566 // CHECK17-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
3567 // CHECK17-NEXT:    br label [[INIT_END]]
3568 // CHECK17:       init.end:
3569 // CHECK17-NEXT:    [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8
3570 // CHECK17-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0
3571 // CHECK17-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
3572 // CHECK17:       init.check2:
3573 // CHECK17-NEXT:    [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
3574 // CHECK17-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0
3575 // CHECK17-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
3576 // CHECK17:       init4:
3577 // CHECK17-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00)
3578 // CHECK17-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
3579 // CHECK17-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
3580 // CHECK17-NEXT:    br label [[INIT_END5]]
3581 // CHECK17:       init.end5:
3582 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
3583 // CHECK17-NEXT:    store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4
3584 // CHECK17-NEXT:    [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)
3585 // CHECK17-NEXT:    [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
3586 // CHECK17-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
3587 // CHECK17-NEXT:    store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4
3588 // CHECK17-NEXT:    [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v()
3589 // CHECK17-NEXT:    store i32 [[CALL7]], i32* [[RETVAL]], align 4
3590 // CHECK17-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
3591 // CHECK17-NEXT:    [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4
3592 // CHECK17-NEXT:    ret i32 [[TMP8]]
3593 //
3594 //
3595 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3596 // CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3597 // CHECK17-NEXT:  entry:
3598 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3599 // CHECK17-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3600 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3601 // CHECK17-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3602 // CHECK17-NEXT:    ret void
3603 //
3604 //
3605 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
3606 // CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
3607 // CHECK17-NEXT:  entry:
3608 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3609 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S*, align 8
3610 // CHECK17-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3611 // CHECK17-NEXT:    store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
3612 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3613 // CHECK17-NEXT:    ret %struct.S* [[THIS1]]
3614 //
3615 //
3616 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3617 // CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3618 // CHECK17-NEXT:  entry:
3619 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3620 // CHECK17-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3621 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3622 // CHECK17-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
3623 // CHECK17-NEXT:    ret void
3624 //
3625 //
3626 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3627 // CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3628 // CHECK17-NEXT:  entry:
3629 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3630 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3631 // CHECK17-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3632 // CHECK17-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
3633 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3634 // CHECK17-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3635 // CHECK17-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3636 // CHECK17-NEXT:    ret void
3637 //
3638 //
3639 // CHECK17-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3640 // CHECK17-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" {
3641 // CHECK17-NEXT:  entry:
3642 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
3643 // CHECK17-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3644 // CHECK17-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3645 // CHECK17:       arraydestroy.body:
3646 // CHECK17-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3647 // CHECK17-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3648 // CHECK17-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
3649 // CHECK17-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0)
3650 // CHECK17-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3651 // CHECK17:       arraydestroy.done1:
3652 // CHECK17-NEXT:    ret void
3653 //
3654 //
3655 // CHECK17-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3656 // CHECK17-SAME: () #[[ATTR2]] comdat {
3657 // CHECK17-NEXT:  entry:
3658 // CHECK17-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3659 // CHECK17-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
3660 // CHECK17-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3661 // CHECK17-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
3662 // CHECK17-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
3663 // CHECK17-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]]
3664 // CHECK17-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8
3665 // CHECK17-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3666 // CHECK17-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]]
3667 // CHECK17:       init.check:
3668 // CHECK17-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
3669 // CHECK17-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
3670 // CHECK17-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
3671 // CHECK17:       init:
3672 // CHECK17-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1)
3673 // CHECK17-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2)
3674 // CHECK17-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]]
3675 // CHECK17-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
3676 // CHECK17-NEXT:    br label [[INIT_END]]
3677 // CHECK17:       init.end:
3678 // CHECK17-NEXT:    [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8
3679 // CHECK17-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0
3680 // CHECK17-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
3681 // CHECK17:       init.check2:
3682 // CHECK17-NEXT:    [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
3683 // CHECK17-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0
3684 // CHECK17-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
3685 // CHECK17:       init4:
3686 // CHECK17-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3)
3687 // CHECK17-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
3688 // CHECK17-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
3689 // CHECK17-NEXT:    br label [[INIT_END5]]
3690 // CHECK17:       init.end5:
3691 // CHECK17-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
3692 // CHECK17-NEXT:    store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128
3693 // CHECK17-NEXT:    [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)
3694 // CHECK17-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
3695 // CHECK17-NEXT:    ret i32 0
3696 //
3697 //
3698 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3699 // CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3700 // CHECK17-NEXT:  entry:
3701 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3702 // CHECK17-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3703 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3704 // CHECK17-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3705 // CHECK17-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
3706 // CHECK17-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3707 // CHECK17-NEXT:    store float [[CONV]], float* [[F]], align 4
3708 // CHECK17-NEXT:    ret void
3709 //
3710 //
3711 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
3712 // CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3713 // CHECK17-NEXT:  entry:
3714 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3715 // CHECK17-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3716 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3717 // CHECK17-NEXT:    ret void
3718 //
3719 //
3720 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
3721 // CHECK17-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3722 // CHECK17-NEXT:  entry:
3723 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3724 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3725 // CHECK17-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3726 // CHECK17-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
3727 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3728 // CHECK17-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3729 // CHECK17-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3730 // CHECK17-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
3731 // CHECK17-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
3732 // CHECK17-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
3733 // CHECK17-NEXT:    store float [[ADD]], float* [[F]], align 4
3734 // CHECK17-NEXT:    ret void
3735 //
3736 //
3737 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
3738 // CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3739 // CHECK17-NEXT:  entry:
3740 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3741 // CHECK17-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3742 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3743 // CHECK17-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
3744 // CHECK17-NEXT:    ret void
3745 //
3746 //
3747 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
3748 // CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
3749 // CHECK17-NEXT:  entry:
3750 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3751 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8
3752 // CHECK17-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3753 // CHECK17-NEXT:    store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8
3754 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3755 // CHECK17-NEXT:    ret %struct.S.0* [[THIS1]]
3756 //
3757 //
3758 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
3759 // CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3760 // CHECK17-NEXT:  entry:
3761 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3762 // CHECK17-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3763 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3764 // CHECK17-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
3765 // CHECK17-NEXT:    ret void
3766 //
3767 //
3768 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
3769 // CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3770 // CHECK17-NEXT:  entry:
3771 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3772 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3773 // CHECK17-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3774 // CHECK17-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3775 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3776 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3777 // CHECK17-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
3778 // CHECK17-NEXT:    ret void
3779 //
3780 //
3781 // CHECK17-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1
3782 // CHECK17-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
3783 // CHECK17-NEXT:  entry:
3784 // CHECK17-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
3785 // CHECK17-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3786 // CHECK17-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3787 // CHECK17:       arraydestroy.body:
3788 // CHECK17-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3789 // CHECK17-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3790 // CHECK17-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
3791 // CHECK17-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0)
3792 // CHECK17-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3793 // CHECK17:       arraydestroy.done1:
3794 // CHECK17-NEXT:    ret void
3795 //
3796 //
3797 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
3798 // CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3799 // CHECK17-NEXT:  entry:
3800 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3801 // CHECK17-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3802 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3803 // CHECK17-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3804 // CHECK17-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
3805 // CHECK17-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
3806 // CHECK17-NEXT:    ret void
3807 //
3808 //
3809 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
3810 // CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3811 // CHECK17-NEXT:  entry:
3812 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3813 // CHECK17-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3814 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3815 // CHECK17-NEXT:    ret void
3816 //
3817 //
3818 // CHECK17-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
3819 // CHECK17-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3820 // CHECK17-NEXT:  entry:
3821 // CHECK17-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
3822 // CHECK17-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
3823 // CHECK17-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
3824 // CHECK17-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
3825 // CHECK17-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
3826 // CHECK17-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
3827 // CHECK17-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
3828 // CHECK17-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
3829 // CHECK17-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
3830 // CHECK17-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
3831 // CHECK17-NEXT:    ret void
3832 //
3833 //
3834 // CHECK18-LABEL: define {{[^@]+}}@main
3835 // CHECK18-SAME: () #[[ATTR0:[0-9]+]] {
3836 // CHECK18-NEXT:  entry:
3837 // CHECK18-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
3838 // CHECK18-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S:%.*]], align 4
3839 // CHECK18-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S]], align 4
3840 // CHECK18-NEXT:    store i32 0, i32* [[RETVAL]], align 4
3841 // CHECK18-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]])
3842 // CHECK18-NEXT:    call void @_ZN1SIfEC1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
3843 // CHECK18-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]])
3844 // CHECK18-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3:[0-9]+]]
3845 // CHECK18-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE5s_arr to i8*) acquire, align 8
3846 // CHECK18-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3847 // CHECK18-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
3848 // CHECK18:       init.check:
3849 // CHECK18-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
3850 // CHECK18-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
3851 // CHECK18-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
3852 // CHECK18:       init:
3853 // CHECK18-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), float 1.000000e+00)
3854 // CHECK18-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 1), float 2.000000e+00)
3855 // CHECK18-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR3]]
3856 // CHECK18-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE5s_arr) #[[ATTR3]]
3857 // CHECK18-NEXT:    br label [[INIT_END]]
3858 // CHECK18:       init.end:
3859 // CHECK18-NEXT:    [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ4mainE3var to i8*) acquire, align 8
3860 // CHECK18-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0
3861 // CHECK18-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
3862 // CHECK18:       init.check2:
3863 // CHECK18-NEXT:    [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
3864 // CHECK18-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0
3865 // CHECK18-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
3866 // CHECK18:       init4:
3867 // CHECK18-NEXT:    call void @_ZN1SIfEC1Ef(%struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var, float 3.000000e+00)
3868 // CHECK18-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S*)* @_ZN1SIfED1Ev to void (i8*)*), i8* bitcast (%struct.S* @_ZZ4mainE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
3869 // CHECK18-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ4mainE3var) #[[ATTR3]]
3870 // CHECK18-NEXT:    br label [[INIT_END5]]
3871 // CHECK18:       init.end5:
3872 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
3873 // CHECK18-NEXT:    store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ4mainE3vec, i64 0, i64 0), align 4
3874 // CHECK18-NEXT:    [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S* @_ZN1SIfEaSERKS0_(%struct.S* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i64 0, i64 0), %struct.S* nonnull align 4 dereferenceable(4) @_ZZ4mainE3var)
3875 // CHECK18-NEXT:    [[TMP7:%.*]] = load i32, i32* @_ZZ4mainE5t_var, align 4
3876 // CHECK18-NEXT:    [[INC:%.*]] = add nsw i32 [[TMP7]], 1
3877 // CHECK18-NEXT:    store i32 [[INC]], i32* @_ZZ4mainE5t_var, align 4
3878 // CHECK18-NEXT:    [[CALL7:%.*]] = call i32 @_Z5tmainIiET_v()
3879 // CHECK18-NEXT:    store i32 [[CALL7]], i32* [[RETVAL]], align 4
3880 // CHECK18-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
3881 // CHECK18-NEXT:    [[TMP8:%.*]] = load i32, i32* [[RETVAL]], align 4
3882 // CHECK18-NEXT:    ret i32 [[TMP8]]
3883 //
3884 //
3885 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ev
3886 // CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1:[0-9]+]] comdat align 2 {
3887 // CHECK18-NEXT:  entry:
3888 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3889 // CHECK18-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3890 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3891 // CHECK18-NEXT:    call void @_ZN1SIfEC2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]])
3892 // CHECK18-NEXT:    ret void
3893 //
3894 //
3895 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEaSERKS0_
3896 // CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2:[0-9]+]] comdat align 2 {
3897 // CHECK18-NEXT:  entry:
3898 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3899 // CHECK18-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S*, align 8
3900 // CHECK18-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3901 // CHECK18-NEXT:    store %struct.S* [[TMP0]], %struct.S** [[DOTADDR]], align 8
3902 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3903 // CHECK18-NEXT:    ret %struct.S* [[THIS1]]
3904 //
3905 //
3906 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED1Ev
3907 // CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3908 // CHECK18-NEXT:  entry:
3909 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3910 // CHECK18-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3911 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3912 // CHECK18-NEXT:    call void @_ZN1SIfED2Ev(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
3913 // CHECK18-NEXT:    ret void
3914 //
3915 //
3916 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC1Ef
3917 // CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3918 // CHECK18-NEXT:  entry:
3919 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3920 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
3921 // CHECK18-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3922 // CHECK18-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
3923 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3924 // CHECK18-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
3925 // CHECK18-NEXT:    call void @_ZN1SIfEC2Ef(%struct.S* nonnull align 4 dereferenceable(4) [[THIS1]], float [[TMP0]])
3926 // CHECK18-NEXT:    ret void
3927 //
3928 //
3929 // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
3930 // CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4:[0-9]+]] section ".text.startup" {
3931 // CHECK18-NEXT:  entry:
3932 // CHECK18-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
3933 // CHECK18-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
3934 // CHECK18-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
3935 // CHECK18:       arraydestroy.body:
3936 // CHECK18-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S* [ getelementptr inbounds ([[STRUCT_S:%.*]], %struct.S* getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
3937 // CHECK18-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S]], %struct.S* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
3938 // CHECK18-NEXT:    call void @_ZN1SIfED1Ev(%struct.S* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
3939 // CHECK18-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S], [2 x %struct.S]* @_ZZ4mainE5s_arr, i32 0, i32 0)
3940 // CHECK18-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
3941 // CHECK18:       arraydestroy.done1:
3942 // CHECK18-NEXT:    ret void
3943 //
3944 //
3945 // CHECK18-LABEL: define {{[^@]+}}@_Z5tmainIiET_v
3946 // CHECK18-SAME: () #[[ATTR2]] comdat {
3947 // CHECK18-NEXT:  entry:
3948 // CHECK18-NEXT:    [[TEST:%.*]] = alloca [[STRUCT_S_0:%.*]], align 4
3949 // CHECK18-NEXT:    [[REF_TMP:%.*]] = alloca [[STRUCT_S_0]], align 4
3950 // CHECK18-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]])
3951 // CHECK18-NEXT:    call void @_ZN1SIiEC1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
3952 // CHECK18-NEXT:    [[CALL:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]], %struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]])
3953 // CHECK18-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[REF_TMP]]) #[[ATTR3]]
3954 // CHECK18-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE5s_arr to i8*) acquire, align 8
3955 // CHECK18-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
3956 // CHECK18-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2]]
3957 // CHECK18:       init.check:
3958 // CHECK18-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
3959 // CHECK18-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
3960 // CHECK18-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
3961 // CHECK18:       init:
3962 // CHECK18-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), i32 1)
3963 // CHECK18-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 1), i32 2)
3964 // CHECK18-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor.1, i8* null, i8* @__dso_handle) #[[ATTR3]]
3965 // CHECK18-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE5s_arr) #[[ATTR3]]
3966 // CHECK18-NEXT:    br label [[INIT_END]]
3967 // CHECK18:       init.end:
3968 // CHECK18-NEXT:    [[TMP3:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ5tmainIiET_vE3var to i8*) acquire, align 8
3969 // CHECK18-NEXT:    [[GUARD_UNINITIALIZED1:%.*]] = icmp eq i8 [[TMP3]], 0
3970 // CHECK18-NEXT:    br i1 [[GUARD_UNINITIALIZED1]], label [[INIT_CHECK2:%.*]], label [[INIT_END5:%.*]], !prof [[PROF2]]
3971 // CHECK18:       init.check2:
3972 // CHECK18-NEXT:    [[TMP4:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
3973 // CHECK18-NEXT:    [[TOBOOL3:%.*]] = icmp ne i32 [[TMP4]], 0
3974 // CHECK18-NEXT:    br i1 [[TOBOOL3]], label [[INIT4:%.*]], label [[INIT_END5]]
3975 // CHECK18:       init4:
3976 // CHECK18-NEXT:    call void @_ZN1SIiEC1Ei(%struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var, i32 3)
3977 // CHECK18-NEXT:    [[TMP5:%.*]] = call i32 @__cxa_atexit(void (i8*)* bitcast (void (%struct.S.0*)* @_ZN1SIiED1Ev to void (i8*)*), i8* bitcast (%struct.S.0* @_ZZ5tmainIiET_vE3var to i8*), i8* @__dso_handle) #[[ATTR3]]
3978 // CHECK18-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ5tmainIiET_vE3var) #[[ATTR3]]
3979 // CHECK18-NEXT:    br label [[INIT_END5]]
3980 // CHECK18:       init.end5:
3981 // CHECK18-NEXT:    [[TMP6:%.*]] = load i32, i32* @_ZZ5tmainIiET_vE5t_var, align 128
3982 // CHECK18-NEXT:    store i32 [[TMP6]], i32* getelementptr inbounds ([2 x i32], [2 x i32]* @_ZZ5tmainIiET_vE3vec, i64 0, i64 0), align 128
3983 // CHECK18-NEXT:    [[CALL6:%.*]] = call nonnull align 4 dereferenceable(4) %struct.S.0* @_ZN1SIiEaSERKS0_(%struct.S.0* nonnull align 4 dereferenceable(4) getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i64 0, i64 0), %struct.S.0* nonnull align 4 dereferenceable(4) @_ZZ5tmainIiET_vE3var)
3984 // CHECK18-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[TEST]]) #[[ATTR3]]
3985 // CHECK18-NEXT:    ret i32 0
3986 //
3987 //
3988 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ev
3989 // CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
3990 // CHECK18-NEXT:  entry:
3991 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
3992 // CHECK18-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
3993 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
3994 // CHECK18-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
3995 // CHECK18-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
3996 // CHECK18-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP0]] to float
3997 // CHECK18-NEXT:    store float [[CONV]], float* [[F]], align 4
3998 // CHECK18-NEXT:    ret void
3999 //
4000 //
4001 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfED2Ev
4002 // CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4003 // CHECK18-NEXT:  entry:
4004 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4005 // CHECK18-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4006 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4007 // CHECK18-NEXT:    ret void
4008 //
4009 //
4010 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIfEC2Ef
4011 // CHECK18-SAME: (%struct.S* nonnull align 4 dereferenceable(4) [[THIS:%.*]], float [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4012 // CHECK18-NEXT:  entry:
4013 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S*, align 8
4014 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
4015 // CHECK18-NEXT:    store %struct.S* [[THIS]], %struct.S** [[THIS_ADDR]], align 8
4016 // CHECK18-NEXT:    store float [[A]], float* [[A_ADDR]], align 4
4017 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S*, %struct.S** [[THIS_ADDR]], align 8
4018 // CHECK18-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S:%.*]], %struct.S* [[THIS1]], i32 0, i32 0
4019 // CHECK18-NEXT:    [[TMP0:%.*]] = load float, float* [[A_ADDR]], align 4
4020 // CHECK18-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
4021 // CHECK18-NEXT:    [[CONV:%.*]] = sitofp i32 [[TMP1]] to float
4022 // CHECK18-NEXT:    [[ADD:%.*]] = fadd float [[TMP0]], [[CONV]]
4023 // CHECK18-NEXT:    store float [[ADD]], float* [[F]], align 4
4024 // CHECK18-NEXT:    ret void
4025 //
4026 //
4027 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ev
4028 // CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4029 // CHECK18-NEXT:  entry:
4030 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4031 // CHECK18-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4032 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4033 // CHECK18-NEXT:    call void @_ZN1SIiEC2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]])
4034 // CHECK18-NEXT:    ret void
4035 //
4036 //
4037 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEaSERKS0_
4038 // CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], %struct.S.0* nonnull align 4 dereferenceable(4) [[TMP0:%.*]]) #[[ATTR2]] comdat align 2 {
4039 // CHECK18-NEXT:  entry:
4040 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4041 // CHECK18-NEXT:    [[DOTADDR:%.*]] = alloca %struct.S.0*, align 8
4042 // CHECK18-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4043 // CHECK18-NEXT:    store %struct.S.0* [[TMP0]], %struct.S.0** [[DOTADDR]], align 8
4044 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4045 // CHECK18-NEXT:    ret %struct.S.0* [[THIS1]]
4046 //
4047 //
4048 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED1Ev
4049 // CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4050 // CHECK18-NEXT:  entry:
4051 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4052 // CHECK18-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4053 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4054 // CHECK18-NEXT:    call void @_ZN1SIiED2Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]]) #[[ATTR3]]
4055 // CHECK18-NEXT:    ret void
4056 //
4057 //
4058 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC1Ei
4059 // CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4060 // CHECK18-NEXT:  entry:
4061 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4062 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4063 // CHECK18-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4064 // CHECK18-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4065 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4066 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4067 // CHECK18-NEXT:    call void @_ZN1SIiEC2Ei(%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS1]], i32 [[TMP0]])
4068 // CHECK18-NEXT:    ret void
4069 //
4070 //
4071 // CHECK18-LABEL: define {{[^@]+}}@__cxx_global_array_dtor.1
4072 // CHECK18-SAME: (i8* [[TMP0:%.*]]) #[[ATTR4]] section ".text.startup" {
4073 // CHECK18-NEXT:  entry:
4074 // CHECK18-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
4075 // CHECK18-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4076 // CHECK18-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
4077 // CHECK18:       arraydestroy.body:
4078 // CHECK18-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.S.0* [ getelementptr inbounds ([[STRUCT_S_0:%.*]], %struct.S.0* getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4079 // CHECK18-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_S_0]], %struct.S.0* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4080 // CHECK18-NEXT:    call void @_ZN1SIiED1Ev(%struct.S.0* nonnull align 4 dereferenceable(4) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR3]]
4081 // CHECK18-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.S.0* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.S.0], [2 x %struct.S.0]* @_ZZ5tmainIiET_vE5s_arr, i32 0, i32 0)
4082 // CHECK18-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4083 // CHECK18:       arraydestroy.done1:
4084 // CHECK18-NEXT:    ret void
4085 //
4086 //
4087 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ev
4088 // CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4089 // CHECK18-NEXT:  entry:
4090 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4091 // CHECK18-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4092 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4093 // CHECK18-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4094 // CHECK18-NEXT:    [[TMP0:%.*]] = load volatile i32, i32* @g, align 128
4095 // CHECK18-NEXT:    store i32 [[TMP0]], i32* [[F]], align 4
4096 // CHECK18-NEXT:    ret void
4097 //
4098 //
4099 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiED2Ev
4100 // CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4101 // CHECK18-NEXT:  entry:
4102 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4103 // CHECK18-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4104 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4105 // CHECK18-NEXT:    ret void
4106 //
4107 //
4108 // CHECK18-LABEL: define {{[^@]+}}@_ZN1SIiEC2Ei
4109 // CHECK18-SAME: (%struct.S.0* nonnull align 4 dereferenceable(4) [[THIS:%.*]], i32 [[A:%.*]]) unnamed_addr #[[ATTR1]] comdat align 2 {
4110 // CHECK18-NEXT:  entry:
4111 // CHECK18-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.S.0*, align 8
4112 // CHECK18-NEXT:    [[A_ADDR:%.*]] = alloca i32, align 4
4113 // CHECK18-NEXT:    store %struct.S.0* [[THIS]], %struct.S.0** [[THIS_ADDR]], align 8
4114 // CHECK18-NEXT:    store i32 [[A]], i32* [[A_ADDR]], align 4
4115 // CHECK18-NEXT:    [[THIS1:%.*]] = load %struct.S.0*, %struct.S.0** [[THIS_ADDR]], align 8
4116 // CHECK18-NEXT:    [[F:%.*]] = getelementptr inbounds [[STRUCT_S_0:%.*]], %struct.S.0* [[THIS1]], i32 0, i32 0
4117 // CHECK18-NEXT:    [[TMP0:%.*]] = load i32, i32* [[A_ADDR]], align 4
4118 // CHECK18-NEXT:    [[TMP1:%.*]] = load volatile i32, i32* @g, align 128
4119 // CHECK18-NEXT:    [[ADD:%.*]] = add nsw i32 [[TMP0]], [[TMP1]]
4120 // CHECK18-NEXT:    store i32 [[ADD]], i32* [[F]], align 4
4121 // CHECK18-NEXT:    ret void
4122 //
4123 //
4124 // CHECK19-LABEL: define {{[^@]+}}@main
4125 // CHECK19-SAME: () #[[ATTR0:[0-9]+]] {
4126 // CHECK19-NEXT:  entry:
4127 // CHECK19-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
4128 // CHECK19-NEXT:    [[REF_TMP:%.*]] = alloca [[CLASS_ANON:%.*]], align 1
4129 // CHECK19-NEXT:    store i32 0, i32* [[RETVAL]], align 4
4130 // CHECK19-NEXT:    call void @"_ZZ4mainENK3$_0clEv"(%class.anon* nonnull align 1 dereferenceable(1) [[REF_TMP]])
4131 // CHECK19-NEXT:    ret i32 0
4132 //
4133 //
4134 // CHECK20-LABEL: define {{[^@]+}}@main
4135 // CHECK20-SAME: () #[[ATTR1:[0-9]+]] {
4136 // CHECK20-NEXT:  entry:
4137 // CHECK20-NEXT:    [[RETVAL:%.*]] = alloca i32, align 4
4138 // CHECK20-NEXT:    store i32 0, i32* [[RETVAL]], align 4
4139 // CHECK20-NEXT:    [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to %struct.__block_literal_generic*), i32 0, i32 3), align 8
4140 // CHECK20-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
4141 // CHECK20-NEXT:    call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global to i8*))
4142 // CHECK20-NEXT:    ret i32 0
4143 //
4144 //
4145 // CHECK20-LABEL: define {{[^@]+}}@__main_block_invoke
4146 // CHECK20-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2:[0-9]+]] {
4147 // CHECK20-NEXT:  entry:
4148 // CHECK20-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
4149 // CHECK20-NEXT:    [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
4150 // CHECK20-NEXT:    store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
4151 // CHECK20-NEXT:    [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
4152 // CHECK20-NEXT:    store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
4153 // CHECK20-NEXT:    store volatile i32 1, i32* @g, align 128
4154 // CHECK20-NEXT:    [[TMP0:%.*]] = load i8*, i8** getelementptr inbounds ([[STRUCT___BLOCK_LITERAL_GENERIC:%.*]], %struct.__block_literal_generic* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to %struct.__block_literal_generic*), i32 0, i32 3), align 8
4155 // CHECK20-NEXT:    [[TMP1:%.*]] = bitcast i8* [[TMP0]] to void (i8*)*
4156 // CHECK20-NEXT:    call void [[TMP1]](i8* bitcast ({ i8**, i32, i32, i8*, %struct.__block_descriptor* }* @__block_literal_global.2 to i8*))
4157 // CHECK20-NEXT:    ret void
4158 //
4159 //
4160 // CHECK20-LABEL: define {{[^@]+}}@__main_block_invoke_2
4161 // CHECK20-SAME: (i8* [[DOTBLOCK_DESCRIPTOR:%.*]]) #[[ATTR2]] {
4162 // CHECK20-NEXT:  entry:
4163 // CHECK20-NEXT:    [[DOTBLOCK_DESCRIPTOR_ADDR:%.*]] = alloca i8*, align 8
4164 // CHECK20-NEXT:    [[BLOCK_ADDR:%.*]] = alloca <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*, align 8
4165 // CHECK20-NEXT:    store i8* [[DOTBLOCK_DESCRIPTOR]], i8** [[DOTBLOCK_DESCRIPTOR_ADDR]], align 8
4166 // CHECK20-NEXT:    [[BLOCK:%.*]] = bitcast i8* [[DOTBLOCK_DESCRIPTOR]] to <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>*
4167 // CHECK20-NEXT:    store <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>* [[BLOCK]], <{ i8*, i32, i32, i8*, %struct.__block_descriptor* }>** [[BLOCK_ADDR]], align 8
4168 // CHECK20-NEXT:    store volatile i32 2, i32* @g, align 128
4169 // CHECK20-NEXT:    ret void
4170 //
4171 //
4172 // CHECK21-LABEL: define {{[^@]+}}@_Z10array_funcv
4173 // CHECK21-SAME: () #[[ATTR0:[0-9]+]] {
4174 // CHECK21-NEXT:  entry:
4175 // CHECK21-NEXT:    [[TMP0:%.*]] = load atomic i8, i8* bitcast (i64* @_ZGVZ10array_funcvE1s to i8*) acquire, align 8
4176 // CHECK21-NEXT:    [[GUARD_UNINITIALIZED:%.*]] = icmp eq i8 [[TMP0]], 0
4177 // CHECK21-NEXT:    br i1 [[GUARD_UNINITIALIZED]], label [[INIT_CHECK:%.*]], label [[INIT_END:%.*]], !prof [[PROF2:![0-9]+]]
4178 // CHECK21:       init.check:
4179 // CHECK21-NEXT:    [[TMP1:%.*]] = call i32 @__cxa_guard_acquire(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1:[0-9]+]]
4180 // CHECK21-NEXT:    [[TOBOOL:%.*]] = icmp ne i32 [[TMP1]], 0
4181 // CHECK21-NEXT:    br i1 [[TOBOOL]], label [[INIT:%.*]], label [[INIT_END]]
4182 // CHECK21:       init:
4183 // CHECK21-NEXT:    br label [[ARRAYCTOR_LOOP:%.*]]
4184 // CHECK21:       arrayctor.loop:
4185 // CHECK21-NEXT:    [[ARRAYCTOR_CUR:%.*]] = phi %struct.St* [ getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), [[INIT]] ], [ [[ARRAYCTOR_NEXT:%.*]], [[ARRAYCTOR_LOOP]] ]
4186 // CHECK21-NEXT:    call void @_ZN2StC1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYCTOR_CUR]])
4187 // CHECK21-NEXT:    [[ARRAYCTOR_NEXT]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[ARRAYCTOR_CUR]], i64 1
4188 // CHECK21-NEXT:    [[ARRAYCTOR_DONE:%.*]] = icmp eq %struct.St* [[ARRAYCTOR_NEXT]], getelementptr inbounds ([[STRUCT_ST]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2)
4189 // CHECK21-NEXT:    br i1 [[ARRAYCTOR_DONE]], label [[ARRAYCTOR_CONT:%.*]], label [[ARRAYCTOR_LOOP]]
4190 // CHECK21:       arrayctor.cont:
4191 // CHECK21-NEXT:    [[TMP2:%.*]] = call i32 @__cxa_atexit(void (i8*)* @__cxx_global_array_dtor, i8* null, i8* @__dso_handle) #[[ATTR1]]
4192 // CHECK21-NEXT:    call void @__cxa_guard_release(i64* @_ZGVZ10array_funcvE1s) #[[ATTR1]]
4193 // CHECK21-NEXT:    br label [[INIT_END]]
4194 // CHECK21:       init.end:
4195 // CHECK21-NEXT:    ret void
4196 //
4197 //
4198 // CHECK21-LABEL: define {{[^@]+}}@_ZN2StC1Ev
4199 // CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2:[0-9]+]] comdat align 2 {
4200 // CHECK21-NEXT:  entry:
4201 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
4202 // CHECK21-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
4203 // CHECK21-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
4204 // CHECK21-NEXT:    call void @_ZN2StC2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]])
4205 // CHECK21-NEXT:    ret void
4206 //
4207 //
4208 // CHECK21-LABEL: define {{[^@]+}}@__cxx_global_array_dtor
4209 // CHECK21-SAME: (i8* [[TMP0:%.*]]) #[[ATTR3:[0-9]+]] section ".text.startup" {
4210 // CHECK21-NEXT:  entry:
4211 // CHECK21-NEXT:    [[DOTADDR:%.*]] = alloca i8*, align 8
4212 // CHECK21-NEXT:    store i8* [[TMP0]], i8** [[DOTADDR]], align 8
4213 // CHECK21-NEXT:    br label [[ARRAYDESTROY_BODY:%.*]]
4214 // CHECK21:       arraydestroy.body:
4215 // CHECK21-NEXT:    [[ARRAYDESTROY_ELEMENTPAST:%.*]] = phi %struct.St* [ getelementptr inbounds ([[STRUCT_ST:%.*]], %struct.St* getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0), i64 2), [[ENTRY:%.*]] ], [ [[ARRAYDESTROY_ELEMENT:%.*]], [[ARRAYDESTROY_BODY]] ]
4216 // CHECK21-NEXT:    [[ARRAYDESTROY_ELEMENT]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[ARRAYDESTROY_ELEMENTPAST]], i64 -1
4217 // CHECK21-NEXT:    call void @_ZN2StD1Ev(%struct.St* nonnull align 4 dereferenceable(8) [[ARRAYDESTROY_ELEMENT]]) #[[ATTR1]]
4218 // CHECK21-NEXT:    [[ARRAYDESTROY_DONE:%.*]] = icmp eq %struct.St* [[ARRAYDESTROY_ELEMENT]], getelementptr inbounds ([2 x %struct.St], [2 x %struct.St]* @_ZZ10array_funcvE1s, i32 0, i32 0)
4219 // CHECK21-NEXT:    br i1 [[ARRAYDESTROY_DONE]], label [[ARRAYDESTROY_DONE1:%.*]], label [[ARRAYDESTROY_BODY]]
4220 // CHECK21:       arraydestroy.done1:
4221 // CHECK21-NEXT:    ret void
4222 //
4223 //
4224 // CHECK21-LABEL: define {{[^@]+}}@_ZN2StD1Ev
4225 // CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4226 // CHECK21-NEXT:  entry:
4227 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
4228 // CHECK21-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
4229 // CHECK21-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
4230 // CHECK21-NEXT:    call void @_ZN2StD2Ev(%struct.St* nonnull align 4 dereferenceable(8) [[THIS1]]) #[[ATTR1]]
4231 // CHECK21-NEXT:    ret void
4232 //
4233 //
4234 // CHECK21-LABEL: define {{[^@]+}}@_ZN2StC2Ev
4235 // CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4236 // CHECK21-NEXT:  entry:
4237 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
4238 // CHECK21-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
4239 // CHECK21-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
4240 // CHECK21-NEXT:    [[A:%.*]] = getelementptr inbounds [[STRUCT_ST:%.*]], %struct.St* [[THIS1]], i32 0, i32 0
4241 // CHECK21-NEXT:    store i32 0, i32* [[A]], align 4
4242 // CHECK21-NEXT:    [[B:%.*]] = getelementptr inbounds [[STRUCT_ST]], %struct.St* [[THIS1]], i32 0, i32 1
4243 // CHECK21-NEXT:    store i32 0, i32* [[B]], align 4
4244 // CHECK21-NEXT:    ret void
4245 //
4246 //
4247 // CHECK21-LABEL: define {{[^@]+}}@_ZN2StD2Ev
4248 // CHECK21-SAME: (%struct.St* nonnull align 4 dereferenceable(8) [[THIS:%.*]]) unnamed_addr #[[ATTR2]] comdat align 2 {
4249 // CHECK21-NEXT:  entry:
4250 // CHECK21-NEXT:    [[THIS_ADDR:%.*]] = alloca %struct.St*, align 8
4251 // CHECK21-NEXT:    store %struct.St* [[THIS]], %struct.St** [[THIS_ADDR]], align 8
4252 // CHECK21-NEXT:    [[THIS1:%.*]] = load %struct.St*, %struct.St** [[THIS_ADDR]], align 8
4253 // CHECK21-NEXT:    ret void
4254 //
4255